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wifi: mt76: mt7996: rework DMA configuration for mt7990
Modify DMA ring setting for mt7990. This is a preliminary patch to support mt7990 chipset. Co-developed-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com> Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com> Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com> Signed-off-by: Shayne Chen <shayne.chen@mediatek.com> Link: https://patch.msgid.link/20250409140750.724437-5-shayne.chen@mediatek.com Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Peter Chiu
Felix Fietkau
parent
76d13deb1a
commit
9ba4a76db9
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@ -55,20 +55,32 @@ static void mt7996_dma_config(struct mt7996_dev *dev)
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/* rx queue */
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RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, MT7996_RXQ_MCU_WM);
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/* for mt7990, RX ring 1 is for SDO instead */
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RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7996_RXQ_MCU_WA);
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/* mt7996: band0 and band1, mt7992: band0 */
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RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0, MT7996_RXQ_BAND0);
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RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN, MT7996_RXQ_MCU_WA_MAIN);
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if (mt7996_has_wa(dev))
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RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN,
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MT7996_RXQ_MCU_WA_MAIN);
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if (is_mt7996(&dev->mt76)) {
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/* mt7996 band2 */
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RXQ_CONFIG(MT_RXQ_BAND2, WFDMA0, MT_INT_RX_DONE_BAND2, MT7996_RXQ_BAND2);
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RXQ_CONFIG(MT_RXQ_BAND2_WA, WFDMA0, MT_INT_RX_DONE_WA_TRI, MT7996_RXQ_MCU_WA_TRI);
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} else {
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/* mt7992 band1 */
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RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1, MT7996_RXQ_BAND1);
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switch (mt76_chip(&dev->mt76)) {
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case MT7992_DEVICE_ID:
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RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA0, MT_INT_RX_DONE_WA_EXT, MT7996_RXQ_MCU_WA_EXT);
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RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1, MT7996_RXQ_BAND1);
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break;
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case MT7990_DEVICE_ID:
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RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1, MT7996_RXQ_BAND1);
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RXQ_CONFIG(MT_RXQ_TXFREE_BAND0, WFDMA0,
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MT_INT_RX_TXFREE_BAND0_MT7990, MT7990_RXQ_TXFREE0);
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if (dev->hif2)
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RXQ_CONFIG(MT_RXQ_TXFREE_BAND1, WFDMA0,
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MT_INT_RX_TXFREE_BAND1_MT7990, MT7990_RXQ_TXFREE1);
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break;
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case MT7996_DEVICE_ID:
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default:
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/* mt7996 band2 */
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RXQ_CONFIG(MT_RXQ_BAND2_WA, WFDMA0, MT_INT_RX_DONE_WA_TRI, MT7996_RXQ_MCU_WA_TRI);
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RXQ_CONFIG(MT_RXQ_BAND2, WFDMA0, MT_INT_RX_DONE_BAND2, MT7996_RXQ_BAND2);
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break;
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}
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if (dev->has_rro) {
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@ -104,9 +116,11 @@ static void mt7996_dma_config(struct mt7996_dev *dev)
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}
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/* mcu tx queue */
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MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, MT7996_TXQ_MCU_WM);
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MCUQ_CONFIG(MT_MCUQ_WA, WFDMA0, MT_INT_TX_DONE_MCU_WA, MT7996_TXQ_MCU_WA);
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MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, MT7996_TXQ_FWDL);
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MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, MT7996_TXQ_MCU_WM);
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if (mt7996_has_wa(dev))
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MCUQ_CONFIG(MT_MCUQ_WA, WFDMA0, MT_INT_TX_DONE_MCU_WA,
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MT7996_TXQ_MCU_WA);
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}
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static u32 __mt7996_dma_prefetch_base(u16 *base, u8 depth)
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@ -121,43 +135,62 @@ static u32 __mt7996_dma_prefetch_base(u16 *base, u8 depth)
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static void __mt7996_dma_prefetch(struct mt7996_dev *dev, u32 ofs)
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{
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u16 base = 0;
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u8 queue;
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u8 queue, val;
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#define PREFETCH(_depth) (__mt7996_dma_prefetch_base(&base, (_depth)))
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/* prefetch SRAM wrapping boundary for tx/rx ring. */
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mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x2));
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mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x2));
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/* Tx Command Rings */
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val = is_mt7996(&dev->mt76) ? 2 : 4;
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mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(val));
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mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(val));
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if (mt7996_has_wa(dev))
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mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(val));
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/* Tx Data Rings */
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mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x8));
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mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0x8));
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mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0x2));
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mt76_wr(dev, MT_TXQ_EXT_CTRL(2) + ofs, PREFETCH(0x8));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x2));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x2));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x2));
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if (!is_mt7996(&dev->mt76) || dev->hif2)
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mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0x8));
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if (is_mt7996(&dev->mt76))
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mt76_wr(dev, MT_TXQ_EXT_CTRL(2) + ofs, PREFETCH(0x8));
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queue = is_mt7996(&dev->mt76) ? MT_RXQ_BAND2_WA : MT_RXQ_BAND1_WA;
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(queue) + ofs, PREFETCH(0x2));
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/* Rx Event Rings */
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mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(val));
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mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(val));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x10));
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/* Rx TxFreeDone From WA Rings */
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if (mt7996_has_wa(dev)) {
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mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(val));
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queue = is_mt7996(&dev->mt76) ? MT_RXQ_BAND2_WA : MT_RXQ_BAND1_WA;
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mt76_wr(dev, MT_RXQ_EXT_CTRL(queue) + ofs, PREFETCH(val));
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}
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/* Rx TxFreeDone From MAC Rings */
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val = is_mt7996(&dev->mt76) ? 4 : 8;
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if (is_mt7990(&dev->mt76) || (is_mt7996(&dev->mt76) && dev->has_rro))
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mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_TXFREE_BAND0) + ofs, PREFETCH(val));
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if (is_mt7990(&dev->mt76) && dev->hif2)
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mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_TXFREE_BAND1) + ofs, PREFETCH(val));
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else if (is_mt7996(&dev->mt76) && dev->has_rro)
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mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_TXFREE_BAND2) + ofs, PREFETCH(val));
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/* Rx Data Rings */
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mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x10));
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queue = is_mt7996(&dev->mt76) ? MT_RXQ_BAND2 : MT_RXQ_BAND1;
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(queue) + ofs, PREFETCH(0x10));
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mt76_wr(dev, MT_RXQ_EXT_CTRL(queue) + ofs, PREFETCH(0x10));
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/* Rx RRO Rings */
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if (dev->has_rro) {
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_RRO_BAND0) + ofs,
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PREFETCH(0x10));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_RRO_BAND2) + ofs,
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PREFETCH(0x10));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MSDU_PAGE_BAND0) + ofs,
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PREFETCH(0x4));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MSDU_PAGE_BAND1) + ofs,
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PREFETCH(0x4));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MSDU_PAGE_BAND2) + ofs,
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PREFETCH(0x4));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_TXFREE_BAND0) + ofs,
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PREFETCH(0x4));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_TXFREE_BAND2) + ofs,
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PREFETCH(0x4));
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mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_RRO_BAND0) + ofs, PREFETCH(0x10));
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queue = is_mt7996(&dev->mt76) ? MT_RXQ_RRO_BAND2 : MT_RXQ_RRO_BAND1;
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mt76_wr(dev, MT_RXQ_EXT_CTRL(queue) + ofs, PREFETCH(0x10));
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mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MSDU_PAGE_BAND0) + ofs, PREFETCH(val));
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if (is_mt7996(&dev->mt76)) {
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mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MSDU_PAGE_BAND1) + ofs,
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PREFETCH(val));
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mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MSDU_PAGE_BAND2) + ofs,
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PREFETCH(val));
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}
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}
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#undef PREFETCH
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@ -269,6 +302,9 @@ void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset)
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mtk_wed_device_start(wed, wed_irq_mask);
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}
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if (!mt7996_has_wa(dev))
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irq_mask &= ~(MT_INT_RX(MT_RXQ_MAIN_WA) |
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MT_INT_RX(MT_RXQ_BAND1_WA));
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irq_mask = reset ? MT_INT_MCU_CMD : irq_mask;
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mt7996_irq_enable(dev, irq_mask);
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@ -474,12 +510,14 @@ int mt7996_dma_init(struct mt7996_dev *dev)
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return ret;
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/* command to WA */
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ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA,
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MT_MCUQ_ID(MT_MCUQ_WA),
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MT7996_TX_MCU_RING_SIZE,
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MT_MCUQ_RING_BASE(MT_MCUQ_WA));
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if (ret)
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return ret;
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if (mt7996_has_wa(dev)) {
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ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA,
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MT_MCUQ_ID(MT_MCUQ_WA),
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MT7996_TX_MCU_RING_SIZE,
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MT_MCUQ_RING_BASE(MT_MCUQ_WA));
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if (ret)
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return ret;
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}
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/* firmware download */
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ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL,
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@ -498,7 +536,7 @@ int mt7996_dma_init(struct mt7996_dev *dev)
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if (ret)
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return ret;
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/* event from WA */
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/* event from WA, or SDO event for mt7990 */
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
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MT_RXQ_ID(MT_RXQ_MCU_WA),
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MT7996_RX_MCU_RING_SIZE_WA,
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@ -527,13 +565,41 @@ int mt7996_dma_init(struct mt7996_dev *dev)
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dev->mt76.q_rx[MT_RXQ_MAIN_WA].wed = wed;
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}
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA],
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MT_RXQ_ID(MT_RXQ_MAIN_WA),
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MT7996_RX_MCU_RING_SIZE,
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MT_RX_BUF_SIZE,
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MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA));
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if (ret)
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return ret;
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if (mt7996_has_wa(dev)) {
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA],
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MT_RXQ_ID(MT_RXQ_MAIN_WA),
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MT7996_RX_MCU_RING_SIZE,
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MT_RX_BUF_SIZE,
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MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA));
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if (ret)
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return ret;
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} else {
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if (mtk_wed_device_active(wed)) {
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dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0].flags = MT_WED_Q_TXFREE;
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dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0].wed = wed;
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}
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0],
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MT_RXQ_ID(MT_RXQ_TXFREE_BAND0),
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MT7996_RX_MCU_RING_SIZE,
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MT7996_RX_BUF_SIZE,
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MT_RXQ_RING_BASE(MT_RXQ_TXFREE_BAND0));
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if (ret)
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return ret;
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}
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if (!mt7996_has_wa(dev) && dev->hif2) {
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if (mtk_wed_device_active(wed)) {
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dev->mt76.q_rx[MT_RXQ_TXFREE_BAND1].flags = MT_WED_Q_TXFREE;
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dev->mt76.q_rx[MT_RXQ_TXFREE_BAND1].wed = wed;
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}
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_TXFREE_BAND1],
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MT_RXQ_ID(MT_RXQ_TXFREE_BAND1),
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MT7996_RX_MCU_RING_SIZE,
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MT7996_RX_BUF_SIZE,
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MT_RXQ_RING_BASE(MT_RXQ_TXFREE_BAND1));
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if (ret)
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return ret;
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}
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if (mt7996_band_valid(dev, MT_BAND2)) {
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/* rx data queue for mt7996 band2 */
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@ -573,14 +639,16 @@ int mt7996_dma_init(struct mt7996_dev *dev)
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return ret;
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/* tx free notify event from WA for mt7992 band1 */
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rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1_WA) + hif1_ofs;
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1_WA],
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MT_RXQ_ID(MT_RXQ_BAND1_WA),
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MT7996_RX_MCU_RING_SIZE,
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MT_RX_BUF_SIZE,
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rx_base);
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if (ret)
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return ret;
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if (mt7996_has_wa(dev)) {
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rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1_WA) + hif1_ofs;
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1_WA],
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MT_RXQ_ID(MT_RXQ_BAND1_WA),
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MT7996_RX_MCU_RING_SIZE,
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MT_RX_BUF_SIZE,
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rx_base);
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if (ret)
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return ret;
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}
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}
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if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed) &&
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@ -177,6 +177,8 @@ enum mt7996_rxq_id {
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MT7996_RXQ_TXFREE1 = 9,
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MT7996_RXQ_TXFREE2 = 7,
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MT7996_RXQ_RRO_IND = 0,
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MT7990_RXQ_TXFREE0 = 6,
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MT7990_RXQ_TXFREE1 = 7,
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};
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struct mt7996_twt_flow {
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@ -483,7 +483,7 @@ enum offs_rev {
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#define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \
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MT_MCUQ_ID(q) * 0x4)
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#define MT_RXQ_BAND1_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \
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#define MT_RXQ_EXT_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \
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MT_RXQ_ID(q) * 0x4)
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#define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
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MT_TXQ_ID(q) * 0x4)
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@ -504,6 +504,8 @@ enum offs_rev {
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#define MT_INT_RX_DONE_WA_TRI BIT(3)
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#define MT_INT_RX_TXFREE_MAIN BIT(17)
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#define MT_INT_RX_TXFREE_TRI BIT(15)
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#define MT_INT_RX_TXFREE_BAND0_MT7990 BIT(14)
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#define MT_INT_RX_TXFREE_BAND1_MT7990 BIT(15)
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#define MT_INT_RX_DONE_BAND2_EXT BIT(23)
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#define MT_INT_RX_TXFREE_EXT BIT(26)
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#define MT_INT_MCU_CMD BIT(29)
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