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drm/amdgpu: Use the correct API to read register

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Use SOC15 API so that the register offset is calculated correctly.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar 2022-01-12 19:42:56 +05:30 committed by Alex Deucher
parent f544afac3f
commit 9b4fd27601
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
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@ -1637,7 +1637,7 @@ static int gfx_v9_4_3_mqd_init(struct amdgpu_ring *ring)
/* set static priority for a queue/ring */
gfx_v9_4_3_mqd_set_priority(ring, mqd);
mqd->cp_hqd_quantum = RREG32(regCP_HQD_QUANTUM);
mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, regCP_HQD_QUANTUM);
/* map_queues packet doesn't need activate the queue,
* so only kiq need set this field.