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KVM selftests changes for 6.15, part 1
- Misc cleanups and prep work.
- Annotate _no_printf() with "printf" so that pr_debug() statements are
checked by the compiler for default builds (and pr_info() when QUIET).
- Attempt to whack the last LLC references/misses mole in the Intel PMU
counters test by adding a data load and doing CLFLUSH{OPT} on the data
instead of the code being executed. The theory is that modern Intel CPUs
have learned new code prefetching tricks that bypass the PMU counters.
- Fix a flaw in the Intel PMU counters test where it asserts that an event is
counting correctly without actually knowing what the event counts on the
underlying hardware.
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Merge tag 'kvm-x86-selftests_6.15-1' of https://github.com/kvm-x86/linux into HEAD
KVM selftests changes for 6.15, part 1
- Misc cleanups and prep work.
- Annotate _no_printf() with "printf" so that pr_debug() statements are
checked by the compiler for default builds (and pr_info() when QUIET).
- Attempt to whack the last LLC references/misses mole in the Intel PMU
counters test by adding a data load and doing CLFLUSH{OPT} on the data
instead of the code being executed. The theory is that modern Intel CPUs
have learned new code prefetching tricks that bypass the PMU counters.
- Fix a flaw in the Intel PMU counters test where it asserts that an event is
counting correctly without actually knowing what the event counts on the
underlying hardware.
This commit is contained in:
Paolo Bonzini
commit
9b47f288eb
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@ -239,7 +239,7 @@ static void vcpu_thread_main(struct memstress_vcpu_args *vcpu_args)
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case ITERATION_MARK_IDLE:
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mark_vcpu_memory_idle(vm, vcpu_args);
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break;
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};
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}
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vcpu_last_completed_iteration[vcpu_idx] = current_iteration;
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}
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@ -22,7 +22,7 @@
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#define msecs_to_usecs(msec) ((msec) * 1000ULL)
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static inline int _no_printf(const char *format, ...) { return 0; }
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static inline __printf(1, 2) int _no_printf(const char *format, ...) { return 0; }
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#ifdef DEBUG
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#define pr_debug(...) printf(__VA_ARGS__)
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@ -183,6 +183,9 @@ struct kvm_x86_cpu_feature {
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* Extended Leafs, a.k.a. AMD defined
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*/
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#define X86_FEATURE_SVM KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 2)
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#define X86_FEATURE_PERFCTR_CORE KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 23)
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#define X86_FEATURE_PERFCTR_NB KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 24)
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#define X86_FEATURE_PERFCTR_LLC KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 28)
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#define X86_FEATURE_NX KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 20)
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#define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26)
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#define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27)
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@ -199,6 +202,8 @@ struct kvm_x86_cpu_feature {
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#define X86_FEATURE_VGIF KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16)
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#define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1)
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#define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3)
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#define X86_FEATURE_PERFMON_V2 KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 0)
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#define X86_FEATURE_LBR_PMC_FREEZE KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 2)
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/*
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* KVM defined paravirt features.
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@ -285,6 +290,8 @@ struct kvm_x86_cpu_property {
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#define X86_PROPERTY_GUEST_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 16, 23)
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#define X86_PROPERTY_SEV_C_BIT KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5)
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#define X86_PROPERTY_PHYS_ADDR_REDUCTION KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11)
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#define X86_PROPERTY_NR_PERFCTR_CORE KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 0, 3)
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#define X86_PROPERTY_NR_PERFCTR_NB KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 10, 15)
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#define X86_PROPERTY_MAX_CENTAUR_LEAF KVM_X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31)
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@ -1339,6 +1346,46 @@ static inline void kvm_hypercall_map_gpa_range(uint64_t gpa, uint64_t size,
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GUEST_ASSERT(!ret);
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}
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/*
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* Execute HLT in an STI interrupt shadow to ensure that a pending IRQ that's
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* intended to be a wake event arrives *after* HLT is executed. Modern CPUs,
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* except for a few oddballs that KVM is unlikely to run on, block IRQs for one
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* instruction after STI, *if* RFLAGS.IF=0 before STI. Note, Intel CPUs may
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* block other events beyond regular IRQs, e.g. may block NMIs and SMIs too.
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*/
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static inline void safe_halt(void)
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{
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asm volatile("sti; hlt");
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}
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/*
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* Enable interrupts and ensure that interrupts are evaluated upon return from
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* this function, i.e. execute a nop to consume the STi interrupt shadow.
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*/
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static inline void sti_nop(void)
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{
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asm volatile ("sti; nop");
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}
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/*
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* Enable interrupts for one instruction (nop), to allow the CPU to process all
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* interrupts that are already pending.
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*/
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static inline void sti_nop_cli(void)
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{
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asm volatile ("sti; nop; cli");
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}
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static inline void sti(void)
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{
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asm volatile("sti");
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}
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static inline void cli(void)
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{
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asm volatile ("cli");
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}
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void __vm_xsave_require_permission(uint64_t xfeature, const char *name);
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#define vm_xsave_require_permission(xfeature) \
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|
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@ -63,8 +63,10 @@ static void receiver_code(void *hcall_page, vm_vaddr_t pgs_gpa)
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/* Signal sender vCPU we're ready */
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ipis_rcvd[vcpu_id] = (u64)-1;
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for (;;)
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asm volatile("sti; hlt; cli");
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for (;;) {
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safe_halt();
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cli();
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}
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}
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static void guest_ipi_handler(struct ex_regs *regs)
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|
|
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|
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@ -17,7 +17,7 @@
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* Number of instructions in each loop. 1 CLFLUSH/CLFLUSHOPT/NOP, 1 MFENCE,
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* 1 LOOP.
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*/
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#define NUM_INSNS_PER_LOOP 3
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#define NUM_INSNS_PER_LOOP 4
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/*
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* Number of "extra" instructions that will be counted, i.e. the number of
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@ -29,10 +29,59 @@
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/* Total number of instructions retired within the measured section. */
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#define NUM_INSNS_RETIRED (NUM_LOOPS * NUM_INSNS_PER_LOOP + NUM_EXTRA_INSNS)
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/* Track which architectural events are supported by hardware. */
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static uint32_t hardware_pmu_arch_events;
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static uint8_t kvm_pmu_version;
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static bool kvm_has_perf_caps;
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#define X86_PMU_FEATURE_NULL \
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({ \
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struct kvm_x86_pmu_feature feature = {}; \
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\
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feature; \
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})
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static bool pmu_is_null_feature(struct kvm_x86_pmu_feature event)
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{
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return !(*(u64 *)&event);
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}
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struct kvm_intel_pmu_event {
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struct kvm_x86_pmu_feature gp_event;
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struct kvm_x86_pmu_feature fixed_event;
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};
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/*
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* Wrap the array to appease the compiler, as the macros used to construct each
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* kvm_x86_pmu_feature use syntax that's only valid in function scope, and the
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* compiler often thinks the feature definitions aren't compile-time constants.
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*/
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static struct kvm_intel_pmu_event intel_event_to_feature(uint8_t idx)
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{
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const struct kvm_intel_pmu_event __intel_event_to_feature[] = {
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[INTEL_ARCH_CPU_CYCLES_INDEX] = { X86_PMU_FEATURE_CPU_CYCLES, X86_PMU_FEATURE_CPU_CYCLES_FIXED },
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[INTEL_ARCH_INSTRUCTIONS_RETIRED_INDEX] = { X86_PMU_FEATURE_INSNS_RETIRED, X86_PMU_FEATURE_INSNS_RETIRED_FIXED },
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/*
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* Note, the fixed counter for reference cycles is NOT the same as the
|
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* general purpose architectural event. The fixed counter explicitly
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* counts at the same frequency as the TSC, whereas the GP event counts
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* at a fixed, but uarch specific, frequency. Bundle them here for
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* simplicity.
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*/
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[INTEL_ARCH_REFERENCE_CYCLES_INDEX] = { X86_PMU_FEATURE_REFERENCE_CYCLES, X86_PMU_FEATURE_REFERENCE_TSC_CYCLES_FIXED },
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[INTEL_ARCH_LLC_REFERENCES_INDEX] = { X86_PMU_FEATURE_LLC_REFERENCES, X86_PMU_FEATURE_NULL },
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[INTEL_ARCH_LLC_MISSES_INDEX] = { X86_PMU_FEATURE_LLC_MISSES, X86_PMU_FEATURE_NULL },
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[INTEL_ARCH_BRANCHES_RETIRED_INDEX] = { X86_PMU_FEATURE_BRANCH_INSNS_RETIRED, X86_PMU_FEATURE_NULL },
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[INTEL_ARCH_BRANCHES_MISPREDICTED_INDEX] = { X86_PMU_FEATURE_BRANCHES_MISPREDICTED, X86_PMU_FEATURE_NULL },
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[INTEL_ARCH_TOPDOWN_SLOTS_INDEX] = { X86_PMU_FEATURE_TOPDOWN_SLOTS, X86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED },
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};
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kvm_static_assert(ARRAY_SIZE(__intel_event_to_feature) == NR_INTEL_ARCH_EVENTS);
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return __intel_event_to_feature[idx];
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}
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|
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static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct kvm_vcpu **vcpu,
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void *guest_code,
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uint8_t pmu_version,
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|
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@ -42,6 +91,7 @@ static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct kvm_vcpu **vcpu,
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vm = vm_create_with_one_vcpu(vcpu, guest_code);
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sync_global_to_guest(vm, kvm_pmu_version);
|
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sync_global_to_guest(vm, hardware_pmu_arch_events);
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|
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/*
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* Set PERF_CAPABILITIES before PMU version as KVM disallows enabling
|
||||
|
|
@ -98,14 +148,12 @@ static uint8_t guest_get_pmu_version(void)
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* Sanity check that in all cases, the event doesn't count when it's disabled,
|
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* and that KVM correctly emulates the write of an arbitrary value.
|
||||
*/
|
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static void guest_assert_event_count(uint8_t idx,
|
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struct kvm_x86_pmu_feature event,
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uint32_t pmc, uint32_t pmc_msr)
|
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static void guest_assert_event_count(uint8_t idx, uint32_t pmc, uint32_t pmc_msr)
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{
|
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uint64_t count;
|
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|
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count = _rdpmc(pmc);
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if (!this_pmu_has(event))
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if (!(hardware_pmu_arch_events & BIT(idx)))
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goto sanity_checks;
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|
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switch (idx) {
|
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|
|
@ -126,7 +174,9 @@ static void guest_assert_event_count(uint8_t idx,
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GUEST_ASSERT_NE(count, 0);
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break;
|
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case INTEL_ARCH_TOPDOWN_SLOTS_INDEX:
|
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GUEST_ASSERT(count >= NUM_INSNS_RETIRED);
|
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__GUEST_ASSERT(count >= NUM_INSNS_RETIRED,
|
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"Expected top-down slots >= %u, got count = %lu",
|
||||
NUM_INSNS_RETIRED, count);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
|
@ -162,75 +212,42 @@ do { \
|
|||
"1:\n\t" \
|
||||
clflush "\n\t" \
|
||||
"mfence\n\t" \
|
||||
"mov %[m], %%eax\n\t" \
|
||||
FEP "loop 1b\n\t" \
|
||||
FEP "mov %%edi, %%ecx\n\t" \
|
||||
FEP "xor %%eax, %%eax\n\t" \
|
||||
FEP "xor %%edx, %%edx\n\t" \
|
||||
"wrmsr\n\t" \
|
||||
:: "a"((uint32_t)_value), "d"(_value >> 32), \
|
||||
"c"(_msr), "D"(_msr) \
|
||||
"c"(_msr), "D"(_msr), [m]"m"(kvm_pmu_version) \
|
||||
); \
|
||||
} while (0)
|
||||
|
||||
#define GUEST_TEST_EVENT(_idx, _event, _pmc, _pmc_msr, _ctrl_msr, _value, FEP) \
|
||||
#define GUEST_TEST_EVENT(_idx, _pmc, _pmc_msr, _ctrl_msr, _value, FEP) \
|
||||
do { \
|
||||
wrmsr(pmc_msr, 0); \
|
||||
wrmsr(_pmc_msr, 0); \
|
||||
\
|
||||
if (this_cpu_has(X86_FEATURE_CLFLUSHOPT)) \
|
||||
GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflushopt .", FEP); \
|
||||
GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflushopt %[m]", FEP); \
|
||||
else if (this_cpu_has(X86_FEATURE_CLFLUSH)) \
|
||||
GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflush .", FEP); \
|
||||
GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflush %[m]", FEP); \
|
||||
else \
|
||||
GUEST_MEASURE_EVENT(_ctrl_msr, _value, "nop", FEP); \
|
||||
\
|
||||
guest_assert_event_count(_idx, _event, _pmc, _pmc_msr); \
|
||||
guest_assert_event_count(_idx, _pmc, _pmc_msr); \
|
||||
} while (0)
|
||||
|
||||
static void __guest_test_arch_event(uint8_t idx, struct kvm_x86_pmu_feature event,
|
||||
uint32_t pmc, uint32_t pmc_msr,
|
||||
static void __guest_test_arch_event(uint8_t idx, uint32_t pmc, uint32_t pmc_msr,
|
||||
uint32_t ctrl_msr, uint64_t ctrl_msr_value)
|
||||
{
|
||||
GUEST_TEST_EVENT(idx, event, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, "");
|
||||
GUEST_TEST_EVENT(idx, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, "");
|
||||
|
||||
if (is_forced_emulation_enabled)
|
||||
GUEST_TEST_EVENT(idx, event, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, KVM_FEP);
|
||||
}
|
||||
|
||||
#define X86_PMU_FEATURE_NULL \
|
||||
({ \
|
||||
struct kvm_x86_pmu_feature feature = {}; \
|
||||
\
|
||||
feature; \
|
||||
})
|
||||
|
||||
static bool pmu_is_null_feature(struct kvm_x86_pmu_feature event)
|
||||
{
|
||||
return !(*(u64 *)&event);
|
||||
GUEST_TEST_EVENT(idx, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, KVM_FEP);
|
||||
}
|
||||
|
||||
static void guest_test_arch_event(uint8_t idx)
|
||||
{
|
||||
const struct {
|
||||
struct kvm_x86_pmu_feature gp_event;
|
||||
struct kvm_x86_pmu_feature fixed_event;
|
||||
} intel_event_to_feature[] = {
|
||||
[INTEL_ARCH_CPU_CYCLES_INDEX] = { X86_PMU_FEATURE_CPU_CYCLES, X86_PMU_FEATURE_CPU_CYCLES_FIXED },
|
||||
[INTEL_ARCH_INSTRUCTIONS_RETIRED_INDEX] = { X86_PMU_FEATURE_INSNS_RETIRED, X86_PMU_FEATURE_INSNS_RETIRED_FIXED },
|
||||
/*
|
||||
* Note, the fixed counter for reference cycles is NOT the same
|
||||
* as the general purpose architectural event. The fixed counter
|
||||
* explicitly counts at the same frequency as the TSC, whereas
|
||||
* the GP event counts at a fixed, but uarch specific, frequency.
|
||||
* Bundle them here for simplicity.
|
||||
*/
|
||||
[INTEL_ARCH_REFERENCE_CYCLES_INDEX] = { X86_PMU_FEATURE_REFERENCE_CYCLES, X86_PMU_FEATURE_REFERENCE_TSC_CYCLES_FIXED },
|
||||
[INTEL_ARCH_LLC_REFERENCES_INDEX] = { X86_PMU_FEATURE_LLC_REFERENCES, X86_PMU_FEATURE_NULL },
|
||||
[INTEL_ARCH_LLC_MISSES_INDEX] = { X86_PMU_FEATURE_LLC_MISSES, X86_PMU_FEATURE_NULL },
|
||||
[INTEL_ARCH_BRANCHES_RETIRED_INDEX] = { X86_PMU_FEATURE_BRANCH_INSNS_RETIRED, X86_PMU_FEATURE_NULL },
|
||||
[INTEL_ARCH_BRANCHES_MISPREDICTED_INDEX] = { X86_PMU_FEATURE_BRANCHES_MISPREDICTED, X86_PMU_FEATURE_NULL },
|
||||
[INTEL_ARCH_TOPDOWN_SLOTS_INDEX] = { X86_PMU_FEATURE_TOPDOWN_SLOTS, X86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED },
|
||||
};
|
||||
|
||||
uint32_t nr_gp_counters = this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS);
|
||||
uint32_t pmu_version = guest_get_pmu_version();
|
||||
/* PERF_GLOBAL_CTRL exists only for Architectural PMU Version 2+. */
|
||||
|
|
@ -248,7 +265,7 @@ static void guest_test_arch_event(uint8_t idx)
|
|||
else
|
||||
base_pmc_msr = MSR_IA32_PERFCTR0;
|
||||
|
||||
gp_event = intel_event_to_feature[idx].gp_event;
|
||||
gp_event = intel_event_to_feature(idx).gp_event;
|
||||
GUEST_ASSERT_EQ(idx, gp_event.f.bit);
|
||||
|
||||
GUEST_ASSERT(nr_gp_counters);
|
||||
|
|
@ -262,14 +279,14 @@ static void guest_test_arch_event(uint8_t idx)
|
|||
if (guest_has_perf_global_ctrl)
|
||||
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(i));
|
||||
|
||||
__guest_test_arch_event(idx, gp_event, i, base_pmc_msr + i,
|
||||
__guest_test_arch_event(idx, i, base_pmc_msr + i,
|
||||
MSR_P6_EVNTSEL0 + i, eventsel);
|
||||
}
|
||||
|
||||
if (!guest_has_perf_global_ctrl)
|
||||
return;
|
||||
|
||||
fixed_event = intel_event_to_feature[idx].fixed_event;
|
||||
fixed_event = intel_event_to_feature(idx).fixed_event;
|
||||
if (pmu_is_null_feature(fixed_event) || !this_pmu_has(fixed_event))
|
||||
return;
|
||||
|
||||
|
|
@ -277,7 +294,7 @@ static void guest_test_arch_event(uint8_t idx)
|
|||
|
||||
wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, FIXED_PMC_CTRL(i, FIXED_PMC_KERNEL));
|
||||
|
||||
__guest_test_arch_event(idx, fixed_event, i | INTEL_RDPMC_FIXED,
|
||||
__guest_test_arch_event(idx, i | INTEL_RDPMC_FIXED,
|
||||
MSR_CORE_PERF_FIXED_CTR0 + i,
|
||||
MSR_CORE_PERF_GLOBAL_CTRL,
|
||||
FIXED_PMC_GLOBAL_CTRL_ENABLE(i));
|
||||
|
|
@ -331,9 +348,9 @@ __GUEST_ASSERT(expect_gp ? vector == GP_VECTOR : !vector, \
|
|||
expect_gp ? "#GP" : "no fault", msr, vector) \
|
||||
|
||||
#define GUEST_ASSERT_PMC_VALUE(insn, msr, val, expected) \
|
||||
__GUEST_ASSERT(val == expected_val, \
|
||||
__GUEST_ASSERT(val == expected, \
|
||||
"Expected " #insn "(0x%x) to yield 0x%lx, got 0x%lx", \
|
||||
msr, expected_val, val);
|
||||
msr, expected, val);
|
||||
|
||||
static void guest_test_rdpmc(uint32_t rdpmc_idx, bool expect_success,
|
||||
uint64_t expected_val)
|
||||
|
|
@ -545,7 +562,6 @@ static void test_fixed_counters(uint8_t pmu_version, uint64_t perf_capabilities,
|
|||
|
||||
static void test_intel_counters(void)
|
||||
{
|
||||
uint8_t nr_arch_events = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH);
|
||||
uint8_t nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS);
|
||||
uint8_t nr_gp_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS);
|
||||
uint8_t pmu_version = kvm_cpu_property(X86_PROPERTY_PMU_VERSION);
|
||||
|
|
@ -567,18 +583,26 @@ static void test_intel_counters(void)
|
|||
|
||||
/*
|
||||
* Detect the existence of events that aren't supported by selftests.
|
||||
* This will (obviously) fail any time the kernel adds support for a
|
||||
* new event, but it's worth paying that price to keep the test fresh.
|
||||
* This will (obviously) fail any time hardware adds support for a new
|
||||
* event, but it's worth paying that price to keep the test fresh.
|
||||
*/
|
||||
TEST_ASSERT(nr_arch_events <= NR_INTEL_ARCH_EVENTS,
|
||||
TEST_ASSERT(this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH) <= NR_INTEL_ARCH_EVENTS,
|
||||
"New architectural event(s) detected; please update this test (length = %u, mask = %x)",
|
||||
nr_arch_events, kvm_cpu_property(X86_PROPERTY_PMU_EVENTS_MASK));
|
||||
this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH),
|
||||
this_cpu_property(X86_PROPERTY_PMU_EVENTS_MASK));
|
||||
|
||||
/*
|
||||
* Force iterating over known arch events regardless of whether or not
|
||||
* KVM/hardware supports a given event.
|
||||
* Iterate over known arch events irrespective of KVM/hardware support
|
||||
* to verify that KVM doesn't reject programming of events just because
|
||||
* the *architectural* encoding is unsupported. Track which events are
|
||||
* supported in hardware; the guest side will validate supported events
|
||||
* count correctly, even if *enumeration* of the event is unsupported
|
||||
* by KVM and/or isn't exposed to the guest.
|
||||
*/
|
||||
nr_arch_events = max_t(typeof(nr_arch_events), nr_arch_events, NR_INTEL_ARCH_EVENTS);
|
||||
for (i = 0; i < NR_INTEL_ARCH_EVENTS; i++) {
|
||||
if (this_pmu_has(intel_event_to_feature(i).gp_event))
|
||||
hardware_pmu_arch_events |= BIT(i);
|
||||
}
|
||||
|
||||
for (v = 0; v <= max_pmu_version; v++) {
|
||||
for (i = 0; i < ARRAY_SIZE(perf_caps); i++) {
|
||||
|
|
@ -594,8 +618,8 @@ static void test_intel_counters(void)
|
|||
* vector length.
|
||||
*/
|
||||
if (v == pmu_version) {
|
||||
for (k = 1; k < (BIT(nr_arch_events) - 1); k++)
|
||||
test_arch_events(v, perf_caps[i], nr_arch_events, k);
|
||||
for (k = 1; k < (BIT(NR_INTEL_ARCH_EVENTS) - 1); k++)
|
||||
test_arch_events(v, perf_caps[i], NR_INTEL_ARCH_EVENTS, k);
|
||||
}
|
||||
/*
|
||||
* Test single bits for all PMU version and lengths up
|
||||
|
|
@ -604,11 +628,11 @@ static void test_intel_counters(void)
|
|||
* host length). Explicitly test a mask of '0' and all
|
||||
* ones i.e. all events being available and unavailable.
|
||||
*/
|
||||
for (j = 0; j <= nr_arch_events + 1; j++) {
|
||||
for (j = 0; j <= NR_INTEL_ARCH_EVENTS + 1; j++) {
|
||||
test_arch_events(v, perf_caps[i], j, 0);
|
||||
test_arch_events(v, perf_caps[i], j, 0xff);
|
||||
|
||||
for (k = 0; k < nr_arch_events; k++)
|
||||
for (k = 0; k < NR_INTEL_ARCH_EVENTS; k++)
|
||||
test_arch_events(v, perf_caps[i], j, BIT(k));
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -42,10 +42,7 @@ static void l2_guest_code(struct svm_test_data *svm)
|
|||
x2apic_write_reg(APIC_ICR,
|
||||
APIC_DEST_SELF | APIC_INT_ASSERT | INTR_IRQ_NUMBER);
|
||||
|
||||
__asm__ __volatile__(
|
||||
"sti\n"
|
||||
"nop\n"
|
||||
);
|
||||
sti_nop();
|
||||
|
||||
GUEST_ASSERT(vintr_irq_called);
|
||||
GUEST_ASSERT(intr_irq_called);
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@ static void ucna_injection_guest_code(void)
|
|||
wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN);
|
||||
|
||||
/* Enables interrupt in guest. */
|
||||
asm volatile("sti");
|
||||
sti();
|
||||
|
||||
/* Let user space inject the first UCNA */
|
||||
GUEST_SYNC(SYNC_FIRST_UCNA);
|
||||
|
|
|
|||
|
|
@ -106,7 +106,8 @@ static void halter_guest_code(struct test_data_page *data)
|
|||
data->halter_tpr = xapic_read_reg(APIC_TASKPRI);
|
||||
data->halter_ppr = xapic_read_reg(APIC_PROCPRI);
|
||||
data->hlt_count++;
|
||||
asm volatile("sti; hlt; cli");
|
||||
safe_halt();
|
||||
cli();
|
||||
data->wake_count++;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ struct xapic_vcpu {
|
|||
|
||||
static void xapic_guest_code(void)
|
||||
{
|
||||
asm volatile("cli");
|
||||
cli();
|
||||
|
||||
xapic_enable();
|
||||
|
||||
|
|
@ -38,7 +38,7 @@ static void xapic_guest_code(void)
|
|||
|
||||
static void x2apic_guest_code(void)
|
||||
{
|
||||
asm volatile("cli");
|
||||
cli();
|
||||
|
||||
x2apic_enable();
|
||||
|
||||
|
|
|
|||
|
|
@ -191,10 +191,7 @@ static void guest_code(void)
|
|||
struct vcpu_runstate_info *rs = (void *)RUNSTATE_VADDR;
|
||||
int i;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"sti\n"
|
||||
"nop\n"
|
||||
);
|
||||
sti_nop();
|
||||
|
||||
/* Trigger an interrupt injection */
|
||||
GUEST_SYNC(TEST_INJECT_VECTOR);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user