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Merge branch irq/generic_handle_domain_irq into irq/irqchip-next

Browse Source 
- Tree-wide conversion to generic_handle_domain_irq()
- irqdomain documentation update

* irq/generic_handle_domain_irq:
  EDAC/altera: Convert to generic_handle_domain_irq()
  powerpc: Bulk conversion to generic_handle_domain_irq()
  nios2: Bulk conversion to generic_handle_domain_irq()
  xtensa: Bulk conversion to generic_handle_domain_irq()
  SH: Bulk conversion to generic_handle_domain_irq()
  gpu: Bulk conversion to generic_handle_domain_irq()
  mips: Bulk conversion to generic_handle_domain_irq()
  arc: Bulk conversion to generic_handle_domain_irq()
  ARM: Bulk conversion to generic_handle_domain_irq()
  mfd: Bulk conversion to generic_handle_domain_irq()
  pinctrl: Bulk conversion to generic_handle_domain_irq()
  gpio: Bulk conversion to generic_handle_domain_irq()
  Documentation: Update irq_domain.rst with new lookup APIs

Signed-off-by: Marc Zyngier <maz@kernel.org>
This commit is contained in:
Marc Zyngier 2021-08-12 11:40:15 +01:00
commit 9b24dab993
109 changed files with 286 additions and 427 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
Documentation/core-api/irq/irq-domain.rst
View File

@ -55,8 +55,24 @@ exist then it will allocate a new Linux irq_desc, associate it with
the hwirq, and call the .map() callback so the driver can perform any
required hardware setup.
When an interrupt is received, irq_find_mapping() function should
be used to find the Linux IRQ number from the hwirq number.
Once a mapping has been established, it can be retrieved or used via a
variety of methods:
- irq_resolve_mapping() returns a pointer to the irq_desc structure
for a given domain and hwirq number, and NULL if there was no
mapping.
- irq_find_mapping() returns a Linux IRQ number for a given domain and
hwirq number, and 0 if there was no mapping
- irq_linear_revmap() is now identical to irq_find_mapping(), and is
deprecated
- generic_handle_domain_irq() handles an interrupt described by a
domain and a hwirq number
- handle_domain_irq() does the same thing for root interrupt
controllers and deals with the set_irq_reg()/irq_enter() sequences
that most architecture requires
Note that irq domain lookups must happen in contexts that are
compatible with a RCU read-side critical section.
The irq_create_mapping() function must be called *atleast once*
before any call to irq_find_mapping(), lest the descriptor will not
@ -137,7 +153,9 @@ required. Calling irq_create_direct_mapping() will allocate a Linux
IRQ number and call the .map() callback so that driver can program the
Linux IRQ number into the hardware.
Most drivers cannot use this mapping.
Most drivers cannot use this mapping, and it is now gated on the
CONFIG_IRQ_DOMAIN_NOMAP option. Please refrain from introducing new
users of this API.
Legacy
------
@ -157,6 +175,10 @@ for IRQ numbers that are passed to struct device registrations. In that
case the Linux IRQ numbers cannot be dynamically assigned and the legacy
mapping should be used.
As the name implies, the *_legacy() functions are deprecated and only
exist to ease the support of ancient platforms. No new users should be
added.
The legacy map assumes a contiguous range of IRQ numbers has already
been allocated for the controller and that the IRQ number can be
calculated by adding a fixed offset to the hwirq number, and

2
arch/arc/kernel/mcip.c
View File

@ -352,7 +352,7 @@ static void idu_cascade_isr(struct irq_desc *desc)
irq_hw_number_t idu_hwirq = core_hwirq - FIRST_EXT_IRQ;
chained_irq_enter(core_chip, desc);
generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq));
generic_handle_domain_irq(idu_domain, idu_hwirq);
chained_irq_exit(core_chip, desc);
}

12
arch/arm/common/sa1111.c
View File

@ -196,14 +196,6 @@ static int sa1111_map_irq(struct sa1111 *sachip, irq_hw_number_t hwirq)
return irq_create_mapping(sachip->irqdomain, hwirq);
}
static void sa1111_handle_irqdomain(struct irq_domain *irqdomain, int irq)
{
struct irq_desc *d = irq_to_desc(irq_linear_revmap(irqdomain, irq));
if (d)
generic_handle_irq_desc(d);
}
/*
* SA1111 interrupt support. Since clearing an IRQ while there are
* active IRQs causes the interrupt output to pulse, the upper levels
@ -234,11 +226,11 @@ static void sa1111_irq_handler(struct irq_desc *desc)
for (i = 0; stat0; i++, stat0 >>= 1)
if (stat0 & 1)
sa1111_handle_irqdomain(irqdomain, i);
generic_handle_domain_irq(irqdomain, i);
for (i = 32; stat1; i++, stat1 >>= 1)
if (stat1 & 1)
sa1111_handle_irqdomain(irqdomain, i);
generic_handle_domain_irq(irqdomain, i);
/* For level-based interrupts */
desc->irq_data.chip->irq_unmask(&desc->irq_data);

6
arch/arm/mach-pxa/pxa_cplds_irqs.c
View File

@ -39,10 +39,8 @@ static irqreturn_t cplds_irq_handler(int in_irq, void *d)
do {
pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask;
for_each_set_bit(bit, &pending, CPLDS_NB_IRQ) {
generic_handle_irq(irq_find_mapping(fpga->irqdomain,
bit));
}
for_each_set_bit(bit, &pending, CPLDS_NB_IRQ)
generic_handle_domain_irq(fpga->irqdomain, bit);
} while (pending);
return IRQ_HANDLED;

5
arch/arm/mach-s3c/irq-s3c24xx.c
View File

@ -298,7 +298,7 @@ static void s3c_irq_demux(struct irq_desc *desc)
struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
struct s3c_irq_intc *intc = irq_data->intc;
struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
unsigned int n, offset, irq;
unsigned int n, offset;
unsigned long src, msk;
/* we're using individual domains for the non-dt case
@ -318,8 +318,7 @@ static void s3c_irq_demux(struct irq_desc *desc)
while (src) {
n = __ffs(src);
src &= ~(1 << n);
irq = irq_find_mapping(sub_intc->domain, offset + n);
generic_handle_irq(irq);
generic_handle_domain_irq(sub_intc->domain, offset + n);
}
chained_irq_exit(chip, desc);

14
arch/mips/ath25/ar2315.c
View File

@ -69,24 +69,24 @@ static void ar2315_misc_irq_handler(struct irq_desc *desc)
{
u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
ar2315_rst_reg_read(AR2315_IMR);
unsigned nr, misc_irq = 0;
unsigned nr;
int ret = 0;
if (pending) {
struct irq_domain *domain = irq_desc_get_handler_data(desc);
nr = __ffs(pending);
misc_irq = irq_find_mapping(domain, nr);
}
if (misc_irq) {
if (nr == AR2315_MISC_IRQ_GPIO)
ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
else if (nr == AR2315_MISC_IRQ_WATCHDOG)
ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
generic_handle_irq(misc_irq);
} else {
spurious_interrupt();
ret = generic_handle_domain_irq(domain, nr);
}
if (!pending || ret)
spurious_interrupt();
}
static void ar2315_misc_irq_unmask(struct irq_data *d)

13
arch/mips/ath25/ar5312.c
View File

@ -73,22 +73,21 @@ static void ar5312_misc_irq_handler(struct irq_desc *desc)
{
u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
ar5312_rst_reg_read(AR5312_IMR);
unsigned nr, misc_irq = 0;
unsigned nr;
int ret = 0;
if (pending) {
struct irq_domain *domain = irq_desc_get_handler_data(desc);
nr = __ffs(pending);
misc_irq = irq_find_mapping(domain, nr);
}
if (misc_irq) {
generic_handle_irq(misc_irq);
ret = generic_handle_domain_irq(domain, nr);
if (nr == AR5312_MISC_IRQ_TIMER)
ar5312_rst_reg_read(AR5312_TIMER);
} else {
spurious_interrupt();
}
if (!pending || ret)
spurious_interrupt();
}
/* Enable the specified AR5312_MISC_IRQ interrupt */

2
arch/mips/lantiq/irq.c
View File

@ -300,7 +300,7 @@ static void ltq_hw_irq_handler(struct irq_desc *desc)
*/
irq = __fls(irq);
hwirq = irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module);
generic_handle_irq(irq_linear_revmap(ltq_domain, hwirq));
generic_handle_domain_irq(ltq_domain, hwirq);
/* if this is a EBU irq, we need to ack it or get a deadlock */
if (irq == LTQ_ICU_EBU_IRQ && !module && LTQ_EBU_PCC_ISTAT != 0)

8
arch/mips/pci/pci-ar2315.c
View File

@ -337,14 +337,12 @@ static void ar2315_pci_irq_handler(struct irq_desc *desc)
struct ar2315_pci_ctrl *apc = irq_desc_get_handler_data(desc);
u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
unsigned pci_irq = 0;
int ret = 0;
if (pending)
pci_irq = irq_find_mapping(apc->domain, __ffs(pending));
ret = generic_handle_domain_irq(apc->domain, __ffs(pending));
if (pci_irq)
generic_handle_irq(pci_irq);
else
if (!pending || ret)
spurious_interrupt();
}

5
arch/mips/pci/pci-rt3883.c
View File

@ -140,10 +140,9 @@ static void rt3883_pci_irq_handler(struct irq_desc *desc)
}
while (pending) {
unsigned irq, bit = __ffs(pending);
unsigned bit = __ffs(pending);
irq = irq_find_mapping(rpc->irq_domain, bit);
generic_handle_irq(irq);
generic_handle_domain_irq(rpc->irq_domain, bit);
pending &= ~BIT(bit);
}

2
arch/mips/ralink/irq.c
View File

@ -100,7 +100,7 @@ static void ralink_intc_irq_handler(struct irq_desc *desc)
if (pending) {
struct irq_domain *domain = irq_desc_get_handler_data(desc);
generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
generic_handle_domain_irq(domain, __ffs(pending));
} else {
spurious_interrupt();
}

16
arch/mips/sgi-ip27/ip27-irq.c
View File

@ -190,7 +190,7 @@ static void ip27_do_irq_mask0(struct irq_desc *desc)
unsigned long *mask = per_cpu(irq_enable_mask, cpu);
struct irq_domain *domain;
u64 pend0;
int irq;
int ret;
/* copied from Irix intpend0() */
pend0 = LOCAL_HUB_L(PI_INT_PEND0);
@ -216,10 +216,8 @@ static void ip27_do_irq_mask0(struct irq_desc *desc)
#endif
{
domain = irq_desc_get_handler_data(desc);
irq = irq_linear_revmap(domain, __ffs(pend0));
if (irq)
generic_handle_irq(irq);
else
ret = generic_handle_domain_irq(domain, __ffs(pend0));
if (ret)
spurious_interrupt();
}
@ -232,7 +230,7 @@ static void ip27_do_irq_mask1(struct irq_desc *desc)
unsigned long *mask = per_cpu(irq_enable_mask, cpu);
struct irq_domain *domain;
u64 pend1;
int irq;
int ret;
/* copied from Irix intpend0() */
pend1 = LOCAL_HUB_L(PI_INT_PEND1);
@ -242,10 +240,8 @@ static void ip27_do_irq_mask1(struct irq_desc *desc)
return;
domain = irq_desc_get_handler_data(desc);
irq = irq_linear_revmap(domain, __ffs(pend1) + 64);
if (irq)
generic_handle_irq(irq);
else
ret = generic_handle_domain_irq(domain, __ffs(pend1) + 64);
if (ret)
spurious_interrupt();
LOCAL_HUB_L(PI_INT_PEND1);

8
arch/mips/sgi-ip30/ip30-irq.c
View File

@ -99,7 +99,7 @@ static void ip30_normal_irq(struct irq_desc *desc)
int cpu = smp_processor_id();
struct irq_domain *domain;
u64 pend, mask;
int irq;
int ret;
pend = heart_read(&heart_regs->isr);
mask = (heart_read(&heart_regs->imr[cpu]) &
@ -130,10 +130,8 @@ static void ip30_normal_irq(struct irq_desc *desc)
#endif
{
domain = irq_desc_get_handler_data(desc);
irq = irq_linear_revmap(domain, __ffs(pend));
if (irq)
generic_handle_irq(irq);
else
ret = generic_handle_domain_irq(domain, __ffs(pend));
if (ret)
spurious_interrupt();
}
}

4
arch/nios2/kernel/irq.c
View File

@ -19,11 +19,9 @@ static u32 ienable;
asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
{
struct pt_regs *oldregs = set_irq_regs(regs);
int irq;
irq_enter();
irq = irq_find_mapping(NULL, hwirq);
generic_handle_irq(irq);
generic_handle_domain_irq(NULL, hwirq);
irq_exit();
set_irq_regs(oldregs);

4
arch/powerpc/platforms/4xx/uic.c
View File

@ -198,7 +198,6 @@ static void uic_irq_cascade(struct irq_desc *desc)
struct uic *uic = irq_desc_get_handler_data(desc);
u32 msr;
int src;
int subvirq;
raw_spin_lock(&desc->lock);
if (irqd_is_level_type(idata))
@ -213,8 +212,7 @@ static void uic_irq_cascade(struct irq_desc *desc)
src = 32 - ffs(msr);
subvirq = irq_linear_revmap(uic->irqhost, src);
generic_handle_irq(subvirq);
generic_handle_domain_irq(uic->irqhost, src);
uic_irq_ret:
raw_spin_lock(&desc->lock);

23
arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
View File

@ -81,11 +81,10 @@ static struct irq_chip cpld_pic = {
.irq_unmask = cpld_unmask_irq,
};
static int
static unsigned int
cpld_pic_get_irq(int offset, u8 ignore, u8 __iomem *statusp,
u8 __iomem *maskp)
{
int cpld_irq;
u8 status = in_8(statusp);
u8 mask = in_8(maskp);
@ -93,28 +92,26 @@ cpld_pic_get_irq(int offset, u8 ignore, u8 __iomem *statusp,
status |= (ignore | mask);
if (status == 0xff)
return 0;
return ~0;
cpld_irq = ffz(status) + offset;
return irq_linear_revmap(cpld_pic_host, cpld_irq);
return ffz(status) + offset;
}
static void cpld_pic_cascade(struct irq_desc *desc)
{
unsigned int irq;
unsigned int hwirq;
irq = cpld_pic_get_irq(0, PCI_IGNORE, &cpld_regs->pci_status,
hwirq = cpld_pic_get_irq(0, PCI_IGNORE, &cpld_regs->pci_status,
&cpld_regs->pci_mask);
if (irq) {
generic_handle_irq(irq);
if (hwirq != ~0) {
generic_handle_domain_irq(cpld_pic_host, hwirq);
return;
}
irq = cpld_pic_get_irq(8, MISC_IGNORE, &cpld_regs->misc_status,
hwirq = cpld_pic_get_irq(8, MISC_IGNORE, &cpld_regs->misc_status,
&cpld_regs->misc_mask);
if (irq) {
generic_handle_irq(irq);
if (hwirq != ~0) {
generic_handle_domain_irq(cpld_pic_host, hwirq);
return;
}
}

9
arch/powerpc/platforms/52xx/media5200.c
View File

@ -78,7 +78,7 @@ static struct irq_chip media5200_irq_chip = {
static void media5200_irq_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
int sub_virq, val;
int val;
u32 status, enable;
/* Mask off the cascaded IRQ */
@ -92,11 +92,10 @@ static void media5200_irq_cascade(struct irq_desc *desc)
enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
if (val) {
sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
/* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
* __func__, virq, status, enable, val - 1, sub_virq);
generic_handle_domain_irq(media5200_irq.irqhost, val - 1);
/* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i\n",
* __func__, virq, status, enable, val - 1);
*/
generic_handle_irq(sub_virq);
}
/* Processing done; can reenable the cascade now */

7
arch/powerpc/platforms/52xx/mpc52xx_gpt.c
View File

@ -190,14 +190,11 @@ static struct irq_chip mpc52xx_gpt_irq_chip = {
static void mpc52xx_gpt_irq_cascade(struct irq_desc *desc)
{
struct mpc52xx_gpt_priv *gpt = irq_desc_get_handler_data(desc);
int sub_virq;
u32 status;
status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
if (status) {
sub_virq = irq_linear_revmap(gpt->irqhost, 0);
generic_handle_irq(sub_virq);
}
if (status)
generic_handle_domain_irq(gpt->irqhost, 0);
}
static int mpc52xx_gpt_irq_map(struct irq_domain *h, unsigned int virq,

6
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
View File

@ -91,10 +91,8 @@ static void pq2ads_pci_irq_demux(struct irq_desc *desc)
break;
for (bit = 0; pend != 0; ++bit, pend <<= 1) {
if (pend & 0x80000000) {
int virq = irq_linear_revmap(priv->host, bit);
generic_handle_irq(virq);
}
if (pend & 0x80000000)
generic_handle_domain_irq(priv->host, bit);
}
}
}

8
arch/powerpc/platforms/cell/interrupt.c
View File

@ -106,13 +106,9 @@ static void iic_ioexc_cascade(struct irq_desc *desc)
out_be64(&node_iic->iic_is, ack);
/* handle them */
for (cascade = 63; cascade >= 0; cascade--)
if (bits & (0x8000000000000000UL >> cascade)) {
unsigned int cirq =
irq_linear_revmap(iic_host,
if (bits & (0x8000000000000000UL >> cascade))
generic_handle_domain_irq(iic_host,
base | cascade);
if (cirq)
generic_handle_irq(cirq);
}
/* post-ack level interrupts */
ack = bits & ~IIC_ISR_EDGE_MASK;
if (ack)

11
arch/powerpc/platforms/cell/spider-pic.c
View File

@ -190,16 +190,11 @@ static void spider_irq_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct spider_pic *pic = irq_desc_get_handler_data(desc);
unsigned int cs, virq;
unsigned int cs;
cs = in_be32(pic->regs + TIR_CS) >> 24;
if (cs == SPIDER_IRQ_INVALID)
virq = 0;
else
virq = irq_linear_revmap(pic->host, cs);
if (virq)
generic_handle_irq(virq);
if (cs != SPIDER_IRQ_INVALID)
generic_handle_domain_irq(pic->host, cs);
chip->irq_eoi(&desc->irq_data);
}

15
arch/powerpc/platforms/embedded6xx/hlwd-pic.c
View File

@ -108,7 +108,6 @@ static const struct irq_domain_ops hlwd_irq_domain_ops = {
static unsigned int __hlwd_pic_get_irq(struct irq_domain *h)
{
void __iomem *io_base = h->host_data;
int irq;
u32 irq_status;
irq_status = in_be32(io_base + HW_BROADWAY_ICR) &
@ -116,23 +115,22 @@ static unsigned int __hlwd_pic_get_irq(struct irq_domain *h)
if (irq_status == 0)
return 0; /* no more IRQs pending */
irq = __ffs(irq_status);
return irq_linear_revmap(h, irq);
return __ffs(irq_status);
}
static void hlwd_pic_irq_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_domain *irq_domain = irq_desc_get_handler_data(desc);
unsigned int virq;
unsigned int hwirq;
raw_spin_lock(&desc->lock);
chip->irq_mask(&desc->irq_data); /* IRQ_LEVEL */
raw_spin_unlock(&desc->lock);
virq = __hlwd_pic_get_irq(irq_domain);
if (virq)
generic_handle_irq(virq);
hwirq = __hlwd_pic_get_irq(irq_domain);
if (hwirq)
generic_handle_domain_irq(irq_domain, hwirq);
else
pr_err("spurious interrupt!\n");
@ -190,7 +188,8 @@ static struct irq_domain *hlwd_pic_init(struct device_node *np)
unsigned int hlwd_pic_get_irq(void)
{
return __hlwd_pic_get_irq(hlwd_irq_host);
unsigned int hwirq = __hlwd_pic_get_irq(hlwd_irq_host);
return hwirq ? irq_linear_revmap(hlwd_irq_host, hwirq) : 0;
}
/*

11
arch/powerpc/platforms/powernv/opal-irqchip.c
View File

@ -46,18 +46,15 @@ void opal_handle_events(void)
e = READ_ONCE(last_outstanding_events) & opal_event_irqchip.mask;
again:
while (e) {
int virq, hwirq;
int hwirq;
hwirq = fls64(e) - 1;
e &= ~BIT_ULL(hwirq);
local_irq_disable();
virq = irq_find_mapping(opal_event_irqchip.domain, hwirq);
if (virq) {
irq_enter();
generic_handle_irq(virq);
irq_exit();
}
irq_enter();
generic_handle_domain_irq(opal_event_irqchip.domain, hwirq);
irq_exit();
local_irq_enable();
cond_resched();

11
arch/powerpc/sysdev/fsl_mpic_err.c
View File

@ -99,7 +99,6 @@ static irqreturn_t fsl_error_int_handler(int irq, void *data)
struct mpic *mpic = (struct mpic *) data;
u32 eisr, eimr;
int errint;
unsigned int cascade_irq;
eisr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EISR);
eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR);
@ -108,13 +107,11 @@ static irqreturn_t fsl_error_int_handler(int irq, void *data)
return IRQ_NONE;
while (eisr) {
int ret;
errint = __builtin_clz(eisr);
cascade_irq = irq_linear_revmap(mpic->irqhost,
mpic->err_int_vecs[errint]);
WARN_ON(!cascade_irq);
if (cascade_irq) {
generic_handle_irq(cascade_irq);
} else {
ret = generic_handle_domain_irq(mpic->irqhost,
mpic->err_int_vecs[errint]);
if (WARN_ON(ret)) {
eimr |= 1 << (31 - errint);
mpic_fsl_err_write(mpic->err_regs, eimr);
}

12
arch/powerpc/sysdev/fsl_msi.c
View File

@ -266,7 +266,6 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
static irqreturn_t fsl_msi_cascade(int irq, void *data)
{
unsigned int cascade_irq;
struct fsl_msi *msi_data;
int msir_index = -1;
u32 msir_value = 0;
@ -279,9 +278,6 @@ static irqreturn_t fsl_msi_cascade(int irq, void *data)
msir_index = cascade_data->index;
if (msir_index >= NR_MSI_REG_MAX)
cascade_irq = 0;
switch (msi_data->feature & FSL_PIC_IP_MASK) {
case FSL_PIC_IP_MPIC:
msir_value = fsl_msi_read(msi_data->msi_regs,
@ -305,15 +301,15 @@ static irqreturn_t fsl_msi_cascade(int irq, void *data)
}
while (msir_value) {
int err;
intr_index = ffs(msir_value) - 1;
cascade_irq = irq_linear_revmap(msi_data->irqhost,
err = generic_handle_domain_irq(msi_data->irqhost,
msi_hwirq(msi_data, msir_index,
intr_index + have_shift));
if (cascade_irq) {
generic_handle_irq(cascade_irq);
if (!err)
ret = IRQ_HANDLED;
}
have_shift += intr_index + 1;
msir_value = msir_value >> (intr_index + 1);
}

2
arch/sh/boards/mach-se/7343/irq.c
View File

@ -38,7 +38,7 @@ static void se7343_irq_demux(struct irq_desc *desc)
mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG);
for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR)
generic_handle_irq(irq_linear_revmap(se7343_irq_domain, bit));
generic_handle_domain_irq(se7343_irq_domain, bit);
chip->irq_unmask(data);
}

2
arch/sh/boards/mach-se/7722/irq.c
View File

@ -37,7 +37,7 @@ static void se7722_irq_demux(struct irq_desc *desc)
mask = ioread16(se7722_irq_regs + IRQ01_STS_REG);
for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR)
generic_handle_irq(irq_linear_revmap(se7722_irq_domain, bit));
generic_handle_domain_irq(se7722_irq_domain, bit);
chip->irq_unmask(data);
}

2
arch/sh/boards/mach-x3proto/gpio.c
View File

@ -68,7 +68,7 @@ static void x3proto_gpio_irq_handler(struct irq_desc *desc)
mask = __raw_readw(KEYDETR);
for_each_set_bit(pin, &mask, NR_BASEBOARD_GPIOS)
generic_handle_irq(irq_linear_revmap(x3proto_irq_domain, pin));
generic_handle_domain_irq(x3proto_irq_domain, pin);
chip->irq_unmask(data);
}

4
arch/xtensa/kernel/irq.c
View File

@ -33,8 +33,6 @@ DECLARE_PER_CPU(unsigned long, nmi_count);
asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
{
int irq = irq_find_mapping(NULL, hwirq);
#ifdef CONFIG_DEBUG_STACKOVERFLOW
/* Debugging check for stack overflow: is there less than 1KB free? */
{
@ -48,7 +46,7 @@ asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
sp - sizeof(struct thread_info));
}
#endif
generic_handle_irq(irq);
generic_handle_domain_irq(NULL, hwirq);
}
int arch_show_interrupts(struct seq_file *p, int prec)

7
drivers/edac/altera_edac.c
View File

@ -1804,11 +1804,8 @@ static void altr_edac_a10_irq_handler(struct irq_desc *desc)
regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
bits = irq_status;
for_each_set_bit(bit, &bits, 32) {
irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
if (irq)
generic_handle_irq(irq);
}
for_each_set_bit(bit, &bits, 32)
generic_handle_domain_irq(edac->domain, dberr * 32 + bit);
chained_irq_exit(chip, desc);
}

4
drivers/gpio/gpio-104-dio-48e.c
View File

@ -336,8 +336,8 @@ static irqreturn_t dio48e_irq_handler(int irq, void *dev_id)
unsigned long gpio;
for_each_set_bit(gpio, &irq_mask, 2)
generic_handle_irq(irq_find_mapping(chip->irq.domain,
19 + gpio*24));
generic_handle_domain_irq(chip->irq.domain,
19 + gpio*24);
raw_spin_lock(&dio48egpio->lock);

4
drivers/gpio/gpio-104-idi-48.c
View File

@ -223,8 +223,8 @@ static irqreturn_t idi_48_irq_handler(int irq, void *dev_id)
for_each_set_bit(bit_num, &irq_mask, 8) {
gpio = bit_num + boundary * 8;
generic_handle_irq(irq_find_mapping(chip->irq.domain,
gpio));
generic_handle_domain_irq(chip->irq.domain,
gpio);
}
}

2
drivers/gpio/gpio-104-idio-16.c
View File

@ -208,7 +208,7 @@ static irqreturn_t idio_16_irq_handler(int irq, void *dev_id)
int gpio;
for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));
generic_handle_domain_irq(chip->irq.domain, gpio);
raw_spin_lock(&idio16gpio->lock);

11
drivers/gpio/gpio-altera.c
View File

@ -201,9 +201,8 @@ static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
(readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
generic_handle_irq(irq_find_mapping(irqdomain, i));
}
for_each_set_bit(i, &status, mm_gc->gc.ngpio)
generic_handle_domain_irq(irqdomain, i);
}
chained_irq_exit(chip, desc);
@ -228,9 +227,9 @@ static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
generic_handle_irq(irq_find_mapping(irqdomain, i));
}
for_each_set_bit(i, &status, mm_gc->gc.ngpio)
generic_handle_domain_irq(irqdomain, i);
chained_irq_exit(chip, desc);
}

9
drivers/gpio/gpio-aspeed-sgpio.c
View File

@ -392,7 +392,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct irq_chip *ic = irq_desc_get_chip(desc);
struct aspeed_sgpio *data = gpiochip_get_data(gc);
unsigned int i, p, girq;
unsigned int i, p;
unsigned long reg;
chained_irq_enter(ic, desc);
@ -402,11 +402,8 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
reg = ioread32(bank_reg(data, bank, reg_irq_status));
for_each_set_bit(p, &reg, 32) {
girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
generic_handle_irq(girq);
}
for_each_set_bit(p, &reg, 32)
generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
}
chained_irq_exit(ic, desc);

9
drivers/gpio/gpio-aspeed.c
View File

@ -661,7 +661,7 @@ static void aspeed_gpio_irq_handler(struct irq_desc *desc)
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct irq_chip *ic = irq_desc_get_chip(desc);
struct aspeed_gpio *data = gpiochip_get_data(gc);
unsigned int i, p, girq, banks;
unsigned int i, p, banks;
unsigned long reg;
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
@ -673,11 +673,8 @@ static void aspeed_gpio_irq_handler(struct irq_desc *desc)
reg = ioread32(bank_reg(data, bank, reg_irq_status));
for_each_set_bit(p, &reg, 32) {
girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
generic_handle_irq(girq);
}
for_each_set_bit(p, &reg, 32)
generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
}
chained_irq_exit(ic, desc);

7
drivers/gpio/gpio-ath79.c
View File

@ -204,11 +204,8 @@ static void ath79_gpio_irq_handler(struct irq_desc *desc)
raw_spin_unlock_irqrestore(&ctrl->lock, flags);
if (pending) {
for_each_set_bit(irq, &pending, gc->ngpio)
generic_handle_irq(
irq_linear_revmap(gc->irq.domain, irq));
}
for_each_set_bit(irq, &pending, gc->ngpio)
generic_handle_domain_irq(gc->irq.domain, irq);
chained_irq_exit(irqchip, desc);
}

6
drivers/gpio/gpio-bcm-kona.c
View File

@ -466,9 +466,6 @@ static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
(~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
for_each_set_bit(bit, &sta, 32) {
int hwirq = GPIO_PER_BANK * bank_id + bit;
int child_irq =
irq_find_mapping(bank->kona_gpio->irq_domain,
hwirq);
/*
* Clear interrupt before handler is called so we don't
* miss any interrupt occurred during executing them.
@ -476,7 +473,8 @@ static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
/* Invoke interrupt handler */
generic_handle_irq(child_irq);
generic_handle_domain_irq(bank->kona_gpio->irq_domain,
hwirq);
}
}

5
drivers/gpio/gpio-brcmstb.c
View File

@ -277,15 +277,14 @@ static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
unsigned long status;
while ((status = brcmstb_gpio_get_active_irqs(bank))) {
unsigned int irq, offset;
unsigned int offset;
for_each_set_bit(offset, &status, 32) {
if (offset >= bank->width)
dev_warn(&priv->pdev->dev,
"IRQ for invalid GPIO (bank=%d, offset=%d)\n",
bank->id, offset);
irq = irq_linear_revmap(domain, hwbase + offset);
generic_handle_irq(irq);
generic_handle_domain_irq(domain, hwbase + offset);
}
}
}

2
drivers/gpio/gpio-cadence.c
View File

@ -133,7 +133,7 @@ static void cdns_gpio_irq_handler(struct irq_desc *desc)
~ioread32(cgpio->regs + CDNS_GPIO_IRQ_MASK);
for_each_set_bit(hwirq, &status, chip->ngpio)
generic_handle_irq(irq_find_mapping(chip->irq.domain, hwirq));
generic_handle_domain_irq(chip->irq.domain, hwirq);
chained_irq_exit(irqchip, desc);
}

3
drivers/gpio/gpio-davinci.c
View File

@ -369,8 +369,7 @@ static void gpio_irq_handler(struct irq_desc *desc)
*/
hw_irq = (bank_num / 2) * 32 + bit;
generic_handle_irq(
irq_find_mapping(d->irq_domain, hw_irq));
generic_handle_domain_irq(d->irq_domain, hw_irq);
}
}
chained_irq_exit(irq_desc_get_chip(desc), desc);

22
drivers/gpio/gpio-dln2.c
View File

@ -395,7 +395,7 @@ static struct irq_chip dln2_gpio_irqchip = {
static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
const void *data, int len)
{
int pin, irq;
int pin, ret;
const struct {
__le16 count;
@ -416,24 +416,20 @@ static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
return;
}
irq = irq_find_mapping(dln2->gpio.irq.domain, pin);
if (!irq) {
dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin);
return;
}
switch (dln2->irq_type[pin]) {
case DLN2_GPIO_EVENT_CHANGE_RISING:
if (event->value)
generic_handle_irq(irq);
if (!event->value)
return;
break;
case DLN2_GPIO_EVENT_CHANGE_FALLING:
if (!event->value)
generic_handle_irq(irq);
if (event->value)
return;
break;
default:
generic_handle_irq(irq);
}
ret = generic_handle_domain_irq(dln2->gpio.irq.domain, pin);
if (unlikely(ret))
dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin);
}
static int dln2_gpio_probe(struct platform_device *pdev)

2
drivers/gpio/gpio-em.c
View File

@ -173,7 +173,7 @@ static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
while ((pending = em_gio_read(p, GIO_MST))) {
offset = __ffs(pending);
em_gio_write(p, GIO_IIR, BIT(offset));
generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
generic_handle_domain_irq(p->irq_domain, offset);
irqs_handled++;
}

8
drivers/gpio/gpio-ep93xx.c
View File

@ -128,13 +128,13 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
*/
stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
for_each_set_bit(offset, &stat, 8)
generic_handle_irq(irq_find_mapping(epg->gc[0].gc.irq.domain,
offset));
generic_handle_domain_irq(epg->gc[0].gc.irq.domain,
offset);
stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
for_each_set_bit(offset, &stat, 8)
generic_handle_irq(irq_find_mapping(epg->gc[1].gc.irq.domain,
offset));
generic_handle_domain_irq(epg->gc[1].gc.irq.domain,
offset);
chained_irq_exit(irqchip, desc);
}

3
drivers/gpio/gpio-ftgpio010.c
View File

@ -149,8 +149,7 @@ static void ftgpio_gpio_irq_handler(struct irq_desc *desc)
stat = readl(g->base + GPIO_INT_STAT_RAW);
if (stat)
for_each_set_bit(offset, &stat, gc->ngpio)
generic_handle_irq(irq_find_mapping(gc->irq.domain,
offset));
generic_handle_domain_irq(gc->irq.domain, offset);
chained_irq_exit(irqchip, desc);
}

4
drivers/gpio/gpio-hisi.c
View File

@ -186,8 +186,8 @@ static void hisi_gpio_irq_handler(struct irq_desc *desc)
chained_irq_enter(irq_c, desc);
for_each_set_bit(hwirq, &irq_msk, HISI_GPIO_LINE_NUM_MAX)
generic_handle_irq(irq_find_mapping(hisi_gpio->chip.irq.domain,
hwirq));
generic_handle_domain_irq(hisi_gpio->chip.irq.domain,
hwirq);
chained_irq_exit(irq_c, desc);
}

7
drivers/gpio/gpio-hlwd.c
View File

@ -97,11 +97,8 @@ static void hlwd_gpio_irqhandler(struct irq_desc *desc)
chained_irq_enter(chip, desc);
for_each_set_bit(hwirq, &pending, 32) {
int irq = irq_find_mapping(hlwd->gpioc.irq.domain, hwirq);
generic_handle_irq(irq);
}
for_each_set_bit(hwirq, &pending, 32)
generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq);
chained_irq_exit(chip, desc);
}

8
drivers/gpio/gpio-merrifield.c
View File

@ -359,12 +359,8 @@ static void mrfld_irq_handler(struct irq_desc *desc)
/* Only interrupts that are enabled */
pending &= enabled;
for_each_set_bit(gpio, &pending, 32) {
unsigned int irq;
irq = irq_find_mapping(gc->irq.domain, base + gpio);
generic_handle_irq(irq);
}
for_each_set_bit(gpio, &pending, 32)
generic_handle_domain_irq(gc->irq.domain, base + gpio);
}
chained_irq_exit(irqchip, desc);

2
drivers/gpio/gpio-mpc8xxx.c
View File

@ -120,7 +120,7 @@ static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
for_each_set_bit(i, &mask, 32)
generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i));
generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
return IRQ_HANDLED;
}

4
drivers/gpio/gpio-mt7621.c
View File

@ -95,9 +95,7 @@ mediatek_gpio_irq_handler(int irq, void *data)
pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
u32 map = irq_find_mapping(gc->irq.domain, bit);
generic_handle_irq(map);
generic_handle_domain_irq(gc->irq.domain, bit);
mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
ret |= IRQ_HANDLED;
}

2
drivers/gpio/gpio-mxc.c
View File

@ -241,7 +241,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
if (port->both_edges & (1 << irqoffset))
mxc_flip_edge(port, irqoffset);
generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
generic_handle_domain_irq(port->domain, irqoffset);
irq_stat &= ~(1 << irqoffset);
}

2
drivers/gpio/gpio-mxs.c
View File

@ -157,7 +157,7 @@ static void mxs_gpio_irq_handler(struct irq_desc *desc)
if (port->both_edges & (1 << irqoffset))
mxs_flip_edge(port, irqoffset);
generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
generic_handle_domain_irq(port->domain, irqoffset);
irq_stat &= ~(1 << irqoffset);
}
}

3
drivers/gpio/gpio-omap.c
View File

@ -611,8 +611,7 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
bit));
generic_handle_domain_irq(bank->chip.irq.domain, bit);
raw_spin_unlock_irqrestore(&bank->wa_lock,
wa_lock_flags);

2
drivers/gpio/gpio-pci-idio-16.c
View File

@ -260,7 +260,7 @@ static irqreturn_t idio_16_irq_handler(int irq, void *dev_id)
return IRQ_NONE;
for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));
generic_handle_domain_irq(chip->irq.domain, gpio);
raw_spin_lock(&idio16gpio->lock);

3
drivers/gpio/gpio-pcie-idio-24.c
View File

@ -468,8 +468,7 @@ static irqreturn_t idio_24_irq_handler(int irq, void *dev_id)
irq_mask = idio24gpio->irq_mask & irq_status;
for_each_set_bit(gpio, &irq_mask, chip->ngpio - 24)
generic_handle_irq(irq_find_mapping(chip->irq.domain,
gpio + 24));
generic_handle_domain_irq(chip->irq.domain, gpio + 24);
raw_spin_lock(&idio24gpio->lock);

4
drivers/gpio/gpio-pl061.c
View File

@ -223,8 +223,8 @@ static void pl061_irq_handler(struct irq_desc *desc)
pending = readb(pl061->base + GPIOMIS);
if (pending) {
for_each_set_bit(offset, &pending, PL061_GPIO_NR)
generic_handle_irq(irq_find_mapping(gc->irq.domain,
offset));
generic_handle_domain_irq(gc->irq.domain,
offset);
}
chained_irq_exit(irqchip, desc);

9
drivers/gpio/gpio-pxa.c
View File

@ -455,9 +455,8 @@ static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
for_each_set_bit(n, &gedr, BITS_PER_LONG) {
loop = 1;
generic_handle_irq(
irq_find_mapping(pchip->irqdomain,
gpio + n));
generic_handle_domain_irq(pchip->irqdomain,
gpio + n);
}
}
handled += loop;
@ -471,9 +470,9 @@ static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
struct pxa_gpio_chip *pchip = d;
if (in_irq == pchip->irq0) {
generic_handle_irq(irq_find_mapping(pchip->irqdomain, 0));
generic_handle_domain_irq(pchip->irqdomain, 0);
} else if (in_irq == pchip->irq1) {
generic_handle_irq(irq_find_mapping(pchip->irqdomain, 1));
generic_handle_domain_irq(pchip->irqdomain, 1);
} else {
pr_err("%s() unknown irq %d\n", __func__, in_irq);
return IRQ_NONE;

4
drivers/gpio/gpio-rcar.c
View File

@ -213,8 +213,8 @@ static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
gpio_rcar_read(p, INTMSK))) {
offset = __ffs(pending);
gpio_rcar_write(p, INTCLR, BIT(offset));
generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
offset));
generic_handle_domain_irq(p->gpio_chip.irq.domain,
offset);
irqs_handled++;
}

8
drivers/gpio/gpio-rda.c
View File

@ -181,7 +181,7 @@ static void rda_gpio_irq_handler(struct irq_desc *desc)
struct irq_chip *ic = irq_desc_get_chip(desc);
struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
unsigned long status;
u32 n, girq;
u32 n;
chained_irq_enter(ic, desc);
@ -189,10 +189,8 @@ static void rda_gpio_irq_handler(struct irq_desc *desc)
/* Only lower 8 bits are capable of generating interrupts */
status &= RDA_GPIO_IRQ_MASK;
for_each_set_bit(n, &status, RDA_GPIO_BANK_NR) {
girq = irq_find_mapping(chip->irq.domain, n);
generic_handle_irq(girq);
}
for_each_set_bit(n, &status, RDA_GPIO_BANK_NR)
generic_handle_domain_irq(chip->irq.domain, n);
chained_irq_exit(ic, desc);
}

7
drivers/gpio/gpio-realtek-otto.c
View File

@ -196,7 +196,6 @@ static void realtek_gpio_irq_handler(struct irq_desc *desc)
struct irq_chip *irq_chip = irq_desc_get_chip(desc);
unsigned int lines_done;
unsigned int port_pin_count;
unsigned int irq;
unsigned long status;
int offset;
@ -205,10 +204,8 @@ static void realtek_gpio_irq_handler(struct irq_desc *desc)
for (lines_done = 0; lines_done < gc->ngpio; lines_done += 8) {
status = realtek_gpio_read_isr(ctrl, lines_done / 8);
port_pin_count = min(gc->ngpio - lines_done, 8U);
for_each_set_bit(offset, &status, port_pin_count) {
irq = irq_find_mapping(gc->irq.domain, offset);
generic_handle_irq(irq);
}
for_each_set_bit(offset, &status, port_pin_count)
generic_handle_domain_irq(gc->irq.domain, offset);
}
chained_irq_exit(irq_chip, desc);

2
drivers/gpio/gpio-sch.c
View File

@ -259,7 +259,7 @@ static u32 sch_gpio_gpe_handler(acpi_handle gpe_device, u32 gpe, void *context)
pending = (resume_status << sch->resume_base) | core_status;
for_each_set_bit(offset, &pending, sch->chip.ngpio)
generic_handle_irq(irq_find_mapping(gc->irq.domain, offset));
generic_handle_domain_irq(gc->irq.domain, offset);
/* Set returning value depending on whether we handled an interrupt */
ret = pending ? ACPI_INTERRUPT_HANDLED : ACPI_INTERRUPT_NOT_HANDLED;

2
drivers/gpio/gpio-sodaville.c
View File

@ -84,7 +84,7 @@ static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
return IRQ_NONE;
for_each_set_bit(irq_bit, &irq_stat, 32)
generic_handle_irq(irq_find_mapping(sd->id, irq_bit));
generic_handle_domain_irq(sd->id, irq_bit);
return IRQ_HANDLED;
}

12
drivers/gpio/gpio-sprd.c
View File

@ -189,7 +189,7 @@ static void sprd_gpio_irq_handler(struct irq_desc *desc)
struct gpio_chip *chip = irq_desc_get_handler_data(desc);
struct irq_chip *ic = irq_desc_get_chip(desc);
struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
u32 bank, n, girq;
u32 bank, n;
chained_irq_enter(ic, desc);
@ -198,13 +198,9 @@ static void sprd_gpio_irq_handler(struct irq_desc *desc)
unsigned long reg = readl_relaxed(base + SPRD_GPIO_MIS) &
SPRD_GPIO_BANK_MASK;
for_each_set_bit(n, &reg, SPRD_GPIO_BANK_NR) {
girq = irq_find_mapping(chip->irq.domain,
bank * SPRD_GPIO_BANK_NR + n);
generic_handle_irq(girq);
}
for_each_set_bit(n, &reg, SPRD_GPIO_BANK_NR)
generic_handle_domain_irq(chip->irq.domain,
bank * SPRD_GPIO_BANK_NR + n);
}
chained_irq_exit(ic, desc);
}

2
drivers/gpio/gpio-tb10x.c
View File

@ -100,7 +100,7 @@ static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data)
int i;
for_each_set_bit(i, &bits, 32)
generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));
generic_handle_domain_irq(tb10x_gpio->domain, i);
return IRQ_HANDLED;
}

9
drivers/gpio/gpio-tegra.c
View File

@ -408,6 +408,8 @@ static void tegra_gpio_irq_handler(struct irq_desc *desc)
lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
for_each_set_bit(pin, &sta, 8) {
int ret;
tegra_gpio_writel(tgi, 1 << pin,
GPIO_INT_CLR(tgi, gpio));
@ -420,11 +422,8 @@ static void tegra_gpio_irq_handler(struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
irq = irq_find_mapping(domain, gpio + pin);
if (WARN_ON(irq == 0))
continue;
generic_handle_irq(irq);
ret = generic_handle_domain_irq(domain, gpio + pin);
WARN_RATELIMIT(ret, "hwirq = %d", gpio + pin);
}
}

9
drivers/gpio/gpio-tegra186.c
View File

@ -456,7 +456,7 @@ static void tegra186_gpio_irq(struct irq_desc *desc)
for (i = 0; i < gpio->soc->num_ports; i++) {
const struct tegra_gpio_port *port = &gpio->soc->ports[i];
unsigned int pin, irq;
unsigned int pin;
unsigned long value;
void __iomem *base;
@ -469,11 +469,8 @@ static void tegra186_gpio_irq(struct irq_desc *desc)
value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
for_each_set_bit(pin, &value, port->pins) {
irq = irq_find_mapping(domain, offset + pin);
if (WARN_ON(irq == 0))
continue;
generic_handle_irq(irq);
int ret = generic_handle_domain_irq(domain, offset + pin);
WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
}
skip:

10
drivers/gpio/gpio-tqmx86.c
View File

@ -183,7 +183,7 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc)
struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
struct irq_chip *irq_chip = irq_desc_get_chip(desc);
unsigned long irq_bits;
int i = 0, child_irq;
int i = 0;
u8 irq_status;
chained_irq_enter(irq_chip, desc);
@ -192,11 +192,9 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc)
tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
irq_bits = irq_status;
for_each_set_bit(i, &irq_bits, TQMX86_NGPI) {
child_irq = irq_find_mapping(gpio->chip.irq.domain,
i + TQMX86_NGPO);
generic_handle_irq(child_irq);
}
for_each_set_bit(i, &irq_bits, TQMX86_NGPI)
generic_handle_domain_irq(gpio->chip.irq.domain,
i + TQMX86_NGPO);
chained_irq_exit(irq_chip, desc);
}

2
drivers/gpio/gpio-vf610.c
View File

@ -149,7 +149,7 @@ static void vf610_gpio_irq_handler(struct irq_desc *desc)
for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin));
generic_handle_domain_irq(port->gc.irq.domain, pin);
}
chained_irq_exit(chip, desc);

4
drivers/gpio/gpio-ws16c48.c
View File

@ -339,8 +339,8 @@ static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
for_each_set_bit(port, &int_pending, 3) {
int_id = inb(ws16c48gpio->base + 8 + port);
for_each_set_bit(gpio, &int_id, 8)
generic_handle_irq(irq_find_mapping(
chip->irq.domain, gpio + 8*port));
generic_handle_domain_irq(chip->irq.domain,
gpio + 8*port);
}
int_pending = inb(ws16c48gpio->base + 6) & 0x7;

2
drivers/gpio/gpio-xgs-iproc.c
View File

@ -185,7 +185,7 @@ static irqreturn_t iproc_gpio_irq_handler(int irq, void *data)
int_bits = level | event;
for_each_set_bit(bit, &int_bits, gc->ngpio)
generic_handle_irq(irq_linear_revmap(gc->irq.domain, bit));
generic_handle_domain_irq(gc->irq.domain, bit);
}
return int_bits ? IRQ_HANDLED : IRQ_NONE;

2
drivers/gpio/gpio-xilinx.c
View File

@ -538,7 +538,7 @@ static void xgpio_irqhandler(struct irq_desc *desc)
for_each_set_bit(bit, all, 64) {
irq_offset = xgpio_from_bit(chip, bit);
generic_handle_irq(irq_find_mapping(gc->irq.domain, irq_offset));
generic_handle_domain_irq(gc->irq.domain, irq_offset);
}
chained_irq_exit(irqchip, desc);

3
drivers/gpio/gpio-xlp.c
View File

@ -216,8 +216,7 @@ static void xlp_gpio_generic_handler(struct irq_desc *desc)
}
if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
generic_handle_irq(irq_find_mapping(
priv->chip.irq.domain, gpio));
generic_handle_domain_irq(priv->chip.irq.domain, gpio);
}
chained_irq_exit(irqchip, desc);
}

8
drivers/gpio/gpio-zynq.c
View File

@ -628,12 +628,8 @@ static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
if (!pending)
return;
for_each_set_bit(offset, &pending, 32) {
unsigned int gpio_irq;
gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
generic_handle_irq(gpio_irq);
}
for_each_set_bit(offset, &pending, 32)
generic_handle_domain_irq(irqdomain, offset + bank_offset);
}
/**

2
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
View File

@ -502,7 +502,7 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,
} else if ((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) &&
adev->irq.virq[src_id]) {
generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
generic_handle_domain_irq(adev->irq.domain, src_id);
} else if (!adev->irq.client[client_id].sources) {
DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",

15
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
View File

@ -45,20 +45,13 @@ static void dpu_mdss_irq(struct irq_desc *desc)
while (interrupts) {
irq_hw_number_t hwirq = fls(interrupts) - 1;
unsigned int mapping;
int rc;
mapping = irq_find_mapping(dpu_mdss->irq_controller.domain,
hwirq);
if (mapping == 0) {
DRM_ERROR("couldn't find irq mapping for %lu\n", hwirq);
break;
}
rc = generic_handle_irq(mapping);
rc = generic_handle_domain_irq(dpu_mdss->irq_controller.domain,
hwirq);
if (rc < 0) {
DRM_ERROR("handle irq fail: irq=%lu mapping=%u rc=%d\n",
hwirq, mapping, rc);
DRM_ERROR("handle irq fail: irq=%lu rc=%d\n",
hwirq, rc);
break;
}

3
drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
View File

@ -50,8 +50,7 @@ static irqreturn_t mdss_irq(int irq, void *arg)
while (intr) {
irq_hw_number_t hwirq = fls(intr) - 1;
generic_handle_irq(irq_find_mapping(
mdp5_mdss->irqcontroller.domain, hwirq));
generic_handle_domain_irq(mdp5_mdss->irqcontroller.domain, hwirq);
intr &= ~(1 << hwirq);
}

11
drivers/gpu/ipu-v3/ipu-common.c
View File

@ -1003,19 +1003,16 @@ static int ipu_submodules_init(struct ipu_soc *ipu,
static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
{
unsigned long status;
int i, bit, irq;
int i, bit;
for (i = 0; i < num_regs; i++) {
status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
for_each_set_bit(bit, &status, 32) {
irq = irq_linear_revmap(ipu->domain,
regs[i] * 32 + bit);
if (irq)
generic_handle_irq(irq);
}
for_each_set_bit(bit, &status, 32)
generic_handle_domain_irq(ipu->domain,
regs[i] * 32 + bit);
}
}

2
drivers/mfd/db8500-prcmu.c
View File

@ -2364,7 +2364,7 @@ static bool read_mailbox_0(void)
for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
if (ev & prcmu_irq_bit[n])
generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));
generic_handle_domain_irq(db8500_irq_domain, n);
}
r = true;
break;

4
drivers/mfd/fsl-imx25-tsadc.c
View File

@ -35,10 +35,10 @@ static void mx25_tsadc_irq_handler(struct irq_desc *desc)
regmap_read(tsadc->regs, MX25_TSC_TGSR, &status);
if (status & MX25_TGSR_GCQ_INT)
generic_handle_irq(irq_find_mapping(tsadc->domain, 1));
generic_handle_domain_irq(tsadc->domain, 1);
if (status & MX25_TGSR_TCQ_INT)
generic_handle_irq(irq_find_mapping(tsadc->domain, 0));
generic_handle_domain_irq(tsadc->domain, 0);
chained_irq_exit(chip, desc);
}

10
drivers/mfd/ioc3.c
View File

@ -105,19 +105,15 @@ static void ioc3_irq_handler(struct irq_desc *desc)
struct ioc3_priv_data *ipd = domain->host_data;
struct ioc3 __iomem *regs = ipd->regs;
u32 pending, mask;
unsigned int irq;
pending = readl(&regs->sio_ir);
mask = readl(&regs->sio_ies);
pending &= mask; /* Mask off not enabled interrupts */
if (pending) {
irq = irq_find_mapping(domain, __ffs(pending));
if (irq)
generic_handle_irq(irq);
} else {
if (pending)
generic_handle_domain_irq(domain, __ffs(pending));
else
spurious_interrupt();
}
}
/*

10
drivers/mfd/qcom-pm8xxx.c
View File

@ -122,7 +122,7 @@ pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
{
int pmirq, irq, i, ret = 0;
int pmirq, i, ret = 0;
unsigned int bits;
ret = pm8xxx_read_block_irq(chip, block, &bits);
@ -139,8 +139,7 @@ static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
for (i = 0; i < 8; i++) {
if (bits & (1 << i)) {
pmirq = block * 8 + i;
irq = irq_find_mapping(chip->irqdomain, pmirq);
generic_handle_irq(irq);
generic_handle_domain_irq(chip->irqdomain, pmirq);
}
}
return 0;
@ -199,7 +198,7 @@ static void pm8xxx_irq_handler(struct irq_desc *desc)
static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
int master, int block)
{
int pmirq, irq, i, ret;
int pmirq, i, ret;
unsigned int bits;
ret = regmap_read(chip->regmap,
@ -216,8 +215,7 @@ static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
for (i = 0; i < 8; i++) {
if (bits & BIT(i)) {
pmirq = block * 8 + i;
irq = irq_find_mapping(chip->irqdomain, pmirq);
generic_handle_irq(irq);
generic_handle_domain_irq(chip->irqdomain, pmirq);
}
}
}

5
drivers/pinctrl/actions/pinctrl-owl.c
View File

@ -833,7 +833,7 @@ static void owl_gpio_irq_handler(struct irq_desc *desc)
unsigned int parent = irq_desc_get_irq(desc);
const struct owl_gpio_port *port;
void __iomem *base;
unsigned int pin, irq, offset = 0, i;
unsigned int pin, offset = 0, i;
unsigned long pending_irq;
chained_irq_enter(chip, desc);
@ -849,8 +849,7 @@ static void owl_gpio_irq_handler(struct irq_desc *desc)
pending_irq = readl_relaxed(base + port->intc_pd);
for_each_set_bit(pin, &pending_irq, port->pins) {
irq = irq_find_mapping(domain, offset + pin);
generic_handle_irq(irq);
generic_handle_domain_irq(domain, offset + pin);
/* clear pending interrupt */
owl_gpio_update_reg(base + port->intc_pd, pin, true);

4
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View File

@ -395,8 +395,8 @@ static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
events &= pc->enabled_irq_map[bank];
for_each_set_bit(offset, &events, 32) {
gpio = (32 * bank) + offset;
generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
gpio));
generic_handle_domain_irq(pc->gpio_chip.irq.domain,
gpio);
}
}

3
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
View File

@ -176,7 +176,6 @@ static void iproc_gpio_irq_handler(struct irq_desc *desc)
for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
unsigned pin = NGPIOS_PER_BANK * i + bit;
int child_irq = irq_find_mapping(gc->irq.domain, pin);
/*
* Clear the interrupt before invoking the
@ -185,7 +184,7 @@ static void iproc_gpio_irq_handler(struct irq_desc *desc)
writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
IPROC_GPIO_INT_CLR_OFFSET);
generic_handle_irq(child_irq);
generic_handle_domain_irq(gc->irq.domain, pin);
}
}

3
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
View File

@ -155,8 +155,7 @@ static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
int_bits = level | event;
for_each_set_bit(bit, &int_bits, gc->ngpio)
generic_handle_irq(
irq_linear_revmap(gc->irq.domain, bit));
generic_handle_domain_irq(gc->irq.domain, bit);
}
return int_bits ? IRQ_HANDLED : IRQ_NONE;

7
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -1444,7 +1444,6 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
u32 base, pin;
void __iomem *reg;
unsigned long pending;
unsigned int virq;
/* check from GPIO controller which pin triggered the interrupt */
for (base = 0; base < vg->chip.ngpio; base += 32) {
@ -1460,10 +1459,8 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
raw_spin_lock(&byt_lock);
pending = readl(reg);
raw_spin_unlock(&byt_lock);
for_each_set_bit(pin, &pending, 32) {
virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
generic_handle_irq(virq);
}
for_each_set_bit(pin, &pending, 32)
generic_handle_domain_irq(vg->chip.irq.domain, base + pin);
}
chip->irq_eoi(data);
}

5
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -1409,11 +1409,10 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
raw_spin_unlock_irqrestore(&chv_lock, flags);
for_each_set_bit(intr_line, &pending, community->nirqs) {
unsigned int irq, offset;
unsigned int offset;
offset = cctx->intr_lines[intr_line];
irq = irq_find_mapping(gc->irq.domain, offset);
generic_handle_irq(irq);
generic_handle_domain_irq(gc->irq.domain, offset);
}
chained_irq_exit(chip, desc);

8
drivers/pinctrl/intel/pinctrl-lynxpoint.c
View File

@ -653,12 +653,8 @@ static void lp_gpio_irq_handler(struct irq_desc *desc)
/* Only interrupts that are enabled */
pending = ioread32(reg) & ioread32(ena);
for_each_set_bit(pin, &pending, 32) {
unsigned int irq;
irq = irq_find_mapping(lg->chip.irq.domain, base + pin);
generic_handle_irq(irq);
}
for_each_set_bit(pin, &pending, 32)
generic_handle_domain_irq(lg->chip.irq.domain, base + pin);
}
chip->irq_eoi(data);
}

5
drivers/pinctrl/mediatek/mtk-eint.c
View File

@ -319,7 +319,7 @@ static void mtk_eint_irq_handler(struct irq_desc *desc)
struct irq_chip *chip = irq_desc_get_chip(desc);
struct mtk_eint *eint = irq_desc_get_handler_data(desc);
unsigned int status, eint_num;
int offset, mask_offset, index, virq;
int offset, mask_offset, index;
void __iomem *reg = mtk_eint_get_offset(eint, 0, eint->regs->stat);
int dual_edge, start_level, curr_level;
@ -331,7 +331,6 @@ static void mtk_eint_irq_handler(struct irq_desc *desc)
offset = __ffs(status);
mask_offset = eint_num >> 5;
index = eint_num + offset;
virq = irq_find_mapping(eint->domain, index);
status &= ~BIT(offset);
/*
@ -361,7 +360,7 @@ static void mtk_eint_irq_handler(struct irq_desc *desc)
index);
}
generic_handle_irq(virq);
generic_handle_domain_irq(eint->domain, index);
if (dual_edge) {
curr_level = mtk_eint_flip_edge(eint, index);

2
drivers/pinctrl/nomadik/pinctrl-nomadik.c
View File

@ -815,7 +815,7 @@ static void nmk_gpio_irq_handler(struct irq_desc *desc)
while (status) {
int bit = __ffs(status);
generic_handle_irq(irq_find_mapping(chip->irq.domain, bit));
generic_handle_domain_irq(chip->irq.domain, bit);
status &= ~BIT(bit);
}

2
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
View File

@ -231,7 +231,7 @@ static void npcmgpio_irq_handler(struct irq_desc *desc)
sts &= en;
for_each_set_bit(bit, (const void *)&sts, NPCM7XX_GPIO_PER_BANK)
generic_handle_irq(irq_linear_revmap(gc->irq.domain, bit));
generic_handle_domain_irq(gc->irq.domain, bit);
chained_irq_exit(chip, desc);
}

6
drivers/pinctrl/pinctrl-amd.c
View File

@ -621,14 +621,12 @@ static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
if (!(regval & PIN_IRQ_PENDING) ||
!(regval & BIT(INTERRUPT_MASK_OFF)))
continue;
irq = irq_find_mapping(gc->irq.domain, irqnr + i);
if (irq != 0)
generic_handle_irq(irq);
generic_handle_domain_irq(gc->irq.domain, irqnr + i);
/* Clear interrupt.
* We must read the pin register again, in case the
* value was changed while executing
* generic_handle_irq() above.
* generic_handle_domain_irq() above.
* If we didn't find a mapping for the interrupt,
* disable it in order to avoid a system hang caused
* by an interrupt storm.

6
drivers/pinctrl/pinctrl-at91.c
View File

@ -1712,10 +1712,8 @@ static void gpio_irq_handler(struct irq_desc *desc)
continue;
}
for_each_set_bit(n, &isr, BITS_PER_LONG) {
generic_handle_irq(irq_find_mapping(
gpio_chip->irq.domain, n));
}
for_each_set_bit(n, &isr, BITS_PER_LONG)
generic_handle_domain_irq(gpio_chip->irq.domain, n);
}
chained_irq_exit(chip, desc);
/* now it may re-trigger */

2
drivers/pinctrl/pinctrl-equilibrium.c
View File

@ -155,7 +155,7 @@ static void eqbr_irq_handler(struct irq_desc *desc)
pins = readl(gctrl->membase + GPIO_IRNCR);
for_each_set_bit(offset, &pins, gc->ngpio)
generic_handle_irq(irq_find_mapping(gc->irq.domain, offset));
generic_handle_domain_irq(gc->irq.domain, offset);
chained_irq_exit(ic, desc);
}

2
drivers/pinctrl/pinctrl-ingenic.c
View File

@ -3080,7 +3080,7 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc)
flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR);
for_each_set_bit(i, &flag, 32)
generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
generic_handle_domain_irq(gc->irq.domain, i);
chained_irq_exit(irq_chip, desc);
}

2
drivers/pinctrl/pinctrl-microchip-sgpio.c
View File

@ -673,7 +673,7 @@ static void sgpio_irq_handler(struct irq_desc *desc)
for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) {
gpio = sgpio_addr_to_pin(priv, port, bit);
generic_handle_irq(irq_linear_revmap(chip->irq.domain, gpio));
generic_handle_domain_irq(chip->irq.domain, gpio);
}
chained_irq_exit(parent_chip, desc);

3
drivers/pinctrl/pinctrl-ocelot.c
View File

@ -1290,8 +1290,7 @@ static void ocelot_irq_handler(struct irq_desc *desc)
for_each_set_bit(irq, &irqs,
min(32U, info->desc->npins - 32 * i))
generic_handle_irq(irq_linear_revmap(chip->irq.domain,
irq + 32 * i));
generic_handle_domain_irq(chip->irq.domain, irq + 32 * i);
chained_irq_exit(parent_chip, desc);
}

2
drivers/pinctrl/pinctrl-oxnas.c
View File

@ -1055,7 +1055,7 @@ static void oxnas_gpio_irq_handler(struct irq_desc *desc)
stat = readl(bank->reg_base + IRQ_PENDING);
for_each_set_bit(pin, &stat, BITS_PER_LONG)
generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
generic_handle_domain_irq(gc->irq.domain, pin);
chained_irq_exit(chip, desc);
}

2
drivers/pinctrl/pinctrl-pic32.c
View File

@ -2101,7 +2101,7 @@ static void pic32_gpio_irq_handler(struct irq_desc *desc)
pending = pic32_gpio_get_pending(gc, stat);
for_each_set_bit(pin, &pending, BITS_PER_LONG)
generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
generic_handle_domain_irq(gc->irq.domain, pin);
chained_irq_exit(chip, desc);
}

2
drivers/pinctrl/pinctrl-pistachio.c
View File

@ -1306,7 +1306,7 @@ static void pistachio_gpio_irq_handler(struct irq_desc *desc)
pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) &
gpio_readl(bank, GPIO_INTERRUPT_EN);
for_each_set_bit(pin, &pending, 16)
generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
generic_handle_domain_irq(gc->irq.domain, pin);
chained_irq_exit(chip, desc);
}

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