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arm64: dts: mediatek: mt8395-nio-12l: Enable PHYs and USB role switch

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Enable the PCIe0 PHY to be able to set calibrations read from eFuses,
improving the stability and performance of the PCIe link.

While at it, also enable the T-PHYs for both PCIe1 and for USB, allowing
the USB ports to finally switch to gadget mode if needed, and configure
the VBUS/ID pins of both USB ports for the same.

Link: https://lore.kernel.org/r/20240409114211.310462-5-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
AngeloGioacchino Del Regno 2024-04-09 13:42:10 +02:00
parent 048a70e314
commit 9af4238590
No known key found for this signature in database
GPG Key ID: 9A3604CFAD978478
1 changed files with 40 additions and 0 deletions
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40
arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
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@ -685,6 +685,26 @@ pins-bus {
};
};
usb3_port0_pins: usb3p0-default-pins {
pins-vbus {
pinmux = <PINMUX_GPIO63__FUNC_VBUSVALID>;
input-enable;
};
};
usb2_port0_pins: usb2p0-default-pins {
pins-iddig {
pinmux = <PINMUX_GPIO130__FUNC_IDDIG_1P>;
input-enable;
bias-pull-up;
};
pins-vbus {
pinmux = <PINMUX_GPIO131__FUNC_USB_DRVVBUS_1P>;
output-low;
};
};
wifi_vreg_pins: wifi-vreg-pins {
pins-wifi-pmu-en {
pinmux = <PINMUX_GPIO65__FUNC_GPIO65>;
@ -709,6 +729,10 @@ &pcie1 {
status = "okay";
};
&pciephy {
status = "okay";
};
&pmic {
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
};
@ -776,6 +800,18 @@ mt6315_7_vbuck1: vbuck1 {
};
};
&u3phy0 {
status = "okay";
};
&u3phy1 {
status = "okay";
};
&u3phy2 {
status = "okay";
};
&uart0 {
/* Exposed at 40 pin connector */
pinctrl-0 = <&uart0_pins>;
@ -791,6 +827,8 @@ &uart1 {
};
&ssusb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb3_port0_pins>;
role-switch-default-mode = "host";
usb-role-switch;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
@ -804,6 +842,8 @@ mtu3_hs0_role_sw: endpoint {
};
&ssusb2 {
pinctrl-names = "default";
pinctrl-0 = <&usb2_port0_pins>;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};