From 468238ced6c39dd4927392f16cedcde5f27cd0ef Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Thu, 4 Jun 2026 21:48:01 +0800 Subject: [PATCH 1/5] clk: imx: Add audio PLL debugfs for K-divider control Add debugfs support for runtime tuning of the audio PLL K divider, which enables fine-grained frequency adjustments for audio PLL. This is used for: - Audio clock calibration and testing - Debugging audio synchronization issues Two debug interfaces are exported to userspace: - delta_k: It is used to adjust the K divider in PLL based on small steps - pll_parameter: It is used for get PLL's current M-divider, P-divider, S-divider & K-divider setting in PLL register Signed-off-by: Jacky Bai Reviewed-by: Peng Fan Reviewed-by: Abel Vesa Link: https://patch.msgid.link/20260604-imx8m_pll_debugfs-v3-1-4e331ebc85d7@nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8mm.c | 6 ++ drivers/clk/imx/clk-pll14xx.c | 119 +++++++++++++++++++++++++++++++++- drivers/clk/imx/clk.h | 1 + 3 files changed, 125 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 319af4deec01..89d442415a01 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -300,6 +300,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; + struct clk_hw *audio_pll_hws[2]; void __iomem *base; int ret; @@ -610,6 +611,11 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) imx_register_uart_clocks(); + /* Add debug interface for audio PLLs */ + audio_pll_hws[0] = hws[IMX8MM_AUDIO_PLL1]; + audio_pll_hws[1] = hws[IMX8MM_AUDIO_PLL2]; + imx_audio_pll_debug_init(audio_pll_hws, ARRAY_SIZE(audio_pll_hws)); + return 0; unregister_hws: diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 39600ee22be3..b6f1cc9f5700 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -8,11 +8,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include "clk.h" @@ -40,6 +42,8 @@ struct clk_pll14xx { enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; int rate_count; + s16 delta_k; + spinlock_t lock; }; #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw) @@ -134,6 +138,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat u32 pll_div_ctl0, pll_div_ctl1; int mdiv, pdiv, sdiv, kdiv; long fout, rate_min, rate_max, dist, best = LONG_MAX; + unsigned long flags; const struct imx_pll14xx_rate_table *tt; /* @@ -161,11 +166,16 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat return; } + spin_lock_irqsave(&pll->lock, flags); + pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); + + spin_unlock_irqrestore(&pll->lock, flags); + mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0); - pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); /* Then see if we can get the desired rate by only adjusting kdiv (glitch free) */ rate_min = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MIN, prate); @@ -361,11 +371,14 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, { struct clk_pll14xx *pll = to_clk_pll14xx(hw); struct imx_pll14xx_rate_table rate; + unsigned long flags; u32 gnrl_ctl, div_ctl0; int ret; imx_pll14xx_calc_settings(pll, drate, prate, &rate); + spin_lock_irqsave(&pll->lock, flags); + div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); if (!clk_pll14xx_mp_change(&rate, div_ctl0)) { @@ -377,6 +390,8 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); + spin_unlock_irqrestore(&pll->lock, flags); + return 0; } @@ -396,6 +411,8 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); + spin_unlock_irqrestore(&pll->lock, flags); + /* * According to SPEC, t3 - t2 need to be greater than * 1us and 1/FREF, respectively. @@ -508,6 +525,8 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, if (!pll) return ERR_PTR(-ENOMEM); + spin_lock_init(&pll->lock); + init.name = name; init.flags = pll_clk->flags; init.parent_names = &parent_name; @@ -551,3 +570,101 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, return hw; } EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx); + +/* + * Debugfs interface for Audio PLL runtime monitoring and control + * + * This interface allows dynamic adjustment of the Audio PLL + * K-divider for precise frequency tuning, particularly useful + * for audio applications. + * + * examples for the usage of the two interfaces: + * 1): Get the current PLL setting of dividers + * cat /sys/kernel/debug/audio_pll_monitor/audio_pll1/pll_parameter + * + * 2): Adjust the K-divider by a small delta_k + * echo 1 > /sys/kernel/debug/audio_pll_monitor/audio_pll1/delta_k; + */ +#ifdef CONFIG_DEBUG_FS +static int pll_delta_k_get(void *data, u64 *val) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(data); + *val = pll->delta_k; + return 0; +} + +static int pll_delta_k_set(void *data, u64 val) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(data); + unsigned long flags; + u32 div_ctl1; + s16 kdiv, delta_k; + + delta_k = (s16)clamp_t(s64, val, KDIV_MIN, KDIV_MAX); + + spin_lock_irqsave(&pll->lock, flags); + + pll->delta_k = delta_k; + + div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); + kdiv = (s16)FIELD_GET(KDIV_MASK, div_ctl1); + kdiv = (s16)clamp_t(s32, (s32)kdiv + delta_k, KDIV_MIN, KDIV_MAX); + writel_relaxed(FIELD_PREP(KDIV_MASK, kdiv), pll->base + DIV_CTL1); + + spin_unlock_irqrestore(&pll->lock, flags); + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(delta_k_fops, pll_delta_k_get, pll_delta_k_set, "%lld\n"); + +static int pll_setting_show(struct seq_file *s, void *data) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(s->private); + unsigned long flags; + u32 div_ctl0, div_ctl1; + u32 mdiv, pdiv, sdiv, kdiv; + + spin_lock_irqsave(&pll->lock, flags); + + div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); + + spin_unlock_irqrestore(&pll->lock, flags); + + mdiv = FIELD_GET(MDIV_MASK, div_ctl0); + pdiv = FIELD_GET(PDIV_MASK, div_ctl0); + sdiv = FIELD_GET(SDIV_MASK, div_ctl0); + kdiv = FIELD_GET(KDIV_MASK, div_ctl1); + + seq_printf(s, "Mdiv: 0x%x; Pdiv: 0x%x; Sdiv: 0x%x; Kdiv: 0x%x\n", + mdiv, pdiv, sdiv, kdiv); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(pll_setting); + +void imx_audio_pll_debug_init(struct clk_hw *hws[], unsigned int num_plls) +{ + struct dentry *rootdir, *audio_pll_dir; + const char *pll_name; + int i; + + rootdir = debugfs_create_dir("audio_pll_monitor", NULL); + + for (i = 0; i < num_plls; i++) { + if (!IS_ERR_OR_NULL(hws[i])) { + pll_name = clk_hw_get_name(hws[i]); + audio_pll_dir = debugfs_create_dir(pll_name, rootdir); + debugfs_create_file_unsafe("delta_k", 0600, audio_pll_dir, + hws[i], &delta_k_fops); + debugfs_create_file("pll_parameter", 0444, audio_pll_dir, + hws[i], &pll_setting_fops); + } + } +} +#else /* !CONFIG_DEBUG_FS */ +void imx_audio_pll_debug_init(struct clk_hw *hws[], unsigned int num_plls) +{ +} +#endif /* CONFIG_DEBUG_FS */ +EXPORT_SYMBOL_GPL(imx_audio_pll_debug_init); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index aa5202f284f3..40bb41e353f9 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -487,4 +487,5 @@ struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible, u32 reg, const char **parent_names, u8 num_parents, const u32 *mux_table, u32 mask); +void imx_audio_pll_debug_init(struct clk_hw *hws[], unsigned int num_plls); #endif From e89485455ac49925565061733c0d73d568333fc0 Mon Sep 17 00:00:00 2001 From: Pengpeng Hou Date: Sat, 4 Jul 2026 23:01:41 +0800 Subject: [PATCH 2/5] clk: imx: imx8qxp-lpcg: add missing MODULE_DEVICE_TABLE() The driver has a match table for the of bus wired into its driver structure, but the table is not exported with MODULE_DEVICE_TABLE(). Add the missing MODULE_DEVICE_TABLE() entry so module alias information is generated for automatic module loading. This is a source-level fix. It does not claim dynamic hardware reproduction; the evidence is the driver-owned match table, its use by the driver registration structure, and the missing module alias publication. Signed-off-by: Pengpeng Hou Reviewed-by: Frank Li Reviewed-by: Brian Masney Reviewed-by: Peng Fan Link: https://patch.msgid.link/20260704150344.59563-1-pengpeng@iscas.ac.cn Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8qxp-lpcg.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c index 1dae3410ee99..f0cf6cf91899 100644 --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c @@ -354,6 +354,7 @@ static const struct of_device_id imx8qxp_lpcg_match[] = { { .compatible = "fsl,imx8qxp-lpcg", NULL }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, imx8qxp_lpcg_match); static struct platform_driver imx8qxp_lpcg_clk_driver = { .driver = { From cd21fdcbef3fb32136f72075ab668b075423b3f6 Mon Sep 17 00:00:00 2001 From: Pengpeng Hou Date: Sun, 5 Jul 2026 08:17:05 +0800 Subject: [PATCH 3/5] clk: imx: imx8qxp: add missing MODULE_DEVICE_TABLE() The driver has a match table for the of bus wired into its driver structure, but the table is not exported with MODULE_DEVICE_TABLE(). Add the missing MODULE_DEVICE_TABLE() entry so module alias information is generated for automatic module loading. This is a source-level fix. It does not claim dynamic hardware reproduction; the evidence is the driver-owned match table, its use by the driver registration structure, and the missing module alias publication. Signed-off-by: Pengpeng Hou Reviewed-by: Brian Masney Link: https://patch.msgid.link/20260705001705.70400-1-pengpeng@iscas.ac.cn Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8qxp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index c781425a005e..1f6d9f45dad7 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -337,6 +337,7 @@ static const struct of_device_id imx8qxp_match[] = { { .compatible = "fsl,imx8qm-clk", &imx_clk_scu_rsrc_imx8qm, }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, imx8qxp_match); static struct platform_driver imx8qxp_clk_driver = { .driver = { From 884dfb2dfe2cde33b8efe91ebf91542c88ca9034 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 30 Jul 2026 16:55:42 +0800 Subject: [PATCH 4/5] clk: imx95-blk-ctl: Add func_out_en clock for i.MX9x PCIe Add a func_out_en clock for i.MX9x PCIe to serve as the parent gate clock of the CREF_EN (BIT6) gate clock. Both of these two gate clocks enable the output of the internal 100MHz differential reference clock. When the internal PLL clock is used as the PCIe reference clock, both BIT6 (CREF_EN) and BIT2 (FUNC_OUTPUT_EN) control the PCIE_REF_OUT_CLK. If these bits default to 1, the output clock is enabled. With typical 100-ohm termination on the board, this results in approximately 6mA of unnecessary power consumption when the PCIe internal PLL clock is not in use. To eliminate this power consumption, add a func_out_en clock gate that serves as the parent of the existing CREF_EN (BIT6) gate clock. Both gates must be enabled to output the internal 100MHz differential reference clock, and both will be disabled when the clock is not needed. Signed-off-by: Richard Zhu Reviewed-by: Peng Fan Link: https://patch.msgid.link/20260730085542.263025-1-hongxing.zhu@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx95-blk-ctl.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c index 56bed4471995..1f9259f45607 100644 --- a/drivers/clk/imx/clk-imx95-blk-ctl.c +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c @@ -286,18 +286,28 @@ static const struct imx95_blk_ctl_dev_data netcmix_dev_data = { static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = { [0] = { .name = "hsio_blk_ctl_clk", - .parent_names = (const char *[]){ "hsio_pll", }, + .parent_names = (const char *[]){ "func_out_en", }, .num_parents = 1, .reg = 0, .bit_idx = 6, .bit_width = 1, .type = CLK_GATE, .flags = CLK_SET_RATE_PARENT, + }, + [1] = { + .name = "func_out_en", + .parent_names = (const char *[]){ "hsio_pll", }, + .num_parents = 1, + .reg = 0, + .bit_idx = 2, + .bit_width = 1, + .type = CLK_GATE, + .flags = CLK_SET_RATE_PARENT, } }; static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = { - .num_clks = 1, + .num_clks = ARRAY_SIZE(hsio_blk_ctl_clk_dev_data), .clk_dev_data = hsio_blk_ctl_clk_dev_data, .clk_reg_offset = 0, }; From 39ec460b56b26319d1f31b459e8be7ea34ae9c67 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 30 Jul 2026 17:04:47 +0800 Subject: [PATCH 5/5] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on i.MX95 When the internal PLL is used as the PCIe reference clock source on i.MX95, a REFCLK rise-fall time mismatch is observed during PCIe Gen1 compliance testing with the Lfast IO analyzer. Fix this issue by configuring the IREF_TX field to 0xF (15), which adjusts the transmitter current reference to meet the PCIe specification timing requirements. Signed-off-by: Richard Zhu Reviewed-by: Peng Fan Link: https://patch.msgid.link/20260730090447.271109-1-hongxing.zhu@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx95-blk-ctl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c index 1f9259f45607..bc6957299cec 100644 --- a/drivers/clk/imx/clk-imx95-blk-ctl.c +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c @@ -44,6 +44,8 @@ struct imx95_blk_ctl_clk_dev_data { const char * const *parent_names; u32 num_parents; u32 reg; + u32 reg_init_msk; + u32 reg_init_val; u32 bit_idx; u32 bit_width; u32 clk_type; @@ -289,6 +291,8 @@ static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = { .parent_names = (const char *[]){ "func_out_en", }, .num_parents = 1, .reg = 0, + .reg_init_msk = GENMASK(10, 7), + .reg_init_val = GENMASK(10, 7), .bit_idx = 6, .bit_width = 1, .type = CLK_GATE, @@ -410,6 +414,9 @@ static int imx95_bc_probe(struct platform_device *pdev) const struct imx95_blk_ctl_clk_dev_data *data = &bc->pdata->clk_dev_data[i]; void __iomem *reg = base + data->reg; + if (data->reg_init_msk) + writel((readl(reg) & ~data->reg_init_msk) | data->reg_init_val, reg); + if (data->type == CLK_MUX) { hws[i] = clk_hw_register_mux(dev, data->name, data->parent_names, data->num_parents, data->flags, reg,