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phy: rockchip: samsung-hdptx: Fix rate recalculation for 3.2GHz FRL

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rk_hdptx_phy_clk_calc_rate_from_pll_cfg() is currently unable to handle
cascade mode for the 3.2GHz FRL operating mode, as it relies solely on
LCPLL_LCVCO_MODE_EN_MASK to determinate the rate from the
rk_hdptx_frl_lcpll_cfg array.  Since there is no entry for this
particular rate, the function returns 0.

This is the only rate which requires LC_REF_CLK_SEL to be set in
GRF_HDPTX_CON0, hence extend the FRL matching accordingly.

Reported-by: Sashiko <sashiko-bot@kernel.org>
Closes: https://sashiko.dev/#/patchset/20260611-hdptx-clk-fixes-v3-0-67b1b0c00e16@collabora.com?part=1
Fixes: de5dba8331 ("phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support")
Tested-by: Diederik de Haas <diederik@cknow-tech.com>  # NanoPC-T6 LTS
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://patch.msgid.link/20260811-hdptx-clk-fixes-v6-4-75bca0ee5753@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Cristian Ciocaltea 2026-08-11 18:44:45 +03:00 committed by Vinod Koul
parent 229788526f
commit 9ac3daadb9
1 changed files with 24 additions and 9 deletions
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33
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
View File

@ -2206,16 +2206,31 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(struct rk_hdptx_phy *hdptx)
return 0;
lcpll_hw.sdc_n = (val & LCPLL_SDC_N_MASK) >> 1;
for (i = 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) {
const struct lcpll_config *cfg = &rk_hdptx_frl_lcpll_cfg[i];
ret = regmap_read(hdptx->grf, GRF_HDPTX_CON0, &val);
if (ret)
return 0;
if (cfg->pms_mdiv == lcpll_hw.pms_mdiv &&
cfg->pms_sdiv == lcpll_hw.pms_sdiv &&
cfg->sdm_num_sign == lcpll_hw.sdm_num_sign &&
cfg->sdm_num == lcpll_hw.sdm_num &&
cfg->sdm_deno == lcpll_hw.sdm_deno &&
cfg->sdc_n == lcpll_hw.sdc_n)
return cfg->rate;
if (val & LC_REF_CLK_SEL) {
if (lcpll_hw.pms_mdiv == 0x6b &&
lcpll_hw.sdm_num_sign == 0x01 &&
lcpll_hw.sdm_num == 0x02 &&
lcpll_hw.sdm_deno == 0x09 &&
lcpll_hw.sdc_n == FIELD_GET(LCPLL_SDC_N_MASK, 0x02))
return FRL_8G4L_RATE;
} else {
const struct lcpll_config *cfg;
for (i = 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) {
cfg = &rk_hdptx_frl_lcpll_cfg[i];
if (cfg->pms_mdiv == lcpll_hw.pms_mdiv &&
cfg->pms_sdiv == lcpll_hw.pms_sdiv &&
cfg->sdm_num_sign == lcpll_hw.sdm_num_sign &&
cfg->sdm_num == lcpll_hw.sdm_num &&
cfg->sdm_deno == lcpll_hw.sdm_deno &&
cfg->sdc_n == lcpll_hw.sdc_n)
return cfg->rate;
}
}
dev_dbg(hdptx->dev, "%s no FRL match found\n", __func__);