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drm/amd/powerplay: Enable SOCCLK ULV for sienna_cichlid

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Enable FW DSTATE for sienna_cichlid.
Enable DF CSTATE for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao 2020-03-06 17:01:22 +08:00 committed by Alex Deucher
parent 02bb391d91
commit 9aa6021340
1 changed files with 2 additions and 0 deletions
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drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
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@ -272,6 +272,8 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
| FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
| FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
| FEATURE_MASK(FEATURE_THERMAL_BIT);
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)