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drm/msm/adreno: add Adreno 810 GPU support
Add catalog entry and register configuration for the Adreno 810 found in Qualcomm SM7635 (Milos) based devices. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Signed-off-by: Alexander Koskovich <akoskovich@pm.me> Patchwork: https://patchwork.freedesktop.org/patch/728812/ Message-ID: <20260528-adreno-810-v7-6-7fe7fdd97fc2@pm.me> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
This commit is contained in:
Alexander Koskovich
Rob Clark
parent
c2c083bbe0
commit
9a96712542
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@ -1799,6 +1799,261 @@ static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = {
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};
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DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist);
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static const struct adreno_reglist_pipe a810_nonctxt_regs[] = {
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{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
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{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00f80800, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_1, 0x00000023, BIT(PIPE_BV) }, /* Avoid partial waves at VFD */
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{ REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
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/* Partially enable perf clear, Disable DINT to c/z be data forwarding */
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{ REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) },
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{ REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
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{ REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
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{ REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
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{ REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
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{ REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
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{ REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
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{ REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
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{ REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
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{ REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
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/*
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* BIT(22): Disable PS out of order retire
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* BIT(23): Enable half wave mode and MM instruction src&dst is half precision
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*/
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{ REG_A7XX_SP_CHICKEN_BITS_2, BIT(22) | BIT(23), BIT(PIPE_NONE) },
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{ REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
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{ REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
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{ REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
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{ REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) },
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{ REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000724, BIT(PIPE_NONE) },
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{ REG_A6XX_UCHE_MODE_CNTL, 0x00020000, BIT(PIPE_NONE) },
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{ REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
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{ REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
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/* Disable write slow pointer in data phase queue */
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{ REG_A8XX_UCHE_HW_DBG_CNTL, BIT(8), BIT(PIPE_NONE) },
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{ REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
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{ REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00100020, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_RB_GC_GMEM_PROTECT, 0x00900000, BIT(PIPE_BR) },
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{ },
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};
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static const u32 a810_protect_regs[] = {
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A6XX_PROTECT_RDONLY(0x00000, 0x03a3),
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A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
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A6XX_PROTECT_NORDWR(0x00440, 0x001f),
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A6XX_PROTECT_RDONLY(0x00580, 0x005f),
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A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
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A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
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A6XX_PROTECT_RDONLY(0x00759, 0x0026),
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A6XX_PROTECT_RDONLY(0x00789, 0x0000),
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A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
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A6XX_PROTECT_NORDWR(0x00800, 0x0029),
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A6XX_PROTECT_NORDWR(0x00837, 0x00af),
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A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
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A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
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A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
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A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
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A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
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A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
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A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
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A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
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A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
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A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff),
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A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
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A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
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A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
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A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
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A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
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A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
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A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
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A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
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A6XX_PROTECT_NORDWR(0x0ae00, 0x0006),
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A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
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A6XX_PROTECT_NORDWR(0x0ae10, 0x036f),
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A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
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A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
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A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
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A6XX_PROTECT_NORDWR(0x18400, 0x003f),
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A6XX_PROTECT_RDONLY(0x18440, 0x013f),
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A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
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A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
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A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
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A6XX_PROTECT_RDONLY(0x1f878, 0x0787),
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A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
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A6XX_PROTECT_NORDWR(0x20000, 0x1fff),
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A6XX_PROTECT_NORDWR(0x27800, 0x007f),
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A6XX_PROTECT_RDONLY(0x27880, 0x0381),
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A6XX_PROTECT_NORDWR(0x27882, 0x0001),
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A6XX_PROTECT_NORDWR(0x27c02, 0x0000),
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};
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DECLARE_ADRENO_PROTECT(a810_protect, 64);
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static const uint32_t a810_pwrup_reglist_regs[] = {
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REG_A6XX_UCHE_MODE_CNTL,
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REG_A8XX_UCHE_VARB_IDLE_TIMEOUT,
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REG_A8XX_UCHE_GBIF_GX_CONFIG,
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REG_A8XX_UCHE_CACHE_WAYS,
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REG_A8XX_UCHE_CCHE_MODE_CNTL,
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REG_A8XX_UCHE_CCHE_CACHE_WAYS,
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REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN,
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REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1,
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REG_A8XX_UCHE_CCHE_TRAP_BASE,
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REG_A8XX_UCHE_CCHE_TRAP_BASE + 1,
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REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE,
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REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1,
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REG_A8XX_UCHE_HW_DBG_CNTL,
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REG_A8XX_UCHE_WRITE_THRU_BASE,
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REG_A8XX_UCHE_WRITE_THRU_BASE + 1,
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REG_A8XX_UCHE_TRAP_BASE,
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REG_A8XX_UCHE_TRAP_BASE + 1,
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REG_A8XX_UCHE_CLIENT_PF,
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REG_A8XX_RB_CMP_NC_MODE_CNTL,
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REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP,
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REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN,
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REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1,
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REG_A7XX_SP_READ_SEL,
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REG_A6XX_TPL1_NC_MODE_CNTL,
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REG_A6XX_TPL1_DBG_ECO_CNTL,
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REG_A6XX_TPL1_DBG_ECO_CNTL1,
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18),
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REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19),
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};
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DECLARE_ADRENO_REGLIST_LIST(a810_pwrup_reglist);
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static const u32 a810_ifpc_reglist_regs[] = {
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REG_A8XX_RBBM_NC_MODE_CNTL,
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REG_A8XX_RBBM_PERFCTR_CNTL,
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REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL,
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REG_A8XX_RBBM_SLICE_NC_MODE_CNTL,
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REG_A6XX_SP_NC_MODE_CNTL,
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REG_A7XX_SP_CHICKEN_BITS_2,
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REG_A7XX_SP_CHICKEN_BITS_3,
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REG_A6XX_SP_PERFCTR_SHADER_MASK,
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REG_A8XX_CP_PROTECT_GLOBAL(0),
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REG_A8XX_CP_PROTECT_GLOBAL(1),
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REG_A8XX_CP_PROTECT_GLOBAL(2),
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REG_A8XX_CP_PROTECT_GLOBAL(3),
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REG_A8XX_CP_PROTECT_GLOBAL(4),
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REG_A8XX_CP_PROTECT_GLOBAL(5),
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REG_A8XX_CP_PROTECT_GLOBAL(6),
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REG_A8XX_CP_PROTECT_GLOBAL(7),
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REG_A8XX_CP_PROTECT_GLOBAL(8),
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REG_A8XX_CP_PROTECT_GLOBAL(9),
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REG_A8XX_CP_PROTECT_GLOBAL(10),
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REG_A8XX_CP_PROTECT_GLOBAL(11),
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REG_A8XX_CP_PROTECT_GLOBAL(12),
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REG_A8XX_CP_PROTECT_GLOBAL(13),
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REG_A8XX_CP_PROTECT_GLOBAL(14),
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REG_A8XX_CP_PROTECT_GLOBAL(15),
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REG_A8XX_CP_PROTECT_GLOBAL(16),
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REG_A8XX_CP_PROTECT_GLOBAL(17),
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REG_A8XX_CP_PROTECT_GLOBAL(18),
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REG_A8XX_CP_PROTECT_GLOBAL(19),
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REG_A8XX_CP_PROTECT_GLOBAL(20),
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REG_A8XX_CP_PROTECT_GLOBAL(21),
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REG_A8XX_CP_PROTECT_GLOBAL(22),
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REG_A8XX_CP_PROTECT_GLOBAL(23),
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REG_A8XX_CP_PROTECT_GLOBAL(24),
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REG_A8XX_CP_PROTECT_GLOBAL(25),
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REG_A8XX_CP_PROTECT_GLOBAL(26),
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REG_A8XX_CP_PROTECT_GLOBAL(27),
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REG_A8XX_CP_PROTECT_GLOBAL(28),
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REG_A8XX_CP_PROTECT_GLOBAL(29),
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REG_A8XX_CP_PROTECT_GLOBAL(30),
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REG_A8XX_CP_PROTECT_GLOBAL(31),
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REG_A8XX_CP_PROTECT_GLOBAL(32),
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REG_A8XX_CP_PROTECT_GLOBAL(33),
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REG_A8XX_CP_PROTECT_GLOBAL(34),
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REG_A8XX_CP_PROTECT_GLOBAL(35),
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REG_A8XX_CP_PROTECT_GLOBAL(36),
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REG_A8XX_CP_PROTECT_GLOBAL(37),
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REG_A8XX_CP_PROTECT_GLOBAL(38),
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REG_A8XX_CP_PROTECT_GLOBAL(39),
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REG_A8XX_CP_PROTECT_GLOBAL(40),
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REG_A8XX_CP_PROTECT_GLOBAL(41),
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REG_A8XX_CP_PROTECT_GLOBAL(42),
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REG_A8XX_CP_PROTECT_GLOBAL(43),
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REG_A8XX_CP_PROTECT_GLOBAL(44),
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REG_A8XX_CP_PROTECT_GLOBAL(45),
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REG_A8XX_CP_PROTECT_GLOBAL(46),
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REG_A8XX_CP_PROTECT_GLOBAL(47),
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REG_A8XX_CP_PROTECT_GLOBAL(48),
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REG_A8XX_CP_PROTECT_GLOBAL(49),
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REG_A8XX_CP_PROTECT_GLOBAL(50),
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REG_A8XX_CP_PROTECT_GLOBAL(51),
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REG_A8XX_CP_PROTECT_GLOBAL(52),
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REG_A8XX_CP_PROTECT_GLOBAL(53),
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REG_A8XX_CP_PROTECT_GLOBAL(54),
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REG_A8XX_CP_PROTECT_GLOBAL(55),
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REG_A8XX_CP_PROTECT_GLOBAL(56),
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REG_A8XX_CP_PROTECT_GLOBAL(57),
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REG_A8XX_CP_PROTECT_GLOBAL(58),
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REG_A8XX_CP_PROTECT_GLOBAL(59),
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REG_A8XX_CP_PROTECT_GLOBAL(60),
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REG_A8XX_CP_PROTECT_GLOBAL(61),
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REG_A8XX_CP_PROTECT_GLOBAL(62),
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REG_A8XX_CP_PROTECT_GLOBAL(63),
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};
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DECLARE_ADRENO_REGLIST_LIST(a810_ifpc_reglist);
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static const struct adreno_reglist_pipe a810_dyn_pwrup_reglist_regs[] = {
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{ REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
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{ REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
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{ REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) },
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{ REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR) },
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{ REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
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{ REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
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{ REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) },
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{ REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) },
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{ REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) },
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{ REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) },
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{ REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
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{ REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
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{ REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
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{ REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
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};
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DECLARE_ADRENO_REGLIST_PIPE_LIST(a810_dyn_pwrup_reglist);
|
||||
|
||||
static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
|
||||
{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
|
||||
{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
|
|
@ -2193,6 +2448,48 @@ static const struct adreno_info a8xx_gpus[] = {
|
|||
{ 252, 2 },
|
||||
{ 221, 3 },
|
||||
),
|
||||
}, {
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x44010000),
|
||||
.family = ADRENO_8XX_GEN1,
|
||||
.fw = {
|
||||
[ADRENO_FW_SQE] = "gen80300_sqe.fw",
|
||||
[ADRENO_FW_GMU] = "gen80300_gmu.bin",
|
||||
},
|
||||
.gmem = SZ_512K + SZ_64K,
|
||||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
|
||||
ADRENO_QUIRK_HAS_HW_APRIV |
|
||||
ADRENO_QUIRK_PREEMPTION |
|
||||
ADRENO_QUIRK_IFPC,
|
||||
.funcs = &a8xx_gpu_funcs,
|
||||
.zapfw = "gen80300_zap.mbn",
|
||||
.a6xx = &(const struct a6xx_info) {
|
||||
.protect = &a810_protect,
|
||||
.nonctxt_reglist = a810_nonctxt_regs,
|
||||
.pwrup_reglist = &a810_pwrup_reglist,
|
||||
.dyn_pwrup_reglist = &a810_dyn_pwrup_reglist,
|
||||
.ifpc_reglist = &a810_ifpc_reglist,
|
||||
.gbif_cx = a840_gbif,
|
||||
.max_slices = 1,
|
||||
.gmu_chipid = 0x8030000,
|
||||
.bcms = (const struct a6xx_bcm[]) {
|
||||
{ .name = "SH0", .buswidth = 16 },
|
||||
{ .name = "MC0", .buswidth = 4 },
|
||||
{
|
||||
.name = "ACV",
|
||||
.fixed = true,
|
||||
.perfmode = BIT(2),
|
||||
.perfmode_bw = 10687500,
|
||||
},
|
||||
{ /* sentinel */ },
|
||||
},
|
||||
},
|
||||
.preempt_record_size = 4558 * SZ_1K,
|
||||
.speedbins = ADRENO_SPEEDBINS(
|
||||
{ 0, 0 },
|
||||
{ 242, 1 },
|
||||
{ 221, 2 },
|
||||
),
|
||||
}
|
||||
};
|
||||
|
||||
|
|
@ -2205,4 +2502,5 @@ static inline __always_unused void __build_asserts(void)
|
|||
BUILD_BUG_ON(a660_protect.count > a660_protect.count_max);
|
||||
BUILD_BUG_ON(a690_protect.count > a690_protect.count_max);
|
||||
BUILD_BUG_ON(a730_protect.count > a730_protect.count_max);
|
||||
BUILD_BUG_ON(a810_protect.count > a810_protect.count_max);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -587,6 +587,11 @@ static inline int adreno_is_a8xx(struct adreno_gpu *gpu)
|
|||
return gpu->info->family >= ADRENO_8XX_GEN1;
|
||||
}
|
||||
|
||||
static inline int adreno_is_a810(struct adreno_gpu *gpu)
|
||||
{
|
||||
return gpu->info->chip_ids[0] == 0x44010000;
|
||||
}
|
||||
|
||||
static inline int adreno_is_x285(struct adreno_gpu *gpu)
|
||||
{
|
||||
return gpu->info->chip_ids[0] == 0x44070001;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user