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drm/amd/display: [FW Promotion] Release 0.1.63.0

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[Why & How]
Add some CACP command and remove some unused struct and enum.

Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Taimur Hassan 2026-06-05 17:09:34 -04:00 committed by Alex Deucher
parent 79d21b5095
commit 9a591ae691
1 changed files with 35 additions and 143 deletions
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178
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
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@ -1800,28 +1800,13 @@ enum dmub_inbox0_command {
*
* Command IDs should be treated as stable ABI.
* Do not reuse or modify IDs.
* Note that command IDs 1-4 have been deprecated.
*/
enum dmub_cmd_type {
/**
* Invalid command.
*/
DMUB_CMD__NULL = 0,
/**
* Read modify write register sequence offload.
*/
DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
/**
* Field update register sequence offload.
*/
DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
/**
* Burst write sequence offload.
*/
DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
/**
* Reg wait sequence offload.
*/
DMUB_CMD__REG_REG_WAIT = 4,
/**
* Workaround to avoid HUBP underflow during NV12 playback.
*/
@ -2041,98 +2026,6 @@ struct dmub_cmd_header {
unsigned int reserved1 : 2; /**< reserved bits */
};
/*
* struct dmub_cmd_read_modify_write_sequence - Read modify write
*
* 60 payload bytes can hold up to 5 sets of read modify writes,
* each take 3 dwords.
*
* number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
*
* modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
* command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
*/
struct dmub_cmd_read_modify_write_sequence {
uint32_t addr; /**< register address */
uint32_t modify_mask; /**< modify mask */
uint32_t modify_value; /**< modify value */
};
/**
* Maximum number of ops in read modify write sequence.
*/
#define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
/**
* struct dmub_cmd_read_modify_write_sequence - Read modify write command.
*/
struct dmub_rb_cmd_read_modify_write {
struct dmub_cmd_header header; /**< command header */
/**
* Read modify write sequence.
*/
struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
};
/*
* Update a register with specified masks and values sequeunce
*
* 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
*
* number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
*
*
* USE CASE:
* 1. auto-increment register where additional read would update pointer and produce wrong result
* 2. toggle a bit without read in the middle
*/
struct dmub_cmd_reg_field_update_sequence {
uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
uint32_t modify_value; /**< value to update with */
};
/**
* Maximum number of ops in field update sequence.
*/
#define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
/**
* struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
*/
struct dmub_rb_cmd_reg_field_update_sequence {
struct dmub_cmd_header header; /**< command header */
uint32_t addr; /**< register address */
/**
* Field update sequence.
*/
struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
};
/**
* Maximum number of burst write values.
*/
#define DMUB_BURST_WRITE_VALUES__MAX 14
/*
* struct dmub_rb_cmd_burst_write - Burst write
*
* support use case such as writing out LUTs.
*
* 60 payload bytes can hold up to 14 values to write to given address
*
* number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
*/
struct dmub_rb_cmd_burst_write {
struct dmub_cmd_header header; /**< command header */
uint32_t addr; /**< register start address */
/**
* Burst write register values.
*/
uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
};
/**
* struct dmub_rb_cmd_common - Common command header
*/
@ -2144,24 +2037,6 @@ struct dmub_rb_cmd_common {
uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
};
/**
* struct dmub_cmd_reg_wait_data - Register wait data
*/
struct dmub_cmd_reg_wait_data {
uint32_t addr; /**< Register address */
uint32_t mask; /**< Mask for register bits */
uint32_t condition_field_value; /**< Value to wait for */
uint32_t time_out_us; /**< Time out for reg wait in microseconds */
};
/**
* struct dmub_rb_cmd_reg_wait - Register wait command
*/
struct dmub_rb_cmd_reg_wait {
struct dmub_cmd_header header; /**< Command header */
struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
};
/**
* struct dmub_cmd_PLAT_54186_wa - Underflow workaround
*
@ -6439,10 +6314,43 @@ struct dmub_cmd_cacp_set_backlight_data {
*/
uint8_t panel_mask;
/**
* AUX HW Instance.
*/
uint8_t aux_inst;
/**
* Explicit padding to 4 byte boundary.
*/
uint8_t pad[2];
uint8_t pad[1];
/**
* Backlight control type.
* Value 0 is PWM backlight control.
* Value 1 is VAUX backlight control.
* Value 2 is AMD DPCD AUX backlight control.
*/
enum dmub_backlight_control_type backlight_control_type;
/**
* Minimum luminance in nits.
*/
uint32_t min_luminance;
/**
* Maximum luminance in nits.
*/
uint32_t max_luminance;
/**
* Minimum backlight in pwm.
*/
uint32_t min_backlight_pwm;
/**
* Maximum backlight in pwm.
*/
uint32_t max_backlight_pwm;
};
/**
@ -7362,22 +7270,6 @@ union dmub_rb_cmd {
* Elements shared with all commands.
*/
struct dmub_rb_cmd_common cmd_common;
/**
* Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
*/
struct dmub_rb_cmd_read_modify_write read_modify_write;
/**
* Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
*/
struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
/**
* Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
*/
struct dmub_rb_cmd_burst_write burst_write;
/**
* Definition of a DMUB_CMD__REG_REG_WAIT command.
*/
struct dmub_rb_cmd_reg_wait reg_wait;
/**
* Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
*/