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drm/amd/display: Adjust dm to use supported interfaces for setting multiple crc windows
[Why & How] We actually have the capability to calculate independent CRC for 2 crc window at the same time. Extend dm with the capability by having array to configure/maintain multiple crc windows. Add the flexibility but use 1st CRC instance only for now. Can change to use the 2nd CRC instance if needed. Reviewed-by: HaoPing Liu <haoping.liu@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wayne Lin
Alex Deucher
parent
10008a962b
commit
9a45ad15a1
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@ -2155,6 +2155,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
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amdgpu_dm_crtc_secure_display_create_contexts(adev);
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if (!adev->dm.secure_display_ctx.crtc_ctx)
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DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
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if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 0, 1))
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adev->dm.secure_display_ctx.support_mul_roi = true;
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#endif
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DRM_DEBUG_DRIVER("KMS initialized.\n");
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@ -10027,14 +10031,19 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
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#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
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if (amdgpu_dm_crc_window_is_activated(crtc)) {
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uint8_t cnt;
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spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
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acrtc->dm_irq_params.window_param.update_win = true;
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for (cnt = 0; cnt < MAX_CRC_WINDOW_NUM; cnt++) {
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if (acrtc->dm_irq_params.window_param[cnt].enable) {
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acrtc->dm_irq_params.window_param[cnt].update_win = true;
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/**
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* It takes 2 frames for HW to stably generate CRC when
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* resuming from suspend, so we set skip_frame_cnt 2.
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*/
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acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
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/**
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* It takes 2 frames for HW to stably generate CRC when
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* resuming from suspend, so we set skip_frame_cnt 2.
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*/
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acrtc->dm_irq_params.window_param[cnt].skip_frame_cnt = 2;
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}
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}
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spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
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}
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#endif
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@ -295,33 +295,41 @@ static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc, struct dc_st
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struct drm_device *drm_dev = crtc->dev;
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struct amdgpu_display_manager *dm = &drm_to_adev(drm_dev)->dm;
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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bool was_activated;
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struct amdgpu_dm_connector *aconnector;
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bool was_activated;
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uint8_t phy_id;
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unsigned long flags;
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int i;
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spin_lock_irq(&drm_dev->event_lock);
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was_activated = acrtc->dm_irq_params.window_param.activated;
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acrtc->dm_irq_params.window_param.x_start = 0;
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acrtc->dm_irq_params.window_param.y_start = 0;
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acrtc->dm_irq_params.window_param.x_end = 0;
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acrtc->dm_irq_params.window_param.y_end = 0;
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acrtc->dm_irq_params.window_param.activated = false;
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acrtc->dm_irq_params.window_param.update_win = false;
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acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
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spin_unlock_irq(&drm_dev->event_lock);
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spin_lock_irqsave(&drm_dev->event_lock, flags);
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was_activated = acrtc->dm_irq_params.crc_window_activated;
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for (i = 0; i < MAX_CRC_WINDOW_NUM; i++) {
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acrtc->dm_irq_params.window_param[i].x_start = 0;
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acrtc->dm_irq_params.window_param[i].y_start = 0;
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acrtc->dm_irq_params.window_param[i].x_end = 0;
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acrtc->dm_irq_params.window_param[i].y_end = 0;
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acrtc->dm_irq_params.window_param[i].enable = false;
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acrtc->dm_irq_params.window_param[i].update_win = false;
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acrtc->dm_irq_params.window_param[i].skip_frame_cnt = 0;
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}
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acrtc->dm_irq_params.crc_window_activated = false;
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spin_unlock_irqrestore(&drm_dev->event_lock, flags);
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/* Disable secure_display if it was enabled */
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if (was_activated) {
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/* stop ROI update on this crtc */
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flush_work(&dm->secure_display_ctx.crtc_ctx[crtc->index].notify_ta_work);
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flush_work(&dm->secure_display_ctx.crtc_ctx[crtc->index].forward_roi_work);
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aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
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if (aconnector && get_phy_id(dm, aconnector, &phy_id))
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dc_stream_forward_crc_window(stream, NULL, phy_id, true);
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else
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if (aconnector && get_phy_id(dm, aconnector, &phy_id)) {
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if (dm->secure_display_ctx.support_mul_roi)
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dc_stream_forward_multiple_crc_window(stream, NULL, phy_id, true);
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else
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dc_stream_forward_crc_window(stream, NULL, phy_id, true);
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} else {
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DRM_DEBUG_DRIVER("%s Can't find matching phy id", __func__);
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}
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}
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}
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@ -393,6 +401,8 @@ amdgpu_dm_forward_crc_window(struct work_struct *work)
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struct drm_crtc *crtc;
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struct dc_stream_state *stream;
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struct amdgpu_dm_connector *aconnector;
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struct crc_window roi_cpy[MAX_CRC_WINDOW_NUM];
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unsigned long flags;
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uint8_t phy_id;
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crtc_ctx = container_of(work, struct secure_display_crtc_context, forward_roi_work);
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@ -416,9 +426,17 @@ amdgpu_dm_forward_crc_window(struct work_struct *work)
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}
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mutex_unlock(&crtc->dev->mode_config.mutex);
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spin_lock_irqsave(&crtc->dev->event_lock, flags);
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memcpy(roi_cpy, crtc_ctx->roi, sizeof(struct crc_window) * MAX_CRC_WINDOW_NUM);
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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mutex_lock(&dm->dc_lock);
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dc_stream_forward_crc_window(stream, &crtc_ctx->rect,
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phy_id, false);
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if (dm->secure_display_ctx.support_mul_roi)
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dc_stream_forward_multiple_crc_window(stream, roi_cpy,
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phy_id, false);
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else
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dc_stream_forward_crc_window(stream, &roi_cpy[0].rect,
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phy_id, false);
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mutex_unlock(&dm->dc_lock);
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}
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@ -429,7 +447,7 @@ bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc)
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bool ret = false;
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spin_lock_irq(&drm_dev->event_lock);
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ret = acrtc->dm_irq_params.window_param.activated;
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ret = acrtc->dm_irq_params.crc_window_activated;
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spin_unlock_irq(&drm_dev->event_lock);
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return ret;
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@ -726,7 +744,15 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc)
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struct amdgpu_crtc *acrtc = NULL;
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struct amdgpu_device *adev = NULL;
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struct secure_display_crtc_context *crtc_ctx = NULL;
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bool reset_crc_frame_count[MAX_CRC_WINDOW_NUM] = {false};
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uint32_t crc_r[MAX_CRC_WINDOW_NUM] = {0};
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uint32_t crc_g[MAX_CRC_WINDOW_NUM] = {0};
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uint32_t crc_b[MAX_CRC_WINDOW_NUM] = {0};
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unsigned long flags1;
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bool forward_roi_change = false;
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bool notify_ta = false;
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bool all_crc_ready = true;
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int i;
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if (crtc == NULL)
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return;
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@ -740,15 +766,14 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc)
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/* Early return if CRC capture is not enabled. */
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if (!amdgpu_dm_is_valid_crc_source(cur_crc_src) ||
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!dm_is_crc_source_crtc(cur_crc_src))
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goto cleanup;
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!dm_is_crc_source_crtc(cur_crc_src)) {
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spin_unlock_irqrestore(&drm_dev->event_lock, flags1);
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return;
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}
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if (!acrtc->dm_irq_params.window_param.activated)
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goto cleanup;
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if (acrtc->dm_irq_params.window_param.skip_frame_cnt) {
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acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1;
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goto cleanup;
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if (!acrtc->dm_irq_params.crc_window_activated) {
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spin_unlock_irqrestore(&drm_dev->event_lock, flags1);
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return;
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}
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crtc_ctx = &adev->dm.secure_display_ctx.crtc_ctx[acrtc->crtc_id];
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@ -759,32 +784,90 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc)
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crtc_ctx->crtc = crtc;
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}
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if (acrtc->dm_irq_params.window_param.update_win) {
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/* prepare work for dmub to update ROI */
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crtc_ctx->rect.x = acrtc->dm_irq_params.window_param.x_start;
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crtc_ctx->rect.y = acrtc->dm_irq_params.window_param.y_start;
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crtc_ctx->rect.width = acrtc->dm_irq_params.window_param.x_end -
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acrtc->dm_irq_params.window_param.x_start;
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crtc_ctx->rect.height = acrtc->dm_irq_params.window_param.y_end -
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acrtc->dm_irq_params.window_param.y_start;
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schedule_work(&crtc_ctx->forward_roi_work);
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for (i = 0; i < MAX_CRC_WINDOW_NUM; i++) {
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crtc_ctx->roi[i].enable = acrtc->dm_irq_params.window_param[i].enable;
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acrtc->dm_irq_params.window_param.update_win = false;
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if (!acrtc->dm_irq_params.window_param[i].enable) {
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crtc_ctx->crc_info.crc[i].crc_ready = false;
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continue;
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}
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/* Statically skip 1 frame, because we may need to wait below things
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* before sending ROI to dmub:
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* 1. We defer the work by using system workqueue.
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* 2. We may need to wait for dc_lock before accessing dmub.
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*/
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acrtc->dm_irq_params.window_param.skip_frame_cnt = 1;
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if (acrtc->dm_irq_params.window_param[i].skip_frame_cnt) {
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acrtc->dm_irq_params.window_param[i].skip_frame_cnt -= 1;
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crtc_ctx->crc_info.crc[i].crc_ready = false;
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continue;
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}
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} else {
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/* prepare work for psp to read ROI/CRC and send to I2C */
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schedule_work(&crtc_ctx->notify_ta_work);
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if (acrtc->dm_irq_params.window_param[i].update_win) {
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/* prepare work for dmub to update ROI */
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crtc_ctx->roi[i].rect.x = acrtc->dm_irq_params.window_param[i].x_start;
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crtc_ctx->roi[i].rect.y = acrtc->dm_irq_params.window_param[i].y_start;
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crtc_ctx->roi[i].rect.width = acrtc->dm_irq_params.window_param[i].x_end -
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acrtc->dm_irq_params.window_param[i].x_start;
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crtc_ctx->roi[i].rect.height = acrtc->dm_irq_params.window_param[i].y_end -
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acrtc->dm_irq_params.window_param[i].y_start;
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forward_roi_change = true;
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reset_crc_frame_count[i] = true;
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acrtc->dm_irq_params.window_param[i].update_win = false;
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/* Statically skip 1 frame, because we may need to wait below things
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* before sending ROI to dmub:
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* 1. We defer the work by using system workqueue.
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* 2. We may need to wait for dc_lock before accessing dmub.
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*/
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acrtc->dm_irq_params.window_param[i].skip_frame_cnt = 1;
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crtc_ctx->crc_info.crc[i].crc_ready = false;
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} else {
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struct dc_stream_state *stream_state = to_dm_crtc_state(crtc->state)->stream;
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if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, i,
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&crc_r[i], &crc_g[i], &crc_b[i]))
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DRM_ERROR("Secure Display: fail to get crc from engine %d\n", i);
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/* prepare work for psp to read ROI/CRC and send to I2C */
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notify_ta = true;
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/* crc ready for psp to read out */
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crtc_ctx->crc_info.crc[i].crc_ready = true;
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}
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}
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cleanup:
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spin_unlock_irqrestore(&drm_dev->event_lock, flags1);
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if (forward_roi_change)
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schedule_work(&crtc_ctx->forward_roi_work);
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if (notify_ta)
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schedule_work(&crtc_ctx->notify_ta_work);
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spin_lock_irqsave(&crtc_ctx->crc_info.lock, flags1);
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for (i = 0; i < MAX_CRC_WINDOW_NUM; i++) {
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crtc_ctx->crc_info.crc[i].crc_R = crc_r[i];
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crtc_ctx->crc_info.crc[i].crc_G = crc_g[i];
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crtc_ctx->crc_info.crc[i].crc_B = crc_b[i];
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if (!crtc_ctx->roi[i].enable) {
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crtc_ctx->crc_info.crc[i].frame_count = 0;
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continue;
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}
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if (!crtc_ctx->crc_info.crc[i].crc_ready)
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all_crc_ready = false;
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if (reset_crc_frame_count[i] || crtc_ctx->crc_info.crc[i].frame_count == UINT_MAX)
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/* Reset the reference frame count after user update the ROI
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* or it reaches the maximum value.
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*/
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crtc_ctx->crc_info.crc[i].frame_count = 0;
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else
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crtc_ctx->crc_info.crc[i].frame_count += 1;
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}
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spin_unlock_irqrestore(&crtc_ctx->crc_info.lock, flags1);
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if (all_crc_ready)
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complete_all(&crtc_ctx->crc_info.completion);
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}
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void amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev)
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@ -805,6 +888,7 @@ void amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev)
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INIT_WORK(&crtc_ctx[i].forward_roi_work, amdgpu_dm_forward_crc_window);
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INIT_WORK(&crtc_ctx[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read);
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crtc_ctx[i].crtc = &adev->mode_info.crtcs[i]->base;
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spin_lock_init(&crtc_ctx[i].crc_info.lock);
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}
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adev->dm.secure_display_ctx.crtc_ctx = crtc_ctx;
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@ -51,13 +51,27 @@ struct phy_id_mapping {
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u8 rad[8];
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};
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struct crc_data {
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uint32_t crc_R;
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uint32_t crc_G;
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uint32_t crc_B;
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uint32_t frame_count;
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bool crc_ready;
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};
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struct crc_info {
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struct crc_data crc[MAX_CRC_WINDOW_NUM];
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struct completion completion;
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spinlock_t lock;
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};
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struct crc_window_param {
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uint16_t x_start;
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uint16_t y_start;
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uint16_t x_end;
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uint16_t y_end;
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/* CRC window is activated or not*/
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bool activated;
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bool enable;
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/* Update crc window during vertical blank or not */
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bool update_win;
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/* skip reading/writing for few frames */
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@ -74,13 +88,16 @@ struct secure_display_crtc_context {
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struct drm_crtc *crtc;
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/* Region of Interest (ROI) */
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struct rect rect;
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struct crc_window roi[MAX_CRC_WINDOW_NUM];
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struct crc_info crc_info;
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};
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struct secure_display_context {
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struct secure_display_crtc_context *crtc_ctx;
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/* Whether dmub support multiple ROI setting */
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bool support_mul_roi;
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bool phy_mapping_updated;
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int phy_id_mapping_cnt;
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struct phy_id_mapping phy_id_mapping[MAX_CRTC];
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@ -3480,8 +3480,8 @@ static int crc_win_x_start_set(void *data, u64 val)
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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spin_lock_irq(&drm_dev->event_lock);
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acrtc->dm_irq_params.window_param.x_start = (uint16_t) val;
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acrtc->dm_irq_params.window_param.update_win = false;
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acrtc->dm_irq_params.window_param[0].x_start = (uint16_t) val;
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acrtc->dm_irq_params.window_param[0].update_win = false;
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spin_unlock_irq(&drm_dev->event_lock);
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return 0;
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@ -3497,7 +3497,7 @@ static int crc_win_x_start_get(void *data, u64 *val)
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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spin_lock_irq(&drm_dev->event_lock);
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*val = acrtc->dm_irq_params.window_param.x_start;
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*val = acrtc->dm_irq_params.window_param[0].x_start;
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spin_unlock_irq(&drm_dev->event_lock);
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return 0;
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@ -3517,8 +3517,8 @@ static int crc_win_y_start_set(void *data, u64 val)
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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spin_lock_irq(&drm_dev->event_lock);
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acrtc->dm_irq_params.window_param.y_start = (uint16_t) val;
|
||||
acrtc->dm_irq_params.window_param.update_win = false;
|
||||
acrtc->dm_irq_params.window_param[0].y_start = (uint16_t) val;
|
||||
acrtc->dm_irq_params.window_param[0].update_win = false;
|
||||
spin_unlock_irq(&drm_dev->event_lock);
|
||||
|
||||
return 0;
|
||||
|
|
@ -3534,7 +3534,7 @@ static int crc_win_y_start_get(void *data, u64 *val)
|
|||
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
|
||||
|
||||
spin_lock_irq(&drm_dev->event_lock);
|
||||
*val = acrtc->dm_irq_params.window_param.y_start;
|
||||
*val = acrtc->dm_irq_params.window_param[0].y_start;
|
||||
spin_unlock_irq(&drm_dev->event_lock);
|
||||
|
||||
return 0;
|
||||
|
|
@ -3553,8 +3553,8 @@ static int crc_win_x_end_set(void *data, u64 val)
|
|||
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
|
||||
|
||||
spin_lock_irq(&drm_dev->event_lock);
|
||||
acrtc->dm_irq_params.window_param.x_end = (uint16_t) val;
|
||||
acrtc->dm_irq_params.window_param.update_win = false;
|
||||
acrtc->dm_irq_params.window_param[0].x_end = (uint16_t) val;
|
||||
acrtc->dm_irq_params.window_param[0].update_win = false;
|
||||
spin_unlock_irq(&drm_dev->event_lock);
|
||||
|
||||
return 0;
|
||||
|
|
@ -3570,7 +3570,7 @@ static int crc_win_x_end_get(void *data, u64 *val)
|
|||
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
|
||||
|
||||
spin_lock_irq(&drm_dev->event_lock);
|
||||
*val = acrtc->dm_irq_params.window_param.x_end;
|
||||
*val = acrtc->dm_irq_params.window_param[0].x_end;
|
||||
spin_unlock_irq(&drm_dev->event_lock);
|
||||
|
||||
return 0;
|
||||
|
|
@ -3589,8 +3589,8 @@ static int crc_win_y_end_set(void *data, u64 val)
|
|||
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
|
||||
|
||||
spin_lock_irq(&drm_dev->event_lock);
|
||||
acrtc->dm_irq_params.window_param.y_end = (uint16_t) val;
|
||||
acrtc->dm_irq_params.window_param.update_win = false;
|
||||
acrtc->dm_irq_params.window_param[0].y_end = (uint16_t) val;
|
||||
acrtc->dm_irq_params.window_param[0].update_win = false;
|
||||
spin_unlock_irq(&drm_dev->event_lock);
|
||||
|
||||
return 0;
|
||||
|
|
@ -3606,7 +3606,7 @@ static int crc_win_y_end_get(void *data, u64 *val)
|
|||
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
|
||||
|
||||
spin_lock_irq(&drm_dev->event_lock);
|
||||
*val = acrtc->dm_irq_params.window_param.y_end;
|
||||
*val = acrtc->dm_irq_params.window_param[0].y_end;
|
||||
spin_unlock_irq(&drm_dev->event_lock);
|
||||
|
||||
return 0;
|
||||
|
|
@ -3633,9 +3633,10 @@ static int crc_win_update_set(void *data, u64 val)
|
|||
|
||||
spin_lock_irq(&adev_to_drm(adev)->event_lock);
|
||||
|
||||
acrtc->dm_irq_params.window_param.activated = true;
|
||||
acrtc->dm_irq_params.window_param.update_win = true;
|
||||
acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
|
||||
acrtc->dm_irq_params.window_param[0].enable = true;
|
||||
acrtc->dm_irq_params.window_param[0].update_win = true;
|
||||
acrtc->dm_irq_params.window_param[0].skip_frame_cnt = 0;
|
||||
acrtc->dm_irq_params.crc_window_activated = true;
|
||||
|
||||
spin_unlock_irq(&adev_to_drm(adev)->event_lock);
|
||||
mutex_unlock(&adev->dm.dc_lock);
|
||||
|
|
|
|||
|
|
@ -39,7 +39,9 @@ struct dm_irq_params {
|
|||
#ifdef CONFIG_DEBUG_FS
|
||||
enum amdgpu_dm_pipe_crc_source crc_src;
|
||||
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
|
||||
struct crc_window_param window_param;
|
||||
struct crc_window_param window_param[MAX_CRC_WINDOW_NUM];
|
||||
/* At least one CRC window is activated or not*/
|
||||
bool crc_window_activated;
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user