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drm/i915/dsc: have intel_dsc_pps_read() return the value

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Register read functions usually return the value instead of passing via
pointer parameters. Return the multiple register verification results
via a pointer parameter, which can also be NULL to skip the extra
checks.

Make the name conform to existing style better while at it.

Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/4d08c0f63c4975cc8cd01b0f82845c989bf13dd0.1693933849.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2023-09-05 20:11:22 +03:00
parent 34131651e1
commit 9995d61512
1 changed files with 19 additions and 13 deletions
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32
drivers/gpu/drm/i915/display/intel_vdsc.c
View File

@ -809,13 +809,14 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
}
}
static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
int pps, u32 *pps_val)
static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
bool *check_equal)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
i915_reg_t dsc_reg[2];
int i, vdsc_per_pipe, dsc_reg_num;
u32 val = 0;
vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
@ -824,20 +825,25 @@ static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
*pps_val = 0;
if (check_equal)
*check_equal = true;
for (i = 0; i < dsc_reg_num; i++) {
u32 pps_temp;
u32 tmp;
pps_temp = intel_de_read(i915, dsc_reg[i]);
tmp = intel_de_read(i915, dsc_reg[i]);
if (i == 0)
*pps_val = pps_temp;
else if (pps_temp != *pps_val)
return false;
if (i == 0) {
val = tmp;
} else if (check_equal && tmp != val) {
*check_equal = false;
break;
} else if (!check_equal) {
break;
}
}
return true;
return val;
}
static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)
@ -845,10 +851,10 @@ static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, in
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
u32 val;
int ret;
bool all_equal;
ret = intel_dsc_read_pps_reg(crtc_state, pps, &val);
drm_WARN_ON(&i915->drm, !ret);
val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
drm_WARN_ON(&i915->drm, !all_equal);
return val;
}