From 414772b8f7d7a9ccbfb5f0f3fd51bbfb8d54501a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 2 Jul 2023 20:52:21 +0200 Subject: [PATCH 01/68] arm64: dts: ti: minor whitespace cleanup around '=' The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230702185221.44319-1-krzysztof.kozlowski@linaro.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 4 +-- .../arm64/boot/dts/ti/k3-am625-beagleplay.dts | 2 +- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 8 +++--- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 +- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 28 +++++++++---------- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 14 +++++----- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 14 +++++----- .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 14 +++++----- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 24 ++++++++-------- .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 14 +++++----- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 4 +-- 11 files changed, 64 insertions(+), 64 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 2488e3a537fe..4a1dab9e40a0 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -590,7 +590,7 @@ usbss0: dwc3-usb@f900000 { usb0: usb@31000000 { compatible = "snps,dwc3"; - reg =<0x00 0x31000000 0x00 0x50000>; + reg = <0x00 0x31000000 0x00 0x50000>; interrupts = , /* irq.0 */ ; /* irq.0 */ interrupt-names = "host", "peripheral"; @@ -613,7 +613,7 @@ usbss1: dwc3-usb@f910000 { usb1: usb@31100000 { compatible = "snps,dwc3"; - reg =<0x00 0x31100000 0x00 0x50000>; + reg = <0x00 0x31100000 0x00 0x50000>; interrupts = , /* irq.0 */ ; /* irq.0 */ interrupt-names = "host", "peripheral"; diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index 589bf998bc52..7c1402b0fa2d 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -14,7 +14,7 @@ #include "k3-am625.dtsi" / { - compatible = "beagle,am625-beagleplay", "ti,am625"; + compatible = "beagle,am625-beagleplay", "ti,am625"; model = "BeagleBoard.org BeaglePlay"; aliases { diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 8b315cc61550..8397cb80f559 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -150,8 +150,8 @@ dmsc: system-controller@44043000 { reg-names = "debug_messages"; ti,host-id = <12>; mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_main 12>, - <&secure_proxy_main 13>; + mboxes = <&secure_proxy_main 12>, + <&secure_proxy_main 13>; k3_pds: power-controller { compatible = "ti,sci-pm-domain"; @@ -527,7 +527,7 @@ usbss0: dwc3-usb@f900000 { usb0: usb@31000000 { compatible = "snps,dwc3"; - reg =<0x00 0x31000000 0x00 0x50000>; + reg = <0x00 0x31000000 0x00 0x50000>; interrupts = , /* irq.0 */ ; /* irq.0 */ interrupt-names = "host", "peripheral"; @@ -550,7 +550,7 @@ usbss1: dwc3-usb@f910000 { usb1: usb@31100000 { compatible = "snps,dwc3"; - reg =<0x00 0x31100000 0x00 0x50000>; + reg = <0x00 0x31100000 0x00 0x50000>; interrupts = , /* irq.0 */ ; /* irq.0 */ interrupt-names = "host", "peripheral"; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index ecc0e13331c4..d2cca6182738 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -13,7 +13,7 @@ #include "k3-am62a7.dtsi" / { - compatible = "ti,am62a7-sk", "ti,am62a7"; + compatible = "ti,am62a7-sk", "ti,am62a7"; model = "Texas Instruments AM62A7 SK"; aliases { diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 3f8ff2589842..791c6b38993d 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -773,10 +773,10 @@ mailbox0_cluster11: mailbox@31f8b000 { ringacc: ringacc@3c000000 { compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x3c000000 0x0 0x400000>, - <0x0 0x38000000 0x0 0x400000>, - <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; ti,num-rings = <818>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ @@ -787,9 +787,9 @@ ringacc: ringacc@3c000000 { main_udmap: dma-controller@31150000 { compatible = "ti,am654-navss-main-udmap"; - reg = <0x0 0x31150000 0x0 0x100>, - <0x0 0x34000000 0x0 0x100000>, - <0x0 0x35000000 0x0 0x100000>; + reg = <0x0 0x31150000 0x0 0x100>, + <0x0 0x34000000 0x0 0x100000>, + <0x0 0x35000000 0x0 0x100000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&inta_main_udmass>; #dma-cells = <1>; @@ -1006,13 +1006,13 @@ csi2_0: port@0 { dss: dss@4a00000 { compatible = "ti,am65x-dss"; - reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ - <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ - <0x0 0x04a06000 0x0 0x1000>, /* vid */ - <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ - <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ - <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ + <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ + <0x0 0x04a06000 0x0 0x1000>, /* vid */ + <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ + <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ + <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ + <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ reg-names = "common", "vidl1", "vid", "ovr1", "ovr2", "vp1", "vp2"; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index b7a4b5a89aaf..7b1f94a89eca 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -194,10 +194,10 @@ mcu_navss: bus@28380000 { mcu_ringacc: ringacc@2b800000 { compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>; + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ @@ -208,9 +208,9 @@ mcu_ringacc: ringacc@2b800000 { mcu_udmap: dma-controller@285c0000 { compatible = "ti,am654-navss-mcu-udmap"; - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x2aa00000 0x0 0x40000>; + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x2aa00000 0x0 0x40000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&inta_main_udmass>; #dma-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index ac62bbc1660d..6eaade5aeb42 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -264,10 +264,10 @@ mailbox0_cluster11: mailbox@31f8b000 { main_ringacc: ringacc@3c000000 { compatible = "ti,am654-navss-ringacc"; - reg = <0x00 0x3c000000 0x00 0x400000>, - <0x00 0x38000000 0x00 0x400000>, - <0x00 0x31120000 0x00 0x100>, - <0x00 0x33000000 0x00 0x40000>; + reg = <0x00 0x3c000000 0x00 0x400000>, + <0x00 0x38000000 0x00 0x400000>, + <0x00 0x31120000 0x00 0x100>, + <0x00 0x33000000 0x00 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; ti,num-rings = <1024>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ @@ -278,9 +278,9 @@ main_ringacc: ringacc@3c000000 { main_udmap: dma-controller@31150000 { compatible = "ti,j721e-navss-main-udmap"; - reg = <0x00 0x31150000 0x00 0x100>, - <0x00 0x34000000 0x00 0x100000>, - <0x00 0x35000000 0x00 0x100000>; + reg = <0x00 0x31150000 0x00 0x100>, + <0x00 0x34000000 0x00 0x100000>, + <0x00 0x35000000 0x00 0x100000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index c5e4c41effd1..ee7860913c38 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -326,10 +326,10 @@ mcu_navss: bus@28380000 { mcu_ringacc: ringacc@2b800000 { compatible = "ti,am654-navss-ringacc"; - reg = <0x00 0x2b800000 0x00 0x400000>, - <0x00 0x2b000000 0x00 0x400000>, - <0x00 0x28590000 0x00 0x100>, - <0x00 0x2a500000 0x00 0x40000>; + reg = <0x00 0x2b800000 0x00 0x400000>, + <0x00 0x2b000000 0x00 0x400000>, + <0x00 0x28590000 0x00 0x100>, + <0x00 0x2a500000 0x00 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ @@ -340,9 +340,9 @@ mcu_ringacc: ringacc@2b800000 { mcu_udmap: dma-controller@285c0000 { compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x00 0x285c0000 0x00 0x100>, - <0x00 0x2a800000 0x00 0x40000>, - <0x00 0x2aa00000 0x00 0x40000>; + reg = <0x00 0x285c0000 0x00 0x100>, + <0x00 0x2a800000 0x00 0x40000>, + <0x00 0x2aa00000 0x00 0x40000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 2ded1ee1a854..649628685c32 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -364,10 +364,10 @@ mailbox0_cluster11: mailbox@31f8b000 { main_ringacc: ringacc@3c000000 { compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x3c000000 0x0 0x400000>, - <0x0 0x38000000 0x0 0x400000>, - <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; ti,num-rings = <1024>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ @@ -378,9 +378,9 @@ main_ringacc: ringacc@3c000000 { main_udmap: dma-controller@31150000 { compatible = "ti,j721e-navss-main-udmap"; - reg = <0x0 0x31150000 0x0 0x100>, - <0x0 0x34000000 0x0 0x100000>, - <0x0 0x35000000 0x0 0x100000>; + reg = <0x0 0x31150000 0x0 0x100>, + <0x0 0x34000000 0x0 0x100000>, + <0x0 0x35000000 0x0 0x100000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; @@ -1761,11 +1761,11 @@ dss: dss@4a00000 { "vp1", "vp2", "vp3", "vp4", "wb"; - clocks = <&k3_clks 152 0>, - <&k3_clks 152 1>, - <&k3_clks 152 4>, - <&k3_clks 152 9>, - <&k3_clks 152 13>; + clocks = <&k3_clks 152 0>, + <&k3_clks 152 1>, + <&k3_clks 152 4>, + <&k3_clks 152 9>, + <&k3_clks 152 13>; clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index ea5b9e104491..c1b6f8d7d189 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -445,10 +445,10 @@ mcu_navss: bus@28380000 { mcu_ringacc: ringacc@2b800000 { compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>; + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ @@ -459,9 +459,9 @@ mcu_ringacc: ringacc@2b800000 { mcu_udmap: dma-controller@285c0000 { compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x2aa00000 0x0 0x40000>; + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x2aa00000 0x0 0x40000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 2ea0adae6832..11f163e5cadf 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -618,7 +618,7 @@ main_sdhci0: mmc@4f80000 { interrupts = ; power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; - clock-names = "clk_ahb", "clk_xin"; + clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 140 2>; assigned-clock-parents = <&k3_clks 140 3>; bus-width = <8>; @@ -646,7 +646,7 @@ main_sdhci1: mmc@4fb0000 { interrupts = ; power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; - clock-names = "clk_ahb", "clk_xin"; + clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 141 4>; assigned-clock-parents = <&k3_clks 141 5>; bus-width = <4>; From 48a498a269c60cd3ca3de87761a1016aa7de9593 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jul 2023 16:57:55 +0200 Subject: [PATCH 02/68] arm64: dts: ti: add missing space before { Add missing whitespace between node name/label and opening {. Signed-off-by: Krzysztof Kozlowski Reviewed-by: David Lechner Link: https://lore.kernel.org/r/20230705145755.292927-2-krzysztof.kozlowski@linaro.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 2 +- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 4 ++-- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 2 +- arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 2 +- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 2 +- 7 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 3f9ef4053aa6..7c98c1b855d1 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -212,7 +212,7 @@ &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 1664d9f0241c..a57ea7130ca3 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -733,7 +733,7 @@ timesync_router: pinctrl@a40000 { pinctrl-single,function-mask = <0x000107ff>; }; - usbss0: cdns-usb@f900000{ + usbss0: cdns-usb@f900000 { compatible = "ti,am64-usb"; reg = <0x00 0xf900000 0x00 0x100>; power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; @@ -744,7 +744,7 @@ usbss0: cdns-usb@f900000{ #address-cells = <2>; #size-cells = <2>; ranges; - usb0: usb@f400000{ + usb0: usb@f400000 { compatible = "cdns,usb3"; reg = <0x00 0xf400000 0x00 0x10000>, <0x00 0xf410000 0x00 0x10000>, diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 649628685c32..575435c1a984 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -660,7 +660,7 @@ wiz1_refclk_dig: refclk-dig { assigned-clock-parents = <&k3_clks 293 13>; }; - wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ + wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div { clocks = <&wiz1_refclk_dig>; #clock-cells = <0>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 04d4739d7245..092ab1e14ba5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -407,7 +407,7 @@ &ospi1 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index e7dd947a1814..736ec5fa0ea2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -440,7 +440,7 @@ mcu_spi2: spi@40320000 { status = "disabled"; }; - mcu_navss: bus@28380000{ + mcu_navss: bus@28380000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 430b8a2c5df5..7ad152a1b90f 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -499,7 +499,7 @@ &ospi1 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 657fb1d72512..740ee794d7b9 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -441,7 +441,7 @@ mcu_spi2: spi@40320000 { status = "disabled"; }; - mcu_navss: bus@28380000{ + mcu_navss: bus@28380000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; From 2a7cc7bedb58d4eedc177e642efedc25d713445a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 13 Jul 2023 13:47:59 -0500 Subject: [PATCH 03/68] arm64: dts: ti: Fix compatible of ti,*-ehrpwm-tbclk TI EHRPWM compatible is just ti,*-ehrpwm-tbclk without needing a syscon compatibility. Fixes the following dtbs_check warnings: compatible: [''ti,am654-ehrpwm-tbclk, 'syscon'] is too long compatible: ['ti,am64-epwm-tbclk', 'syscon'] is too long compatible: ['ti,am62-epwm-tbclk', 'syscon'] is too long Reviewed-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20230713184759.3336536-1-nm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 4a1dab9e40a0..5cea46be40f5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -56,7 +56,7 @@ phy_gmii_sel: phy@4044 { }; epwm_tbclk: clock@4130 { - compatible = "ti,am62-epwm-tbclk", "syscon"; + compatible = "ti,am62-epwm-tbclk"; reg = <0x4130 0x4>; #clock-cells = <1>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index a57ea7130ca3..d3dd8c426dad 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -222,7 +222,7 @@ phy_gmii_sel: phy@4044 { }; epwm_tbclk: clock@4140 { - compatible = "ti,am64-epwm-tbclk", "syscon"; + compatible = "ti,am64-epwm-tbclk"; reg = <0x4130 0x4>; #clock-cells = <1>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 791c6b38993d..350beddc3d3c 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -503,7 +503,7 @@ dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { }; ehrpwm_tbclk: clock@4140 { - compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + compatible = "ti,am654-ehrpwm-tbclk"; reg = <0x4140 0x18>; #clock-cells = <1>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 575435c1a984..6c9fe28b6de7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -76,7 +76,7 @@ usb_serdes_mux: mux-controller@4000 { }; ehrpwm_tbclk: clock-controller@4140 { - compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + compatible = "ti,am654-ehrpwm-tbclk"; reg = <0x4140 0x18>; #clock-cells = <1>; }; From 8717c76ff38d8a6fa99cce4cccf7892288108ec8 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Fri, 21 Jul 2023 13:53:44 +0530 Subject: [PATCH 04/68] arm64: dts: ti: k3-j721e-som-p0: Remove Duplicated wkup_i2c0 node wkup_i2c0 and associated eeprom device node were duplicated, This patch fixes the node duplication. Fixes: 4af0332876f9 ("arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eeprom") Signed-off-by: Udit Kumar Link: https://lore.kernel.org/r/20230721082344.1534094-1-u-kumar1@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 38ae13cc3aa3..e90e43202546 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -201,19 +201,6 @@ eeprom@50 { }; }; -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@50 { - /* CAV24C256WE-GT3 */ - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; From 8d08d7aac7f620b5d298fad0ba0e6e431ea132a9 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Fri, 21 Jul 2023 18:27:31 +0530 Subject: [PATCH 05/68] arm64: dts: ti: Use local header for SERDES MUX idle-state values The DTS uses constants for SERDES MUX idle state values which were earlier provided as bindings header. But they are unsuitable for bindings. So move these constants in a header next to DTS. Also add J784S4 SERDES4 lane definitions which were missed earlier. Suggested-by: Nishanth Menon Suggested-by: Krzysztof Kozlowski Suggested-by: Roger Quadros Link: https://lore.kernel.org/linux-arm-kernel/b24c2124-fe3b-246c-9af9-3ecee9fb32d4@kernel.org/ Signed-off-by: Jayesh Choudhary Reviewed-by: Krzysztof Kozlowski Acked-by: Roger Quadros Acked-by: Peter Rosin Link: https://lore.kernel.org/r/20230721125732.122421-2-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 3 +- .../dts/ti/k3-am642-phyboard-electra-rdk.dts | 3 +- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 3 +- .../boot/dts/ti/k3-am68-sk-base-board.dts | 3 +- .../dts/ti/k3-j7200-common-proc-board.dts | 3 +- .../ti/k3-j7200-evm-quad-port-eth-exp.dtso | 2 +- .../ti/k3-j721e-evm-quad-port-eth-exp.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 3 +- .../dts/ti/k3-j721s2-common-proc-board.dts | 3 +- arch/arm64/boot/dts/ti/k3-serdes.h | 204 ++++++++++++++++++ 10 files changed, 220 insertions(+), 9 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-serdes.h diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 15c282c93467..d84e7ee16032 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -6,12 +6,13 @@ /dts-v1/; #include -#include #include #include #include #include "k3-am642.dtsi" +#include "k3-serdes.h" + / { compatible = "ti,am642-evm", "ti,am642"; model = "Texas Instruments AM642 EVM"; diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 9c418abd29d8..9175e96842d8 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -16,11 +16,12 @@ #include #include #include -#include #include #include "k3-am642.dtsi" #include "k3-am64-phycore-som.dtsi" +#include "k3-serdes.h" + / { compatible = "phytec,am642-phyboard-electra-rdk", "phytec,am64-phycore-som", "ti,am642"; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index cbce43dbe3f9..963d796a3a97 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -5,13 +5,14 @@ /dts-v1/; -#include #include #include #include #include #include "k3-am642.dtsi" +#include "k3-serdes.h" + / { compatible = "ti,am642-sk", "ti,am642"; model = "Texas Instruments AM642 SK"; diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index d5889ba3fa46..21ad49cfa7ee 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -11,7 +11,8 @@ #include #include #include -#include + +#include "k3-serdes.h" / { compatible = "ti,am68-sk", "ti,j721s2"; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 3cf288128c3f..92a541491172 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -8,9 +8,10 @@ #include "k3-j7200-som-p0.dtsi" #include #include -#include #include +#include "k3-serdes.h" + / { compatible = "ti,j7200-evm", "ti,j7200"; model = "Texas Instruments J7200 EVM"; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso index 34a0747cbe69..32d905235ed7 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso +++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso @@ -10,9 +10,9 @@ /plugin/; #include -#include #include "k3-pinctrl.h" +#include "k3-serdes.h" &{/} { aliases { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso index 6f0adf591b98..d4c51ffc3d6b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso @@ -10,11 +10,11 @@ /plugin/; #include -#include #include #include #include "k3-pinctrl.h" +#include "k3-serdes.h" &{/} { aliases { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 6c9fe28b6de7..3acd55ffd4ff 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -7,7 +7,8 @@ #include #include #include -#include + +#include "k3-serdes.h" / { cmn_refclk: clock-cmnrefclk { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 092ab1e14ba5..02b7a559bdf2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -11,7 +11,8 @@ #include #include #include -#include + +#include "k3-serdes.h" / { compatible = "ti,j721s2-evm", "ti,j721s2"; diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h new file mode 100644 index 000000000000..29167f85c1f6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-serdes.h @@ -0,0 +1,204 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for SERDES MUX for TI SoCs + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef DTS_ARM64_TI_K3_SERDES_H +#define DTS_ARM64_TI_K3_SERDES_H + +/* J721E */ + +#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 +#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 +#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 +#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 +#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 +#define J721E_SERDES0_LANE1_USB3_0 0x2 +#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 +#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 +#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 +#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 + +#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 +#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 +#define J721E_SERDES1_LANE1_USB3_1 0x2 +#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 + +#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 +#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 +#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 +#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 + +#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 +#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 +#define J721E_SERDES2_LANE1_USB3_1 0x2 +#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 + +#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 +#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 +#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 +#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 + +#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 +#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 +#define J721E_SERDES3_LANE1_USB3_0 0x2 +#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE0_EDP_LANE0 0x0 +#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 +#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE1_EDP_LANE1 0x0 +#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 +#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE2_EDP_LANE2 0x0 +#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 +#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE3_EDP_LANE3 0x0 +#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 +#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 + +/* J7200 */ + +#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 +#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 +#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 +#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 +#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 +#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 +#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 +#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 +#define J7200_SERDES0_LANE3_USB 0x2 +#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 + +/* AM64 */ + +#define AM64_SERDES0_LANE0_PCIE0 0x0 +#define AM64_SERDES0_LANE0_USB 0x1 + +/* J721S2 */ + +#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 +#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 +#define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2 +#define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 +#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 +#define J721S2_SERDES0_LANE1_USB 0x2 +#define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 +#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 +#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 + +#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 +#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 +#define J721S2_SERDES0_LANE3_USB 0x2 +#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3 + +/* J784S4 */ + +#define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0 +#define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1 +#define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2 +#define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0 +#define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1 +#define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2 +#define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0 +#define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1 +#define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3 + +#define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0 +#define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1 +#define J784S4_SERDES0_LANE3_USB 0x2 +#define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3 + +#define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0 +#define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1 +#define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2 +#define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3 + +#define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0 +#define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1 +#define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2 +#define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3 + +#define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0 +#define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1 +#define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2 +#define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3 + +#define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0 +#define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1 +#define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2 +#define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3 + +#define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0 +#define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1 +#define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2 +#define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3 + +#define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0 +#define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1 +#define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2 +#define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3 + +#define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0 +#define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1 +#define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2 +#define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3 + +#define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0 +#define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1 +#define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2 +#define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3 + +#define J784S4_SERDES4_LANE0_EDP_LANE0 0x0 +#define J784S4_SERDES4_LANE0_QSGMII_LANE5 0x1 +#define J784S4_SERDES4_LANE0_IP3_UNUSED 0x2 +#define J784S4_SERDES4_LANE0_IP4_UNUSED 0x3 + +#define J784S4_SERDES4_LANE1_EDP_LANE1 0x0 +#define J784S4_SERDES4_LANE1_QSGMII_LANE6 0x1 +#define J784S4_SERDES4_LANE1_IP3_UNUSED 0x2 +#define J784S4_SERDES4_LANE1_IP4_UNUSED 0x3 + +#define J784S4_SERDES4_LANE2_EDP_LANE2 0x0 +#define J784S4_SERDES4_LANE2_QSGMII_LANE7 0x1 +#define J784S4_SERDES4_LANE2_IP3_UNUSED 0x2 +#define J784S4_SERDES4_LANE2_IP4_UNUSED 0x3 + +#define J784S4_SERDES4_LANE3_EDP_LANE3 0x0 +#define J784S4_SERDES4_LANE3_QSGMII_LANE8 0x1 +#define J784S4_SERDES4_LANE3_USB 0x2 +#define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3 + +#endif /* DTS_ARM64_TI_K3_SERDES_H */ From 5438d75fb9d7bb863ddc5ef28b242ca50c9879ff Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Fri, 21 Jul 2023 18:27:32 +0530 Subject: [PATCH 06/68] dt-bindings: ti-serdes-mux: Deprecate header with constants The constants to define the idle state of SERDES MUX were defined in bindings header. They are used only in DTS and driver uses the dt property to set the idle state making it unsuitable for bindings. The constants are moved to header next to DTS ("arch/arm64/boot/dts/ti/") and all the references to bindings header are removed. So add a warning to mark this bindings header as deprecated. Signed-off-by: Jayesh Choudhary Reviewed-by: Krzysztof Kozlowski Acked-by: Roger Quadros Acked-by: Peter Rosin Link: https://lore.kernel.org/r/20230721125732.122421-3-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- include/dt-bindings/mux/ti-serdes.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h index 669ca2d6abce..b0b1091aad6d 100644 --- a/include/dt-bindings/mux/ti-serdes.h +++ b/include/dt-bindings/mux/ti-serdes.h @@ -6,6 +6,14 @@ #ifndef _DT_BINDINGS_MUX_TI_SERDES #define _DT_BINDINGS_MUX_TI_SERDES +/* + * These bindings are deprecated, because they do not match the actual + * concept of bindings but rather contain pure constants values used only + * in DTS board files. + * Instead include the header in the DTS source directory. + */ +#warning "These bindings are deprecated. Instead, use the header in the DTS source directory." + /* J721E */ #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 From e1f7d17a734c5c617d05c3d188939d5032d3d5a2 Mon Sep 17 00:00:00 2001 From: Kamlesh Gurudasani Date: Fri, 14 Jul 2023 14:42:41 +0530 Subject: [PATCH 07/68] dt-bindings: crypto: ti,sa2ul: make power-domains conditional Devices specific to compatible ti,am62-sa3ul don't have control over power of SA3UL from main domain. "power-domains" property in crypto node tries to access the SA3UL power, for which it gets NACK and hence, driver doesn't probe properly for those particular devices. Make "power-domains" property as false for devices with compatible ti,am62-sa3ul. Fixes: 2ce9a7299bf6 ("dt-bindings: crypto: Add TI SA2UL crypto accelerator documentation") Reviewed-by: Conor Dooley Signed-off-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230614-sa3ul-v5-1-29dd2366fba3@ti.com Signed-off-by: Nishanth Menon --- .../devicetree/bindings/crypto/ti,sa2ul.yaml | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml b/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml index 77ec8bc70bf7..f0ef7685550a 100644 --- a/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml +++ b/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml @@ -66,10 +66,22 @@ patternProperties: required: - compatible - reg - - power-domains - dmas - dma-names +allOf: + - if: + properties: + compatible: + contains: + const: ti,am62-sa3ul + then: + properties: + power-domains: false + else: + required: + - power-domains + additionalProperties: false examples: From b573bf35ef3f113c1717fa22cefdfdfbb83aec70 Mon Sep 17 00:00:00 2001 From: Kamlesh Gurudasani Date: Fri, 14 Jul 2023 14:42:42 +0530 Subject: [PATCH 08/68] arm64: dts: ti: k3-am62-main: Remove power-domains from crypto node Only SYSFW has control of SA3UL power. From SYSFW 08.04.00.002, for security reasons, device ID for power management of SA3UL has been removed. "power-domains" property in crypto node tries to access the SA3UL, for which it gets NACK and hence, SA3UL driver doesn't probe properly. Fixes: 8af893654c02 ("arm64: dts: ti: k3-am62-main: Enable crypto accelerator") Signed-off-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230614-sa3ul-v5-2-29dd2366fba3@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 5cea46be40f5..33b6aadc9083 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -174,7 +174,6 @@ k3_reset: reset-controller { crypto: crypto@40900000 { compatible = "ti,am62-sa3ul"; reg = <0x00 0x40900000 0x00 0x1200>; - power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; From 0bec3d7ecc7493b0e530f6f34539841ef6779006 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 19 Jun 2023 08:16:20 -0500 Subject: [PATCH 09/68] arm64: dts: ti: k3-pinctrl: Introduce debounce select mux macros Introduce the debounce select mux macros to allow folks to setup debounce configuration for pins. Each configuration selected maps to a specific timing register as documented in appropriate Technical Reference Manual (example:[1]). [1] AM625x TRM (section 6.1.2.2): https://www.ti.com/lit/pdf/spruiv7 Reviewed-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20230619131620.3286650-1-nm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h index c97548a3f42d..6004e0967ec5 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -11,6 +11,7 @@ #define PULLUDEN_SHIFT (16) #define PULLTYPESEL_SHIFT (17) #define RXACTIVE_SHIFT (18) +#define DEBOUNCE_SHIFT (11) #define PULL_DISABLE (1 << PULLUDEN_SHIFT) #define PULL_ENABLE (0 << PULLUDEN_SHIFT) @@ -29,6 +30,14 @@ #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) +#define PIN_DEBOUNCE_DISABLE (0 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF1 (1 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF2 (2 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF3 (3 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF4 (4 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) + #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) From 98f3b667e1de99dc670e12563eae03e15c668d95 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Tue, 25 Jul 2023 14:29:39 +0530 Subject: [PATCH 10/68] arm64: dts: ti: k3-j721s2: Add support for CAN instances 3 and 5 in main domain CAN instances 3 and 5 in the main domain are brought on the common processor board through header J27 and J28. The CAN High and Low lines from the SoC are routed through a mux on the SoM. The select lines need to be set for the CAN signals to get connected to the transceivers on the common processor board. Threfore, add respective mux, transceiver dt nodes to add support for these CAN instances. Reviewed-by: Udit Kumar Signed-off-by: Bhavya Kapoor Link: https://lore.kernel.org/r/20230725085939.536766-1-b-kapoor@ti.com Signed-off-by: Nishanth Menon --- .../dts/ti/k3-j721s2-common-proc-board.dts | 46 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 12 +++++ 2 files changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 02b7a559bdf2..20b32563c0ed 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -30,6 +30,8 @@ aliases { can0 = &main_mcan16; can1 = &mcu_mcan0; can2 = &mcu_mcan1; + can3 = &main_mcan3; + can4 = &main_mcan5; }; evm_12v0: fixedregulator-evm12v0 { @@ -110,6 +112,22 @@ transceiver2: can-phy2 { standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; }; + transceiver3: can-phy3 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; + enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; + mux-states = <&mux0 1>; + }; + + transceiver4: can-phy4 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>; + mux-states = <&mux1 1>; + }; }; &main_pmx0 { @@ -153,6 +171,20 @@ main_usbss0_pins_default: main-usbss0-default-pins { J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ >; }; + + main_mcan3_pins_default: main-mcan3-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */ + J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */ + >; + }; + + main_mcan5_pins_default: main-mcan5-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */ + J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */ + >; + }; }; &wkup_pmx2 { @@ -461,3 +493,17 @@ adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; + +&main_mcan3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan3_pins_default>; + phys = <&transceiver3>; +}; + +&main_mcan5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan5_pins_default>; + phys = <&transceiver4>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index d57dd43da0ef..594766482071 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -31,6 +31,18 @@ secure_ddr: optee@9e800000 { }; }; + mux0: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; + }; + + mux1: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; + }; + transceiver0: can-phy0 { /* standby pin has been grounded by default */ compatible = "ti,tcan1042"; From 99e7172db1ae018d865da34cf3efe32992333187 Mon Sep 17 00:00:00 2001 From: Sinthu Raja Date: Fri, 21 Jul 2023 13:51:50 +0530 Subject: [PATCH 11/68] arm64: dts: ti: k3-j721s2-main: Add dts nodes for EHRPWMs Add dts nodes for 6 EHRPWM instances on SoC. Disable EHRPWM nodes in the dtsi files and only enable the ones that are actually pinned out on a given board in the board dts file. Signed-off-by: Sinthu Raja Link: https://lore.kernel.org/r/20230721082150.12599-1-sinthu.raja@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 66 ++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index ed79ab3a3271..2fb90b899560 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -58,6 +58,72 @@ serdes_ln_ctrl: mux-controller@80 { mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ }; + + ehrpwm_tbclk: clock-controller@140 { + compatible = "ti,am654-ehrpwm-tbclk"; + reg = <0x140 0x18>; + #clock-cells = <1>; + }; + }; + + main_ehrpwm0: pwm@3000000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3000000 0x00 0x100>; + power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm1: pwm@3010000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3010000 0x00 0x100>; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm2: pwm@3020000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3020000 0x00 0x100>; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm3: pwm@3030000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3030000 0x00 0x100>; + power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm4: pwm@3040000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3040000 0x00 0x100>; + power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm5: pwm@3050000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3050000 0x00 0x100>; + power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; }; gic500: interrupt-controller@1800000 { From f33f5e4c801b7f1838f05aae81eaed8189a1eac4 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Tue, 25 Jul 2023 19:06:06 +0530 Subject: [PATCH 12/68] arm64: dts: ti: k3-j784s4-main: Add DT node for UFS Add UFS support present in J784S4 SOC. UFS is documented in J784S4 TRM[1] Section 12.3.7 'Universal Flash Storage (UFS) Interface' [1] http://www.ti.com/lit/zip/spruj52 Cc: Chai Wenle Tested-by: Chai Wenle Signed-off-by: Udit Kumar Reviewed-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20230725133607.2021379-2-u-kumar1@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 11f163e5cadf..a04c44708a09 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1370,6 +1370,30 @@ main_spi7: spi@2170000 { status = "disabled"; }; + ufs_wrapper: ufs-wrapper@4e80000 { + compatible = "ti,j721e-ufs"; + reg = <0x00 0x4e80000 0x00 0x100>; + power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 387 3>; + assigned-clocks = <&k3_clks 387 3>; + assigned-clock-parents = <&k3_clks 387 6>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + ufs@4e84000 { + compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; + reg = <0x00 0x4e84000 0x00 0x10000>; + interrupts = ; + freq-table-hz = <250000000 250000000>, <19200000 19200000>, + <19200000 19200000>; + clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>; + clock-names = "core_clk", "phy_clk", "ref_clk"; + dma-coherent; + }; + }; + main_r5fss0: r5fss@5c00000 { compatible = "ti,j721s2-r5fss"; ti,cluster-mode = <1>; From 5d55545cc2da8ad320b73705b26a5c0a837b20da Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Tue, 25 Jul 2023 19:06:07 +0530 Subject: [PATCH 13/68] arm64: dts: ti: k3-j784s4-evm: Add Support for UFS peripheral J784S4 EVM board has 32GB Non-Volatile UFS Memory. So enabling UFS at board level. UFS flash details are documented in board data sheet[1] Section 1.2 Key Features and Interfaces. [1] https://www.ti.com/lit/pdf/spruj62 Cc: Chai Wenle Tested-by: Chai Wenle Signed-off-by: Udit Kumar Reviewed-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20230725133607.2021379-3-u-kumar1@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 7ad152a1b90f..1e38a8f1bec5 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -430,6 +430,10 @@ &main_uart8 { pinctrl-0 = <&main_uart8_pins_default>; }; +&ufs_wrapper { + status = "okay"; +}; + &fss { status = "okay"; }; From 7815b2816d146f302f3884ee8e87c7b39fea1ecc Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Tue, 25 Jul 2023 13:00:57 +0530 Subject: [PATCH 14/68] arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports with GESI The J7 GESI EXP board for J721E Common-Proc-Board supports RGMII mode. Use the overlay to configure CPSW9G ports in RGMII-RXID mode. Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli Reviewed-by: Ravi Gunasekaran Link: https://lore.kernel.org/r/20230725073057.96705-1-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 2 + .../dts/ti/k3-j721e-evm-gesi-exp-board.dtso | 196 ++++++++++++++++++ 2 files changed, 198 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 6dd7b6f1d6ab..01d58aa8b06e 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -46,6 +46,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm.dtb k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb # Boards with J721s2 SoC @@ -58,3 +59,4 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb # Enable support for device-tree overlays DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ +DTC_FLAGS_k3-j721e-common-proc-board += -@ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso new file mode 100644 index 000000000000..6a7d37575da1 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with + * J721E board. + * + * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; + ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; + ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; + }; +}; + +&cpsw0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_default_pins + &rgmii2_default_pins + &rgmii3_default_pins + &rgmii4_default_pins>; +}; + +&cpsw0_port1 { + status = "okay"; + phy-handle = <&cpsw9g_phy12>; + phy-mode = "rgmii-rxid"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 1>; +}; + +&cpsw0_port2 { + status = "okay"; + phy-handle = <&cpsw9g_phy15>; + phy-mode = "rgmii-rxid"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 2>; +}; + +&cpsw0_port3 { + status = "okay"; + phy-handle = <&cpsw9g_phy0>; + phy-mode = "rgmii-rxid"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 3>; +}; + +&cpsw0_port4 { + status = "okay"; + phy-handle = <&cpsw9g_phy3>; + phy-mode = "rgmii-rxid"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 4>; +}; + +&cpsw9g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_default_pins>; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + + cpsw9g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; + cpsw9g_phy3: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; + cpsw9g_phy12: ethernet-phy@12 { + reg = <12>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; + cpsw9g_phy15: ethernet-phy@15 { + reg = <15>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&exp1 { + p15-hog { + /* P15 - EXP_MUX2 */ + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_MUX2"; + }; + + p16-hog { + /* P16 - EXP_MUX3 */ + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_MUX3"; + }; +}; + +&main_pmx0 { + mdio0_default_pins: mdio0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */ + J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */ + >; + }; + + rgmii1_default_pins: rgmii1-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x4, PIN_INPUT, 4) /* (AC23) PRG1_PRU0_GPO0.RGMII1_RD0 */ + J721E_IOPAD(0x8, PIN_INPUT, 4) /* (AG22) PRG1_PRU0_GPO1.RGMII1_RD1 */ + J721E_IOPAD(0xc, PIN_INPUT, 4) /* (AF22) PRG1_PRU0_GPO2.RGMII1_RD2 */ + J721E_IOPAD(0x10, PIN_INPUT, 4) /* (AJ23) PRG1_PRU0_GPO3.RGMII1_RD3 */ + J721E_IOPAD(0x1c, PIN_INPUT, 4) /* (AD22) PRG1_PRU0_GPO6.RGMII1_RXC */ + J721E_IOPAD(0x14, PIN_INPUT, 4) /* (AH23) PRG1_PRU0_GPO4.RGMII1_RX_CTL */ + J721E_IOPAD(0x30, PIN_OUTPUT, 4) /* (AF24) PRG1_PRU0_GPO11.RGMII1_TD0 */ + J721E_IOPAD(0x34, PIN_OUTPUT, 4) /* (AJ24) PRG1_PRU0_GPO12.RGMII1_TD1 */ + J721E_IOPAD(0x38, PIN_OUTPUT, 4) /* (AG24) PRG1_PRU0_GPO13.RGMII1_TD2 */ + J721E_IOPAD(0x3c, PIN_OUTPUT, 4) /* (AD24) PRG1_PRU0_GPO14.RGMII1_TD3 */ + J721E_IOPAD(0x44, PIN_OUTPUT, 4) /* (AE24) PRG1_PRU0_GPO16.RGMII1_TXC */ + J721E_IOPAD(0x40, PIN_OUTPUT, 4) /* (AC24) PRG1_PRU0_GPO15.RGMII1_TX_CTL */ + >; + }; + + rgmii2_default_pins: rgmii2-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x58, PIN_INPUT, 4) /* (AE22) PRG1_PRU1_GPO0.RGMII2_RD0 */ + J721E_IOPAD(0x5c, PIN_INPUT, 4) /* (AG23) PRG1_PRU1_GPO1.RGMII2_RD1 */ + J721E_IOPAD(0x60, PIN_INPUT, 4) /* (AF23) PRG1_PRU1_GPO2.RGMII2_RD2 */ + J721E_IOPAD(0x64, PIN_INPUT, 4) /* (AD23) PRG1_PRU1_GPO3.RGMII2_RD3 */ + J721E_IOPAD(0x70, PIN_INPUT, 4) /* (AE23) PRG1_PRU1_GPO6.RGMII2_RXC */ + J721E_IOPAD(0x68, PIN_INPUT, 4) /* (AH24) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + J721E_IOPAD(0x84, PIN_OUTPUT, 4) /* (AJ25) PRG1_PRU1_GPO11.RGMII2_TD0 */ + J721E_IOPAD(0x88, PIN_OUTPUT, 4) /* (AH25) PRG1_PRU1_GPO12.RGMII2_TD1 */ + J721E_IOPAD(0x8c, PIN_OUTPUT, 4) /* (AG25) PRG1_PRU1_GPO13.RGMII2_TD2 */ + J721E_IOPAD(0x90, PIN_OUTPUT, 4) /* (AH26) PRG1_PRU1_GPO14.RGMII2_TD3 */ + J721E_IOPAD(0x98, PIN_OUTPUT, 4) /* (AJ26) PRG1_PRU1_GPO16.RGMII2_TXC */ + J721E_IOPAD(0x94, PIN_OUTPUT, 4) /* (AJ27) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; + + rgmii3_default_pins: rgmii3-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0xb0, PIN_INPUT, 4) /* (AF28) PRG0_PRU0_GPO0.RGMII3_RD0 */ + J721E_IOPAD(0xb4, PIN_INPUT, 4) /* (AE28) PRG0_PRU0_GPO1.RGMII3_RD1 */ + J721E_IOPAD(0xb8, PIN_INPUT, 4) /* (AE27) PRG0_PRU0_GPO2.RGMII3_RD2 */ + J721E_IOPAD(0xbc, PIN_INPUT, 4) /* (AD26) PRG0_PRU0_GPO3.RGMII3_RD3 */ + J721E_IOPAD(0xc8, PIN_INPUT, 4) /* (AE26) PRG0_PRU0_GPO6.RGMII3_RXC */ + J721E_IOPAD(0xc0, PIN_INPUT, 4) /* (AD25) PRG0_PRU0_GPO4.RGMII3_RX_CTL */ + J721E_IOPAD(0xdc, PIN_OUTPUT, 4) /* (AJ28) PRG0_PRU0_GPO11.RGMII3_TD0 */ + J721E_IOPAD(0xe0, PIN_OUTPUT, 4) /* (AH27) PRG0_PRU0_GPO12.RGMII3_TD1 */ + J721E_IOPAD(0xe4, PIN_OUTPUT, 4) /* (AH29) PRG0_PRU0_GPO13.RGMII3_TD2 */ + J721E_IOPAD(0xe8, PIN_OUTPUT, 4) /* (AG28) PRG0_PRU0_GPO14.RGMII3_TD3 */ + J721E_IOPAD(0xf0, PIN_OUTPUT, 4) /* (AH28) PRG0_PRU0_GPO16.RGMII3_TXC */ + J721E_IOPAD(0xec, PIN_OUTPUT, 4) /* (AG27) PRG0_PRU0_GPO15.RGMII3_TX_CTL */ + >; + }; + + rgmii4_default_pins: rgmii4-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x100, PIN_INPUT, 4) /* (AE29) PRG0_PRU1_GPO0.RGMII4_RD0 */ + J721E_IOPAD(0x104, PIN_INPUT, 4) /* (AD28) PRG0_PRU1_GPO1.RGMII4_RD1 */ + J721E_IOPAD(0x108, PIN_INPUT, 4) /* (AD27) PRG0_PRU1_GPO2.RGMII4_RD2 */ + J721E_IOPAD(0x10c, PIN_INPUT, 4) /* (AC25) PRG0_PRU1_GPO3.RGMII4_RD3 */ + J721E_IOPAD(0x118, PIN_INPUT, 4) /* (AC26) PRG0_PRU1_GPO6.RGMII4_RXC */ + J721E_IOPAD(0x110, PIN_INPUT, 4) /* (AD29) PRG0_PRU1_GPO4.RGMII4_RX_CTL */ + J721E_IOPAD(0x12c, PIN_OUTPUT, 4) /* (AG26) PRG0_PRU1_GPO11.RGMII4_TD0 */ + J721E_IOPAD(0x130, PIN_OUTPUT, 4) /* (AF27) PRG0_PRU1_GPO12.RGMII4_TD1 */ + J721E_IOPAD(0x134, PIN_OUTPUT, 4) /* (AF26) PRG0_PRU1_GPO13.RGMII4_TD2 */ + J721E_IOPAD(0x138, PIN_OUTPUT, 4) /* (AE25) PRG0_PRU1_GPO14.RGMII4_TD3 */ + J721E_IOPAD(0x140, PIN_OUTPUT, 4) /* (AG29) PRG0_PRU1_GPO16.RGMII4_TXC */ + J721E_IOPAD(0x13c, PIN_OUTPUT, 4) /* (AF29) PRG0_PRU1_GPO15.RGMII4_TX_CTL */ + >; + }; +}; From d6ffe1b4b8c1cdc0ae36b6bc65b11d336aecbb72 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Wed, 26 Jul 2023 12:24:06 +0530 Subject: [PATCH 15/68] arm64: dts: ti: k3-j721s2-main: Add main CPSW2G devicetree node TI's J721S2 SoC has a MAIN CPSW2G instance of the CPSW Ethernet Switch. Add devicetree node for it. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Siddharth Vadapalli Reviewed-by: Ravi Gunasekaran Link: https://lore.kernel.org/r/20230726065407.378455-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 2fb90b899560..6e3fb86cc88e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -51,6 +51,12 @@ usb_serdes_mux: mux-controller@0 { mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; + phy_gmii_sel_cpsw: phy@34 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x34 0x4>; + #phy-cells = <1>; + }; + serdes_ln_ctrl: mux-controller@80 { compatible = "mmio-mux"; reg = <0x80 0x10>; @@ -1105,6 +1111,69 @@ cpts@310d0000 { }; }; + main_cpsw: ethernet@c200000 { + compatible = "ti,j721e-cpsw-nuss"; + reg = <0x00 0xc200000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + dma-coherent; + clocks = <&k3_clks 28 28>; + clock-names = "fck"; + power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xc640>, + <&main_udmap 0xc641>, + <&main_udmap 0xc642>, + <&main_udmap 0xc643>, + <&main_udmap 0xc644>, + <&main_udmap 0xc645>, + <&main_udmap 0xc646>, + <&main_udmap 0xc647>, + <&main_udmap 0x4640>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + phys = <&phy_gmii_sel_cpsw 1>; + status = "disabled"; + }; + }; + + main_cpsw_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 28 28>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 28 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x04104000 0x00 0x100>; From cac04e27f093c3cafdc10c03b6f50e1578ef8cbc Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Wed, 26 Jul 2023 12:24:07 +0530 Subject: [PATCH 16/68] arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI Expansion Board connected to the J7 Common-Proc-Board. Use the overlay to enable this. Add alias for the MAIN CPSW2G port to enable kernel to fetch MAC address directly from U-Boot. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Siddharth Vadapalli Reviewed-by: Ravi Gunasekaran Link: https://lore.kernel.org/r/20230726065407.378455-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 2 + .../dts/ti/k3-j721s2-evm-gesi-exp-board.dtso | 85 +++++++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 01d58aa8b06e..ec8d7608b90e 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -52,6 +52,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb # Boards with J721s2 SoC dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb @@ -60,3 +61,4 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb # Enable support for device-tree overlays DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ DTC_FLAGS_k3-j721e-common-proc-board += -@ +DTC_FLAGS_k3-j721s2-common-proc-board += -@ diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso new file mode 100644 index 000000000000..b78feea31b54 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board. + * + * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; + }; +}; + +&main_pmx0 { + main_cpsw_mdio_default_pins: main-cpsw-mdio-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */ + J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + + rgmii1_default_pins: rgmii1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */ + J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */ + J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */ + J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */ + J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */ + J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */ + J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */ + J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */ + J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */ + J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */ + J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */ + >; + }; +}; + +&exp1 { + p15 { + /* P15 - EXP_MUX2 */ + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_MUX2"; + }; +}; + +&main_cpsw { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_default_pins>; +}; + +&main_cpsw_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw_mdio_default_pins>; + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&main_cpsw_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&main_cpsw_phy0>; +}; From ee1ada53846b6ff4154ac7a78b74a12cfd6a8639 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Thu, 27 Jul 2023 15:21:18 +0200 Subject: [PATCH 17/68] dt-bindings: arm: ti: Add compatible for AM642-based TQMaX4XxL SOM family and carrier board For now only the MBaX4Xx carrier board is defined. Signed-off-by: Matthias Schiffer Acked-by: Conor Dooley Link: https://lore.kernel.org/r/e4283d6af59c77d2f690e070eb948dd9142a2276.1690463382.git.matthias.schiffer@ew.tq-group.com Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 577eee95c893..5ca6af492507 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -72,6 +72,13 @@ properties: - const: phytec,am64-phycore-som - const: ti,am642 + - description: K3 AM642 SoC on TQ-Systems TQMaX4XxL SoM + items: + - enum: + - tq,am642-tqma6442l-mbax4xxl # MBaX4XxL base board + - const: tq,am642-tqma6442l + - const: ti,am642 + - description: K3 AM654 SoC items: - enum: From 4717a36f31ecc7c090ce4459a6ed220869d27eca Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Thu, 27 Jul 2023 15:21:19 +0200 Subject: [PATCH 18/68] arm64: dts: ti: Add TQ-Systems TQMa64XxL SoM and MBaX4XxL carrier board Device Trees The TQMa64XxL is an LGA SoM based on the TI AM64x SoC family. Add DTS(I) for the AM642 (2x Cortex-A53) variant and its combination with our MBaX4XxL carrier board. Signed-off-by: Matthias Schiffer Link: https://lore.kernel.org/r/2a635428c73b5ab0fe793e558db6b5d88edccf8c.1690463382.git.matthias.schiffer@ew.tq-group.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 1 + .../dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 871 ++++++++++++++++++ .../arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 252 +++++ 3 files changed, 1124 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index ec8d7608b90e..32722e49c77f 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -27,6 +27,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb # Boards with AM65x SoC k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts new file mode 100644 index 000000000000..ac132a0867d0 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -0,0 +1,871 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (c) 2022-2023 TQ-Systems GmbH , D-82229 Seefeld, Germany. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "k3-serdes.h" + +#include "k3-am642-tqma64xxl.dtsi" + +/ { + compatible = "tq,am642-tqma6442l-mbax4xxl", "tq,am642-tqma6442l", + "ti,am642"; + model = "TQ-Systems TQMa64xxL SoM on MBax4xxL carrier board"; + + aliases { + ethernet0 = &cpsw_port1; + i2c1 = &mcu_i2c0; + mmc1 = &sdhci1; + serial0 = &mcu_uart0; + serial1 = &mcu_uart1; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial4 = &main_uart2; + serial5 = &main_uart4; + serial6 = &main_uart5; + serial7 = &main_uart3; + spi1 = &main_spi0; + spi2 = &mcu_spi0; + }; + + chosen { + stdout-path = &main_uart0; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_gpio_keys_pins>; + + user-button { + label = "USER_BUTTON"; + linux,code = ; + gpios = <&mcu_gpio0 5 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_gpio_leds_pins>; + + led-0 { + label = "led0"; + gpios = <&mcu_gpio0 8 GPIO_ACTIVE_HIGH>; + }; + led-1 { + label = "led1"; + gpios = <&mcu_gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_fan_pins>; + fan-supply = <®_pwm_fan>; + #cooling-cells = <2>; + /* typical 25 kHz -> 40.000 nsec */ + pwms = <&epwm5 0 40000 PWM_POLARITY_INVERTED>; + cooling-levels = <0 32 64 128 196 240>; + pulses-per-revolution = <2>; + interrupt-parent = <&main_gpio1>; + interrupts = <49 IRQ_TYPE_EDGE_FALLING>; + status = "disabled"; + }; + + wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_wifi_pwrseq_pins>; + reset-gpios = <&main_gpio0 23 GPIO_ACTIVE_LOW>; + }; + + reg_pwm_fan: regulator-pwm-fan { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_fan_reg_pins>; + regulator-name = "FAN_PWR"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&main_gpio1 48 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd: regulator-sd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_reg_pins>; + regulator-name = "V_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&main_gpio1 43 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_pins>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_mdio_pins>; + status = "okay"; + + cpsw3g_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&main_gpio0 44 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + ti,rx-fifo-depth = ; + ti,tx-fifo-depth = ; + ti,rx-internal-delay = ; + ti,clk-output-sel = ; + }; +}; + +&epwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&epwm5_pins>; + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio0_digital_pins>, + <&main_gpio0_hog_pins>; + gpio-line-names = + "", "", "", "", /* 0-3 */ + "", "", "", "", /* 4-7 */ + "", "", "", "", /* 8-11 */ + "", "", "", "", /* 12-15 */ + "", "", "", "", /* 16-19 */ + "", "", "", "", /* 20-23 */ + "", "", "EN_DIG_OUT_1", "STATUS_OUT_1", /* 24-27 */ + "EN_DIG_OUT_2", "STATUS_OUT_2", "EN_SIG_OUT_3", "", /* 28-31 */ + "", "", "STATUS_OUT_3", "EN_DIG_OUT_4", /* 32-35 */ + "", "", "STATUS_OUT_4", "DIG_IN_1", /* 36-39 */ + "DIG_IN_2", "DIG_IN_3", "DIG_IN_4"; /* 40- */ +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_hog_pins>; + gpio-line-names = + "", "", "", "", /* 0-3 */ + "", "", "", "", /* 4-7 */ + "", "", "", "", /* 8-11 */ + "", "", "", "", /* 12-15 */ + "", "", "", "", /* 16-19 */ + "", "", "", "", /* 20-23 */ + "", "", "", "", /* 24-27 */ + "", "", "", "", /* 28-31 */ + "", "", "", "", /* 32-35 */ + "", "", "", "", /* 36-39 */ + "", "", "", "", /* 40-43 */ + "", "", "", "", /* 44-47 */ + "", "", "", "", /* 48-51 */ + "", "", "", "ADC_SYNC", /* 52-55 */ + "", "", "ADC_RST#", "ADC_DATA_RDY", /* 56-59 */ + "", "", "", "", /* 60-63 */ + "", "", "", "ADC_INT#", /* 64-67 */ + "BG95_PWRKEY", "BG95_RESET"; /* 68- */ + + line50-hog { + /* See also usb0 */ + gpio-hog; + gpios = <50 0>; + line-name = "USB0_VBUS_OC#"; + input; + }; + + line54-hog { + gpio-hog; + gpios = <54 0>; + line-name = "PRG0_MDIO_SWITCH"; + output-low; + }; + + line70-hog { + gpio-hog; + gpios = <70 0>; + line-name = "PHY_INT#"; + input; + }; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins>; + status = "okay"; +}; + +&main_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan1_pins>; + status = "okay"; +}; + +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi0_pins>; + ti,pindir-d0-out-d1-in; + status = "okay"; + + /* adc@0: NXP NAFE13388 */ +}; + +/* UART/USB adapter port 1 */ +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins>; + status = "okay"; +}; + +/* + * IOT Module - GNSS UART + * + * Note: We expect usage of a SYSFW that does not reserve UART1 for debug traces + */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins>; + status = "okay"; +}; + +/* RS485 port */ +&main_uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart2_pins>; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + status = "okay"; +}; + +/* Bluetooth module */ +&main_uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart3_pins>; + /* + * Left disabled for now, until a way to deal with drivers and firmware + * for the combined WLAN/BT module has been figured out + */ +}; + +/* IOT module - Main UART */ +&main_uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart4_pins>; + status = "okay"; +}; + +/* IOT module - DBG UART */ +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart5_pins>; + status = "okay"; +}; + +&main0_thermal { + trips { + main0_active0: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + main0_active1: trip-active1 { + temperature = <48000>; + hysteresis = <3000>; + type = "active"; + }; + + main0_active2: trip-active2 { + temperature = <60000>; + hysteresis = <10000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&main0_active0>; + cooling-device = <&fan0 1 1>; + }; + + map2 { + trip = <&main0_active1>; + cooling-device = <&fan0 2 2>; + }; + + map3 { + trip = <&main0_active2>; + cooling-device = <&fan0 3 3>; + }; + }; +}; + +&main1_thermal { + trips { + main1_active0: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + main1_active1: trip-active1 { + temperature = <48000>; + hysteresis = <3000>; + type = "active"; + }; + + main1_active2: trip-active2 { + temperature = <60000>; + hysteresis = <10000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&main1_active0>; + cooling-device = <&fan0 1 1>; + }; + + map2 { + trip = <&main1_active1>; + cooling-device = <&fan0 2 2>; + }; + + map3 { + trip = <&main1_active2>; + cooling-device = <&fan0 3 3>; + }; + }; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_gpio0_pins>; +}; + +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins>; + /* Left disabled: not functional without external pullup */ +}; + +&mcu_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_spi0_pins>; + ti,pindir-d0-out-d1-in; + status = "okay"; +}; + +/* UART/USB adapter port 2 */ +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins>; + status = "okay"; +}; + +/* Pin header */ +&mcu_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart1_pins>; + status = "okay"; +}; + +&serdes_ln_ctrl { + idle-states = ; +}; + +&serdes0 { + serdes0_usb_link: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&serdes_wiz0 1>; + cdns,num-lanes = <1>; + cdns,phy-type = ; + }; +}; + +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins>; + bus-width = <4>; + cd-gpios = <&main_gpio1 77 GPIO_ACTIVE_LOW>; + disable-wp; + no-mmc; + ti,driver-strength-ohm = <50>; + ti,fails-without-test-cd; + /* Enabled by overlay */ + status = "disabled"; +}; + +&tscadc0 { + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&usb0 { + /* + * The CDNS USB driver currently doesn't support overcurrent GPIOs, + * so there is no overcurrent detection. The OC pin is configured + * as a GPIO hog instead. + */ + pinctrl-names = "default"; + pinctrl-0 = <&main_usb0_pins>; + dr_mode = "otg"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&usbss0 { + ti,vbus-divider; +}; + +&main_pmx0 { + cpsw_pins: cpsw-pins { + pinctrl-single,pins = < + /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ + AM64X_IOPAD(0x01cc, PIN_INPUT, 4) + /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ + AM64X_IOPAD(0x01d4, PIN_INPUT, 4) + /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ + AM64X_IOPAD(0x01d8, PIN_INPUT, 4) + /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ + AM64X_IOPAD(0x01f4, PIN_INPUT, 4) + /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ + AM64X_IOPAD(0x0188, PIN_INPUT, 4) + /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ + AM64X_IOPAD(0x0184, PIN_INPUT, 4) + /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ + AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) + /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ + AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) + /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ + AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) + /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ + AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) + /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ + AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) + /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ + AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) + >; + }; + + cpsw_mdio_pins: cpsw-mdio-pins { + pinctrl-single,pins = < + /* (R21) GPMC0_CSn3.GPIO0_44 - RESET_RGMII1# */ + AM64X_IOPAD(0x00b4, PIN_OUTPUT, 7) + + /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ + AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) + /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ + AM64X_IOPAD(0x01f8, PIN_INPUT, 4) + >; + }; + + epwm5_pins: epwm5-pins { + pinctrl-single,pins = < + /* (W19) GPMC0_WAIT0.EHRPWM5_B */ + AM64X_IOPAD(0x0098, PIN_OUTPUT, 3) + >; + }; + + /* Digital IOs */ + main_gpio0_digital_pins: main-gpio0-digital-pins { + pinctrl-single,pins = < + /* (W20) GPMC0_AD11.GPIO0_26 - EN_DIG_OUT_1 */ + AM64X_IOPAD(0x0068, PIN_OUTPUT, 7) + /* (W21) GPMC0_AD12.GPIO0_27 - STATUS_OUT_1 */ + AM64X_IOPAD(0x006c, PIN_INPUT, 7) + /* (V18) GPMC0_AD13.GPIO0_28 - EN_DIG_OUT_2 */ + AM64X_IOPAD(0x0070, PIN_OUTPUT, 7) + /* (Y21) GPMC0_AD14.GPIO0_29 - STATUS_OUT_2 */ + AM64X_IOPAD(0x0074, PIN_INPUT, 7) + /* (Y20) GPMC0_AD15.GPIO0_30 - EN_DIG_OUT_3 */ + AM64X_IOPAD(0x0078, PIN_OUTPUT, 7) + /* (T21) GPMC0_WEn.GPIO0_34 - STATUS_OUT_3 */ + AM64X_IOPAD(0x008c, PIN_INPUT, 7) + /* (P17) GPMC0_BE0n_CLE.GPIO0_35 - EN_DIG_OUT_4 */ + AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) + /* (Y18) GPMC0_WAIT1.GPIO0_38 - STATUS_OUT_4 */ + AM64X_IOPAD(0x009c, PIN_INPUT, 7) + /* (N16) GPMC0_WPn.GPIO0_39 - DIG_IN_1 */ + AM64X_IOPAD(0x00a0, PIN_INPUT, 7) + /* (N17) GPMC0_DIR.GPIO0_40 - DIG_IN_2 */ + AM64X_IOPAD(0x00a4, PIN_INPUT, 7) + /* (R19) GPMC0_CSn0.GPIO0_41 - DIG_IN_3 */ + AM64X_IOPAD(0x00a8, PIN_INPUT, 7) + /* (R20) GPMC0_CSn1.GPIO0_42 - DIG_IN_4 */ + AM64X_IOPAD(0x00ac, PIN_INPUT, 7) + >; + }; + + main_gpio0_hog_pins: main-gpio0-hog-pins { + pinctrl-single,pins = < + /* (P19) GPMC0_CSn2.GPIO0_43 - MMC1_CTRL */ + AM64X_IOPAD(0x00b0, PIN_OUTPUT, 7) + >; + }; + + main_gpio1_hog_pins: main-gpio1-hog-pins { + pinctrl-single,pins = < + /* (B15) SPI1_D0.GPIO1_50 - USB0_VBUS_OC# */ + AM64X_IOPAD(0x0228, PIN_INPUT, 7) + /* (B16) UART0_CTSn.GPIO1_54 - PRG0_MDIO_SWITCH */ + AM64X_IOPAD(0x0238, PIN_OUTPUT, 7) + /* (C19) EXTINTn.GPIO1_70 - PHY_INT# */ + AM64X_IOPAD(0x0278, PIN_INPUT, 7) + >; + }; + + main_mcan0_pins: main-mcan0-pins { + pinctrl-single,pins = < + /* (B17) MCAN0_RX */ + AM64X_IOPAD(0x0254, PIN_INPUT, 0) + /* (A17) MCAN0_TX */ + AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) + >; + }; + + main_mcan1_pins: main-mcan1-pins { + pinctrl-single,pins = < + /* (D17) MCAN1_RX */ + AM64X_IOPAD(0x025c, PIN_INPUT, 0) + /* (C17) MCAN1_TX */ + AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) + >; + }; + + main_mmc1_pins: main-mmc1-pins { + pinctrl-single,pins = < + /* (J19) MMC1_CMD */ + AM64X_IOPAD(0x0294, PIN_INPUT, 0) + /* (L20) MMC1_CLK */ + AM64X_IOPAD(0x028c, PIN_INPUT, 0) + /* (K21) MMC1_DAT0 */ + AM64X_IOPAD(0x0288, PIN_INPUT, 0) + /* (L21) MMC1_DAT1 */ + AM64X_IOPAD(0x0284, PIN_INPUT, 0) + /* (K19) MMC1_DAT2 */ + AM64X_IOPAD(0x0280, PIN_INPUT, 0) + /* (K18) MMC1_DAT3 */ + AM64X_IOPAD(0x027c, PIN_INPUT, 0) + /* (D19) MMC1_SDCD.GPIO1_77 */ + AM64X_IOPAD(0x0298, PIN_INPUT, 7) + /* (#N/A) MMC1_CLKLB */ + AM64X_IOPAD(0x0290, PIN_INPUT, 0) + >; + }; + + main_mmc1_reg_pins: main-mmc1-reg-pins { + pinctrl-single,pins = < + /* (C13) SPI0_CS1.GPIO1_43 - MMC1_SD_EN */ + AM64X_IOPAD(0x020c, PIN_OUTPUT, 7) + >; + }; + + main_mmc1_wifi_pwrseq_pins: main-mmc1-wifi-pwrseq-pins { + pinctrl-single,pins = < + /* (V19) GPMC0_AD8.GPIO0_23 - WIFI-BT_EN */ + AM64X_IOPAD(0x005c, PIN_OUTPUT, 7) + >; + }; + + main_spi0_pins: main-spi0-pins { + pinctrl-single,pins = < + /* (D13) SPI0_CLK */ + AM64X_IOPAD(0x0210, PIN_OUTPUT, 0) + /* (D12) SPI0_CS0 */ + AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) + /* (A13) SPI0_D0 */ + AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) + /* (A14) SPI0_D1 */ + AM64X_IOPAD(0x0218, PIN_INPUT, 0) + >; + }; + + main_spi0_adc_pins: main-spi0-adc-pins { + pinctrl-single,pins = < + /* (A16) UART0_RTSn.GPIO1_55 - ADC_SYNC */ + AM64X_IOPAD(0x023c, PIN_INPUT, 7) + /* (D16) UART1_CTSn.GPIO1_58 - ADC_RST# */ + AM64X_IOPAD(0x0248, PIN_OUTPUT, 7) + /* (E16) UART1_RTSn.GPIO1_59 - ADC_DATA_RDY */ + AM64X_IOPAD(0x024c, PIN_INPUT, 7) + /* (B19) I2C1_SDA.GPIO1_67 - ADC_INT# */ + AM64X_IOPAD(0x026c, PIN_INPUT, 7) + >; + }; + + main_uart0_pins: main-uart0-pins { + pinctrl-single,pins = < + /* (D15) UART0_RXD */ + AM64X_IOPAD(0x0230, PIN_INPUT, 0) + /* (C16) UART0_TXD */ + AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) + >; + }; + + main_uart1_pins: main-uart1-pins { + pinctrl-single,pins = < + /* (E15) UART1_RXD */ + AM64X_IOPAD(0x0240, PIN_INPUT, 0) + /* (E14) UART1_TXD */ + AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) + >; + }; + + main_uart2_pins: main-uart2-pins { + pinctrl-single,pins = < + /* (T18) GPMC0_AD2.UART2_RTSn */ + AM64X_IOPAD(0x0044, PIN_OUTPUT, 2) + /* (T20) GPMC0_AD0.UART2_RXD */ + AM64X_IOPAD(0x003c, PIN_INPUT, 2) + /* (U21) GPMC0_AD1.UART2_TXD */ + AM64X_IOPAD(0x0040, PIN_OUTPUT, 2) + >; + }; + + main_uart3_pins: main-uart3-pins { + pinctrl-single,pins = < + /* (T17) GPMC0_AD9.UART3_CTSn */ + AM64X_IOPAD(0x0060, PIN_INPUT, 2) + /* (U19) GPMC0_AD5.UART3_RTSn */ + AM64X_IOPAD(0x0050, PIN_OUTPUT, 2) + /* (U20) GPMC0_AD3.UART3_RXD */ + AM64X_IOPAD(0x0048, PIN_INPUT, 2) + /* (U18) GPMC0_AD4.UART3_TXD */ + AM64X_IOPAD(0x004c, PIN_OUTPUT, 2) + >; + }; + + main_uart4_pins: main-uart4-pins { + pinctrl-single,pins = < + /* (R16) GPMC0_AD10.UART4_CTSn */ + AM64X_IOPAD(0x0064, PIN_INPUT, 2) + /* (R17) GPMC0_CLK.UART4_RTSn */ + AM64X_IOPAD(0x007c, PIN_OUTPUT, 2) + /* (V20) GPMC0_AD6.UART4_RXD */ + AM64X_IOPAD(0x0054, PIN_INPUT, 2) + /* (V21) GPMC0_AD7.UART4_TXD */ + AM64X_IOPAD(0x0058, PIN_OUTPUT, 2) + + /* Control GPIOs for IOT Module connected to UART4 */ + /* (D18) ECAP0_IN_APWM_OUT.GPIO1_68 - BG95_PWRKEY */ + AM64X_IOPAD(0x0270, PIN_OUTPUT, 7) + /* (A19) EXT_REFCLK1.GPIO1_69 - BG95_RESET */ + AM64X_IOPAD(0x0274, PIN_OUTPUT, 7) + >; + }; + + main_uart5_pins: main-uart5-pins { + pinctrl-single,pins = < + /* (P16) GPMC0_ADVn_ALE.UART5_RXD */ + AM64X_IOPAD(0x0084, PIN_INPUT, 2) + /* (R18) GPMC0_OEn_REn.UART5_TXD */ + AM64X_IOPAD(0x0088, PIN_OUTPUT, 2) + >; + }; + + main_usb0_pins: main-usb0-pins { + pinctrl-single,pins = < + /* (E19) USB0_DRVVBUS */ + AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) + >; + }; + + pru_icssg1_mdio_pins: pru-icssg1-mdio-pins { + pinctrl-single,pins = < + /* (A15) SPI1_D1.GPIO1_51 - RESET_PRG1_RGMII1# */ + AM64X_IOPAD(0x022c, PIN_OUTPUT, 7) + /* (B14) SPI1_CS0.GPIO1_47 - RESET_PRG1_RGMII2# */ + AM64X_IOPAD(0x021c, PIN_OUTPUT, 7) + + /* (Y6) PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) + /* (AA6) PRG1_MDIO0_MDIO */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) + >; + }; + + pru_icssg1_rgmii1_pins: pru-icssg1-rgmii1-pins { + pinctrl-single,pins = < + /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) + /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) + /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) + /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) + /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) + /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) + /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ + AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) + /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ + AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) + /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ + AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) + /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ + AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) + /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + AM64X_IOPAD(0x00f8, PIN_OUTPUT, 2) + /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ + AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) + >; + }; + + pru_icssg1_rgmii2_pins: pru-icssg1-rgmii2-pins { + pinctrl-single,pins = < + /* (W11) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */ + AM64X_IOPAD(0x0108, PIN_INPUT, 2) + /* (V11) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) + /* (AA12) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) + /* (Y12) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) + /* (U11) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) + /* (W12) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) + /* (AA10) PRG1_PRU1_GPO11.PRG1_RGMII2_TD0 */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) + /* (V10) PRG1_PRU1_GPO12.PRG1_RGMII2_TD1 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) + /* (U10) PRG1_PRU1_GPO13.PRG1_RGMII2_TD2 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) + /* (AA11) PRG1_PRU1_GPO14.PRG1_RGMII2_TD3 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) + /* (Y10) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 2) + /* (Y11) PRG1_PRU1_GPO15.PRG1_RGMII2_TX_CTL */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) + >; + }; + + pwm_fan_pins: pwm-fan-pins { + pinctrl-single,pins = < + /* (T19) GPMC0_BE1n.EHRPWM5_A */ + AM64X_IOPAD(0x0094, PIN_OUTPUT, 3) + /* (C14) SPI1_CLK.GPIO1_49 - FAN_RPM */ + AM64X_IOPAD(0x0224, PIN_INPUT, 7) + >; + }; + + pwm_fan_reg_pins: pwm-fan-reg-pins { + pinctrl-single,pins = < + /* (D14) SPI1_CS1.GPIO1_48 - FAN_PWR */ + AM64X_IOPAD(0x0220, PIN_OUTPUT, 7) + >; + }; +}; + +&mcu_pmx0 { + mcu_gpio_keys_pins: mcu-gpio-keys-pins { + pinctrl-single,pins = < + /* (A7) MCU_SPI1_CS0.MCU_GPIO0_5 */ + AM64X_MCU_IOPAD(0x0014, PIN_INPUT, 7) + >; + }; + + mcu_gpio_leds_pins: mcu-gpio-leds-pins { + pinctrl-single,pins = < + /* (C7) MCU_SPI1_D0.MCU_GPIO0_8 */ + AM64X_MCU_IOPAD(0x0020, PIN_OUTPUT, 7) + /* (C8) MCU_SPI1_D1.MCU_GPIO0_9 */ + AM64X_MCU_IOPAD(0x0024, PIN_OUTPUT, 7) + >; + }; + + mcu_gpio0_pins: mcu-gpio0-pins { + pinctrl-single,pins = < + /* (E8) MCU_UART0_RTSn.MCU_GPIO0_0 */ + AM64X_MCU_IOPAD(0x0034, PIN_INPUT, 7) + /* (D8) MCU_UART0_CTSn.MCU_GPIO0_1 */ + AM64X_MCU_IOPAD(0x0030, PIN_INPUT, 7) + /* (B7) MCU_SPI1_CS1.MCU_GPIO0_6 */ + AM64X_MCU_IOPAD(0x0018, PIN_INPUT, 7) + /* (D7) MCU_SPI1_CLK.MCU_GPIO0_7 */ + AM64X_MCU_IOPAD(0x001c, PIN_INPUT, 7) + /* (A11) MCU_I2C1_SCL.MCU_GPIO0_20 */ + AM64X_MCU_IOPAD(0x0050, PIN_INPUT, 7) + /* (B10) MCU_I2C1_SDA.MCU_GPIO0_21 */ + AM64X_MCU_IOPAD(0x0054, PIN_INPUT, 7) + >; + }; + + mcu_i2c0_pins: mcu-i2c0-pins { + pinctrl-single,pins = < + /* (E9) MCU_I2C0_SCL */ + AM64X_MCU_IOPAD(0x0048, PIN_INPUT, 0) + /* (A10) MCU_I2C0_SDA */ + AM64X_MCU_IOPAD(0x004c, PIN_INPUT, 0) + >; + }; + + mcu_spi0_pins: mcu-spi0-pins { + pinctrl-single,pins = < + /* (E6) MCU_SPI0_CLK */ + AM64X_MCU_IOPAD(0x0008, PIN_OUTPUT, 0) + /* (D6) MCU_SPI0_CS0 */ + AM64X_MCU_IOPAD(0x0000, PIN_OUTPUT, 0) + /* (C6) MCU_SPI0_CS1 */ + AM64X_MCU_IOPAD(0x0004, PIN_OUTPUT, 0) + /* (E7) MCU_SPI0_D0 */ + AM64X_MCU_IOPAD(0x000c, PIN_OUTPUT, 0) + /* (B6) MCU_SPI0_D1 */ + AM64X_MCU_IOPAD(0x0010, PIN_INPUT, 0) + >; + }; + + mcu_uart0_pins: mcu-uart0-pins { + pinctrl-single,pins = < + /* (A9) MCU_UART0_RXD */ + AM64X_MCU_IOPAD(0x0028, PIN_INPUT, 0) + /* (A8) MCU_UART0_TXD */ + AM64X_MCU_IOPAD(0x002c, PIN_OUTPUT, 0) + >; + }; + + mcu_uart1_pins: mcu-uart1-pins { + pinctrl-single,pins = < + /* (B8) MCU_UART1_CTSn */ + AM64X_MCU_IOPAD(0x0040, PIN_INPUT, 0) + /* (B9) MCU_UART1_RTSn */ + AM64X_MCU_IOPAD(0x0044, PIN_OUTPUT, 0) + /* (C9) MCU_UART1_RXD */ + AM64X_MCU_IOPAD(0x0038, PIN_INPUT, 0) + /* (D9) MCU_UART1_TXD */ + AM64X_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) + >; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi new file mode 100644 index 000000000000..5e9012107afa --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (c) 2022-2023 TQ-Systems GmbH , D-82229 Seefeld, Germany. + */ + +#include "k3-am642.dtsi" + +/ { + aliases { + i2c0 = &main_i2c0; + mmc0 = &sdhci0; + spi0 = &ospi0; + }; + + memory@80000000 { + device_type = "memory"; + /* 1G RAM - default variant */ + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; + + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + alignment = <0x1000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; + }; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; + + tmp1075: temperature-sensor@4a { + compatible = "ti,tmp1075"; + reg = <0x4a>; + }; + + eeprom0: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + read-only; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <12500>; + }; + + eeprom1: eeprom@54 { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster6 { + status = "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <84000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Filled by bootloader */ + }; + }; +}; + +&sdhci0 { + non-removable; + disable-wp; + no-sdio; + no-sd; + ti,driver-strength-ohm = <50>; +}; + +&main_pmx0 { + main_i2c0_pins: main-i2c0-pins { + pinctrl-single,pins = < + /* (A18) I2C0_SCL */ + AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) + /* (B18) I2C0_SDA */ + AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) + >; + }; + + ospi0_pins: ospi0-pins { + pinctrl-single,pins = < + /* (N20) OSPI0_CLK */ + AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) + /* (L19) OSPI0_CSn0 */ + AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) + /* (M19) OSPI0_D0 */ + AM64X_IOPAD(0x000c, PIN_INPUT, 0) + /* (M18) OSPI0_D1 */ + AM64X_IOPAD(0x0010, PIN_INPUT, 0) + /* (M20) OSPI0_D2 */ + AM64X_IOPAD(0x0014, PIN_INPUT, 0) + /* (M21) OSPI0_D3 */ + AM64X_IOPAD(0x0018, PIN_INPUT, 0) + /* (P21) OSPI0_D4 */ + AM64X_IOPAD(0x001c, PIN_INPUT, 0) + /* (P20) OSPI0_D5 */ + AM64X_IOPAD(0x0020, PIN_INPUT, 0) + /* (N18) OSPI0_D6 */ + AM64X_IOPAD(0x0024, PIN_INPUT, 0) + /* (M17) OSPI0_D7 */ + AM64X_IOPAD(0x0028, PIN_INPUT, 0) + /* (N19) OSPI0_DQS */ + AM64X_IOPAD(0x0008, PIN_INPUT, 0) + >; + }; +}; From 5e52cf6bf3c7216de1ee4a74ee002cb99b3f6c11 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Thu, 27 Jul 2023 15:21:20 +0200 Subject: [PATCH 19/68] arm64: dts: ti: k3-am64-tqma64xxl-mbax4xxl: add SD-card and WLAN overlays As the SD-card and WLAN are connected to the same SDHC interface (with a GPIO-controlled mux), they are mutually exclusive. Provide Device Tree overlays for both configurations. Signed-off-by: Matthias Schiffer Link: https://lore.kernel.org/r/8ff8a6f1fdbe6ebb478f88bb0737628054c43c5b.1690463382.git.matthias.schiffer@ew.tq-group.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 8 +++++++ .../ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso | 22 +++++++++++++++++++ .../ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso | 22 +++++++++++++++++++ 3 files changed, 52 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso create mode 100644 arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 32722e49c77f..437a3d7e8e3a 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -29,6 +29,14 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb +k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ + k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo +k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ + k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo + +dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb + # Boards with AM65x SoC k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso b/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso new file mode 100644 index 000000000000..79ed19c6c0e9 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2023 TQ-Systems GmbH , D-82229 Seefeld, Germany. + */ + +/dts-v1/; +/plugin/; + +&sdhci1 { + vmmc-supply = <®_sd>; + no-sdio; + status = "okay"; +}; + +&main_gpio0 { + line43-hog { + gpio-hog; + gpios = <43 0>; + line-name = "MMC1_CTRL"; + output-low; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso b/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso new file mode 100644 index 000000000000..32596a84b7ba --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2023 TQ-Systems GmbH , D-82229 Seefeld, Germany. + */ + +/dts-v1/; +/plugin/; + +&sdhci1 { + mmc-pwrseq = <&wifi_pwrseq>; + no-sd; + status = "okay"; +}; + +&main_gpio0 { + line43-hog { + gpio-hog; + gpios = <43 0>; + line-name = "MMC1_CTRL"; + output-high; + }; +}; From 7a649518c13bc6cbbc83f27eda9d1b05b45fe3ac Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 1 Aug 2023 23:03:47 -0500 Subject: [PATCH 20/68] arm64: dts: ti: k3: Fixup remaining pin group node names for make dtbs checks Fix up outstanding pingroup node names to be compliant with the upcoming pinctrl-single schema. Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230802040347.2264339-1-nm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 2 +- arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 2 +- arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts | 4 ++-- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 4 ++-- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index 7c1402b0fa2d..e07ddff22e07 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -432,7 +432,7 @@ AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ >; }; - gbe_pmx_obsclk: gbe-pmx-clk-default { + gbe_pmx_obsclk: gbe-pmx-obsclk-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (B8) MCU_SPI0_CS1.MCU_OBSCLK0 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi index e73458ca6900..e9419c4fe605 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi @@ -10,7 +10,7 @@ */ &main_pmx0 { - cp2102n_reset_pin_default: cp2102n-reset-pin-default { + cp2102n_reset_pin_default: cp2102n-reset-default-pins { pinctrl-single,pins = < /* (AF12) GPIO1_24, used as cp2102 reset */ AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 973a89b04a22..734b051c9700 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -192,7 +192,7 @@ AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */ >; }; - wkup_pca554_default: wkup-pca554-default { + wkup_pca554_default: wkup-pca554-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts index cbe44634914f..774eb14ac907 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts @@ -33,7 +33,7 @@ AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */ >; }; - main_bkey_pcie_reset: main-bkey-pcie-reset { + main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */ >; @@ -46,7 +46,7 @@ AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */ >; }; - main_m2_pcie_mux_control: main-m2-pcie-mux-control { + main_m2_pcie_mux_control: main-m2-pcie-mux-control-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */ AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */ diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 21ad49cfa7ee..a8172ba55f4b 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -273,7 +273,7 @@ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ >; }; - mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-pins0-default { + mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ @@ -289,7 +289,7 @@ J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */ }; &wkup_pmx3 { - mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-pins1-default { + mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-default-pins-1 { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */ >; From 108f61e03963a3a019486fd80cc84d5db5c204d0 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Wed, 2 Aug 2023 09:36:34 +0200 Subject: [PATCH 21/68] arm64: dts: ti: k3-am62: Add MCU MCAN nodes On AM62x there are no hardware interrupts routed to A53 GIC interrupt controller for MCU MCAN IPs, so MCU MCAN nodes were omitted from MCU dtsi. Timer polling was introduced in commits [1][2] so now add MCU MCAN nodes to the MCU dtsi for the Cortex A53. [1] commit b382380c0d2d ("can: m_can: Add hrtimer to generate software interrupt") [2] commit bb410c03b999 ("dt-bindings: net: can: Remove interrupt properties for MCAN") [fd: fixed labels to match datasheet numbering, revised commit message, fixed reg/reg-names order] Signed-off-by: Judith Mendez Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20230802073635.11290-2-francesco@dolcini.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi index 19fc38157d94..80a3e1db26a9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -147,4 +147,28 @@ mcu_rti0: watchdog@4880000 { /* Tightly coupled to M4F */ status = "reserved"; }; + + mcu_mcan0: can@4e08000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e08000 0x00 0x200>, + <0x00 0x4e00000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcu_mcan1: can@4e18000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e18000 0x00 0x200>, + <0x00 0x4e10000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; }; From 7480cea33b4c36aeffe592eb6f151bc9974fee70 Mon Sep 17 00:00:00 2001 From: Hiago De Franco Date: Wed, 2 Aug 2023 09:36:35 +0200 Subject: [PATCH 22/68] arm64: dts: ti: k3-am625-verdin: enable CAN_2 Add Verdin CAN_2 (TI AM62 MCU_MCAN0) and enable it on the Yavia, Dahlia and Verdin Development board. Signed-off-by: Hiago De Franco Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20230802073635.11290-3-francesco@dolcini.it Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am62-verdin-dahlia.dtsi | 5 +++++ .../arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi | 5 +++++ .../boot/dts/ti/k3-am62-verdin-yavia.dtsi | 5 +++++ arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 19 +++++++++++++++++-- 4 files changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi index 3abd8d1d6761..33c8f6ffaa30 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi @@ -115,6 +115,11 @@ &mcu_i2c0 { status = "okay"; }; +/* Verdin CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + /* Verdin UART_4 */ &mcu_uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi index 846caee7dfa4..8205081fda33 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi @@ -144,6 +144,11 @@ &mcu_i2c0 { status = "okay"; }; +/* Verdin CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + /* Verdin UART_4 */ &mcu_uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi index cb11d6e7f525..c685df7deaee 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi @@ -167,6 +167,11 @@ &mcu_i2c0 { status = "okay"; }; +/* Verdin CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + /* Verdin UART_4 */ &mcu_uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index 57dd061911ab..12dd1d64eac9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -19,6 +19,8 @@ chosen { }; aliases { + can0 = &main_mcan0; + can1 = &mcu_mcan0; ethernet0 = &cpsw_port1; ethernet1 = &cpsw_port2; i2c0 = &main_i2c0; @@ -732,6 +734,14 @@ AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ /* SODIMM 57 */ >; }; + /* Verdin CAN_2 */ + pinctrl_mcu_mcan0: mcu-mcan0-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ /* SODIMM 26 */ + AM62X_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ /* SODIMM 24 */ + >; + }; + /* Verdin UART_4 - Reserved to Cortex-M4 */ pinctrl_mcu_uart0: mcu-uart0-default-pins { pinctrl-single,pins = < @@ -1238,8 +1248,6 @@ &main_mcan0 { status = "disabled"; }; -/* Verdin CAN_2 - Reserved to Cortex-M4 */ - /* Verdin SPI_1 */ &main_spi1 { pinctrl-names = "default"; @@ -1333,6 +1341,13 @@ &mcu_gpio0 { ""; }; +/* Verdin CAN_2 */ +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_mcan0>; + status = "disabled"; +}; + /* Verdin UART_4 - Cortex-M4 UART */ &mcu_uart0 { pinctrl-names = "default"; From 5a5cf3bdda04fe72440aa837c9451410d62ffa2f Mon Sep 17 00:00:00 2001 From: Ravi Gunasekaran Date: Tue, 25 Jul 2023 16:06:51 +0530 Subject: [PATCH 23/68] arm64: dts: ti: k3-am62a7-sk: Enable dual role support for Type-C port USB0 is interfaced with a Type-C DRP connector and is managed via a USB PD controller. Add support for the Type-C port with dual data and power sink role. Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230725103651.1612-1-r-gunasekaran@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 33 +++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index d2cca6182738..cff283c75f8e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -226,6 +226,24 @@ &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + + typec_pd0: usb-power-controller@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + port { + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; }; &main_i2c1 { @@ -290,6 +308,21 @@ &main_uart1 { status = "reserved"; }; +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + usb-role-switch; + + port { + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + &usbss1 { status = "okay"; }; From b9d801dbb2d5cb796dce32ffcee63fba83f72841 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 2 Aug 2023 12:45:19 -0500 Subject: [PATCH 24/68] arm64: dts: ti: k3-am62a: Remove syscon compatible from epwm_tbclk The other instances have been fixed, but AM62a seems to have been missed, fix this here. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230802174521.236255-1-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 8397cb80f559..3198af08fb9f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -56,7 +56,7 @@ phy_gmii_sel: phy@4044 { }; epwm_tbclk: clock-controller@4130 { - compatible = "ti,am62-epwm-tbclk", "syscon"; + compatible = "ti,am62-epwm-tbclk"; reg = <0x4130 0x4>; #clock-cells = <1>; }; From a57ba56bca42fa484bec916f7a88a3dc03d6cbdf Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 2 Aug 2023 12:45:20 -0500 Subject: [PATCH 25/68] arm64: dts: ti: k3-am64: Merge the two main_conf nodes There are two nodes representing the same register space, this looks to have been created by some merge or copy/paste error. Remove the second instance of this node and move its children into the first instance. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230802174521.236255-2-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 42 ++++++++++-------------- 1 file changed, 17 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index d3dd8c426dad..e27eb2e585f1 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -44,11 +44,28 @@ main_conf: syscon@43000000 { #size-cells = <1>; ranges = <0x0 0x0 0x43000000 0x20000>; + chipid@14 { + compatible = "ti,am654-chipid"; + reg = <0x00000014 0x4>; + }; + serdes_ln_ctrl: mux-controller { compatible = "mmio-mux"; #mux-control-cells = <1>; mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ }; + + phy_gmii_sel: phy@4044 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4044 0x8>; + #phy-cells = <1>; + }; + + epwm_tbclk: clock@4140 { + compatible = "ti,am64-epwm-tbclk"; + reg = <0x4130 0x4>; + #clock-cells = <1>; + }; }; gic500: interrupt-controller@1800000 { @@ -203,31 +220,6 @@ main_pmx0: pinctrl@f4000 { pinctrl-single,function-mask = <0xffffffff>; }; - main_conf: syscon@43000000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x43000000 0x00 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x43000000 0x20000>; - - chipid@14 { - compatible = "ti,am654-chipid"; - reg = <0x00000014 0x4>; - }; - - phy_gmii_sel: phy@4044 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4044 0x8>; - #phy-cells = <1>; - }; - - epwm_tbclk: clock@4140 { - compatible = "ti,am64-epwm-tbclk"; - reg = <0x4130 0x4>; - #clock-cells = <1>; - }; - }; - main_timer0: timer@2400000 { compatible = "ti,am654-timer"; reg = <0x00 0x2400000 0x00 0x400>; From f6a5b651144096bfccda41b62861a7dde87ec287 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 2 Aug 2023 12:45:21 -0500 Subject: [PATCH 26/68] arm64: dts: ti: k3: Fix epwm_tbclk node name to generic name The name "clock" is not allowed for nodes, use "clock-controller" to remove the DTS check warning. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230802174521.236255-3-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 33b6aadc9083..ef90b2bc81eb 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -55,7 +55,7 @@ phy_gmii_sel: phy@4044 { #phy-cells = <1>; }; - epwm_tbclk: clock@4130 { + epwm_tbclk: clock-controller@4130 { compatible = "ti,am62-epwm-tbclk"; reg = <0x4130 0x4>; #clock-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index e27eb2e585f1..4e3e450e4e4c 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -61,7 +61,7 @@ phy_gmii_sel: phy@4044 { #phy-cells = <1>; }; - epwm_tbclk: clock@4140 { + epwm_tbclk: clock-controller@4140 { compatible = "ti,am64-epwm-tbclk"; reg = <0x4130 0x4>; #clock-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 350beddc3d3c..d08f086d7d01 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -502,7 +502,7 @@ dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { reg = <0x000041e0 0x14>; }; - ehrpwm_tbclk: clock@4140 { + ehrpwm_tbclk: clock-controller@4140 { compatible = "ti,am654-ehrpwm-tbclk"; reg = <0x4140 0x18>; #clock-cells = <1>; From a1f62d114c8ce64d1273c308228b43de8bf45171 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Thu, 3 Aug 2023 13:47:59 +0530 Subject: [PATCH 27/68] arm64: dts: ti: k3-j721s2-main: Add DSS node Add DSS node for J721S2 SoC. DSS IP in J721S2 is same as DSS IP in J721E, so same compatible is used. Signed-off-by: Jayesh Choudhary Reviewed-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20230803081800.368582-2-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 6e3fb86cc88e..dc7920a35237 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1642,4 +1642,50 @@ main_spi7: spi@2170000 { clocks = <&k3_clks 346 1>; status = "disabled"; }; + + dss: dss@4a00000 { + compatible = "ti,j721e-dss"; + reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ + <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ + <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ + <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ + <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ + <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ + <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ + <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ + <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ + <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ + <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ + <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ + <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ + <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ + <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ + <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ + <0x00 0x04af0000 0x00 0x10000>; /* wb */ + reg-names = "common_m", "common_s0", + "common_s1", "common_s2", + "vidl1", "vidl2","vid1","vid2", + "ovr1", "ovr2", "ovr3", "ovr4", + "vp1", "vp2", "vp3", "vp4", + "wb"; + clocks = <&k3_clks 158 0>, + <&k3_clks 158 2>, + <&k3_clks 158 5>, + <&k3_clks 158 14>, + <&k3_clks 158 18>; + clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + interrupts = , + , + , + ; + interrupt-names = "common_m", + "common_s0", + "common_s1", + "common_s2"; + status = "disabled"; + + dss_ports: ports { + }; + }; }; From dfe5ccf2359f70d36bf7e64711a46fbff2126ca8 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Thu, 3 Aug 2023 13:48:00 +0530 Subject: [PATCH 28/68] arm64: dts: ti: k3-am68-sk-base-board: Add HDMI support AM68-SK has an HDMI port. The bridge used is TI-TFP410. Add support to enable the connection: DSS => TI TFP410 DPI-to-DVI Bridge => HDMI connector Signed-off-by: Jayesh Choudhary Reviewed-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20230803081800.368582-3-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am68-sk-base-board.dts | 138 ++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index a8172ba55f4b..e6e4133d1e9b 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -122,6 +122,52 @@ transceiver4: can-phy3 { #phy-cells = <0>; max-bitrate = <5000000>; }; + + connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_pins_default>; + ddc-i2c-bus = <&mcu_i2c1>; + /* HDMI_HPD */ + hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + bridge-dvi { + compatible = "ti,tfp410"; + /* HDMI_PDn */ + powerdown-gpios = <&exp2 0 GPIO_ACTIVE_LOW>; + ti,deskew = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_out0>; + pclk-sample = <1>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; }; &main_pmx0 { @@ -202,6 +248,45 @@ J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */ J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */ >; }; + + dss_vout0_pins_default: dss-vout0-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */ + J721S2_IOPAD(0x070, PIN_OUTPUT, 2) /* (R27) MCAN1_RX.VOUT0_DATA1 */ + J721S2_IOPAD(0x04c, PIN_OUTPUT, 2) /* (V27) MCASP1_AXR1.VOUT0_DATA10 */ + J721S2_IOPAD(0x048, PIN_OUTPUT, 2) /* (AB27) MCASP0_AXR2.VOUT0_DATA11 */ + J721S2_IOPAD(0x044, PIN_OUTPUT, 2) /* (Y26) MCASP0_AXR1.VOUT0_DATA12 */ + J721S2_IOPAD(0x040, PIN_OUTPUT, 2) /* (AC28) MCASP0_AXR0.VOUT0_DATA13 */ + J721S2_IOPAD(0x03c, PIN_OUTPUT, 2) /* (U27) MCASP0_AFSX.VOUT0_DATA14 */ + J721S2_IOPAD(0x038, PIN_OUTPUT, 2) /* (AB28) MCASP0_ACLKX.VOUT0_DATA15 */ + J721S2_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AD28) EXT_REFCLK1.VOUT0_DATA16 */ + J721S2_IOPAD(0x030, PIN_OUTPUT, 2) /* (T26) GPIO0_12.VOUT0_DATA17 */ + J721S2_IOPAD(0x02c, PIN_OUTPUT, 2) /* (V23) GPIO0_11.VOUT0_DATA18 */ + J721S2_IOPAD(0x028, PIN_OUTPUT, 2) /* (AB24) MCAN16_RX.VOUT0_DATA19 */ + J721S2_IOPAD(0x07c, PIN_OUTPUT, 2) /* (T27) MCASP0_AXR3.VOUT0_DATA2 */ + J721S2_IOPAD(0x024, PIN_OUTPUT, 2) /* (Y28) MCAN16_TX.VOUT0_DATA20 */ + J721S2_IOPAD(0x020, PIN_OUTPUT, 2) /* (AA23) MCAN15_RX.VOUT0_DATA21 */ + J721S2_IOPAD(0x01c, PIN_OUTPUT, 2) /* (Y24) MCAN15_TX.VOUT0_DATA22 */ + J721S2_IOPAD(0x018, PIN_OUTPUT, 2) /* (W23) MCAN14_RX.VOUT0_DATA23 */ + J721S2_IOPAD(0x068, PIN_OUTPUT, 2) /* (U28) MCAN0_RX.VOUT0_DATA3 */ + J721S2_IOPAD(0x064, PIN_OUTPUT, 2) /* (W28) MCAN0_TX.VOUT0_DATA4 */ + J721S2_IOPAD(0x060, PIN_OUTPUT, 2) /* (AC27) MCASP2_AXR1.VOUT0_DATA5 */ + J721S2_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AA26) MCASP2_AXR0.VOUT0_DATA6 */ + J721S2_IOPAD(0x058, PIN_OUTPUT, 2) /* (AA27) MCASP2_AFSX.VOUT0_DATA7 */ + J721S2_IOPAD(0x054, PIN_OUTPUT, 2) /* (Y27) MCASP2_ACLKX.VOUT0_DATA8 */ + J721S2_IOPAD(0x050, PIN_OUTPUT, 2) /* (W27) MCASP1_AXR2.VOUT0_DATA9 */ + J721S2_IOPAD(0x084, PIN_OUTPUT, 2) /* (AA28) MCASP0_AXR5.VOUT0_DE */ + J721S2_IOPAD(0x080, PIN_OUTPUT, 2) /* (U26) MCASP0_AXR4.VOUT0_HSYNC */ + J721S2_IOPAD(0x078, PIN_OUTPUT, 2) /* (Y25) MCAN2_RX.VOUT0_PCLK */ + J721S2_IOPAD(0x088, PIN_OUTPUT, 2) /* (AD27) MCASP0_AXR6.VOUT0_VP0_VSYNC */ + >; + }; + + hdmi_hpd_pins_default: hdmi-hpd-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x000, PIN_INPUT, 7) /* (AG24) EXTINTN.GPIO0_0 */ + >; + }; }; &wkup_pmx2 { @@ -373,6 +458,23 @@ &mcu_i2c0 { clock-frequency = <400000>; }; +&mcu_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c1_pins_default>; + /* i2c1 is used for DVI DDC, so we need to use 100kHz */ + clock-frequency = <100000>; + + exp2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "HDMI_PDn","HDMI_LS_OE", + "DP0_3V3_EN","eDP_ENABLE"; + }; +}; + &main_sdhci0 { /* Unused */ status = "disabled"; @@ -433,3 +535,39 @@ &main_mcan7 { pinctrl-0 = <&main_mcan7_pins_default>; phys = <&transceiver4>; }; + +&dss { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dss_vout0_pins_default>; + /* + * These clock assignments are chosen to enable the following outputs: + * + * VP0 - DisplayPort SST + * VP1 - DPI0 + * VP2 - DSI + * VP3 - DPI1 + */ + assigned-clocks = <&k3_clks 158 2>, + <&k3_clks 158 5>, + <&k3_clks 158 14>, + <&k3_clks 158 18>; + assigned-clock-parents = <&k3_clks 158 3>, + <&k3_clks 158 7>, + <&k3_clks 158 16>, + <&k3_clks 158 22>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* HDMI */ + port@1 { + reg = <1>; + + dpi_out0: endpoint { + remote-endpoint = <&tfp410_in>; + }; + }; +}; From a0592af49737dfadd0bfcd896dccd34403fdfdd2 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Fri, 4 Aug 2023 17:01:37 -0500 Subject: [PATCH 29/68] arm64: dts: ti: k3-am62a7: Add MCU MCAN nodes On AM62ax there are no hardware interrupts routed to A53 GIC interrupt controller for MCU MCAN IPs, so MCU MCAN nodes were omitted from MCU dtsi. Timer polling was introduced in commits [1][2] enabling 3x MCAN on AM62ax, so now add MCU MCAN nodes to the mcu dtsi for the Cortex A53. [1] commit b382380c0d2d ("can: m_can: Add hrtimer to generate software interrupt") [2] commit bb410c03b999 ("dt-bindings: net: can: Remove interrupt properties for MCAN") Signed-off-by: Judith Mendez Link: https://lore.kernel.org/r/20230804220137.425442-1-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi index 04599762c2b7..a6d16a94088c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -143,4 +143,28 @@ mcu_rti0: watchdog@4880000 { /* Tightly coupled to M4F */ status = "reserved"; }; + + mcu_mcan0: can@4e08000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e08000 0x00 0x200>, + <0x00 0x4e00000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcu_mcan1: can@4e18000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e18000 0x00 0x200>, + <0x00 0x4e10000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; }; From f10f836ccfea21ae3ad3066eb9576625f1acdea2 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Wed, 2 Aug 2023 17:11:26 +0530 Subject: [PATCH 30/68] arm64: dts: ti: k3-j784s4-evm: Correct Pin mux offset for ospi After splitting wkup_pmx pin mux for J784S4 into four regions. Pin mux offset for OSPI nodes were not updated to align with new regions, due to this while setting ospi pin muxes out of range error was seen. Pin mux offsets for OSPI nodes are corrected in this patch. Fixes: 14462bd0b247 ("arm64: dts: ti: k3-j784s4: Fix wakeup pinmux range and pinctrl node offsets") Signed-off-by: Udit Kumar Tested-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230802114126.162445-1-u-kumar1@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 29 +++++++++++++++--------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 1e38a8f1bec5..edc1009b2d1e 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -379,21 +379,28 @@ J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ - J784S4_WKUP_IOPAD(0x03c, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_CSn3.MCU_OSPI0_ECC_FAIL */ - J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_CSn2.MCU_OSPI0_RESET_OUT0 */ + >; + }; +}; + +&wkup_pmx1 { + mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ >; }; mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ - J784S4_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ - J784S4_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ - J784S4_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ - J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ - J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ - J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ - J784S4_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ + J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ + J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ + J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ >; }; }; @@ -441,7 +448,7 @@ &fss { &ospi0 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; flash@0 { compatible = "jedec,spi-nor"; From 06c4e7aa4af0682910ea52d7c23d85f59ea7dcc6 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Fri, 4 Aug 2023 13:23:41 +0530 Subject: [PATCH 31/68] arm64: dts: ti: k3-j721s2: correct pinmux offset for ospi Due to non-addressable regions in J721S2 SOC wkup_pmx was split into four regions from wkup_pmx0 to wkup_pmx3. Correcting OSPI1 pin mux, which now falls under wkup_pmx1. Along with that removing unused pin mux for OSPI-0. Fixes: 6bc829ceea41 ("arm64: dts: ti: k3-j721s2: Fix wkup pinmux range") Signed-off-by: Udit Kumar Reviewed-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230804075341.3858488-1-u-kumar1@ti.com Signed-off-by: Nishanth Menon --- .../dts/ti/k3-j721s2-common-proc-board.dts | 19 ++++++++++--------- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 3 --- 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 20b32563c0ed..e81ef8a7a8a2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -282,18 +282,19 @@ J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ >; }; +}; +&wkup_pmx1 { mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ - J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ - J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ - J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ - J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ - J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ - J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ - J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ - J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ >; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index 594766482071..a4006f328027 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -56,9 +56,6 @@ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ - J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ - J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ - J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ From 6111ac92f93415eaa680e7ef43ee4fa78b1eb7f2 Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Mon, 7 Aug 2023 22:21:56 +0200 Subject: [PATCH 32/68] arm64: dts: ti: k3-am62: Enable AUDIO_REFCLKx On AM62-based SoCs the AUDIO_REFCLKx clocks can be used as an input to external peripherals when configured through CTRL_MMR, so add the clock nodes. Signed-off-by: Jai Luthra Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20230807202159.13095-2-francesco@dolcini.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index ef90b2bc81eb..5f19ef46d44c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -60,6 +60,24 @@ epwm_tbclk: clock-controller@4130 { reg = <0x4130 0x4>; #clock-cells = <1>; }; + + audio_refclk0: clock-controller@82e0 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e0 0x4>; + clocks = <&k3_clks 157 0>; + assigned-clocks = <&k3_clks 157 0>; + assigned-clock-parents = <&k3_clks 157 8>; + #clock-cells = <0>; + }; + + audio_refclk1: clock-controller@82e4 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e4 0x4>; + clocks = <&k3_clks 157 10>; + assigned-clocks = <&k3_clks 157 10>; + assigned-clock-parents = <&k3_clks 157 18>; + #clock-cells = <0>; + }; }; dmss: bus@48000000 { From 0bf6d62cb5173d85113f4f759cad3191845e15fa Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Mon, 7 Aug 2023 22:21:57 +0200 Subject: [PATCH 33/68] arm64: dts: ti: verdin-am62: Set I2S_1 MCLK rate Set AUDIO_EXT_REFCLK1, used as I2S_1_MCLK on Verdin AM62 family, to 25MHz (this is the only valid option according to TI [1]). [1] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1188051/am625-audio_ext_refclk1-clock-output---dts-support/4476322#4476322 Reviewed-by: Jai Luthra Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20230807202159.13095-3-francesco@dolcini.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index 12dd1d64eac9..5db9ef2dc7e5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -768,6 +768,11 @@ AM62X_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ /* SODIM }; }; +/* VERDIN I2S_1_MCLK */ +&audio_refclk1 { + assigned-clock-rates = <25000000>; +}; + &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rgmii1>; From c90658201cbeb7aae072ab3da4e255f47d9e25b3 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Mon, 7 Aug 2023 22:21:58 +0200 Subject: [PATCH 34/68] arm64: dts: ti: verdin-am62: dev: add sound card Add NAU8822 based analog sound card to Development carrier board. Reviewed-by: Jai Luthra Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20230807202159.13095-4-francesco@dolcini.it Signed-off-by: Nishanth Menon --- .../arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi index 8205081fda33..6701cb8974bb 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi @@ -8,6 +8,42 @@ * https://www.toradex.com/products/carrier-board/verdin-development-board-kit */ +/ { + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,name = "verdin-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + codec_dai: simple-audio-card,codec { + clocks = <&audio_refclk1>; + sound-dai = <&nau8822_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + }; + }; +}; + /* Verdin ETHs */ &cpsw3g { pinctrl-names = "default"; @@ -65,6 +101,15 @@ &main_gpio0 { &main_i2c1 { status = "okay"; + /* Audio Codec */ + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s1_mclk>; + #sound-dai-cells = <0>; + }; + /* IO Expander */ gpio_expander_21: gpio@21 { compatible = "nxp,pcal6416"; From f5bf894c865b26ea8ec43186e87bb08d092b6fa1 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Mon, 7 Aug 2023 22:21:59 +0200 Subject: [PATCH 35/68] arm64: dts: ti: verdin-am62: dahlia: add sound card Add WM8904 based analog sound card to Dahlia carrier board. Reviewed-by: Jai Luthra Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20230807202159.13095-5-francesco@dolcini.it Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am62-verdin-dahlia.dtsi | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi index 33c8f6ffaa30..013357d17d48 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi @@ -8,6 +8,43 @@ * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit */ +/ { + reg_1v8_sw: regulator-1v8-sw { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-carrier +V1.8_SW"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,name = "verdin-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Headphone Jack", "MICBIAS", + "IN1L", "Headphone Jack"; + simple-audio-card,widgets = + "Microphone", "Headphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + clocks = <&audio_refclk1>; + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + }; + }; +}; + /* Verdin ETHs */ &cpsw3g { status = "okay"; @@ -46,6 +83,22 @@ &main_gpio0 { &main_i2c1 { status = "okay"; + /* Audio Codec */ + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s1_mclk>; + #sound-dai-cells = <0>; + clocks = <&audio_refclk1>; + clock-names = "mclk"; + AVDD-supply = <®_1v8_sw>; + CPVDD-supply = <®_1v8_sw>; + DBVDD-supply = <®_1v8_sw>; + DCVDD-supply = <®_1v8_sw>; + MICVDD-supply = <®_1v8_sw>; + }; + /* Current measurement into module VCC */ hwmon@40 { compatible = "ti,ina219"; From 8be3ac2d8bd77bb9cb9ddbb7a545decf9f5e4181 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Wed, 9 Aug 2023 10:31:08 +0530 Subject: [PATCH 36/68] arm64: dts: ti: k3-j784s4-evm: Correct Pin mux offset for ADC After splitting wkup_pmx pin mux for J784S4 into four regions. Pin mux offset for ADC nodes were not updated to align with new regions, due to this while probing ADC driver out of range error was seen. Pin mux offsets for ADC nodes are corrected in this patch. Fixes: 14462bd0b247 ("arm64: dts: ti: k3-j784s4: Fix wakeup pinmux range and pinctrl node offsets") Signed-off-by: Udit Kumar Reviewed-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230809050108.751164-1-u-kumar1@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 32 ++++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index edc1009b2d1e..b4ffa720209c 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -340,27 +340,27 @@ J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ mcu_adc0_pins_default: mcu-adc0-default-pins { pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ - J784S4_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ - J784S4_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ - J784S4_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ - J784S4_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ - J784S4_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ - J784S4_WKUP_IOPAD(0x14c, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ - J784S4_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ + J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ + J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ + J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ + J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ + J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ + J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ + J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ + J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ >; }; mcu_adc1_pins_default: mcu-adc1-default-pins { pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ - J784S4_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ - J784S4_WKUP_IOPAD(0x15c, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ - J784S4_WKUP_IOPAD(0x160, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ - J784S4_WKUP_IOPAD(0x164, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ - J784S4_WKUP_IOPAD(0x168, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ - J784S4_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ - J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ + J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ + J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ + J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ + J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ + J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ + J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ + J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ + J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ >; }; }; From 4f1e869915b7a8c48a0501ad0b102002013a7b7a Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Wed, 9 Aug 2023 23:29:31 +0530 Subject: [PATCH 37/68] dt-bindings: soc: ti: k3-ringacc: Describe cfg reg region RINGACC module on K3 SoCs have CFG register region which is usually configured by a Device Management firmware. But certain entities such as bootloader (like U-Boot) may have to access them directly. Describe this region in the binding documentation for completeness of module description. Keep the binding compatible with existing DTS files by requiring first four regions to be present at least. Signed-off-by: Vignesh Raghavendra Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230809175932.2553156-2-vigneshr@ti.com Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml index 22cf9002fee7..a08959c6e072 100644 --- a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml +++ b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml @@ -34,18 +34,22 @@ properties: - const: ti,am654-navss-ringacc reg: + minItems: 4 items: - description: real time registers regions - description: fifos registers regions - description: proxy gcfg registers regions - description: proxy target registers regions + - description: configuration registers region reg-names: + minItems: 4 items: - const: rt - const: fifos - const: proxy_gcfg - const: proxy_target + - const: cfg msi-parent: true @@ -80,8 +84,9 @@ examples: reg = <0x0 0x3c000000 0x0 0x400000>, <0x0 0x38000000 0x0 0x400000>, <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x33000000 0x0 0x40000>, + <0x0 0x31080000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <818>; ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ ti,sci = <&dmsc>; From 702110c2be999c1ad354ca6e14e8583ebcea2462 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Wed, 9 Aug 2023 23:29:32 +0530 Subject: [PATCH 38/68] arm64: dts: ti: k3: Add cfg reg region to ringacc node Add register range of ringacc cfg node to all k3 SoC dtsi files. This is normally under Device Management firmware control but some entities like bootloader have to access directly and thus required to be present in DT. Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20230809175932.2553156-3-vigneshr@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 6 ++++-- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 6 ++++-- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 5 +++-- 10 files changed, 32 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index d08f086d7d01..bc460033a37a 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -776,8 +776,9 @@ ringacc: ringacc@3c000000 { reg = <0x0 0x3c000000 0x0 0x400000>, <0x0 0x38000000 0x0 0x400000>, <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x33000000 0x0 0x40000>, + <0x0 0x31080000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <818>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 7b1f94a89eca..1c16c3cac612 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -197,8 +197,10 @@ mcu_ringacc: ringacc@2b800000 { reg = <0x0 0x2b800000 0x0 0x400000>, <0x0 0x2b000000 0x0 0x400000>, <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", + "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 6eaade5aeb42..e695f7881733 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -267,8 +267,9 @@ main_ringacc: ringacc@3c000000 { reg = <0x00 0x3c000000 0x00 0x400000>, <0x00 0x38000000 0x00 0x400000>, <0x00 0x31120000 0x00 0x100>, - <0x00 0x33000000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x00 0x33000000 0x00 0x40000>, + <0x00 0x31080000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <1024>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index ee7860913c38..04f39b081dc0 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -329,8 +329,10 @@ mcu_ringacc: ringacc@2b800000 { reg = <0x00 0x2b800000 0x00 0x400000>, <0x00 0x2b000000 0x00 0x400000>, <0x00 0x28590000 0x00 0x100>, - <0x00 0x2a500000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x00 0x2a500000 0x00 0x40000>, + <0x00 0x28440000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", + "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 3acd55ffd4ff..68a8abf59d24 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -368,8 +368,9 @@ main_ringacc: ringacc@3c000000 { reg = <0x0 0x3c000000 0x0 0x400000>, <0x0 0x38000000 0x0 0x400000>, <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x33000000 0x0 0x40000>, + <0x0 0x31080000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <1024>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index c1b6f8d7d189..c5ede7bbc263 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -448,8 +448,9 @@ mcu_ringacc: ringacc@2b800000 { reg = <0x0 0x2b800000 0x0 0x400000>, <0x0 0x2b000000 0x0 0x400000>, <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index dc7920a35237..20548d95ab13 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1065,8 +1065,9 @@ main_ringacc: ringacc@3c000000 { reg = <0x0 0x3c000000 0x0 0x400000>, <0x0 0x38000000 0x0 0x400000>, <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x33000000 0x0 0x40000>, + <0x0 0x31080000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <1024>; ti,sci-rm-range-gp-rings = <0x1>; ti,sci = <&sms>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 736ec5fa0ea2..bba2d75324b8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -455,8 +455,9 @@ mcu_ringacc: ringacc@2b800000 { reg = <0x0 0x2b800000 0x0 0x400000>, <0x0 0x2b000000 0x0 0x400000>, <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; ti,sci = <&sms>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index a04c44708a09..29adf3c6a70d 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -966,8 +966,9 @@ main_ringacc: ringacc@3c000000 { reg = <0x00 0x3c000000 0x00 0x400000>, <0x00 0x38000000 0x00 0x400000>, <0x00 0x31120000 0x00 0x100>, - <0x00 0x33000000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x00 0x33000000 0x00 0x40000>, + <0x00 0x31080000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <1024>; ti,sci-rm-range-gp-rings = <0x1>; ti,sci = <&sms>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 740ee794d7b9..42709489c5d1 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -455,8 +455,9 @@ mcu_ringacc: ringacc@2b800000 { reg = <0x00 0x2b800000 0x00 0x400000>, <0x00 0x2b000000 0x00 0x400000>, <0x00 0x28590000 0x00 0x100>, - <0x00 0x2a500000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x00 0x2a500000 0x00 0x40000>, + <0x00 0x28440000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; ti,sci = <&sms>; From 05a1f130101e7a49ff1e8734939facd43596ea26 Mon Sep 17 00:00:00 2001 From: Apelete Seketeli Date: Thu, 10 Aug 2023 01:16:22 +0530 Subject: [PATCH 39/68] arm64: dts: ti: k3-j784s4: Fix interrupt ranges for wkup & main gpio This patch fixes the interrupt range for wakeup and main domain gpio interrupt routers. They were wrongly subtracted by 32 instead of following what is defined in the interrupt map in the TRM (Table 9-35). Link: http://www.ti.com/lit/pdf/spruj52 Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC") Signed-off-by: Apelete Seketeli Signed-off-by: Esteban Blanc Signed-off-by: Jai Luthra Link: https://lore.kernel.org/r/20230810-tps6594-v6-4-2b2e2399e2ef@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 29adf3c6a70d..1b927dbdcc5c 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -60,7 +60,7 @@ main_gpio_intr: interrupt-controller@a00000 { #interrupt-cells = <1>; ti,sci = <&sms>; ti,sci-dev-id = <10>; - ti,interrupt-ranges = <8 360 56>; + ti,interrupt-ranges = <8 392 56>; }; main_pmx0: pinctrl@11c000 { diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 42709489c5d1..920d5b5f1b75 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -107,7 +107,7 @@ wkup_gpio_intr: interrupt-controller@42200000 { #interrupt-cells = <1>; ti,sci = <&sms>; ti,sci-dev-id = <177>; - ti,interrupt-ranges = <16 928 16>; + ti,interrupt-ranges = <16 960 16>; }; /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ From 6fbd1310f99fc95d063b64d42addf701309663d6 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 19:38:02 -0500 Subject: [PATCH 40/68] arm64: dts: ti: k3-j721e: Enable SDHCI nodes at the board level SDHCI nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20230810003814.85450-2-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 7 ++----- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 7 ++----- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 11 +---------- 4 files changed, 8 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 66aac145e753..64eed76bbb7a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -563,6 +563,7 @@ &main_uart0 { &main_sdhci0 { /* eMMC */ + status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; @@ -570,6 +571,7 @@ &main_sdhci0 { &main_sdhci1 { /* SD Card */ + status = "okay"; vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv_alt>; pinctrl-names = "default"; @@ -578,11 +580,6 @@ &main_sdhci1 { disable-wp; }; -&main_sdhci2 { - /* Unused */ - status = "disabled"; -}; - &ospi0 { /* Unused */ status = "disabled"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index c1cbbae76182..e9b84d2c64b2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -504,6 +504,7 @@ &wkup_gpio1 { &main_sdhci0 { /* eMMC */ + status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; @@ -511,6 +512,7 @@ &main_sdhci0 { &main_sdhci1 { /* SD/MMC */ + status = "okay"; vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv_alt>; pinctrl-names = "default"; @@ -519,11 +521,6 @@ &main_sdhci1 { disable-wp; }; -&main_sdhci2 { - /* Unused */ - status = "disabled"; -}; - &usb_serdes_mux { idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 68a8abf59d24..3c53ddd6a67a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1479,6 +1479,7 @@ main_sdhci0: mmc@4f80000 { ti,itap-del-sel-ddr52 = <0x3>; ti,trm-icp = <0x8>; dma-coherent; + status = "disabled"; }; main_sdhci1: mmc@4fb0000 { @@ -1506,6 +1507,7 @@ main_sdhci1: mmc@4fb0000 { ti,clkbuf-sel = <0x7>; dma-coherent; sdhci-caps-mask = <0x2 0x0>; + status = "disabled"; }; main_sdhci2: mmc@4f98000 { @@ -1533,6 +1535,7 @@ main_sdhci2: mmc@4f98000 { ti,clkbuf-sel = <0x7>; dma-coherent; sdhci-caps-mask = <0x2 0x0>; + status = "disabled"; }; usbss0: cdns-usb@4104000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 0ee4f38ec8f0..bd1bd1b74605 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -582,13 +582,9 @@ &main_uart1 { pinctrl-0 = <&main_uart1_pins_default>; }; -&main_sdhci0 { - /* Unused */ - status = "disabled"; -}; - &main_sdhci1 { /* SD Card */ + status = "okay"; vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv_alt>; pinctrl-names = "default"; @@ -597,11 +593,6 @@ &main_sdhci1 { disable-wp; }; -&main_sdhci2 { - /* Unused */ - status = "disabled"; -}; - &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; From 013b7dd32c75ad3db218aa7a2d63f541304ac3b6 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 19:38:03 -0500 Subject: [PATCH 41/68] arm64: dts: ti: k3-j7200: Enable SDHCI nodes at the board level SDHCI nodes defined in the top-level J7200 SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230810003814.85450-3-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 92a541491172..dee9056f5605 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -326,6 +326,7 @@ exp3: gpio@20 { &main_sdhci0 { /* eMMC */ + status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; @@ -333,6 +334,7 @@ &main_sdhci0 { &main_sdhci1 { /* SD card */ + status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>; pinctrl-names = "default"; vmmc-supply = <&vdd_mmc1>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index e695f7881733..5ffcbd8acf86 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -655,6 +655,7 @@ main_sdhci0: mmc@4f80000 { mmc-hs200-1_8v; mmc-hs400-1_8v; dma-coherent; + status = "disabled"; }; main_sdhci1: mmc@4fb0000 { @@ -678,6 +679,7 @@ main_sdhci1: mmc@4fb0000 { ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; + status = "disabled"; }; serdes_wiz0: wiz@5060000 { From 5f715be31638b62de560acab7fdc7ff3d9e01bf9 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 19:38:04 -0500 Subject: [PATCH 42/68] arm64: dts: ti: k3-j721s2: Enable SDHCI nodes at the board level SDHCI nodes defined in the top-level J721s2 SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230810003814.85450-4-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 6 +----- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 ++ 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index e6e4133d1e9b..5fd06cd26b47 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -475,13 +475,9 @@ exp2: gpio@20 { }; }; -&main_sdhci0 { - /* Unused */ - status = "disabled"; -}; - &main_sdhci1 { /* SD card */ + status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>; pinctrl-names = "default"; disable-wp; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index e81ef8a7a8a2..7794063b77c8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -366,6 +366,7 @@ exp2: gpio@22 { &main_sdhci0 { /* eMMC */ + status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; @@ -373,6 +374,7 @@ &main_sdhci0 { &main_sdhci1 { /* SD card */ + status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>; pinctrl-names = "default"; disable-wp; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 20548d95ab13..7470f7242520 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -737,6 +737,7 @@ main_sdhci0: mmc@4f80000 { mmc-hs200-1_8v; mmc-hs400-1_8v; dma-coherent; + status = "disabled"; }; main_sdhci1: mmc@4fb0000 { @@ -766,6 +767,7 @@ main_sdhci1: mmc@4fb0000 { dma-coherent; /* Masking support for SDR104 capability */ sdhci-caps-mask = <0x00000003 0x00000000>; + status = "disabled"; }; main_navss: bus@30000000 { From 46d0c519e44bf31f45dd0a62654c75cae76215b8 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 19:38:05 -0500 Subject: [PATCH 43/68] arm64: dts: ti: k3-am65: Enable OSPI nodes at the board level OSPI nodes defined in the top-level AM65x SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230810003814.85450-5-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 + 3 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index e26bd988e522..6041862d5aa7 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -593,6 +593,7 @@ adc { }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 1c16c3cac612..616230ecfc33 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -297,6 +297,7 @@ ospi0: spi@47040000 { power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; ospi1: spi@47050000 { @@ -311,6 +312,7 @@ ospi1: spi@47050000 { power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 734b051c9700..aac243bacfee 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -530,6 +530,7 @@ &mcu_r5fss0_core1 { }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; From 73676c480b7286cb528170de73a7c03e19a5ade2 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 19:38:06 -0500 Subject: [PATCH 44/68] arm64: dts: ti: k3-j721e: Enable OSPI nodes at the board level OSPI nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230810003814.85450-6-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 10 ---------- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 6 +----- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 1 + 4 files changed, 4 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 64eed76bbb7a..0b89977351c9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -580,16 +580,6 @@ &main_sdhci1 { disable-wp; }; -&ospi0 { - /* Unused */ - status = "disabled"; -}; - -&ospi1 { - /* Unused */ - status = "disabled"; -}; - &main_i2c0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index c5ede7bbc263..2b5dfb3aba12 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -378,6 +378,7 @@ ospi0: spi@47040000 { power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; ospi1: spi@47050000 { @@ -392,6 +393,7 @@ ospi1: spi@47050000 { power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index bd1bd1b74605..4cd5346f2dd5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -594,6 +594,7 @@ &main_sdhci1 { }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; @@ -657,11 +658,6 @@ partition@3fc0000 { }; }; -&ospi1 { - /* Unused */ - status = "disabled"; -}; - &main_i2c0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index e90e43202546..928d3a8ad2d0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -202,6 +202,7 @@ eeprom@50 { }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; From 1a576c89168422b0658f7831d6e1bad63252eaea Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 19:38:07 -0500 Subject: [PATCH 45/68] arm64: dts: ti: k3-j7200: Enable OSPI nodes at the board level OSPI nodes defined in the top-level J7200 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20230810003814.85450-7-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 04f39b081dc0..1cda01b6f648 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -546,6 +546,7 @@ ospi0: spi@47040000 { power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index b37f4f88ece4..5a300d4c8ba0 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -267,6 +267,7 @@ eeprom@50 { }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; From cd9f6b324277d324ae056ffd8dda6287bcb649ab Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 19:38:08 -0500 Subject: [PATCH 46/68] arm64: dts: ti: k3-am64: Enable OSPI nodes at the board level OSPI nodes defined in the top-level AM64 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20230810003814.85450-8-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am642-evm.dts | 1 + arch/arm64/boot/dts/ti/k3-am642-sk.dts | 1 + arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 4e3e450e4e4c..ed1b63b9c1c5 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -794,6 +794,7 @@ ospi0: spi@fc40000 { assigned-clock-parents = <&k3_clks 75 7>; assigned-clock-rates = <166666666>; power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 5606d775153d..1c2c8f0daca9 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -181,6 +181,7 @@ i2c_som_rtc: rtc@52 { }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index d84e7ee16032..b4a1f73d4fb1 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -520,6 +520,7 @@ &tscadc0 { }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 963d796a3a97..af06ccd46680 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -518,6 +518,7 @@ &tscadc0 { }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi index 5e9012107afa..6229849b5d96 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -180,6 +180,7 @@ &main_r5fss1_core1 { }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins>; From 8757108b59e1490062d3c6a55ceccbafbee50e35 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 19:38:09 -0500 Subject: [PATCH 47/68] arm64: dts: ti: k3-j721e: Enable GPIO nodes at the board level GPIO nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. Disable the GPIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20230810003814.85450-9-afd@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 41 +++---------------- .../dts/ti/k3-j721e-common-proc-board.dts | 33 ++++----------- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++ .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 + arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 30 ++------------ 5 files changed, 27 insertions(+), 87 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 0b89977351c9..f06e7bda46f0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -647,52 +647,23 @@ eeprom@50 { }; }; -&main_gpio2 { - /* Unused */ - status = "disabled"; -}; - -&main_gpio3 { - /* Unused */ - status = "disabled"; -}; - -&main_gpio4 { - /* Unused */ - status = "disabled"; -}; - -&main_gpio5 { - /* Unused */ - status = "disabled"; -}; - -&main_gpio6 { - /* Unused */ - status = "disabled"; -}; - -&main_gpio7 { - /* Unused */ - status = "disabled"; -}; - &wkup_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>, <&mikro_bus_pins_default>; }; -&wkup_gpio1 { - /* Unused */ - status = "disabled"; -}; - &main_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>; }; +&main_gpio1 { + status = "okay"; +}; + &usb_serdes_mux { idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index e9b84d2c64b2..824874a7dcb9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -469,37 +469,18 @@ &main_uart4 { pinctrl-0 = <&main_uart4_pins_default>; }; -&main_gpio2 { - status = "disabled"; -}; - -&main_gpio3 { - status = "disabled"; -}; - -&main_gpio4 { - status = "disabled"; -}; - -&main_gpio5 { - status = "disabled"; -}; - -&main_gpio6 { - status = "disabled"; -}; - -&main_gpio7 { - status = "disabled"; -}; - &wkup_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_gpio_pins_default>; }; -&wkup_gpio1 { - status = "disabled"; +&main_gpio0 { + status = "okay"; +}; + +&main_gpio1 { + status = "okay"; }; &main_sdhci0 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 3c53ddd6a67a..e9eb3bac0632 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1340,6 +1340,7 @@ main_gpio0: gpio@600000 { power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio1: gpio@601000 { @@ -1356,6 +1357,7 @@ main_gpio1: gpio@601000 { power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 106 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio2: gpio@610000 { @@ -1373,6 +1375,7 @@ main_gpio2: gpio@610000 { power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio3: gpio@611000 { @@ -1389,6 +1392,7 @@ main_gpio3: gpio@611000 { power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 108 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio4: gpio@620000 { @@ -1406,6 +1410,7 @@ main_gpio4: gpio@620000 { power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 109 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio5: gpio@621000 { @@ -1422,6 +1427,7 @@ main_gpio5: gpio@621000 { power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 110 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio6: gpio@630000 { @@ -1439,6 +1445,7 @@ main_gpio6: gpio@630000 { power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 111 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio7: gpio@631000 { @@ -1455,6 +1462,7 @@ main_gpio7: gpio@631000 { power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 112 0>; clock-names = "gpio"; + status = "disabled"; }; main_sdhci0: mmc@4f80000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 2b5dfb3aba12..4ecc19b1e92e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -281,6 +281,7 @@ wkup_gpio0: gpio@42110000 { power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 113 0>; clock-names = "gpio"; + status = "disabled"; }; wkup_gpio1: gpio@42100000 { @@ -297,6 +298,7 @@ wkup_gpio1: gpio@42100000 { power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; clock-names = "gpio"; + status = "disabled"; }; mcu_i2c0: i2c@40b00000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 4cd5346f2dd5..ed4994d264f2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -731,41 +731,19 @@ &main_i2c5 { }; &main_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&rpi_header_gpio0_pins_default>; }; &main_gpio1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&rpi_header_gpio1_pins_default>; }; -&main_gpio2 { - status = "disabled"; -}; - -&main_gpio3 { - status = "disabled"; -}; - -&main_gpio4 { - status = "disabled"; -}; - -&main_gpio5 { - status = "disabled"; -}; - -&main_gpio6 { - status = "disabled"; -}; - -&main_gpio7 { - status = "disabled"; -}; - -&wkup_gpio1 { - status = "disabled"; +&wkup_gpio0 { + status = "okay"; }; &usb_serdes_mux { From 578bf4d09ef5d6e6707682ef0ae9d954ef77b8fb Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 19:38:10 -0500 Subject: [PATCH 48/68] arm64: dts: ti: k3-j721s2: Enable GPIO nodes at the board level GPIO nodes defined in the top-level J721s2 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. Disable the GPIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20230810003814.85450-10-afd@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am68-sk-base-board.dts | 18 ++---------------- .../dts/ti/k3-j721s2-common-proc-board.dts | 16 ++++------------ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 4 ++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++ 4 files changed, 12 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 5fd06cd26b47..5df5946687b3 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -382,31 +382,17 @@ J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */ }; &main_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&rpi_header_gpio0_pins_default>; }; -&main_gpio2 { - status = "disabled"; -}; - -&main_gpio4 { - status = "disabled"; -}; - -&main_gpio6 { - status = "disabled"; -}; - &wkup_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>; }; -&wkup_gpio1 { - status = "disabled"; -}; - &wkup_uart0 { status = "reserved"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 7794063b77c8..c6b85bbf9a17 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -299,20 +299,12 @@ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ }; }; -&main_gpio2 { - status = "disabled"; +&main_gpio0 { + status = "okay"; }; -&main_gpio4 { - status = "disabled"; -}; - -&main_gpio6 { - status = "disabled"; -}; - -&wkup_gpio1 { - status = "disabled"; +&wkup_gpio0 { + status = "okay"; }; &wkup_uart0 { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 7470f7242520..084f8f5b6699 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -579,6 +579,7 @@ main_gpio0: gpio@600000 { power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 111 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio2: gpio@610000 { @@ -595,6 +596,7 @@ main_gpio2: gpio@610000 { power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 112 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio4: gpio@620000 { @@ -611,6 +613,7 @@ main_gpio4: gpio@620000 { power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 113 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio6: gpio@630000 { @@ -627,6 +630,7 @@ main_gpio6: gpio@630000 { power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; clock-names = "gpio"; + status = "disabled"; }; main_i2c0: i2c@2000000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index bba2d75324b8..2ddad9318554 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -323,6 +323,7 @@ wkup_gpio0: gpio@42110000 { power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 115 0>; clock-names = "gpio"; + status = "disabled"; }; wkup_gpio1: gpio@42100000 { @@ -339,6 +340,7 @@ wkup_gpio1: gpio@42100000 { power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 116 0>; clock-names = "gpio"; + status = "disabled"; }; wkup_i2c0: i2c@42120000 { From d9fe476d39f62719adb805fc8c5668a3e21570d0 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 19:38:11 -0500 Subject: [PATCH 49/68] arm64: dts: ti: k3-j7200: Enable GPIO nodes at the board level GPIO nodes defined in the top-level J7200 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. Disable the GPIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230810003814.85450-11-afd@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 17 +++-------------- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++ 3 files changed, 9 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index dee9056f5605..cee2b4b0eb87 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -240,27 +240,16 @@ &main_uart3 { pinctrl-0 = <&main_uart3_pins_default>; }; -&main_gpio2 { - status = "disabled"; -}; - -&main_gpio4 { - status = "disabled"; -}; - -&main_gpio6 { - status = "disabled"; +&main_gpio0 { + status = "okay"; }; &wkup_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_gpio_pins_default>; }; -&wkup_gpio1 { - status = "disabled"; -}; - &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 5ffcbd8acf86..cdb1d6b2a982 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -833,6 +833,7 @@ main_gpio0: gpio@600000 { power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio2: gpio@610000 { @@ -850,6 +851,7 @@ main_gpio2: gpio@610000 { power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio4: gpio@620000 { @@ -867,6 +869,7 @@ main_gpio4: gpio@620000 { power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 109 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio6: gpio@630000 { @@ -884,6 +887,7 @@ main_gpio6: gpio@630000 { power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 111 0>; clock-names = "gpio"; + status = "disabled"; }; main_spi0: spi@2100000 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 1cda01b6f648..6ffaf85fa63f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -297,6 +297,7 @@ wkup_gpio0: gpio@42110000 { power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 113 0>; clock-names = "gpio"; + status = "disabled"; }; wkup_gpio1: gpio@42100000 { @@ -313,6 +314,7 @@ wkup_gpio1: gpio@42100000 { power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; clock-names = "gpio"; + status = "disabled"; }; mcu_navss: bus@28380000 { From a5a4cddad9ff71c55494328d0e39f051fe5905c2 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 19:38:12 -0500 Subject: [PATCH 50/68] arm64: dts: ti: k3-j721e: Enable TSCADC nodes at the board level TSCADC nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and/or device information. Disable the TSCADC nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230810003814.85450-12-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 10 ---------- 4 files changed, 6 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index f06e7bda46f0..9f3a809ddf90 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -747,6 +747,7 @@ &usb1 { }; &tscadc0 { + status = "okay"; /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */ adc { ti,adc-channels = <0 1 2 3 4 5 6>; @@ -754,6 +755,7 @@ adc { }; &tscadc1 { + status = "okay"; /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */ adc { ti,adc-channels = <0>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 824874a7dcb9..fe5207ac7d85 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -619,12 +619,14 @@ partition@3fe0000 { }; &tscadc0 { + status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; &tscadc1 { + status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 4ecc19b1e92e..2724fa459160 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -411,6 +411,7 @@ tscadc0: tscadc@40200000 { dmas = <&main_udmap 0x7400>, <&main_udmap 0x7401>; dma-names = "fifo0", "fifo1"; + status = "disabled"; adc { #io-channel-cells = <1>; @@ -430,6 +431,7 @@ tscadc1: tscadc@40210000 { dmas = <&main_udmap 0x7402>, <&main_udmap 0x7403>; dma-names = "fifo0", "fifo1"; + status = "disabled"; adc { #io-channel-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index ed4994d264f2..4032601fd53f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -828,16 +828,6 @@ &usb1 { phy-names = "cdns3,usb3-phy"; }; -&tscadc0 { - /* Unused */ - status = "disabled"; -}; - -&tscadc1 { - /* Unused */ - status = "disabled"; -}; - &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; From 1228242df12ec1b7cd099c8e57a35940f32b89c3 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 19:38:13 -0500 Subject: [PATCH 51/68] arm64: dts: ti: k3-am65: Enable TSCADC nodes at the board level TSCADC nodes defined in the top-level AM65 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and/or device information. Disable the TSCADC nodes in the top-level dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230810003814.85450-13-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 5 +---- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 2 ++ 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 6041862d5aa7..ba1c14a54acf 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -582,11 +582,8 @@ &mcu_spi0 { ti,pindir-d0-out-d1-in; }; -&tscadc0 { - status = "disabled"; -}; - &tscadc1 { + status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 616230ecfc33..cdc89902c122 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -112,6 +112,7 @@ tscadc0: tscadc@40200000 { dmas = <&mcu_udmap 0x7100>, <&mcu_udmap 0x7101 >; dma-names = "fifo0", "fifo1"; + status = "disabled"; adc { #io-channel-cells = <1>; @@ -130,6 +131,7 @@ tscadc1: tscadc@40210000 { dmas = <&mcu_udmap 0x7102>, <&mcu_udmap 0x7103>; dma-names = "fifo0", "fifo1"; + status = "disabled"; adc { #io-channel-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index aac243bacfee..f5c26e9fba98 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -478,12 +478,14 @@ &usb0_phy { }; &tscadc0 { + status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; &tscadc1 { + status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; From bcd8a3f28ad6baec7f4d8cbb0fe7cbaf6e351567 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 19:38:14 -0500 Subject: [PATCH 52/68] arm64: dts: ti: k3-am64: Enable TSCADC nodes at the board level TSCADC nodes defined in the top-level AM64 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and/or device information. Disable the TSCADC nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20230810003814.85450-14-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am642-sk.dts | 4 ---- arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 1 + 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index ed1b63b9c1c5..0df54a741824 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -765,6 +765,7 @@ tscadc0: tscadc@28001000 { assigned-clock-parents = <&k3_clks 0 3>; assigned-clock-rates = <60000000>; clock-names = "fck"; + status = "disabled"; adc { #io-channel-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index af06ccd46680..722fd285a34e 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -513,10 +513,6 @@ cpsw3g_phy1: ethernet-phy@1 { }; }; -&tscadc0 { - status = "disabled"; -}; - &ospi0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts index ac132a0867d0..04c15b64f0b7 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -424,6 +424,7 @@ &sdhci1 { }; &tscadc0 { + status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; From 8ea3fc2bea6bccaa18e21febdcd311566a078612 Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Thu, 10 Aug 2023 13:48:47 +0530 Subject: [PATCH 53/68] arm64: dts: ti: k3-*: fix fss node dtbs check warnings Fix these fss node warnings that dtbs_check throws: fss@47000000: $nodename:0: 'fss@47000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' By renaming fss to bus. Cc: Nishant Menon Suggested-by: Andrew Davis Signed-off-by: Dhruva Gole Reviewed-by: Reid Tonking Link: https://lore.kernel.org/r/20230810081847.277094-1-d-gole@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index cdc89902c122..1e536dc41f61 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -278,7 +278,7 @@ m_can1: can@40568000 { status = "disabled"; }; - fss: fss@47000000 { + fss: bus@47000000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 2724fa459160..05d6ef127ba7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -337,7 +337,7 @@ wkup_i2c0: i2c@42120000 { status = "disabled"; }; - fss: fss@47000000 { + fss: bus@47000000 { compatible = "simple-bus"; reg = <0x0 0x47000000 0x0 0x100>; #address-cells = <2>; From 35dba715971733d5fdfd98f4772ccc679d4989c2 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 13:01:43 -0500 Subject: [PATCH 54/68] arm64: dts: ti: k3-j721e: Enable C7x DSP nodes at the board level C7x DSP nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with both mboxes and memory-region information. As theses only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the C7x DSP nodes in the dtsi files and only enable the ones that are given the required mboxes and memory-region on a given board. Signed-off-by: Andrew Davis Acked-by: Hari Nagalla Tested-by: Udit Kumar Link: https://lore.kernel.org/r/20230809180145.53158-1-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 1 + arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 1 + arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 9f3a809ddf90..e4757285dd6f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -984,6 +984,7 @@ &c66_1 { }; &c71_0 { + status = "okay"; mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index e9eb3bac0632..f20ec447bff7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -2146,6 +2146,7 @@ c71_0: dsp@64800000 { ti,sci-proc-ids = <0x30 0xff>; resets = <&k3_reset 15 1>; firmware-name = "j7-c71_0-fw"; + status = "disabled"; }; icssg0: icssg@b000000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 4032601fd53f..764ed8f37046 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -1065,6 +1065,7 @@ &c66_1 { }; &c71_0 { + status = "okay"; mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 928d3a8ad2d0..1bfd5a4eca5e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -437,6 +437,7 @@ &c66_1 { }; &c71_0 { + status = "okay"; mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; From c23b203b929f22fb22f2b07c1e5d658a7d455263 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 13:01:44 -0500 Subject: [PATCH 55/68] arm64: dts: ti: k3-j784s4: Enable C7x DSP nodes at the board level C7x DSP nodes defined in the top-level J784s4 SoC dtsi files are incomplete and will not be functional unless they are extended with both mboxes and memory-region information. As theses only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the C7x DSP nodes in the dtsi files and only enable the ones that are given the required mboxes and memory-region on a given board. Signed-off-by: Andrew Davis Acked-by: Hari Nagalla Tested-by: Udit Kumar Link: https://lore.kernel.org/r/20230809180145.53158-2-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 1b927dbdcc5c..1ac5bf31cb39 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1525,6 +1525,7 @@ c71_0: dsp@64800000 { ti,sci-proc-ids = <0x30 0xff>; resets = <&k3_reset 30 1>; firmware-name = "j784s4-c71_0-fw"; + status = "disabled"; }; c71_1: dsp@65800000 { @@ -1537,6 +1538,7 @@ c71_1: dsp@65800000 { ti,sci-proc-ids = <0x31 0xff>; resets = <&k3_reset 33 1>; firmware-name = "j784s4-c71_1-fw"; + status = "disabled"; }; c71_2: dsp@66800000 { @@ -1549,6 +1551,7 @@ c71_2: dsp@66800000 { ti,sci-proc-ids = <0x32 0xff>; resets = <&k3_reset 37 1>; firmware-name = "j784s4-c71_2-fw"; + status = "disabled"; }; c71_3: dsp@67800000 { @@ -1561,5 +1564,6 @@ c71_3: dsp@67800000 { ti,sci-proc-ids = <0x33 0xff>; resets = <&k3_reset 40 1>; firmware-name = "j784s4-c71_3-fw"; + status = "disabled"; }; }; From 00ae4c39cd16ef8b1662c5915dda08eb28eed762 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 9 Aug 2023 13:01:45 -0500 Subject: [PATCH 56/68] arm64: dts: ti: k3-j721e: Enable C6x DSP nodes at the board level C6x DSP nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with both mboxes and memory-region information. As theses only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the C6x DSP nodes in the dtsi files and only enable the ones that are given the required mboxes and memory-region on a given board. Signed-off-by: Andrew Davis Acked-by: Hari Nagalla Tested-by: Udit Kumar Link: https://lore.kernel.org/r/20230809180145.53158-3-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 2 ++ 4 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index e4757285dd6f..2f954729f353 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -972,12 +972,14 @@ &main_r5fss1_core1 { }; &c66_0 { + status = "okay"; mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { + status = "okay"; mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index f20ec447bff7..f6c7e1614521 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -2121,6 +2121,7 @@ c66_0: dsp@4d80800000 { ti,sci-proc-ids = <0x03 0xff>; resets = <&k3_reset 142 1>; firmware-name = "j7-c66_0-fw"; + status = "disabled"; }; c66_1: dsp@4d81800000 { @@ -2134,6 +2135,7 @@ c66_1: dsp@4d81800000 { ti,sci-proc-ids = <0x04 0xff>; resets = <&k3_reset 143 1>; firmware-name = "j7-c66_1-fw"; + status = "disabled"; }; c71_0: dsp@64800000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 764ed8f37046..42fe8eee9ec8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -1053,12 +1053,14 @@ &main_r5fss1_core1 { }; &c66_0 { + status = "okay"; mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { + status = "okay"; mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 1bfd5a4eca5e..7f0686c2ce37 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -425,12 +425,14 @@ &main_r5fss1_core1 { }; &c66_0 { + status = "okay"; mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { + status = "okay"; mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; From 73387da70f9c26b6fba4f62371d013cce14663d9 Mon Sep 17 00:00:00 2001 From: Aradhya Bhatia Date: Wed, 9 Aug 2023 14:15:54 +0530 Subject: [PATCH 57/68] arm64: dts: ti: k3-am62x-sk-common: Update main-i2c1 frequency The Display Data Channel (DDC) transactions between an HDMI transmitter (SIL9022A in this case) and an HDMI monitor, occur at a maximum of 100KHz. That's the maximum supported frequency within DDC standards. While the SIL9022A can transact with the core at 400KHz, it needs to drop the frequency to 100KHz when communicating with the monitor, otherwise, the i2c controller times out and shows warning like this. [ 985.773431] omap_i2c 20010000.i2c: controller timed out That feature, however, has not been enabled in the SIL9022 driver. Since, dropping the frequency doesn't affect any other devices on the bus, drop the main-i2c1 frequency from 400KHz to 100KHz. Fixes: a841581451af ("arm64: dts: ti: Refractor AM625 SK dts") Signed-off-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20230809084559.17322-2-a-bhatia1@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 34c8ffc553ec..540ed8a0d7fb 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -300,7 +300,7 @@ &main_i2c1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; + clock-frequency = <100000>; tlv320aic3106: audio-codec@1b { #sound-dai-cells = <0>; From 8ccc1073c7bb2ae9654529a75f85ef23b7215c9b Mon Sep 17 00:00:00 2001 From: Aradhya Bhatia Date: Wed, 9 Aug 2023 14:15:55 +0530 Subject: [PATCH 58/68] arm64: dts: ti: k3-am62-main: Add node for DSS Add Display SubSystem (DSS) DT node for the AM625 SoC. The DSS supports one each of video pipeline (vid) and video-lite pipeline (vidl1). It outputs OLDI signals on one video port (VP1) and DPI signals on another (VP2). The video ports are connected to the pipelines via 2 identical overlay managers (ovr1 and ovr2). Also add the DT node for DSS clock divider. This is a fixed-factor-clock and does not have any register. This comes into effect whenenver OLDI display is used. The input to this divider is a serial clock used by OLDI TXes. The divider divides the input clock by 7, and provides the pixel clock to VP1. Signed-off-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20230809084559.17322-3-a-bhatia1@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 25 ++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62.dtsi | 8 ++++++++ 2 files changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 5f19ef46d44c..284b90c94da8 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -735,6 +735,31 @@ cpts@3d000 { }; }; + dss: dss@30200000 { + compatible = "ti,am625-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ + <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&dss_vp1_clk>, + <&k3_clks 186 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = ; + status = "disabled"; + + dss_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + hwspinlock: spinlock@2a000000 { compatible = "ti,am64-hwspinlock"; reg = <0x00 0x2a000000 0x00 0x1000>; diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi index 5e72c445f37a..11f14eef2d44 100644 --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -102,6 +102,14 @@ cbass_wakeup: bus@b00000 { }; }; + dss_vp1_clk: clock-divider-oldi { + compatible = "fixed-factor-clock"; + clocks = <&k3_clks 186 0>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + }; + #include "k3-am62-thermal.dtsi" }; From db6e8237cf5435e972ea47632e5d8ac3e356f210 Mon Sep 17 00:00:00 2001 From: Aradhya Bhatia Date: Wed, 9 Aug 2023 14:15:56 +0530 Subject: [PATCH 59/68] arm64: dts: ti: k3-am62x-sk-common: Add HDMI support The DSS outputs DPI signals via its second video port (VP2). The DPI output from DSS is 24 bits (RGB888) and is forwarded to an HDMI transmitter (SIL9022) on the board. Add pinmux info for DSS DPI output. Add DT nodes for SIL9022 HDMI transmitter (TX), and the HDMI connector on the AM625 SK and AM62-LP SK platforms. Additionally, connect the output of DSS (VP2) with input of the HDMI TX, and the output of HDMI TX to the input of the HDMI connector. Signed-off-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20230809084559.17322-4-a-bhatia1@ti.com Signed-off-by: Nishanth Menon --- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 540ed8a0d7fb..677ff8de4b6e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -114,6 +114,17 @@ sound_master: simple-audio-card,codec { clocks = <&tlv320_mclk>; }; }; + + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; }; &main_pmx0 { @@ -226,6 +237,39 @@ AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25/J17) GPMC0_WEN.MCASP1_AXR0 */ AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */ >; }; + + main_dss0_pins_default: main-dss0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ + AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ + AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ + AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ + AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ + AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ + AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ + AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ + AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ + AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ + AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ + AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ + AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ + AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ + AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ + AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ + AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ + AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ + AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ + AM62X_IOPAD(0x05c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ + AM62X_IOPAD(0x060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ + AM62X_IOPAD(0x064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */ + AM62X_IOPAD(0x068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */ + AM62X_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ + AM62X_IOPAD(0x070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */ + AM62X_IOPAD(0x074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */ + AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ + >; + }; }; &mcu_pmx0 { @@ -313,6 +357,36 @@ tlv320aic3106: audio-codec@1b { IOVDD-supply = <&vcc_3v3_sys>; DRVDD-supply = <&vcc_3v3_sys>; }; + + sii9022: bridge-hdmi@3b { + compatible = "sil,sii9022"; + reg = <0x3b>; + interrupt-parent = <&exp1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = < 0 >; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; }; &sdhci0 { @@ -410,3 +484,20 @@ &mcasp1 { tx-num-evt = <32>; rx-num-evt = <32>; }; + +&dss { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_dss0_pins_default>; +}; + +&dss_ports { + /* VP2: DPI Output */ + port@1 { + reg = <1>; + + dpi1_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; From b50ccab9e07ca19d49a0d629dfbe184e6975be22 Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Wed, 9 Aug 2023 14:15:57 +0530 Subject: [PATCH 60/68] arm64: dts: ti: am62x-sk: Add overlay for HDMI audio Enable audio output over HDMI instead of the 3.5mm jack. A FET switch (U65) on the EVM muxes serial audio lines coming from McASP between the codec (tlv320aic3106) and the HDMI bridge (sii9022). By default it uses the codec, but it can be toggled to use the HDMI bridge by shorting a (J24) header on the board. Signed-off-by: Jai Luthra [a-bhatia1: Cosmetic changes] Signed-off-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20230809084559.17322-5-a-bhatia1@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 3 ++ .../boot/dts/ti/k3-am62x-sk-hdmi-audio.dtso | 40 +++++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-audio.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 437a3d7e8e3a..e3eadf69d43b 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -19,6 +19,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo # Boards with AM62Ax SoC dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb @@ -68,6 +69,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb # Enable support for device-tree overlays +DTC_FLAGS_k3-am625-sk += -@ +DTC_FLAGS_k3-am62-lp-sk += -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ DTC_FLAGS_k3-j721e-common-proc-board += -@ DTC_FLAGS_k3-j721s2-common-proc-board += -@ diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-audio.dtso b/arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-audio.dtso new file mode 100644 index 000000000000..43a0ddc123e5 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-audio.dtso @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Audio playback via HDMI for AM625-SK and AM62-LP SK. + * + * Links: + * AM625 SK: https://www.ti.com/tool/SK-AM62 + * AM62-LP SK: https://www.ti.com/tool/SK-AM62-LP + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + hdmi_audio: sound-sii9022 { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM62x-Sil9022-HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&hdmi_dailink_master>; + simple-audio-card,frame-master = <&hdmi_dailink_master>; + + hdmi_dailink_master: simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-direction-out; + }; + + simple-audio-card,codec { + sound-dai = <&sii9022>; + }; + }; +}; + +&mcasp1 { + auxclk-fs-ratio = <2177>; +}; + +&codec_audio { + status = "disabled"; +}; From 1f7226a5e52cb8b90771cefc29077f9ce13a3c90 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 9 Aug 2023 14:15:58 +0530 Subject: [PATCH 61/68] arm64: dts: ti: k3-am625-beagleplay: Add HDMI support The DSS outputs DPI signals via its second video port (VP2). The DPI output from DSS is 24 bits (RGB888) and is forwarded to an HDMI transmitter (ITE-IT66121) on the BeaglePlay platform. For audio output, BeaglePlay uses mcasp1. Add pinmux info for DSS DPI signals. Further, add support for HDMI audio and video output. Signed-off-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20230809084559.17322-6-a-bhatia1@ti.com Signed-off-by: Nishanth Menon --- .../arm64/boot/dts/ti/k3-am625-beagleplay.dts | 150 ++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index e07ddff22e07..7cfdf562b53b 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -192,6 +192,34 @@ usr: button-usr { }; + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&it66121_out>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "it66121 HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&hdmi_dailink_master>; + simple-audio-card,frame-master = <&hdmi_dailink_master>; + + hdmi_dailink_master: simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-direction-out; + }; + + simple-audio-card,codec { + sound-dai = <&it66121>; + }; + }; + /* Workaround for errata i2329 - just use mdio bitbang */ mdio0: mdio { compatible = "virtual,mdio-gpio"; @@ -422,6 +450,57 @@ pmic_irq_pins_default: pmic-irq-default-pins { AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */ >; }; + + hdmi_gpio_pins_default: hdmi-gpio-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0094, PIN_INPUT_PULLUP | PIN_DEBOUNCE_CONF6, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ + AM62X_IOPAD(0x0054, PIN_OUTPUT_PULLUP, 7) /* (P21) GPMC0_AD6.GPIO0_21 */ + >; + }; + + mcasp_hdmi_pins_default: mcasp-hdmi-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ + AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ + AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0 */ + AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */ + AM62X_IOPAD(0x0084, PIN_INPUT, 2) /* (L23) GPMC0_ADVn_ALE.MCASP1_AXR2 */ + AM62X_IOPAD(0x007c, PIN_INPUT, 2) /* (P25) GPMC0_CLK.MCASP1_AXR3 */ + >; + }; + + dss0_pins_default: dss0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ + AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ + AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ + AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ + AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ + AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ + AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ + AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ + AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ + AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ + AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ + AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ + AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ + AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ + AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ + AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ + AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ + AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ + AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ + AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ + AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ + AM62X_IOPAD(0x0064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */ + AM62X_IOPAD(0x0068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */ + AM62X_IOPAD(0x006c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ + AM62X_IOPAD(0x0070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */ + AM62X_IOPAD(0x0074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */ + AM62X_IOPAD(0x0078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ + >; + }; }; &mcu_pmx0 { @@ -670,6 +749,42 @@ &main_i2c2 { pinctrl-0 = <&i2c2_1v8_pins_default>; clock-frequency = <100000>; status = "okay"; + + it66121: bridge-hdmi@4c { + compatible = "ite,it66121"; + reg = <0x4c>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_gpio_pins_default>; + vcn33-supply = <&vdd_3v3>; + vcn18-supply = <&buck2_reg>; + vrf12-supply = <&buck3_reg>; + reset-gpios = <&main_gpio0 21 GPIO_ACTIVE_LOW>; + interrupt-parent = <&main_gpio0>; + interrupts = <36 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + it66121_in: endpoint { + bus-width = <24>; + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + it66121_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; }; &main_i2c3 { @@ -756,3 +871,38 @@ &main_uart6 { pinctrl-0 = <&wifi_debug_uart_pins_default>; status = "okay"; }; + +&dss { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dss0_pins_default>; +}; + +&dss_ports { + /* VP2: DPI Output */ + port@1 { + reg = <1>; + + dpi1_out: endpoint { + remote-endpoint = <&it66121_in>; + }; + }; +}; + +&mcasp1 { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp_hdmi_pins_default>; + auxclk-fs-ratio = <2177>; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; From 3a4086985696295577c20ae558f99d974067e316 Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Sat, 12 Aug 2023 00:50:28 +0530 Subject: [PATCH 62/68] arm64: dts: ti: k3-j784s4: Add phase tags marking bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT. That's why add it also to Linux to be aligned with bootloader requirement. On TI K3 J784S4 SoC, only secure_proxy_mcu and secure_proxy_sa3 nodes are exclusively used by R5 bootloader, rest of the dts nodes with bootph-* are used by later boot stages also. And secure_proxy_mcu and secure_proxy_sa3 are disabled in kernel device tree, and will be only enabled in R5 bootloader device tree. So, bootph-pre-ram for secure_proxy_mcu and secure_proxy_sa3 will be added in R5 bootloader device tree only. Add bootph-all for all other nodes that are used in the bootloader on K3 J784S4 SoC, and bootph-pre-ram is not needed specifically for any node in kernel dts. Signed-off-by: Apurva Nandan Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230811192030.3480616-2-a-nandan@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 9 +++++++++ arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 2 ++ 3 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 1ac5bf31cb39..efed2d683f63 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -670,6 +670,7 @@ main_sdhci1: mmc@4fb0000 { }; main_navss: bus@30000000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -705,6 +706,7 @@ main_udmass_inta: msi-controller@33d00000 { }; secure_proxy_main: mailbox@32c00000 { + bootph-all; compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 920d5b5f1b75..4ab4018d3695 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -7,6 +7,7 @@ &cbass_mcu_wakeup { sms: system-controller@44083000 { + bootph-all; compatible = "ti,k2g-sci"; ti,host-id = <12>; @@ -19,22 +20,26 @@ sms: system-controller@44083000 { reg = <0x00 0x44083000 0x00 0x1000>; k3_pds: power-controller { + bootph-all; compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; }; k3_clks: clock-controller { + bootph-all; compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; k3_reset: reset-controller { + bootph-all; compatible = "ti,sci-reset"; #reset-cells = <2>; }; }; chipid@43000014 { + bootph-all; compatible = "ti,am654-chipid"; reg = <0x00 0x43000014 0x00 0x4>; }; @@ -161,6 +166,7 @@ mcu_timer0: timer@40400000 { }; mcu_timer1: timer@40410000 { + bootph-all; compatible = "ti,am654-timer"; reg = <0x00 0x40410000 0x00 0x400>; interrupts = ; @@ -442,6 +448,7 @@ mcu_spi2: spi@40320000 { }; mcu_navss: bus@28380000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -451,6 +458,7 @@ mcu_navss: bus@28380000 { dma-ranges; mcu_ringacc: ringacc@2b800000 { + bootph-all; compatible = "ti,am654-navss-ringacc"; reg = <0x00 0x2b800000 0x00 0x400000>, <0x00 0x2b000000 0x00 0x400000>, @@ -466,6 +474,7 @@ mcu_ringacc: ringacc@2b800000 { }; mcu_udmap: dma-controller@285c0000 { + bootph-all; compatible = "ti,j721e-navss-mcu-udmap"; reg = <0x00 0x285c0000 0x00 0x100>, <0x00 0x2a800000 0x00 0x40000>, diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi index 8b5974d92e33..4398c3a463e1 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -228,6 +228,7 @@ pmu: pmu { }; cbass_main: bus@100000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -263,6 +264,7 @@ cbass_main: bus@100000 { <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; cbass_mcu_wakeup: bus@28380000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; From c74d8de338a553da7b0084bab2554b042375625e Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Sat, 12 Aug 2023 00:50:29 +0530 Subject: [PATCH 63/68] arm64: dts: ti: k3-j784s4-evm: Add phase tags marking bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT. That's why add it also to Linux to be aligned with bootloader requirement. wkup_i2c0, mcu_uart0, main_uart8, fss, ospi0, ospi1, main_sdhci0 and main_sdhci1 are required for bootloader operation on TI K3 J784S4 EVM. These IPs along with pinmuxes need to be marked for all bootloader phases, hence add bootph-all to these nodes in kernel dts. Signed-off-by: Apurva Nandan Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230811192030.3480616-3-a-nandan@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index b4ffa720209c..5991c2e1d994 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -252,7 +252,9 @@ vdd_sd_dv: regulator-TLV71033 { }; &main_pmx0 { + bootph-all; main_uart8_pins_default: main-uart8-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ @@ -269,6 +271,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ }; main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -289,7 +292,9 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ }; &wkup_pmx2 { + bootph-all; wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-all; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -299,6 +304,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ }; wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-all; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ @@ -306,6 +312,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ }; mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ @@ -366,7 +373,9 @@ J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ }; &wkup_pmx0 { + bootph-all; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ @@ -384,7 +393,9 @@ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ }; &wkup_pmx1 { + bootph-all; mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ @@ -392,6 +403,7 @@ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ }; mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ @@ -413,6 +425,7 @@ &wkup_uart0 { }; &wkup_i2c0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; @@ -426,12 +439,14 @@ eeprom@50 { }; &mcu_uart0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart8 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart8_pins_default>; @@ -442,15 +457,18 @@ &ufs_wrapper { }; &fss { + bootph-all; status = "okay"; }; &ospi0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; flash@0 { + bootph-all; compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -498,6 +516,7 @@ partition@800000 { }; partition@3fc0000 { + bootph-all; label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; }; @@ -506,11 +525,13 @@ partition@3fc0000 { }; &ospi1 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; flash@0 { + bootph-all; compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; @@ -558,6 +579,7 @@ partition@800000 { }; partition@3fc0000 { + bootph-all; label = "qspi.phypattern"; reg = <0x3fc0000 0x40000>; }; @@ -602,6 +624,7 @@ exp2: gpio@22 { }; &main_sdhci0 { + bootph-all; /* eMMC */ status = "okay"; non-removable; @@ -610,6 +633,7 @@ &main_sdhci0 { }; &main_sdhci1 { + bootph-all; /* SD card */ status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>; From 68501d3cc16a7828b05ee24bdb037f697e207854 Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Sat, 12 Aug 2023 00:50:30 +0530 Subject: [PATCH 64/68] arm64: dts: ti: k3-am69-sk: Add phase tags marking bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT. That's why add it also to Linux to be aligned with bootloader requirement. wkup_i2c0, mcu_uart0, main_uart8, main_sdhci0 and main_sdhci1 are required for bootloader operation on TI K3 AM69-SK EVM. These IPs along with pinmuxes need to be marked for all bootloader phases, hence add bootph-all to these nodes in kernel dts. Signed-off-by: Apurva Nandan Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230811192030.3480616-4-a-nandan@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index d282c2c633c1..06993709111e 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -110,7 +110,9 @@ vdd_sd_dv: regulator-tlv71033 { }; &main_pmx0 { + bootph-all; main_uart8_pins_default: main-uart8-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ @@ -125,6 +127,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ }; main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -164,7 +167,9 @@ J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ }; &wkup_pmx2 { + bootph-all; wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-all; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -174,6 +179,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ }; wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-all; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ @@ -181,6 +187,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ }; mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ @@ -249,6 +256,7 @@ &wkup_uart0 { }; &wkup_i2c0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; @@ -268,6 +276,7 @@ &wkup_gpio0 { }; &mcu_uart0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; @@ -281,6 +290,7 @@ &mcu_i2c0 { }; &main_uart8 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart8_pins_default>; @@ -307,6 +317,7 @@ exp1: gpio@21 { }; &main_sdhci0 { + bootph-all; /* eMMC */ status = "okay"; non-removable; @@ -315,6 +326,7 @@ &main_sdhci0 { }; &main_sdhci1 { + bootph-all; /* SD card */ status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>; From b57fc5cbdbdfd04d44697800a9d59aeb3be2f273 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Sat, 12 Aug 2023 00:14:30 +0530 Subject: [PATCH 65/68] dt-bindings: arm: ti: Add bindings for AM62P5 SoCs Add bindings for TI's AM62P5 family of devices. Signed-off-by: Bryan Brattlof Acked-by: Conor Dooley Reviewed-by: Dhruva Gole Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20230811184432.732215-2-vigneshr@ti.com Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 5ca6af492507..03d2a0d79fb0 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -25,6 +25,12 @@ properties: - ti,am62a7-sk - const: ti,am62a7 + - description: K3 AM62P5 SoC and Boards + items: + - enum: + - ti,am62p5-sk + - const: ti,am62p5 + - description: K3 AM625 SoC PHYTEC phyBOARD-Lyra items: - const: phytec,am625-phyboard-lyra-rdk From 29075cc09f43a024d962da66d2e4f9eb577713d0 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Sat, 12 Aug 2023 00:14:31 +0530 Subject: [PATCH 66/68] arm64: dts: ti: Introduce AM62P5 family of SoCs The AM62Px is an extension of the existing Sitara AM62x low-cost family of application processors built for Automotive and Linux Application development. Scalable Arm Cortex-A53 performance and embedded features, such as: multi high-definition display support, 3D-graphics acceleration, 4K video acceleration, and extensive peripherals make the AM62Px well-suited for a broad range of automation and industrial application, including automotive digital instrumentation, automotive displays, industrial HMI, and more. Some highlights of AM62P SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single core variants are provided in the same package to allow HW compatible designs. * One Device manager Cortext-R5F for system power and resource management, and one Cortex-R5F for Functional Safety or general-purpose usage. * One 3D GPU up to 50 GLFOPS * H.264/H.265 Video Encode/Decode. * Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI, or DPI. Up to 3840x1080@60fps resolution * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized Hardware Security Module with support for secure boot, debug security and crypto acceleration and trusted execution environment. * One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types. * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling battery powered system design. For those interested, more details about this SoC can be found in the Technical Reference Manual here: https://www.ti.com/lit/pdf/spruj83 Signed-off-by: Bryan Brattlof Acked-by: Andrew Davis Reviewed-by: Dhruva Gole Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20230811184432.732215-3-vigneshr@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 136 ++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi | 15 +++ arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 32 +++++ arch/arm64/boot/dts/ti/k3-am62p.dtsi | 122 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 107 +++++++++++++++ arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 + 6 files changed, 415 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi new file mode 100644 index 000000000000..c24ff905437f --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P main domain peripherals + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + oc_sram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x00 0x70000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x70000000 0x10000>; + }; + + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = ; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + dmss: bus@48000000 { + bootph-all; + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; + + ti,sci-dev-id = <25>; + + secure_proxy_main: mailbox@4d000000 { + bootph-all; + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x4d000000 0x00 0x80000>, + <0x00 0x4a600000 0x00 0x80000>, + <0x00 0x4a400000 0x00 0x80000>; + interrupt-names = "rx_012"; + interrupts = ; + }; + }; + + dmsc: system-controller@44043000 { + bootph-all; + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + mbox-names = "rx", "tx"; + mboxes = <&secure_proxy_main 12>, + <&secure_proxy_main 13>; + reg-names = "debug_messages"; + reg = <0x00 0x44043000 0x00 0xfe0>; + + k3_pds: power-controller { + bootph-all; + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + + k3_clks: clock-controller { + bootph-all; + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + bootph-all; + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + main_pmx0: pinctrl@f4000 { + bootph-all; + compatible = "pinctrl-single"; + reg = <0x00 0xf4000 0x00 0x2ac>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_timer0: timer@2400000 { + bootph-all; + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 36 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 2>; + assigned-clock-parents = <&k3_clks 36 3>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 146 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>; + clock-names = "fclk"; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi new file mode 100644 index 000000000000..27ca1c9c6d13 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P MCU domain peripherals + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu { + mcu_pmx0: pinctrl@4084000 { + compatible = "pinctrl-single"; + reg = <0x00 0x04084000 0x00 0x88>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi new file mode 100644 index 000000000000..aaf4b793b58e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P wakeup domain peripherals + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_wakeup { + wkup_conf: bus@43000000 { + bootph-all; + compatible = "simple-bus"; + reg = <0x00 0x43000000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x43000000 0x20000>; + + chipid: chipid@14 { + bootph-all; + compatible = "ti,am654-chipid"; + reg = <0x14 0x4>; + }; + }; + + wkup_uart0: serial@2b300000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x2b300000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "fclk"; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi new file mode 100644 index 000000000000..294ab73ec98b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62P SoC Family + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include + +#include "k3-pinctrl.h" + +/ { + model = "Texas Instruments K3 AM62P5 SoC"; + compatible = "ti,am62p5"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + cbass_main: bus@f0000 { + bootph-all; + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, + + /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; + + cbass_mcu: bus@4000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */ + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ + }; + + cbass_wakeup: bus@b00000 { + bootph-all; + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ + }; + }; +}; + +/* Now include peripherals for each bus segment */ +#include "k3-am62p-main.dtsi" +#include "k3-am62p-mcu.dtsi" +#include "k3-am62p-wakeup.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi new file mode 100644 index 000000000000..50147bb63e03 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P5 SoC family (quad core) + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * TRM: https://www.ti.com/lit/pdf/spruj83 + */ + +/dts-v1/; + +#include "k3-am62p.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 135 0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 136 0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 137 0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 138 0>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h index 6004e0967ec5..2a4e0e084d69 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -41,6 +41,9 @@ #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) From 935c4047d42e53a06ec768ddc495a44f6869209c Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Sat, 12 Aug 2023 00:14:32 +0530 Subject: [PATCH 67/68] arm64: dts: ti: Add support for the AM62P5 Starter Kit Add basic support for the AM62P5 SK with UART console and ramdisk as rootfs. Schematics is at https://www.ti.com/lit/zip/sprr487 Signed-off-by: Bryan Brattlof Acked-by: Andrew Davis Reviewed-by: Dhruva Gole Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20230811184432.732215-4-vigneshr@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 3 + arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 116 ++++++++++++++++++++++++ 2 files changed, 119 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index e3eadf69d43b..e7b8e2e7f083 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -24,6 +24,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo # Boards with AM62Ax SoC dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb +# Boards with AM62Px SoC +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb + # Boards with AM64x SoC dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts new file mode 100644 index 000000000000..6fb17b17c95e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P5-SK + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://www.ti.com/lit/zip/sprr487 + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" + +/ { + compatible = "ti,am62p5-sk", "ti,am62p5"; + model = "Texas Instruments AM62P5 SK"; + + aliases { + serial0 = &wkup_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + }; + + chosen { + stdout-path = &main_uart0; + }; + + memory@80000000 { + /* 8G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + }; +}; + +&main_pmx0 { + main_uart0_pins_default: main-uart0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ + AM62PX_IOPAD(0x1d0, PIN_INPUT, 0) /* (A23) UART0_CTSn */ + AM62PX_IOPAD(0x1d4, PIN_OUTPUT, 0) /* (C22) UART0_RTSn */ + >; + }; + + main_uart1_pins_default: main-uart1-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62PX_IOPAD(0x194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3 */ + AM62PX_IOPAD(0x198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2 */ + AM62PX_IOPAD(0x1ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR */ + AM62PX_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR */ + >; + }; +}; + +&main_uart0 { + bootph-all; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; +}; + +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; +}; + +&cbass_mcu { + bootph-all; +}; + +&mcu_pmx0 { + bootph-all; + wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ + AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ + AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ + AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ + >; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + bootph-all; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "reserved"; +}; From 9e77200356badfda6cec99e37be55fa940f83c7d Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Sat, 12 Aug 2023 21:11:23 +0200 Subject: [PATCH 68/68] arm64: dts: ti: verdin-am62: Add DSI display support Add MIPI-DSI support to Verdin AM62. Verdin AM62 has a MIPI DSI interface on the edge connector, this is provided with a Toshiba TC358778 DPI to MIPI-DSI bridge connected to the DSS DPI port with a 18-bit width parallel bus. Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20230812191123.14779-1-francesco@dolcini.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index 5db9ef2dc7e5..40992e7e4c30 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -815,6 +815,26 @@ cpsw3g_phy0: ethernet-phy@0 { }; }; +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_rgb>; + status = "disabled"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP2: DPI Output */ + port@1 { + reg = <1>; + + dpi_out: endpoint { + remote-endpoint = <&rgb_in>; + }; + }; +}; + /* Verdin PWM_1, PWM_2 */ &epwm0 { pinctrl-names = "default"; @@ -1051,6 +1071,7 @@ port@0 { rgb_in: endpoint { data-lines = <18>; + remote-endpoint = <&dpi_out>; }; };