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i.MX fixes for 6.5, 2nd round:
- Fix i.MX93 ANATOP 'reg' resource size to avoid overlapping with TMU memory area. - Fix RTC interrupt level on imx6qdl-phytec-mira board. - Remove LDB endpoint from from the common imx6sx.dtsi as it causes regression for boards that has the LCDIF connected directly to a parallel display. - Drop CSI1 PHY reference clock configuration from i.MX8MM/N device tree to avoid overclocking. - Set a proper default tuning step for i.MX6SX and i.MX7D uSDHC to fix a tuning failure seen with some SD cards. -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmTTYzIUHHNoYXduZ3Vv QGtlcm5lbC5vcmcACgkQUFdYWoewfM5THQf/bDZP+YPT8RxUdxVdL6jT2GGHR3t8 wq3+vM1KVgg+1E9nMBcG0aT1fUTvPM22N5Ae72bGYd69HGbqS64UJ37JlvrSXfwW QtJHPb9mbDPsdyoLbWBuJq3bdY6NgdbzeKEEGRWlZAkJqvB5a1S63g3riJO89inp mMsm0dFGn7IZFkhflMtMFL9T0FOz4IwbJGBCm5WvRCR/5nH82MJe5w9JfWBGoRPY Y0+vm8bS8A/hjQrYVWyAxe1sRAjxNNPWEsjelY/F89gpqOcuBrTTFVmMhEVKX6sd BjgCQFFWzds4ezmTNloMTyB4dSnW/q2Nsg87A9MXVECW6eIzAeO9p2dINA== =pxhp -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmTXPu4ACgkQYKtH/8kJ UieZnRAAnbxsC6/NT7qOwo/d6+hfX2Nh7Tgy9MDLBwIGtzdR822SD0WKwYRIb0K/ iMQMt+6ItPcYDKOLUXKv1MY3QX3BcirvE4yDyPGVxgcnkmL1egeUlYJ4R2U8QnOq Vwn+cqAcA6RSQIYEV0w32gXHjeDBMdsToT+DlV7id5C6QyreQEkSRzrqf0zm1CTF zNWCXeaaLkTV+j7W4fb3yPhSMhnnfkwmZB3lVVd5K/vwt7x3OQc7WaSQVNPAcGTC jiWsbW5KF4HbcukUpb16hyxyyJlt94FxrqqUyN86mj/ONBS55Hf7ilgZX4x/KphG PJ2V7fnCDnrhIWVEUlknMxLZmPUXTMqaSVsXrx0JOOz+y3KSq6lZudswXPK5fvbV WGZw9YpC/Hm3hN7Xi+BBUZVJGB7r9pyjcZUcUZBqK1EOxDSRiDMogyC55cC6C6Z2 uX4AfntpeDskj1nUtAgXK38bM1NLQ/jQnkZPVV69qpSkRQK/zLBwNuTSDUtW42vM ftbbSIyN4tEBQD5bmXy01ug7qxFJaeRQ9dW44UH03zYvDlH5QTrRM64tmySKIRZ+ urab1ShoN0UNA7t9PFpj45bbLb9sndeI6EOh0Vi8RozQ+dCEq1I6HFt54K886qar sjcsnrJxMZysZnoGGf3q1REe3NjuQ1gRd2nwg4Rbj7VkytuInWI= =3ZEY -----END PGP SIGNATURE----- Merge tag 'imx-fixes-6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes i.MX fixes for 6.5, 2nd round: - Fix i.MX93 ANATOP 'reg' resource size to avoid overlapping with TMU memory area. - Fix RTC interrupt level on imx6qdl-phytec-mira board. - Remove LDB endpoint from from the common imx6sx.dtsi as it causes regression for boards that has the LCDIF connected directly to a parallel display. - Drop CSI1 PHY reference clock configuration from i.MX8MM/N device tree to avoid overclocking. - Set a proper default tuning step for i.MX6SX and i.MX7D uSDHC to fix a tuning failure seen with some SD cards. * tag 'imx-fixes-6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: imx93: Fix anatop node size ARM: dts: imx: Set default tuning step for imx6sx usdhc arm64: dts: imx8mm: Drop CSI1 PHY reference clock configuration arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration ARM: dts: imx: Set default tuning step for imx7d usdhc ARM: dts: imx6: phytec: fix RTC interrupt level ARM: dts: imx6sx: Remove LDB endpoint Link: https://lore.kernel.org/r/20230809100034.GS151430@dragon Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
991e0d9dbb
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@ -182,7 +182,7 @@ i2c_rtc: rtc@68 {
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pinctrl-0 = <&pinctrl_rtc_int>;
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reg = <0x68>;
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interrupt-parent = <&gpio7>;
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
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status = "disabled";
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};
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};
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@ -863,7 +863,6 @@ port@0 {
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reg = <0>;
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ldb_from_lcdif1: endpoint {
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remote-endpoint = <&lcdif1_to_ldb>;
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};
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};
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@ -1010,6 +1009,8 @@ usdhc1: mmc@2190000 {
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<&clks IMX6SX_CLK_USDHC1>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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status = "disabled";
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};
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@ -1022,6 +1023,8 @@ usdhc2: mmc@2194000 {
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<&clks IMX6SX_CLK_USDHC2>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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status = "disabled";
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};
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@ -1034,6 +1037,8 @@ usdhc3: mmc@2198000 {
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<&clks IMX6SX_CLK_USDHC3>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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status = "disabled";
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};
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@ -1309,11 +1314,8 @@ lcdif1: lcdif@2220000 {
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power-domains = <&pd_disp>;
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status = "disabled";
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ports {
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port {
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lcdif1_to_ldb: endpoint {
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remote-endpoint = <&ldb_from_lcdif1>;
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};
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port {
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lcdif1_to_ldb: endpoint {
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};
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};
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};
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@ -1184,6 +1184,8 @@ usdhc1: mmc@30b40000 {
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<&clks IMX7D_USDHC1_ROOT_CLK>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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fsl,tuning-step = <2>;
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fsl,tuning-start-tap = <20>;
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status = "disabled";
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};
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@ -1196,6 +1198,8 @@ usdhc2: mmc@30b50000 {
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<&clks IMX7D_USDHC2_ROOT_CLK>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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fsl,tuning-step = <2>;
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fsl,tuning-start-tap = <20>;
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status = "disabled";
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};
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@ -1208,6 +1212,8 @@ usdhc3: mmc@30b60000 {
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<&clks IMX7D_USDHC3_ROOT_CLK>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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fsl,tuning-step = <2>;
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fsl,tuning-start-tap = <20>;
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status = "disabled";
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};
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@ -1221,10 +1221,9 @@ mipi_csi: mipi-csi@32e30000 {
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compatible = "fsl,imx8mm-mipi-csi2";
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reg = <0x32e30000 0x1000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
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<&clk IMX8MM_CLK_CSI1_PHY_REF>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
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<&clk IMX8MM_SYS_PLL2_1000M>;
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assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;
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clock-frequency = <333000000>;
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clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
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<&clk IMX8MM_CLK_CSI1_ROOT>,
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@ -1175,10 +1175,8 @@ mipi_csi: mipi-csi@32e30000 {
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compatible = "fsl,imx8mm-mipi-csi2";
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reg = <0x32e30000 0x1000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>,
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<&clk IMX8MN_CLK_CSI1_PHY_REF>;
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>,
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<&clk IMX8MN_SYS_PLL2_1000M>;
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assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
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assigned-clock-rates = <333000000>;
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clock-frequency = <333000000>;
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clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,
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@ -340,7 +340,7 @@ mediamix: power-domain@44462400 {
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anatop: anatop@44480000 {
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compatible = "fsl,imx93-anatop", "syscon";
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reg = <0x44480000 0x10000>;
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reg = <0x44480000 0x2000>;
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};
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adc1: adc@44530000 {
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