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ASoC: cs42l42: Add SoundWire support
Merge series from Stefan Binding <sbinding@opensource.cirrus.com>: The CS42L42 has a SoundWire interface for control and audio. This chain of patches adds support for this. Patches #1 .. #5 split out various changes to the existing code that are needed for adding Soundwire. These are mostly around clocking and supporting the separate probe and enumeration stages in SoundWire. Patches #6 .. #8 actually adds the SoundWire handling.
This commit is contained in:
Mark Brown
commit
98fda42a85
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@ -469,7 +469,7 @@ static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus,
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}
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/* Inform slave about the impending port prepare */
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sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_PRE_PREP);
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sdw_do_port_prep(s_rt, prep_ch, prep ? SDW_OPS_PORT_PRE_PREP : SDW_OPS_PORT_PRE_DEPREP);
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/* Prepare Slave port implementing CP_SM */
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if (!dpn_prop->simple_ch_prep_sm) {
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@ -501,7 +501,7 @@ static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus,
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}
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/* Inform slaves about ports prepared */
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sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_POST_PREP);
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sdw_do_port_prep(s_rt, prep_ch, prep ? SDW_OPS_PORT_POST_PREP : SDW_OPS_PORT_POST_DEPREP);
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/* Disable interrupt after Port de-prepare */
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if (!prep && intr)
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@ -566,13 +566,15 @@ struct sdw_prepare_ch {
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* enum sdw_port_prep_ops: Prepare operations for Data Port
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*
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* @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port
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* @SDW_OPS_PORT_PREP: Prepare operation for the Port
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* @SDW_OPS_PORT_PRE_DEPREP: Pre deprepare operation for the Port
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* @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port
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* @SDW_OPS_PORT_POST_DEPREP: Post deprepare operation for the Port
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*/
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enum sdw_port_prep_ops {
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SDW_OPS_PORT_PRE_PREP = 0,
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SDW_OPS_PORT_PREP = 1,
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SDW_OPS_PORT_POST_PREP = 2,
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SDW_OPS_PORT_PRE_DEPREP,
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SDW_OPS_PORT_POST_PREP,
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SDW_OPS_PORT_POST_DEPREP,
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};
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/**
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@ -34,6 +34,7 @@
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#define CS42L42_PAGE_24 0x2400
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#define CS42L42_PAGE_25 0x2500
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#define CS42L42_PAGE_26 0x2600
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#define CS42L42_PAGE_27 0x2700
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#define CS42L42_PAGE_28 0x2800
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#define CS42L42_PAGE_29 0x2900
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#define CS42L42_PAGE_2A 0x2A00
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@ -720,6 +721,10 @@
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#define CS42L42_SRC_SDOUT_FS (CS42L42_PAGE_26 + 0x09)
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/* Page 0x27 DMA */
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#define CS42L42_SOFT_RESET_REBOOT (CS42L42_PAGE_27 + 0x01)
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#define CS42L42_SFT_RST_REBOOT_MASK BIT(1)
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/* Page 0x28 S/PDIF Registers */
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#define CS42L42_SPDIF_CTL1 (CS42L42_PAGE_28 + 0x01)
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#define CS42L42_SPDIF_CTL2 (CS42L42_PAGE_28 + 0x02)
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@ -69,6 +69,7 @@ config SND_SOC_ALL_CODECS
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imply SND_SOC_CS35L45_I2C
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imply SND_SOC_CS35L45_SPI
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imply SND_SOC_CS42L42
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imply SND_SOC_CS42L42_SDW
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imply SND_SOC_CS42L51_I2C
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imply SND_SOC_CS42L52
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imply SND_SOC_CS42L56
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@ -722,6 +723,13 @@ config SND_SOC_CS42L42
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select REGMAP_I2C
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select SND_SOC_CS42L42_CORE
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config SND_SOC_CS42L42_SDW
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tristate "Cirrus Logic CS42L42 CODEC on Soundwire"
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depends on SOUNDWIRE
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select SND_SOC_CS42L42_CORE
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help
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Enable support for Cirrus Logic CS42L42 codec with Soundwire control
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config SND_SOC_CS42L51
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tristate
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@ -69,6 +69,7 @@ snd-soc-cs35l45-spi-objs := cs35l45-spi.o
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snd-soc-cs35l45-i2c-objs := cs35l45-i2c.o
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snd-soc-cs42l42-objs := cs42l42.o
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snd-soc-cs42l42-i2c-objs := cs42l42-i2c.o
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snd-soc-cs42l42-sdw-objs := cs42l42-sdw.o
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snd-soc-cs42l51-objs := cs42l51.o
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snd-soc-cs42l51-i2c-objs := cs42l51-i2c.o
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snd-soc-cs42l52-objs := cs42l52.o
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@ -434,6 +435,7 @@ obj-$(CONFIG_SND_SOC_CS35L45_SPI) += snd-soc-cs35l45-spi.o
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obj-$(CONFIG_SND_SOC_CS35L45_I2C) += snd-soc-cs35l45-i2c.o
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obj-$(CONFIG_SND_SOC_CS42L42_CORE) += snd-soc-cs42l42.o
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obj-$(CONFIG_SND_SOC_CS42L42) += snd-soc-cs42l42-i2c.o
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obj-$(CONFIG_SND_SOC_CS42L42_SDW) += snd-soc-cs42l42-sdw.o
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obj-$(CONFIG_SND_SOC_CS42L51) += snd-soc-cs42l51.o
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obj-$(CONFIG_SND_SOC_CS42L51_I2C) += snd-soc-cs42l51-i2c.o
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obj-$(CONFIG_SND_SOC_CS42L52) += snd-soc-cs42l52.o
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610
sound/soc/codecs/cs42l42-sdw.c
Normal file
610
sound/soc/codecs/cs42l42-sdw.c
Normal file
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@ -0,0 +1,610 @@
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// SPDX-License-Identifier: GPL-2.0-only
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// cs42l42-sdw.c -- CS42L42 ALSA SoC audio driver SoundWire driver
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//
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// Copyright (C) 2022 Cirrus Logic, Inc. and
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// Cirrus Logic International Semiconductor Ltd.
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#include <linux/acpi.h>
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#include <linux/device.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/of_irq.h>
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#include <linux/pm_runtime.h>
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#include <linux/soundwire/sdw.h>
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#include <linux/soundwire/sdw_registers.h>
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#include <linux/soundwire/sdw_type.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/sdw.h>
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#include <sound/soc.h>
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#include "cs42l42.h"
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#define CS42L42_SDW_CAPTURE_PORT 1
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#define CS42L42_SDW_PLAYBACK_PORT 2
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/* Register addresses are offset when sent over SoundWire */
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#define CS42L42_SDW_ADDR_OFFSET 0x8000
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#define CS42L42_SDW_MEM_ACCESS_STATUS 0xd0
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#define CS42L42_SDW_MEM_READ_DATA 0xd8
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#define CS42L42_SDW_LAST_LATE BIT(3)
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#define CS42L42_SDW_CMD_IN_PROGRESS BIT(2)
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#define CS42L42_SDW_RDATA_RDY BIT(0)
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#define CS42L42_DELAYED_READ_POLL_US 1
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#define CS42L42_DELAYED_READ_TIMEOUT_US 100
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static const struct snd_soc_dapm_route cs42l42_sdw_audio_map[] = {
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/* Playback Path */
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{ "HP", NULL, "MIXER" },
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{ "MIXER", NULL, "DACSRC" },
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{ "DACSRC", NULL, "Playback" },
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/* Capture Path */
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{ "ADCSRC", NULL, "HS" },
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{ "Capture", NULL, "ADCSRC" },
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};
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static int cs42l42_sdw_dai_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
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if (!cs42l42->init_done)
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return -ENODEV;
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return 0;
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}
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static int cs42l42_sdw_dai_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
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struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
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struct sdw_stream_config stream_config = {0};
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struct sdw_port_config port_config = {0};
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int ret;
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if (!sdw_stream)
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return -EINVAL;
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/* Needed for PLL configuration when we are notified of new bus config */
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cs42l42->sample_rate = params_rate(params);
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snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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port_config.num = CS42L42_SDW_PLAYBACK_PORT;
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else
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port_config.num = CS42L42_SDW_CAPTURE_PORT;
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ret = sdw_stream_add_slave(cs42l42->sdw_peripheral, &stream_config, &port_config, 1,
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sdw_stream);
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if (ret) {
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dev_err(dai->dev, "Failed to add sdw stream: %d\n", ret);
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return ret;
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}
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cs42l42_src_config(dai->component, params_rate(params));
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return 0;
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}
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static int cs42l42_sdw_dai_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
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dev_dbg(dai->dev, "dai_prepare: sclk=%u rate=%u\n", cs42l42->sclk, cs42l42->sample_rate);
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if (!cs42l42->sclk || !cs42l42->sample_rate)
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return -EINVAL;
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/*
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* At this point we know the sample rate from hw_params, and the SWIRE_CLK from bus_config()
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* callback. This could only fail if the ACPI or machine driver are misconfigured to allow
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* an unsupported SWIRE_CLK and sample_rate combination.
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*/
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return cs42l42_pll_config(dai->component, cs42l42->sclk, cs42l42->sample_rate);
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}
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static int cs42l42_sdw_dai_hw_free(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
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struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
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sdw_stream_remove_slave(cs42l42->sdw_peripheral, sdw_stream);
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cs42l42->sample_rate = 0;
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return 0;
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}
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static int cs42l42_sdw_port_prep(struct sdw_slave *slave,
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struct sdw_prepare_ch *prepare_ch,
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enum sdw_port_prep_ops state)
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{
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struct cs42l42_private *cs42l42 = dev_get_drvdata(&slave->dev);
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unsigned int pdn_mask;
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if (prepare_ch->num == CS42L42_SDW_PLAYBACK_PORT)
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pdn_mask = CS42L42_HP_PDN_MASK;
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else
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pdn_mask = CS42L42_ADC_PDN_MASK;
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if (state == SDW_OPS_PORT_PRE_PREP) {
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dev_dbg(cs42l42->dev, "Prep Port pdn_mask:%x\n", pdn_mask);
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regmap_clear_bits(cs42l42->regmap, CS42L42_PWR_CTL1, pdn_mask);
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usleep_range(CS42L42_HP_ADC_EN_TIME_US, CS42L42_HP_ADC_EN_TIME_US + 1000);
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} else if (state == SDW_OPS_PORT_POST_DEPREP) {
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dev_dbg(cs42l42->dev, "Deprep Port pdn_mask:%x\n", pdn_mask);
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regmap_set_bits(cs42l42->regmap, CS42L42_PWR_CTL1, pdn_mask);
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}
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return 0;
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}
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static int cs42l42_sdw_dai_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
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int direction)
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{
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if (!sdw_stream)
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return 0;
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if (direction == SNDRV_PCM_STREAM_PLAYBACK)
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dai->playback_dma_data = sdw_stream;
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else
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dai->capture_dma_data = sdw_stream;
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return 0;
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}
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static void cs42l42_sdw_dai_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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snd_soc_dai_set_dma_data(dai, substream, NULL);
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}
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static const struct snd_soc_dai_ops cs42l42_sdw_dai_ops = {
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.startup = cs42l42_sdw_dai_startup,
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.shutdown = cs42l42_sdw_dai_shutdown,
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.hw_params = cs42l42_sdw_dai_hw_params,
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.prepare = cs42l42_sdw_dai_prepare,
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.hw_free = cs42l42_sdw_dai_hw_free,
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.mute_stream = cs42l42_mute_stream,
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.set_stream = cs42l42_sdw_dai_set_sdw_stream,
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};
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static struct snd_soc_dai_driver cs42l42_sdw_dai = {
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.name = "cs42l42-sdw",
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.playback = {
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.stream_name = "Playback",
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.channels_min = 1,
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.channels_max = 2,
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/* Restrict which rates and formats are supported */
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S24_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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.capture = {
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.stream_name = "Capture",
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.channels_min = 1,
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.channels_max = 1,
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/* Restrict which rates and formats are supported */
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S24_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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.symmetric_rate = 1,
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.ops = &cs42l42_sdw_dai_ops,
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};
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static int cs42l42_sdw_poll_status(struct sdw_slave *peripheral, u8 mask, u8 match)
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{
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int ret, sdwret;
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ret = read_poll_timeout(sdw_read_no_pm, sdwret,
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(sdwret < 0) || ((sdwret & mask) == match),
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CS42L42_DELAYED_READ_POLL_US, CS42L42_DELAYED_READ_TIMEOUT_US,
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false, peripheral, CS42L42_SDW_MEM_ACCESS_STATUS);
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if (ret == 0)
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ret = sdwret;
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if (ret < 0)
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dev_err(&peripheral->dev, "MEM_ACCESS_STATUS & %#x for %#x fail: %d\n",
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mask, match, ret);
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return ret;
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}
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static int cs42l42_sdw_read(void *context, unsigned int reg, unsigned int *val)
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{
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struct sdw_slave *peripheral = context;
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u8 data;
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int ret;
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reg += CS42L42_SDW_ADDR_OFFSET;
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ret = cs42l42_sdw_poll_status(peripheral, CS42L42_SDW_CMD_IN_PROGRESS, 0);
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if (ret < 0)
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return ret;
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ret = sdw_read_no_pm(peripheral, reg);
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if (ret < 0) {
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dev_err(&peripheral->dev, "Failed to issue read @0x%x: %d\n", reg, ret);
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return ret;
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}
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data = (u8)ret; /* possible non-delayed read value */
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ret = sdw_read_no_pm(peripheral, CS42L42_SDW_MEM_ACCESS_STATUS);
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if (ret < 0) {
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dev_err(&peripheral->dev, "Failed to read MEM_ACCESS_STATUS: %d\n", ret);
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return ret;
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}
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/* If read was not delayed we already have the result */
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if ((ret & CS42L42_SDW_LAST_LATE) == 0) {
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*val = data;
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return 0;
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}
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/* Poll for delayed read completion */
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if ((ret & CS42L42_SDW_RDATA_RDY) == 0) {
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ret = cs42l42_sdw_poll_status(peripheral,
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CS42L42_SDW_RDATA_RDY, CS42L42_SDW_RDATA_RDY);
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if (ret < 0)
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return ret;
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}
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ret = sdw_read_no_pm(peripheral, CS42L42_SDW_MEM_READ_DATA);
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if (ret < 0) {
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dev_err(&peripheral->dev, "Failed to read READ_DATA: %d\n", ret);
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return ret;
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}
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*val = (u8)ret;
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return 0;
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}
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static int cs42l42_sdw_write(void *context, unsigned int reg, unsigned int val)
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{
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struct sdw_slave *peripheral = context;
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int ret;
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ret = cs42l42_sdw_poll_status(peripheral, CS42L42_SDW_CMD_IN_PROGRESS, 0);
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if (ret < 0)
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return ret;
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return sdw_write_no_pm(peripheral, reg + CS42L42_SDW_ADDR_OFFSET, (u8)val);
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}
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/* Initialise cs42l42 using SoundWire - this is only called once, during initialisation */
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static void cs42l42_sdw_init(struct sdw_slave *peripheral)
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{
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struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
|
||||
int ret;
|
||||
|
||||
regcache_cache_only(cs42l42->regmap, false);
|
||||
|
||||
ret = cs42l42_init(cs42l42);
|
||||
if (ret < 0) {
|
||||
regcache_cache_only(cs42l42->regmap, true);
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Write out any cached changes that happened between probe and attach */
|
||||
ret = regcache_sync(cs42l42->regmap);
|
||||
if (ret < 0)
|
||||
dev_warn(cs42l42->dev, "Failed to sync cache: %d\n", ret);
|
||||
|
||||
/* Disable internal logic that makes clock-stop conditional */
|
||||
regmap_clear_bits(cs42l42->regmap, CS42L42_PWR_CTL3, CS42L42_SW_CLK_STP_STAT_SEL_MASK);
|
||||
|
||||
err:
|
||||
/* This cancels the pm_runtime_get_noresume() call from cs42l42_sdw_probe(). */
|
||||
pm_runtime_put_autosuspend(cs42l42->dev);
|
||||
}
|
||||
|
||||
static int cs42l42_sdw_read_prop(struct sdw_slave *peripheral)
|
||||
{
|
||||
struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
|
||||
struct sdw_slave_prop *prop = &peripheral->prop;
|
||||
struct sdw_dpn_prop *ports;
|
||||
|
||||
ports = devm_kcalloc(cs42l42->dev, 2, sizeof(*ports), GFP_KERNEL);
|
||||
if (!ports)
|
||||
return -ENOMEM;
|
||||
|
||||
prop->source_ports = BIT(CS42L42_SDW_CAPTURE_PORT);
|
||||
prop->sink_ports = BIT(CS42L42_SDW_PLAYBACK_PORT);
|
||||
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
|
||||
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
|
||||
|
||||
/* DP1 - capture */
|
||||
ports[0].num = CS42L42_SDW_CAPTURE_PORT,
|
||||
ports[0].type = SDW_DPN_FULL,
|
||||
ports[0].ch_prep_timeout = 10,
|
||||
prop->src_dpn_prop = &ports[0];
|
||||
|
||||
/* DP2 - playback */
|
||||
ports[1].num = CS42L42_SDW_PLAYBACK_PORT,
|
||||
ports[1].type = SDW_DPN_FULL,
|
||||
ports[1].ch_prep_timeout = 10,
|
||||
prop->sink_dpn_prop = &ports[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cs42l42_sdw_update_status(struct sdw_slave *peripheral,
|
||||
enum sdw_slave_status status)
|
||||
{
|
||||
struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
|
||||
|
||||
switch (status) {
|
||||
case SDW_SLAVE_ATTACHED:
|
||||
dev_dbg(cs42l42->dev, "ATTACHED\n");
|
||||
/*
|
||||
* Initialise codec, this only needs to be done once.
|
||||
* When resuming from suspend, resume callback will handle re-init of codec,
|
||||
* using regcache_sync().
|
||||
*/
|
||||
if (!cs42l42->init_done)
|
||||
cs42l42_sdw_init(peripheral);
|
||||
break;
|
||||
case SDW_SLAVE_UNATTACHED:
|
||||
dev_dbg(cs42l42->dev, "UNATTACHED\n");
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cs42l42_sdw_bus_config(struct sdw_slave *peripheral,
|
||||
struct sdw_bus_params *params)
|
||||
{
|
||||
struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
|
||||
unsigned int new_sclk = params->curr_dr_freq / 2;
|
||||
|
||||
/* The cs42l42 cannot support a glitchless SWIRE_CLK change. */
|
||||
if ((new_sclk != cs42l42->sclk) && cs42l42->stream_use) {
|
||||
dev_warn(cs42l42->dev, "Rejected SCLK change while audio active\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
cs42l42->sclk = new_sclk;
|
||||
|
||||
dev_dbg(cs42l42->dev, "bus_config: sclk=%u c=%u r=%u\n",
|
||||
cs42l42->sclk, params->col, params->row);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct sdw_slave_ops cs42l42_sdw_ops = {
|
||||
/* No interrupt callback because only hardware INT is supported for Jack Detect in the CS42L42 */
|
||||
.read_prop = cs42l42_sdw_read_prop,
|
||||
.update_status = cs42l42_sdw_update_status,
|
||||
.bus_config = cs42l42_sdw_bus_config,
|
||||
.port_prep = cs42l42_sdw_port_prep,
|
||||
};
|
||||
|
||||
static int __maybe_unused cs42l42_sdw_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
|
||||
|
||||
dev_dbg(dev, "Runtime suspend\n");
|
||||
|
||||
if (!cs42l42->init_done)
|
||||
return 0;
|
||||
|
||||
/* The host controller could suspend, which would mean no register access */
|
||||
regcache_cache_only(cs42l42->regmap, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct reg_sequence __maybe_unused cs42l42_soft_reboot_seq[] = {
|
||||
REG_SEQ0(CS42L42_SOFT_RESET_REBOOT, 0x1e),
|
||||
};
|
||||
|
||||
static int __maybe_unused cs42l42_sdw_handle_unattach(struct cs42l42_private *cs42l42)
|
||||
{
|
||||
struct sdw_slave *peripheral = cs42l42->sdw_peripheral;
|
||||
|
||||
if (!peripheral->unattach_request)
|
||||
return 0;
|
||||
|
||||
/* Cannot access registers until master re-attaches. */
|
||||
dev_dbg(&peripheral->dev, "Wait for initialization_complete\n");
|
||||
if (!wait_for_completion_timeout(&peripheral->initialization_complete,
|
||||
msecs_to_jiffies(5000))) {
|
||||
dev_err(&peripheral->dev, "initialization_complete timed out\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
peripheral->unattach_request = 0;
|
||||
|
||||
/*
|
||||
* After a bus reset there must be a reconfiguration reset to
|
||||
* reinitialize the internal state of CS42L42.
|
||||
*/
|
||||
regmap_multi_reg_write_bypassed(cs42l42->regmap,
|
||||
cs42l42_soft_reboot_seq,
|
||||
ARRAY_SIZE(cs42l42_soft_reboot_seq));
|
||||
usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
|
||||
regcache_mark_dirty(cs42l42->regmap);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused cs42l42_sdw_runtime_resume(struct device *dev)
|
||||
{
|
||||
static const unsigned int ts_dbnce_ms[] = { 0, 125, 250, 500, 750, 1000, 1250, 1500};
|
||||
struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
|
||||
unsigned int dbnce;
|
||||
int ret;
|
||||
|
||||
dev_dbg(dev, "Runtime resume\n");
|
||||
|
||||
if (!cs42l42->init_done)
|
||||
return 0;
|
||||
|
||||
ret = cs42l42_sdw_handle_unattach(cs42l42);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
} else if (ret > 0) {
|
||||
dbnce = max(cs42l42->ts_dbnc_rise, cs42l42->ts_dbnc_fall);
|
||||
|
||||
if (dbnce > 0)
|
||||
msleep(ts_dbnce_ms[dbnce]);
|
||||
}
|
||||
|
||||
regcache_cache_only(cs42l42->regmap, false);
|
||||
|
||||
/* Sync LATCH_TO_VP first so the VP domain registers sync correctly */
|
||||
regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1);
|
||||
regcache_sync(cs42l42->regmap);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused cs42l42_sdw_resume(struct device *dev)
|
||||
{
|
||||
struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
dev_dbg(dev, "System resume\n");
|
||||
|
||||
/* Power-up so it can re-enumerate */
|
||||
ret = cs42l42_resume(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Wait for re-attach */
|
||||
ret = cs42l42_sdw_handle_unattach(cs42l42);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
cs42l42_resume_restore(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cs42l42_sdw_probe(struct sdw_slave *peripheral, const struct sdw_device_id *id)
|
||||
{
|
||||
struct snd_soc_component_driver *component_drv;
|
||||
struct device *dev = &peripheral->dev;
|
||||
struct cs42l42_private *cs42l42;
|
||||
struct regmap_config *regmap_conf;
|
||||
struct regmap *regmap;
|
||||
int irq, ret;
|
||||
|
||||
cs42l42 = devm_kzalloc(dev, sizeof(*cs42l42), GFP_KERNEL);
|
||||
if (!cs42l42)
|
||||
return -ENOMEM;
|
||||
|
||||
if (has_acpi_companion(dev))
|
||||
irq = acpi_dev_gpio_irq_get(ACPI_COMPANION(dev), 0);
|
||||
else
|
||||
irq = of_irq_get(dev->of_node, 0);
|
||||
|
||||
if (irq == -ENOENT)
|
||||
irq = 0;
|
||||
else if (irq < 0)
|
||||
return dev_err_probe(dev, irq, "Failed to get IRQ\n");
|
||||
|
||||
regmap_conf = devm_kmemdup(dev, &cs42l42_regmap, sizeof(cs42l42_regmap), GFP_KERNEL);
|
||||
if (!regmap_conf)
|
||||
return -ENOMEM;
|
||||
regmap_conf->reg_bits = 16;
|
||||
regmap_conf->num_ranges = 0;
|
||||
regmap_conf->reg_read = cs42l42_sdw_read;
|
||||
regmap_conf->reg_write = cs42l42_sdw_write;
|
||||
|
||||
regmap = devm_regmap_init(dev, NULL, peripheral, regmap_conf);
|
||||
if (IS_ERR(regmap))
|
||||
return dev_err_probe(dev, PTR_ERR(regmap), "Failed to allocate register map\n");
|
||||
|
||||
/* Start in cache-only until device is enumerated */
|
||||
regcache_cache_only(regmap, true);
|
||||
|
||||
component_drv = devm_kmemdup(dev,
|
||||
&cs42l42_soc_component,
|
||||
sizeof(cs42l42_soc_component),
|
||||
GFP_KERNEL);
|
||||
if (!component_drv)
|
||||
return -ENOMEM;
|
||||
|
||||
component_drv->dapm_routes = cs42l42_sdw_audio_map;
|
||||
component_drv->num_dapm_routes = ARRAY_SIZE(cs42l42_sdw_audio_map);
|
||||
|
||||
cs42l42->dev = dev;
|
||||
cs42l42->regmap = regmap;
|
||||
cs42l42->sdw_peripheral = peripheral;
|
||||
cs42l42->irq = irq;
|
||||
cs42l42->devid = CS42L42_CHIP_ID;
|
||||
|
||||
/*
|
||||
* pm_runtime is needed to control bus manager suspend, and to
|
||||
* recover from an unattach_request when the manager suspends.
|
||||
*/
|
||||
pm_runtime_set_autosuspend_delay(cs42l42->dev, 3000);
|
||||
pm_runtime_use_autosuspend(cs42l42->dev);
|
||||
pm_runtime_mark_last_busy(cs42l42->dev);
|
||||
pm_runtime_set_active(cs42l42->dev);
|
||||
pm_runtime_get_noresume(cs42l42->dev);
|
||||
pm_runtime_enable(cs42l42->dev);
|
||||
|
||||
ret = cs42l42_common_probe(cs42l42, component_drv, &cs42l42_sdw_dai);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cs42l42_sdw_remove(struct sdw_slave *peripheral)
|
||||
{
|
||||
struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
|
||||
|
||||
cs42l42_common_remove(cs42l42);
|
||||
pm_runtime_disable(cs42l42->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops cs42l42_sdw_pm = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(cs42l42_suspend, cs42l42_sdw_resume)
|
||||
SET_RUNTIME_PM_OPS(cs42l42_sdw_runtime_suspend, cs42l42_sdw_runtime_resume, NULL)
|
||||
};
|
||||
|
||||
static const struct sdw_device_id cs42l42_sdw_id[] = {
|
||||
SDW_SLAVE_ENTRY(0x01FA, 0x4242, 0),
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(sdw, cs42l42_sdw_id);
|
||||
|
||||
static struct sdw_driver cs42l42_sdw_driver = {
|
||||
.driver = {
|
||||
.name = "cs42l42-sdw",
|
||||
.pm = &cs42l42_sdw_pm,
|
||||
},
|
||||
.probe = cs42l42_sdw_probe,
|
||||
.remove = cs42l42_sdw_remove,
|
||||
.ops = &cs42l42_sdw_ops,
|
||||
.id_table = cs42l42_sdw_id,
|
||||
};
|
||||
|
||||
module_sdw_driver(cs42l42_sdw_driver);
|
||||
|
||||
MODULE_DESCRIPTION("ASoC CS42L42 SoundWire driver");
|
||||
MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_IMPORT_NS(SND_SOC_CS42L42_CORE);
|
||||
|
|
@ -20,6 +20,7 @@
|
|||
#include <linux/slab.h>
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/property.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
|
|
@ -293,6 +294,7 @@ bool cs42l42_readable_register(struct device *dev, unsigned int reg)
|
|||
case CS42L42_SPDIF_SW_CTL1:
|
||||
case CS42L42_SRC_SDIN_FS:
|
||||
case CS42L42_SRC_SDOUT_FS:
|
||||
case CS42L42_SOFT_RESET_REBOOT:
|
||||
case CS42L42_SPDIF_CTL1:
|
||||
case CS42L42_SPDIF_CTL2:
|
||||
case CS42L42_SPDIF_CTL3:
|
||||
|
|
@ -358,6 +360,7 @@ bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
|
|||
case CS42L42_LOAD_DET_DONE:
|
||||
case CS42L42_DET_STATUS1:
|
||||
case CS42L42_DET_STATUS2:
|
||||
case CS42L42_SOFT_RESET_REBOOT:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
|
|
@ -523,6 +526,10 @@ static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
|
|||
|
||||
/* Playback/Capture Requirements */
|
||||
SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0),
|
||||
|
||||
/* Soundwire SRC power control */
|
||||
SND_SOC_DAPM_PGA("DACSRC", CS42L42_PWR_CTL2, CS42L42_DAC_SRC_PDNB_SHIFT, 0, NULL, 0),
|
||||
SND_SOC_DAPM_PGA("ADCSRC", CS42L42_PWR_CTL2, CS42L42_ADC_SRC_PDNB_SHIFT, 0, NULL, 0),
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
|
||||
|
|
@ -590,7 +597,6 @@ const struct snd_soc_component_driver cs42l42_soc_component = {
|
|||
.num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map),
|
||||
.controls = cs42l42_snd_controls,
|
||||
.num_controls = ARRAY_SIZE(cs42l42_snd_controls),
|
||||
.idle_bias_on = 1,
|
||||
.endianness = 1,
|
||||
};
|
||||
EXPORT_SYMBOL_NS_GPL(cs42l42_soc_component, SND_SOC_CS42L42_CORE);
|
||||
|
|
@ -651,11 +657,11 @@ static const struct cs42l42_pll_params pll_ratio_table[] = {
|
|||
{ 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}
|
||||
};
|
||||
|
||||
static int cs42l42_pll_config(struct snd_soc_component *component, unsigned int clk)
|
||||
int cs42l42_pll_config(struct snd_soc_component *component, unsigned int clk,
|
||||
unsigned int sample_rate)
|
||||
{
|
||||
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
|
||||
int i;
|
||||
u32 fsync;
|
||||
|
||||
/* Don't reconfigure if there is an audio stream running */
|
||||
if (cs42l42->stream_use) {
|
||||
|
|
@ -666,6 +672,10 @@ static int cs42l42_pll_config(struct snd_soc_component *component, unsigned int
|
|||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
|
||||
/* MCLKint must be a multiple of the sample rate */
|
||||
if (pll_ratio_table[i].mclk_int % sample_rate)
|
||||
continue;
|
||||
|
||||
if (pll_ratio_table[i].sclk == clk) {
|
||||
cs42l42->pll_config = i;
|
||||
|
||||
|
|
@ -677,40 +687,6 @@ static int cs42l42_pll_config(struct snd_soc_component *component, unsigned int
|
|||
(pll_ratio_table[i].mclk_int !=
|
||||
24000000)) <<
|
||||
CS42L42_INTERNAL_FS_SHIFT);
|
||||
|
||||
/* Set up the LRCLK */
|
||||
fsync = clk / cs42l42->srate;
|
||||
if (((fsync * cs42l42->srate) != clk)
|
||||
|| ((fsync % 2) != 0)) {
|
||||
dev_err(component->dev,
|
||||
"Unsupported sclk %d/sample rate %d\n",
|
||||
clk,
|
||||
cs42l42->srate);
|
||||
return -EINVAL;
|
||||
}
|
||||
/* Set the LRCLK period */
|
||||
snd_soc_component_update_bits(component,
|
||||
CS42L42_FSYNC_P_LOWER,
|
||||
CS42L42_FSYNC_PERIOD_MASK,
|
||||
CS42L42_FRAC0_VAL(fsync - 1) <<
|
||||
CS42L42_FSYNC_PERIOD_SHIFT);
|
||||
snd_soc_component_update_bits(component,
|
||||
CS42L42_FSYNC_P_UPPER,
|
||||
CS42L42_FSYNC_PERIOD_MASK,
|
||||
CS42L42_FRAC1_VAL(fsync - 1) <<
|
||||
CS42L42_FSYNC_PERIOD_SHIFT);
|
||||
/* Set the LRCLK to 50% duty cycle */
|
||||
fsync = fsync / 2;
|
||||
snd_soc_component_update_bits(component,
|
||||
CS42L42_FSYNC_PW_LOWER,
|
||||
CS42L42_FSYNC_PULSE_WIDTH_MASK,
|
||||
CS42L42_FRAC0_VAL(fsync - 1) <<
|
||||
CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
|
||||
snd_soc_component_update_bits(component,
|
||||
CS42L42_FSYNC_PW_UPPER,
|
||||
CS42L42_FSYNC_PULSE_WIDTH_MASK,
|
||||
CS42L42_FRAC1_VAL(fsync - 1) <<
|
||||
CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
|
||||
if (pll_ratio_table[i].mclk_src_sel == 0) {
|
||||
/* Pass the clock straight through */
|
||||
snd_soc_component_update_bits(component,
|
||||
|
|
@ -768,8 +744,9 @@ static int cs42l42_pll_config(struct snd_soc_component *component, unsigned int
|
|||
|
||||
return -EINVAL;
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(cs42l42_pll_config, SND_SOC_CS42L42_CORE);
|
||||
|
||||
static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
|
||||
void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
|
||||
{
|
||||
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
|
||||
unsigned int fs;
|
||||
|
|
@ -801,6 +778,47 @@ static void cs42l42_src_config(struct snd_soc_component *component, unsigned int
|
|||
CS42L42_CLK_OASRC_SEL_MASK,
|
||||
fs << CS42L42_CLK_OASRC_SEL_SHIFT);
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(cs42l42_src_config, SND_SOC_CS42L42_CORE);
|
||||
|
||||
static int cs42l42_asp_config(struct snd_soc_component *component,
|
||||
unsigned int sclk, unsigned int sample_rate)
|
||||
{
|
||||
u32 fsync = sclk / sample_rate;
|
||||
|
||||
/* Set up the LRCLK */
|
||||
if (((fsync * sample_rate) != sclk) || ((fsync % 2) != 0)) {
|
||||
dev_err(component->dev,
|
||||
"Unsupported sclk %d/sample rate %d\n",
|
||||
sclk,
|
||||
sample_rate);
|
||||
return -EINVAL;
|
||||
}
|
||||
/* Set the LRCLK period */
|
||||
snd_soc_component_update_bits(component,
|
||||
CS42L42_FSYNC_P_LOWER,
|
||||
CS42L42_FSYNC_PERIOD_MASK,
|
||||
CS42L42_FRAC0_VAL(fsync - 1) <<
|
||||
CS42L42_FSYNC_PERIOD_SHIFT);
|
||||
snd_soc_component_update_bits(component,
|
||||
CS42L42_FSYNC_P_UPPER,
|
||||
CS42L42_FSYNC_PERIOD_MASK,
|
||||
CS42L42_FRAC1_VAL(fsync - 1) <<
|
||||
CS42L42_FSYNC_PERIOD_SHIFT);
|
||||
/* Set the LRCLK to 50% duty cycle */
|
||||
fsync = fsync / 2;
|
||||
snd_soc_component_update_bits(component,
|
||||
CS42L42_FSYNC_PW_LOWER,
|
||||
CS42L42_FSYNC_PULSE_WIDTH_MASK,
|
||||
CS42L42_FRAC0_VAL(fsync - 1) <<
|
||||
CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
|
||||
snd_soc_component_update_bits(component,
|
||||
CS42L42_FSYNC_PW_UPPER,
|
||||
CS42L42_FSYNC_PULSE_WIDTH_MASK,
|
||||
CS42L42_FRAC1_VAL(fsync - 1) <<
|
||||
CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
|
||||
{
|
||||
|
|
@ -891,13 +909,12 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
|
|||
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
|
||||
unsigned int channels = params_channels(params);
|
||||
unsigned int width = (params_width(params) / 8) - 1;
|
||||
unsigned int sample_rate = params_rate(params);
|
||||
unsigned int slot_width = 0;
|
||||
unsigned int val = 0;
|
||||
unsigned int bclk;
|
||||
int ret;
|
||||
|
||||
cs42l42->srate = params_rate(params);
|
||||
|
||||
if (cs42l42->bclk_ratio) {
|
||||
/* machine driver has set the BCLK/samp-rate ratio */
|
||||
bclk = cs42l42->bclk_ratio * params_rate(params);
|
||||
|
|
@ -954,11 +971,15 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
|
|||
break;
|
||||
}
|
||||
|
||||
ret = cs42l42_pll_config(component, bclk);
|
||||
ret = cs42l42_pll_config(component, bclk, sample_rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
cs42l42_src_config(component, params_rate(params));
|
||||
ret = cs42l42_asp_config(component, bclk, sample_rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
cs42l42_src_config(component, sample_rate);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -998,7 +1019,7 @@ static int cs42l42_set_bclk_ratio(struct snd_soc_dai *dai,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
|
||||
int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
|
||||
{
|
||||
struct snd_soc_component *component = dai->component;
|
||||
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
|
||||
|
|
@ -1091,6 +1112,7 @@ static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
|
|||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(cs42l42_mute_stream, SND_SOC_CS42L42_CORE);
|
||||
|
||||
#define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
|
||||
SNDRV_PCM_FMTBIT_S24_LE |\
|
||||
|
|
@ -1633,7 +1655,7 @@ static const struct cs42l42_irq_params irq_params_table[] = {
|
|||
CS42L42_TSRS_PLUG_VAL_MASK}
|
||||
};
|
||||
|
||||
static irqreturn_t cs42l42_irq_thread(int irq, void *data)
|
||||
irqreturn_t cs42l42_irq_thread(int irq, void *data)
|
||||
{
|
||||
struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
|
||||
unsigned int stickies[12];
|
||||
|
|
@ -1642,9 +1664,11 @@ static irqreturn_t cs42l42_irq_thread(int irq, void *data)
|
|||
unsigned int current_button_status;
|
||||
unsigned int i;
|
||||
|
||||
pm_runtime_get_sync(cs42l42->dev);
|
||||
mutex_lock(&cs42l42->irq_lock);
|
||||
if (cs42l42->suspended || !cs42l42->init_done) {
|
||||
mutex_unlock(&cs42l42->irq_lock);
|
||||
pm_runtime_put_autosuspend(cs42l42->dev);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
|
|
@ -1747,9 +1771,12 @@ static irqreturn_t cs42l42_irq_thread(int irq, void *data)
|
|||
}
|
||||
|
||||
mutex_unlock(&cs42l42->irq_lock);
|
||||
pm_runtime_mark_last_busy(cs42l42->dev);
|
||||
pm_runtime_put_autosuspend(cs42l42->dev);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(cs42l42_irq_thread, SND_SOC_CS42L42_CORE);
|
||||
|
||||
static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
|
||||
{
|
||||
|
|
@ -2125,6 +2152,9 @@ int cs42l42_suspend(struct device *dev)
|
|||
u8 save_regs[ARRAY_SIZE(cs42l42_shutdown_seq)];
|
||||
int i, ret;
|
||||
|
||||
if (!cs42l42->init_done)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* Wait for threaded irq handler to be idle and stop it processing
|
||||
* future interrupts. This ensures a safe disable if the interrupt
|
||||
|
|
@ -2185,6 +2215,9 @@ int cs42l42_resume(struct device *dev)
|
|||
struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
if (!cs42l42->init_done)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* If jack was unplugged and re-plugged during suspend it could
|
||||
* have changed type but the tip-sense state hasn't changed.
|
||||
|
|
@ -2369,6 +2402,18 @@ int cs42l42_init(struct cs42l42_private *cs42l42)
|
|||
if (ret != 0)
|
||||
goto err_shutdown;
|
||||
|
||||
/*
|
||||
* SRC power is linked to ASP power so doesn't work in Soundwire mode.
|
||||
* Override it and use DAPM to control SRC power for Soundwire.
|
||||
*/
|
||||
if (cs42l42->sdw_peripheral) {
|
||||
regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2,
|
||||
CS42L42_SRC_PDN_OVERRIDE_MASK |
|
||||
CS42L42_DAC_SRC_PDNB_MASK |
|
||||
CS42L42_ADC_SRC_PDNB_MASK,
|
||||
CS42L42_SRC_PDN_OVERRIDE_MASK);
|
||||
}
|
||||
|
||||
/* Setup headset detection */
|
||||
cs42l42_setup_hs_type_detect(cs42l42);
|
||||
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/mutex.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/soundwire/sdw.h>
|
||||
#include <sound/jack.h>
|
||||
#include <sound/cs42l42.h>
|
||||
#include <sound/soc-component.h>
|
||||
|
|
@ -30,13 +31,14 @@ struct cs42l42_private {
|
|||
struct gpio_desc *reset_gpio;
|
||||
struct completion pdn_done;
|
||||
struct snd_soc_jack *jack;
|
||||
struct sdw_slave *sdw_peripheral;
|
||||
struct mutex irq_lock;
|
||||
int devid;
|
||||
int irq;
|
||||
int pll_config;
|
||||
u32 sclk;
|
||||
u32 sample_rate;
|
||||
u32 bclk_ratio;
|
||||
u32 srate;
|
||||
u8 plug_state;
|
||||
u8 hs_type;
|
||||
u8 ts_inv;
|
||||
|
|
@ -62,6 +64,11 @@ extern struct snd_soc_dai_driver cs42l42_dai;
|
|||
bool cs42l42_readable_register(struct device *dev, unsigned int reg);
|
||||
bool cs42l42_volatile_register(struct device *dev, unsigned int reg);
|
||||
|
||||
int cs42l42_pll_config(struct snd_soc_component *component,
|
||||
unsigned int clk, unsigned int sample_rate);
|
||||
void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate);
|
||||
int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream);
|
||||
irqreturn_t cs42l42_irq_thread(int irq, void *data);
|
||||
int cs42l42_suspend(struct device *dev);
|
||||
int cs42l42_resume(struct device *dev);
|
||||
void cs42l42_resume_restore(struct device *dev);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user