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wifi: rtw89: 8852b: add chip_ops related to BT coexistence
These chip_ops are used to assist BT coexistence module to control chip specific operations, such as initial, pre-AGC, BT grant, set wifi priority and tx power, RX gain, and get BT counter. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20221009125403.19662-6-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
Kalle Valo
parent
8f88474ce3
commit
98bf0ddf20
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@ -3151,6 +3151,7 @@
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#define BTC_BREAK_PARAM 0xf0ffffff
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#define R_BTC_BT_COEX_MSK_TABLE 0xDA30
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#define B_BTC_PRI_MASK_RXCCK_V1 BIT(28)
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#define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3)
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#define R_AX_BT_COEX_CFG_2 0xDA34
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@ -56,6 +56,44 @@ static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = {
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NULL},
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};
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static const struct rtw89_reg3_def rtw8852b_btc_preagc_en_defs[] = {
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{0x46D0, GENMASK(1, 0), 0x3},
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{0x4790, GENMASK(1, 0), 0x3},
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{0x4AD4, GENMASK(31, 0), 0xf},
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{0x4AE0, GENMASK(31, 0), 0xf},
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{0x4688, GENMASK(31, 24), 0x80},
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{0x476C, GENMASK(31, 24), 0x80},
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{0x4694, GENMASK(7, 0), 0x80},
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{0x4694, GENMASK(15, 8), 0x80},
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{0x4778, GENMASK(7, 0), 0x80},
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{0x4778, GENMASK(15, 8), 0x80},
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{0x4AE4, GENMASK(23, 0), 0x780D1E},
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{0x4AEC, GENMASK(23, 0), 0x780D1E},
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{0x469C, GENMASK(31, 26), 0x34},
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{0x49F0, GENMASK(31, 26), 0x34},
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};
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static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_en_defs);
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static const struct rtw89_reg3_def rtw8852b_btc_preagc_dis_defs[] = {
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{0x46D0, GENMASK(1, 0), 0x0},
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{0x4790, GENMASK(1, 0), 0x0},
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{0x4AD4, GENMASK(31, 0), 0x60},
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{0x4AE0, GENMASK(31, 0), 0x60},
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{0x4688, GENMASK(31, 24), 0x1a},
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{0x476C, GENMASK(31, 24), 0x1a},
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{0x4694, GENMASK(7, 0), 0x2a},
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{0x4694, GENMASK(15, 8), 0x2a},
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{0x4778, GENMASK(7, 0), 0x2a},
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{0x4778, GENMASK(15, 8), 0x2a},
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{0x4AE4, GENMASK(23, 0), 0x79E99E},
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{0x4AEC, GENMASK(23, 0), 0x79E99E},
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{0x469C, GENMASK(31, 26), 0x26},
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{0x49F0, GENMASK(31, 26), 0x26},
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};
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static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_dis_defs);
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static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev)
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{
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u32 val32;
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@ -1397,6 +1435,55 @@ rtw8852b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
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return 0;
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}
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static void rtw8852b_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
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{
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rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852b_btc_preagc_en_defs_tbl :
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&rtw8852b_btc_preagc_dis_defs_tbl);
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}
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static void rtw8852b_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
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{
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if (btg) {
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rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
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B_PATH0_BT_SHARE_V1, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
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B_PATH0_BTG_PATH_V1, 0x0);
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rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
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B_PATH1_G_LNA6_OP1DB_V1, 0x20);
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rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
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B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30);
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rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
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B_PATH1_BT_SHARE_V1, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
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B_PATH1_BTG_PATH_V1, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
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rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x2);
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rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
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B_BT_DYN_DC_EST_EN_MSK, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1);
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} else {
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rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
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B_PATH0_BT_SHARE_V1, 0x0);
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rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
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B_PATH0_BTG_PATH_V1, 0x0);
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rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
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B_PATH1_G_LNA6_OP1DB_V1, 0x1a);
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rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
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B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a);
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rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
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B_PATH1_BT_SHARE_V1, 0x0);
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rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
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B_PATH1_BTG_PATH_V1, 0x0);
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rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc);
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rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
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rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
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rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
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B_BT_DYN_DC_EST_EN_MSK, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
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}
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}
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static u8 rtw8852b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
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{
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if (rtwdev->is_tssi_mode[rf_path]) {
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@ -1414,6 +1501,212 @@ static u8 rtw8852b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_p
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return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
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}
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static void rtw8852b_btc_set_rfe(struct rtw89_dev *rtwdev)
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{
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struct rtw89_btc *btc = &rtwdev->btc;
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struct rtw89_btc_module *module = &btc->mdinfo;
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module->rfe_type = rtwdev->efuse.rfe_type;
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module->cv = rtwdev->hal.cv;
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module->bt_solo = 0;
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module->switch_type = BTC_SWITCH_INTERNAL;
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if (module->rfe_type > 0)
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module->ant.num = module->rfe_type % 2 ? 2 : 3;
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else
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module->ant.num = 2;
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module->ant.diversity = 0;
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module->ant.isolation = 10;
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if (module->ant.num == 3) {
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module->ant.type = BTC_ANT_DEDICATED;
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module->bt_pos = BTC_BT_ALONE;
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} else {
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module->ant.type = BTC_ANT_SHARED;
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module->bt_pos = BTC_BT_BTG;
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}
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}
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static
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void rtw8852b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
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{
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rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000);
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rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
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rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
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rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
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}
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static void rtw8852b_btc_init_cfg(struct rtw89_dev *rtwdev)
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{
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struct rtw89_btc *btc = &rtwdev->btc;
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struct rtw89_btc_module *module = &btc->mdinfo;
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const struct rtw89_chip_info *chip = rtwdev->chip;
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const struct rtw89_mac_ax_coex coex_params = {
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.pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
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.direction = RTW89_MAC_AX_COEX_INNER,
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};
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/* PTA init */
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rtw89_mac_coex_init(rtwdev, &coex_params);
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/* set WL Tx response = Hi-Pri */
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chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
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chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
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/* set rf gnt debug off */
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0);
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/* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
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if (module->ant.type == BTC_ANT_SHARED) {
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rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
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rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
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/* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
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rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
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rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x55f);
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} else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
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rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
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rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
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rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
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rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x5ff);
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}
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/* set PTA break table */
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rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
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/* enable BT counter 0xda40[16,2] = 2b'11 */
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rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
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btc->cx.wl.status.map.init_ok = true;
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}
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static
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void rtw8852b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
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{
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u32 bitmap;
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u32 reg;
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switch (map) {
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case BTC_PRI_MASK_TX_RESP:
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reg = R_BTC_BT_COEX_MSK_TABLE;
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bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
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break;
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case BTC_PRI_MASK_BEACON:
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reg = R_AX_WL_PRI_MSK;
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bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
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break;
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case BTC_PRI_MASK_RX_CCK:
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reg = R_BTC_BT_COEX_MSK_TABLE;
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bitmap = B_BTC_PRI_MASK_RXCCK_V1;
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break;
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default:
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return;
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}
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if (state)
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rtw89_write32_set(rtwdev, reg, bitmap);
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else
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rtw89_write32_clr(rtwdev, reg, bitmap);
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}
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union rtw8852b_btc_wl_txpwr_ctrl {
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u32 txpwr_val;
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struct {
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union {
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u16 ctrl_all_time;
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struct {
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s16 data:9;
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u16 rsvd:6;
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u16 flag:1;
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} all_time;
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};
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union {
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u16 ctrl_gnt_bt;
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struct {
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s16 data:9;
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u16 rsvd:7;
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} gnt_bt;
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};
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};
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} __packed;
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static void
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rtw8852b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
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{
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union rtw8852b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
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s32 val;
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#define __write_ctrl(_reg, _msk, _val, _en, _cond) \
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do { \
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u32 _wrt = FIELD_PREP(_msk, _val); \
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BUILD_BUG_ON(!!(_msk & _en)); \
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if (_cond) \
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_wrt |= _en; \
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else \
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_wrt &= ~_en; \
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rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
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_msk | _en, _wrt); \
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} while (0)
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switch (arg.ctrl_all_time) {
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case 0xffff:
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val = 0;
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break;
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default:
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val = arg.all_time.data;
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break;
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}
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__write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
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val, B_AX_FORCE_PWR_BY_RATE_EN,
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arg.ctrl_all_time != 0xffff);
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switch (arg.ctrl_gnt_bt) {
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case 0xffff:
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val = 0;
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break;
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default:
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val = arg.gnt_bt.data;
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break;
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}
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__write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
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B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
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#undef __write_ctrl
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}
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static
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s8 rtw8852b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
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{
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return clamp_t(s8, val, -100, 0) + 100;
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}
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static
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void rtw8852b_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
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{
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/* Feature move to firmware */
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}
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static void rtw8852b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
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{
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x31);
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/* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
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if (state)
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x579);
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else
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x20);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
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}
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static void rtw8852b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
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{
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}
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static int rtw8852b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
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{
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int ret;
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@ -1481,8 +1774,20 @@ static const struct rtw89_chip_ops rtw8852b_chip_ops = {
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.set_txpwr_ctrl = rtw8852b_set_txpwr_ctrl,
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.init_txpwr_unit = rtw8852b_init_txpwr_unit,
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.get_thermal = rtw8852b_get_thermal,
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.ctrl_btg = rtw8852b_ctrl_btg,
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.bb_ctrl_btc_preagc = rtw8852b_bb_ctrl_btc_preagc,
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.pwr_on_func = rtw8852b_pwr_on_func,
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.pwr_off_func = rtw8852b_pwr_off_func,
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.btc_set_rfe = rtw8852b_btc_set_rfe,
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.btc_init_cfg = rtw8852b_btc_init_cfg,
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.btc_set_wl_pri = rtw8852b_btc_set_wl_pri,
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.btc_set_wl_txpwr_ctrl = rtw8852b_btc_set_wl_txpwr_ctrl,
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.btc_get_bt_rssi = rtw8852b_btc_get_bt_rssi,
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.btc_update_bt_cnt = rtw8852b_btc_update_bt_cnt,
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.btc_wl_s1_standby = rtw8852b_btc_wl_s1_standby,
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.btc_set_wl_rx_gain = rtw8852b_btc_set_wl_rx_gain,
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||||
.btc_set_policy = rtw89_btc_set_policy,
|
||||
};
|
||||
|
||||
const struct rtw89_chip_info rtw8852b_chip_info = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user