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perf vendor events intel: Update lunarlake events from 1.21 to 1.22

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The updated events and metrics were published in:

  fae822a0f9

Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andreas Färber <afaerber@suse.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers 2026-05-28 21:51:50 -07:00 committed by Arnaldo Carvalho de Melo
parent 8036f15685
commit 988e264ae9
3 changed files with 30 additions and 1 deletions
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20
tools/perf/pmu-events/arch/x86/lunarlake/cache.json
View File

@ -289,6 +289,16 @@
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x24",
"EventName": "L2_REQUEST.HIT",
"PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]",
"SampleAfterValue": "200003",
"UMask": "0x5f",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of total L2 Cache Accesses that resulted in a Miss from a front door request only (does not include rejects or recycles), per core event",
"Counter": "0,1,2,3,4,5,6,7",
@ -387,6 +397,16 @@
"UMask": "0x21",
"Unit": "cpu_core"
},
{
"BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x24",
"EventName": "L2_RQSTS.HIT",
"PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]",
"SampleAfterValue": "200003",
"UMask": "0x5f",
"Unit": "cpu_core"
},
{
"BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_REQUEST.MISS]",
"Counter": "0,1,2,3,4,5,6,7,8,9",

9
tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json
View File

@ -315,6 +315,15 @@
"UMask": "0xfd",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of relative JMP branch instructions retired.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.REL_JMP",
"SampleAfterValue": "200003",
"UMask": "0xdf",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
"Counter": "0,1,2,3,4,5,6,7",

2
tools/perf/pmu-events/arch/x86/mapfile.csv
View File

@ -22,7 +22,7 @@ GenuineIntel-6-3A,v24,ivybridge,core
GenuineIntel-6-3E,v24,ivytown,core
GenuineIntel-6-2D,v24,jaketown,core
GenuineIntel-6-(57|85),v16,knightslanding,core
GenuineIntel-6-BD,v1.21,lunarlake,core
GenuineIntel-6-BD,v1.22,lunarlake,core
GenuineIntel-6-(AA|AC|B5),v1.20,meteorlake,core
GenuineIntel-6-1[AEF],v4,nehalemep,core
GenuineIntel-6-2E,v4,nehalemex,core

1 Family-model Version Filename EventType
22 GenuineIntel-6-3E v24 ivytown core
23 GenuineIntel-6-2D v24 jaketown core
24 GenuineIntel-6-(57|85) v16 knightslanding core
25 GenuineIntel-6-BD v1.21 v1.22 lunarlake core
26 GenuineIntel-6-(AA|AC|B5) v1.20 meteorlake core
27 GenuineIntel-6-1[AEF] v4 nehalemep core
28 GenuineIntel-6-2E v4 nehalemex core