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drm/i915: Add separate defines for cursor WM/DDB register bits

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Make a more thorough split between universal planes vs. cursors
by defining the contents of the cursor WM/DDB registers separately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-8-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä 2024-05-16 16:56:16 +03:00
parent 0ff7639bb1
commit 9871927034
4 changed files with 39 additions and 11 deletions
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34
drivers/gpu/drm/i915/display/intel_cursor.c
View File

@ -24,7 +24,6 @@
#include "intel_psr.h"
#include "intel_psr_regs.h"
#include "intel_vblank.h"
#include "skl_universal_plane.h"
#include "skl_watermark.h"
#include "gem/i915_gem_object.h"
@ -559,6 +558,29 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
}
}
static u32 skl_cursor_ddb_reg_val(const struct skl_ddb_entry *entry)
{
if (!entry->end)
return 0;
return CUR_BUF_END(entry->end - 1) |
CUR_BUF_START(entry->start);
}
static u32 skl_cursor_wm_reg_val(const struct skl_wm_level *level)
{
u32 val = 0;
if (level->enable)
val |= CUR_WM_EN;
if (level->ignore_lines)
val |= CUR_WM_IGNORE_LINES;
val |= REG_FIELD_PREP(CUR_WM_BLOCKS_MASK, level->blocks);
val |= REG_FIELD_PREP(CUR_WM_LINES_MASK, level->lines);
return val;
}
static void skl_write_cursor_wm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
@ -572,22 +594,22 @@ static void skl_write_cursor_wm(struct intel_plane *plane,
for (level = 0; level < i915->display.wm.num_levels; level++)
intel_de_write_fw(i915, CUR_WM(pipe, level),
skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
if (HAS_HW_SAGV_WM(i915)) {
const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
skl_plane_wm_reg_val(&wm->sagv.wm0));
skl_cursor_wm_reg_val(&wm->sagv.wm0));
intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
skl_plane_wm_reg_val(&wm->sagv.trans_wm));
skl_cursor_wm_reg_val(&wm->sagv.trans_wm));
}
intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
skl_plane_ddb_reg_val(ddb));
skl_cursor_ddb_reg_val(ddb));
}
/* TODO: split into noarm+arm pair */

9
drivers/gpu/drm/i915/display/intel_cursor_regs.h
View File

@ -78,6 +78,10 @@
#define _CUR_WM_A_0 0x70140
#define _CUR_WM_B_0 0x71140
#define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + (level) * 4)
#define CUR_WM_EN REG_BIT(31)
#define CUR_WM_IGNORE_LINES REG_BIT(30)
#define CUR_WM_LINES_MASK REG_GENMASK(26, 14)
#define CUR_WM_BLOCKS_MASK REG_GENMASK(11, 0)
#define _CUR_WM_SAGV_A 0x70158
#define _CUR_WM_SAGV_B 0x71158
@ -94,6 +98,11 @@
#define _CUR_BUF_CFG_A 0x7017c
#define _CUR_BUF_CFG_B 0x7117c
#define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
#define CUR_BUF_END_MASK REG_GENMASK(27, 16)
#define CUR_BUF_END(end) REG_FIELD_PREP(CUR_BUF_END_MASK, (end))
#define CUR_BUF_START_MASK REG_GENMASK(11, 0)
#define CUR_BUF_START(start) REG_FIELD_PREP(CUR_BUF_START_MASK, (start))
/* tgl+ */
#define _SEL_FETCH_CUR_CTL_A 0x70880

4
drivers/gpu/drm/i915/display/skl_universal_plane.c
View File

@ -622,7 +622,7 @@ static u32 skl_plane_stride(const struct intel_plane_state *plane_state,
return stride / skl_plane_stride_mult(fb, color_plane, rotation);
}
u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
{
if (!entry->end)
return 0;
@ -631,7 +631,7 @@ u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
PLANE_BUF_START(entry->start);
}
u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
{
u32 val = 0;

3
drivers/gpu/drm/i915/display/skl_universal_plane.h
View File

@ -37,7 +37,4 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
u8 icl_hdr_plane_mask(void);
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry);
u32 skl_plane_wm_reg_val(const struct skl_wm_level *level);
#endif