diff --git a/.mailmap b/.mailmap index 34acd34bbf9b..b78aa092b4bb 100644 --- a/.mailmap +++ b/.mailmap @@ -19,6 +19,7 @@ Abhinav Kumar Ahmad Masri Adam Oldham Adam Radford +Aditya Garg Adriana Reus Adrian Bunk Ajay Kaher @@ -207,6 +208,7 @@ Claudiu Beznea Colin Ian King Corey Minyard Damian Hobson-Garcia +Dan Carpenter Dan Carpenter Dan Williams Daniel Borkmann @@ -495,6 +497,7 @@ Leon Romanovsky Leon Romanovsky Leon Romanovsky Leo Yan +Liam R. Howlett Liam Mark Linas Vepstas Linus Lüssing @@ -505,6 +508,8 @@ Linus Walleij Linus Walleij Linus Walleij +Li Wang +Li Wang Li Yang Li Yang Lior David @@ -687,6 +692,7 @@ Punit Agrawal Puranjay Mohan Qais Yousef Qais Yousef +Qi Zheng Quentin Monnet Quentin Monnet Quentin Perret diff --git a/Documentation/admin-guide/cgroup-v2.rst b/Documentation/admin-guide/cgroup-v2.rst index 8ad0b2781317..6efd0095ed99 100644 --- a/Documentation/admin-guide/cgroup-v2.rst +++ b/Documentation/admin-guide/cgroup-v2.rst @@ -220,7 +220,7 @@ cgroup v2 currently supports the following mount options. memory_hugetlb_accounting Count HugeTLB memory usage towards the cgroup's overall memory usage for the memory controller (for the purpose of - statistics reporting and memory protetion). This is a new + statistics reporting and memory protection). This is a new behavior that could regress existing setups, so it must be explicitly opted in with this mount option. diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index 7c4d6170491d..f5c584cf2146 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -24,6 +24,7 @@ properties: compatible: items: - enum: + - qcom,eliza-ipcc - qcom,glymur-ipcc - qcom,kaanapali-ipcc - qcom,milos-ipcc diff --git a/Documentation/filesystems/isofs.rst b/Documentation/filesystems/isofs.rst index 08fd469091d4..2a30999b024f 100644 --- a/Documentation/filesystems/isofs.rst +++ b/Documentation/filesystems/isofs.rst @@ -57,7 +57,7 @@ Mount options unique to the isofs filesystem. Recommended documents about ISO 9660 standard are located at: - http://www.y-adagio.com/ -- ftp://ftp.ecma.ch/ecma-st/Ecma-119.pdf +- https://ecma-international.org/wp-content/uploads/ECMA-119_2nd_edition_december_1987.pdf Quoting from the PDF "This 2nd Edition of Standard ECMA-119 is technically identical with ISO 9660.", so it is a valid and gratis substitute of the diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst index 033167025fcc..d553dd599c96 100644 --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst @@ -233,8 +233,15 @@ we have a dedicated glossary for Display Core at TC Texture Cache + TCC + Texture Cache per Channel - L2 cache attached to the memory channels. + May be used when shader cores are accessing memory. + Despite "Texture" in the name, this is used by any kind of memory access. + TCCs may be mapped to TCPs, depending on the architecture. + TCP (AMDGPU) - Texture Cache per Pipe. Even though the name "Texture" is part of this + Texture Cache per Pipe - L1 cache attached to each CU. + Even though the name "Texture" is part of this acronym, the TCP represents the path to memory shaders; i.e., it is not related to texture. The name is a leftover from older designs where shader stages had different cache designs; it refers to the L1 cache in older diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst index 2292e65f044c..fbe0583eb84c 100644 --- a/Documentation/gpu/drm-kms.rst +++ b/Documentation/gpu/drm-kms.rst @@ -206,11 +206,11 @@ Atomic Mode Setting style=dashed label="Free-standing state" - "drm_atomic_state" -> "duplicated drm_plane_state A" - "drm_atomic_state" -> "duplicated drm_plane_state B" - "drm_atomic_state" -> "duplicated drm_crtc_state" - "drm_atomic_state" -> "duplicated drm_connector_state" - "drm_atomic_state" -> "duplicated driver private state" + "drm_atomic_commit" -> "duplicated drm_plane_state A" + "drm_atomic_commit" -> "duplicated drm_plane_state B" + "drm_atomic_commit" -> "duplicated drm_crtc_state" + "drm_atomic_commit" -> "duplicated drm_connector_state" + "drm_atomic_commit" -> "duplicated driver private state" } subgraph cluster_current { @@ -230,7 +230,7 @@ Atomic Mode Setting "driver private object" -> "driver private state" } - "drm_atomic_state" -> "drm_device" [label="atomic_commit"] + "drm_atomic_commit" -> "drm_device" [label="atomic_commit"] "duplicated drm_plane_state A" -> "drm_device"[style=invis] } @@ -265,7 +265,7 @@ Taken all together there's two consequences for the atomic design: drm_private_state`. - An atomic update is assembled and validated as an entirely free-standing pile - of structures within the :c:type:`drm_atomic_state ` + of structures within the :c:type:`drm_atomic_commit ` container. Driver private state structures are also tracked in the same structure; see the next chapter. Only when a state is committed is it applied to the driver and modeset objects. This way rolling back an update boils down diff --git a/Documentation/gpu/drm-ras.rst b/Documentation/gpu/drm-ras.rst index 70b246a78fc8..4636e68f5678 100644 --- a/Documentation/gpu/drm-ras.rst +++ b/Documentation/gpu/drm-ras.rst @@ -52,6 +52,8 @@ User space tools can: as a parameter. * Query specific error counter values with the ``get-error-counter`` command, using both ``node-id`` and ``error-id`` as parameters. +* Clear specific error counters with the ``clear-error-counter`` command, using both + ``node-id`` and ``error-id`` as parameters. YAML-based Interface -------------------- @@ -101,3 +103,9 @@ Example: Query an error counter for a given node sudo ynl --family drm_ras --do get-error-counter --json '{"node-id":0, "error-id":1}' {'error-id': 1, 'error-name': 'error_name1', 'error-value': 0} +Example: Clear an error counter for a given node + +.. code-block:: bash + + sudo ynl --family drm_ras --do clear-error-counter --json '{"node-id":0, "error-id":1}' + None diff --git a/Documentation/gpu/komeda-kms.rst b/Documentation/gpu/komeda-kms.rst index eaea40eb725b..9c0745940659 100644 --- a/Documentation/gpu/komeda-kms.rst +++ b/Documentation/gpu/komeda-kms.rst @@ -367,7 +367,7 @@ So, one KMS-Obj represents a sub-pipeline of komeda resources. So, for komeda, we treat KMS crtc/plane/connector as users of pipeline and component, and at any one time a pipeline/component only can be used by one user. And pipeline/component will be treated as private object of DRM-KMS; the -state will be managed by drm_atomic_state as well. +state will be managed by drm_atomic_commit as well. How to map plane to Layer(input) pipeline ----------------------------------------- @@ -416,8 +416,8 @@ Add :c:type:`drm_private_obj` to :c:type:`komeda_component`, :c:type:`komeda_pip ... } -Tracking component_state/pipeline_state by drm_atomic_state ------------------------------------------------------------ +Tracking component_state/pipeline_state by drm_atomic_commit +------------------------------------------------------------ Add :c:type:`drm_private_state` and user to :c:type:`komeda_component_state`, :c:type:`komeda_pipeline_state` @@ -454,7 +454,7 @@ similar, usually including the following steps: put the data flow into next stage. Setup 2: check user_state with component features and capabilities to see if requirements can be met; if not, return fail. - Setup 3: get component_state from drm_atomic_state, and try set to set + Setup 3: get component_state from drm_atomic_commit, and try set to set user to component; fail if component has been assigned to another user already. Setup 3: configure the component_state, like set its input component, diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index bc9f14c8a2ec..cdddf8db35f5 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -152,29 +152,6 @@ Contact: Simona Vetter, respective driver maintainers Level: Advanced -Rename drm_atomic_state ------------------------ - -The KMS framework uses two slightly different definitions for the ``state`` -concept. For a given object (plane, CRTC, encoder, etc., so -``drm_$OBJECT_state``), the state is the entire state of that object. However, -at the device level, ``drm_atomic_state`` refers to a state update for a -limited number of objects. - -The state isn't the entire device state, but only the full state of some -objects in that device. This is confusing to newcomers, and -``drm_atomic_state`` should be renamed to something clearer like -``drm_atomic_commit``. - -In addition to renaming the structure itself, it would also imply renaming some -related functions (``drm_atomic_state_alloc``, ``drm_atomic_state_get``, -``drm_atomic_state_put``, ``drm_atomic_state_init``, -``__drm_atomic_state_free``, etc.). - -Contact: Maxime Ripard - -Level: Advanced - Fallout from atomic KMS ----------------------- diff --git a/Documentation/gpu/xe/index.rst b/Documentation/gpu/xe/index.rst index bc432c95d1a3..874ffcb6da3a 100644 --- a/Documentation/gpu/xe/index.rst +++ b/Documentation/gpu/xe/index.rst @@ -29,3 +29,4 @@ DG2, etc is provided to prototype the driver. xe_device xe-drm-usage-stats.rst xe_configfs + xe_gt_stats diff --git a/Documentation/gpu/xe/xe_gt_stats.rst b/Documentation/gpu/xe/xe_gt_stats.rst new file mode 100644 index 000000000000..5ff806abaddb --- /dev/null +++ b/Documentation/gpu/xe/xe_gt_stats.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +================ +Xe GT Statistics +================ + +.. kernel-doc:: drivers/gpu/drm/xe/xe_gt_stats.c + :doc: Xe GT Statistics + +.. kernel-doc:: drivers/gpu/drm/xe/xe_gt_stats_types.h + :internal: diff --git a/Documentation/netlink/specs/drm_ras.yaml b/Documentation/netlink/specs/drm_ras.yaml index 79af25dac3c5..e113056f8c01 100644 --- a/Documentation/netlink/specs/drm_ras.yaml +++ b/Documentation/netlink/specs/drm_ras.yaml @@ -99,7 +99,7 @@ operations: flags: [admin-perm] do: request: - attributes: + attributes: &id-attrs - node-id - error-id reply: @@ -113,3 +113,14 @@ operations: - node-id reply: attributes: *errorinfo + - + name: clear-error-counter + doc: >- + Clear error counter for a given node. + The request includes the error-id and node-id of the + counter to be cleared. + attribute-set: error-counter-attrs + flags: [admin-perm] + do: + request: + attributes: *id-attrs diff --git a/Documentation/netlink/specs/psp.yaml b/Documentation/netlink/specs/psp.yaml index 100c36cda8e5..bfcd6e4ecb85 100644 --- a/Documentation/netlink/specs/psp.yaml +++ b/Documentation/netlink/specs/psp.yaml @@ -188,6 +188,7 @@ operations: name: dev-set doc: Set the configuration of a PSP device. attribute-set: dev + flags: [admin-perm] do: request: attributes: @@ -207,6 +208,7 @@ operations: name: key-rotate doc: Rotate the device key. attribute-set: dev + flags: [admin-perm] do: request: attributes: diff --git a/MAINTAINERS b/MAINTAINERS index e3d22cb168b2..2e8d160babc2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7875,7 +7875,7 @@ F: drivers/gpu/drm/sun4i/sun8i* DRM DRIVER FOR APPLE TOUCH BARS M: Aun-Ali Zaidi -M: Aditya Garg +M: Aditya Garg L: dri-devel@lists.freedesktop.org S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git @@ -13869,7 +13869,6 @@ M: Pratyush Yadav R: Dave Young L: kexec@lists.infradead.org S: Maintained -W: http://lse.sourceforge.net/kdump/ F: Documentation/admin-guide/kdump/ F: fs/proc/vmcore.c F: include/linux/crash_core.h @@ -15261,7 +15260,7 @@ M: Andrea Cervesato M: Cyril Hrubis M: Jan Stancek M: Petr Vorel -M: Li Wang +M: Li Wang M: Yang Xu M: Xiao Yang L: ltp@lists.linux.it (subscribers-only) @@ -15408,7 +15407,7 @@ F: include/net/netns/mctp.h F: net/mctp/ MAPLE TREE -M: Liam R. Howlett +M: Liam R. Howlett R: Alice Ryhl R: Andrew Ballance L: maple-tree@lists.infradead.org @@ -16768,7 +16767,7 @@ MEMORY MANAGEMENT - CORE M: Andrew Morton M: David Hildenbrand R: Lorenzo Stoakes -R: Liam R. Howlett +R: Liam R. Howlett R: Vlastimil Babka R: Mike Rapoport R: Suren Baghdasaryan @@ -16814,7 +16813,7 @@ F: mm/sparse.c F: mm/util.c F: mm/vmpressure.c F: mm/vmstat.c -N: include/linux/page[-_]* +N: include\/linux\/page[-_][a-zA-Z]* MEMORY MANAGEMENT - EXECMEM M: Andrew Morton @@ -16904,7 +16903,7 @@ MEMORY MANAGEMENT - MISC M: Andrew Morton M: David Hildenbrand R: Lorenzo Stoakes -R: Liam R. Howlett +R: Liam R. Howlett R: Vlastimil Babka R: Mike Rapoport R: Suren Baghdasaryan @@ -16971,6 +16970,7 @@ S: Maintained F: include/linux/compaction.h F: include/linux/gfp.h F: include/linux/page-isolation.h +F: include/linux/pageblock-flags.h F: mm/compaction.c F: mm/debug_page_alloc.c F: mm/debug_page_ref.c @@ -16992,7 +16992,7 @@ M: Andrew Morton M: Johannes Weiner R: David Hildenbrand R: Michal Hocko -R: Qi Zheng +R: Qi Zheng R: Shakeel Butt R: Lorenzo Stoakes L: linux-mm@kvack.org @@ -17005,7 +17005,7 @@ M: Andrew Morton M: David Hildenbrand M: Lorenzo Stoakes R: Rik van Riel -R: Liam R. Howlett +R: Liam R. Howlett R: Vlastimil Babka R: Harry Yoo R: Jann Horn @@ -17052,7 +17052,7 @@ M: David Hildenbrand M: Lorenzo Stoakes R: Zi Yan R: Baolin Wang -R: Liam R. Howlett +R: Liam R. Howlett R: Nico Pache R: Ryan Roberts R: Dev Jain @@ -17090,7 +17090,7 @@ F: tools/testing/selftests/mm/uffd-*.[ch] MEMORY MANAGEMENT - RUST M: Alice Ryhl R: Lorenzo Stoakes -R: Liam R. Howlett +R: Liam R. Howlett L: linux-mm@kvack.org L: rust-for-linux@vger.kernel.org S: Maintained @@ -17104,7 +17104,7 @@ F: rust/kernel/page.rs MEMORY MAPPING M: Andrew Morton -M: Liam R. Howlett +M: Liam R. Howlett M: Lorenzo Stoakes R: Vlastimil Babka R: Jann Horn @@ -17136,7 +17136,7 @@ F: tools/testing/vma/ MEMORY MAPPING - LOCKING M: Andrew Morton M: Suren Baghdasaryan -M: Liam R. Howlett +M: Liam R. Howlett M: Lorenzo Stoakes R: Vlastimil Babka R: Shakeel Butt @@ -17151,7 +17151,7 @@ F: mm/mmap_lock.c MEMORY MAPPING - MADVISE (MEMORY ADVICE) M: Andrew Morton -M: Liam R. Howlett +M: Liam R. Howlett M: Lorenzo Stoakes M: David Hildenbrand R: Vlastimil Babka @@ -18681,19 +18681,59 @@ F: net/xfrm/ F: tools/testing/selftests/net/ipsec.c NETWORKING [IPv4/IPv6] -M: "David S. Miller" M: David Ahern +M: Ido Schimmel L: netdev@vger.kernel.org S: Maintained -T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git -F: arch/x86/net/* -F: include/linux/ip.h -F: include/linux/ipv6* +F: Documentation/netlink/specs/rt-addr.yaml +F: Documentation/netlink/specs/rt-neigh.yaml +F: Documentation/netlink/specs/rt-route.yaml +F: Documentation/netlink/specs/rt-rule.yaml +F: include/linux/inetdevice.h +F: include/linux/mroute* +F: include/net/addrconf.h +F: include/net/arp.h F: include/net/fib* +F: include/net/if_inet6.h +F: include/net/inetpeer.h F: include/net/ip* +F: include/net/lwtunnel.h +F: include/net/ndisc.h +F: include/net/netns/nexthop.h +F: include/net/nexthop.h F: include/net/route.h -F: net/ipv4/ -F: net/ipv6/ +F: include/uapi/linux/fib_rules.h +F: include/uapi/linux/in_route.h +F: include/uapi/linux/mroute* +F: include/uapi/linux/nexthop.h +F: net/core/fib* +F: net/core/lwtunnel.c +F: net/ipv4/arp.c +F: net/ipv4/devinet.c +F: net/ipv4/fib* +F: net/ipv4/icmp.c +F: net/ipv4/igmp.c +F: net/ipv4/inet_fragment.c +F: net/ipv4/inetpeer.c +F: net/ipv4/ip* +F: net/ipv4/metrics.c +F: net/ipv4/netlink.c +F: net/ipv4/nexthop.c +F: net/ipv4/route.c +F: net/ipv6/addr* +F: net/ipv6/anycast.c +F: net/ipv6/exthdrs.c +F: net/ipv6/exthdrs_core.c +F: net/ipv6/fib* +F: net/ipv6/icmp.c +F: net/ipv6/ip* +F: net/ipv6/mcast* +F: net/ipv6/ndisc.c +F: net/ipv6/output_core.c +F: net/ipv6/reassembly.c +F: net/ipv6/route.c +F: tools/testing/selftests/net/fib* +F: tools/testing/selftests/net/forwarding/ NETWORKING [LABELED] (NetLabel, Labeled IPsec, SECMARK) M: Paul Moore @@ -18828,18 +18868,11 @@ F: Documentation/networking/net_failover.rst F: drivers/net/net_failover.c F: include/net/net_failover.h -NEXTHOP -M: David Ahern -L: netdev@vger.kernel.org -S: Maintained -F: include/net/netns/nexthop.h -F: include/net/nexthop.h -F: include/uapi/linux/nexthop.h -F: net/ipv4/nexthop.c - NFC SUBSYSTEM -L: netdev@vger.kernel.org -S: Orphan +M: David Heidelberg +L: oe-linux-nfc@lists.linux.dev +S: Maintained +T: git https://codeberg.org/linux-nfc/linux.git F: Documentation/devicetree/bindings/net/nfc/ F: drivers/nfc/ F: include/net/nfc/ @@ -20783,6 +20816,7 @@ M: Dominik Brodowski S: Odd Fixes T: git git://git.kernel.org/pub/scm/linux/kernel/git/brodo/linux.git F: Documentation/pcmcia/ +F: drivers/net/ethernet/8390/pcnet_cs.c F: drivers/pcmcia/ F: include/pcmcia/ F: tools/pcmcia/ @@ -23378,7 +23412,7 @@ RUST [ALLOC] M: Danilo Krummrich R: Lorenzo Stoakes R: Vlastimil Babka -R: Liam R. Howlett +R: Liam R. Howlett R: Uladzislau Rezki L: rust-for-linux@vger.kernel.org S: Maintained @@ -23530,7 +23564,7 @@ F: drivers/s390/net/ S390 PCI SUBSYSTEM M: Niklas Schnelle -M: Gerald Schaefer +M: Gerd Bayer L: linux-s390@vger.kernel.org S: Supported F: Documentation/arch/s390/pci.rst @@ -24323,7 +24357,7 @@ F: include/media/i2c/rj54n1cb0c.h SHRINKER M: Andrew Morton M: Dave Chinner -R: Qi Zheng +R: Qi Zheng R: Roman Gushchin R: Muchun Song L: linux-mm@kvack.org @@ -24773,6 +24807,7 @@ SOFTWARE RAID (Multiple Disks) SUPPORT M: Song Liu M: Yu Kuai R: Li Nan +R: Xiao Ni L: linux-raid@vger.kernel.org S: Supported Q: https://patchwork.kernel.org/project/linux-raid/list/ diff --git a/Makefile b/Makefile index e27c91ea56fc..9f88dcaae382 100644 --- a/Makefile +++ b/Makefile @@ -2,7 +2,7 @@ VERSION = 7 PATCHLEVEL = 1 SUBLEVEL = 0 -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc2 NAME = Baby Opossum Posse # *DOCUMENTATION* diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h index d4d7451c2c12..a8cb5a5c93b7 100644 --- a/arch/arm64/include/asm/irqflags.h +++ b/arch/arm64/include/asm/irqflags.h @@ -40,7 +40,7 @@ static __always_inline void __pmr_local_irq_enable(void) barrier(); } -static inline void arch_local_irq_enable(void) +static __always_inline void arch_local_irq_enable(void) { if (system_uses_irq_prio_masking()) { __pmr_local_irq_enable(); @@ -68,7 +68,7 @@ static __always_inline void __pmr_local_irq_disable(void) barrier(); } -static inline void arch_local_irq_disable(void) +static __always_inline void arch_local_irq_disable(void) { if (system_uses_irq_prio_masking()) { __pmr_local_irq_disable(); @@ -90,7 +90,7 @@ static __always_inline unsigned long __pmr_local_save_flags(void) /* * Save the current interrupt enable state. */ -static inline unsigned long arch_local_save_flags(void) +static __always_inline unsigned long arch_local_save_flags(void) { if (system_uses_irq_prio_masking()) { return __pmr_local_save_flags(); @@ -109,7 +109,7 @@ static __always_inline bool __pmr_irqs_disabled_flags(unsigned long flags) return flags != GIC_PRIO_IRQON; } -static inline bool arch_irqs_disabled_flags(unsigned long flags) +static __always_inline bool arch_irqs_disabled_flags(unsigned long flags) { if (system_uses_irq_prio_masking()) { return __pmr_irqs_disabled_flags(flags); @@ -128,7 +128,7 @@ static __always_inline bool __pmr_irqs_disabled(void) return __pmr_irqs_disabled_flags(__pmr_local_save_flags()); } -static inline bool arch_irqs_disabled(void) +static __always_inline bool arch_irqs_disabled(void) { if (system_uses_irq_prio_masking()) { return __pmr_irqs_disabled(); @@ -160,7 +160,7 @@ static __always_inline unsigned long __pmr_local_irq_save(void) return flags; } -static inline unsigned long arch_local_irq_save(void) +static __always_inline unsigned long arch_local_irq_save(void) { if (system_uses_irq_prio_masking()) { return __pmr_local_irq_save(); @@ -187,7 +187,7 @@ static __always_inline void __pmr_local_irq_restore(unsigned long flags) /* * restore saved IRQ state */ -static inline void arch_local_irq_restore(unsigned long flags) +static __always_inline void arch_local_irq_restore(unsigned long flags) { if (system_uses_irq_prio_masking()) { __pmr_local_irq_restore(flags); diff --git a/arch/arm64/include/asm/kernel-pgtable.h b/arch/arm64/include/asm/kernel-pgtable.h index 74a4f738c5f5..229ee7976f69 100644 --- a/arch/arm64/include/asm/kernel-pgtable.h +++ b/arch/arm64/include/asm/kernel-pgtable.h @@ -68,7 +68,12 @@ #define KERNEL_SEGMENT_COUNT 5 #if SWAPPER_BLOCK_SIZE > SEGMENT_ALIGN -#define EARLY_SEGMENT_EXTRA_PAGES (KERNEL_SEGMENT_COUNT + 1) +/* + * KERNEL_SEGMENT_COUNT counts the permanent kernel VMAs. The early mapping + * has one additional split, [_text, _stext). Reserve one more page for the + * SWAPPER_BLOCK_SIZE-unaligned boundaries. + */ +#define EARLY_SEGMENT_EXTRA_PAGES (KERNEL_SEGMENT_COUNT + 2) /* * The initial ID map consists of the kernel image, mapped as two separate * segments, and may appear misaligned wrt the swapper block size. This means diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h index 37414440cee7..043495f7fc78 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -50,6 +50,9 @@ #include +#define MARKER(m) \ + m, __after_##m = m - 1 + enum __kvm_host_smccc_func { /* Hypercalls that are unavailable once pKVM has finalised. */ /* __KVM_HOST_SMCCC_FUNC___kvm_hyp_init */ @@ -59,8 +62,10 @@ enum __kvm_host_smccc_func { __KVM_HOST_SMCCC_FUNC___kvm_enable_ssbs, __KVM_HOST_SMCCC_FUNC___vgic_v3_init_lrs, __KVM_HOST_SMCCC_FUNC___vgic_v3_get_gic_config, + + MARKER(__KVM_HOST_SMCCC_FUNC_MIN_PKVM), + __KVM_HOST_SMCCC_FUNC___pkvm_prot_finalize, - __KVM_HOST_SMCCC_FUNC_MIN_PKVM = __KVM_HOST_SMCCC_FUNC___pkvm_prot_finalize, /* Hypercalls that are always available and common to [nh]VHE/pKVM. */ __KVM_HOST_SMCCC_FUNC___kvm_adjust_pc, @@ -72,11 +77,20 @@ enum __kvm_host_smccc_func { __KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid_range, __KVM_HOST_SMCCC_FUNC___kvm_flush_cpu_context, __KVM_HOST_SMCCC_FUNC___kvm_timer_set_cntvoff, + __KVM_HOST_SMCCC_FUNC___tracing_load, + __KVM_HOST_SMCCC_FUNC___tracing_unload, + __KVM_HOST_SMCCC_FUNC___tracing_enable, + __KVM_HOST_SMCCC_FUNC___tracing_swap_reader, + __KVM_HOST_SMCCC_FUNC___tracing_update_clock, + __KVM_HOST_SMCCC_FUNC___tracing_reset, + __KVM_HOST_SMCCC_FUNC___tracing_enable_event, + __KVM_HOST_SMCCC_FUNC___tracing_write_event, __KVM_HOST_SMCCC_FUNC___vgic_v3_save_aprs, __KVM_HOST_SMCCC_FUNC___vgic_v3_restore_vmcr_aprs, __KVM_HOST_SMCCC_FUNC___vgic_v5_save_apr, __KVM_HOST_SMCCC_FUNC___vgic_v5_restore_vmcr_apr, - __KVM_HOST_SMCCC_FUNC_MAX_NO_PKVM = __KVM_HOST_SMCCC_FUNC___vgic_v5_restore_vmcr_apr, + + MARKER(__KVM_HOST_SMCCC_FUNC_PKVM_ONLY), /* Hypercalls that are available only when pKVM has finalised. */ __KVM_HOST_SMCCC_FUNC___pkvm_host_share_hyp, @@ -100,14 +114,8 @@ enum __kvm_host_smccc_func { __KVM_HOST_SMCCC_FUNC___pkvm_vcpu_load, __KVM_HOST_SMCCC_FUNC___pkvm_vcpu_put, __KVM_HOST_SMCCC_FUNC___pkvm_tlb_flush_vmid, - __KVM_HOST_SMCCC_FUNC___tracing_load, - __KVM_HOST_SMCCC_FUNC___tracing_unload, - __KVM_HOST_SMCCC_FUNC___tracing_enable, - __KVM_HOST_SMCCC_FUNC___tracing_swap_reader, - __KVM_HOST_SMCCC_FUNC___tracing_update_clock, - __KVM_HOST_SMCCC_FUNC___tracing_reset, - __KVM_HOST_SMCCC_FUNC___tracing_enable_event, - __KVM_HOST_SMCCC_FUNC___tracing_write_event, + + MARKER(__KVM_HOST_SMCCC_FUNC_MAX) }; #define DECLARE_KVM_VHE_SYM(sym) extern char sym[] diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 851f6171751c..65eead8362e0 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -450,9 +450,6 @@ struct kvm_vcpu_fault_info { r = __VNCR_START__ + ((VNCR_ ## r) / 8), \ __after_##r = __MAX__(__before_##r - 1, r) -#define MARKER(m) \ - m, __after_##m = m - 1 - enum vcpu_sysreg { __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ MPIDR_EL1, /* MultiProcessor Affinity Register */ @@ -1548,7 +1545,7 @@ static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature) #define kvm_vcpu_has_feature(k, f) __vcpu_has_feature(&(k)->arch, (f)) #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f)) -#define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED) +#define kvm_vcpu_initialized(v) vcpu_get_flag(v, VCPU_INITIALIZED) int kvm_trng_call(struct kvm_vcpu *vcpu); #ifdef CONFIG_KVM diff --git a/arch/arm64/kernel/pi/patch-scs.c b/arch/arm64/kernel/pi/patch-scs.c index dac568e4a54f..3944ad899021 100644 --- a/arch/arm64/kernel/pi/patch-scs.c +++ b/arch/arm64/kernel/pi/patch-scs.c @@ -196,9 +196,9 @@ static int scs_handle_fde_frame(const struct eh_frame *frame, loc += *opcode++ * code_alignment_factor; loc += (*opcode++ << 8) * code_alignment_factor; loc += (*opcode++ << 16) * code_alignment_factor; - loc += (*opcode++ << 24) * code_alignment_factor; + loc += ((u64)*opcode++ << 24) * code_alignment_factor; size -= 4; - break; + break; case DW_CFA_def_cfa: case DW_CFA_offset_extended: diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index 08ffc5a5aea4..38e6fa204c17 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -67,6 +67,9 @@ struct rt_sigframe_user_layout { unsigned long end_offset; }; +#define TERMINATOR_SIZE round_up(sizeof(struct _aarch64_ctx), 16) +#define EXTRA_CONTEXT_SIZE round_up(sizeof(struct extra_context), 16) + /* * Holds any EL0-controlled state that influences unprivileged memory accesses. * This includes both accesses done in userspace and uaccess done in the kernel. @@ -74,13 +77,35 @@ struct rt_sigframe_user_layout { * This state needs to be carefully managed to ensure that it doesn't cause * uaccess to fail when setting up the signal frame, and the signal handler * itself also expects a well-defined state when entered. + * + * The struct should be zero-initialised. Its members should only be accessed + * via the accessors below. __valid_fields tracks which of the fields are valid + * (have been set to some value). */ struct user_access_state { - u64 por_el0; + unsigned int __valid_fields; + u64 __por_el0; }; -#define TERMINATOR_SIZE round_up(sizeof(struct _aarch64_ctx), 16) -#define EXTRA_CONTEXT_SIZE round_up(sizeof(struct extra_context), 16) +#define UA_STATE_HAS_POR_EL0 BIT(0) + +static void set_ua_state_por_el0(struct user_access_state *ua_state, + u64 por_el0) +{ + ua_state->__por_el0 = por_el0; + ua_state->__valid_fields |= UA_STATE_HAS_POR_EL0; +} + +static int get_ua_state_por_el0(const struct user_access_state *ua_state, + u64 *por_el0) +{ + if (ua_state->__valid_fields & UA_STATE_HAS_POR_EL0) { + *por_el0 = ua_state->__por_el0; + return 0; + } + + return -ENOENT; +} /* * Save the user access state into ua_state and reset it to disable any @@ -94,7 +119,7 @@ static void save_reset_user_access_state(struct user_access_state *ua_state) for (int pkey = 0; pkey < arch_max_pkey(); pkey++) por_enable_all |= POR_ELx_PERM_PREP(pkey, POE_RWX); - ua_state->por_el0 = read_sysreg_s(SYS_POR_EL0); + set_ua_state_por_el0(ua_state, read_sysreg_s(SYS_POR_EL0)); write_sysreg_s(por_enable_all, SYS_POR_EL0); /* * No ISB required as we can tolerate spurious Overlay faults - @@ -122,8 +147,10 @@ static void set_handler_user_access_state(void) */ static void restore_user_access_state(const struct user_access_state *ua_state) { - if (system_supports_poe()) - write_sysreg_s(ua_state->por_el0, SYS_POR_EL0); + u64 por_el0; + + if (get_ua_state_por_el0(ua_state, &por_el0) == 0) + write_sysreg_s(por_el0, SYS_POR_EL0); } static void init_user_layout(struct rt_sigframe_user_layout *user) @@ -333,11 +360,16 @@ static int restore_fpmr_context(struct user_ctxs *user) static int preserve_poe_context(struct poe_context __user *ctx, const struct user_access_state *ua_state) { - int err = 0; + int err; + u64 por_el0; + + err = get_ua_state_por_el0(ua_state, &por_el0); + if (WARN_ON_ONCE(err)) + return err; __put_user_error(POE_MAGIC, &ctx->head.magic, err); __put_user_error(sizeof(*ctx), &ctx->head.size, err); - __put_user_error(ua_state->por_el0, &ctx->por_el0, err); + __put_user_error(por_el0, &ctx->por_el0, err); return err; } @@ -353,7 +385,7 @@ static int restore_poe_context(struct user_ctxs *user, __get_user_error(por_el0, &(user->poe->por_el0), err); if (!err) - ua_state->por_el0 = por_el0; + set_ua_state_por_el0(ua_state, por_el0); return err; } @@ -1095,7 +1127,7 @@ SYSCALL_DEFINE0(rt_sigreturn) { struct pt_regs *regs = current_pt_regs(); struct rt_sigframe __user *frame; - struct user_access_state ua_state; + struct user_access_state ua_state = {}; /* Always make any pending restarted system calls return -EINTR */ current->restart_block.fn = do_no_restart_syscall; @@ -1507,7 +1539,7 @@ static int setup_rt_frame(int usig, struct ksignal *ksig, sigset_t *set, { struct rt_sigframe_user_layout user; struct rt_sigframe __user *frame; - struct user_access_state ua_state; + struct user_access_state ua_state = {}; int err = 0; fpsimd_save_and_flush_current_state(); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 176cbe8baad3..8bb2c7422cc8 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -824,6 +824,10 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *v) { bool irq_lines = *vcpu_hcr(v) & (HCR_VI | HCR_VF | HCR_VSE); + irq_lines |= (!irqchip_in_kernel(v->kvm) && + (kvm_timer_should_notify_user(v) || + kvm_pmu_should_notify_user(v))); + return ((irq_lines || kvm_vgic_vcpu_pending_irq(v)) && !kvm_arm_vcpu_stopped(v) && !v->arch.pause); } diff --git a/arch/arm64/kvm/config.c b/arch/arm64/kvm/config.c index f35b8dddd7c1..0622162b089e 100644 --- a/arch/arm64/kvm/config.c +++ b/arch/arm64/kvm/config.c @@ -131,7 +131,6 @@ struct reg_feat_map_desc { } #define FEAT_SPE ID_AA64DFR0_EL1, PMSVer, IMP -#define FEAT_SPE_FnE ID_AA64DFR0_EL1, PMSVer, V1P2 #define FEAT_BRBE ID_AA64DFR0_EL1, BRBE, IMP #define FEAT_TRC_SR ID_AA64DFR0_EL1, TraceVer, IMP #define FEAT_PMUv3 ID_AA64DFR0_EL1, PMUVer, IMP @@ -192,7 +191,7 @@ struct reg_feat_map_desc { #define FEAT_SRMASK ID_AA64MMFR4_EL1, SRMASK, IMP #define FEAT_PoPS ID_AA64MMFR4_EL1, PoPS, IMP #define FEAT_PFAR ID_AA64PFR1_EL1, PFAR, IMP -#define FEAT_Debugv8p9 ID_AA64DFR0_EL1, PMUVer, V3P9 +#define FEAT_Debugv8p9 ID_AA64DFR0_EL1, DebugVer, V8P9 #define FEAT_PMUv3_SS ID_AA64DFR0_EL1, PMSS, IMP #define FEAT_SEBEP ID_AA64DFR0_EL1, SEBEP, IMP #define FEAT_EBEP ID_AA64DFR1_EL1, EBEP, IMP @@ -283,7 +282,7 @@ static bool feat_anerr(struct kvm *kvm) static bool feat_sme_smps(struct kvm *kvm) { /* - * Revists this if KVM ever supports SME -- this really should + * Revisit this if KVM ever supports SME -- this really should * look at the guest's view of SMIDR_EL1. Funnily enough, this * is not captured in the JSON file, but only as a note in the * ARM ARM. @@ -295,17 +294,27 @@ static bool feat_sme_smps(struct kvm *kvm) static bool feat_spe_fds(struct kvm *kvm) { /* - * Revists this if KVM ever supports SPE -- this really should + * Revisit this if KVM ever supports SPE -- this really should * look at the guest's view of PMSIDR_EL1. */ return (kvm_has_feat(kvm, FEAT_SPEv1p4) && (read_sysreg_s(SYS_PMSIDR_EL1) & PMSIDR_EL1_FDS)); } +static bool feat_spe_fne(struct kvm *kvm) +{ + /* + * Revisit this if KVM ever supports SPE -- this really should + * look at the guest's view of PMSIDR_EL1. + */ + return (kvm_has_feat(kvm, FEAT_SPEv1p2) && + (read_sysreg_s(SYS_PMSIDR_EL1) & PMSIDR_EL1_FnE)); +} + static bool feat_trbe_mpam(struct kvm *kvm) { /* - * Revists this if KVM ever supports both MPAM and TRBE -- + * Revisit this if KVM ever supports both MPAM and TRBE -- * this really should look at the guest's view of TRBIDR_EL1. */ return (kvm_has_feat(kvm, FEAT_TRBE) && @@ -537,7 +546,7 @@ static const struct reg_bits_to_feat_map hdfgrtr_feat_map[] = { HDFGRTR_EL2_PMBPTR_EL1 | HDFGRTR_EL2_PMBLIMITR_EL1, FEAT_SPE), - NEEDS_FEAT(HDFGRTR_EL2_nPMSNEVFR_EL1, FEAT_SPE_FnE), + NEEDS_FEAT(HDFGRTR_EL2_nPMSNEVFR_EL1, feat_spe_fne), NEEDS_FEAT(HDFGRTR_EL2_nBRBDATA | HDFGRTR_EL2_nBRBCTL | HDFGRTR_EL2_nBRBIDR, @@ -605,7 +614,7 @@ static const struct reg_bits_to_feat_map hdfgwtr_feat_map[] = { HDFGWTR_EL2_PMBPTR_EL1 | HDFGWTR_EL2_PMBLIMITR_EL1, FEAT_SPE), - NEEDS_FEAT(HDFGWTR_EL2_nPMSNEVFR_EL1, FEAT_SPE_FnE), + NEEDS_FEAT(HDFGWTR_EL2_nPMSNEVFR_EL1, feat_spe_fne), NEEDS_FEAT(HDFGWTR_EL2_nBRBDATA | HDFGWTR_EL2_nBRBCTL, FEAT_BRBE), diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c index 73f2e0221e70..06db299c37a8 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -709,6 +709,14 @@ static const hcall_t host_hcall[] = { HANDLE_FUNC(__kvm_tlb_flush_vmid_range), HANDLE_FUNC(__kvm_flush_cpu_context), HANDLE_FUNC(__kvm_timer_set_cntvoff), + HANDLE_FUNC(__tracing_load), + HANDLE_FUNC(__tracing_unload), + HANDLE_FUNC(__tracing_enable), + HANDLE_FUNC(__tracing_swap_reader), + HANDLE_FUNC(__tracing_update_clock), + HANDLE_FUNC(__tracing_reset), + HANDLE_FUNC(__tracing_enable_event), + HANDLE_FUNC(__tracing_write_event), HANDLE_FUNC(__vgic_v3_save_aprs), HANDLE_FUNC(__vgic_v3_restore_vmcr_aprs), HANDLE_FUNC(__vgic_v5_save_apr), @@ -735,22 +743,16 @@ static const hcall_t host_hcall[] = { HANDLE_FUNC(__pkvm_vcpu_load), HANDLE_FUNC(__pkvm_vcpu_put), HANDLE_FUNC(__pkvm_tlb_flush_vmid), - HANDLE_FUNC(__tracing_load), - HANDLE_FUNC(__tracing_unload), - HANDLE_FUNC(__tracing_enable), - HANDLE_FUNC(__tracing_swap_reader), - HANDLE_FUNC(__tracing_update_clock), - HANDLE_FUNC(__tracing_reset), - HANDLE_FUNC(__tracing_enable_event), - HANDLE_FUNC(__tracing_write_event), }; static void handle_host_hcall(struct kvm_cpu_context *host_ctxt) { DECLARE_REG(unsigned long, id, host_ctxt, 0); - unsigned long hcall_min = 0, hcall_max = -1; + unsigned long hcall_min = 0, hcall_max = __KVM_HOST_SMCCC_FUNC_MAX; hcall_t hfn; + BUILD_BUG_ON(ARRAY_SIZE(host_hcall) != __KVM_HOST_SMCCC_FUNC_MAX); + /* * If pKVM has been initialised then reject any calls to the * early "privileged" hypercalls. Note that we cannot reject @@ -763,16 +765,14 @@ static void handle_host_hcall(struct kvm_cpu_context *host_ctxt) if (static_branch_unlikely(&kvm_protected_mode_initialized)) { hcall_min = __KVM_HOST_SMCCC_FUNC_MIN_PKVM; } else { - hcall_max = __KVM_HOST_SMCCC_FUNC_MAX_NO_PKVM; + hcall_max = __KVM_HOST_SMCCC_FUNC_PKVM_ONLY; } id &= ~ARM_SMCCC_CALL_HINTS; id -= KVM_HOST_SMCCC_ID(0); - if (unlikely(id < hcall_min || id > hcall_max || - id >= ARRAY_SIZE(host_hcall))) { + if (unlikely(id < hcall_min || id >= hcall_max)) goto inval; - } hfn = host_hcall[id]; if (unlikely(!hfn)) @@ -805,6 +805,10 @@ static void handle_host_smc(struct kvm_cpu_context *host_ctxt) } func_id &= ~ARM_SMCCC_CALL_HINTS; + if (upper_32_bits(func_id)) { + cpu_reg(host_ctxt, 0) = SMCCC_RET_NOT_SUPPORTED; + goto exit_skip_instr; + } handled = kvm_host_psci_handler(host_ctxt, func_id); if (!handled) diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index 7ed96d64d611..e7496eb85628 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -266,7 +266,8 @@ struct pkvm_hyp_vcpu *pkvm_load_hyp_vcpu(pkvm_handle_t handle, if (hyp_vm->kvm.created_vcpus <= vcpu_idx) goto unlock; - hyp_vcpu = hyp_vm->vcpus[vcpu_idx]; + /* Pairs with smp_store_release() in register_hyp_vcpu(). */ + hyp_vcpu = smp_load_acquire(&hyp_vm->vcpus[vcpu_idx]); if (!hyp_vcpu) goto unlock; @@ -860,12 +861,30 @@ int __pkvm_init_vm(struct kvm *host_kvm, unsigned long vm_hva, * the page-aligned size of 'struct pkvm_hyp_vcpu'. * Return 0 on success, negative error code on failure. */ +static int register_hyp_vcpu(struct pkvm_hyp_vm *hyp_vm, + struct pkvm_hyp_vcpu *hyp_vcpu) +{ + unsigned int idx = hyp_vcpu->vcpu.vcpu_idx; + + if (idx >= hyp_vm->kvm.created_vcpus) + return -EINVAL; + + if (hyp_vm->vcpus[idx]) + return -EINVAL; + + /* + * Ensure the hyp_vcpu is initialised before publishing it to + * the vCPU-load path via 'hyp_vm->vcpus[]'. + */ + smp_store_release(&hyp_vm->vcpus[idx], hyp_vcpu); + return 0; +} + int __pkvm_init_vcpu(pkvm_handle_t handle, struct kvm_vcpu *host_vcpu, unsigned long vcpu_hva) { struct pkvm_hyp_vcpu *hyp_vcpu; struct pkvm_hyp_vm *hyp_vm; - unsigned int idx; int ret; hyp_vcpu = map_donated_memory(vcpu_hva, sizeof(*hyp_vcpu)); @@ -884,18 +903,11 @@ int __pkvm_init_vcpu(pkvm_handle_t handle, struct kvm_vcpu *host_vcpu, if (ret) goto unlock; - idx = hyp_vcpu->vcpu.vcpu_idx; - if (idx >= hyp_vm->kvm.created_vcpus) { - ret = -EINVAL; - goto unlock; + ret = register_hyp_vcpu(hyp_vm, hyp_vcpu); + if (ret) { + unpin_host_vcpu(host_vcpu); + unpin_host_sve_state(hyp_vcpu); } - - if (hyp_vm->vcpus[idx]) { - ret = -EINVAL; - goto unlock; - } - - hyp_vm->vcpus[idx] = hyp_vcpu; unlock: hyp_spin_unlock(&vm_table_lock); diff --git a/arch/arm64/kvm/hyp/nvhe/setup.c b/arch/arm64/kvm/hyp/nvhe/setup.c index d8e5b563fd3d..d461981616d9 100644 --- a/arch/arm64/kvm/hyp/nvhe/setup.c +++ b/arch/arm64/kvm/hyp/nvhe/setup.c @@ -312,10 +312,6 @@ void __noreturn __pkvm_init_finalise(void) }; pkvm_pgtable.mm_ops = &pkvm_pgtable_mm_ops; - ret = fix_host_ownership(); - if (ret) - goto out; - ret = fix_hyp_pgtable_refcnt(); if (ret) goto out; @@ -324,6 +320,10 @@ void __noreturn __pkvm_init_finalise(void) if (ret) goto out; + ret = fix_host_ownership(); + if (ret) + goto out; + ret = hyp_ffa_init(ffa_proxy_pages); if (ret) goto out; diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v2.c b/arch/arm64/kvm/vgic/vgic-mmio-v2.c index 406845b3117c..0643e333db35 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v2.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v2.c @@ -91,7 +91,7 @@ static int vgic_mmio_uaccess_write_v2_misc(struct kvm_vcpu *vcpu, * migration from old kernels to new kernels with legacy * userspace. */ - reg = FIELD_GET(GICD_IIDR_REVISION_MASK, reg); + reg = FIELD_GET(GICD_IIDR_REVISION_MASK, val); switch (reg) { case KVM_VGIC_IMP_REV_2: case KVM_VGIC_IMP_REV_3: diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c index 89edb84d1ac6..5913a20d8301 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c @@ -194,7 +194,7 @@ static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu, if ((reg ^ val) & ~GICD_IIDR_REVISION_MASK) return -EINVAL; - reg = FIELD_GET(GICD_IIDR_REVISION_MASK, reg); + reg = FIELD_GET(GICD_IIDR_REVISION_MASK, val); switch (reg) { case KVM_VGIC_IMP_REV_2: case KVM_VGIC_IMP_REV_3: diff --git a/arch/s390/kernel/debug.c b/arch/s390/kernel/debug.c index 31430e9bcfdd..7650f2adb5cf 100644 --- a/arch/s390/kernel/debug.c +++ b/arch/s390/kernel/debug.c @@ -1414,6 +1414,9 @@ static inline char *debug_get_user_string(const char __user *user_buf, { char *buffer; + if (!user_len) + return ERR_PTR(-EINVAL); + buffer = memdup_user_nul(user_buf, user_len); if (IS_ERR(buffer)) return buffer; @@ -1584,6 +1587,11 @@ static int debug_input_flush_fn(debug_info_t *id, struct debug_view *view, char input_buf[1]; int rc = user_len; + if (!user_len) { + rc = -EINVAL; + goto out; + } + if (user_len > 0x10000) user_len = 0x10000; if (*offset != 0) { diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c index 191cc53caead..028aeb9c48d6 100644 --- a/arch/s390/mm/fault.c +++ b/arch/s390/mm/fault.c @@ -438,7 +438,7 @@ void do_secure_storage_access(struct pt_regs *regs) panic("Unexpected PGM 0x3d with TEID bit 61=0"); } if (is_kernel_fault(regs)) { - folio = phys_to_folio(addr); + folio = virt_to_folio((void *)addr); if (unlikely(!folio_try_get(folio))) return; rc = uv_convert_from_secure(folio_to_phys(folio)); diff --git a/arch/sh/include/asm/setup.h b/arch/sh/include/asm/setup.h index 63c9efc06348..8488f76b48b4 100644 --- a/arch/sh/include/asm/setup.h +++ b/arch/sh/include/asm/setup.h @@ -7,7 +7,7 @@ /* * This is set up by the setup-routine at boot-time */ -extern unsigned char *boot_params_page; +extern unsigned char boot_params_page[]; #define PARAM boot_params_page #define MOUNT_ROOT_RDONLY (*(unsigned long *) (PARAM+0x000)) diff --git a/crypto/authencesn.c b/crypto/authencesn.c index af3d584e584f..522df41365d8 100644 --- a/crypto/authencesn.c +++ b/crypto/authencesn.c @@ -390,6 +390,11 @@ static int crypto_authenc_esn_create(struct crypto_template *tmpl, auth = crypto_spawn_ahash_alg(&ctx->auth); auth_base = &auth->base; + if (auth->digestsize > 0 && auth->digestsize < 4) { + err = -EINVAL; + goto err_free_inst; + } + err = crypto_grab_skcipher(&ctx->enc, aead_crypto_instance(inst), crypto_attr_alg_name(tb[2]), 0, mask); if (err) diff --git a/drivers/acpi/acpi_tad.c b/drivers/acpi/acpi_tad.c index b406d7a98996..cac07e997028 100644 --- a/drivers/acpi/acpi_tad.c +++ b/drivers/acpi/acpi_tad.c @@ -605,15 +605,12 @@ static umode_t acpi_tad_attr_is_visible(struct kobject *kobj, return 0; } -static const struct attribute_group acpi_tad_attr_group = { +static const struct attribute_group acpi_tad_group = { .attrs = acpi_tad_attrs, .is_visible = acpi_tad_attr_is_visible, }; -static const struct attribute_group *acpi_tad_attr_groups[] = { - &acpi_tad_attr_group, - NULL, -}; +__ATTRIBUTE_GROUPS(acpi_tad); #ifdef CONFIG_RTC_CLASS /* RTC class device interface */ @@ -683,9 +680,8 @@ static int acpi_tad_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t) acpi_tad_rt_to_tm(&rt, &tm_now); - value = ktime_divns(ktime_sub(rtc_tm_to_ktime(t->time), - rtc_tm_to_ktime(tm_now)), NSEC_PER_SEC); - if (value <= 0 || value > U32_MAX) + value = rtc_tm_to_time64(&t->time) - rtc_tm_to_time64(&tm_now); + if (value <= 0 || value >= U32_MAX) return -EINVAL; } @@ -748,8 +744,7 @@ static int acpi_tad_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *t) if (retval != ACPI_TAD_WAKE_DISABLED) { t->enabled = 1; - t->time = rtc_ktime_to_tm(ktime_add_ns(rtc_tm_to_ktime(tm_now), - (u64)retval * NSEC_PER_SEC)); + rtc_time64_to_tm(rtc_tm_to_time64(&tm_now) + retval, &t->time); } else { t->enabled = 0; t->time = tm_now; @@ -795,9 +790,9 @@ static int acpi_tad_disable_timer(struct device *dev, u32 timer_id) return acpi_tad_wake_set(dev, "_STV", timer_id, ACPI_TAD_WAKE_DISABLED); } -static void acpi_tad_remove(struct platform_device *pdev) +static void acpi_tad_remove(void *data) { - struct device *dev = &pdev->dev; + struct device *dev = data; struct acpi_tad_driver_data *dd = dev_get_drvdata(dev); device_init_wakeup(dev, false); @@ -824,6 +819,7 @@ static int acpi_tad_probe(struct platform_device *pdev) struct acpi_tad_driver_data *dd; acpi_status status; unsigned long long caps; + int ret; /* * Initialization failure messages are mostly about firmware issues, so @@ -863,13 +859,21 @@ static int acpi_tad_probe(struct platform_device *pdev) } /* - * The platform bus type layer tells the ACPI PM domain powers up the - * device, so set the runtime PM status of it to "active". + * The platform bus type probe callback tells the ACPI PM domain to + * power up the device, so set the runtime PM status of it to "active". */ pm_runtime_set_active(dev); pm_runtime_enable(dev); pm_runtime_suspend(dev); + /* + * acpi_tad_remove() needs to run after unregistering the RTC class + * device to avoid racing with the latter's callbacks. + */ + ret = devm_add_action_or_reset(&pdev->dev, acpi_tad_remove, &pdev->dev); + if (ret) + return ret; + if (caps & ACPI_TAD_RT) acpi_tad_register_rtc(dev, caps); @@ -885,10 +889,9 @@ static struct platform_driver acpi_tad_driver = { .driver = { .name = "acpi-tad", .acpi_match_table = acpi_tad_ids, - .dev_groups = acpi_tad_attr_groups, + .dev_groups = acpi_tad_groups, }, .probe = acpi_tad_probe, - .remove = acpi_tad_remove, }; MODULE_DEVICE_TABLE(acpi, acpi_tad_ids); diff --git a/drivers/acpi/apei/einj-core.c b/drivers/acpi/apei/einj-core.c index a9248af078f6..1f3fa2278584 100644 --- a/drivers/acpi/apei/einj-core.c +++ b/drivers/acpi/apei/einj-core.c @@ -401,8 +401,18 @@ static struct acpi_generic_address *einj_get_trigger_parameter_region( return NULL; } + +static bool is_memory_injection(u32 type, u32 flags) +{ + if (flags & SETWA_FLAGS_EINJV2) + return !!(type & ACPI_EINJV2_MEMORY); + if (type & ACPI5_VENDOR_BIT) + return !!(vendor_flags & SETWA_FLAGS_MEM); + return !!(type & MEM_ERROR_MASK) || !!(flags & SETWA_FLAGS_MEM); +} + /* Execute instructions in trigger error action table */ -static int __einj_error_trigger(u64 trigger_paddr, u32 type, +static int __einj_error_trigger(u64 trigger_paddr, u32 type, u32 flags, u64 param1, u64 param2) { struct acpi_einj_trigger trigger_tab; @@ -480,7 +490,7 @@ static int __einj_error_trigger(u64 trigger_paddr, u32 type, * This will cause resource conflict with regular memory. So * remove it from trigger table resources. */ - if ((param_extension || acpi5) && (type & MEM_ERROR_MASK) && param2) { + if ((param_extension || acpi5) && is_memory_injection(type, flags)) { struct apei_resources addr_resources; apei_resources_init(&addr_resources); @@ -660,7 +670,7 @@ static int __einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, return rc; trigger_paddr = apei_exec_ctx_get_output(&ctx); if (notrigger == 0) { - rc = __einj_error_trigger(trigger_paddr, type, param1, param2); + rc = __einj_error_trigger(trigger_paddr, type, flags, param1, param2); if (rc) return rc; } @@ -718,28 +728,6 @@ int einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, u64 param3, SETWA_FLAGS_PCIE_SBDF | SETWA_FLAGS_EINJV2))) return -EINVAL; - /* check if type is a valid EINJv2 error type */ - if (is_v2) { - if (!(type & available_error_type_v2)) - return -EINVAL; - } - /* - * We need extra sanity checks for memory errors. - * Other types leap directly to injection. - */ - - /* ensure param1/param2 existed */ - if (!(param_extension || acpi5)) - goto inject; - - /* ensure injection is memory related */ - if (type & ACPI5_VENDOR_BIT) { - if (vendor_flags != SETWA_FLAGS_MEM) - goto inject; - } else if (!(type & MEM_ERROR_MASK) && !(flags & SETWA_FLAGS_MEM)) { - goto inject; - } - /* * Injections targeting a CXL 1.0/1.1 port have to be injected * via the einj_cxl_rch_error_inject() path as that does the proper @@ -748,6 +736,23 @@ int einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, u64 param3, if (einj_is_cxl_error_type(type) && (flags & SETWA_FLAGS_MEM)) return -EINVAL; + /* check if type is a valid EINJv2 error type */ + if (is_v2) { + if (!(type & available_error_type_v2)) + return -EINVAL; + } + + /* ensure param1/param2 existed */ + if (!(param_extension || acpi5)) + goto inject; + + /* + * We need extra sanity checks for memory errors. + * Other types leap directly to injection. + */ + if (!is_memory_injection(type, flags)) + goto inject; + /* * Disallow crazy address masks that give BIOS leeway to pick * injection address almost anywhere. Insist on page or diff --git a/drivers/acpi/arm64/cpuidle.c b/drivers/acpi/arm64/cpuidle.c index 801f9c450142..c68a5db8ebba 100644 --- a/drivers/acpi/arm64/cpuidle.c +++ b/drivers/acpi/arm64/cpuidle.c @@ -16,7 +16,7 @@ static int psci_acpi_cpu_init_idle(unsigned int cpu) { - int i, count; + int i; struct acpi_lpi_state *lpi; struct acpi_processor *pr = per_cpu(processors, cpu); @@ -30,14 +30,10 @@ static int psci_acpi_cpu_init_idle(unsigned int cpu) if (!psci_ops.cpu_suspend) return -EOPNOTSUPP; - count = pr->power.count - 1; - if (count <= 0) - return -ENODEV; - - for (i = 0; i < count; i++) { + for (i = 1; i < pr->power.count; i++) { u32 state; - lpi = &pr->power.lpi_states[i + 1]; + lpi = &pr->power.lpi_states[i]; /* * Only bits[31:0] represent a PSCI power_state while * bits[63:32] must be 0x0 as per ARM ACPI FFH Specification diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 2e91c5a97761..f370be8715ae 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -362,7 +362,7 @@ static int send_pcc_cmd(int pcc_ss_id, u16 cmd) end: if (cmd == CMD_WRITE) { if (unlikely(ret)) { - for_each_online_cpu(i) { + for_each_possible_cpu(i) { struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i); if (!desc) @@ -524,13 +524,13 @@ int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data) else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY) cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY; - for_each_online_cpu(i) { + for_each_possible_cpu(i) { if (i == cpu) continue; match_cpc_ptr = per_cpu(cpc_desc_ptr, i); if (!match_cpc_ptr) - goto err_fault; + continue; match_pdomain = &(match_cpc_ptr->domain_info); if (match_pdomain->domain != pdomain->domain) diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c index 0a3c8232d15d..458efa4fe9d4 100644 --- a/drivers/acpi/video_detect.c +++ b/drivers/acpi/video_detect.c @@ -916,6 +916,14 @@ static const struct dmi_system_id video_detect_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_NAME, "82K8"), }, }, + { + .callback = video_detect_force_native, + /* HP OMEN Gaming Laptop 16-n0xxx */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "HP"), + DMI_MATCH(DMI_PRODUCT_NAME, "OMEN by HP Gaming Laptop 16-n0xxx"), + }, + }, /* * x86 android tablets which directly control the backlight through diff --git a/drivers/ata/pata_parport/pata_parport.c b/drivers/ata/pata_parport/pata_parport.c index a5b959891cb7..40baeac594a9 100644 --- a/drivers/ata/pata_parport/pata_parport.c +++ b/drivers/ata/pata_parport/pata_parport.c @@ -459,19 +459,11 @@ static void pata_parport_dev_release(struct device *dev) kfree(pi); } -static void pata_parport_bus_release(struct device *dev) -{ - /* nothing to do here but required to avoid warning on device removal */ -} - static const struct bus_type pata_parport_bus_type = { .name = DRV_NAME, }; -static struct device pata_parport_bus = { - .init_name = DRV_NAME, - .release = pata_parport_bus_release, -}; +static struct device *pata_parport_bus; static const struct scsi_host_template pata_parport_sht = { PATA_PARPORT_SHT("pata_parport") @@ -518,7 +510,7 @@ static struct pi_adapter *pi_init_one(struct parport *parport, } /* set up pi->dev before pi_probe_unit() so it can use dev_printk() */ - pi->dev.parent = &pata_parport_bus; + pi->dev.parent = pata_parport_bus; pi->dev.bus = &pata_parport_bus_type; pi->dev.driver = &pr->driver; pi->dev.release = pata_parport_dev_release; @@ -780,8 +772,9 @@ static __init int pata_parport_init(void) return error; } - error = device_register(&pata_parport_bus); - if (error) { + pata_parport_bus = root_device_register(DRV_NAME); + if (IS_ERR(pata_parport_bus)) { + error = PTR_ERR(pata_parport_bus); pr_err("failed to register pata_parport bus, error: %d\n", error); goto out_unregister_bus; } @@ -811,7 +804,7 @@ static __init int pata_parport_init(void) out_remove_new: bus_remove_file(&pata_parport_bus_type, &bus_attr_new_device); out_unregister_dev: - device_unregister(&pata_parport_bus); + root_device_unregister(pata_parport_bus); out_unregister_bus: bus_unregister(&pata_parport_bus_type); return error; @@ -822,7 +815,7 @@ static __exit void pata_parport_exit(void) parport_unregister_driver(&pata_parport_driver); bus_remove_file(&pata_parport_bus_type, &bus_attr_new_device); bus_remove_file(&pata_parport_bus_type, &bus_attr_delete_device); - device_unregister(&pata_parport_bus); + root_device_unregister(pata_parport_bus); bus_unregister(&pata_parport_bus_type); } diff --git a/drivers/base/regmap/regmap-sdw-mbq.c b/drivers/base/regmap/regmap-sdw-mbq.c index 4533fe793c5f..2585933d4946 100644 --- a/drivers/base/regmap/regmap-sdw-mbq.c +++ b/drivers/base/regmap/regmap-sdw-mbq.c @@ -172,7 +172,7 @@ static int regmap_sdw_mbq_read(void *context, unsigned int reg, unsigned int *va ret = regmap_sdw_mbq_read_impl(slave, reg, val, mbq_size); if (ret == -ENODATA) { if (!deferrable) - dev_warn(dev, "Defer on undeferable control: %x\n", reg); + dev_warn(dev, "Defer on undeferrable control: %x\n", reg); ret = regmap_sdw_mbq_poll_busy(slave, reg, ctx); if (ret) diff --git a/drivers/cdrom/cdrom.c b/drivers/cdrom/cdrom.c index fc049612d6dc..62934cf4b10d 100644 --- a/drivers/cdrom/cdrom.c +++ b/drivers/cdrom/cdrom.c @@ -631,6 +631,16 @@ int register_cdrom(struct gendisk *disk, struct cdrom_device_info *cdi) WARN_ON(!cdo->generic_packet); + /* + * Propagate the drive's write support to the block layer so BLKROGET + * reflects actual write capability. Drivers that use GET CONFIGURATION + * features (CDC_MRW_W, CDC_RAM) must have called + * cdrom_probe_write_features() before register_cdrom() so the mask is + * complete here. + */ + set_disk_ro(disk, !CDROM_CAN(CDC_DVD_RAM | CDC_MRW_W | CDC_RAM | + CDC_CD_RW)); + cd_dbg(CD_REG_UNREG, "drive \"/dev/%s\" registered\n", cdi->name); mutex_lock(&cdrom_mutex); list_add(&cdi->list, &cdrom_list); @@ -742,6 +752,44 @@ static int cdrom_is_random_writable(struct cdrom_device_info *cdi, int *write) return 0; } +/* + * Probe write-related MMC features via GET CONFIGURATION and update + * cdi->mask accordingly. Drivers that populate cdi->mask from the MODE SENSE + * capabilities page (e.g. sr) should call this after those MODE SENSE bits + * have been set but before register_cdrom(), so that the full set of + * write-capability bits is known by the time register_cdrom() decides on the + * initial read-only state of the disk. + */ +void cdrom_probe_write_features(struct cdrom_device_info *cdi) +{ + int mrw, mrw_write, ram_write; + + mrw = 0; + if (!cdrom_is_mrw(cdi, &mrw_write)) + mrw = 1; + + if (CDROM_CAN(CDC_MO_DRIVE)) + ram_write = 1; + else + (void) cdrom_is_random_writable(cdi, &ram_write); + + if (mrw) + cdi->mask &= ~CDC_MRW; + else + cdi->mask |= CDC_MRW; + + if (mrw_write) + cdi->mask &= ~CDC_MRW_W; + else + cdi->mask |= CDC_MRW_W; + + if (ram_write) + cdi->mask &= ~CDC_RAM; + else + cdi->mask |= CDC_RAM; +} +EXPORT_SYMBOL(cdrom_probe_write_features); + static int cdrom_media_erasable(struct cdrom_device_info *cdi) { disc_information di; @@ -894,33 +942,8 @@ static int cdrom_is_dvd_rw(struct cdrom_device_info *cdi) */ static int cdrom_open_write(struct cdrom_device_info *cdi) { - int mrw, mrw_write, ram_write; int ret = 1; - mrw = 0; - if (!cdrom_is_mrw(cdi, &mrw_write)) - mrw = 1; - - if (CDROM_CAN(CDC_MO_DRIVE)) - ram_write = 1; - else - (void) cdrom_is_random_writable(cdi, &ram_write); - - if (mrw) - cdi->mask &= ~CDC_MRW; - else - cdi->mask |= CDC_MRW; - - if (mrw_write) - cdi->mask &= ~CDC_MRW_W; - else - cdi->mask |= CDC_MRW_W; - - if (ram_write) - cdi->mask &= ~CDC_RAM; - else - cdi->mask |= CDC_RAM; - if (CDROM_CAN(CDC_MRW_W)) ret = cdrom_mrw_open_write(cdi); else if (CDROM_CAN(CDC_DVD_RAM)) diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c index af7ce62ec55c..0ff1658c2dc1 100644 --- a/drivers/dpll/dpll_netlink.c +++ b/drivers/dpll/dpll_netlink.c @@ -900,11 +900,21 @@ int dpll_pin_delete_ntf(struct dpll_pin *pin) return dpll_pin_event_send(DPLL_CMD_PIN_DELETE_NTF, pin); } +/** + * __dpll_pin_change_ntf - notify that the pin has been changed + * @pin: registered pin pointer + * + * Context: caller must hold dpll_lock. Suitable for use inside pin + * callbacks which are already invoked under dpll_lock. + * Return: 0 if succeeds, error code otherwise. + */ int __dpll_pin_change_ntf(struct dpll_pin *pin) { + lockdep_assert_held(&dpll_lock); dpll_pin_notify(pin, DPLL_PIN_CHANGED); return dpll_pin_event_send(DPLL_CMD_PIN_CHANGE_NTF, pin); } +EXPORT_SYMBOL_GPL(__dpll_pin_change_ntf); /** * dpll_pin_change_ntf - notify that the pin has been changed diff --git a/drivers/dpll/dpll_netlink.h b/drivers/dpll/dpll_netlink.h index dd28b56d27c5..a9cfd55f57fc 100644 --- a/drivers/dpll/dpll_netlink.h +++ b/drivers/dpll/dpll_netlink.h @@ -11,5 +11,3 @@ int dpll_device_delete_ntf(struct dpll_device *dpll); int dpll_pin_create_ntf(struct dpll_pin *pin); int dpll_pin_delete_ntf(struct dpll_pin *pin); - -int __dpll_pin_change_ntf(struct dpll_pin *pin); diff --git a/drivers/gpu/drm/adp/adp_drv.c b/drivers/gpu/drm/adp/adp_drv.c index 0a11820d5b8a..ce9dd6222634 100644 --- a/drivers/gpu/drm/adp/adp_drv.c +++ b/drivers/gpu/drm/adp/adp_drv.c @@ -129,7 +129,7 @@ struct adp_drv_private { #define crtc_to_adp(x) container_of(x, struct adp_drv_private, crtc) static int adp_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state; struct drm_crtc_state *crtc_state; @@ -151,7 +151,7 @@ static int adp_plane_atomic_check(struct drm_plane *plane, } static void adp_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct adp_drv_private *adp; struct drm_rect src_rect; @@ -193,7 +193,7 @@ static void adp_plane_atomic_update(struct drm_plane *plane, } static void adp_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct adp_drv_private *adp = to_adp(plane->dev); @@ -279,7 +279,7 @@ static void adp_crtc_disable_vblank(struct drm_crtc *crtc) } static void adp_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct adp_drv_private *adp = crtc_to_adp(crtc); @@ -292,7 +292,7 @@ static void adp_crtc_atomic_enable(struct drm_crtc *crtc, } static void adp_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct adp_drv_private *adp = crtc_to_adp(crtc); struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -308,7 +308,7 @@ static void adp_crtc_atomic_disable(struct drm_crtc *crtc, } static void adp_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { u32 frame_num = 1; unsigned long flags; diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index db66c6372199..154a60e22c70 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -90,7 +90,7 @@ amdgpu-y += \ nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o soc24.o \ sienna_cichlid.o smu_v13_0_10.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o \ nbio_v7_9.o aqua_vanjaram.o nbio_v7_11.o lsdma_v7_0.o hdp_v7_0.o nbif_v6_3_1.o \ - cyan_skillfish_reg_init.o soc_v1_0.o lsdma_v7_1.o + cyan_skillfish_reg_init.o soc_v1_0.o lsdma_v7_1.o nbio_v6_3_2.o # add DF block amdgpu-y += \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 8bc591deb546..25b80d4b097f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -464,7 +464,7 @@ int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ /** - * amdgpu_wb - This struct is used for small GPU memory allocation. + * struct amdgpu_wb - This struct is used for small GPU memory allocation. * * This struct is used to allocate a small amount of GPU memory that can be * used to shadow certain states into the memory. This is especially useful for @@ -538,44 +538,6 @@ struct amdgpu_allowed_register_entry { bool grbm_indexed; }; -/** - * enum amd_reset_method - Methods for resetting AMD GPU devices - * - * @AMD_RESET_METHOD_NONE: The device will not be reset. - * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. - * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the - * any device. - * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) - * individually. Suitable only for some discrete GPU, not - * available for all ASICs. - * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs - * are reset depends on the ASIC. Notably doesn't reset IPs - * shared with the CPU on APUs or the memory controllers (so - * VRAM is not lost). Not available on all ASICs. - * @AMD_RESET_LINK: Triggers SW-UP link reset on other GPUs - * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card - * but without powering off the PCI bus. Suitable only for - * discrete GPUs. - * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset - * and does a secondary bus reset or FLR, depending on what the - * underlying hardware supports. - * - * Methods available for AMD GPU driver for resetting the device. Not all - * methods are suitable for every device. User can override the method using - * module parameter `reset_method`. - */ -enum amd_reset_method { - AMD_RESET_METHOD_NONE = -1, - AMD_RESET_METHOD_LEGACY = 0, - AMD_RESET_METHOD_MODE0, - AMD_RESET_METHOD_MODE1, - AMD_RESET_METHOD_MODE2, - AMD_RESET_METHOD_LINK, - AMD_RESET_METHOD_BACO, - AMD_RESET_METHOD_PCI, - AMD_RESET_METHOD_ON_INIT, -}; - struct amdgpu_video_codec_info { u32 codec_type; u32 max_width; @@ -1373,6 +1335,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) +#include "amdgpu_reset.h" + /* * ASICs macro. */ @@ -1462,6 +1426,8 @@ ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, const struct amdgpu_vm_pte_funcs *vm_pte_funcs); +void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev, + const struct amdgpu_buffer_funcs *buffer_funcs); /* atpx handler */ #if defined(CONFIG_VGA_SWITCHEROO) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index 35d04e69aec0..aa039e148a5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -33,6 +33,7 @@ #include #include #include +#include /* * BIOS. */ @@ -467,7 +468,8 @@ static bool amdgpu_prefer_rom_resource(struct amdgpu_device *adev) { struct resource *res = &adev->pdev->resource[PCI_ROM_RESOURCE]; - return (res->flags & IORESOURCE_ROM_SHADOW); + return (res->flags & IORESOURCE_ROM_SHADOW) || + adev->pdev == vga_default_device(); } static bool amdgpu_get_bios_dgpu(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c index 4e6e390854e6..004edc28d0cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c @@ -153,7 +153,7 @@ int amdgpu_cper_entry_fill_fatal_section(struct amdgpu_device *adev, FATAL_SEC_OFFSET(hdr->sec_cnt, idx)); amdgpu_cper_entry_fill_section_desc(adev, section_desc, false, false, - CPER_SEV_FATAL, CRASHDUMP, FATAL_SEC_LEN, + CPER_SEV_FATAL_UNCORRECTED, CRASHDUMP, FATAL_SEC_LEN, FATAL_SEC_OFFSET(hdr->sec_cnt, idx)); section->body.reg_ctx_type = CPER_CTX_TYPE_CRASH; @@ -215,7 +215,7 @@ int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev NONSTD_SEC_OFFSET(hdr->sec_cnt, idx)); amdgpu_cper_entry_fill_section_desc(adev, section_desc, true, false, - CPER_SEV_FATAL, RUNTIME, NONSTD_SEC_LEN, + CPER_SEV_FATAL_UNCORRECTED, RUNTIME, NONSTD_SEC_LEN, NONSTD_SEC_OFFSET(hdr->sec_cnt, idx)); section->hdr.valid_bits.err_info_cnt = 1; @@ -312,7 +312,7 @@ int amdgpu_cper_generate_ue_record(struct amdgpu_device *adev, reg_data.synd_lo = lower_32_bits(bank->regs[ACA_REG_IDX_SYND]); reg_data.synd_hi = upper_32_bits(bank->regs[ACA_REG_IDX_SYND]); - amdgpu_cper_entry_fill_hdr(adev, fatal, AMDGPU_CPER_TYPE_FATAL, CPER_SEV_FATAL); + amdgpu_cper_entry_fill_hdr(adev, fatal, AMDGPU_CPER_TYPE_FATAL, CPER_SEV_FATAL_UNCORRECTED); ret = amdgpu_cper_entry_fill_fatal_section(adev, fatal, 0, reg_data); if (ret) return ret; @@ -337,7 +337,7 @@ int amdgpu_cper_generate_bp_threshold_record(struct amdgpu_device *adev) amdgpu_cper_entry_fill_hdr(adev, bp_threshold, AMDGPU_CPER_TYPE_BP_THRESHOLD, - CPER_SEV_FATAL); + CPER_SEV_FATAL_UNCORRECTED); ret = amdgpu_cper_entry_fill_bad_page_threshold_section(adev, bp_threshold, 0); if (ret) return ret; @@ -353,14 +353,14 @@ static enum cper_error_severity amdgpu_aca_err_type_to_cper_sev(struct amdgpu_de { switch (aca_err_type) { case ACA_ERROR_TYPE_UE: - return CPER_SEV_FATAL; + return CPER_SEV_FATAL_UNCORRECTED; case ACA_ERROR_TYPE_CE: return CPER_SEV_NON_FATAL_CORRECTED; case ACA_ERROR_TYPE_DEFERRED: return CPER_SEV_NON_FATAL_UNCORRECTED; default: dev_err(adev->dev, "Unknown ACA error type!\n"); - return CPER_SEV_FATAL; + return CPER_SEV_FATAL_UNCORRECTED; } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 20fcfa09e9e3..d293444d026f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2459,7 +2459,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) if (r) goto init_failed; - amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_ttm_enable_buffer_funcs(adev); /* Don't init kfd if whole hive need to be reset during init */ if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { @@ -2838,8 +2838,12 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) * that checks whether the PSP is running. A solution for those issues * in the APU is to trigger a GPU reset, but this should be done during * the unload phase to avoid adding boot latency and screen flicker. + * GFX V11 has GC block as default off IP. Every time AMDGPU driver sends + * a request to PMFW to unload MP1, PMFW will put GC in reset and power down + * the voltage. Hence, skipping reset for APUs with GFX V11 or later. */ - if ((adev->flags & AMD_IS_APU) && !adev->gmc.is_app_apu) { + if ((adev->flags & AMD_IS_APU) && !adev->gmc.is_app_apu && + amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 0, 0)) { r = amdgpu_asic_reset(adev); if (r) dev_err(adev->dev, "asic reset on %s failed\n", __func__); @@ -3143,7 +3147,7 @@ static int amdgpu_device_ip_suspend(struct amdgpu_device *adev) amdgpu_virt_request_full_gpu(adev, false); } - amdgpu_ttm_set_buffer_funcs_status(adev, false); + amdgpu_ttm_disable_buffer_funcs(adev); r = amdgpu_device_ip_suspend_phase1(adev); if (r) @@ -3358,7 +3362,7 @@ static int amdgpu_device_ip_resume(struct amdgpu_device *adev) r = amdgpu_device_ip_resume_phase2(adev); - amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_ttm_enable_buffer_funcs(adev); if (r) return r; @@ -3696,7 +3700,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->num_rings = 0; RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub()); adev->mman.buffer_funcs = NULL; - adev->mman.buffer_funcs_ring = NULL; + adev->mman.num_buffer_funcs_scheds = 0; adev->vm_manager.vm_pte_funcs = NULL; adev->vm_manager.vm_pte_num_scheds = 0; adev->gmc.gmc_funcs = NULL; @@ -3853,6 +3857,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, * completed before the need for a different level is detected. */ amdgpu_set_init_level(adev, AMDGPU_INIT_LEVEL_DEFAULT); + + amdgpu_device_check_iommu_direct_map(adev); + /* early init functions */ r = amdgpu_device_ip_early_init(adev); if (r) @@ -4110,8 +4117,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, if (px) vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); - amdgpu_device_check_iommu_direct_map(adev); - adev->pm_nb.notifier_call = amdgpu_device_pm_notifier; r = register_pm_notifier(&adev->pm_nb); if (r) @@ -4209,7 +4214,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) /* disable ras feature must before hw fini */ amdgpu_ras_pre_fini(adev); - amdgpu_ttm_set_buffer_funcs_status(adev, false); + amdgpu_ttm_disable_buffer_funcs(adev); /* * device went through surprise hotplug; we need to destroy topology @@ -4476,7 +4481,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) if (r) goto unwind_userq; - amdgpu_ttm_set_buffer_funcs_status(adev, false); + amdgpu_ttm_disable_buffer_funcs(adev); amdgpu_fence_driver_hw_fini(adev); @@ -4490,7 +4495,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) return 0; unwind_evict: - amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_ttm_enable_buffer_funcs(adev); amdgpu_fence_driver_hw_init(adev); unwind_userq: @@ -5224,7 +5229,7 @@ int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context) if (r) goto out; - amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true); + amdgpu_ttm_enable_buffer_funcs(tmp_adev); r = amdgpu_device_ip_resume_phase3(tmp_adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index fcad7daaa41b..a6040ad15384 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -64,6 +64,7 @@ #include "nbio_v7_2.h" #include "nbio_v7_7.h" #include "nbif_v6_3_1.h" +#include "nbio_v6_3_2.h" #include "hdp_v5_0.h" #include "hdp_v5_2.h" #include "hdp_v6_0.h" @@ -3090,10 +3091,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): - adev->family = AMDGPU_FAMILY_GC_11_5_0; - break; case IP_VERSION(11, 5, 4): - adev->family = AMDGPU_FAMILY_GC_11_5_4; + adev->family = AMDGPU_FAMILY_GC_11_5_0; break; case IP_VERSION(12, 0, 0): case IP_VERSION(12, 0, 1): @@ -3195,6 +3194,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) adev->nbio.funcs = &nbif_v6_3_1_funcs; adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; break; + case IP_VERSION(6, 3, 2): + adev->nbio.funcs = &nbio_v6_3_2_funcs; + break; default: break; } @@ -3418,3 +3420,28 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) return 0; } +int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev, + uint16_t *major, uint16_t *minor) +{ + uint8_t *discovery_bin = adev->discovery.bin; + struct table_info *info; + union gc_info *gc_info; + u16 offset; + + if (!discovery_bin) + return -EINVAL; + if (amdgpu_discovery_get_table_info(adev, &info, GC)) + return -EINVAL; + + offset = le16_to_cpu(info->offset); + if (!offset) + return -EINVAL; + + gc_info = (union gc_info *)(discovery_bin + offset); + + if (major) + *major = le16_to_cpu(gc_info->v1.header.version_major); + if (minor) + *minor = le16_to_cpu(gc_info->v1.header.version_minor); + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h index 0ff1a7923eed..e0010f6a3eda 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h @@ -48,6 +48,8 @@ int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, uint32_t *nps_type, struct amdgpu_gmc_memrange *ranges, int *range_cnt, bool refresh); +int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev, + uint16_t *major, uint16_t *minor); void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index e47921e2a9af..60debd543e44 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3149,17 +3149,15 @@ static int __init amdgpu_init(void) r = amdgpu_sync_init(); if (r) - goto error_sync; - - r = amdgpu_userq_fence_slab_init(); - if (r) - goto error_fence; + return r; amdgpu_register_atpx_handler(); amdgpu_acpi_detect(); - /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ - amdgpu_amdkfd_init(); + /* Ignore KFD init failures when CONFIG_HSA_AMD is not set. */ + r = amdgpu_amdkfd_init(); + if (r && r != -ENOENT) + goto error_fini_sync; if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); @@ -3170,10 +3168,8 @@ static int __init amdgpu_init(void) /* let modprobe override vga console setting */ return pci_register_driver(&amdgpu_kms_pci_driver); -error_fence: +error_fini_sync: amdgpu_sync_fini(); - -error_sync: return r; } @@ -3184,7 +3180,6 @@ static void __exit amdgpu_exit(void) amdgpu_unregister_atpx_handler(); amdgpu_acpi_release(); amdgpu_sync_fini(); - amdgpu_userq_fence_slab_fini(); mmu_notifier_synchronize(); amdgpu_xcp_drv_release(); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index bc772ca3dab7..b6f849d51c2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -262,12 +262,19 @@ void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) */ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) { + int r; + if (adev->gart.bo != NULL) return 0; - return amdgpu_bo_create_kernel(adev, adev->gart.table_size, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.bo, - NULL, (void *)&adev->gart.ptr); + r = amdgpu_bo_create_kernel(adev, adev->gart.table_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.bo, + NULL, (void *)&adev->gart.ptr); + if (r) + return r; + + memset_io(adev->gart.ptr, adev->gart.gart_pte_flags, adev->gart.table_size); + return 0; } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 5376035d32fe..9ef80bca4102 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -27,6 +27,7 @@ */ #include #include +#include #include #include #include @@ -1217,13 +1218,14 @@ int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data, return ret; } -static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, - int width, - int cpp, - bool tiled) +static unsigned int amdgpu_gem_align_pitch(struct amdgpu_device *adev, + unsigned int width, + unsigned int cpp, + bool tiled) { - int aligned = width; - int pitch_mask = 0; + unsigned int aligned = width; + unsigned int pitch_mask = 0; + unsigned int pitch; switch (cpp) { case 1: @@ -1238,9 +1240,12 @@ static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, break; } - aligned += pitch_mask; + if (check_add_overflow(aligned, pitch_mask, &aligned)) + return 0; aligned &= ~pitch_mask; - return aligned * cpp; + if (check_mul_overflow(aligned, cpp, &pitch)) + return 0; + return pitch; } int amdgpu_mode_dumb_create(struct drm_file *file_priv, @@ -1267,8 +1272,12 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, args->pitch = amdgpu_gem_align_pitch(adev, args->width, DIV_ROUND_UP(args->bpp, 8), 0); + if (!args->pitch) + return -EINVAL; args->size = (u64)args->pitch * args->height; args->size = ALIGN(args->size, PAGE_SIZE); + if (!args->size) + return -EINVAL; domain = amdgpu_bo_get_preferred_domain(adev, amdgpu_display_supported_domains(adev, flags)); r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index b8ca876694ff..515cc4a2aeb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -2686,3 +2686,54 @@ void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev) #endif } +int amdgpu_gfx_ring_preempt_ib(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; + struct amdgpu_ring *kiq_ring = &kiq->ring; + unsigned long flags; + int i; + + if (adev->enable_mes) + return -EINVAL; + + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) + return -EINVAL; + + spin_lock_irqsave(&kiq->ring_lock, flags); + + if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { + spin_unlock_irqrestore(&kiq->ring_lock, flags); + return -ENOMEM; + } + + /* assert preemption condition */ + amdgpu_ring_set_preempt_cond_exec(ring, false); + + /* assert IB preemption, emit the trailing fence */ + kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, + ring->trail_fence_gpu_addr, + ++ring->trail_seq); + amdgpu_ring_commit(kiq_ring); + + spin_unlock_irqrestore(&kiq->ring_lock, flags); + + /* poll the trailing fence */ + for (i = 0; i < adev->usec_timeout; i++) { + if (ring->trail_seq == + le32_to_cpu(*(ring->trail_fence_cpu_addr))) + break; + udelay(1); + } + + /* deassert preemption condition */ + amdgpu_ring_set_preempt_cond_exec(ring, true); + + if (i >= adev->usec_timeout) { + DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); + return -EINVAL; + } + + return 0; +} + diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index a0cf0a3b41da..77050f9884f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -664,6 +664,8 @@ void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count); void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev); void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev); +int amdgpu_gfx_ring_preempt_ib(struct amdgpu_ring *ring); + static inline const char *amdgpu_gfx_compute_mode_desc(int mode) { switch (mode) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 285e217fba04..276f9f49d6d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -280,6 +280,15 @@ void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc mc->gart_size >> 20, mc->gart_start, mc->gart_end); } +void amdgpu_gmc_set_gart_size(struct amdgpu_device *adev, u64 default_size) +{ + if (amdgpu_gart_size == -1) + adev->gmc.gart_size = + default_size + adev->pm.smu_prv_buffer_size; + else + adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; +} + /** * amdgpu_gmc_gart_location - try to find GART location * @@ -314,7 +323,10 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, mc->gart_start = max_mc_address - mc->gart_size + 1; break; case AMDGPU_GART_PLACEMENT_LOW: - mc->gart_start = 0; + if (size_bf >= mc->gart_size) + mc->gart_start = 0; + else + mc->gart_start = ALIGN(mc->fb_end, four_gb); break; case AMDGPU_GART_PLACEMENT_BEST_FIT: default: @@ -708,12 +720,14 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, uint32_t vmhub, uint32_t flush_type) { - struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; + struct amdgpu_ring *ring; struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; struct dma_fence *fence; struct amdgpu_job *job; int r; + ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); + if (!hub->sdma_invalidation_workaround || vmid || !adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready || !ring->sched.ready) { @@ -1002,6 +1016,9 @@ void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) gc_ver == IP_VERSION(9, 5, 0) || gc_ver >= IP_VERSION(10, 3, 0)); + /* For GFX12.1 B0, set xnack (retry) on as default */ + if (gc_ver == IP_VERSION(12, 1, 0) && (adev->rev_id & 0xf) == 0x1) + noretry_default = false; if (!amdgpu_sriov_xnack_support(adev)) gmc->noretry = 1; else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index 6ab4c1e297fc..676e3aaa1f27 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -365,6 +365,8 @@ struct amdgpu_gmc { bool flush_tlb_needs_extra_type_0; bool flush_tlb_needs_extra_type_2; bool flush_pasid_uses_kiq; + + bool override_pte; }; #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) @@ -484,4 +486,6 @@ void amdgpu_gmc_init_sw_mem_ranges(struct amdgpu_device *adev, struct amdgpu_mem_partition_info *mem_ranges); int amdgpu_gmc_get_vram_info(struct amdgpu_device *adev, int *vram_width, int *vram_type, int *vram_vendor); + +void amdgpu_gmc_set_gart_size(struct amdgpu_device *adev, u64 default_size); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h index f58b6be7fccc..444437c30088 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h @@ -91,6 +91,12 @@ struct amdgpu_ih_funcs { uint64_t (*decode_iv_ts)(struct amdgpu_ih_ring *ih, u32 rptr, signed int offset); void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); + /* Decode IH cookie node_id into a human-readable die name string. + * Returns buf, or NULL if this IH version does not support node_id decoding. + */ + const char *(*node_id_to_die_name)(struct amdgpu_device *adev, + unsigned int node_id, + char *buf, size_t size); }; #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h index 9c56be725ff3..eb8537558f5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h @@ -39,7 +39,6 @@ struct amdgpu_imu_funcs { int (*switch_compute_partition)(struct amdgpu_device *adev, int num_xccs_per_xcp, int compute_partition_mode); - void (*init_mcm_addr_lut)(struct amdgpu_device *adev); }; struct imu_rlc_ram_golden { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 06efce38f323..71272f40feef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -873,68 +873,59 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) ? -EFAULT : 0; } case AMDGPU_INFO_READ_MMR_REG: { - int ret = 0; - unsigned int n, alloc_size; - uint32_t *regs; unsigned int se_num = (info->read_mmr_reg.instance >> AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & AMDGPU_INFO_MMR_SE_INDEX_MASK; unsigned int sh_num = (info->read_mmr_reg.instance >> AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & AMDGPU_INFO_MMR_SH_INDEX_MASK; - - if (!down_read_trylock(&adev->reset_domain->sem)) - return -ENOENT; + unsigned int alloc_size; + uint32_t *regs; + int ret; /* set full masks if the userspace set all bits * in the bitfields */ - if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) { + if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) se_num = 0xffffffff; - } else if (se_num >= AMDGPU_GFX_MAX_SE) { - ret = -EINVAL; - goto out; - } + else if (se_num >= AMDGPU_GFX_MAX_SE) + return -EINVAL; - if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) { + if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) sh_num = 0xffffffff; - } else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) { - ret = -EINVAL; - goto out; - } + else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) + return -EINVAL; - if (info->read_mmr_reg.count > 128) { - ret = -EINVAL; - goto out; - } + if (info->read_mmr_reg.count > 128) + return -EINVAL; - regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); - if (!regs) { - ret = -ENOMEM; - goto out; - } + regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), + GFP_KERNEL); + if (!regs) + return -ENOMEM; + down_read(&adev->reset_domain->sem); alloc_size = info->read_mmr_reg.count * sizeof(*regs); - amdgpu_gfx_off_ctrl(adev, false); + ret = 0; for (i = 0; i < info->read_mmr_reg.count; i++) { if (amdgpu_asic_read_register(adev, se_num, sh_num, info->read_mmr_reg.dword_offset + i, ®s[i])) { DRM_DEBUG_KMS("unallowed offset %#x\n", info->read_mmr_reg.dword_offset + i); - kfree(regs); - amdgpu_gfx_off_ctrl(adev, true); ret = -EFAULT; - goto out; + break; } } amdgpu_gfx_off_ctrl(adev, true); - n = copy_to_user(out, regs, min(size, alloc_size)); - kfree(regs); - ret = (n ? -EFAULT : 0); -out: up_read(&adev->reset_domain->sem); + + if (!ret) { + ret = copy_to_user(out, regs, min(size, alloc_size)) + ? -EFAULT : 0; + } + kfree(regs); return ret; } case AMDGPU_INFO_DEV_INFO: { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 0d4c77c1b4b5..610dc2ca67a2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -103,7 +103,7 @@ static inline u32 amdgpu_mes_get_hqd_mask(u32 num_pipe, int amdgpu_mes_init(struct amdgpu_device *adev) { - int i, r, num_pipes; + int i, r, num_pipes, num_queues = 0; u32 total_vmid_mask, reserved_vmid_mask; int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; u32 gfx_hqd_mask = amdgpu_mes_get_hqd_mask(adev->gfx.me.num_pipe_per_me, @@ -159,7 +159,8 @@ int amdgpu_mes_init(struct amdgpu_device *adev) adev->mes.compute_hqd_mask[i] = compute_hqd_mask; } - num_pipes = adev->sdma.num_instances; + num_pipes = adev->sdma.num_inst_per_xcc ? + adev->sdma.num_inst_per_xcc : adev->sdma.num_instances; if (num_pipes > AMDGPU_MES_MAX_SDMA_PIPES) dev_warn(adev->dev, "more SDMA pipes than supported by MES! (%d vs %d)\n", num_pipes, AMDGPU_MES_MAX_SDMA_PIPES); @@ -216,8 +217,27 @@ int amdgpu_mes_init(struct amdgpu_device *adev) if (r) goto error_doorbell; + if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 1, 0)) { + /* When queue/pipe reset is done in MES instead of in the + * driver, MES passes hung queues information to the driver in + * hung_queue_hqd_info. Calculate required space to store this + * information. + */ + for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) + num_queues += hweight32(adev->mes.gfx_hqd_mask[i]); + + for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) + num_queues += hweight32(adev->mes.compute_hqd_mask[i]); + + for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) + num_queues += hweight32(adev->mes.sdma_hqd_mask[i]) * num_xcc; + + adev->mes.hung_queue_hqd_info_offset = num_queues; + adev->mes.hung_queue_db_array_size = num_queues * 2; + } + if (adev->mes.hung_queue_db_array_size) { - for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { + for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) { r = amdgpu_bo_create_kernel(adev, adev->mes.hung_queue_db_array_size * sizeof(u32), PAGE_SIZE, @@ -264,10 +284,10 @@ void amdgpu_mes_fini(struct amdgpu_device *adev) &adev->mes.event_log_cpu_addr); for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { - amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj[i], - &adev->mes.hung_queue_db_array_gpu_addr[i], - &adev->mes.hung_queue_db_array_cpu_addr[i]); - + if (adev->mes.hung_queue_db_array_gpu_obj[i]) + amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj[i], + &adev->mes.hung_queue_db_array_gpu_addr[i], + &adev->mes.hung_queue_db_array_cpu_addr[i]); if (adev->mes.sch_ctx_ptr[i]) amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]); if (adev->mes.query_status_fence_ptr[i]) @@ -281,7 +301,7 @@ void amdgpu_mes_fini(struct amdgpu_device *adev) mutex_destroy(&adev->mes.mutex_hidden); } -int amdgpu_mes_suspend(struct amdgpu_device *adev) +int amdgpu_mes_suspend(struct amdgpu_device *adev, u32 xcc_id) { struct mes_suspend_gang_input input; int r; @@ -291,6 +311,7 @@ int amdgpu_mes_suspend(struct amdgpu_device *adev) memset(&input, 0x0, sizeof(struct mes_suspend_gang_input)); input.suspend_all_gangs = 1; + input.xcc_id = xcc_id; /* * Avoid taking any other locks under MES lock to avoid circular @@ -305,7 +326,7 @@ int amdgpu_mes_suspend(struct amdgpu_device *adev) return r; } -int amdgpu_mes_resume(struct amdgpu_device *adev) +int amdgpu_mes_resume(struct amdgpu_device *adev, u32 xcc_id) { struct mes_resume_gang_input input; int r; @@ -315,6 +336,7 @@ int amdgpu_mes_resume(struct amdgpu_device *adev) memset(&input, 0x0, sizeof(struct mes_resume_gang_input)); input.resume_all_gangs = 1; + input.xcc_id = xcc_id; /* * Avoid taking any other locks under MES lock to avoid circular @@ -428,7 +450,7 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, { struct mes_detect_and_reset_queue_input input; u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr[xcc_id]; - int r, i; + int hqd_info_offset = adev->mes.hung_queue_hqd_info_offset, r, i; if (!hung_db_num || !hung_db_array) return -EINVAL; @@ -443,26 +465,34 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, adev->mes.hung_queue_db_array_size * sizeof(u32)); input.queue_type = queue_type; input.detect_only = detect_only; + input.xcc_id = xcc_id; r = adev->mes.funcs->detect_and_reset_hung_queues(&adev->mes, &input); - if (r) { - dev_err(adev->dev, "failed to detect and reset\n"); - } else { - *hung_db_num = 0; - for (i = 0; i < adev->mes.hung_queue_hqd_info_offset; i++) { - if (db_array[i] != AMDGPU_MES_INVALID_DB_OFFSET) { - hung_db_array[i] = db_array[i]; - *hung_db_num += 1; - } - } - /* - * TODO: return HQD info for MES scheduled user compute queue reset cases - * stored in hung_db_array hqd info offset to full array size - */ + if (r && detect_only) { + dev_err(adev->dev, "Failed to detect hung queues\n"); + return r; } + *hung_db_num = 0; + /* MES passes hung queues' doorbell to driver */ + for (i = 0; i < adev->mes.hung_queue_hqd_info_offset; i++) { + /* Finding hung queues where db_array[i] is a valid doorbell */ + if (db_array[i] != AMDGPU_MES_INVALID_DB_OFFSET) { + hung_db_array[i] = db_array[i]; + *hung_db_num += 1; + } + } + + if (r && !(*hung_db_num)) { + dev_err(adev->dev, "Failed to detect and reset hung queues\n"); + return r; + } + + for (i = hqd_info_offset; i < hqd_info_offset + *hung_db_num; i++) + hung_db_array[i] = db_array[i]; + return r; } @@ -758,6 +788,12 @@ bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev) amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)); } +bool amdgpu_mes_queue_reset_by_mes_supported(struct amdgpu_device *adev) +{ + return (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0) && + (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x73); +} + /* Fix me -- node_id is used to identify the correct MES instances in the future */ static int amdgpu_mes_set_enforce_isolation(struct amdgpu_device *adev, uint32_t node_id, bool enable) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index f80e3aca9c78..31cad8a5bb9f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -170,6 +170,19 @@ struct amdgpu_mes { uint64_t shared_cmd_buf_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; }; +struct amdgpu_mes_hung_queue_hqd_info { + union { + struct { + u32 queue_type: 3; // queue type + u32 pipe_index: 4; // pipe index + u32 queue_index: 8; // queue index + u32 reserved: 17; + }; + + u32 bit0_31; + }; +}; + struct amdgpu_mes_gang { int gang_id; int priority; @@ -312,8 +325,9 @@ struct mes_reset_queue_input { }; struct mes_detect_and_reset_queue_input { - uint32_t queue_type; - bool detect_only; + u32 queue_type; + bool detect_only; + u32 xcc_id; }; struct mes_inv_tlbs_pasid_input { @@ -429,8 +443,8 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); int amdgpu_mes_init(struct amdgpu_device *adev); void amdgpu_mes_fini(struct amdgpu_device *adev); -int amdgpu_mes_suspend(struct amdgpu_device *adev); -int amdgpu_mes_resume(struct amdgpu_device *adev); +int amdgpu_mes_suspend(struct amdgpu_device *adev, u32 xcc_id); +int amdgpu_mes_resume(struct amdgpu_device *adev, u32 xcc_id); int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring, uint32_t xcc_id); @@ -534,6 +548,7 @@ static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) } bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); +bool amdgpu_mes_queue_reset_by_mes_supported(struct amdgpu_device *adev); int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 51ab1a332615..8069fc41cc7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -38,7 +38,6 @@ #include #include #include -#include #include "amdgpu_irq.h" #include @@ -505,9 +504,6 @@ struct amdgpu_crtc { u32 line_time; u32 lb_vblank_lead_lines; struct drm_display_mode hw_mode; - /* for virtual dce */ - struct hrtimer vblank_timer; - enum amdgpu_interrupt_state vsync_timer_enabled; int otg_inst; struct drm_pending_vblank_event *event; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c index a974265837f0..e4c8e98725f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c @@ -84,3 +84,13 @@ int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if * amdgpu_ras_block_late_fini(adev, ras_block); return r; } + + +void amdgpu_nbio_program_aspm(struct amdgpu_device *adev) +{ + if (!amdgpu_device_should_use_aspm(adev)) + return; + + if (adev->nbio.funcs->program_aspm) + adev->nbio.funcs->program_aspm(adev); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h index b528de6a01f6..a61f3a6e8ec7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h @@ -121,4 +121,6 @@ u64 amdgpu_nbio_get_pcie_replay_count(struct amdgpu_device *adev); bool amdgpu_nbio_is_replay_cnt_supported(struct amdgpu_device *adev); +void amdgpu_nbio_program_aspm(struct amdgpu_device *adev); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index b6aabac39b46..f98bfba59a2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -717,13 +717,17 @@ int amdgpu_bo_create(struct amdgpu_device *adev, bo->tbo.resource->mem_type == TTM_PL_VRAM) { struct dma_fence *fence; - r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence); + r = amdgpu_ttm_clear_buffer(amdgpu_ttm_next_clear_entity(adev), + bo, bo->tbo.base.resv, &fence, + true, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); if (unlikely(r)) goto fail_unreserve; - dma_resv_add_fence(bo->tbo.base.resv, fence, - DMA_RESV_USAGE_KERNEL); - dma_fence_put(fence); + if (fence) { + dma_resv_add_fence(bo->tbo.base.resv, fence, + DMA_RESV_USAGE_KERNEL); + dma_fence_put(fence); + } } if (!bp->resv) amdgpu_bo_unreserve(bo); @@ -1325,9 +1329,9 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) if (r) goto out; - r = amdgpu_fill_buffer(amdgpu_ttm_next_clear_entity(adev), - abo, 0, &bo->base._resv, - &fence, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); + r = amdgpu_ttm_clear_buffer(amdgpu_ttm_next_clear_entity(adev), + abo, &bo->base._resv, &fence, + false, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); if (WARN_ON(r)) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index f0e4d020f4c7..4a64e39fa9cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -518,7 +518,7 @@ static int psp_sw_init(struct amdgpu_ip_block *ip_block) } ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, - (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? + (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, &psp->fw_pri_bo, &psp->fw_pri_mc_addr, @@ -3527,7 +3527,12 @@ int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) const struct psp_firmware_header_v1_0 *toc_hdr; int err = 0; - err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, + if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 8) && + adev->rev_id == 0) + err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, + "amdgpu/%s_toc_1.bin", chip_name); + else + err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, "amdgpu/%s_toc.bin", chip_name); if (err) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index cdf4909592d2..0c57fe259894 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -1950,7 +1950,7 @@ void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev) if (!control || amdgpu_bad_page_threshold == 0) return; - if (control->ras_num_bad_pages >= ras->bad_page_cnt_threshold) { + if (control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { if (amdgpu_dpm_send_rma_reason(adev)) dev_warn(adev->dev, "Unable to send out-of-band RMA CPER"); else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index 540040c76058..daefbeeee4d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -956,3 +956,21 @@ uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst, } return ret; } + + +uint32_t amdgpu_read_indexed_register(struct amdgpu_device *adev, + u32 se_num, u32 sh_num, u32 reg_offset) +{ + uint32_t val; + + mutex_lock(&adev->grbm_idx_mutex); + if (se_num != 0xffffffff || sh_num != 0xffffffff) + amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); + + val = RREG32(reg_offset); + + if (se_num != 0xffffffff || sh_num != 0xffffffff) + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); + mutex_unlock(&adev->grbm_idx_mutex); + return val; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index 4d88e5cd19fc..a1011af6b52b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -160,4 +160,7 @@ uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst, uint32_t reg_addr, char reg_name[], uint32_t expected_value, uint32_t mask); +uint32_t amdgpu_read_indexed_register(struct amdgpu_device *adev, + u32 se_num, u32 sh_num, u32 reg_offset); + #endif /* __AMDGPU_REG_ACCESS_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h index 07b4d37f1db6..c9f23a8e8db8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h @@ -46,6 +46,47 @@ enum AMDGPU_RESET_SRCS { AMDGPU_RESET_SRC_USERQ, }; +/** + * enum amd_reset_method - Methods for resetting AMD GPU devices + * + * @AMD_RESET_METHOD_NONE: The device will not be reset. + * @AMD_RESET_METHOD_LEGACY: Method reserved for SI, CIK and VI ASICs. + * @AMD_RESET_METHOD_MODE0: Reset the entire ASIC. Not currently available for + * the any device. + * @AMD_RESET_METHOD_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, + * etc.) individually. Suitable only for some discrete GPU, + * not available for all ASICs. + * @AMD_RESET_METHOD_MODE2: Resets a lesser level of IPs compared to MODE1. + * Which IPs are reset depends on the ASIC. Notably doesn't + * reset IPs shared with the CPU on APUs or the memory + * controllers (so VRAM is not lost). Not available on all + * ASICs. + * @AMD_RESET_METHOD_LINK: Triggers SW-UP link reset on other GPUs + * @AMD_RESET_METHOD_BACO: BACO (Bus Alive, Chip Off) method powers off and on + * the card but without powering off the PCI bus. Suitable + * only for discrete GPUs. + * @AMD_RESET_METHOD_PCI: Does a full bus reset using core Linux subsystem + * PCI reset and does a secondary bus reset or FLR, + * depending on what the underlying hardware supports. + * @AMD_RESET_METHOD_ON_INIT: Does a device reset during the driver init + * sequence. + * + * Methods available for AMD GPU driver for resetting the device. Not all + * methods are suitable for every device. User can override the method using + * module parameter `reset_method`. + */ +enum amd_reset_method { + AMD_RESET_METHOD_NONE = -1, + AMD_RESET_METHOD_LEGACY = 0, + AMD_RESET_METHOD_MODE0, + AMD_RESET_METHOD_MODE1, + AMD_RESET_METHOD_MODE2, + AMD_RESET_METHOD_LINK, + AMD_RESET_METHOD_BACO, + AMD_RESET_METHOD_PCI, + AMD_RESET_METHOD_ON_INIT, +}; + struct amdgpu_reset_context { enum amd_reset_method method; struct amdgpu_device *reset_req_dev; @@ -56,6 +97,20 @@ struct amdgpu_reset_context { enum AMDGPU_RESET_SRCS src; }; +struct amdgpu_reset_control { + void *handle; + struct work_struct reset_work; + struct mutex reset_lock; + struct amdgpu_reset_handler *( + *reset_handlers)[AMDGPU_RESET_MAX_HANDLERS]; + atomic_t in_reset; + enum amd_reset_method active_reset; + struct amdgpu_reset_handler *(*get_reset_handler)( + struct amdgpu_reset_control *reset_ctl, + struct amdgpu_reset_context *context); + void (*async_reset)(struct work_struct *work); +}; + struct amdgpu_reset_handler { enum amd_reset_method reset_method; int (*prepare_env)(struct amdgpu_reset_control *reset_ctl, @@ -72,20 +127,6 @@ struct amdgpu_reset_handler { int (*do_reset)(struct amdgpu_device *adev); }; -struct amdgpu_reset_control { - void *handle; - struct work_struct reset_work; - struct mutex reset_lock; - struct amdgpu_reset_handler *( - *reset_handlers)[AMDGPU_RESET_MAX_HANDLERS]; - atomic_t in_reset; - enum amd_reset_method active_reset; - struct amdgpu_reset_handler *(*get_reset_handler)( - struct amdgpu_reset_control *reset_ctl, - struct amdgpu_reset_context *context); - void (*async_reset)(struct work_struct *work); -}; - enum amdgpu_reset_domain_type { SINGLE_DEVICE, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 0dc68fb9d88e..2740de94e93c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -75,6 +75,9 @@ static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, unsigned int type, uint64_t size_in_page) { + if (!size_in_page) + return 0; + return ttm_range_man_init(&adev->mman.bdev, type, false, size_in_page); } @@ -168,7 +171,7 @@ amdgpu_ttm_job_submit(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entit { struct amdgpu_ring *ring; - ring = adev->mman.buffer_funcs_ring; + ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); amdgpu_ring_pad_ib(ring, &job->ibs[0]); WARN_ON(job->ibs[0].length_dw > num_dw); @@ -417,8 +420,8 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo, if (old_mem->mem_type == TTM_PL_VRAM && (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { struct dma_fence *wipe_fence = NULL; - r = amdgpu_fill_buffer(entity, abo, 0, NULL, &wipe_fence, - AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); + r = amdgpu_ttm_clear_buffer(entity, abo, NULL, &wipe_fence, + false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); if (r) { goto error; } else if (wipe_fence) { @@ -1560,7 +1563,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, if (!adev->mman.sdma_access_ptr) return -EACCES; - if (!drm_dev_enter(adev_to_drm(adev), &idx)) + if (!adev->mman.buffer_funcs_enabled || !drm_dev_enter(adev_to_drm(adev), &idx)) return -ENODEV; if (write) @@ -1712,10 +1715,7 @@ static void amdgpu_ttm_init_fw_resv_region(struct amdgpu_device *adev) reserve_size = max(reserve_size, (uint32_t)280 << 20); else if (!adev->bios && amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) { - if (hweight32(adev->aid_mask) == 1) - reserve_size = max(reserve_size, (uint32_t)128 << 20); - else - reserve_size = max(reserve_size, (uint32_t)144 << 20); + reserve_size = max(reserve_size, (uint32_t)150 << 20); } else if (!reserve_size) reserve_size = DISCOVERY_TMR_OFFSET; @@ -2098,7 +2098,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) } /* Change the size here instead of the init above so only lpfn is affected */ - amdgpu_ttm_set_buffer_funcs_status(adev, false); + amdgpu_ttm_disable_buffer_funcs(adev); #ifdef CONFIG_64BIT #ifdef CONFIG_X86 if (adev->gmc.xgmi.connected_to_cpu) @@ -2278,115 +2278,92 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) } /** - * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions + * amdgpu_ttm_enable_buffer_funcs - enable use of buffer functions * * @adev: amdgpu_device pointer - * @enable: true when we can use buffer functions. * - * Enable/disable use of buffer functions during suspend/resume. This should + * Enable use of buffer functions during suspend/resume. This should * only be called at bootup or when userspace isn't running. */ -void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) +void amdgpu_ttm_enable_buffer_funcs(struct amdgpu_device *adev) { struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); u32 num_clear_entities, num_move_entities; - uint64_t size; int r, i, j; if (!adev->mman.initialized || amdgpu_in_reset(adev) || - adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu) + adev->mman.buffer_funcs_enabled || adev->gmc.is_app_apu) return; - if (enable) { - struct amdgpu_ring *ring; - struct drm_gpu_scheduler *sched; + if (!adev->mman.num_buffer_funcs_scheds) { + dev_warn(adev->dev, "Not enabling DMA transfers for in kernel use"); + return; + } - if (!adev->mman.buffer_funcs_ring || !adev->mman.buffer_funcs_ring->sched.ready) { - dev_warn(adev->dev, "Not enabling DMA transfers for in kernel use"); - return; - } + /* default_entity doesn't need multiple schedulers so pass only 1. */ + r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, + &adev->mman.default_entity, + DRM_SCHED_PRIORITY_KERNEL, + adev->mman.buffer_funcs_scheds, 1, 0); + if (r < 0) { + dev_err(adev->dev, + "Failed setting up TTM entity (%d)\n", r); + return; + } + + num_clear_entities = MIN(adev->mman.num_buffer_funcs_scheds, TTM_NUM_MOVE_FENCES); + num_move_entities = MIN(adev->mman.num_buffer_funcs_scheds, TTM_NUM_MOVE_FENCES); + + adev->mman.clear_entities = kcalloc(num_clear_entities, + sizeof(struct amdgpu_ttm_buffer_entity), + GFP_KERNEL); + atomic_set(&adev->mman.next_clear_entity, 0); + if (!adev->mman.clear_entities) + goto error_free_default_entity; + + adev->mman.num_clear_entities = num_clear_entities; + + for (i = 0; i < num_clear_entities; i++) { + r = amdgpu_ttm_buffer_entity_init( + &adev->mman.gtt_mgr, + &adev->mman.clear_entities[i], + DRM_SCHED_PRIORITY_KERNEL, + adev->mman.buffer_funcs_scheds, + adev->mman.num_buffer_funcs_scheds, 1); - num_clear_entities = 1; - num_move_entities = 1; - ring = adev->mman.buffer_funcs_ring; - sched = &ring->sched; - r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, - &adev->mman.default_entity, - DRM_SCHED_PRIORITY_KERNEL, - &sched, 1, 0); if (r < 0) { - dev_err(adev->dev, - "Failed setting up TTM entity (%d)\n", r); - return; - } - - adev->mman.clear_entities = kcalloc(num_clear_entities, - sizeof(struct amdgpu_ttm_buffer_entity), - GFP_KERNEL); - atomic_set(&adev->mman.next_clear_entity, 0); - if (!adev->mman.clear_entities) + for (j = 0; j < i; j++) + amdgpu_ttm_buffer_entity_fini( + &adev->mman.gtt_mgr, &adev->mman.clear_entities[j]); + adev->mman.num_clear_entities = 0; + kfree(adev->mman.clear_entities); goto error_free_default_entity; - - adev->mman.num_clear_entities = num_clear_entities; - - for (i = 0; i < num_clear_entities; i++) { - r = amdgpu_ttm_buffer_entity_init( - &adev->mman.gtt_mgr, &adev->mman.clear_entities[i], - DRM_SCHED_PRIORITY_NORMAL, &sched, 1, 1); - - if (r < 0) { - for (j = 0; j < i; j++) - amdgpu_ttm_buffer_entity_fini( - &adev->mman.gtt_mgr, &adev->mman.clear_entities[j]); - kfree(adev->mman.clear_entities); - adev->mman.num_clear_entities = 0; - adev->mman.clear_entities = NULL; - goto error_free_default_entity; - } } + } - adev->mman.num_move_entities = num_move_entities; - atomic_set(&adev->mman.next_move_entity, 0); - for (i = 0; i < num_move_entities; i++) { - r = amdgpu_ttm_buffer_entity_init( - &adev->mman.gtt_mgr, - &adev->mman.move_entities[i], - DRM_SCHED_PRIORITY_NORMAL, &sched, 1, 2); + adev->mman.num_move_entities = num_move_entities; + atomic_set(&adev->mman.next_move_entity, 0); + for (i = 0; i < num_move_entities; i++) { + r = amdgpu_ttm_buffer_entity_init( + &adev->mman.gtt_mgr, + &adev->mman.move_entities[i], + DRM_SCHED_PRIORITY_KERNEL, + adev->mman.buffer_funcs_scheds, + adev->mman.num_buffer_funcs_scheds, 2); - if (r < 0) { - for (j = 0; j < i; j++) - amdgpu_ttm_buffer_entity_fini( - &adev->mman.gtt_mgr, &adev->mman.move_entities[j]); - adev->mman.num_move_entities = 0; - goto error_free_clear_entities; - } + if (r < 0) { + for (j = 0; j < i; j++) + amdgpu_ttm_buffer_entity_fini( + &adev->mman.gtt_mgr, + &adev->mman.move_entities[j]); + adev->mman.num_move_entities = 0; + goto error_free_clear_entities; } - } else { - amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, - &adev->mman.default_entity); - for (i = 0; i < adev->mman.num_clear_entities; i++) - amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, - &adev->mman.clear_entities[i]); - for (i = 0; i < adev->mman.num_move_entities; i++) - amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, - &adev->mman.move_entities[i]); - /* Drop all the old fences since re-creating the scheduler entities - * will allocate new contexts. - */ - ttm_resource_manager_cleanup(man); - kfree(adev->mman.clear_entities); - adev->mman.clear_entities = NULL; - adev->mman.num_clear_entities = 0; - adev->mman.num_move_entities = 0; } /* this just adjusts TTM size idea, which sets lpfn to the correct value */ - if (enable) - size = adev->gmc.real_vram_size; - else - size = adev->gmc.visible_vram_size; - man->size = size; - adev->mman.buffer_funcs_enabled = enable; + man->size = adev->gmc.real_vram_size; + adev->mman.buffer_funcs_enabled = true; return; @@ -2402,6 +2379,42 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) &adev->mman.default_entity); } +/** + * amdgpu_ttm_disable_buffer_funcs - disable use of buffer functions + * + * @adev: amdgpu_device pointer + */ +void amdgpu_ttm_disable_buffer_funcs(struct amdgpu_device *adev) +{ + struct ttm_resource_manager *man = + ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); + int i; + + if (!adev->mman.buffer_funcs_enabled || amdgpu_in_reset(adev)) + return; + + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.default_entity); + for (i = 0; i < adev->mman.num_move_entities; i++) + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.move_entities[i]); + for (i = 0; i < adev->mman.num_clear_entities; i++) + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.clear_entities[i]); + /* Drop all the old fences since re-creating the scheduler entities + * will allocate new contexts. + */ + ttm_resource_manager_cleanup(man); + + kfree(adev->mman.clear_entities); + adev->mman.clear_entities = NULL; + adev->mman.num_clear_entities = 0; + adev->mman.num_move_entities = 0; + + man->size = adev->gmc.visible_vram_size; + adev->mman.buffer_funcs_enabled = false; +} + static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entity *entity, unsigned int num_dw, @@ -2446,7 +2459,7 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, unsigned int i; int r; - ring = adev->mman.buffer_funcs_ring; + ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); if (!ring->sched.ready) { dev_err(adev->dev, @@ -2521,77 +2534,23 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_device *adev, } /** - * amdgpu_ttm_clear_buffer - clear memory buffers - * @bo: amdgpu buffer object - * @resv: reservation object - * @fence: dma_fence associated with the operation + * amdgpu_ttm_clear_buffer - fill a buffer with 0 + * @entity: entity to use + * @bo: the bo to fill + * @resv: fences contained in this reservation will be used as dependencies. + * @out_fence: the fence from the last clear will be stored here. It might be + * NULL if no job was run. + * @consider_clear_status: true if region reported as cleared by amdgpu_res_cleared() + * are skipped. + * @k_job_id: trace id * - * Clear the memory buffer resource. - * - * Returns: - * 0 for success or a negative error code on failure. */ -int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, +int amdgpu_ttm_clear_buffer(struct amdgpu_ttm_buffer_entity *entity, + struct amdgpu_bo *bo, struct dma_resv *resv, - struct dma_fence **fence) -{ - struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - struct amdgpu_ttm_buffer_entity *entity; - struct amdgpu_res_cursor cursor; - u64 addr; - int r = 0; - - if (!adev->mman.buffer_funcs_enabled) - return -EINVAL; - - if (!fence) - return -EINVAL; - entity = &adev->mman.clear_entities[0]; - *fence = dma_fence_get_stub(); - - amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor); - - mutex_lock(&entity->lock); - while (cursor.remaining) { - struct dma_fence *next = NULL; - u64 size; - - if (amdgpu_res_cleared(&cursor)) { - amdgpu_res_next(&cursor, cursor.size); - continue; - } - - /* Never clear more than 256MiB at once to avoid timeouts */ - size = min(cursor.size, 256ULL << 20); - - r = amdgpu_ttm_map_buffer(entity, &bo->tbo, bo->tbo.resource, &cursor, - 0, false, &size, &addr); - if (r) - goto err; - - r = amdgpu_ttm_fill_mem(adev, entity, 0, addr, size, resv, - &next, true, - AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); - if (r) - goto err; - - dma_fence_put(*fence); - *fence = next; - - amdgpu_res_next(&cursor, size); - } -err: - mutex_unlock(&entity->lock); - - return r; -} - -int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, - struct amdgpu_bo *bo, - uint32_t src_data, - struct dma_resv *resv, - struct dma_fence **f, - u64 k_job_id) + struct dma_fence **out_fence, + bool consider_clear_status, + u64 k_job_id) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); struct dma_fence *fence = NULL; @@ -2608,6 +2567,11 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, struct dma_fence *next; uint64_t cur_size, to; + if (consider_clear_status && amdgpu_res_cleared(&dst)) { + amdgpu_res_next(&dst, dst.size); + continue; + } + /* Never fill more than 256MiB at once to avoid timeouts */ cur_size = min(dst.size, 256ULL << 20); @@ -2617,7 +2581,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, goto error; r = amdgpu_ttm_fill_mem(adev, entity, - src_data, to, cur_size, resv, + 0, to, cur_size, resv, &next, true, k_job_id); if (r) goto error; @@ -2629,9 +2593,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, } error: mutex_unlock(&entity->lock); - if (f) - *f = dma_fence_get(fence); - dma_fence_put(fence); + *out_fence = fence; return r; } @@ -2679,6 +2641,41 @@ int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type) return ttm_resource_manager_evict_all(&adev->mman.bdev, man); } +void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev, + const struct amdgpu_buffer_funcs *buffer_funcs) +{ + struct drm_gpu_scheduler *sched; + struct amdgpu_vmhub *hub; + int i, n; + + adev->mman.buffer_funcs = buffer_funcs; + + for (i = 0, n = 0; i < adev->sdma.num_instances; i++) { + if (adev->sdma.has_page_queue) + sched = &adev->sdma.instance[i].page.sched; + else + sched = &adev->sdma.instance[i].ring.sched; + + if (!sched->ready) + continue; + + adev->mman.buffer_funcs_scheds[n++] = sched; + } + + if (n == 0) { + adev->mman.num_buffer_funcs_scheds = 0; + drm_warn(&adev->ddev, "No working sdma ring available\n"); + return; + } + + /* Navi1x's workaround requires us to limit to a single SDMA sched + * for ttm. + */ + hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; + adev->mman.num_buffer_funcs_scheds = hub->sdma_invalidation_workaround ? + 1 : n; +} + #if defined(CONFIG_DEBUG_FS) static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index f2f23a42b3cc..2d72fa217274 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -87,7 +87,8 @@ struct amdgpu_mman { /* buffer handling */ const struct amdgpu_buffer_funcs *buffer_funcs; - struct amdgpu_ring *buffer_funcs_ring; + struct drm_gpu_scheduler *buffer_funcs_scheds[AMDGPU_MAX_RINGS]; + u32 num_buffer_funcs_scheds; bool buffer_funcs_enabled; /* @default_entity: for workarounds, has no gart windows */ @@ -184,8 +185,8 @@ void amdgpu_ttm_unmark_vram_reserved(struct amdgpu_device *adev, int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); -void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, - bool enable); +void amdgpu_ttm_enable_buffer_funcs(struct amdgpu_device *adev); +void amdgpu_ttm_disable_buffer_funcs(struct amdgpu_device *adev); int amdgpu_copy_buffer(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entity *entity, uint64_t src_offset, @@ -193,15 +194,12 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, struct dma_resv *resv, struct dma_fence **fence, bool vm_needs_flush, uint32_t copy_flags); -int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, +int amdgpu_ttm_clear_buffer(struct amdgpu_ttm_buffer_entity *entity, + struct amdgpu_bo *bo, struct dma_resv *resv, - struct dma_fence **fence); -int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, - struct amdgpu_bo *bo, - uint32_t src_data, - struct dma_resv *resv, - struct dma_fence **f, - u64 k_job_id); + struct dma_fence **out_fence, + bool consider_clear_status, + u64 k_job_id); struct amdgpu_ttm_buffer_entity *amdgpu_ttm_next_clear_entity(struct amdgpu_device *adev); int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index d5abf785ca17..de140a8ed135 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -205,6 +205,19 @@ void amdgpu_userq_start_hang_detect_work(struct amdgpu_usermode_queue *queue) msecs_to_jiffies(timeout_ms)); } +void amdgpu_userq_process_fence_irq(struct amdgpu_device *adev, u32 doorbell) +{ + struct xarray *xa = &adev->userq_doorbell_xa; + struct amdgpu_usermode_queue *queue; + unsigned long flags; + + xa_lock_irqsave(xa, flags); + queue = xa_load(xa, doorbell); + if (queue) + amdgpu_userq_fence_driver_process(queue->fence_drv); + xa_unlock_irqrestore(xa, flags); +} + static void amdgpu_userq_init_hang_detect_work(struct amdgpu_usermode_queue *queue) { INIT_DELAYED_WORK(&queue->hang_detect_work, amdgpu_userq_hang_detect_work); @@ -643,12 +656,6 @@ amdgpu_userq_destroy(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_que #endif amdgpu_userq_detect_and_reset_queues(uq_mgr); r = amdgpu_userq_unmap_helper(queue); - /*TODO: It requires a reset for userq hw unmap error*/ - if (r) { - drm_warn(adev_to_drm(uq_mgr->adev), "trying to destroy a HW mapping userq\n"); - queue->state = AMDGPU_USERQ_STATE_HUNG; - } - atomic_dec(&uq_mgr->userq_count[queue->queue_type]); amdgpu_userq_cleanup(queue); mutex_unlock(&uq_mgr->userq_mutex); @@ -1187,7 +1194,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) bo = range->bo; ret = amdgpu_ttm_tt_get_user_pages(bo, range); if (ret) - goto unlock_all; + goto free_ranges; } invalidated = true; @@ -1214,6 +1221,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) unlock_all: drm_exec_fini(&exec); +free_ranges: xa_for_each(&xa, tmp_key, range) { if (!range) continue; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index 675fe6395ac8..8b8f345b60b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -156,6 +156,7 @@ void amdgpu_userq_reset_work(struct work_struct *work); void amdgpu_userq_pre_reset(struct amdgpu_device *adev); int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost); void amdgpu_userq_start_hang_detect_work(struct amdgpu_usermode_queue *queue); +void amdgpu_userq_process_fence_irq(struct amdgpu_device *adev, u32 doorbell); int amdgpu_userq_input_va_validate(struct amdgpu_device *adev, struct amdgpu_usermode_queue *queue, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index da39ac862f37..e2d5f04296e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -32,29 +32,9 @@ #include "amdgpu.h" #include "amdgpu_userq_fence.h" -static const struct dma_fence_ops amdgpu_userq_fence_ops; -static struct kmem_cache *amdgpu_userq_fence_slab; - #define AMDGPU_USERQ_MAX_HANDLES (1U << 16) -int amdgpu_userq_fence_slab_init(void) -{ - amdgpu_userq_fence_slab = kmem_cache_create("amdgpu_userq_fence", - sizeof(struct amdgpu_userq_fence), - 0, - SLAB_HWCACHE_ALIGN, - NULL); - if (!amdgpu_userq_fence_slab) - return -ENOMEM; - - return 0; -} - -void amdgpu_userq_fence_slab_fini(void) -{ - rcu_barrier(); - kmem_cache_destroy(amdgpu_userq_fence_slab); -} +static const struct dma_fence_ops amdgpu_userq_fence_ops; static inline struct amdgpu_userq_fence *to_amdgpu_userq_fence(struct dma_fence *f) { @@ -231,7 +211,7 @@ void amdgpu_userq_fence_driver_put(struct amdgpu_userq_fence_driver *fence_drv) static int amdgpu_userq_fence_alloc(struct amdgpu_userq_fence **userq_fence) { - *userq_fence = kmem_cache_alloc(amdgpu_userq_fence_slab, GFP_ATOMIC); + *userq_fence = kmalloc(sizeof(**userq_fence), GFP_KERNEL); return *userq_fence ? 0 : -ENOMEM; } @@ -342,7 +322,7 @@ static void amdgpu_userq_fence_free(struct rcu_head *rcu) amdgpu_userq_fence_driver_put(fence_drv); kvfree(userq_fence->fence_drv_array); - kmem_cache_free(amdgpu_userq_fence_slab, userq_fence); + kfree(userq_fence); } static void amdgpu_userq_fence_release(struct dma_fence *f) @@ -545,7 +525,7 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, r = amdgpu_userq_fence_create(queue, userq_fence, wptr, &fence); if (r) { mutex_unlock(&userq_mgr->userq_mutex); - kmem_cache_free(amdgpu_userq_fence_slab, userq_fence); + kfree(userq_fence); goto put_gobj_write; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h index d56246ad8c26..d355a0eecc07 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h @@ -58,9 +58,6 @@ struct amdgpu_userq_fence_driver { char timeline_name[TASK_COMM_LEN]; }; -int amdgpu_userq_fence_slab_init(void); -void amdgpu_userq_fence_slab_fini(void); - void amdgpu_userq_fence_driver_get(struct amdgpu_userq_fence_driver *fence_drv); void amdgpu_userq_fence_driver_put(struct amdgpu_userq_fence_driver *fence_drv); int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index e54295b56282..170adaf7e76a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -5,6 +5,7 @@ #include #include #include +#include #include "amdgpu.h" #ifdef CONFIG_DRM_AMDGPU_SI @@ -42,81 +43,6 @@ static const u32 amdgpu_vkms_formats[] = { DRM_FORMAT_XRGB8888, }; -static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer) -{ - struct amdgpu_crtc *amdgpu_crtc = container_of(timer, struct amdgpu_crtc, vblank_timer); - struct drm_crtc *crtc = &amdgpu_crtc->base; - struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc); - u64 ret_overrun; - bool ret; - - ret_overrun = hrtimer_forward_now(&amdgpu_crtc->vblank_timer, - output->period_ns); - if (ret_overrun != 1) - drm_warn(amdgpu_crtc->base.dev, - "%s: vblank timer overrun count: %llu\n", - __func__, ret_overrun); - - ret = drm_crtc_handle_vblank(crtc); - /* Don't queue timer again when vblank is disabled. */ - if (!ret) - return HRTIMER_NORESTART; - - return HRTIMER_RESTART; -} - -static int amdgpu_vkms_enable_vblank(struct drm_crtc *crtc) -{ - struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); - struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc); - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - - drm_calc_timestamping_constants(crtc, &crtc->mode); - - out->period_ns = ktime_set(0, vblank->framedur_ns); - hrtimer_start(&amdgpu_crtc->vblank_timer, out->period_ns, HRTIMER_MODE_REL); - - return 0; -} - -static void amdgpu_vkms_disable_vblank(struct drm_crtc *crtc) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - - hrtimer_try_to_cancel(&amdgpu_crtc->vblank_timer); -} - -static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, - int *max_error, - ktime_t *vblank_time, - bool in_vblank_irq) -{ - struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc); - struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - - if (!READ_ONCE(vblank->enabled)) { - *vblank_time = ktime_get(); - return true; - } - - *vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires); - - if (WARN_ON(*vblank_time == vblank->time)) - return true; - - /* - * To prevent races we roll the hrtimer forward before we do any - * interrupt processing - this is how real hw works (the interrupt is - * only generated after all the vblank registers are updated) and what - * the vblank core expects. Therefore we need to always correct the - * timestampe by one frame. - */ - *vblank_time -= output->period_ns; - - return true; -} - static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = { .set_config = drm_atomic_helper_set_config, .destroy = drm_crtc_cleanup, @@ -124,45 +50,11 @@ static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = { .reset = drm_atomic_helper_crtc_reset, .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, - .enable_vblank = amdgpu_vkms_enable_vblank, - .disable_vblank = amdgpu_vkms_disable_vblank, - .get_vblank_timestamp = amdgpu_vkms_get_vblank_timestamp, + DRM_CRTC_VBLANK_TIMER_FUNCS, }; -static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - drm_crtc_vblank_on(crtc); -} - -static void amdgpu_vkms_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - drm_crtc_vblank_off(crtc); -} - -static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - unsigned long flags; - if (crtc->state->event) { - spin_lock_irqsave(&crtc->dev->event_lock, flags); - - if (drm_crtc_vblank_get(crtc) != 0) - drm_crtc_send_vblank_event(crtc, crtc->state->event); - else - drm_crtc_arm_vblank_event(crtc, crtc->state->event); - - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - - crtc->state->event = NULL; - } -} - static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { - .atomic_flush = amdgpu_vkms_crtc_atomic_flush, - .atomic_enable = amdgpu_vkms_crtc_atomic_enable, - .atomic_disable = amdgpu_vkms_crtc_atomic_disable, + DRM_CRTC_HELPER_VBLANK_FUNCS, }; static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, @@ -187,10 +79,6 @@ static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; amdgpu_crtc->encoder = NULL; amdgpu_crtc->connector = NULL; - amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE; - - hrtimer_setup(&amdgpu_crtc->vblank_timer, &amdgpu_vkms_vblank_simulate, CLOCK_MONOTONIC, - HRTIMER_MODE_REL); return ret; } @@ -262,13 +150,13 @@ static const struct drm_plane_funcs amdgpu_vkms_plane_funcs = { }; static void amdgpu_vkms_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { return; } static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -538,11 +426,6 @@ static int amdgpu_vkms_sw_init(struct amdgpu_ip_block *ip_block) static int amdgpu_vkms_sw_fini(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - int i = 0; - - for (i = 0; i < adev->mode_info.num_crtc; i++) - if (adev->mode_info.crtcs[i]) - hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer); drm_kms_helper_poll_fini(adev_to_drm(adev)); drm_mode_config_cleanup(adev_to_drm(adev)); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 115a7b269af3..2f2ac3c4c2f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1163,7 +1163,7 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, params.pages_addr = pages_addr; params.unlocked = unlocked; params.needs_flush = flush_tlb; - params.allow_override = allow_override; + params.override_pte = allow_override && adev->gmc.override_pte; INIT_LIST_HEAD(¶ms.tlb_flush_waitlist); amdgpu_vm_eviction_lock(vm); @@ -3023,11 +3023,22 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, is_compute_context = vm->is_compute_context; - if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid, - node_id, addr >> PAGE_SHIFT, ts, write_fault)) { + if (is_compute_context) { + /* Unreserve root since svm_range_restore_pages might try to reserve it. */ + /* TODO: rework svm_range_restore_pages so that this isn't necessary. */ amdgpu_bo_unreserve(root); + + if (!svm_range_restore_pages(adev, pasid, vmid, + node_id, addr >> PAGE_SHIFT, ts, write_fault)) { + amdgpu_bo_unref(&root); + return true; + } amdgpu_bo_unref(&root); - return true; + + /* Re-acquire the VM lock, could be that the VM was freed in between. */ + vm = amdgpu_vm_lock_by_pasid(adev, &root, pasid); + if (!vm) + return false; } addr /= AMDGPU_GPU_PAGE_SIZE; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index d083d7aab75c..f4b0e9da3fa2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -296,10 +296,10 @@ struct amdgpu_vm_update_params { bool needs_flush; /** - * @allow_override: true for memory that is not uncached: allows MTYPE - * to be overridden for NUMA local memory. + * @override_pte: true for memory that is not uncached and gmc override function is + * implemented to allow MTYPE to be overridden for NUMA local memory. */ - bool allow_override; + bool override_pte; /** * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c index f078db3fef79..b31ff6f56f0d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c @@ -88,12 +88,21 @@ static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p, trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate); + if (!p->pages_addr && p->override_pte) + amdgpu_gmc_override_vm_pte_flags(p->adev, p->vm, addr, &flags); + for (i = 0; i < count; i++) { + u64 oflags = flags; + value = p->pages_addr ? amdgpu_vm_map_gart(p->pages_addr, addr) : addr; + + if (p->pages_addr && p->override_pte) + amdgpu_gmc_override_vm_pte_flags(p->adev, p->vm, value, &oflags); + amdgpu_gmc_set_pte_pde(p->adev, (void *)(uintptr_t)pe, - i, value, flags); + i, value, oflags); addr += incr; } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index a930f1522f96..b2494381b98a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c @@ -710,15 +710,6 @@ static void amdgpu_vm_pte_update_flags(struct amdgpu_vm_update_params *params, if (level == AMDGPU_VM_PTB) amdgpu_vm_pte_update_noretry_flags(adev, &flags); - /* APUs mapping system memory may need different MTYPEs on different - * NUMA nodes. Only do this for contiguous ranges that can be assumed - * to be on the same NUMA node. - */ - if ((flags & AMDGPU_PTE_SYSTEM) && (adev->flags & AMD_IS_APU) && - adev->gmc.gmc_funcs->override_vm_pte_flags && - num_possible_nodes() > 1 && !params->pages_addr && params->allow_override) - amdgpu_gmc_override_vm_pte_flags(adev, params->vm, addr, &flags); - params->vm->update_funcs->update(params, pt, pe, addr, count, incr, flags); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 4ccd2e769799..fd09a2b5a147 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -257,6 +257,9 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, } if (!p->pages_addr) { + if (p->override_pte) + amdgpu_gmc_override_vm_pte_flags(p->adev, p->vm, addr, &flags); + /* set page commands needed */ amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count, incr, flags); @@ -275,8 +278,14 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, p->num_dw_left -= nptes * 2; pte = (uint64_t *)&(p->job->ibs->ptr[p->num_dw_left]); for (i = 0; i < nptes; ++i, addr += incr) { + u64 oflags = flags; + pte[i] = amdgpu_vm_map_gart(p->pages_addr, addr); - pte[i] |= flags; + + if (p->override_pte) + amdgpu_gmc_override_vm_pte_flags(p->adev, p->vm, pte[i], &oflags); + + pte[i] |= oflags; } amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes); diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 22780c09177d..120da838ac28 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -939,7 +939,6 @@ static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block) cik_sdma_set_ring_funcs(adev); cik_sdma_set_irq_funcs(adev); - cik_sdma_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &cik_sdma_vm_pte_funcs); return 0; @@ -1000,8 +999,15 @@ static int cik_sdma_sw_fini(struct amdgpu_ip_block *ip_block) static int cik_sdma_hw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + int r; - return cik_sdma_start(adev); + r = cik_sdma_start(adev); + if (r) + return r; + + cik_sdma_set_buffer_funcs(adev); + + return 0; } static int cik_sdma_hw_fini(struct amdgpu_ip_block *ip_block) @@ -1340,8 +1346,7 @@ static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &cik_sdma_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &cik_sdma_buffer_funcs); } const struct amdgpu_ip_block_version cik_sdma_ip_block = diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 8b60299b73ef..58c69dcb527f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7011,6 +7011,11 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); mqd->cp_hqd_ib_control = tmp; + tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); + mqd->cp_hqd_quantum = tmp; + /* set static priority for a compute queue/ring */ mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 8c82e90f871b..fabdbbd0abb7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4417,6 +4417,11 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; + tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); + mqd->cp_hqd_quantum = tmp; + mqd->cp_hqd_active = prop->hqd_active; /* set UQ fenceaddress */ @@ -5219,7 +5224,7 @@ static int gfx_v11_0_post_soft_reset(struct amdgpu_ip_block *ip_block) /** * GFX soft reset will impact MES, need resume MES when do GFX soft reset */ - return amdgpu_mes_resume(adev); + return amdgpu_mes_resume(adev, 0); } static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) @@ -6227,56 +6232,6 @@ static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring, ring->set_q_mode_offs = offs; } -static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) -{ - int i, r = 0; - struct amdgpu_device *adev = ring->adev; - struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; - struct amdgpu_ring *kiq_ring = &kiq->ring; - unsigned long flags; - - if (adev->enable_mes) - return -EINVAL; - - if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) - return -EINVAL; - - spin_lock_irqsave(&kiq->ring_lock, flags); - - if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { - spin_unlock_irqrestore(&kiq->ring_lock, flags); - return -ENOMEM; - } - - /* assert preemption condition */ - amdgpu_ring_set_preempt_cond_exec(ring, false); - - /* assert IB preemption, emit the trailing fence */ - kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, - ring->trail_fence_gpu_addr, - ++ring->trail_seq); - amdgpu_ring_commit(kiq_ring); - - spin_unlock_irqrestore(&kiq->ring_lock, flags); - - /* poll the trailing fence */ - for (i = 0; i < adev->usec_timeout; i++) { - if (ring->trail_seq == - le32_to_cpu(*(ring->trail_fence_cpu_addr))) - break; - udelay(1); - } - - if (i >= adev->usec_timeout) { - r = -EINVAL; - DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); - } - - /* deassert preemption condition */ - amdgpu_ring_set_preempt_cond_exec(ring, true); - return r; -} - static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) { struct amdgpu_device *adev = ring->adev; @@ -6523,15 +6478,7 @@ static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, DRM_DEBUG("IH: CP EOP\n"); if (adev->enable_mes && doorbell_offset) { - struct amdgpu_usermode_queue *queue; - struct xarray *xa = &adev->userq_doorbell_xa; - unsigned long flags; - - xa_lock_irqsave(xa, flags); - queue = xa_load(xa, doorbell_offset); - if (queue) - amdgpu_userq_fence_driver_process(queue->fence_drv); - xa_unlock_irqrestore(xa, flags); + amdgpu_userq_process_fence_irq(adev, doorbell_offset); } else { me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; @@ -7316,7 +7263,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow, .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, - .preempt_ib = gfx_v11_0_ring_preempt_ib, + .preempt_ib = amdgpu_gfx_ring_preempt_ib, .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, .emit_wreg = gfx_v11_0_ring_emit_wreg, .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 65c33823a688..b866a944f878 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3268,6 +3268,11 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; + tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); + mqd->cp_hqd_quantum = tmp; + mqd->cp_hqd_active = prop->hqd_active; /* set UQ fenceaddress */ @@ -4611,56 +4616,6 @@ static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, return ret; } -static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) -{ - int i, r = 0; - struct amdgpu_device *adev = ring->adev; - struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; - struct amdgpu_ring *kiq_ring = &kiq->ring; - unsigned long flags; - - if (adev->enable_mes) - return -EINVAL; - - if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) - return -EINVAL; - - spin_lock_irqsave(&kiq->ring_lock, flags); - - if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { - spin_unlock_irqrestore(&kiq->ring_lock, flags); - return -ENOMEM; - } - - /* assert preemption condition */ - amdgpu_ring_set_preempt_cond_exec(ring, false); - - /* assert IB preemption, emit the trailing fence */ - kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, - ring->trail_fence_gpu_addr, - ++ring->trail_seq); - amdgpu_ring_commit(kiq_ring); - - spin_unlock_irqrestore(&kiq->ring_lock, flags); - - /* poll the trailing fence */ - for (i = 0; i < adev->usec_timeout; i++) { - if (ring->trail_seq == - le32_to_cpu(*(ring->trail_fence_cpu_addr))) - break; - udelay(1); - } - - if (i >= adev->usec_timeout) { - r = -EINVAL; - DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); - } - - /* deassert preemption condition */ - amdgpu_ring_set_preempt_cond_exec(ring, true); - return r; -} - static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t reg_val_offs) { @@ -4854,15 +4809,7 @@ static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, DRM_DEBUG("IH: CP EOP\n"); if (adev->enable_mes && doorbell_offset) { - struct xarray *xa = &adev->userq_doorbell_xa; - struct amdgpu_usermode_queue *queue; - unsigned long flags; - - xa_lock_irqsave(xa, flags); - queue = xa_load(xa, doorbell_offset); - if (queue) - amdgpu_userq_fence_driver_process(queue->fence_drv); - xa_unlock_irqrestore(xa, flags); + amdgpu_userq_process_fence_irq(adev, doorbell_offset); } else { me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; @@ -5539,7 +5486,7 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { .pad_ib = amdgpu_ring_generic_pad_ib, .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, - .preempt_ib = gfx_v12_0_ring_preempt_ib, + .preempt_ib = amdgpu_gfx_ring_preempt_ib, .emit_wreg = gfx_v12_0_ring_emit_wreg, .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 68fd3c04134d..033f15e21ad3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -61,7 +61,7 @@ #define regCP_HQD_IB_CONTROL_DEFAULT 0x00100000 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mec.bin"); -MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc.bin"); +MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc_1.bin"); #define SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 0x00000001 #define DEFAULT_SH_MEM_CONFIG \ @@ -243,9 +243,9 @@ static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); amdgpu_ring_write(ring, /* memory (1) or register (0) */ - (WAIT_REG_MEM_MEM_SPACE(mem_space) | - WAIT_REG_MEM_OPERATION(opt) | /* wait */ - WAIT_REG_MEM_FUNCTION(3))); /* equal */ + (PACKET3_WAIT_REG_MEM__MEM_SPACE(mem_space) | + PACKET3_WAIT_REG_MEM__OPERATION(opt) | /* wait */ + PACKET3_WAIT_REG_MEM__FUNCTION(3))); /* equal */ if (mem_space) BUG_ON(addr0 & 0x3); /* Dword align */ @@ -335,7 +335,7 @@ static int gfx_v12_1_ring_test_ib(struct amdgpu_ring *ring, long timeout) } ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); - ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; + ib.ptr[1] = PACKET3_WRITE_DATA__DST_SEL(5) | PACKET3_WRITE_DATA__WR_CONFIRM(1); ib.ptr[2] = lower_32_bits(gpu_addr); ib.ptr[3] = upper_32_bits(gpu_addr); ib.ptr[4] = 0xDEADBEEF; @@ -409,7 +409,13 @@ static int gfx_v12_1_init_microcode(struct amdgpu_device *adev) amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); if (!amdgpu_sriov_vf(adev)) { - err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0) && + adev->rev_id == 0) + err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, + AMDGPU_UCODE_REQUIRED, + "amdgpu/%s_rlc_1.bin", ucode_prefix); + else + err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, AMDGPU_UCODE_REQUIRED, "amdgpu/%s_rlc.bin", ucode_prefix); if (err) @@ -712,10 +718,19 @@ static void gfx_v12_1_select_me_pipe_q(struct amdgpu_device *adev, soc_v1_0_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); } +#define regGFX_IMU_PARTITION_SWITCH 0x5f8c +#define regGFX_IMU_PARTITION_SWITCH_BASE_IDX 1 +#define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP__SHIFT 0x2 +#define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP_MASK 0x0000003CL + static int gfx_v12_1_get_xccs_per_xcp(struct amdgpu_device *adev) { - /* Fill this in when the interface is ready */ - return 1; + u32 reg_data; + + /* the register data is expected to be the same on all instances */ + reg_data = RREG32_SOC15(GC, GET_INST(GC, 0), regGFX_IMU_PARTITION_SWITCH); + + return REG_GET_FIELD(reg_data, GFX_IMU_PARTITION_SWITCH, TOTAL_XCCS_IN_XCP); } static int gfx_v12_1_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) @@ -1136,6 +1151,7 @@ static int gfx_v12_1_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block) { + uint16_t major_ver, minor_ver; int i, j, k, r, ring_id = 0; unsigned num_compute_rings; int xcc_id, num_xcc; @@ -1146,6 +1162,15 @@ static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block) adev->gfx.mec.num_mec = 1; adev->gfx.mec.num_pipe_per_mec = 4; adev->gfx.mec.num_queue_per_pipe = 8; + + if (!amdgpu_discovery_get_gc_major_minor_version( + adev, &major_ver, &minor_ver)) { + if (major_ver == 1 && minor_ver == 3) { + adev->gfx.config.max_cu_per_sh /= 2; + dev_dbg(adev->dev, "Halving max_cu_per_sh for GC Discovery table v1:3 %d\n", + adev->gfx.config.max_cu_per_sh); + } + } break; default: adev->gfx.mec.num_mec = 2; @@ -1450,6 +1475,19 @@ static void gfx_v12_1_get_tcc_info(struct amdgpu_device *adev) { } +static void gfx_v12_1_xcc_xnack_set_chicken_bits(struct amdgpu_device *adev, int xcc_id) +{ + /* NOTE: COMPRESSION_ENABLE is used a chicken bit to enable/disable xcc xnack */ + mutex_lock(&adev->srbm_mutex); + if (!adev->gmc.noretry) { + WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), + TCP_PERFCOUNTER_FILTER, COMPRESSION_ENABLE, 0x1); + } else + WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), + TCP_PERFCOUNTER_FILTER, COMPRESSION_ENABLE, 0x0); + mutex_unlock(&adev->srbm_mutex); +} + static void gfx_v12_1_xcc_constants_init(struct amdgpu_device *adev, int xcc_id) { @@ -1477,6 +1515,8 @@ static void gfx_v12_1_xcc_constants_init(struct amdgpu_device *adev, mutex_unlock(&adev->srbm_mutex); gfx_v12_1_xcc_init_compute_vmid(adev, xcc_id); + gfx_v12_1_xcc_xnack_set_chicken_bits(adev, xcc_id); + } static void gfx_v12_1_constants_init(struct amdgpu_device *adev) @@ -2246,6 +2286,11 @@ static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m, mqd->cp_mqd_stride_size = prop->mqd_stride_size ? prop->mqd_stride_size : AMDGPU_MQD_SIZE_ALIGN(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size); + tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); + mqd->cp_hqd_quantum = tmp; + mqd->cp_hqd_active = prop->hqd_active; return 0; @@ -3355,7 +3400,7 @@ static void gfx_v12_1_ring_emit_ib_compute(struct amdgpu_ring *ring, uint32_t flags) { unsigned vmid = AMDGPU_JOB_GET_VMID(job); - u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); + u32 control = PACKET3_INDIRECT_BUFFER__VALID(1) | ib->length_dw | (vmid << 24); /* Currently, there is a high possibility to get wave ID mismatch * between ME and GDS, leading to a hw deadlock, because ME generates @@ -3391,15 +3436,15 @@ static void gfx_v12_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, /* RELEASE_MEM - flush caches, send int */ amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); - amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ(1) | - PACKET3_RELEASE_MEM_GCR_GLV_WB | - PACKET3_RELEASE_MEM_GCR_GL2_WB | - PACKET3_RELEASE_MEM_GCR_GL2_SCOPE(2) | - PACKET3_RELEASE_MEM_TEMPORAL(3) | - PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | - PACKET3_RELEASE_MEM_EVENT_INDEX(5))); - amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | - PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); + amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM__GCR_SEQ(1) | + PACKET3_RELEASE_MEM__GCR_GLV_WB | + PACKET3_RELEASE_MEM__GCR_GL2_WB | + PACKET3_RELEASE_MEM__GCR_GL2_SCOPE(2) | + PACKET3_RELEASE_MEM__TEMPORAL(3) | + PACKET3_RELEASE_MEM__EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | + PACKET3_RELEASE_MEM__EVENT_INDEX(5))); + amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM__DATA_SEL(write64bit ? 2 : 1) | + PACKET3_RELEASE_MEM__INT_SEL(int_sel ? 2 : 0))); /* * the address should be Qword aligned if 64bit write, Dword @@ -3460,7 +3505,7 @@ static void gfx_v12_1_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, /* write fence seq to the "addr" */ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); - amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); + amdgpu_ring_write(ring, (PACKET3_WRITE_DATA__DST_SEL(5) | PACKET3_WRITE_DATA__WR_CONFIRM(1))); amdgpu_ring_write(ring, lower_32_bits(addr)); amdgpu_ring_write(ring, upper_32_bits(addr)); amdgpu_ring_write(ring, lower_32_bits(seq)); @@ -3468,7 +3513,7 @@ static void gfx_v12_1_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, if (flags & AMDGPU_FENCE_FLAG_INT) { /* set register to trigger INT */ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); - amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); + amdgpu_ring_write(ring, (PACKET3_WRITE_DATA__DST_SEL(0) | PACKET3_WRITE_DATA__WR_CONFIRM(1))); amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ @@ -3507,7 +3552,7 @@ static void gfx_v12_1_ring_emit_wreg(struct amdgpu_ring *ring, cmd = (1 << 16); /* no inc addr */ break; default: - cmd = WR_CONFIRM; + cmd = PACKET3_WRITE_DATA__WR_CONFIRM(1); break; } amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); @@ -3643,16 +3688,7 @@ static int gfx_v12_1_eop_irq(struct amdgpu_device *adev, DRM_DEBUG("IH: CP EOP\n"); if (adev->enable_mes && doorbell_offset) { - struct xarray *xa = &adev->userq_doorbell_xa; - struct amdgpu_usermode_queue *queue; - unsigned long flags; - - xa_lock_irqsave(xa, flags); - queue = xa_load(xa, doorbell_offset); - if (queue) - amdgpu_userq_fence_driver_process(queue->fence_drv); - - xa_unlock_irqrestore(xa, flags); + amdgpu_userq_process_fence_irq(adev, doorbell_offset); } else { me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; @@ -3819,12 +3855,12 @@ static int gfx_v12_1_rlc_poison_irq(struct amdgpu_device *adev, static void gfx_v12_1_emit_mem_sync(struct amdgpu_ring *ring) { const unsigned int gcr_cntl = - PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | - PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | - PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | - PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | - PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1) | - PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_SCOPE(2); + PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_INV(1) | + PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_WB(1) | + PACKET3_ACQUIRE_MEM__GCR_CNTL__GLV_INV(1) | + PACKET3_ACQUIRE_MEM__GCR_CNTL__GLK_INV(1) | + PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV(1) | + PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE(2); /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h index 21a07530c64d..77b4f6ea532f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h @@ -58,11 +58,36 @@ #define PACKET3_DISPATCH_DIRECT 0x15 #define PACKET3_DISPATCH_INDIRECT 0x16 #define PACKET3_ATOMIC_MEM 0x1E +#define PACKET3_ATOMIC_MEM__ATOMIC(x) ((((unsigned)(x)) & 0x7F) << 0) +#define PACKET3_ATOMIC_MEM__COMMAND(x) ((((unsigned)(x)) & 0xF) << 8) +#define PACKET3_ATOMIC_MEM__SCOPE(x) ((((unsigned)(x)) & 0x3) << 23) +#define PACKET3_ATOMIC_MEM__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) +#define PACKET3_ATOMIC_MEM__ADDR_LO(x) (((unsigned)(x))) +#define PACKET3_ATOMIC_MEM__ADDR_HI(x) (((unsigned)(x))) +#define PACKET3_ATOMIC_MEM__SRC_DATA_LO(x) (((unsigned)(x))) +#define PACKET3_ATOMIC_MEM__SRC_DATA_HI(x) (((unsigned)(x))) +#define PACKET3_ATOMIC_MEM__CMP_DATA_LO(x) (((unsigned)(x))) +#define PACKET3_ATOMIC_MEM__CMP_DATA_HI(x) (((unsigned)(x))) +#define PACKET3_ATOMIC_MEM__LOOP_INTERVAL(x) ((((unsigned)(x)) & 0x1FFF) << 0) +#define PACKET3_ATOMIC_MEM__COMMAND__SINGLE_PASS_ATOMIC 0 +#define PACKET3_ATOMIC_MEM__COMMAND__LOOP_UNTIL_COMPARE_SATISFIED 1 +#define PACKET3_ATOMIC_MEM__COMMAND__WAIT_FOR_WRITE_CONFIRMATION 2 +#define PACKET3_ATOMIC_MEM__COMMAND__SEND_AND_CONTINUE 3 +#define PACKET3_ATOMIC_MEM__SCOPE__CU 0 +#define PACKET3_ATOMIC_MEM__SCOPE__SE 1 +#define PACKET3_ATOMIC_MEM__SCOPE__DEVICE 2 +#define PACKET3_ATOMIC_MEM__SCOPE__SYSTEM 3 +#define PACKET3_ATOMIC_MEM__TEMPORAL__RT 0 +#define PACKET3_ATOMIC_MEM__TEMPORAL__NT 1 +#define PACKET3_ATOMIC_MEM__TEMPORAL__FW 2 +#define PACKET3_ATOMIC_MEM__TEMPORAL__UC 3 #define PACKET3_OCCLUSION_QUERY 0x1F #define PACKET3_SET_PREDICATION 0x20 #define PACKET3_REG_RMW 0x21 #define PACKET3_COND_EXEC 0x22 #define PACKET3_PRED_EXEC 0x23 +#define PACKET3_PRED_EXEC__EXEC_COUNT(x) ((((unsigned)(x)) & 0x3FFF) << 0) +#define PACKET3_PRED_EXEC__VIRTUALXCCID_SELECT(x) ((((unsigned)(x)) & 0xFF) << 24) #define PACKET3_DRAW_INDIRECT 0x24 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 #define PACKET3_INDEX_BASE 0x26 @@ -74,7 +99,11 @@ #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 #define PACKET3_WRITE_DATA 0x37 -#define WRITE_DATA_DST_SEL(x) (((x) & 0xf) << 8) +#define PACKET3_WRITE_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8) +#define PACKET3_WRITE_DATA__DST_SEL__MEM_MAPPED_REGISTER 0 +#define PACKET3_WRITE_DATA__DST_SEL__TC_L2 2 +#define PACKET3_WRITE_DATA__DST_SEL__MEMORY 5 +#define PACKET3_WRITE_DATA__DST_SEL__MEMORY_MAPPED_ADC_PERSISTENT_STATE 6 /* 0 - register * 1 - reserved * 2 - tc_l2 @@ -83,27 +112,52 @@ * 5 - memory (same as tc_l2) * 6 - memory_mapped_adc_persistent_state */ -#define WRITE_DATA_SCOPE(x) (((x) & 0x3) << 12) -#define WRITE_DATA_MODE(x) (((x) & 0x3) << 14) +#define PACKET3_WRITE_DATA__SCOPE(x) ((((unsigned)(x)) & 0x3) << 12) +#define PACKET3_WRITE_DATA__SCOPE__CU 0 +#define PACKET3_WRITE_DATA__SCOPE__SE 1 +#define PACKET3_WRITE_DATA__SCOPE__DEVICE 2 +#define PACKET3_WRITE_DATA__SCOPE__SYSTEM 3 +#define PACKET3_WRITE_DATA__MODE(x) ((((unsigned)(x)) & 0x3) << 14) +#define PACKET3_WRITE_DATA__MODE__LOCAL_XCD 0 +#define PACKET3_WRITE_DATA__MODE__REMOTE_OR_LOCAL_AID 1 +#define PACKET3_WRITE_DATA__MODE__REMOTE_XCD 2 +#define PACKET3_WRITE_DATA__MODE__REMOTE_MID 3 /* 0 - local xcd * 1 - remote/local aid * 2 - remote xcd * 3 - remote mid */ -#define WRITE_DATA_ADDR_INCR (1 << 16) -#define WRITE_DATA_MID_DIE_ID(x) (((x) & 0x3) << 18) -#define WR_CONFIRM (1 << 20) -#define WRITE_DATA_XCD_DIE_ID(x) (((x) & 0xf) << 21) -#define WRITE_DATA_TEMPORAL(x) (((x) & 0x3) << 25) - /* 0 - rt - * 1 - nt - * 2 - ht - * 3 - lu - */ -#define WRITE_DATA_COOP_DISABLE (1 << 27) +#define PACKET3_WRITE_DATA__ADDR_INCR(x) ((((unsigned)(x)) & 0x1) << 16) +#define PACKET3_WRITE_DATA__ADDR_INCR__INCREMENT_ADDRESS 0 +#define PACKET3_WRITE_DATA__ADDR_INCR__DO_NOT_INCREMENT_ADDRESS 1 +#define PACKET3_WRITE_DATA__MID_DIE_ID(x) ((((unsigned)(x)) & 0x3) << 18) +#define PACKET3_WRITE_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20) +#define PACKET3_WRITE_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_WRITE_CONFIRMATION 0 +#define PACKET3_WRITE_DATA__WR_CONFIRM__WAIT_FOR_WRITE_CONFIRMATION 1 +#define PACKET3_WRITE_DATA__XCD_DIE_ID(x) ((((unsigned)(x)) & 0xF) << 21) +#define PACKET3_WRITE_DATA__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) +#define PACKET3_WRITE_DATA__TEMPORAL__RT 0 +#define PACKET3_WRITE_DATA__TEMPORAL__NT 1 +#define PACKET3_WRITE_DATA__TEMPORAL__HT 2 +#define PACKET3_WRITE_DATA__TEMPORAL__LU 3 +#define PACKET3_WRITE_DATA__COOP_DISABLE(x) ((((unsigned)(x)) & 0x1) << 27) +#define PACKET3_WRITE_DATA__COOP_DISABLE__MASTER_AND_SLAVE_COOP 0 +#define PACKET3_WRITE_DATA__COOP_DISABLE__MASTER_ONLY 1 +#define PACKET3_WRITE_DATA__DST_MMREG_ADDR_LO(x) ((unsigned)(x)) +#define PACKET3_WRITE_DATA__DST_MEM_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) +#define PACKET3_WRITE_DATA__DST_MMREG_ADDR_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0) +#define PACKET3_WRITE_DATA__DST_MEM_ADDR_HI(x) ((unsigned)(x)) +#define PACKET3_WRITE_DATA__DATA(x) ((unsigned)(x)) #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 #define PACKET3_WAIT_REG_MEM 0x3C -#define WAIT_REG_MEM_FUNCTION(x) (((x) & 0x7) << 0) +#define PACKET3_WAIT_REG_MEM__FUNCTION(x) ((((unsigned)(x)) & 0x7) << 0) +#define PACKET3_WAIT_REG_MEM__FUNCTION__ALWAYS_PASS 0 +#define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_REF_VALUE 1 +#define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_EQUAL_TO_THE_REF_VALUE 2 +#define PACKET3_WAIT_REG_MEM__FUNCTION__EQUAL_TO_THE_REFERENCE_VALUE 3 +#define PACKET3_WAIT_REG_MEM__FUNCTION__NOT_EQUAL_REFERENCE_VALUE 4 +#define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_OR_EQUAL_REFERENCE_VALUE 5 +#define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_REFERENCE_VALUE 6 /* 0 - always * 1 - < * 2 - <= @@ -112,117 +166,222 @@ * 5 - >= * 6 - > */ -#define WAIT_REG_MEM_MEM_SPACE(x) (((x) & 0x3) << 4) +#define PACKET3_WAIT_REG_MEM__MEM_SPACE(x) ((((unsigned)(x)) & 0x3) << 4) +#define PACKET3_WAIT_REG_MEM__MEM_SPACE__REGISTER_SPACE 0 +#define PACKET3_WAIT_REG_MEM__MEM_SPACE__MEMORY_SPACE 1 /* 0 - reg * 1 - mem */ -#define WAIT_REG_MEM_OPERATION(x) (((x) & 0x3) << 6) +#define PACKET3_WAIT_REG_MEM__OPERATION(x) ((((unsigned)(x)) & 0x3) << 6) +#define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_REG_MEM 0 +#define PACKET3_WAIT_REG_MEM__OPERATION__WR_WAIT_WR_REG 1 +#define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_MEM_PREEMPTABLE 3 /* 0 - wait_reg_mem * 1 - wr_wait_wr_reg + * 2 - reserved + * 3 - wait_mem_preemptable */ -#define WAIT_REG_MEM_MODE(x) (((x) & 0x3) << 10) +#define PACKET3_WAIT_REG_MEM__MODE(x) ((((unsigned)(x)) & 0x3) << 10) +#define PACKET3_WAIT_REG_MEM__MODE__LOCAL_XCD 0 +#define PACKET3_WAIT_REG_MEM__MODE__REMOTE_OR_LOCAL_AID 1 +#define PACKET3_WAIT_REG_MEM__MODE__REMOTE_XCD 2 +#define PACKET3_WAIT_REG_MEM__MODE__REMOTE_MID 3 /* 0 - local xcd * 1 - remote/local aid * 2 - remote xcd * 3 - remote mid */ -#define WAIT_REG_MEM_MID_DIE_ID(x) (((x) & 0x3) << 12) -#define WAIT_REG_MEM_XCD_DIE_ID(x) (((x) & 0xf) << 14) -#define WAIT_REG_MEM_MES_INTR_PIPE(x) (((x) & 0x3) << 22) -#define WAIT_REG_MEM_MES_ACTION(x) (((x) & 0x1) << 24) -#define WAIT_REG_MEM_TEMPORAL(x) (((x) & 0x3) << 25) +#define PACKET3_WAIT_REG_MEM__MID_DIE_ID(x) ((((unsigned)(x)) & 0x3) << 12) +#define PACKET3_WAIT_REG_MEM__XCD_DIE_ID(x) ((((unsigned)(x)) & 0xf) << 14) +#define PACKET3_WAIT_REG_MEM__MES_INTR_PIPE(x) ((((unsigned)(x)) & 0x3) << 22) +#define PACKET3_WAIT_REG_MEM__MES_ACTION(x) ((((unsigned)(x)) & 0x1) << 24) +#define PACKET3_WAIT_REG_MEM__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) +#define PACKET3_WAIT_REG_MEM__TEMPORAL__RT 0 +#define PACKET3_WAIT_REG_MEM__TEMPORAL__NT 1 +#define PACKET3_WAIT_REG_MEM__TEMPORAL__HT 2 +#define PACKET3_WAIT_REG_MEM__TEMPORAL__LU 3 /* 0 - rt * 1 - nt * 2 - ht * 3 - lu */ +#define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) +#define PACKET3_WAIT_REG_MEM__REG_POLL_ADDR(x) ((unsigned)(x)) +#define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR1(x) ((((unsigned)(x)) & 0x3FFFF) << 0) +#define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI(x) ((unsigned)(x)) +#define PACKET3_WAIT_REG_MEM__REG_POLL_ADDR_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0) +#define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR2(x) ((((unsigned)(x)) & 0x3FFFF) << 0) +#define PACKET3_WAIT_REG_MEM__REFERENCE(x) ((unsigned)(x)) +#define PACKET3_WAIT_REG_MEM__MASK(x) ((unsigned)(x)) +#define PACKET3_WAIT_REG_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0) +#define PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE(x) ((((unsigned)(x)) & 0x1) << 31) #define PACKET3_INDIRECT_BUFFER 0x3F -#define INDIRECT_BUFFER_VALID (1 << 23) -#define INDIRECT_BUFFER_TEMPORAL(x) (x) << 28) - /* 0 - rt - * 1 - nt - * 2 - ht - * 3 - lu - */ +#define PACKET3_INDIRECT_BUFFER__IB_BASE_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) +#define PACKET3_INDIRECT_BUFFER__IB_BASE_HI(x) ((unsigned)(x)) +#define PACKET3_INDIRECT_BUFFER__IB_SIZE(x) ((((unsigned)(x)) & 0xFFFFF) << 0) +#define PACKET3_INDIRECT_BUFFER__CHAIN(x) ((((unsigned)(x)) & 0x1) << 20) +#define PACKET3_INDIRECT_BUFFER__OFFLOAD_POLLING(x) ((((unsigned)(x)) & 0x1) << 21) +#define PACKET3_INDIRECT_BUFFER__VALID(x) ((((unsigned)(x)) & 0x1) << 23) +#define PACKET3_INDIRECT_BUFFER__VMID(x) ((((unsigned)(x)) & 0xF) << 24) +#define PACKET3_INDIRECT_BUFFER__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 28) +#define PACKET3_INDIRECT_BUFFER__INHERIT_VMID(x) ((((unsigned)(x)) & 0x1) << 30) +#define PACKET3_INDIRECT_BUFFER__PRIV(x) ((((unsigned)(x)) & 0x1) << 31) +#define PACKET3_INDIRECT_BUFFER__TEMPORAL__RT 0 +#define PACKET3_INDIRECT_BUFFER__TEMPORAL__NT 1 +#define PACKET3_INDIRECT_BUFFER__TEMPORAL__HT 2 +#define PACKET3_INDIRECT_BUFFER__TEMPORAL__LU 3 #define PACKET3_COND_INDIRECT_BUFFER 0x3F #define PACKET3_COPY_DATA 0x40 -#define COPY_DATA_SRC_SEL(x) (((x) & 0xf) << 0) -#define COPY_DATA_DST_SEL(x) (((x) & 0xf) << 8) -#define COPY_DATA_SRC_SCOPE(x) (((x) & 0x3) << 4) -#define COPY_DATA_DST_SCOPE(x) (((x) & 0x3) << 27) -#define COPY_DATA_MODE(x) (((x) & 0x3) << 6) - /* 0 - local xcd - * 1 - remote/local aid - * 2 - remote xcd - * 3 - remote mid - */ -#define COPY_DATA_SRC_TEMPORAL(x) (((x) & 0x3) << 13) -#define COPY_DATA_DST_TEMPORAL(x) (((x) & 0x3) << 25) - /* 0 - rt - * 1 - nt - * 2 - ht - * 3 - lu - */ -#define COPY_DATA_COUNT_SEL (1 << 16) -#define COPY_DATA_SRC_DST_REMOTE_MODE(x) (((x)) & 0x1 << 16) - /* 0 - src remote - * 1 - dst remote - */ -#define COPY_DATA_MID_DIE_ID(x) (((x) & 0x3) << 18) -#define COPY_DATA_XCD_DIE_ID(x) (((x) & 0xf) << 21) -#define COPY_DATA_PQ_EXE_STATUS (1 << 27) +#define PACKET3_COPY_DATA__SRC_SEL(x) ((((unsigned)(x)) & 0xF) << 0) +#define PACKET3_COPY_DATA__SRC_SCOPE(x) ((((unsigned)(x)) & 0x3) << 4) +#define PACKET3_COPY_DATA__MODE(x) ((((unsigned)(x)) & 0x3) << 6) +#define PACKET3_COPY_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8) +#define PACKET3_COPY_DATA__SRC_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 13) +#define PACKET3_COPY_DATA__COUNT_SEL(x) ((((unsigned)(x)) & 0x1) << 16) +#define PACKET3_COPY_DATA__SRC_DST_REMOTE_MODE(x) ((((unsigned)(x)) & 0x1) << 17) +#define PACKET3_COPY_DATA__MID_DIE_ID(x) ((((unsigned)(x)) & 0x3) << 18) +#define PACKET3_COPY_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20) +#define PACKET3_COPY_DATA__XCD_DIE_ID(x) ((((unsigned)(x)) & 0xF) << 21) +#define PACKET3_COPY_DATA__DST_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) +#define PACKET3_COPY_DATA__DST_SCOPE(x) ((((unsigned)(x)) & 0x3) << 27) +#define PACKET3_COPY_DATA__PQ_EXE_STATUS(x) ((((unsigned)(x)) & 0x1) << 29) +#define PACKET3_COPY_DATA__SRC_REG_OFFSET_LO(x) ((unsigned)(x)) +#define PACKET3_COPY_DATA__SRC_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) +#define PACKET3_COPY_DATA__SRC_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) +#define PACKET3_COPY_DATA__IMM_DATA(x) ((unsigned)(x)) +#define PACKET3_COPY_DATA__SRC_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0) +#define PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI(x) ((unsigned)(x)) +#define PACKET3_COPY_DATA__SRC_IMM_DATA(x) ((unsigned)(x)) +#define PACKET3_COPY_DATA__DST_REG_OFFSET_LO(x) ((unsigned)(x)) +#define PACKET3_COPY_DATA__DST_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) +#define PACKET3_COPY_DATA__DST_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) +#define PACKET3_COPY_DATA__DST_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0) +#define PACKET3_COPY_DATA__DST_ADDR_HI(x) ((unsigned)(x)) +#define PACKET3_COPY_DATA__SRC_SEL__MEM_MAPPED_REGISTER 0 +#define PACKET3_COPY_DATA__SRC_SEL__TC_L2_OBSOLETE 1 +#define PACKET3_COPY_DATA__SRC_SEL__TC_L2 2 +#define PACKET3_COPY_DATA__SRC_SEL__PERFCOUNTERS 4 +#define PACKET3_COPY_DATA__SRC_SEL__IMMEDIATE_DATA 5 +#define PACKET3_COPY_DATA__SRC_SEL__ATOMIC_RETURN_DATA 6 +#define PACKET3_COPY_DATA__SRC_SEL__GPU_CLOCK_COUNT 9 +#define PACKET3_COPY_DATA__SRC_SEL__SYSTEM_CLOCK_COUNT 10 +#define PACKET3_COPY_DATA__SRC_SCOPE__CU 0 +#define PACKET3_COPY_DATA__SRC_SCOPE__SE 1 +#define PACKET3_COPY_DATA__SRC_SCOPE__DEVICE 2 +#define PACKET3_COPY_DATA__SRC_SCOPE__SYSTEM 3 +#define PACKET3_COPY_DATA__MODE__LOCAL_XCD 0 +#define PACKET3_COPY_DATA__MODE__REMOTE_OR_LOCAL_AID 1 +#define PACKET3_COPY_DATA__MODE__REMOTE_XCD 2 +#define PACKET3_COPY_DATA__MODE__REMOTE_MID 3 +#define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER 0 +#define PACKET3_COPY_DATA__DST_SEL__TC_L2 2 +#define PACKET3_COPY_DATA__DST_SEL__PERFCOUNTERS 4 +#define PACKET3_COPY_DATA__DST_SEL__TC_L2_OBSOLETE 5 +#define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REG_DC 6 +#define PACKET3_COPY_DATA__SRC_TEMPORAL__RT 0 +#define PACKET3_COPY_DATA__SRC_TEMPORAL__NT 1 +#define PACKET3_COPY_DATA__SRC_TEMPORAL__HT 2 +#define PACKET3_COPY_DATA__SRC_TEMPORAL__LU 3 +#define PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA 0 +#define PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA 1 +#define PACKET3_COPY_DATA__SRC_DST_REMOTE_MODE__SRC_IS_REMOTE 0 +#define PACKET3_COPY_DATA__SRC_DST_REMOTE_MODE__DST_IS_REMOTE 1 +#define PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION 0 +#define PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION 1 +#define PACKET3_COPY_DATA__DST_TEMPORAL__RT 0 +#define PACKET3_COPY_DATA__DST_TEMPORAL__NT 1 +#define PACKET3_COPY_DATA__DST_TEMPORAL__HT 2 +#define PACKET3_COPY_DATA__DST_TEMPORAL__LU 3 +#define PACKET3_COPY_DATA__DST_SCOPE__CU 0 +#define PACKET3_COPY_DATA__DST_SCOPE__SE 1 +#define PACKET3_COPY_DATA__DST_SCOPE__DEVICE 2 +#define PACKET3_COPY_DATA__DST_SCOPE__SYSTEM 3 +#define PACKET3_COPY_DATA__PQ_EXE_STATUS__DEFAULT 0 +#define PACKET3_COPY_DATA__PQ_EXE_STATUS__PHASE_UPDATE 1 #define PACKET3_PFP_SYNC_ME 0x42 #define PACKET3_COND_WRITE 0x45 #define PACKET3_EVENT_WRITE 0x46 -#define EVENT_TYPE(x) ((x) << 0) -#define EVENT_INDEX(x) ((x) << 8) - /* 0 - any non-TS event - * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* - * 2 - SAMPLE_PIPELINESTAT - * 3 - SAMPLE_STREAMOUTSTAT* - * 4 - *S_PARTIAL_FLUSH - */ +#define PACKET3_EVENT_WRITE__EVENT_TYPE(x) ((((unsigned)(x)) & 0x3F) << 0) +#define PACKET3_EVENT_WRITE__EVENT_INDEX(x) ((((unsigned)(x)) & 0xF) << 8) +#define PACKET3_EVENT_WRITE__OFFLOAD_ENABLE(x) ((((unsigned)(x)) & 0x1) << 31) +#define PACKET3_EVENT_WRITE__ADDRESS_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) +#define PACKET3_EVENT_WRITE__ADDRESS_HI(x) ((unsigned)(x)) +#define PACKET3_EVENT_WRITE__EVENT_INDEX__OTHER 0 +#define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_PIPELINESTAT 2 +#define PACKET3_EVENT_WRITE__EVENT_INDEX__CS_PARTIAL_FLUSH 4 +#define PACKET3_EVENT_WRITE_EOP 0x47 +#define PACKET3_EVENT_WRITE_EOS 0x48 #define PACKET3_RELEASE_MEM 0x49 -#define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0) -#define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8) -#define PACKET3_RELEASE_MEM_GCR_GL2_SCOPE(x) ((x) << 12) -#define PACKET3_RELEASE_MEM_GCR_GLV_INV (1 << 14) -#define PACKET3_RELEASE_MEM_GCR_GL2_US (1 << 16) -#define PACKET3_RELEASE_MEM_GCR_GL2_RANGE(x) ((x) << 17) -#define PACKET3_RELEASE_MEM_GCR_GL2_DISCARD (1 << 19) -#define PACKET3_RELEASE_MEM_GCR_GL2_INV (1 << 20) -#define PACKET3_RELEASE_MEM_GCR_GL2_WB (1 << 21) -#define PACKET3_RELEASE_MEM_GCR_SEQ(x) ((x) << 22) -#define PACKET3_RELEASE_MEM_GCR_GLV_WB (1 << 24) -#define PACKET3_RELEASE_MEM_TEMPORAL(x) ((x) << 25) +#define PACKET3_RELEASE_MEM__EVENT_TYPE(x) ((((unsigned)(x)) & 0x3F) << 0) +#define PACKET3_RELEASE_MEM__WAIT_SYNC(x) ((((unsigned)(x)) & 0x1) << 7) +#define PACKET3_RELEASE_MEM__EVENT_INDEX(x) ((((unsigned)(x)) & 0xF) << 8) +#define PACKET3_RELEASE_MEM__EVENT_INDEX__END_OF_PIPE 5 +#define PACKET3_RELEASE_MEM__EVENT_INDEX__SHADER_DONE 6 +#define PACKET3_RELEASE_MEM__GCR_CNTL(x) ((((unsigned)(x)) & 0x1FFF) << 12) +#define PACKET3_RELEASE_MEM__GCR_GL2_SCOPE(x) ((x) << 12) +#define PACKET3_RELEASE_MEM__GCR_GLV_INV (1 << 14) +#define PACKET3_RELEASE_MEM__GCR_GL2_US (1 << 16) +#define PACKET3_RELEASE_MEM__GCR_GL2_RANGE(x) ((x) << 17) +#define PACKET3_RELEASE_MEM__GCR_GL2_DISCARD (1 << 19) +#define PACKET3_RELEASE_MEM__GCR_GL2_INV (1 << 20) +#define PACKET3_RELEASE_MEM__GCR_GL2_WB (1 << 21) +#define PACKET3_RELEASE_MEM__GCR_SEQ(x) ((x) << 22) +#define PACKET3_RELEASE_MEM__GCR_GLV_WB (1 << 24) +#define PACKET3_RELEASE_MEM__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) +#define PACKET3_RELEASE_MEM__TEMPORAL__RT 0 +#define PACKET3_RELEASE_MEM__TEMPORAL__NT 1 +#define PACKET3_RELEASE_MEM__TEMPORAL__HT 2 +#define PACKET3_RELEASE_MEM__TEMPORAL__LU 3 /* 0 - temporal__release_mem__rt * 1 - temporal__release_mem__nt * 2 - temporal__release_mem__ht * 3 - temporal__release_mem__lu */ -#define PACKET3_RELEASE_MEM_PQ_EXE_STATUS (1 << 28) -#define PACKET3_RELEASE_MEM_GCR_GLK_INV (1 << 30) +#define PACKET3_RELEASE_MEM__PQ_EXE_STATUS(x) ((((unsigned)(x)) & 0x1) << 28) +#define PACKET3_RELEASE_MEM__PQ_EXE_STATUS__DEFAULT 0 +#define PACKET3_RELEASE_MEM__PQ_EXE_STATUS__PHASE_UPDATE 1 +#define PACKET3_RELEASE_MEM__GCR_GLK_INV (1 << 30) -#define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) - /* 0 - memory controller - * 1 - TC/L2 - * 2 - register - */ -#define PACKET3_RELEASE_MEM_MES_INTR_PIPE(x) ((x) << 20) -#define PACKET3_RELEASE_MEM_MES_ACTION_ID(x) ((x) << 22) -#define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) - /* 0 - none - * 1 - interrupt only (DATA_SEL = 0) - * 2 - interrupt when data write is confirmed - */ -#define PACKET3_RELEASE_MEM_ADD_DOOREBLL_OFFSET(x) (1 << 28) -#define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) +#define PACKET3_RELEASE_MEM__DST_SEL(x) ((((unsigned)(x)) & 0x3) << 16) +#define PACKET3_RELEASE_MEM__DST_SEL__MEMORY_CONTROLLER 0 +#define PACKET3_RELEASE_MEM__DST_SEL__TC_L2 1 +#define PACKET3_RELEASE_MEM__DST_SEL__QUQUE_WRITE_POINTER_REGISTER 2 +#define PACKET3_RELEASE_MEM__DST_SEL__QUQUE_WRITE_POINTER_POLL_MASK_BIT 3 +#define PACKET3_RELEASE_MEM__MES_INTR_PIPE(x) ((((unsigned)(x)) & 0x3) << 20) +#define PACKET3_RELEASE_MEM__MES_ACTION_ID(x) ((((unsigned)(x)) & 0x3) << 22) +#define PACKET3_RELEASE_MEM__MES_ACTION_ID__NO_MES_NOTIFICATION 0 +#define PACKET3_RELEASE_MEM__MES_ACTION_ID__INTERRUPT_AND_FENCE 1 +#define PACKET3_RELEASE_MEM__MES_ACTION_ID__INTERRUPT_NO_FENCE_THEN_ADDRESS_PAYLOAD 2 +#define PACKET3_RELEASE_MEM__MES_ACTION_ID__INTERRUPT_AND_ADDRESS_PAYLOAD 3 +#define PACKET3_RELEASE_MEM__INT_SEL(x) ((((unsigned)(x)) & 0x7) << 24) +#define PACKET3_RELEASE_MEM__INT_SEL__NONE 0 +#define PACKET3_RELEASE_MEM__INT_SEL__SEND_INTERRUPT_ONLY 1 +#define PACKET3_RELEASE_MEM__INT_SEL__SEND_INTERRUPT_AFTER_WRITE_CONFIRM 2 +#define PACKET3_RELEASE_MEM__INT_SEL__SEND_DATA_AND_WRITE_CONFIRM 3 +#define PACKET3_RELEASE_MEM__INT_SEL__UNCONDITIONALLY_SEND_INT_CTXID 4 +#define PACKET3_RELEASE_MEM__INT_SEL__UNCONDITIONALLY_SEND_INT_CTXID_BASED_ON_32_BIT_COMPARE 5 +#define PACKET3_RELEASE_MEM__INT_SEL__UNCONDITIONALLY_SEND_INT_CTXID_BASED_ON_64_BIT_COMPARE 6 +#define PACKET3_RELEASE_MEM__ADD_DOOREBLL_OFFSET(x) ((((unsigned)(x)) & 0x1) << 28) +#define PACKET3_RELEASE_MEM__DATA_SEL(x) ((((unsigned)(x)) & 0x7) << 29) +#define PACKET3_RELEASE_MEM__DATA_SEL__NONE 0 +#define PACKET3_RELEASE_MEM__DATA_SEL__SEND_32_BIT_LOW 1 +#define PACKET3_RELEASE_MEM__DATA_SEL__SEND_64_BIT_DATA 2 +#define PACKET3_RELEASE_MEM__DATA_SEL__SEND_GPU_CLOCK_COUNTER 3 +#define PACKET3_RELEASE_MEM__DATA_SEL__SEND_SYSTEM_CLOCK_COUNTER 4 /* 0 - discard * 1 - send low 32bit data * 2 - send 64bit data * 3 - send 64bit GPU counter value * 4 - send 64bit sys counter value */ +#define PACKET3_RELEASE_MEM__ADDRESS_LO_32B(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) +#define PACKET3_RELEASE_MEM__ADDRESS_LO_64B(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) +#define PACKET3_RELEASE_MEM__ADDRESS_HI(x) ((unsigned)(x)) +#define PACKET3_RELEASE_MEM__DATA_LO(x) ((unsigned)(x)) +#define PACKET3_RELEASE_MEM__CMP_DATA_LO(x) ((unsigned)(x)) +#define PACKET3_RELEASE_MEM__DATA_HI(x) ((unsigned)(x)) +#define PACKET3_RELEASE_MEM__CMP_DATA_HI(x) ((unsigned)(x)) +#define PACKET3_RELEASE_MEM__INT_CTXID(x) ((unsigned)(x)) #define PACKET3_PREAMBLE_CNTL 0x4A # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) @@ -279,58 +438,78 @@ # define PACKET3_DMA_DATA_CMD_DIS_WC (1 << 30) #define PACKET3_CONTEXT_REG_RMW 0x51 #define PACKET3_ACQUIRE_MEM 0x58 -/* 1. HEADER - * 2. COHER_CNTL [30:0] - * 2.1 ENGINE_SEL [31:31] - * 2. COHER_SIZE [31:0] - * 3. COHER_SIZE_HI [7:0] - * 4. COHER_BASE_LO [31:0] - * 5. COHER_BASE_HI [23:0] - * 7. POLL_INTERVAL [15:0] - * 8. GCR_CNTL [18:0] - */ -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0) +/* 1. HEADER */ +#define PACKET3_ACQUIRE_MEM__COHER_SIZE(x) ((unsigned)(x)) +/* 3. COHER_SIZE [31:0] */ +#define PACKET3_ACQUIRE_MEM__COHER_SIZE_HI(x) ((((unsigned)(x)) & 0xFF) << 0) +/* 4. COHER_SIZE_HI [7:0] */ +#define PACKET3_ACQUIRE_MEM__COHER_BASE_LO(x) ((unsigned)(x)) +/* 5. COHER_BASE_LO [31:0] */ +#define PACKET3_ACQUIRE_MEM__COHER_BASE_HI(x) ((((unsigned)(x)) & 0xFFFFFF) << 0) +/* 6. COHER_BASE_HI [23:0] */ +#define PACKET3_ACQUIRE_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0) +/* 7. POLL_INTERVAL [15:0] */ +#define PACKET3_ACQUIRE_MEM__GCR_CNTL(x) ((((unsigned)(x)) & 0x7FFFF) << 0) +/* 8. GCR_CNTL [18:0] */ +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV(x) ((x) << 0) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__NOP 0 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__ALL 1 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__RANGE 2 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__FIRST_LAST 3 /* * 0:NOP * 1:ALL * 2:RANGE * 3:FIRST_LAST */ -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE(x) ((x) << 2) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE__ALL 0 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE__RANGE 2 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE__FIRST_LAST 3 /* * 0:ALL * 1:reserved * 2:RANGE * 3:FIRST_LAST */ -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_SCOPE(x) ((x) << 4) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE(x) ((x) << 4) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE__DEVICE 0 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE__SYSTEM 1 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE__FORCE_ALL 2 /* * 0:Device scope * 1:System scope * 2:Force INV/WB all * 3:Reserved */ -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_WB(x) ((x) << 6) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLV_WB(x) ((x) << 6) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLK_INV(x) ((x) << 7) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLV_INV(x) ((x) << 8) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_US(x) ((x) << 10) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE(x) ((x) << 11) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__ALL 0 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__VOL 1 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__RANGE 2 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__FIRST_LAST 3 /* * 0:ALL * 1:VOL * 2:RANGE * 3:FIRST_LAST */ -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_DISCARD(x) ((x) << 13) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_INV(x) ((x) << 14) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_WB(x) ((x) << 15) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ(x) ((x) << 16) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ__PARALLET 0 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ__FORWARD 1 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ__REVERSE 2 /* * 0: PARALLEL * 1: FORWARD * 2: REVERSE */ -#define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA (1 << 18) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GCR_RANGE_IS_PA (1 << 18) #define PACKET3_GEN_PDEPTE 0x5B #define PACKET3_PRIME_UTCL2 0x5D #define PACKET3_LOAD_UCONFIG_REG 0x5E @@ -348,11 +527,19 @@ #define PACKET3_SET_SH_REG 0x76 #define PACKET3_SET_SH_REG_START 0x00002c00 #define PACKET3_SET_SH_REG_END 0x00003000 +#define PACKET3_SET_SH_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0) +#define PACKET3_SET_SH_REG__VMID_SHIFT(x) ((((unsigned)(x)) & 0x1F) << 23) +#define PACKET3_SET_SH_REG__INDEX(x) ((((unsigned)(x)) & 0xF) << 28) +#define PACKET3_SET_SH_REG__REG_DATA(x) (((unsigned)(x))) +#define PACKET3_SET_SH_REG__INDEX__DEFAULT 0 +#define PACKET3_SET_SH_REG__INDEX__INSERT_VMID 1 #define PACKET3_SET_SH_REG_OFFSET 0x77 #define PACKET3_SET_QUEUE_REG 0x78 #define PACKET3_SET_UCONFIG_REG 0x79 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 +#define PACKET3_SET_UCONFIG_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0) +#define PACKET3_SET_UCONFIG_REG__REG_DATA(x) (((unsigned)(x))) #define PACKET3_SET_UCONFIG_REG_INDEX 0x7A #define PACKET3_DISPATCH_DRAW_PREAMBLE 0x8C #define PACKET3_DISPATCH_DRAW 0x8D diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 73223d97a87f..ac90d8e9d86a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -1571,6 +1571,71 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) mutex_unlock(&adev->grbm_idx_mutex); } +/** + * gfx_v6_0_setup_tcc() - setup which TCCs are used + * + * @adev: amdgpu_device pointer + * + * Verify whether the current GPU has any TCCs disabled, + * which can happen when the GPU is harvested and some + * memory channels are disabled, reducing the memory bus width. + * For example, on the Radeon HD 7870 XT (Tahiti LE). + * + * If some TCCs are disabled, we need to make sure that + * the disabled TCCs are not used, and the remaining TCCs + * are used optimally. + * + * TCP_CHAN_STEER_LO/HI control which TCC is used by TCP channels. + * TCP_ADDR_CONFIG.NUM_TCC_BANKS controls how many channels are used. + * + * For optimal performance: + * - Rely on the CHAN_STEER from the golden registers table, + * only skip disabled TCCs but keep the mapping order. + * - Limit NUM_TCC_BANKS to number of active TCCs to avoid thrashing, + * which performs better than using the same TCC twice. + */ +static void gfx_v6_0_setup_tcc(struct amdgpu_device *adev) +{ + u32 i, tcc, tcp_addr_config, num_active_tcc = 0; + u64 chan_steer, patched_chan_steer = 0; + const u32 num_max_tcc = adev->gfx.config.max_texture_channel_caches; + const u32 dis_tcc_mask = + amdgpu_gfx_create_bitmask(num_max_tcc) & + (REG_GET_FIELD(RREG32(mmCGTS_TCC_DISABLE), + CGTS_TCC_DISABLE, TCC_DISABLE) | + REG_GET_FIELD(RREG32(mmCGTS_USER_TCC_DISABLE), + CGTS_USER_TCC_DISABLE, TCC_DISABLE)); + + /* When no TCC is disabled, the golden registers table already has optimal TCC setup */ + if (!dis_tcc_mask) + return; + + /* Each 4-bit nibble contains the index of a TCC used by all TCPs */ + chan_steer = RREG32(mmTCP_CHAN_STEER_LO) | ((u64)RREG32(mmTCP_CHAN_STEER_HI) << 32ull); + + /* Patch the TCP to TCC mapping to skip disabled TCCs */ + for (i = 0; i < num_max_tcc; ++i) { + tcc = (chan_steer >> (u64)(4 * i)) & 0xf; + + if (!((1 << tcc) & dis_tcc_mask)) { + /* Copy enabled TCC indices to the patched register value. */ + patched_chan_steer |= (u64)tcc << (u64)(4 * num_active_tcc); + ++num_active_tcc; + } + } + + WARN_ON(num_active_tcc != num_max_tcc - hweight32(dis_tcc_mask)); + + /* Patch number of TCCs used by TCPs */ + tcp_addr_config = REG_SET_FIELD(RREG32(mmTCP_ADDR_CONFIG), + TCP_ADDR_CONFIG, NUM_TCC_BANKS, + num_active_tcc - 1); + + WREG32(mmTCP_ADDR_CONFIG, tcp_addr_config); + WREG32(mmTCP_CHAN_STEER_HI, upper_32_bits(patched_chan_steer)); + WREG32(mmTCP_CHAN_STEER_LO, lower_32_bits(patched_chan_steer)); +} + static void gfx_v6_0_config_init(struct amdgpu_device *adev) { adev->gfx.config.double_offchip_lds_buf = 0; @@ -1729,6 +1794,7 @@ static void gfx_v6_0_constants_init(struct amdgpu_device *adev) gfx_v6_0_tiling_mode_table_init(adev); gfx_v6_0_setup_rb(adev); + gfx_v6_0_setup_tcc(adev); gfx_v6_0_setup_spi(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 2b691452775b..65b8497ad5f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2819,6 +2819,7 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, { u64 hqd_gpu_addr; u64 wb_gpu_addr; + u32 tmp; /* init the mqd struct */ memset(mqd, 0, sizeof(struct cik_mqd)); @@ -2923,7 +2924,11 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO); mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI); mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); - mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); + tmp = RREG32(mmCP_HQD_QUANTUM); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 10); + mqd->cp_hqd_quantum = tmp; mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index a6b4c8f41dc1..130196859ff3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4532,7 +4532,11 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring) /* set static priority for a queue/ring */ gfx_v8_0_mqd_set_priority(ring, mqd); - mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); + tmp = RREG32(mmCP_HQD_QUANTUM); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 10); + mqd->cp_hqd_quantum = tmp; /* map_queues packet doesn't need activate the queue, * so only kiq need set this field. diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 95be105671ec..bf270e605949 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -3667,7 +3667,11 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) /* set static priority for a queue/ring */ gfx_v9_0_mqd_set_priority(ring, mqd); - mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM); + tmp = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); + mqd->cp_hqd_quantum = tmp; /* map_queues packet doesn't need activate the queue, * so only kiq need set this field. @@ -5660,9 +5664,6 @@ static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, { struct amdgpu_device *adev = ring->adev; - /* we only allocate 32bit for each seq wb address */ - BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); - /* write fence seq to the "addr" */ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index ad4d442e7345..d0b8fb931720 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -1943,7 +1943,11 @@ static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) /* set static priority for a queue/ring */ gfx_v9_4_3_mqd_set_priority(ring, mqd); - mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); + mqd->cp_hqd_quantum = tmp; /* map_queues packet doesn't need activate the queue, * so only kiq need set this field. diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index e1ace7d44ffd..8523833a74fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -707,20 +707,16 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev) adev->gmc.visible_vram_size = adev->gmc.aper_size; /* set the gart size */ - if (amdgpu_gart_size == -1) { - switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { - default: - adev->gmc.gart_size = 512ULL << 20; - break; - case IP_VERSION(10, 3, 1): /* DCE SG support */ - case IP_VERSION(10, 3, 3): /* DCE SG support */ - case IP_VERSION(10, 3, 6): /* DCE SG support */ - case IP_VERSION(10, 3, 7): /* DCE SG support */ - adev->gmc.gart_size = 1024ULL << 20; - break; - } - } else { - adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(10, 3, 1): /* DCE SG support */ + case IP_VERSION(10, 3, 3): /* DCE SG support */ + case IP_VERSION(10, 3, 6): /* DCE SG support */ + case IP_VERSION(10, 3, 7): /* DCE SG support */ + amdgpu_gmc_set_gart_size(adev, SZ_1G); + break; + default: + amdgpu_gmc_set_gart_size(adev, SZ_512M); + break; } gmc_v10_0_vram_gtt_location(adev, &adev->gmc); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 94d6631ce0bc..16388e3caea3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -709,10 +709,7 @@ static int gmc_v11_0_mc_init(struct amdgpu_device *adev) adev->gmc.visible_vram_size = adev->gmc.real_vram_size; /* set the gart size */ - if (amdgpu_gart_size == -1) - adev->gmc.gart_size = 512ULL << 20; - else - adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + amdgpu_gmc_set_gart_size(adev, SZ_512M); gmc_v11_0_vram_gtt_location(adev, &adev->gmc); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index e10ac9788d13..586703ec0dfa 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -729,8 +729,10 @@ static int gmc_v12_0_mc_init(struct amdgpu_device *adev) int r; if (adev->gmc.xgmi.connected_to_cpu) - adev->gmc.mc_vram_size = - adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; + /* On A+A, manage driver allocation range to the local + * node segment and prevent allocations on remote HBM. + */ + adev->gmc.mc_vram_size = adev->gmc.xgmi.node_segment_size; else adev->gmc.mc_vram_size = adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; @@ -763,10 +765,7 @@ static int gmc_v12_0_mc_init(struct amdgpu_device *adev) adev->gmc.visible_vram_size = adev->gmc.real_vram_size; /* set the gart size */ - if (amdgpu_gart_size == -1) { - adev->gmc.gart_size = 512ULL << 20; - } else - adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + amdgpu_gmc_set_gart_size(adev, SZ_512M); gmc_v12_0_vram_gtt_location(adev, &adev->gmc); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c index 7ea7b9c30bca..855cd29cbffa 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c @@ -112,6 +112,8 @@ static int gmc_v12_1_process_interrupt(struct amdgpu_device *adev, const char *hub_name; int ret, xcc_id = 0; uint32_t status = 0; + const char *die_name; + char die_name_buf[32]; u64 addr; node_id = entry->node_id; @@ -201,6 +203,17 @@ static int gmc_v12_1_process_interrupt(struct amdgpu_device *adev, dev_err(adev->dev, " in page starting at address 0x%016llx from IH client %d (%s)\n", addr, entry->client_id, soc_v1_0_ih_clientid_name[entry->client_id]); + if (adev->irq.ih_funcs && + adev->irq.ih_funcs->node_id_to_die_name) { + die_name = adev->irq.ih_funcs->node_id_to_die_name(adev, node_id, + die_name_buf, + sizeof(die_name_buf)); + if (die_name) + dev_err(adev->dev, + " cookie node_id %d fault from die %s\n", + node_id, die_name); + } + if (amdgpu_sriov_vf(adev)) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index cc272a96fcef..af6944d2d330 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -328,24 +328,18 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) adev->gmc.visible_vram_size = adev->gmc.aper_size; /* set the gart size */ - if (amdgpu_gart_size == -1) { - switch (adev->asic_type) { - case CHIP_HAINAN: /* no MM engines */ - default: - adev->gmc.gart_size = 256ULL << 20; - break; - case CHIP_VERDE: /* UVD, VCE do not support GPUVM */ - case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */ - case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */ - case CHIP_OLAND: /* UVD, VCE do not support GPUVM */ - adev->gmc.gart_size = 1024ULL << 20; - break; - } - } else { - adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + switch (adev->asic_type) { + case CHIP_VERDE: /* UVD, VCE do not support GPUVM */ + case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */ + case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */ + case CHIP_OLAND: /* UVD, VCE do not support GPUVM */ + amdgpu_gmc_set_gart_size(adev, SZ_1G); + break; + case CHIP_HAINAN: /* no MM engines */ + default: + amdgpu_gmc_set_gart_size(adev, SZ_256M); + break; } - - adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; gmc_v6_0_vram_gtt_location(adev, &adev->gmc); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index bb16ba2ef6fd..96023b4f5f92 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -394,27 +394,21 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) adev->gmc.visible_vram_size = adev->gmc.aper_size; /* set the gart size */ - if (amdgpu_gart_size == -1) { - switch (adev->asic_type) { - case CHIP_TOPAZ: /* no MM engines */ - default: - adev->gmc.gart_size = 256ULL << 20; - break; + switch (adev->asic_type) { #ifdef CONFIG_DRM_AMDGPU_CIK - case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ - case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ - case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ - case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ - case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ - adev->gmc.gart_size = 1024ULL << 20; - break; + case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ + case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ + case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ + case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ + case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ + amdgpu_gmc_set_gart_size(adev, SZ_1G); + break; #endif - } - } else { - adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + case CHIP_TOPAZ: /* no MM engines */ + default: + amdgpu_gmc_set_gart_size(adev, SZ_256M); + break; } - - adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; gmc_v7_0_vram_gtt_location(adev, &adev->gmc); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index a59174f6bcc1..b76fc4441eb7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -585,27 +585,21 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) adev->gmc.visible_vram_size = adev->gmc.aper_size; /* set the gart size */ - if (amdgpu_gart_size == -1) { - switch (adev->asic_type) { - case CHIP_POLARIS10: /* all engines support GPUVM */ - case CHIP_POLARIS11: /* all engines support GPUVM */ - case CHIP_POLARIS12: /* all engines support GPUVM */ - case CHIP_VEGAM: /* all engines support GPUVM */ - default: - adev->gmc.gart_size = 256ULL << 20; - break; - case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ - case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ - case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ - case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ - adev->gmc.gart_size = 1024ULL << 20; - break; - } - } else { - adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + switch (adev->asic_type) { + case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ + case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ + case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ + case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ + amdgpu_gmc_set_gart_size(adev, SZ_1G); + break; + case CHIP_POLARIS10: /* all engines support GPUVM */ + case CHIP_POLARIS11: /* all engines support GPUVM */ + case CHIP_POLARIS12: /* all engines support GPUVM */ + case CHIP_VEGAM: /* all engines support GPUVM */ + default: + amdgpu_gmc_set_gart_size(adev, SZ_256M); + break; } - - adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; gmc_v8_0_vram_gtt_location(adev, &adev->gmc); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e7b78027002b..ced0f3941863 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1204,21 +1204,6 @@ static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, { int local_node, nid; - /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system - * memory can use more efficient MTYPEs. - */ - if (!(adev->flags & AMD_IS_APU) || - amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) - return; - - /* Only direct-mapped memory allows us to determine the NUMA node from - * the DMA address. - */ - if (!adev->ram_is_direct_mapped) { - dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n"); - return; - } - /* MTYPE_NC is the same default and can be overridden. * MTYPE_UC will be present if the memory is extended-coherent * and can also be overridden. @@ -1231,11 +1216,7 @@ static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, return; } - /* FIXME: Only supported on native mode for now. For carve-out, the - * NUMA affinity of the GPU/VM needs to come from the PCI info because - * memory partitions are not associated with different NUMA nodes. - */ - if (adev->gmc.is_app_apu && vm->mem_id >= 0) { + if (vm->mem_id >= 0) { local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; } else { dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n"); @@ -1344,6 +1325,20 @@ static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) { adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; + + /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes, local system + * memory can use more efficient MTYPEs. + * + * APUs mapping system memory may need different MTYPEs on different + * NUMA nodes. + * + * Only direct-mapped memory allows us to determine the NUMA node from + * the DMA address. + */ + adev->gmc.override_pte = adev->gmc.is_app_apu && + num_possible_nodes() > 1 && + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && + adev->ram_is_direct_mapped; } static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) @@ -1736,31 +1731,25 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) adev->gmc.visible_vram_size = adev->gmc.aper_size; /* set the gart size */ - if (amdgpu_gart_size == -1) { - switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { - case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ - case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ - case IP_VERSION(9, 4, 0): - case IP_VERSION(9, 4, 1): - case IP_VERSION(9, 4, 2): - case IP_VERSION(9, 4, 3): - case IP_VERSION(9, 4, 4): - case IP_VERSION(9, 5, 0): - default: - adev->gmc.gart_size = 512ULL << 20; - break; - case IP_VERSION(9, 1, 0): /* DCE SG support */ - case IP_VERSION(9, 2, 2): /* DCE SG support */ - case IP_VERSION(9, 3, 0): - adev->gmc.gart_size = 1024ULL << 20; - break; - } - } else { - adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(9, 1, 0): /* DCE SG support */ + case IP_VERSION(9, 2, 2): /* DCE SG support */ + case IP_VERSION(9, 3, 0): + amdgpu_gmc_set_gart_size(adev, SZ_1G); + break; + case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ + case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ + case IP_VERSION(9, 4, 0): + case IP_VERSION(9, 4, 1): + case IP_VERSION(9, 4, 2): + case IP_VERSION(9, 4, 3): + case IP_VERSION(9, 4, 4): + case IP_VERSION(9, 5, 0): + default: + amdgpu_gmc_set_gart_size(adev, SZ_512M); + break; } - adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; - gmc_v9_0_vram_gtt_location(adev, &adev->gmc); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index 1fbe904f4223..6de9e87e04e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c @@ -798,6 +798,43 @@ static void ih_v7_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 return; } +/* + * ih_v7_0_node_id_to_die_name - Decode IH cookie node_id to a die name string + * + * Currently, only applies to IH v7_1. For other IH versions returns NULL. + * + * IH v7_1 node_id encoding: + * node_id[N:3] = MID index + * node_id[2:0] = sub-slot: 0=MID, 1=AID, 2-5=AID.XCD, 6-7=RSV + */ +static const char *ih_v7_0_node_id_to_die_name(struct amdgpu_device *adev, + unsigned int node_id, + char *buf, size_t size) +{ + int mid_id, sub_slot; + + /* Node ID to die name decoding is only defined for IH v7_1 currenlty. */ + if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(7, 1, 0)) + return NULL; + + mid_id = node_id >> 3; + sub_slot = node_id & 0x7; + + if (mid_id > 1) + return "UNKNOWN"; + + if (sub_slot == 0) + snprintf(buf, size, "MID%d", mid_id); + else if (sub_slot == 1) + snprintf(buf, size, "AID%d", mid_id); + else if (sub_slot <= 5) + snprintf(buf, size, "AID%d.XCD%d", mid_id, sub_slot - 2); + else + snprintf(buf, size, "RSV"); + + return buf; +} + static const struct amd_ip_funcs ih_v7_0_ip_funcs = { .name = "ih_v7_0", .early_init = ih_v7_0_early_init, @@ -819,7 +856,8 @@ static const struct amdgpu_ih_funcs ih_v7_0_funcs = { .get_wptr = ih_v7_0_get_wptr, .decode_iv = amdgpu_ih_decode_iv_helper, .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper, - .set_rptr = ih_v7_0_set_rptr + .set_rptr = ih_v7_0_set_rptr, + .node_id_to_die_name = ih_v7_0_node_id_to_die_name, }; static void ih_v7_0_set_interrupt_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_1.c b/drivers/gpu/drm/amd/amdgpu/imu_v12_1.c index 539785a51f69..fe20cf2b9454 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v12_1.c @@ -140,27 +140,17 @@ static int imu_v12_1_switch_compute_partition(struct amdgpu_device *adev, int ret; if (adev->psp.funcs) { - /*TODO: revisit asp interface once it's avaialble */ - ret = psp_spatial_partition(&adev->psp, - NUM_XCC(adev->gfx.xcc_mask) / - num_xccs_per_xcp); + ret = psp_spatial_partition(&adev->psp, compute_partition_mode); if (ret) return ret; } adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; - return 0; } -static void imu_v12_1_init_mcm_addr_lut(struct amdgpu_device *adev) -{ - /* todo: fill in when interface is ready */ -} - const struct amdgpu_imu_funcs gfx_v12_1_imu_funcs = { .init_microcode = imu_v12_1_init_microcode, .load_microcode = imu_v12_1_load_microcode, .switch_compute_partition = imu_v12_1_switch_compute_partition, - .init_mcm_addr_lut = imu_v12_1_init_mcm_addr_lut, }; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index 9fe8d10ab270..cffb1e6bab35 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -802,6 +802,7 @@ static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v2_0_dec_ring_get_rptr, .get_wptr = jpeg_v2_0_dec_ring_get_wptr, .set_wptr = jpeg_v2_0_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c index 20983f126b49..5208312e7017 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c @@ -149,7 +149,7 @@ static int jpeg_v2_5_sw_init(struct amdgpu_ip_block *ip_block) else ring->vm_hub = AMDGPU_MMHUB0(0); ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i; - sprintf(ring->name, "jpeg_dec_%d", i); + snprintf(ring->name, sizeof(ring->name), "jpeg_dec_%d", i); r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, 0, AMDGPU_RING_PRIO_DEFAULT, NULL); if (r) @@ -693,6 +693,7 @@ static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v2_5_dec_ring_get_rptr, .get_wptr = jpeg_v2_5_dec_ring_get_wptr, .set_wptr = jpeg_v2_5_dec_ring_set_wptr, @@ -724,6 +725,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = { static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v2_5_dec_ring_get_rptr, .get_wptr = jpeg_v2_5_dec_ring_get_wptr, .set_wptr = jpeg_v2_5_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index 98f5e0622bc5..d0445df39d2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -594,6 +594,7 @@ static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v3_0_dec_ring_get_rptr, .get_wptr = jpeg_v3_0_dec_ring_get_wptr, .set_wptr = jpeg_v3_0_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index 0bd83820dd20..6fd4238a8471 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -759,6 +759,7 @@ static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v4_0_dec_ring_get_rptr, .get_wptr = jpeg_v4_0_dec_ring_get_wptr, .set_wptr = jpeg_v4_0_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index 82abe181c730..0c746580de11 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -1219,6 +1219,7 @@ static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr, .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr, .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index 54fd9c800c40..a43582b9c876 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -804,6 +804,7 @@ static const struct amd_ip_funcs jpeg_v4_0_5_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v4_0_5_dec_ring_get_rptr, .get_wptr = jpeg_v4_0_5_dec_ring_get_wptr, .set_wptr = jpeg_v4_0_5_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c index 46bf15dce2bd..72a4b2d0676f 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c @@ -680,6 +680,7 @@ static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v5_0_0_dec_ring_get_rptr, .get_wptr = jpeg_v5_0_0_dec_ring_get_wptr, .set_wptr = jpeg_v5_0_0_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c index edecbfe66c79..250316704dfa 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c @@ -884,6 +884,7 @@ static const struct amd_ip_funcs jpeg_v5_0_1_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v5_0_1_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v5_0_1_dec_ring_get_rptr, .get_wptr = jpeg_v5_0_1_dec_ring_get_wptr, .set_wptr = jpeg_v5_0_1_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c index 285c459379c4..7a4ecea6b39a 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c @@ -703,6 +703,7 @@ static const struct amd_ip_funcs jpeg_v5_0_2_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v5_0_2_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v5_0_2_dec_ring_get_rptr, .get_wptr = jpeg_v5_0_2_dec_ring_get_wptr, .set_wptr = jpeg_v5_0_2_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c index 1821dced936f..e7546816baba 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c @@ -661,6 +661,7 @@ static const struct amd_ip_funcs jpeg_v5_3_0_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v5_3_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v5_3_0_dec_ring_get_rptr, .get_wptr = jpeg_v5_3_0_dec_ring_get_wptr, .set_wptr = jpeg_v5_3_0_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 2fc39a6938f6..9bb8f7330537 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -30,34 +30,6 @@ #define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE #define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE -static int -mes_userq_map_gtt_bo_to_gart(struct amdgpu_bo *bo) -{ - int ret; - - ret = amdgpu_bo_reserve(bo, true); - if (ret) { - DRM_ERROR("Failed to reserve bo. ret %d\n", ret); - goto err_reserve_bo_failed; - } - - ret = amdgpu_ttm_alloc_gart(&bo->tbo); - if (ret) { - DRM_ERROR("Failed to bind bo to GART. ret %d\n", ret); - goto err_map_bo_gart_failed; - } - - amdgpu_bo_unreserve(bo); - bo = amdgpu_bo_ref(bo); - - return 0; - -err_map_bo_gart_failed: - amdgpu_bo_unreserve(bo); -err_reserve_bo_failed: - return ret; -} - static int mes_userq_create_wptr_mapping(struct amdgpu_device *adev, struct amdgpu_userq_mgr *uq_mgr, @@ -65,55 +37,62 @@ mes_userq_create_wptr_mapping(struct amdgpu_device *adev, uint64_t wptr) { struct amdgpu_bo_va_mapping *wptr_mapping; - struct amdgpu_vm *wptr_vm; struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj; + struct amdgpu_bo *obj; + struct amdgpu_vm *vm = queue->vm; + struct drm_exec exec; int ret; - wptr_vm = queue->vm; - ret = amdgpu_bo_reserve(wptr_vm->root.bo, false); - if (ret) - return ret; - wptr &= AMDGPU_GMC_HOLE_MASK; - wptr_mapping = amdgpu_vm_bo_lookup_mapping(wptr_vm, wptr >> PAGE_SHIFT); - amdgpu_bo_unreserve(wptr_vm->root.bo); - if (!wptr_mapping) { - DRM_ERROR("Failed to lookup wptr bo\n"); - return -EINVAL; + + drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 2); + drm_exec_until_all_locked(&exec) { + ret = amdgpu_vm_lock_pd(vm, &exec, 1); + drm_exec_retry_on_contention(&exec); + if (unlikely(ret)) + goto fail_lock; + + wptr_mapping = amdgpu_vm_bo_lookup_mapping(vm, wptr >> PAGE_SHIFT); + if (!wptr_mapping) { + ret = -EINVAL; + goto fail_lock; + } + + obj = wptr_mapping->bo_va->base.bo; + ret = drm_exec_lock_obj(&exec, &obj->tbo.base); + drm_exec_retry_on_contention(&exec); + if (unlikely(ret)) + goto fail_lock; } - wptr_obj->obj = wptr_mapping->bo_va->base.bo; + wptr_obj->obj = amdgpu_bo_ref(wptr_mapping->bo_va->base.bo); if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) { - DRM_ERROR("Requested GART mapping for wptr bo larger than one page\n"); - return -EINVAL; - } - - ret = mes_userq_map_gtt_bo_to_gart(wptr_obj->obj); - if (ret) { - DRM_ERROR("Failed to map wptr bo to GART\n"); - return ret; - } - - ret = amdgpu_bo_reserve(wptr_obj->obj, true); - if (ret) { - DRM_ERROR("Failed to reserve wptr bo\n"); - return ret; + ret = -EINVAL; + goto fail_map; } /* TODO use eviction fence instead of pinning. */ ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT); if (ret) { - drm_file_err(uq_mgr->file, "[Usermode queues] Failed to pin wptr bo\n"); - goto unresv_bo; + DRM_ERROR("Failed to pin wptr bo. ret %d\n", ret); + goto fail_map; + } + + ret = amdgpu_ttm_alloc_gart(&wptr_obj->obj->tbo); + if (ret) { + DRM_ERROR("Failed to bind bo to GART. ret %d\n", ret); + goto fail_map; } queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj); - amdgpu_bo_unreserve(wptr_obj->obj); + drm_exec_fini(&exec); return 0; -unresv_bo: - amdgpu_bo_unreserve(wptr_obj->obj); +fail_map: + amdgpu_bo_unref(&wptr_obj->obj); +fail_lock: + drm_exec_fini(&exec); return ret; } @@ -266,7 +245,7 @@ static int mes_userq_detect_and_reset(struct amdgpu_device *adev, if (found_hung_queue) { /* Resume scheduling after hang recovery */ - r = amdgpu_mes_resume(adev); + r = amdgpu_mes_resume(adev, input.xcc_id); } return r; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c index cec801278126..1931562ea6b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -44,8 +44,11 @@ static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block); static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id); +static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id); #define MES_EOP_SIZE 2048 +#define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset [4:7] hqd info */ +#define MES12_HUNG_HQD_INFO_OFFSET 4 #define regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT 0x100000 #define XCC_MID_MASK 0x41000000 @@ -229,7 +232,7 @@ static int mes_v12_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, xcc_id, pipe, x_pkt->header.opcode); r = amdgpu_fence_wait_polling(ring, seq, timeout); - if (r < 1 || !*status_ptr) { + if (r < 1 || !lower_32_bits(*status_ptr)) { if (misc_op_str) dev_err(adev->dev, "MES(%d, %d) failed to respond to msg=%s (%s)\n", @@ -468,13 +471,43 @@ static int mes_v12_1_unmap_legacy_queue(struct amdgpu_mes *mes, static int mes_v12_1_suspend_gang(struct amdgpu_mes *mes, struct mes_suspend_gang_input *input) { - return 0; + union MESAPI__SUSPEND mes_suspend_gang_pkt; + + memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); + + mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; + mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; + mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; + mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; + mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; + + /* Suspend gang is handled by master MES */ + return mes_v12_1_submit_pkt_and_poll_completion(mes, input->xcc_id, AMDGPU_MES_SCHED_PIPE, + &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), + offsetof(union MESAPI__SUSPEND, api_status)); } static int mes_v12_1_resume_gang(struct amdgpu_mes *mes, struct mes_resume_gang_input *input) { - return 0; + union MESAPI__RESUME mes_resume_gang_pkt; + + memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); + + mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; + mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; + mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; + + /* Resume gang is handled by master MES */ + return mes_v12_1_submit_pkt_and_poll_completion(mes, input->xcc_id, AMDGPU_MES_SCHED_PIPE, + &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), + offsetof(union MESAPI__RESUME, api_status)); } static int mes_v12_1_query_sched_status(struct amdgpu_mes *mes, @@ -621,11 +654,15 @@ static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes, mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; - if (mes->enable_coop_mode && pipe == AMDGPU_MES_SCHED_PIPE) { + /* From version 0x74 above, pipe1 support use shared command buffer + to distribute some tasks on individual XCCs*/ + if (mes->enable_coop_mode && + ((pipe == AMDGPU_MES_SCHED_PIPE) || + ((mes->kiq_version & AMDGPU_MES_VERSION_MASK) >= 0x74))) { master_xcc_id = mes->master_xcc_ids[inst]; mes_set_hw_res_1_pkt.mes_coop_mode = 1; mes_set_hw_res_1_pkt.coop_sch_shared_mc_addr = - mes->shared_cmd_buf_gpu_addr[master_xcc_id]; + mes->shared_cmd_buf_gpu_addr[master_xcc_id + pipe]; } return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, @@ -633,21 +670,10 @@ static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes, offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); } -static void mes_v12_1_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt) -{ - /* - * GFX V12 has only one GFX pipe, but 8 queues in it. - * GFX pipe 0 queue 0 is being used by Kernel queue. - * Set GFX pipe 0 queue 1-7 for MES scheduling - * mask = 1111 1110b - */ - pkt->gfx_hqd_mask[0] = 0xFE; -} - static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes, int pipe, int xcc_id) { - int i; + int i, status; struct amdgpu_device *adev = mes->adev; union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; @@ -667,7 +693,9 @@ static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes, mes_set_hw_res_pkt.compute_hqd_mask[i] = mes->compute_hqd_mask[i]; - mes_v12_1_set_gfx_hqd_mask(&mes_set_hw_res_pkt); + for (i = 0; i < MAX_GFX_PIPES; i++) + mes_set_hw_res_pkt.gfx_hqd_mask[i] = + mes->gfx_hqd_mask[i]; for (i = 0; i < MAX_SDMA_PIPES; i++) mes_set_hw_res_pkt.sdma_hqd_mask[i] = @@ -715,9 +743,23 @@ static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes, if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) mes_set_hw_res_pkt.limit_single_process = 1; - return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, + status = mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); + + /* get MES scheduler versions */ + mutex_lock(&adev->srbm_mutex); + soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); + + if (pipe == AMDGPU_MES_SCHED_PIPE) + adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); + else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) + adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); + + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + mutex_unlock(&adev->srbm_mutex); + + return status; } static void mes_v12_1_init_aggregated_doorbell(struct amdgpu_mes *mes, @@ -837,6 +879,33 @@ static int mes_v12_1_reset_legacy_queue(struct amdgpu_mes *mes, } #endif +static int mes_v12_1_detect_and_reset_hung_queues(struct amdgpu_mes *mes, + struct mes_detect_and_reset_queue_input *input) +{ + union MESAPI__RESET mes_reset_queue_pkt; + + memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); + + mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; + mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_reset_queue_pkt.queue_type = + convert_to_mes_queue_type(input->queue_type); + mes_reset_queue_pkt.doorbell_offset_addr = + mes->hung_queue_db_array_gpu_addr[0]; + + if (input->detect_only) + mes_reset_queue_pkt.hang_detect_only = 1; + else + mes_reset_queue_pkt.hang_detect_then_reset = 1; + + return mes_v12_1_submit_pkt_and_poll_completion(mes, + input->xcc_id, AMDGPU_MES_SCHED_PIPE, + &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), + offsetof(union MESAPI__RESET, api_status)); +} + static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) { /* @@ -894,6 +963,7 @@ static const struct amdgpu_mes_funcs mes_v12_1_funcs = { .resume_gang = mes_v12_1_resume_gang, .misc_op = mes_v12_1_misc_op, .reset_hw_queue = mes_v12_1_reset_hw_queue, + .detect_and_reset_hung_queues = mes_v12_1_detect_and_reset_hung_queues, .invalidate_tlbs_pasid = mes_v12_1_inv_tlbs_pasid, }; @@ -1157,9 +1227,6 @@ static int mes_v12_1_allocate_shared_cmd_buf(struct amdgpu_device *adev, { int r, inst = MES_PIPE_INST(xcc_id, pipe); - if (pipe == AMDGPU_MES_KIQ_PIPE) - return 0; - r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, &adev->mes.shared_cmd_buf_obj[inst], @@ -1405,18 +1472,6 @@ static int mes_v12_1_queue_init(struct amdgpu_device *adev, mes_v12_1_queue_init_register(ring, xcc_id); } - /* get MES scheduler/KIQ versions */ - mutex_lock(&adev->srbm_mutex); - soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); - - if (pipe == AMDGPU_MES_SCHED_PIPE) - adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); - else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) - adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); - - soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); - mutex_unlock(&adev->srbm_mutex); - return 0; } @@ -1723,6 +1778,10 @@ static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) goto failure; if (adev->enable_uni_mes) { + r = mes_v12_1_setup_coop_mode(adev, xcc_id); + if (r) + goto failure; + r = mes_v12_1_set_hw_resources(&adev->mes, AMDGPU_MES_KIQ_PIPE, xcc_id); if (r) @@ -1845,9 +1904,6 @@ static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id) goto failure; if (adev->enable_uni_mes) { - r = mes_v12_1_setup_coop_mode(adev, xcc_id); - if (r) - goto failure; mes_v12_1_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE, xcc_id); } @@ -1897,24 +1953,12 @@ static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) static int mes_v12_1_suspend(struct amdgpu_ip_block *ip_block) { - int r; - - r = amdgpu_mes_suspend(ip_block->adev); - if (r) - return r; - return mes_v12_1_hw_fini(ip_block); } static int mes_v12_1_resume(struct amdgpu_ip_block *ip_block) { - int r; - - r = mes_v12_1_hw_init(ip_block); - if (r) - return r; - - return amdgpu_mes_resume(ip_block->adev); + return mes_v12_1_hw_init(ip_block); } static int mes_v12_1_early_init(struct amdgpu_ip_block *ip_block) @@ -1922,6 +1966,9 @@ static int mes_v12_1_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; int pipe, r; + adev->mes.hung_queue_db_array_size = MES12_HUNG_DB_OFFSET_ARRAY_SIZE; + adev->mes.hung_queue_hqd_info_offset = MES12_HUNG_HQD_INFO_OFFSET; + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { r = amdgpu_mes_init_microcode(adev, pipe); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c new file mode 100644 index 000000000000..5e8f466f23ad --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c @@ -0,0 +1,369 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "nbio/nbio_6_3_2_offset.h" +#include "nbio/nbio_6_3_2_sh_mask.h" + +#include "amdgpu.h" +#include "nbio_v6_3_2.h" + +static u32 nbio_v6_3_2_get_pcie_index_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2); +} + +static u32 nbio_v6_3_2_get_pcie_data_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2); +} + +static u32 nbio_v6_3_2_get_pcie_index_hi_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2_HI); +} + +static u32 nbio_v6_3_2_get_rev_id(struct amdgpu_device *adev) +{ + u32 tmp; + + /* TODO: RCC_STRAP0_RCC_DEV0_EPF0_STRAP0 is not accessible from + * guest side. It requires bootloader to update specific fields + * in ip discovery table to identify soc revision id. + * Return 0 when the function is called from guest side until + * bootloader change is available. + */ + if (amdgpu_sriov_vf(adev)) + return 0; + + tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); + tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, + STRAP_ATI_REV_ID_DEV0_F0); + + return tmp; +} + +static void nbio_v6_3_2_mc_access_enable(struct amdgpu_device *adev, + bool enable) +{ + if (enable) + WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, + BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); + else + WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); +} + +static void nbio_v6_3_2_init_registers(struct amdgpu_device *adev) +{ + WREG32_SOC15(NBIO, 0, regXCD_DOORBELL_FENCE_1, + (0xff & ~(adev->gfx.xcc_mask)) << + XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_DISABLE__SHIFT); +} + +static u32 nbio_v6_3_2_get_memsize(struct amdgpu_device *adev) +{ + return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); +} + +static void nbio_v6_3_2_enable_doorbell_aperture(struct amdgpu_device *adev, + bool enable) +{ + /* Enable to allow doorbell pass thru on pre-silicon bare-metal */ + WREG32_SOC15(NBIO, 0, regGDC0_DOORBELL_ACCESS_EN_PF, 0xfffff); + WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, + BIF_DOORBELL_APER_EN, enable ? 1 : 0); +} + +static void nbio_v6_3_2_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, + bool enable) +{ + u32 tmp = 0; + + if (enable) { + tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, + DOORBELL_SELFRING_GPA_APER_EN, 1) | + REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, + DOORBELL_SELFRING_GPA_APER_MODE, 1) | + REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, + DOORBELL_SELFRING_GPA_APER_SIZE, 0); + + WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, + lower_32_bits(adev->doorbell.base)); + WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, + upper_32_bits(adev->doorbell.base)); + } + + WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); +} + +static void nbio_v6_3_2_enable_doorbell_interrupt(struct amdgpu_device *adev, + bool enable) +{ + WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL, + DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); +} + +static void nbio_v6_3_2_ih_control(struct amdgpu_device *adev) +{ + u32 interrupt_cntl; + + /* setup interrupt control */ + WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); + + interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); + /* + * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi + * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN + */ + interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, + IH_DUMMY_RD_OVERRIDE, 0); + + /* BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ + interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, + IH_REQ_NONSNOOP_EN, 0); + + WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); +} + +static void nbio_v6_3_2_ih_doorbell_range(struct amdgpu_device *adev, + bool use_doorbell, int doorbell_index) +{ + u32 ih_doorbell_range = 0; + u32 ih_doorbell_range1 = 0; + + if (use_doorbell) { + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, + S2A_DOORBELL_PORT1_ENABLE, + 0x1); + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, + S2A_DOORBELL_PORT1_AWID, + 0x0); + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, + S2A_DOORBELL_PORT1_RANGE_OFFSET, + doorbell_index); + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, + S2A_DOORBELL_PORT1_RANGE_SIZE, + 8); + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, + S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, + 0x0); + ih_doorbell_range1 = REG_SET_FIELD(ih_doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1, + S2A_DOORBELL_PORT1_TARGET_PORT_TYPE, + 0x3); + ih_doorbell_range1 = REG_SET_FIELD(ih_doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1, + S2A_DOORBELL_PORT1_TARGET_DIEID, + 0x0); + ih_doorbell_range1 = REG_SET_FIELD(ih_doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1, + S2A_DOORBELL_PORT1_TARGET_PORT_ID, + 0x0); + } + + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1, ih_doorbell_range1); +} + +static void nbio_v6_3_2_gc_doorbell_init(struct amdgpu_device *adev) +{ + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1, 0x3); +} + +static void nbio_v6_3_2_sdma_doorbell_range(struct amdgpu_device *adev, + int instance, bool use_doorbell, + int doorbell_index, + int doorbell_size) +{ + if (instance == 0) { + u32 doorbell_range = 0; + u32 doorbell_range1 = 0; + + if (use_doorbell) { + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL, + S2A_DOORBELL_PORT6_ENABLE, + 0x1); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL, + S2A_DOORBELL_PORT6_AWID, + 0xe); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL, + S2A_DOORBELL_PORT6_RANGE_OFFSET, + doorbell_index); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL, + S2A_DOORBELL_PORT6_RANGE_SIZE, + doorbell_size); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL, + S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE, + 0xe); + doorbell_range1 = REG_SET_FIELD(doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1, + S2A_DOORBELL_PORT6_TARGET_PORT_TYPE, + 0x3); + doorbell_range1 = REG_SET_FIELD(doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1, + S2A_DOORBELL_PORT6_TARGET_DIEID, + 0x0); + doorbell_range1 = REG_SET_FIELD(doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1, + S2A_DOORBELL_PORT6_TARGET_PORT_ID, + 0x0); + } + + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL, doorbell_range); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1, doorbell_range1); + } +} + +static void nbio_v6_3_2_vcn_doorbell_range(struct amdgpu_device *adev, + bool use_doorbell, int doorbell_index, + int instance) +{ + u32 doorbell_range = 0; + u32 doorbell_range1 = 0; + + if (use_doorbell) { + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, + S2A_DOORBELL_PORT2_ENABLE, + 0x1); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, + S2A_DOORBELL_PORT2_AWID, + (instance % adev->vcn.num_inst_per_aid) ? 0x7 : 0x4); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, + S2A_DOORBELL_PORT2_RANGE_OFFSET, + doorbell_index); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, + S2A_DOORBELL_PORT2_RANGE_SIZE, + 8); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, + S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE, + (instance % adev->vcn.num_inst_per_aid) ? 0x7 : 0x4); + doorbell_range1 = REG_SET_FIELD(doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1, + S2A_DOORBELL_PORT2_TARGET_PORT_TYPE, + 0x3); + doorbell_range1 = REG_SET_FIELD(doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1, + S2A_DOORBELL_PORT2_TARGET_DIEID, + (instance / adev->vcn.num_inst_per_aid) ? 0x3 : 0x0); + doorbell_range1 = REG_SET_FIELD(doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1, + S2A_DOORBELL_PORT2_TARGET_PORT_ID, + 0x0); + } + + switch (instance) { + case 0: + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1, doorbell_range1); + break; + case 1: + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, doorbell_range); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1, doorbell_range1); + break; + case 2: + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1, doorbell_range1); + break; + case 3: + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1, doorbell_range1); + break; + default: + dev_err(adev->dev, + "amdgpu: invalid vcn instance set when program doorbell range\n"); + break; + } +} + +static int nbio_v6_3_2_get_compute_partition_mode(struct amdgpu_device *adev) +{ + u32 tmp, px; + + tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS); + px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS, + PARTITION_MODE); + + return px; +} + +static bool nbio_v6_3_2_is_nps_switch_requested(struct amdgpu_device *adev) +{ + u32 tmp; + + tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS); + tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, + CHANGE_STATUS); + + /* 0x8 - NPS switch requested */ + return (tmp == 0x8); +} +static u32 nbio_v6_3_2_get_memory_partition_mode(struct amdgpu_device *adev, + u32 *supp_modes) +{ + u32 tmp; + + tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS); + tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE); + + if (supp_modes) { + *supp_modes = + RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP); + } + + return ffs(tmp); +} + +const struct amdgpu_nbio_funcs nbio_v6_3_2_funcs = { + .get_pcie_index_offset = nbio_v6_3_2_get_pcie_index_offset, + .get_pcie_data_offset = nbio_v6_3_2_get_pcie_data_offset, + .get_pcie_index_hi_offset = nbio_v6_3_2_get_pcie_index_hi_offset, + .get_rev_id = nbio_v6_3_2_get_rev_id, + .mc_access_enable = nbio_v6_3_2_mc_access_enable, + .get_memsize = nbio_v6_3_2_get_memsize, + .enable_doorbell_aperture = nbio_v6_3_2_enable_doorbell_aperture, + .enable_doorbell_selfring_aperture = nbio_v6_3_2_enable_doorbell_selfring_aperture, + .enable_doorbell_interrupt = nbio_v6_3_2_enable_doorbell_interrupt, + .get_compute_partition_mode = nbio_v6_3_2_get_compute_partition_mode, + .get_memory_partition_mode = nbio_v6_3_2_get_memory_partition_mode, + .is_nps_switch_requested = nbio_v6_3_2_is_nps_switch_requested, + .ih_control = nbio_v6_3_2_ih_control, + .ih_doorbell_range = nbio_v6_3_2_ih_doorbell_range, + .gc_doorbell_init = nbio_v6_3_2_gc_doorbell_init, + .sdma_doorbell_range = nbio_v6_3_2_sdma_doorbell_range, + .vcn_doorbell_range = nbio_v6_3_2_vcn_doorbell_range, + .init_registers = nbio_v6_3_2_init_registers, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.h b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.h new file mode 100644 index 000000000000..bc7f747c88f4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.h @@ -0,0 +1,31 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __NBIO_V6_3_2_H__ +#define __NBIO_V6_3_2_H__ + +#include "soc15_common.h" + +extern const struct amdgpu_nbio_funcs nbio_v6_3_2_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 7ce1a1b95606..72edf5326b05 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -354,29 +354,12 @@ static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, }; -static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, - u32 sh_num, u32 reg_offset) -{ - uint32_t val; - - mutex_lock(&adev->grbm_idx_mutex); - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); - - val = RREG32(reg_offset); - - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); - mutex_unlock(&adev->grbm_idx_mutex); - return val; -} - static uint32_t nv_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) { if (indexed) { - return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); + return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); } else { if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) return adev->gfx.config.gb_addr_config; @@ -511,16 +494,6 @@ static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) return 0; } -static void nv_program_aspm(struct amdgpu_device *adev) -{ - if (!amdgpu_device_should_use_aspm(adev)) - return; - - if (adev->nbio.funcs->program_aspm) - adev->nbio.funcs->program_aspm(adev); - -} - const struct amdgpu_ip_block_version nv_common_ip_block = { .type = AMD_IP_BLOCK_TYPE_COMMON, .major = 1, @@ -984,7 +957,7 @@ static int nv_common_hw_init(struct amdgpu_ip_block *ip_block) adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); /* enable aspm */ - nv_program_aspm(adev); + amdgpu_nbio_program_aspm(adev); /* setup nbio registers */ adev->nbio.funcs->init_registers(adev); /* remap HDP registers to a hole in mmio space, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c index b2d7cbd894c0..ec20cd5eb755 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c @@ -32,6 +32,7 @@ #include "mp/mp_15_0_8_sh_mask.h" MODULE_FIRMWARE("amdgpu/psp_15_0_8_toc.bin"); +MODULE_FIRMWARE("amdgpu/psp_15_0_8_toc_1.bin"); static int psp_v15_0_8_init_microcode(struct psp_context *psp) { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 0090ace49024..93ec52c1f367 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -828,7 +828,6 @@ static int sdma_v2_4_early_init(struct amdgpu_ip_block *ip_block) return r; sdma_v2_4_set_ring_funcs(adev); - sdma_v2_4_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v2_4_vm_pte_funcs); sdma_v2_4_set_irq_funcs(adev); @@ -898,7 +897,9 @@ static int sdma_v2_4_hw_init(struct amdgpu_ip_block *ip_block) if (r) return r; - return r; + sdma_v2_4_set_buffer_funcs(adev); + + return 0; } static int sdma_v2_4_hw_fini(struct amdgpu_ip_block *ip_block) @@ -1235,8 +1236,7 @@ static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = { static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v2_4_buffer_funcs); } const struct amdgpu_ip_block_version sdma_v2_4_ip_block = { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 2526d393162a..3fde9be74690 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1108,7 +1108,6 @@ static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block) return r; sdma_v3_0_set_ring_funcs(adev); - sdma_v3_0_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v3_0_vm_pte_funcs); sdma_v3_0_set_irq_funcs(adev); @@ -1184,7 +1183,9 @@ static int sdma_v3_0_hw_init(struct amdgpu_ip_block *ip_block) if (r) return r; - return r; + sdma_v3_0_set_buffer_funcs(adev); + + return 0; } static int sdma_v3_0_hw_fini(struct amdgpu_ip_block *ip_block) @@ -1677,8 +1678,7 @@ static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v3_0_buffer_funcs); } const struct amdgpu_ip_block_version sdma_v3_0_ip_block = diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 44f0f23e1148..cb64d17000df 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -889,7 +889,7 @@ static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se /* write the fence */ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); /* zero in first two bits */ - BUG_ON(addr & 0x3); + WARN_ON(addr & 0x3); amdgpu_ring_write(ring, lower_32_bits(addr)); amdgpu_ring_write(ring, upper_32_bits(addr)); amdgpu_ring_write(ring, lower_32_bits(seq)); @@ -899,7 +899,7 @@ static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se addr += 4; amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); /* zero in first two bits */ - BUG_ON(addr & 0x3); + WARN_ON(addr & 0x3); amdgpu_ring_write(ring, lower_32_bits(addr)); amdgpu_ring_write(ring, upper_32_bits(addr)); amdgpu_ring_write(ring, upper_32_bits(seq)); @@ -1775,7 +1775,6 @@ static int sdma_v4_0_early_init(struct amdgpu_ip_block *ip_block) adev->sdma.has_page_queue = true; sdma_v4_0_set_ring_funcs(adev); - sdma_v4_0_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_0_vm_pte_funcs); sdma_v4_0_set_irq_funcs(adev); sdma_v4_0_set_ras_funcs(adev); @@ -1961,6 +1960,7 @@ static int sdma_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) static int sdma_v4_0_hw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + int r; if (adev->flags & AMD_IS_APU) amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false, 0); @@ -1968,7 +1968,12 @@ static int sdma_v4_0_hw_init(struct amdgpu_ip_block *ip_block) if (!amdgpu_sriov_vf(adev)) sdma_v4_0_init_golden_registers(adev); - return sdma_v4_0_start(adev); + r = sdma_v4_0_start(adev); + if (r) + return r; + sdma_v4_0_set_buffer_funcs(adev); + + return 0; } static int sdma_v4_0_hw_fini(struct amdgpu_ip_block *ip_block) @@ -2626,13 +2631,9 @@ static const struct amdgpu_buffer_funcs sdma_v4_4_buffer_funcs = { static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) { if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >= IP_VERSION(4, 4, 0)) - adev->mman.buffer_funcs = &sdma_v4_4_buffer_funcs; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_4_buffer_funcs); else - adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; - if (adev->sdma.has_page_queue) - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; - else - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_0_buffer_funcs); } static void sdma_v4_0_get_ras_error_count(uint32_t value, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index 78bdfed0a7fd..88428b88e00f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1368,7 +1368,6 @@ static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) adev->sdma.has_page_queue = true; sdma_v4_4_2_set_ring_funcs(adev); - sdma_v4_4_2_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_4_2_vm_pte_funcs); sdma_v4_4_2_set_irq_funcs(adev); sdma_v4_4_2_set_ras_funcs(adev); @@ -1568,8 +1567,11 @@ static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block) sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); r = sdma_v4_4_2_inst_start(adev, inst_mask, false); + if (r) + return r; + sdma_v4_4_2_set_buffer_funcs(adev); - return r; + return 0; } static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block) @@ -2316,11 +2318,7 @@ static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs; - if (adev->sdma.has_page_queue) - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; - else - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_4_2_buffer_funcs); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 52f4e9e099cb..fa02907217e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1373,7 +1373,6 @@ static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block) return r; sdma_v5_0_set_ring_funcs(adev); - sdma_v5_0_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_0_vm_pte_funcs); sdma_v5_0_set_irq_funcs(adev); sdma_v5_0_set_mqd_funcs(adev); @@ -1472,8 +1471,11 @@ static int sdma_v5_0_hw_init(struct amdgpu_ip_block *ip_block) sdma_v5_0_init_golden_registers(adev); r = sdma_v5_0_start(adev); + if (r) + return r; + sdma_v5_0_set_buffer_funcs(adev); - return r; + return 0; } static int sdma_v5_0_hw_fini(struct amdgpu_ip_block *ip_block) @@ -2052,10 +2054,7 @@ static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = { static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) { - if (adev->mman.buffer_funcs == NULL) { - adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; - } + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v5_0_buffer_funcs); } const struct amdgpu_ip_block_version sdma_v5_0_ip_block = { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index b4fb90cc8f7d..f6ecbc524c9b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1264,7 +1264,6 @@ static int sdma_v5_2_early_init(struct amdgpu_ip_block *ip_block) return r; sdma_v5_2_set_ring_funcs(adev); - sdma_v5_2_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_2_vm_pte_funcs); sdma_v5_2_set_irq_funcs(adev); sdma_v5_2_set_mqd_funcs(adev); @@ -1385,8 +1384,14 @@ static int sdma_v5_2_sw_fini(struct amdgpu_ip_block *ip_block) static int sdma_v5_2_hw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + int r; - return sdma_v5_2_start(adev); + r = sdma_v5_2_start(adev); + if (r) + return r; + sdma_v5_2_set_buffer_funcs(adev); + + return 0; } static int sdma_v5_2_hw_fini(struct amdgpu_ip_block *ip_block) @@ -2056,10 +2061,7 @@ static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) { - if (adev->mman.buffer_funcs == NULL) { - adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; - } + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v5_2_buffer_funcs); } const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 0f530bb8a9a3..bf09ac841a68 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1313,7 +1313,6 @@ static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block) return r; sdma_v6_0_set_ring_funcs(adev); - sdma_v6_0_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v6_0_vm_pte_funcs); sdma_v6_0_set_irq_funcs(adev); sdma_v6_0_set_mqd_funcs(adev); @@ -1477,6 +1476,7 @@ static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block) r = sdma_v6_0_start(adev); if (r) return r; + sdma_v6_0_set_buffer_funcs(adev); return sdma_v6_0_set_userq_trap_interrupts(adev, true); } @@ -1662,17 +1662,8 @@ static int sdma_v6_0_process_fence_irq(struct amdgpu_device *adev, u32 doorbell_offset = entry->src_data[0]; if (adev->enable_mes && doorbell_offset) { - struct amdgpu_usermode_queue *queue; - struct xarray *xa = &adev->userq_doorbell_xa; - unsigned long flags; - doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; - - xa_lock_irqsave(xa, flags); - queue = xa_load(xa, doorbell_offset); - if (queue) - amdgpu_userq_fence_driver_process(queue->fence_drv); - xa_unlock_irqrestore(xa, flags); + amdgpu_userq_process_fence_irq(adev, doorbell_offset); } return 0; @@ -1895,8 +1886,7 @@ static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = { static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v6_0_buffer_funcs); } const struct amdgpu_ip_block_version sdma_v6_0_ip_block = { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 9ed817b69a3b..f154b68dda70 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1299,7 +1299,6 @@ static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block) } sdma_v7_0_set_ring_funcs(adev); - sdma_v7_0_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v7_0_vm_pte_funcs); sdma_v7_0_set_irq_funcs(adev); sdma_v7_0_set_mqd_funcs(adev); @@ -1432,6 +1431,7 @@ static int sdma_v7_0_hw_init(struct amdgpu_ip_block *ip_block) r = sdma_v7_0_start(adev); if (r) return r; + sdma_v7_0_set_buffer_funcs(adev); return sdma_v7_0_set_userq_trap_interrupts(adev, true); } @@ -1594,17 +1594,8 @@ static int sdma_v7_0_process_fence_irq(struct amdgpu_device *adev, u32 doorbell_offset = entry->src_data[0]; if (adev->enable_mes && doorbell_offset) { - struct xarray *xa = &adev->userq_doorbell_xa; - struct amdgpu_usermode_queue *queue; - unsigned long flags; - doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; - - xa_lock_irqsave(xa, flags); - queue = xa_load(xa, doorbell_offset); - if (queue) - amdgpu_userq_fence_driver_process(queue->fence_drv); - xa_unlock_irqrestore(xa, flags); + amdgpu_userq_process_fence_irq(adev, doorbell_offset); } return 0; @@ -1845,8 +1836,7 @@ static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = { static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &sdma_v7_0_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v7_0_buffer_funcs); } const struct amdgpu_ip_block_version sdma_v7_0_ip_block = { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c index 061934a2e93a..e1c0a4ff0e7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c @@ -1287,7 +1287,6 @@ static int sdma_v7_1_early_init(struct amdgpu_ip_block *ip_block) } sdma_v7_1_set_ring_funcs(adev); - sdma_v7_1_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v7_1_vm_pte_funcs); sdma_v7_1_set_irq_funcs(adev); sdma_v7_1_set_mqd_funcs(adev); @@ -1386,10 +1385,16 @@ static int sdma_v7_1_hw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; uint32_t inst_mask; + int r; inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); - return sdma_v7_1_inst_start(adev, inst_mask); + r = sdma_v7_1_inst_start(adev, inst_mask); + if (r) + return r; + sdma_v7_1_set_buffer_funcs(adev); + + return 0; } static int sdma_v7_1_hw_fini(struct amdgpu_ip_block *ip_block) @@ -1776,8 +1781,7 @@ static const struct amdgpu_buffer_funcs sdma_v7_1_buffer_funcs = { static void sdma_v7_1_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &sdma_v7_1_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v7_1_buffer_funcs); } const struct amdgpu_ip_block_version sdma_v7_1_ip_block = { diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 3e58feb2d5e4..549708075eb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -487,7 +487,6 @@ static int si_dma_early_init(struct amdgpu_ip_block *ip_block) adev->sdma.num_instances = SDMA_MAX_INSTANCE; si_dma_set_ring_funcs(adev); - si_dma_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &si_dma_vm_pte_funcs); si_dma_set_irq_funcs(adev); @@ -543,8 +542,14 @@ static int si_dma_sw_fini(struct amdgpu_ip_block *ip_block) static int si_dma_hw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + int r; - return si_dma_start(adev); + r = si_dma_start(adev); + if (r) + return r; + si_dma_set_buffer_funcs(adev); + + return 0; } static int si_dma_hw_fini(struct amdgpu_ip_block *ip_block) @@ -833,8 +838,7 @@ static const struct amdgpu_buffer_funcs si_dma_buffer_funcs = { static void si_dma_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &si_dma_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &si_dma_buffer_funcs); } const struct amdgpu_ip_block_version si_dma_ip_block = diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index b456e4541d9a..87b398dd0769 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -401,29 +401,12 @@ static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, }; -static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, - u32 sh_num, u32 reg_offset) -{ - uint32_t val; - - mutex_lock(&adev->grbm_idx_mutex); - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); - - val = RREG32(reg_offset); - - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); - mutex_unlock(&adev->grbm_idx_mutex); - return val; -} - static uint32_t soc15_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) { if (indexed) { - return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); + return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); } else { if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) return adev->gfx.config.gb_addr_config; @@ -695,15 +678,6 @@ static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk return 0; } -static void soc15_program_aspm(struct amdgpu_device *adev) -{ - if (!amdgpu_device_should_use_aspm(adev)) - return; - - if (adev->nbio.funcs->program_aspm) - adev->nbio.funcs->program_aspm(adev); -} - const struct amdgpu_ip_block_version vega10_common_ip_block = { .type = AMD_IP_BLOCK_TYPE_COMMON, @@ -1284,7 +1258,7 @@ static int soc15_common_hw_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; /* enable aspm */ - soc15_program_aspm(adev); + amdgpu_nbio_program_aspm(adev); /* setup nbio registers */ adev->nbio.funcs->init_registers(adev); /* remap HDP registers to a hole in mmio space, diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index fbd1d97f33ad..93c002e511c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -306,29 +306,12 @@ static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, }; -static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, - u32 sh_num, u32 reg_offset) -{ - uint32_t val; - - mutex_lock(&adev->grbm_idx_mutex); - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); - - val = RREG32(reg_offset); - - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); - mutex_unlock(&adev->grbm_idx_mutex); - return val; -} - static uint32_t soc21_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) { if (indexed) { - return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); + return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); } else { if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) return adev->gfx.config.gb_addr_config; @@ -470,15 +453,6 @@ static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk return 0; } -static void soc21_program_aspm(struct amdgpu_device *adev) -{ - if (!amdgpu_device_should_use_aspm(adev)) - return; - - if (adev->nbio.funcs->program_aspm) - adev->nbio.funcs->program_aspm(adev); -} - const struct amdgpu_ip_block_version soc21_common_ip_block = { .type = AMD_IP_BLOCK_TYPE_COMMON, .major = 1, @@ -925,7 +899,7 @@ static int soc21_common_hw_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; /* enable aspm */ - soc21_program_aspm(adev); + amdgpu_nbio_program_aspm(adev); /* setup nbio registers */ adev->nbio.funcs->init_registers(adev); /* remap HDP registers to a hole in mmio space, diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index d1adf19a51c4..265db9331d0b 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -132,31 +132,12 @@ static struct soc15_allowed_register_entry soc24_allowed_read_registers[] = { { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, }; -static uint32_t soc24_read_indexed_register(struct amdgpu_device *adev, - u32 se_num, - u32 sh_num, - u32 reg_offset) -{ - uint32_t val; - - mutex_lock(&adev->grbm_idx_mutex); - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); - - val = RREG32(reg_offset); - - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); - mutex_unlock(&adev->grbm_idx_mutex); - return val; -} - static uint32_t soc24_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) { if (indexed) { - return soc24_read_indexed_register(adev, se_num, sh_num, reg_offset); + return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); } else { if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index 709b1669b07b..5f05c8e68297 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -184,31 +184,13 @@ static struct soc15_allowed_register_entry soc_v1_0_allowed_read_registers[] = { { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG_1) }, }; -static uint32_t soc_v1_0_read_indexed_register(struct amdgpu_device *adev, - u32 se_num, - u32 sh_num, - u32 reg_offset) -{ - uint32_t val; - - mutex_lock(&adev->grbm_idx_mutex); - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); - - val = RREG32(reg_offset); - - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); - mutex_unlock(&adev->grbm_idx_mutex); - return val; -} static uint32_t soc_v1_0_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) { if (indexed) { - return soc_v1_0_read_indexed_register(adev, se_num, sh_num, reg_offset); + return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); } else { if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG_1) && adev->gfx.config.gb_addr_config) @@ -330,6 +312,8 @@ static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) return -EINVAL; } + adev->nbio.funcs->init_registers(adev); + return 0; } @@ -737,15 +721,8 @@ static int soc_v1_0_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, num_xcc_per_xcp = __soc_v1_0_get_xcc_per_xcp(xcp_mgr, mode); if (adev->gfx.imu.funcs && - adev->gfx.imu.funcs->switch_compute_partition) { - ret = adev->gfx.imu.funcs->switch_compute_partition(xcp_mgr->adev, num_xcc_per_xcp, mode); - if (ret) - goto out; - } - if (adev->gfx.imu.funcs && - adev->gfx.imu.funcs->init_mcm_addr_lut && - amdgpu_emu_mode) - adev->gfx.imu.funcs->init_mcm_addr_lut(adev); + adev->gfx.imu.funcs->switch_compute_partition) + adev->gfx.imu.funcs->switch_compute_partition(xcp_mgr->adev, num_xcc_per_xcp, mode); /* Init info about new xcps */ *num_xcps = num_xcc / num_xcc_per_xcp; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index fea576a7f397..efb3fde919ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -242,6 +242,10 @@ static void uvd_v3_1_mc_resume(struct amdgpu_device *adev) uint64_t addr; uint32_t size; + /* When the keyselect is already set, don't perturb it. */ + if (RREG32(mmUVD_FW_START)) + return; + /* program the VCPU memory controller bits 0-27 */ addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3; @@ -284,6 +288,12 @@ static int uvd_v3_1_fw_validate(struct amdgpu_device *adev) int i; uint32_t keysel = adev->uvd.keyselect; + if (RREG32(mmUVD_FW_START) & UVD_FW_STATUS__PASS_MASK) { + dev_dbg(adev->dev, "UVD keyselect already set: 0x%x (on CPU: 0x%x)\n", + RREG32(mmUVD_FW_START), adev->uvd.keyselect); + return 0; + } + WREG32(mmUVD_FW_START, keysel); for (i = 0; i < 10; ++i) { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index e35fae9cdaf6..0442bfcfd384 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -2113,6 +2113,7 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_DEC, .align_mask = 0xf, + .no_user_fence = true, .secure_submission_supported = true, .get_rptr = vcn_v2_0_dec_ring_get_rptr, .get_wptr = vcn_v2_0_dec_ring_get_wptr, @@ -2145,6 +2146,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v2_0_enc_ring_get_rptr, .get_wptr = vcn_v2_0_enc_ring_get_wptr, .set_wptr = vcn_v2_0_enc_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 006a15451197..8b8184fe6764 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -1778,6 +1778,7 @@ static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_DEC, .align_mask = 0xf, + .no_user_fence = true, .secure_submission_supported = true, .get_rptr = vcn_v2_5_dec_ring_get_rptr, .get_wptr = vcn_v2_5_dec_ring_get_wptr, @@ -1879,6 +1880,7 @@ static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v2_5_enc_ring_get_rptr, .get_wptr = vcn_v2_5_enc_ring_get_wptr, .set_wptr = vcn_v2_5_enc_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 6fb4fcdbba4f..81bba3ec2a93 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -1856,6 +1856,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_DEC, .align_mask = 0x3f, .nop = VCN_DEC_SW_CMD_NO_OP, + .no_user_fence = true, .secure_submission_supported = true, .get_rptr = vcn_v3_0_dec_ring_get_rptr, .get_wptr = vcn_v3_0_dec_ring_get_wptr, @@ -1972,6 +1973,7 @@ static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { uint32_t offset, size, *create; + uint64_t buf_end; if (msg[0] != RDECODE_MESSAGE_CREATE) continue; @@ -1979,7 +1981,8 @@ static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, offset = msg[1]; size = msg[2]; - if (size < 4 || offset + size > end - addr) { + if (size < 4 || check_add_overflow(offset, size, &buf_end) || + buf_end > end - addr) { DRM_ERROR("VCN message buffer exceeds BO bounds!\n"); r = -EINVAL; goto out; @@ -2036,6 +2039,7 @@ static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_DEC, .align_mask = 0xf, + .no_user_fence = true, .secure_submission_supported = true, .get_rptr = vcn_v3_0_dec_ring_get_rptr, .get_wptr = vcn_v3_0_dec_ring_get_wptr, @@ -2138,6 +2142,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v3_0_enc_ring_get_rptr, .get_wptr = vcn_v3_0_enc_ring_get_wptr, .set_wptr = vcn_v3_0_enc_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 5dec92691f73..ff7269bafae8 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -1889,6 +1889,7 @@ static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { uint32_t offset, size, *create; + uint64_t buf_end; if (msg[0] != RDECODE_MESSAGE_CREATE) continue; @@ -1896,7 +1897,8 @@ static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, offset = msg[1]; size = msg[2]; - if (size < 4 || offset + size > end - addr) { + if (size < 4 || check_add_overflow(offset, size, &buf_end) || + buf_end > end - addr) { DRM_ERROR("VCN message buffer exceeds BO bounds!\n"); r = -EINVAL; goto out; @@ -1994,6 +1996,7 @@ static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .extra_bytes = sizeof(struct amdgpu_vcn_rb_metadata), .get_rptr = vcn_v4_0_unified_ring_get_rptr, .get_wptr = vcn_v4_0_unified_ring_get_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index ff3013b97abd..10e8fc2821f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -1775,6 +1775,7 @@ static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v4_0_3_unified_ring_get_rptr, .get_wptr = vcn_v4_0_3_unified_ring_get_wptr, .set_wptr = vcn_v4_0_3_unified_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 1f6a22983c0d..1571cc5a148c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -1483,6 +1483,7 @@ static struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v4_0_5_unified_ring_get_rptr, .get_wptr = vcn_v4_0_5_unified_ring_get_wptr, .set_wptr = vcn_v4_0_5_unified_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 6109124f852e..d5f49fa33bee 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -1207,6 +1207,7 @@ static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v5_0_0_unified_ring_get_rptr, .get_wptr = vcn_v5_0_0_unified_ring_get_wptr, .set_wptr = vcn_v5_0_0_unified_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index c28c6aff17aa..54fbf8d73ca6 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -1419,6 +1419,7 @@ static const struct amdgpu_ring_funcs vcn_v5_0_1_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v5_0_1_unified_ring_get_rptr, .get_wptr = vcn_v5_0_1_unified_ring_get_wptr, .set_wptr = vcn_v5_0_1_unified_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c index c3d3cc023058..bbc172db91a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c @@ -994,6 +994,7 @@ static const struct amdgpu_ring_funcs vcn_v5_0_2_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v5_0_2_unified_ring_get_rptr, .get_wptr = vcn_v5_0_2_unified_ring_get_wptr, .set_wptr = vcn_v5_0_2_unified_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 55ea5145a28a..dd27d7ba2ee2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -146,11 +147,6 @@ static int kfd_open(struct inode *inode, struct file *filep) if (IS_ERR(process)) return PTR_ERR(process); - if (kfd_process_init_cwsr_apu(process, filep)) { - kfd_unref_process(process); - return -EFAULT; - } - /* filep now owns the reference returned by kfd_create_process */ filep->private_data = process; @@ -1359,7 +1355,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); if (WARN_ON_ONCE(!peer_pdd)) continue; - kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY); + kfd_flush_tlb(peer_pdd); } kfree(devices_arr); @@ -1454,7 +1450,7 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, if (WARN_ON_ONCE(!peer_pdd)) continue; if (flush_tlb) - kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT); + kfd_flush_tlb(peer_pdd); /* Remove dma mapping after tlb flush to avoid IO_PAGE_FAULT */ err = amdgpu_amdkfd_gpuvm_dmaunmap_mem(mem, peer_pdd->drm_priv); @@ -1695,6 +1691,16 @@ static int kfd_ioctl_smi_events(struct file *filep, return kfd_smi_event_open(pdd->dev, &args->anon_fd); } +static int kfd_ioctl_svm_validate(void *kdata, unsigned int usize) +{ + struct kfd_ioctl_svm_args *args = kdata; + size_t expected = struct_size(args, attrs, args->nattr); + + if (expected == SIZE_MAX || usize < expected) + return -EINVAL; + return 0; +} + #if IS_ENABLED(CONFIG_HSA_AMD_SVM) static int kfd_ioctl_set_xnack_mode(struct file *filep, @@ -2329,6 +2335,9 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, const bool criu_resume = true; u64 offset; + if (bo_priv->idr_handle > INT_MAX) + return -EINVAL; + if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { if (bo_bucket->size != kfd_doorbell_process_slice(pdd->dev->kfd)) @@ -3209,7 +3218,11 @@ static int kfd_ioctl_create_process(struct file *filep, struct kfd_process *p, v #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ - .cmd_drv = 0, .name = #ioctl} + .validate = NULL, .cmd_drv = 0, .name = #ioctl} + +#define AMDKFD_IOCTL_DEF_V(ioctl, _func, _validate, _flags) \ + [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ + .validate = _validate, .cmd_drv = 0, .name = #ioctl} /** Ioctl table */ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { @@ -3306,7 +3319,8 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS, kfd_ioctl_smi_events, 0), - AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0), + AMDKFD_IOCTL_DEF_V(AMDKFD_IOC_SVM, kfd_ioctl_svm, + kfd_ioctl_svm_validate, 0), AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE, kfd_ioctl_set_xnack_mode, 0), @@ -3431,6 +3445,12 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) memset(kdata, 0, usize); } + if (ioctl->validate) { + retcode = ioctl->validate(kdata, usize); + if (retcode) + goto err_i1; + } + retcode = func(filep, process, kdata); if (cmd & IOC_OUT) @@ -3515,9 +3535,8 @@ static int kfd_mmap(struct file *filep, struct vm_area_struct *vma) return kfd_event_mmap(process, vma); case KFD_MMAP_TYPE_RESERVED_MEM: - if (!dev) - return -ENODEV; - return kfd_reserved_mem_mmap(dev, process, vma); + pr_warn("KFD_MMAP_TYPE_RESERVED_MEM is no longer supported\n"); + return -EINVAL; case KFD_MMAP_TYPE_MMIO: if (!dev) return -ENODEV; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 8ff97bf7d95a..b7f8f7ff8198 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -1737,37 +1737,6 @@ bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entr return false; } -/* check if there is kfd process still uses adev */ -static bool kgd2kfd_check_device_idle(struct amdgpu_device *adev) -{ - struct kfd_process *p; - struct hlist_node *p_temp; - unsigned int temp; - struct kfd_node *dev; - - mutex_lock(&kfd_processes_mutex); - - if (hash_empty(kfd_processes_table)) { - mutex_unlock(&kfd_processes_mutex); - return true; - } - - /* check if there is device still use adev */ - hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { - for (int i = 0; i < p->n_pdds; i++) { - dev = p->pdds[i]->dev; - if (dev->adev == adev) { - mutex_unlock(&kfd_processes_mutex); - return false; - } - } - } - - mutex_unlock(&kfd_processes_mutex); - - return true; -} - /** kgd2kfd_teardown_processes - gracefully tear down existing * kfd processes that use adev * @@ -1800,7 +1769,7 @@ void kgd2kfd_teardown_processes(struct amdgpu_device *adev) mutex_unlock(&kfd_processes_mutex); /* wait all kfd processes use adev terminate */ - while (!kgd2kfd_check_device_idle(adev)) + while (!!atomic_read(&adev->kfd.dev->kfd_processes_count)) cond_resched(); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index ab3b2e7be9bd..a9ac575537e5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -71,6 +71,12 @@ static int allocate_sdma_queue(struct device_queue_manager *dqm, struct queue *q, const uint32_t *restore_sdma_id); static int reset_queues_on_hws_hang(struct device_queue_manager *dqm, bool is_sdma); +static int resume_all_queues_mes(struct device_queue_manager *dqm); +static int suspend_all_queues_mes(struct device_queue_manager *dqm); +static struct queue *find_queue_by_doorbell_offset(struct device_queue_manager *dqm, + u32 doorbell_offset); +static void set_queue_as_reset(struct device_queue_manager *dqm, struct queue *q, + struct qcm_process_device *qpd); static inline enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type) @@ -273,13 +279,19 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, return r; } -static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, - struct qcm_process_device *qpd) +static int remove_queue_mes_on_reset_option(struct device_queue_manager *dqm, struct queue *q, + struct qcm_process_device *qpd, + bool is_for_reset, + bool flush_mes_queue) { struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; int r; struct mes_remove_queue_input queue_input; + /* queue was already removed during reset */ + if (q->properties.is_reset) + return 0; + if (!dqm->sched_running || dqm->sched_halt) return 0; if (!down_read_trylock(&adev->reset_domain->sem)) @@ -288,6 +300,7 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); queue_input.doorbell_offset = q->properties.doorbell_off; queue_input.gang_context_addr = q->gang_ctx_gpu_addr; + queue_input.remove_queue_after_reset = flush_mes_queue; queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; amdgpu_mes_lock(&adev->mes); @@ -295,7 +308,13 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, amdgpu_mes_unlock(&adev->mes); up_read(&adev->reset_domain->sem); + if (is_for_reset) + return r; + if (r) { + if (!suspend_all_queues_mes(dqm)) + return resume_all_queues_mes(dqm); + dev_err(adev->dev, "failed to remove hardware queue from MES, doorbell=0x%x\n", q->properties.doorbell_off); dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); @@ -305,6 +324,12 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, return r; } +static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, + struct qcm_process_device *qpd) +{ + return remove_queue_mes_on_reset_option(dqm, q, qpd, false, false); +} + static int remove_all_kfd_queues_mes(struct device_queue_manager *dqm) { struct device_process_node *cur; @@ -359,6 +384,92 @@ static int add_all_kfd_queues_mes(struct device_queue_manager *dqm) return retval; } +static int reset_queues_mes(struct device_queue_manager *dqm) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; + int hqd_info_size = adev->mes.hung_queue_hqd_info_offset; + int num_hung = 0, r = 0, i, pipe, queue, queue_type; + u32 *hung_array = dqm->hung_db_array; + struct amdgpu_mes_hung_queue_hqd_info *hqd_info = dqm->hqd_info; + struct kfd_process_device *pdd; + struct queue *q; + + if (!amdgpu_mes_queue_reset_by_mes_supported(adev)) { + r = -ENOTRECOVERABLE; + goto fail; + } + + /* reset should be used only in dqm locked queue reset */ + if (WARN_ON(dqm->detect_hang_count > 0)) + return 0; + + if (!amdgpu_gpu_recovery) { + r = -ENOTRECOVERABLE; + goto fail; + } + + if (!hung_array || !hqd_info) { + r = -ENOMEM; + goto fail; + } + + memset(hqd_info, 0, hqd_info_size * sizeof(struct amdgpu_mes_hung_queue_hqd_info)); + + /* + * AMDGPU_RING_TYPE_COMPUTE parameter does not matter if called + * post suspend_all as reset & detect will return all hung queue types. + * + * Passed parameter is for targeting queues not scheduled by MES add_queue. + */ + r = amdgpu_mes_detect_and_reset_hung_queues(adev, AMDGPU_RING_TYPE_COMPUTE, + false, &num_hung, hung_array, ffs(dqm->dev->xcc_mask) - 1); + + if (!num_hung || r) { + r = -ENOTRECOVERABLE; + goto fail; + } + + /* MES resets queue/pipe and cleans up internally */ + for (i = 0; i < num_hung; i++) { + hqd_info[i].bit0_31 = hung_array[i + hqd_info_size]; + pipe = hqd_info[i].pipe_index; + queue = hqd_info[i].queue_index; + queue_type = hqd_info[i].queue_type; + + if (queue_type != MES_QUEUE_TYPE_COMPUTE && + queue_type != MES_QUEUE_TYPE_SDMA) { + pr_warn("Unsupported hung queue reset type: %d\n", queue_type); + hung_array[i] = AMDGPU_MES_INVALID_DB_OFFSET; + continue; + } + + q = find_queue_by_doorbell_offset(dqm, hung_array[i]); + if (!q) { + r = -ENOTRECOVERABLE; + goto fail; + } + + pdd = kfd_get_process_device_data(q->device, q->process); + if (!pdd) { + r = -ENODEV; + goto fail; + } + + pr_warn("Hang detected doorbell %x pipe %d queue %d type %d\n", + hung_array[i], pipe, queue, queue_type); + /* Proceed remove_queue with reset=true */ + remove_queue_mes_on_reset_option(dqm, q, &pdd->qpd, true, false); + set_queue_as_reset(dqm, q, &pdd->qpd); + } + + dqm->detect_hang_count = num_hung; + kfd_signal_reset_event(dqm->dev); + +fail: + dqm->detect_hang_count = 0; + return r; +} + static int suspend_all_queues_mes(struct device_queue_manager *dqm) { struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; @@ -367,10 +478,13 @@ static int suspend_all_queues_mes(struct device_queue_manager *dqm) if (!down_read_trylock(&adev->reset_domain->sem)) return -EIO; - r = amdgpu_mes_suspend(adev); + r = amdgpu_mes_suspend(adev, ffs(dqm->dev->xcc_mask) - 1); up_read(&adev->reset_domain->sem); if (r) { + if (!reset_queues_mes(dqm)) + return 0; + dev_err(adev->dev, "failed to suspend gangs from MES\n"); dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); kfd_hws_hang(dqm); @@ -387,7 +501,7 @@ static int resume_all_queues_mes(struct device_queue_manager *dqm) if (!down_read_trylock(&adev->reset_domain->sem)) return -EIO; - r = amdgpu_mes_resume(adev); + r = amdgpu_mes_resume(adev, ffs(dqm->dev->xcc_mask) - 1); up_read(&adev->reset_domain->sem); if (r) { @@ -572,7 +686,7 @@ static int allocate_vmid(struct device_queue_manager *dqm, qpd->vmid, qpd->page_table_base); /* invalidate the VM context after pasid and vmid mapping is set up */ - kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); + kfd_flush_tlb(qpd_to_pdd(qpd)); if (dqm->dev->kfd2kgd->set_scratch_backing_va) dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->adev, @@ -610,7 +724,7 @@ static void deallocate_vmid(struct device_queue_manager *dqm, if (flush_texture_cache_nocpsch(q->device, qpd)) dev_err(dev, "Failed to flush TC\n"); - kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); + kfd_flush_tlb(qpd_to_pdd(qpd)); /* Release the vmid mapping */ set_pasid_vmid_mapping(dqm, 0, qpd->vmid); @@ -1284,7 +1398,7 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm, dqm->dev->adev, qpd->vmid, qpd->page_table_base); - kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY); + kfd_flush_tlb(pdd); } /* Take a safe reference to the mm_struct, which may otherwise @@ -1821,6 +1935,9 @@ static int start_cpsch(struct device_queue_manager *dqm) { struct device *dev = dqm->dev->adev->dev; int retval, num_hw_queue_slots; + struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; + int hung_array_size = amdgpu_mes_get_hung_queue_db_array_size(adev); + int hqd_info_size = adev->mes.hung_queue_hqd_info_offset; dqm_lock(dqm); @@ -1870,6 +1987,11 @@ static int start_cpsch(struct device_queue_manager *dqm) goto fail_detect_hang_buffer; } + dqm->hung_db_array = kzalloc(hung_array_size * sizeof(u32), GFP_KERNEL); + dqm->hqd_info = kzalloc( + hqd_info_size * sizeof(struct amdgpu_mes_hung_queue_hqd_info), + GFP_KERNEL); + dqm_unlock(dqm); return 0; @@ -1910,6 +2032,9 @@ static int stop_cpsch(struct device_queue_manager *dqm) pm_uninit(&dqm->packet_mgr); kfree(dqm->detect_hang_info); dqm->detect_hang_info = NULL; + kfree(dqm->hung_db_array); + kfree(dqm->hqd_info); + dqm_unlock(dqm); return ret; @@ -2137,6 +2262,7 @@ static void set_queue_as_reset(struct device_queue_manager *dqm, struct queue *q q->properties.queue_id, pdd->process->lead_thread->pid); pdd->has_reset_queue = true; + q->properties.is_reset = true; if (q->properties.is_active) { q->properties.is_active = false; decrement_queue_count(dqm, qpd, q); @@ -2203,6 +2329,23 @@ static struct queue *find_queue_by_address(struct device_queue_manager *dqm, uin return NULL; } +static struct queue *find_queue_by_doorbell_offset(struct device_queue_manager *dqm, u32 doorbell_offset) +{ + struct device_process_node *cur; + struct qcm_process_device *qpd; + struct queue *q; + + list_for_each_entry(cur, &dqm->queues, list) { + qpd = cur->qpd; + list_for_each_entry(q, &qpd->queues_list, list) { + if (doorbell_offset == q->properties.doorbell_off) + return q; + } + } + + return NULL; +} + static int reset_hung_queues(struct device_queue_manager *dqm) { int r = 0, reset_count = 0, i; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 3272328da11f..a0323501c6b9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -32,7 +32,6 @@ #include "kfd_priv.h" #include "kfd_mqd_manager.h" - #define VMID_NUM 16 #define KFD_MES_PROCESS_QUANTUM 100000 @@ -285,6 +284,9 @@ struct device_queue_manager { struct dqm_detect_hang_info *detect_hang_info; size_t detect_hang_info_size; int detect_hang_count; + /* for per-queue reset with mes */ + u32 *hung_db_array; + struct amdgpu_mes_hung_queue_hqd_info *hqd_info; }; void device_queue_manager_init_cik( diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c index 9e70a5f8a50b..525989371378 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c @@ -54,6 +54,7 @@ static int update_qpd_v12_1(struct device_queue_manager *dqm, struct kfd_process_device *pdd; struct amdgpu_device *adev = dqm->dev->adev; struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; + bool xnack_enabled; pdd = qpd_to_pdd(qpd); qpd->vm_cntx_cntl = hub->vm_cntx_cntl; @@ -71,16 +72,18 @@ static int update_qpd_v12_1(struct device_queue_manager *dqm, qpd->sh_mem_ape1_base = 0; } - if (KFD_SUPPORT_XNACK_PER_PROCESS(dqm->dev)) { - if (!pdd->process->xnack_enabled) { - qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; - qpd->vm_cntx_cntl &= + xnack_enabled = KFD_SUPPORT_XNACK_PER_PROCESS(dqm->dev) ? + pdd->process->xnack_enabled : + !pdd->dev->kfd->noretry; + + if (!xnack_enabled) { + qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; + qpd->vm_cntx_cntl &= ~(1 << GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT); - } else { - qpd->sh_mem_config &= ~(1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT); - qpd->vm_cntx_cntl |= + } else { + qpd->sh_mem_config &= ~(1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT); + qpd->vm_cntx_cntl |= (1 << GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT); - } } qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 44150a71ffd5..a11c4ab3aafd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -483,6 +483,11 @@ int kfd_criu_restore_event(struct file *devkfd, } *priv_data_offset += sizeof(*ev_priv); + if (ev_priv->event_id > INT_MAX) { + ret = -EINVAL; + goto exit; + } + if (ev_priv->user_handle) { ret = kfd_kmap_event_page(p, ev_priv->user_handle); if (ret) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 964efa325908..28dc6886c1ff 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -129,13 +129,14 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys, struct dma_fence **mfence) { const u64 GTT_MAX_PAGES = AMDGPU_GTT_MAX_TRANSFER_SIZE; - struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; + struct amdgpu_ring *ring; struct amdgpu_ttm_buffer_entity *entity; u64 gart_s, gart_d; struct dma_fence *next; u64 size; int r; + ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); entity = &adev->mman.move_entities[0]; mutex_lock(&entity->lock); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c index c90c0d99b1e3..475589b924e9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c @@ -32,6 +32,10 @@ #include "amdgpu_amdkfd.h" #include "kfd_device_queue_manager.h" +static void update_mqd(struct mqd_manager *mm, void *mqd, + struct queue_properties *q, + struct mqd_update_info *minfo); + static inline struct v12_1_compute_mqd *get_mqd(void *mqd) { return (struct v12_1_compute_mqd *)mqd; @@ -215,7 +219,7 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, *mqd = m; if (gart_addr) *gart_addr = addr; - mm->update_mqd(mm, m, q, NULL); + update_mqd(mm, m, q, NULL); } static int load_mqd(struct mqd_manager *mm, void *mqd, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 6e333bfa17d6..9fe5c66d8013 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -215,8 +215,7 @@ enum cache_policy { ((KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) || \ (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) || \ (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) || \ - (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) || \ - (KFD_GC_VERSION(dev) == IP_VERSION(12, 1, 0))) + (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0))) struct kfd_node; @@ -523,6 +522,7 @@ struct queue_properties { uint32_t pm4_target_xcc; bool is_dbg_wa; bool is_user_cu_masked; + bool is_reset; /* Not relevant for user mode queues in cp scheduling */ unsigned int vmid; /* Relevant only for sdma queues*/ @@ -986,9 +986,6 @@ struct kfd_process { struct kobject *kobj_queues; struct attribute attr_pasid; - /* Keep track cwsr init */ - bool has_cwsr; - /* Exception code enable mask and status */ uint64_t exception_enable_mask; uint64_t exception_status; @@ -1047,10 +1044,13 @@ extern struct srcu_struct kfd_processes_srcu; typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p, void *data); +typedef int amdkfd_ioctl_validate_t(void *kdata, unsigned int usize); + struct amdkfd_ioctl_desc { unsigned int cmd; int flags; amdkfd_ioctl_t *func; + amdkfd_ioctl_validate_t *validate; unsigned int cmd_drv; const char *name; }; @@ -1101,8 +1101,6 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, bool kfd_process_xnack_mode(struct kfd_process *p, bool supported); -int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process, - struct vm_area_struct *vma); void kfd_process_notifier_release_internal(struct kfd_process *p); /* KFD process API for creating and translating handles */ @@ -1219,9 +1217,6 @@ void kfd_process_set_trap_handler(struct qcm_process_device *qpd, void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, bool enabled); -/* CWSR initialization */ -int kfd_process_init_cwsr_apu(struct kfd_process *process, struct file *filep); - /* CRIU */ /* * Need to increment KFD_CRIU_PRIV_VERSION each time a change is made to any of the CRIU private @@ -1551,13 +1546,13 @@ void kfd_signal_reset_event(struct kfd_node *dev); void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid); void kfd_signal_process_terminate_event(struct kfd_process *p); -static inline void kfd_flush_tlb(struct kfd_process_device *pdd, - enum TLB_FLUSH_TYPE type) +static inline void kfd_flush_tlb(struct kfd_process_device *pdd) { struct amdgpu_device *adev = pdd->dev->adev; struct amdgpu_vm *vm = drm_priv_to_vm(pdd->drm_priv); - amdgpu_vm_flush_compute_tlb(adev, vm, type, pdd->dev->xcc_mask); + amdgpu_vm_flush_compute_tlb(adev, vm, TLB_FLUSH_HEAVYWEIGHT, + pdd->dev->xcc_mask); } static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index d28ca581cad0..9228e4a949ed 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1409,50 +1409,6 @@ void kfd_cleanup_processes(void) mmu_notifier_synchronize(); } -int kfd_process_init_cwsr_apu(struct kfd_process *p, struct file *filep) -{ - unsigned long offset; - int i; - - if (p->has_cwsr) - return 0; - - for (i = 0; i < p->n_pdds; i++) { - struct kfd_node *dev = p->pdds[i]->dev; - struct qcm_process_device *qpd = &p->pdds[i]->qpd; - - if (!dev->kfd->cwsr_enabled || qpd->cwsr_kaddr || qpd->cwsr_base) - continue; - - offset = KFD_MMAP_TYPE_RESERVED_MEM | KFD_MMAP_GPU_ID(dev->id); - qpd->tba_addr = (int64_t)vm_mmap(filep, 0, - KFD_CWSR_TBA_TMA_SIZE, PROT_READ | PROT_EXEC, - MAP_SHARED, offset); - - if (IS_ERR_VALUE(qpd->tba_addr)) { - int err = qpd->tba_addr; - - dev_err(dev->adev->dev, - "Failure to set tba address. error %d.\n", err); - qpd->tba_addr = 0; - qpd->cwsr_kaddr = NULL; - return err; - } - - memcpy(qpd->cwsr_kaddr, dev->kfd->cwsr_isa, dev->kfd->cwsr_isa_size); - - kfd_process_set_trap_debug_flag(qpd, p->debug_trap_enabled); - - qpd->tma_addr = qpd->tba_addr + KFD_CWSR_TMA_OFFSET; - pr_debug("set tba :0x%llx, tma:0x%llx, cwsr_kaddr:%p for pqm.\n", - qpd->tba_addr, qpd->tma_addr, qpd->cwsr_kaddr); - } - - p->has_cwsr = true; - - return 0; -} - static int kfd_process_device_init_cwsr_dgpu(struct kfd_process_device *pdd) { struct kfd_node *dev = pdd->dev; @@ -2228,38 +2184,6 @@ int kfd_resume_all_processes(void) return ret; } -int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process, - struct vm_area_struct *vma) -{ - struct kfd_process_device *pdd; - struct qcm_process_device *qpd; - - if ((vma->vm_end - vma->vm_start) != KFD_CWSR_TBA_TMA_SIZE) { - dev_err(dev->adev->dev, "Incorrect CWSR mapping size.\n"); - return -EINVAL; - } - - pdd = kfd_get_process_device_data(dev, process); - if (!pdd) - return -EINVAL; - qpd = &pdd->qpd; - - qpd->cwsr_kaddr = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, - get_order(KFD_CWSR_TBA_TMA_SIZE)); - if (!qpd->cwsr_kaddr) { - dev_err(dev->adev->dev, - "Error allocating per process CWSR buffer.\n"); - return -ENOMEM; - } - - vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND - | VM_NORESERVE | VM_DONTDUMP | VM_PFNMAP); - /* Mapping pages to user process */ - return remap_pfn_range(vma, vma->vm_start, - PFN_DOWN(__pa(qpd->cwsr_kaddr)), - KFD_CWSR_TBA_TMA_SIZE, vma->vm_page_prot); -} - /* assumes caller holds process lock. */ int kfd_process_drain_interrupts(struct kfd_process_device *pdd) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index b120fdb0ef77..35ec67d9739b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1366,6 +1366,12 @@ svm_range_unmap_from_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm, pr_debug("CPU[0x%llx 0x%llx] -> GPU[0x%llx 0x%llx]\n", start, last, gpu_start, gpu_end); + + if (!amdgpu_vm_ready(vm)) { + pr_debug("VM not ready, canceling unmap\n"); + return -EINVAL; + } + return amdgpu_vm_update_range(adev, vm, false, true, true, false, NULL, gpu_start, gpu_end, init_pte_value, 0, 0, NULL, NULL, fence); @@ -1418,7 +1424,7 @@ svm_range_unmap_from_gpus(struct svm_range *prange, unsigned long start, if (r) break; } - kfd_flush_tlb(pdd, TLB_FLUSH_HEAVYWEIGHT); + kfd_flush_tlb(pdd); } return r; @@ -1443,6 +1449,11 @@ svm_range_map_to_gpu(struct kfd_process_device *pdd, struct svm_range *prange, pr_debug("svms 0x%p [0x%lx 0x%lx] readonly %d\n", prange->svms, last_start, last_start + npages - 1, readonly); + if (!amdgpu_vm_ready(vm)) { + pr_debug("VM not ready, canceling map\n"); + return -EINVAL; + } + for (i = offset; i < offset + npages; i++) { uint64_t gpu_start; uint64_t gpu_end; @@ -1560,7 +1571,7 @@ svm_range_map_to_gpus(struct svm_range *prange, unsigned long offset, } } - kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY); + kfd_flush_tlb(pdd); } return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 29dee26261ab..46db0d65d242 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -2027,6 +2027,7 @@ static void kfd_topology_set_capabilities(struct kfd_topology_device *dev) if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(12, 1, 0)) { dev->node_props.capability |= HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED; + dev->node_props.capability |= HSA_CAP_PER_QUEUE_RESET_SUPPORTED; dev->node_props.capability2 |= HSA_CAP2_TRAP_DEBUG_LDS_OUT_OF_ADDR_RANGE_SUPPORTED; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e96a12ff2d31..d590f0df6abd 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -104,6 +104,7 @@ #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" #include "modules/inc/mod_freesync.h" +#include "modules/inc/mod_power.h" #include "modules/power/power_helpers.h" static_assert(AMDGPU_DMUB_NOTIFICATION_MAX == DMUB_NOTIFICATION_MAX, "AMDGPU_DMUB_NOTIFICATION_MAX mismatch"); @@ -232,11 +233,11 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev, static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); -static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state); -static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); +static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state); +static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state); static int amdgpu_dm_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); static void handle_hpd_rx_irq(void *param); @@ -1881,6 +1882,70 @@ static enum dmub_ips_disable_type dm_get_default_ips_mode( return ret; } +static int amdgpu_dm_init_power_module(struct amdgpu_display_manager *dm) +{ + struct mod_power_init_params init_data[MAX_NUM_EDP]; + + if (dm->num_of_edps == 0) { + drm_dbg_driver( + dm->ddev, + "amdgpu: No eDP detected, skip initializing power module\n"); + return 0; + } + + /* Initialize all the power module parameters */ + for (int i = 0; i < dm->num_of_edps; i++) { + init_data[i].allow_psr_smu_optimizations = + !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT); + init_data[i].allow_psr_multi_disp_optimizations = + !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); + /* See dm_late_init */ + init_data[i].backlight_ramping_override = false; + init_data[i].backlight_ramping_start = 0xCCCC; + init_data[i].backlight_ramping_reduction = 0xCCCCCCCC; + init_data[i].def_varibright_level = 0; + init_data[i].abm_config_setting = 0; + init_data[i].num_backlight_levels = 101; + init_data[i].use_nits_based_brightness = false; + init_data[i].panel_max_millinits = 0; + init_data[i].panel_min_millinits = 0; + init_data[i].disable_fractional_pwm = + !(amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK); + init_data[i].use_custom_backlight_caps = false; + init_data[i].custom_backlight_caps_config_no = 0; + init_data[i].use_linear_backlight_curve = false; + init_data[i].def_varibright_enable = 0; + init_data[i].varibright_level = 0; + /* + * Power module uses 16-bit backlight levels (0xFFFF max) rather + * than 8-bit(0XFF max) + */ + init_data[i].min_backlight_pwm = + dm->backlight_caps[i].min_input_signal * 0x101; + init_data[i].max_backlight_pwm = + dm->backlight_caps[i].max_input_signal * 0x101; + init_data[i].min_abm_backlight = + dm->backlight_caps[i].min_input_signal * 0x101; + + /* Min backlight level after ABM reduction, Don't allow below 1% + * 0xFFFF x 0.01 = 0x28F + */ + init_data[i].min_abm_backlight = (init_data[i].min_abm_backlight < 0x28F) ? + 0x28F : init_data[i].min_abm_backlight; + } + + dm->power_module = mod_power_create(dm->dc, init_data, dm->num_of_edps); + if (!dm->power_module) { + drm_err(dm->ddev, "amdgpu: Error allocating memory for power module\n"); + return -ENOMEM; + } + + mod_power_hw_init(dm->power_module); + drm_dbg_driver(dm->ddev, "amdgpu: Power module init done\n"); + + return 0; +} + static int amdgpu_dm_init(struct amdgpu_device *adev) { struct dc_init_data init_data; @@ -1898,12 +1963,18 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) mutex_init(&adev->dm.dc_lock); mutex_init(&adev->dm.audio_lock); + spin_lock_init(&adev->dm.dmub_lock); + if (amdgpu_dm_irq_init(adev)) { drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n"); goto error; } - init_data.asic_id.chip_family = adev->family; + /* special handling for early revisions of GC 11.5.4 */ + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4)) + init_data.asic_id.chip_family = AMDGPU_FAMILY_GC_11_5_4; + else + init_data.asic_id.chip_family = adev->family; init_data.asic_id.pci_revision_id = adev->pdev->revision; init_data.asic_id.hw_internal_rev = adev->external_rev_id; @@ -2194,6 +2265,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) goto error; } + if (amdgpu_dm_init_power_module(&adev->dm)) + goto error; + /* create fake encoders for MST */ dm_dp_create_fake_mst_encoders(adev); @@ -2330,6 +2404,10 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) adev->dm.freesync_module = NULL; } + if (adev->dm.power_module) { + mod_power_destroy(adev->dm.power_module); + adev->dm.power_module = NULL; + } mutex_destroy(&adev->dm.audio_lock); mutex_destroy(&adev->dm.dc_lock); mutex_destroy(&adev->dm.dpia_aux_lock); @@ -3338,7 +3416,7 @@ static int dm_suspend(struct amdgpu_ip_block *ip_block) } struct drm_connector * -amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, +amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_commit *state, struct drm_crtc *crtc) { u32 i; @@ -4902,7 +4980,7 @@ static int register_outbox_irq_handlers(struct amdgpu_device *adev) * * This should only be called during atomic check. */ -int dm_atomic_get_state(struct drm_atomic_state *state, +int dm_atomic_get_state(struct drm_atomic_commit *state, struct dm_atomic_state **dm_state) { struct drm_device *dev = state->dev; @@ -4923,7 +5001,7 @@ int dm_atomic_get_state(struct drm_atomic_state *state, } static struct dm_atomic_state * -dm_atomic_get_new_state(struct drm_atomic_state *state) +dm_atomic_get_new_state(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -5050,8 +5128,8 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) #define AMDGPU_DM_MIN_SPREAD ((AMDGPU_DM_DEFAULT_MAX_BACKLIGHT - AMDGPU_DM_DEFAULT_MIN_BACKLIGHT) / 2) #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 -static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, - int bl_idx) +void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, + int bl_idx) { struct amdgpu_dm_backlight_caps *caps = &dm->backlight_caps[bl_idx]; @@ -5213,15 +5291,34 @@ static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *cap max - min); } +static struct dc_stream_state *dm_find_stream_with_link( + struct amdgpu_display_manager *dm, + struct dc_link *link) +{ + struct dc_state *cur_dc_state = dm->dc->current_state; + struct dc_stream_state *stream = NULL; + int i; + + for (i = 0; i < cur_dc_state->stream_count; i++) { + stream = cur_dc_state->streams[i]; + if (stream->link == link) + return stream; + } + + return NULL; +} + static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, int bl_idx, u32 user_brightness) { struct amdgpu_dm_backlight_caps *caps; struct dc_link *link; - u32 brightness; - bool rc, reallow_idle = false; + u32 brightness = 0; + bool rc = false, reallow_idle = false; struct drm_connector *connector; + struct dc_stream_state *stream; + unsigned int min, max; list_for_each_entry(connector, &dm->ddev->mode_config.connector_list, head) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -5251,13 +5348,6 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, if (caps->brightness_mask) brightness |= caps->brightness_mask; - /* Change brightness based on AUX property */ - mutex_lock(&dm->dc_lock); - if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) { - dc_allow_idle_optimizations(dm->dc, false); - reallow_idle = true; - } - if (trace_amdgpu_dm_brightness_enabled()) { trace_amdgpu_dm_brightness(__builtin_return_address(0), user_brightness, @@ -5266,22 +5356,45 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, power_supply_is_system_supplied() > 0); } - if (caps->aux_support) { - rc = dc_link_set_backlight_level_nits(link, true, brightness, - AUX_BL_DEFAULT_TRANSITION_TIME_MS); - if (!rc) - DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); - } else { - struct set_backlight_level_params backlight_level_params = { 0 }; + stream = dm_find_stream_with_link(dm, link); + if (!stream) + return; - backlight_level_params.backlight_pwm_u16_16 = brightness; - backlight_level_params.transition_time_in_ms = 0; - - rc = dc_link_set_backlight_level(link, &backlight_level_params); - if (!rc) - DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); + mutex_lock(&dm->dc_lock); + if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) { + dc_allow_idle_optimizations(dm->dc, false); + reallow_idle = true; } + if (caps->aux_support) { + rc = mod_power_set_backlight_nits(dm->power_module, stream, brightness, + AUX_BL_DEFAULT_TRANSITION_TIME_MS, false, true); + } else { + /* power module uses millipercent */ + get_brightness_range(caps, &min, &max); + brightness = DIV_ROUND_CLOSEST(brightness * 100, (max - min)) * 1000; + rc = mod_power_set_backlight_percent(dm->power_module, stream, + brightness, 0, false); + } + + /* + * Some kms clients create a ramped backlight transition effect + * by rapidly changing the backlight. Yet we must wait on dmcub + * fw to exit psr/replay before programming backlight. To + * prevent lag, keep disable psr/replay and let the next atomic + * flip clear the event. + * + * ToDo: use ISM to handle rapidly backlight change + * + * Rapidly backlight change is similar to rapidly cursor events, + * which is now handled by ISM. ISM can delay the event until system + * is really idle, so we may use ISM to handle backlight change as well. + */ + amdgpu_dm_psr_set_event(dm, stream, true, + psr_event_hw_programming, true); + amdgpu_dm_replay_set_event(dm, stream, true, + replay_event_hw_programming, true); + if (dm->dc->caps.ips_support && reallow_idle) dc_allow_idle_optimizations(dm->dc, true); @@ -5499,6 +5612,8 @@ static void setup_backlight_device(struct amdgpu_display_manager *dm, static void amdgpu_set_panel_orientation(struct drm_connector *connector); + + /* * In this architecture, the association * connector -> encoder -> crtc @@ -5740,7 +5855,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) psr_feature_enabled = false; if (psr_feature_enabled) { - amdgpu_dm_set_psr_caps(link); + amdgpu_dm_set_psr_caps(link, aconnector); drm_info(adev_to_drm(adev), "%s: PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n", aconnector->base.name, link->psr_settings.psr_feature_enabled, @@ -8366,7 +8481,7 @@ static int fill_hdr_info_packet(const struct drm_connector_state *state, static int amdgpu_dm_connector_atomic_check(struct drm_connector *conn, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *new_con_state = drm_atomic_get_new_connector_state(state, conn); @@ -8488,7 +8603,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { - struct drm_atomic_state *state = crtc_state->state; + struct drm_atomic_commit *state = crtc_state->state; struct drm_connector *connector = conn_state->connector; struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); @@ -8560,7 +8675,7 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { .atomic_check = dm_encoder_helper_atomic_check }; -static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, +static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_commit *state, struct dc_state *dc_state, struct dsc_mst_fairness_vars *vars) { @@ -9404,9 +9519,21 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, if (acrtc_state) { timing = &acrtc_state->stream->timing; - if (amdgpu_ip_version(adev, DCE_HWIP, 0) < - IP_VERSION(3, 5, 0) || - !(adev->flags & AMD_IS_APU)) { + if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= + IP_VERSION(3, 2, 0) && + !(adev->flags & AMD_IS_APU)) { + /* + * DGPUs NV3x and newer that support idle optimizations + * experience intermittent flip-done timeouts on cursor + * updates. Restore 5s offdelay behavior for now. + * + * Discussion on the issue: + * https://lore.kernel.org/amd-gfx/20260217191632.1243826-1-sysdadmin@m1k.cloud/ + */ + config.offdelay_ms = 5000; + config.disable_immediate = false; + } else if (amdgpu_ip_version(adev, DCE_HWIP, 0) < + IP_VERSION(3, 5, 0)) { /* * Older HW and DGPU have issues with instant off; * use a 2 frame offdelay. @@ -9792,7 +9919,8 @@ static void update_stream_irq_parameters( spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); } -static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, +static void amdgpu_dm_handle_vrr_transition(struct amdgpu_display_manager *dm, + struct dm_crtc_state *old_state, struct dm_crtc_state *new_state) { bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); @@ -9811,6 +9939,13 @@ static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR off->on: Get vblank ref\n", __func__, new_state->base.crtc->base.id); + + scoped_guard(mutex, &dm->dc_lock) { + amdgpu_dm_psr_set_event(dm, new_state->stream, true, + psr_event_vrr_transition, true); + amdgpu_dm_replay_set_event(dm, new_state->stream, true, + replay_event_vrr, true); + } } else if (old_vrr_active && !new_vrr_active) { /* Transition VRR active -> inactive: * Allow vblank irq disable again for fixed refresh rate. @@ -9819,10 +9954,17 @@ static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, drm_crtc_vblank_put(new_state->base.crtc); drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR on->off: Drop vblank ref\n", __func__, new_state->base.crtc->base.id); + + scoped_guard(mutex, &dm->dc_lock) { + amdgpu_dm_psr_set_event(dm, new_state->stream, false, + psr_event_vrr_transition, false); + amdgpu_dm_replay_set_event(dm, new_state->stream, false, + replay_event_vrr, false); + } } } -static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) +static void amdgpu_dm_commit_cursors(struct drm_atomic_commit *state) { struct drm_plane *plane; struct drm_plane_state *old_plane_state; @@ -9916,7 +10058,8 @@ static void amdgpu_dm_update_cursor(struct drm_plane *plane, } } -static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach, +static void amdgpu_dm_enable_self_refresh(struct amdgpu_display_manager *dm, + struct amdgpu_crtc *acrtc_attach, const struct dm_crtc_state *acrtc_state, const u64 current_ts) { @@ -9924,20 +10067,10 @@ static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach, struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; - bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); - - if (acrtc_state->update_type > UPDATE_TYPE_FAST) { - if (pr->config.replay_supported && !pr->replay_feature_enabled) - amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn); - else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED && - !psr->psr_feature_enabled) - if (!aconn->disallow_edp_enter_psr) - amdgpu_dm_link_setup_psr(acrtc_state->stream); - } /* Decrement skip count when SR is enabled and we're doing fast updates. */ if (acrtc_state->update_type == UPDATE_TYPE_FAST && - (psr->psr_feature_enabled || pr->config.replay_supported)) { + (psr->psr_feature_enabled || pr->replay_feature_enabled)) { if (aconn->sr_skip_count > 0) aconn->sr_skip_count--; @@ -9952,24 +10085,22 @@ static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach, * of update events. * See `amdgpu_dm_crtc_vblank_control_worker()`. */ - if (!vrr_active && - acrtc_attach->dm_irq_params.allow_sr_entry && -#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY - !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && -#endif - (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) { - if (pr->replay_feature_enabled && !pr->replay_allow_active) - amdgpu_dm_replay_enable(acrtc_state->stream, true); - if (psr->psr_version == DC_PSR_VERSION_SU_1 && - !psr->psr_allow_active && !aconn->disallow_edp_enter_psr) - amdgpu_dm_psr_enable(acrtc_state->stream); + if (acrtc_attach->dm_irq_params.allow_sr_entry && + (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) { + amdgpu_dm_psr_set_event(dm, acrtc_state->stream, false, + psr_event_hw_programming, false); + + amdgpu_dm_replay_set_event(dm, acrtc_state->stream, true, + replay_event_general_ui, true); + amdgpu_dm_replay_set_event(dm, acrtc_state->stream, false, + replay_event_hw_programming, false); } } else { acrtc_attach->dm_irq_params.allow_sr_entry = false; } } -static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, +static void amdgpu_dm_commit_planes(struct drm_atomic_commit *state, struct drm_device *dev, struct amdgpu_display_manager *dm, struct drm_crtc *pcrtc, @@ -10124,15 +10255,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, */ if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && acrtc_attach->dm_irq_params.allow_sr_entry && -#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY - !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && -#endif dirty_rects_changed) { mutex_lock(&dm->dc_lock); acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = timestamp_ns; - if (acrtc_state->stream->link->psr_settings.psr_allow_active) - amdgpu_dm_psr_disable(acrtc_state->stream, true); + amdgpu_dm_psr_set_event(dm, acrtc_state->stream, true, + psr_event_hw_programming, true); mutex_unlock(&dm->dc_lock); } } @@ -10297,15 +10425,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) bundle->stream_update.abm_level = &acrtc_state->abm_level; - mutex_lock(&dm->dc_lock); - if ((acrtc_state->update_type > UPDATE_TYPE_FAST) || vrr_active) { - if (acrtc_state->stream->link->replay_settings.replay_allow_active) - amdgpu_dm_replay_disable(acrtc_state->stream); - if (acrtc_state->stream->link->psr_settings.psr_allow_active) - amdgpu_dm_psr_disable(acrtc_state->stream, true); - } - mutex_unlock(&dm->dc_lock); - /* * If FreeSync state on the stream has changed then we need to * re-adjust the min/max bounds now that DC doesn't handle this @@ -10343,8 +10462,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) dm_update_pflip_irq_state(drm_to_adev(dev), acrtc_attach); - - amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, timestamp_ns); + amdgpu_dm_enable_self_refresh(dm, acrtc_attach, acrtc_state, + timestamp_ns); mutex_unlock(&dm->dc_lock); } @@ -10363,7 +10482,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, } static void amdgpu_dm_commit_audio(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_dm_connector *aconnector; @@ -10463,7 +10582,103 @@ static void dm_clear_writeback(struct amdgpu_display_manager *dm, dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); } -static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, +/** + * amdgpu_dm_mod_power_update_streams - update mod_power stream state on modeset + * @state: the drm atomic state + * @dm: the display manager to update mod_power on + * + * Notify mod_power of stream changes on modeset events, and disable PSR/Replay + * in preparation for hardware programming. See also + * amdgpu_dm_mod_power_setup_streams() for post-modeset mod_power setup. + */ +static void amdgpu_dm_mod_power_update_streams(struct drm_atomic_commit *state, + struct amdgpu_display_manager *dm) +{ + struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; + struct drm_crtc_state *old_crtc_state, *new_crtc_state; + struct amdgpu_dm_connector *aconnector; + struct drm_crtc *crtc; + int i = 0; + + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + + if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) + continue; + + /* + * Update mod_power on modeset event in preparation for hw + * programming. Always use the old stream, since it would have + * been previously added to mod_power. If old stream is null (on + * crtc enable, for example), mod_power will no-op, which is the + * desried behavior. + */ + if (old_crtc_state->active) { + scoped_guard(mutex, &dm->dc_lock) { + amdgpu_dm_psr_set_event(dm, dm_old_crtc_state->stream, true, + psr_event_hw_programming, true); + amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, true, + replay_event_hw_programming, true); + } + } + + if (new_crtc_state->active) { + aconnector = (struct amdgpu_dm_connector *) + dm_new_crtc_state->stream->dm_stream_context; + if (old_crtc_state->active) { + mod_power_replace_stream(dm->power_module, + dm_old_crtc_state->stream, + dm_new_crtc_state->stream, + &aconnector->psr_caps); + } else { + mod_power_add_stream(dm->power_module, + dm_new_crtc_state->stream, + &aconnector->psr_caps); + } + } else if (old_crtc_state->active) { + mod_power_remove_stream(dm->power_module, + dm_old_crtc_state->stream); + } + } +} + +/** + * amdgpu_dm_mod_power_setup_streams - setup mod_power stream state post modeset + * @state: the drm atomic state + * @dm: the display manager to update mod_power on + * + * Notify mod_power of mode_change. This needs to be done after dc_stream + * updates have been committed, and VRR parameters have been updated. + */ +static void amdgpu_dm_mod_power_setup_streams(struct drm_atomic_commit *state, + struct amdgpu_display_manager *dm) +{ + struct dm_crtc_state *dm_new_crtc_state; + struct drm_crtc_state *new_crtc_state; + struct amdgpu_crtc *acrtc; + struct drm_crtc *crtc; + int i = 0; + + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + acrtc = to_amdgpu_crtc(crtc); + + if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) + continue; + + if (new_crtc_state->active) { + amdgpu_dm_link_setup_replay(dm_new_crtc_state->stream, + &acrtc->dm_irq_params.vrr_params); + mod_power_notify_mode_change(dm->power_module, + dm_new_crtc_state->stream, + false); + } + } + +} + +static void amdgpu_dm_commit_streams(struct drm_atomic_commit *state, struct dc_state *dc_state) { struct drm_device *dev = state->dev; @@ -10506,6 +10721,8 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, acrtc->wb_enabled = false; } + amdgpu_dm_mod_power_update_streams(state, dm); + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); @@ -10610,13 +10827,10 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, } } /* for_each_crtc_in_state() */ - /* if there mode set or reset, disable eDP PSR, Replay */ + /* if there mode set or reset, flush vblank work queue */ if (mode_set_reset_required) { if (dm->vblank_control_workqueue) flush_workqueue(dm->vblank_control_workqueue); - - amdgpu_dm_replay_disable_all(dm); - amdgpu_dm_psr_disable_all(dm); } dm_enable_per_frame_crtc_master_sync(dc_state); @@ -10763,7 +10977,7 @@ static void dm_set_writeback(struct amdgpu_display_manager *dm, drm_writeback_queue_job(wb_conn, new_con_state); } -static void amdgpu_dm_update_hdcp(struct drm_atomic_state *state) +static void amdgpu_dm_update_hdcp(struct drm_atomic_commit *state) { struct drm_connector_state *old_con_state, *new_con_state; struct drm_device *dev = state->dev; @@ -10878,7 +11092,7 @@ static void amdgpu_dm_update_hdcp(struct drm_atomic_state *state) } } -static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state) +static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; @@ -10919,7 +11133,7 @@ static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state) * programming the hardware. Any failures here implies a hardware failure, since * atomic check should have filtered anything non-kosher. */ -static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) +static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -11089,7 +11303,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) manage_dm_interrupts(adev, acrtc, dm_new_crtc_state); } /* Handle vrr on->off / off->on transitions */ - amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); + amdgpu_dm_handle_vrr_transition(dm, dm_old_crtc_state, dm_new_crtc_state); #ifdef CONFIG_DEBUG_FS if (new_crtc_state->active && @@ -11127,6 +11341,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) #endif } + amdgpu_dm_mod_power_setup_streams(state, dm); + for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) if (new_crtc_state->async_flip) wait_for_vblank = false; @@ -11224,7 +11440,7 @@ static int dm_force_atomic_commit(struct drm_connector *connector) { int ret = 0; struct drm_device *ddev = connector->dev; - struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); + struct drm_atomic_commit *state = drm_atomic_commit_alloc(ddev); struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); struct drm_plane *plane = disconnected_acrtc->base.primary; struct drm_connector_state *conn_state; @@ -11239,7 +11455,7 @@ static int dm_force_atomic_commit(struct drm_connector *connector) /* Construct an atomic state to restore previous display setting */ /* - * Attach connectors to drm_atomic_state + * Attach connectors to drm_atomic_commit */ conn_state = drm_atomic_get_connector_state(state, connector); @@ -11249,7 +11465,7 @@ static int dm_force_atomic_commit(struct drm_connector *connector) goto out; } - /* Attach crtc to drm_atomic_state*/ + /* Attach crtc to drm_atomic_commit*/ crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); /* Check for error in getting crtc state */ @@ -11261,7 +11477,7 @@ static int dm_force_atomic_commit(struct drm_connector *connector) /* force a restore */ crtc_state->mode_changed = true; - /* Attach plane to drm_atomic_state */ + /* Attach plane to drm_atomic_commit */ plane_state = drm_atomic_get_plane_state(state, plane); /* Check for error in getting plane state */ @@ -11274,7 +11490,7 @@ static int dm_force_atomic_commit(struct drm_connector *connector) ret = drm_atomic_commit(state); out: - drm_atomic_state_put(state); + drm_atomic_commit_put(state); if (ret) drm_err(ddev, "Restoring old state failed with %i\n", ret); @@ -11323,7 +11539,7 @@ void dm_restore_drm_connector_state(struct drm_device *dev, * Waits for completion of all non blocking commits. */ static int do_aquire_global_lock(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_commit *commit; @@ -11468,7 +11684,7 @@ static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) } static int dm_update_crtc_state(struct amdgpu_display_manager *dm, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state, struct drm_crtc_state *new_crtc_state, @@ -11742,7 +11958,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, return ret; } -static bool should_reset_plane(struct drm_atomic_state *state, +static bool should_reset_plane(struct drm_atomic_commit *state, struct drm_plane *plane, struct drm_plane_state *old_plane_state, struct drm_plane_state *new_plane_state) @@ -12000,7 +12216,7 @@ static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc, return 0; } -static bool dm_should_update_native_cursor(struct drm_atomic_state *state, +static bool dm_should_update_native_cursor(struct drm_atomic_commit *state, struct drm_crtc *old_plane_crtc, struct drm_crtc *new_plane_crtc, bool enable) @@ -12030,7 +12246,7 @@ static bool dm_should_update_native_cursor(struct drm_atomic_state *state, } static int dm_update_plane_state(struct dc *dc, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_plane *plane, struct drm_plane_state *old_plane_state, struct drm_plane_state *new_plane_state, @@ -12238,7 +12454,7 @@ dm_get_plane_scale(struct drm_plane_state *plane_state, * indefinitely. */ static inline struct __drm_planes_state *__get_next_zpos( - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct __drm_planes_state *prev) { unsigned int highest_zpos = 0, prev_zpos = 256; @@ -12288,7 +12504,7 @@ static inline struct __drm_planes_state *__get_next_zpos( (old_plane_state) = __i->old_state, \ (new_plane_state) = __i->new_state, 1)) -static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) +static int add_affected_mst_dsc_crtcs(struct drm_atomic_commit *state, struct drm_crtc *crtc) { struct drm_connector *connector; struct drm_connector_state *conn_state, *old_conn_state; @@ -12347,7 +12563,7 @@ static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm * * Return: true if the pipeline modifies pixels, false otherwise. */ -static bool dm_plane_color_pipeline_active(struct drm_atomic_state *state, +static bool dm_plane_color_pipeline_active(struct drm_atomic_commit *state, struct drm_plane *plane, bool use_old) { @@ -12387,7 +12603,7 @@ static bool dm_plane_color_pipeline_active(struct drm_atomic_state *state, * failed. */ static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct dm_crtc_state *dm_crtc_state, enum amdgpu_dm_cursor_mode *cursor_mode) { @@ -12526,7 +12742,7 @@ static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, } static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_crtc_state *crtc_state) { struct drm_plane *plane; @@ -12575,7 +12791,7 @@ static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev, * Return: -Error code if validation failed. */ static int amdgpu_dm_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct amdgpu_device *adev = drm_to_adev(dev); struct dm_atomic_state *dm_state = NULL; @@ -13685,11 +13901,17 @@ int amdgpu_dm_process_dmub_set_config_sync( bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) { + struct amdgpu_device *adev = ctx->driver_context; + + guard(spinlock_irqsave)(&adev->dm.dmub_lock); return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type); } bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) { + struct amdgpu_device *adev = ctx->driver_context; + + guard(spinlock_irqsave)(&adev->dm.dmub_lock); return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type); } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 74a8fe1a1999..74f700fbeb6f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -463,6 +463,13 @@ struct amdgpu_display_manager { */ struct mutex dc_lock; + /** + * @dmub_lock: + * + * Guards access to DMUB command submission. + */ + spinlock_t dmub_lock; + /** * @audio_lock: * @@ -568,6 +575,7 @@ struct amdgpu_display_manager { struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; struct mod_freesync *freesync_module; + struct mod_power *power_module; struct hdcp_workqueue *hdcp_workqueue; /** @@ -584,7 +592,7 @@ struct amdgpu_display_manager { */ struct idle_workqueue *idle_workqueue; - struct drm_atomic_state *cached_state; + struct drm_atomic_commit *cached_state; struct dc_state *cached_dc_state; struct dm_compressor_info compressor; @@ -835,6 +843,7 @@ struct amdgpu_dm_connector { bool force_yuv420_output; bool force_yuv422_output; struct dsc_preferred_settings dsc_settings; + struct psr_caps psr_caps; union dp_downstream_port_present mst_downstream_port_present; /* Cached display modes */ struct drm_display_mode freesync_vid_base; @@ -1123,11 +1132,11 @@ struct dc_stream_state * const struct dm_connector_state *dm_state, const struct dc_stream_state *old_stream); -int dm_atomic_get_state(struct drm_atomic_state *state, +int dm_atomic_get_state(struct drm_atomic_commit *state, struct dm_atomic_state **dm_state); struct drm_connector * -amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, +amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_commit *state, struct drm_crtc *crtc); int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); @@ -1149,4 +1158,5 @@ int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector); void retrieve_dmi_info(struct amdgpu_display_manager *dm); +void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, int bl_idx); #endif /* __AMDGPU_DM_H__ */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index cd1e58b8defc..fa6883ae4dfb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -1499,7 +1499,7 @@ __set_dm_plane_colorop_degamma(struct drm_plane_state *plane_state, { struct drm_colorop *old_colorop; struct drm_colorop_state *colorop_state = NULL, *new_colorop_state; - struct drm_atomic_state *state = plane_state->state; + struct drm_atomic_commit *state = plane_state->state; int i = 0; old_colorop = colorop; @@ -1526,7 +1526,7 @@ __set_dm_plane_colorop_3x4_matrix(struct drm_plane_state *plane_state, { struct drm_colorop *old_colorop; struct drm_colorop_state *colorop_state = NULL, *new_colorop_state; - struct drm_atomic_state *state = plane_state->state; + struct drm_atomic_commit *state = plane_state->state; const struct drm_device *dev = colorop->dev; const struct drm_property_blob *blob; struct drm_color_ctm_3x4 *ctm = NULL; @@ -1567,7 +1567,7 @@ __set_dm_plane_colorop_multiplier(struct drm_plane_state *plane_state, { struct drm_colorop *old_colorop; struct drm_colorop_state *colorop_state = NULL, *new_colorop_state; - struct drm_atomic_state *state = plane_state->state; + struct drm_atomic_commit *state = plane_state->state; const struct drm_device *dev = colorop->dev; int i = 0; @@ -1596,7 +1596,7 @@ __set_dm_plane_colorop_shaper(struct drm_plane_state *plane_state, { struct drm_colorop *old_colorop; struct drm_colorop_state *colorop_state = NULL, *new_colorop_state; - struct drm_atomic_state *state = plane_state->state; + struct drm_atomic_commit *state = plane_state->state; enum dc_transfer_func_predefined default_tf = TRANSFER_FUNCTION_LINEAR; struct dc_transfer_func *tf = &dc_plane_state->in_shaper_func; const struct drm_color_lut32 *shaper_lut; @@ -1704,7 +1704,7 @@ __set_dm_plane_colorop_3dlut(struct drm_plane_state *plane_state, struct drm_colorop *old_colorop; struct drm_colorop_state *colorop_state = NULL, *new_colorop_state; struct dc_transfer_func *tf = &dc_plane_state->in_shaper_func; - struct drm_atomic_state *state = plane_state->state; + struct drm_atomic_commit *state = plane_state->state; const struct amdgpu_device *adev = drm_to_adev(colorop->dev); bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend; const struct drm_device *dev = colorop->dev; @@ -1759,7 +1759,7 @@ __set_dm_plane_colorop_blend(struct drm_plane_state *plane_state, { struct drm_colorop *old_colorop; struct drm_colorop_state *colorop_state = NULL, *new_colorop_state; - struct drm_atomic_state *state = plane_state->state; + struct drm_atomic_commit *state = plane_state->state; enum dc_transfer_func_predefined default_tf = TRANSFER_FUNCTION_LINEAR; struct dc_transfer_func *tf = &dc_plane_state->blend_tf; const struct drm_color_lut32 *blend_lut = NULL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 62573173e2ac..4155984201c6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -503,7 +503,6 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, { struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dc_stream_state *stream_state = dm_crtc_state->stream; - struct amdgpu_dm_connector *aconnector = NULL; bool enable = amdgpu_dm_is_valid_crc_source(source); int ret = 0; enum crc_poly_mode crc_poly_mode = CRC_POLY_MODE_16; @@ -512,21 +511,17 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, if (!stream_state) return -EINVAL; - /* Get connector from stream */ - aconnector = (struct amdgpu_dm_connector *)stream_state->dm_stream_context; - mutex_lock(&adev->dm.dc_lock); - + /* Notify power module about CRC window active to disable PSR/Replay + * Power module will check caps internally and skip if not supported + */ if (enable) { - /* For PSR1, check that the panel has exited PSR */ - if (stream_state->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) - amdgpu_dm_psr_wait_disable(stream_state); + amdgpu_dm_psr_set_event(&adev->dm, stream_state, true, + psr_event_crc_window_active, true); - /* Set flag to disallow enter replay when CRC source is enabled */ - if (aconnector) - aconnector->disallow_edp_enter_replay = true; - amdgpu_dm_replay_disable(stream_state); + amdgpu_dm_replay_set_event(&adev->dm, stream_state, true, + replay_event_crc_window_active, true); } /* CRC polynomial selection only support for DCN3.6+ except DCN4.0.1 */ @@ -559,11 +554,15 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, } if (!enable) { - /* Clear flag to allow enter replay when CRC source is disabled */ - if (aconnector) - aconnector->disallow_edp_enter_replay = false; - } + /* Notify power module about CRC window inactive to re-enable PSR/Replay + * Power module will check caps internally and skip if not supported + */ + amdgpu_dm_psr_set_event(&adev->dm, stream_state, false, + psr_event_crc_window_active, false); + amdgpu_dm_replay_set_event(&adev->dm, stream_state, false, + replay_event_crc_window_active, false); + } unlock: mutex_unlock(&adev->dm.dc_lock); @@ -760,10 +759,13 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) uint32_t crcs[3]; unsigned long flags; - if (crtc == NULL) + if (!crtc || !crtc->state || !crtc->dev) return; crtc_state = to_dm_crtc_state(crtc->state); + if (!crtc_state->stream) + return; + stream_state = crtc_state->stream; acrtc = to_amdgpu_crtc(crtc); drm_dev = crtc->dev; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index d69f5a75b685..3dcedaa67ed8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -34,6 +34,7 @@ #include "amdgpu_dm_plane.h" #include "amdgpu_dm_trace.h" #include "amdgpu_dm_debugfs.h" +#include "modules/inc/mod_power.h" #define HPD_DETECTION_PERIOD_uS 2000000 #define HPD_DETECTION_TIME_uS 100000 @@ -100,68 +101,33 @@ bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state) } /** - * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features. - * @dm: amdgpu display manager instance. - * @acrtc: CRTC whose panel self-refresh state is being updated. - * @stream: DC stream associated with @acrtc. - * @vblank_enabled: Whether the DRM vblank counter is currently enabled. - * @allow_sr_entry: Whether entry into self-refresh mode is allowed. + * amdgpu_dm_crtc_set_static_screen_optimze() - Toggle static screen optimizations. * - * The DRM vblank counter enable/disable action is used as the trigger to enable - * or disable various panel self-refresh features: + * @dm: display manager + * @stream: DC stream state + * @sso_enable: desired static screen optimization state + * @allow_sr_entry: whether entry into self-refresh mode is allowed * - * Panel Replay and PSR SU - * - Enable when: - * - VRR is disabled - * - vblank counter is disabled - * - entry is allowed: usermode demonstrates an adequate number of fast - * commits - * - CRC capture window isn't active - * - Keep enabled even when vblank counter gets enabled - * - * PSR1 - * - Enable condition same as above - * - Disable when vblank counter is enabled + * This function uses the static-screen optimization state as the trigger to + * set/clear the Replay and PSR vsync-related events. */ -void amdgpu_dm_crtc_set_panel_sr_feature( +void amdgpu_dm_crtc_set_static_screen_optimze( struct amdgpu_display_manager *dm, - struct amdgpu_crtc *acrtc, struct dc_stream_state *stream, - bool vblank_enabled, bool allow_sr_entry) + bool sso_enable, bool allow_sr_entry) { struct dc_link *link = stream->link; - bool is_sr_active = (link->replay_settings.replay_allow_active || - link->psr_settings.psr_allow_active); - bool is_crc_window_active = false; - bool vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); + bool set_vsync_event = !sso_enable; -#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY - is_crc_window_active = - amdgpu_dm_crc_window_is_activated(&acrtc->base); -#endif + if (!allow_sr_entry) + return; - if (link->replay_settings.replay_feature_enabled && !vrr_active && - allow_sr_entry && !is_sr_active && !is_crc_window_active) { - amdgpu_dm_replay_enable(stream, true); - } else if (vblank_enabled) { - if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active) - amdgpu_dm_psr_disable(stream, false); - } else if (link->psr_settings.psr_feature_enabled && !vrr_active && - allow_sr_entry && !is_sr_active && !is_crc_window_active) { + amdgpu_dm_replay_set_event(dm, stream, + set_vsync_event, replay_event_vsync, set_vsync_event); - struct amdgpu_dm_connector *aconn = - (struct amdgpu_dm_connector *) stream->dm_stream_context; - - if (!aconn->disallow_edp_enter_psr) { - amdgpu_dm_psr_enable(stream); - if (dm->idle_workqueue && - (dm->dc->config.disable_ips == DMUB_IPS_ENABLE) && - dm->dc->idle_optimizations_allowed && - dm->idle_workqueue->enable && - !dm->idle_workqueue->running) - schedule_work(&dm->idle_workqueue->work); - } - } + if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) + amdgpu_dm_psr_set_event(dm, stream, + set_vsync_event, psr_event_vsync, set_vsync_event); } bool amdgpu_dm_is_headless(struct amdgpu_device *adev) @@ -584,7 +550,7 @@ static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc) static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) { - struct drm_atomic_state *state = new_crtc_state->state; + struct drm_atomic_commit *state = new_crtc_state->state; struct drm_plane *plane; int num_active = 0; @@ -637,7 +603,7 @@ static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, } static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h index 3a8094013a5d..e9fb52f0e66d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h @@ -27,11 +27,10 @@ #ifndef __AMDGPU_DM_CRTC_H__ #define __AMDGPU_DM_CRTC_H__ -void amdgpu_dm_crtc_set_panel_sr_feature( +void amdgpu_dm_crtc_set_static_screen_optimze( struct amdgpu_display_manager *dm, - struct amdgpu_crtc *acrtc, struct dc_stream_state *stream, - bool vblank_enabled, bool allow_sr_entry); + bool sso_enable, bool allow_sr_entry); void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 2409ac72b166..011ae1980f80 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -33,6 +33,7 @@ #include "amdgpu_dm.h" #include "amdgpu_dm_debugfs.h" #include "amdgpu_dm_replay.h" +#include "amdgpu_dm_psr.h" #include "dm_helpers.h" #include "dmub/dmub_srv.h" #include "resource.h" @@ -3300,11 +3301,26 @@ static int disallow_edp_enter_psr_get(void *data, u64 *val) static int disallow_edp_enter_psr_set(void *data, u64 val) { struct amdgpu_dm_connector *aconnector = data; + struct dc_link *link = aconnector->dc_link; - aconnector->disallow_edp_enter_psr = val ? true : false; + aconnector->disallow_edp_enter_psr = (val != 0); + + /* eDP PSR enable / disable is happened during mode change in power module. + * Only psr_settings.psr_version is used to decide whether PSR is enabled or not. + * So here we only update psr_version based on debugfs setting. + * If disallow_edp_enter_psr is true, set psr_version to unsupported; + * if disallow_edp_enter_psr is false, set psr_version based on sink capability. + */ + if (aconnector->disallow_edp_enter_psr) + link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; + else if (aconnector->psr_caps.psr_version == 1) + link->psr_settings.psr_version = DC_PSR_VERSION_1; + else if (aconnector->psr_caps.psr_version == 2) + link->psr_settings.psr_version = DC_PSR_VERSION_SU_1; return 0; } + /* check if kernel disallow eDP enter replay state * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay * 0: allow edp enter replay; 1: disallow @@ -3346,11 +3362,27 @@ static int disallow_edp_enter_replay_get(void *data, u64 *val) static int disallow_edp_enter_replay_set(void *data, u64 val) { struct amdgpu_dm_connector *aconnector = data; + struct dc_link *link = aconnector->dc_link; - aconnector->disallow_edp_enter_replay = val ? true : false; + aconnector->disallow_edp_enter_replay = (val != 0); + + /* eDP replay enable / disable is happened during mode change in power module. + * Only replay_settings.config.replay_supported is used to decide whether + * replay is enabled or not. So here we only update replay_supported based on + * debugfs setting. + * If disallow_edp_enter_replay is true, set replay_supported to false. + * if disallow_edp_enter_replay is false, set replay_supported back based on + * sink replay capability. + */ + if (aconnector->disallow_edp_enter_replay) + link->replay_settings.config.replay_supported = false; + else + link->replay_settings.config.replay_supported = + link->replay_settings.config.replay_cap_support; return 0; } + static int dmub_trace_mask_set(void *data, u64 val) { struct amdgpu_device *adev = data; @@ -3485,6 +3517,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_replay_fops, DEFINE_DEBUGFS_ATTRIBUTE(ips_residency_cntl_fops, ips_residency_cntl_get, ips_residency_cntl_set, "%llu\n"); + DEFINE_SHOW_ATTRIBUTE(current_backlight); DEFINE_SHOW_ATTRIBUTE(target_backlight); DEFINE_SHOW_ATTRIBUTE(ips_status); @@ -3855,28 +3888,35 @@ DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, static int crc_win_update_set(void *data, u64 val) { struct drm_crtc *crtc = data; - struct amdgpu_crtc *acrtc; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = drm_to_adev(crtc->dev); if (val) { - acrtc = to_amdgpu_crtc(crtc); mutex_lock(&adev->dm.dc_lock); - /* PSR may write to OTG CRC window control register, - * so close it before starting secure_display. + /* PSR Replay may write to OTG CRC window control register, + * so inactive it before starting secure_display by sending disable event. */ - amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream, true); + amdgpu_dm_psr_set_event(&adev->dm, acrtc->dm_irq_params.stream, true, + psr_event_crc_window_active, true); + amdgpu_dm_replay_set_event(&adev->dm, acrtc->dm_irq_params.stream, true, + replay_event_crc_window_active, true); spin_lock_irq(&adev_to_drm(adev)->event_lock); - acrtc->dm_irq_params.window_param[0].enable = true; acrtc->dm_irq_params.window_param[0].update_win = true; acrtc->dm_irq_params.window_param[0].skip_frame_cnt = 0; acrtc->dm_irq_params.crc_window_activated = true; - spin_unlock_irq(&adev_to_drm(adev)->event_lock); mutex_unlock(&adev->dm.dc_lock); + } else { + /* Clear disable events to allow PSR/Replay to active */ + mutex_lock(&adev->dm.dc_lock); + amdgpu_dm_psr_set_event(&adev->dm, acrtc->dm_irq_params.stream, false, + psr_event_crc_window_active, false); + amdgpu_dm_replay_set_event(&adev->dm, acrtc->dm_irq_params.stream, false, + replay_event_crc_window_active, false); + mutex_unlock(&adev->dm.dc_lock); } - return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 3b8ae7798a93..a3cb05490dc9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -1032,6 +1032,45 @@ dm_helpers_read_acpi_edid(struct amdgpu_dm_connector *aconnector) return drm_edid_read_custom(connector, dm_helpers_probe_acpi_edid, connector); } +static const struct drm_edid * +dm_helpers_read_vbios_hardcoded_edid(struct dc_link *link, struct amdgpu_dm_connector *aconnector) +{ + struct dc_bios *bios = link->ctx->dc_bios; + struct embedded_panel_info info; + const struct drm_edid *edid; + enum bp_result r; + + if (!dc_is_embedded_signal(link->connector_signal) || + !bios->funcs->get_embedded_panel_info) + return NULL; + + memset(&info, 0, sizeof(info)); + r = bios->funcs->get_embedded_panel_info(bios, &info); + + if (r != BP_RESULT_OK) { + dm_error("Error when reading embedded panel info: %u\n", r); + return NULL; + } + + if (!info.fake_edid || !info.fake_edid_size) { + dm_error("Embedded panel info doesn't contain an EDID\n"); + return NULL; + } + + edid = drm_edid_alloc(info.fake_edid, info.fake_edid_size); + + if (!drm_edid_valid(edid)) { + dm_error("EDID from embedded panel info is invalid\n"); + drm_edid_free(edid); + return NULL; + } + + aconnector->base.display_info.width_mm = info.panel_width_mm; + aconnector->base.display_info.height_mm = info.panel_height_mm; + + return edid; +} + void populate_hdmi_info_from_connector(struct drm_hdmi_info *hdmi, struct dc_edid_caps *edid_caps) { edid_caps->scdc_present = hdmi->scdc.supported; @@ -1052,6 +1091,9 @@ enum dc_edid_status dm_helpers_read_local_edid( if (link->aux_mode) ddc = &aconnector->dm_dp_aux.aux.ddc; + else if (link->ddc_hw_inst == GPIO_DDC_LINE_UNKNOWN && + dc_is_embedded_signal(link->connector_signal)) + ddc = NULL; else ddc = &aconnector->i2c->base; @@ -1065,6 +1107,8 @@ enum dc_edid_status dm_helpers_read_local_edid( drm_edid = dm_helpers_read_acpi_edid(aconnector); if (drm_edid) drm_info(connector->dev, "Using ACPI provided EDID for %s\n", connector->name); + else if (!ddc) + drm_edid = dm_helpers_read_vbios_hardcoded_edid(link, aconnector); else drm_edid = drm_edid_read_ddc(connector, ddc); drm_edid_connector_update(connector, drm_edid); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c index a64e95860e99..d03ea3bafd46 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c @@ -291,24 +291,16 @@ static void dm_ism_commit_idle_optimization_state(struct amdgpu_dm_ism *ism, */ if (stream && stream->link) { /* - * If allow_panel_sso is true when disabling vblank, allow - * deeper panel sleep states such as PSR1 and Replay static - * screen optimization. - */ - if (!vblank_enabled && allow_panel_sso) { - amdgpu_dm_crtc_set_panel_sr_feature( - dm, acrtc, stream, false, - acrtc->dm_irq_params.allow_sr_entry); - } else if (vblank_enabled) { - /* Make sure to exit SSO on vblank enable */ - amdgpu_dm_crtc_set_panel_sr_feature( - dm, acrtc, stream, true, - acrtc->dm_irq_params.allow_sr_entry); - } - /* - * Else, vblank_enabled == false and allow_panel_sso == false; - * do nothing here. + * If the OS requires vblank events (or vblank is otherwise enabled), + * do not allow static screen optimizations. + * + * Keep ism->allow_static_screen_optimizations unchanged so the + * hysteresis-based decision can be reused once vblank is disabled. */ + allow_panel_sso = allow_panel_sso && !vblank_enabled; + amdgpu_dm_crtc_set_static_screen_optimze( + dm, stream, allow_panel_sso, + acrtc->dm_irq_params.allow_sr_entry); } /* diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index be038d9014bb..51924ae87705 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -497,7 +497,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) static struct drm_encoder * dm_mst_atomic_best_encoder(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, connector); @@ -579,7 +579,7 @@ dm_dp_mst_detect(struct drm_connector *connector, } static int dm_dp_mst_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; @@ -986,7 +986,7 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) return dsc_config.bits_per_pixel; } -static int increase_dsc_bpp(struct drm_atomic_state *state, +static int increase_dsc_bpp(struct drm_atomic_commit *state, struct drm_dp_mst_topology_state *mst_state, struct dc_link *dc_link, struct dsc_mst_fairness_params *params, @@ -1090,7 +1090,7 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, return 0; } -static int try_disable_dsc(struct drm_atomic_state *state, +static int try_disable_dsc(struct drm_atomic_commit *state, struct dc_link *dc_link, struct dsc_mst_fairness_params *params, struct dsc_mst_fairness_vars *vars, @@ -1183,7 +1183,7 @@ static void log_dsc_params(int count, struct dsc_mst_fairness_vars *vars, int k) i, vars[i + k].dsc_enabled, vars[i + k].bpp_x16, vars[i + k].pbn); } -static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, +static int compute_mst_dsc_configs_for_link(struct drm_atomic_commit *state, struct dc_state *dc_state, struct dc_link *dc_link, struct dsc_mst_fairness_vars *vars, @@ -1348,7 +1348,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, } static bool is_dsc_need_re_compute( - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct dc_state *dc_state, struct dc_link *dc_link) { @@ -1479,7 +1479,7 @@ static bool is_dsc_need_re_compute( return is_dsc_need_re_compute; } -int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, +int compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state, struct dc_state *dc_state, struct dsc_mst_fairness_vars *vars) { @@ -1549,7 +1549,7 @@ int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, return ret; } -static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, +static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state, struct dc_state *dc_state, struct dsc_mst_fairness_vars *vars) { @@ -1602,7 +1602,7 @@ static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, return ret; } -static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state, +static int find_crtc_index_in_state_by_stream(struct drm_atomic_commit *state, struct dc_stream_state *stream) { int i; @@ -1633,7 +1633,7 @@ static bool is_link_to_dschub(struct dc_link *dc_link) return true; } -static bool is_dsc_precompute_needed(struct drm_atomic_state *state) +static bool is_dsc_precompute_needed(struct drm_atomic_commit *state) { int i; struct drm_crtc *crtc; @@ -1654,7 +1654,7 @@ static bool is_dsc_precompute_needed(struct drm_atomic_state *state) return ret; } -int pre_validate_dsc(struct drm_atomic_state *state, +int pre_validate_dsc(struct drm_atomic_commit *state, struct dm_atomic_state **dm_state_ptr, struct dsc_mst_fairness_vars *vars) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h index 6f7ea684b555..0e8eef5bdb74 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h @@ -80,13 +80,13 @@ struct dsc_mst_fairness_vars { struct amdgpu_dm_connector *aconnector; }; -int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, +int compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state, struct dc_state *dc_state, struct dsc_mst_fairness_vars *vars); bool needs_dsc_aux_workaround(struct dc_link *link); -int pre_validate_dsc(struct drm_atomic_state *state, +int pre_validate_dsc(struct drm_atomic_commit *state, struct dm_atomic_state **dm_state_ptr, struct dsc_mst_fairness_vars *vars); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 81e43534ec59..e957657b06c7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1227,7 +1227,7 @@ int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, } static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -1274,7 +1274,7 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, } static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, - struct drm_atomic_state *state, bool flip) + struct drm_atomic_commit *state, bool flip) { struct drm_crtc_state *new_crtc_state; struct drm_plane_state *new_plane_state; @@ -1431,7 +1431,7 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, } static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c index 99d6d6c93561..dc5913a6456e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c @@ -58,171 +58,76 @@ static bool link_supports_psrsu(struct dc_link *link) return false; } +static void amdgpu_dm_psr_fill_caps(struct dc_link *link, struct psr_caps *caps) +{ + struct dpcd_caps *dpcd_caps = &link->dpcd_caps; + unsigned int power_opts = 0; + + if (amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) + power_opts |= psr_power_opt_smu_opt_static_screen; + power_opts |= psr_power_opt_z10_static_screen; + + if (link->psr_settings.psr_version == DC_PSR_VERSION_1) + caps->psr_version = 1; + else if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) + caps->psr_version = 2; + + caps->psr_rfb_setup_time = (6 - dpcd_caps->psr_info.psr_dpcd_caps.bits.PSR_SETUP_TIME) * 55; + caps->psr_exit_link_training_required = + !dpcd_caps->psr_info.psr_dpcd_caps.bits.LINK_TRAINING_ON_EXIT_NOT_REQUIRED; + caps->edp_revision = dpcd_caps->edp_rev; + caps->support_ver = dpcd_caps->psr_info.psr_version; + caps->su_granularity_required = + dpcd_caps->psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED; + caps->y_coordinate_required = dpcd_caps->psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED; + caps->su_y_granularity = dpcd_caps->psr_info.psr2_su_y_granularity_cap; + caps->alpm_cap = dpcd_caps->alpm_caps.bits.AUX_WAKE_ALPM_CAP; + caps->standby_support = dpcd_caps->alpm_caps.bits.PM_STATE_2A_SUPPORT; + caps->rate_control_caps = 0; /* TODO: read in rc caps from aux */ + caps->psr_power_opt_flag = power_opts; +} + /* * amdgpu_dm_set_psr_caps() - set link psr capabilities * @link: link - * + * @aconnector: amdgpu_dm_connector */ -void amdgpu_dm_set_psr_caps(struct dc_link *link) +bool amdgpu_dm_set_psr_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector) { - if (!(link->connector_signal & SIGNAL_TYPE_EDP)) { - link->psr_settings.psr_feature_enabled = false; - return; - } + struct dc *dc; + unsigned int panel_inst = 0; - if (link->type == dc_connection_none) { - link->psr_settings.psr_feature_enabled = false; - return; - } - - if (link->dpcd_caps.psr_info.psr_version == 0) { - link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; - link->psr_settings.psr_feature_enabled = false; - - } else { - unsigned int panel_inst = 0; - - if (link_supports_psrsu(link)) - link->psr_settings.psr_version = DC_PSR_VERSION_SU_1; - else - link->psr_settings.psr_version = DC_PSR_VERSION_1; - - link->psr_settings.psr_feature_enabled = true; - - /*disable allow psr/psrsu/replay on eDP1*/ - if (dc_get_edp_link_panel_inst(link->ctx->dc, link, &panel_inst) && panel_inst == 1) { - link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; - link->psr_settings.psr_feature_enabled = false; - } - } -} - -/* - * amdgpu_dm_link_setup_psr() - configure psr link - * @stream: stream state - * - * Return: true if success - */ -bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) -{ - struct dc_link *link = NULL; - struct psr_config psr_config = {0}; - struct psr_context psr_context = {0}; - struct dc *dc = NULL; - bool ret = false; - - if (stream == NULL) + if (!link || !aconnector) return false; - link = stream->link; dc = link->ctx->dc; - if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) { - mod_power_calc_psr_configs(&psr_config, link, stream); + /* Reset psr version first */ + link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; - /* linux DM specific updating for psr config fields */ - psr_config.allow_smu_optimizations = - (amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) && - mod_power_only_edp(dc->current_state, stream); - psr_config.allow_multi_disp_optimizations = - (amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); + if (!dc->caps.dmub_caps.psr) + return false; - if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) { - if (!psr_su_set_dsc_slice_height(dc, link, stream, &psr_config)) - return false; - } + if (!(link->connector_signal & SIGNAL_TYPE_EDP)) + return false; - ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context); + if (link->type == dc_connection_none) + return false; - } - DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled); + if (link->dpcd_caps.psr_info.psr_version == 0) + return false; - return ret; -} + /*disable allow psr/psrsu/replay on eDP1*/ + if (dc_get_edp_link_panel_inst(link->ctx->dc, link, &panel_inst) && panel_inst == 1) + return false; -/* - * amdgpu_dm_psr_enable() - enable psr f/w - * @stream: stream state - * - */ -void amdgpu_dm_psr_enable(struct dc_stream_state *stream) -{ - struct dc_link *link = stream->link; - unsigned int vsync_rate_hz = 0; - struct dc_static_screen_params params = {0}; - /* Calculate number of static frames before generating interrupt to - * enter PSR. - */ - // Init fail safe of 2 frames static - unsigned int num_frames_static = 2; - unsigned int power_opt = 0; - bool psr_enable = true; + if (link_supports_psrsu(link)) + link->psr_settings.psr_version = DC_PSR_VERSION_SU_1; + else + link->psr_settings.psr_version = DC_PSR_VERSION_1; - DRM_DEBUG_DRIVER("Enabling psr...\n"); - - vsync_rate_hz = div64_u64(div64_u64(( - stream->timing.pix_clk_100hz * (uint64_t)100), - stream->timing.v_total), - stream->timing.h_total); - - /* Round up - * Calculate number of frames such that at least 30 ms of time has - * passed. - */ - if (vsync_rate_hz != 0) { - unsigned int frame_time_microsec = 1000000 / vsync_rate_hz; - - num_frames_static = (30000 / frame_time_microsec) + 1; - } - - params.triggers.cursor_update = true; - params.triggers.overlay_update = true; - params.triggers.surface_update = true; - params.num_frames = num_frames_static; - - dc_stream_set_static_screen_params(link->ctx->dc, - &stream, 1, - ¶ms); - - /* - * Only enable static-screen optimizations for PSR1. For PSR SU, this - * causes vstartup interrupt issues, used by amdgpu_dm to send vblank - * events. - */ - if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) - power_opt |= psr_power_opt_z10_static_screen; - - dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt); - - if (link->ctx->dc->caps.ips_support) - dc_allow_idle_optimizations(link->ctx->dc, true); -} - -/* - * amdgpu_dm_psr_disable() - disable psr f/w - * @stream: stream state - * - * Return: true if success - */ -bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait) -{ - bool psr_enable = false; - - DRM_DEBUG_DRIVER("Disabling psr...\n"); - - return dc_link_set_psr_allow_active(stream->link, &psr_enable, wait, false, NULL); -} - -/* - * amdgpu_dm_psr_disable_all() - disable psr f/w for all streams - * if psr is enabled on any stream - * - * Return: true if success - */ -bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm) -{ - DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n"); - return dc_set_psr_allow_active(dm->dc, false); + amdgpu_dm_psr_fill_caps(link, &aconnector->psr_caps); + return true; } /* @@ -250,36 +155,37 @@ bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm) break; } } - return allow_active; } -/** - * amdgpu_dm_psr_wait_disable() - Wait for eDP panel to exit PSR - * @stream: stream state attached to the eDP link +/* + * amdgpu_dm_psr_set_event() - set or clear PSR event for stream + * @dm: pointer to amdgpu_display_manager + * @stream: pointer to dc_stream_state + * @set_event: true to set event, false to clear event + * @event: PSR event type + * @wait_for_disable: whether to wait for PSR to be disabled * - * Waits for a max of 500ms for the eDP panel to exit PSR. - * - * Return: true if panel exited PSR, false otherwise. + * Return: true if successful, false otherwise */ -bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream) +bool amdgpu_dm_psr_set_event(struct amdgpu_display_manager *dm, struct dc_stream_state *stream, + bool set_event, enum psr_event event, bool wait_for_disable) { - enum dc_psr_state psr_state = PSR_STATE0; - struct dc_link *link = stream->link; - int retry_count; + unsigned int psr_events; - if (link == NULL) + /* Validate all required parameters */ + if (!stream || !stream->link || + !stream->link->psr_settings.psr_feature_enabled) return false; - for (retry_count = 0; retry_count <= 1000; retry_count++) { - dc_link_get_psr_state(link, &psr_state); - if (psr_state == PSR_STATE0) - break; - udelay(500); - } - - if (retry_count == 1000) + /* Get current psr events */ + if (!mod_power_get_psr_event(dm->power_module, stream, &psr_events)) return false; - return true; + /* If all events already in desired state, return true. */ + if ((psr_events & event) == (set_event ? event : 0)) + return true; + + return mod_power_set_psr_event(dm->power_module, stream, + set_event, event, wait_for_disable); } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h index 4fb8626913cf..16d535806ad6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h @@ -28,16 +28,15 @@ #define AMDGPU_DM_AMDGPU_DM_PSR_H_ #include "amdgpu.h" +#include "dc.h" +#include "modules/inc/mod_power.h" /* the number of pageflips before enabling psr */ #define AMDGPU_DM_PSR_ENTRY_DELAY 5 -void amdgpu_dm_set_psr_caps(struct dc_link *link); -void amdgpu_dm_psr_enable(struct dc_stream_state *stream); -bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream); -bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait); -bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm); +bool amdgpu_dm_set_psr_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector); bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm); -bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream); - +bool amdgpu_dm_psr_set_event(struct amdgpu_display_manager *dm, + struct dc_stream_state *stream, bool set_event, enum psr_event event, + bool wait_for_disable); #endif /* AMDGPU_DM_AMDGPU_DM_PSR_H_ */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c index 8c150b001105..297125d1db70 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c @@ -27,7 +27,6 @@ #include "amdgpu_dm_replay.h" #include "dc_dmub_srv.h" #include "dc.h" -#include "dm_helpers.h" #include "amdgpu_dm.h" #include "modules/power/power_helpers.h" #include "dmub/inc/dmub_cmd.h" @@ -99,13 +98,29 @@ bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector !dc->ctx->dmub_srv->dmub->feature_caps.replay_supported) return false; + /* Mark Replay is supported in link and update related attributes + * This flag presents DPCD caps & amd_vsdb caps satisfy replay requirement. + */ + pr_config.replay_cap_support = true; + // Mark Replay is supported in pr_config pr_config.replay_supported = true; + pr_config.replay_enable_option = pr_enable_option_general_ui | + pr_enable_option_static_screen | + pr_enable_option_static_screen_coasting; + pr_config.replay_power_opt_supported = replay_power_opt_smu_opt_static_screen | + replay_power_opt_z10_static_screen; + pr_config.replay_smu_opt_supported = false; + pr_config.replay_support_fast_resync_in_ultra_sleep_mode = + aconnector->max_vfreq >= 2 * aconnector->min_vfreq; + pr_config.force_disable_desync_error_check = false; + debug_flags = (union replay_debug_flags *)&pr_config.debug_flags; debug_flags->u32All = 0; debug_flags->bitfields.visual_confirm = link->ctx->dc->debug.visual_confirm == VISUAL_CONFIRM_REPLAY; + debug_flags->bitfields.skip_crtc_disabled = dc->debug.replay_skip_crtc_disabled; init_replay_config(link, &pr_config); @@ -113,104 +128,80 @@ bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector } /* - * amdgpu_dm_link_setup_replay() - configure replay link - * @link: link - * @aconnector: aconnector + * amdgpu_dm_link_setup_replay() - config replay settings + * @stream: pointer to dc_stream_state structure + * @vrr_params: pointer to mod_vrr_params structure containing VRR parameters * + * config replay link settings including coasting vtotal calculations. + * + * Return: true if successful, false if any parameter is invalid or replay not supported */ -bool amdgpu_dm_link_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector) +bool amdgpu_dm_link_setup_replay(struct dc_stream_state *stream, + struct mod_vrr_params *vrr_params) { - struct replay_config *pr_config; + struct dc_link *link; + unsigned int static_coasting_vtotal; + unsigned int nom_coasting_vtotal; - if (link == NULL || aconnector == NULL) + if (!stream || !stream->link || !vrr_params) return false; - pr_config = &link->replay_settings.config; - - if (!pr_config->replay_supported) + link = stream->link; + if (!link->replay_settings.config.replay_supported) return false; - pr_config->replay_power_opt_supported = 0x11; - pr_config->replay_smu_opt_supported = false; - pr_config->replay_enable_option |= pr_enable_option_static_screen; - pr_config->replay_support_fast_resync_in_ultra_sleep_mode = aconnector->max_vfreq >= 2 * aconnector->min_vfreq; - pr_config->replay_timing_sync_supported = false; + if (link->replay_settings.replay_feature_enabled) + return true; - if (!pr_config->replay_timing_sync_supported) - pr_config->replay_enable_option &= ~pr_enable_option_general_ui; + calculate_replay_link_off_frame_count(link, stream->timing.v_total, + stream->timing.h_total); - link->replay_settings.replay_feature_enabled = true; + nom_coasting_vtotal = stream->timing.v_total; + static_coasting_vtotal = mod_freesync_calc_v_total_from_refresh(stream, + vrr_params->min_refresh_in_uhz); + set_replay_coasting_vtotal(link, PR_COASTING_TYPE_NOM, + nom_coasting_vtotal); + set_replay_coasting_vtotal(link, PR_COASTING_TYPE_STATIC, + static_coasting_vtotal); return true; } /* - * amdgpu_dm_replay_enable() - enable replay f/w - * @stream: stream state + * amdgpu_dm_replay_set_event() - set or clear replay event for a stream + * @dm: pointer to amdgpu_display_manager + * @stream: pointer to dc_stream_state + * @set_event: true to set event, false to clear event + * @event: replay event type to set or clear + * @wait_for_disable: whether to wait for replay to be disabled before returning * - * Return: true if success + * This function sets or clears a specific replay event for the given stream. + * It temporarily disables idle optimizations during the operation to ensure + * hardware access is available. + * + * Return: true if successful, false if any parameter is invalid or operation fails */ -bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool wait) +bool amdgpu_dm_replay_set_event(struct amdgpu_display_manager *dm, + struct dc_stream_state *stream, + bool set_event, + enum replay_event event, + bool wait_for_disable) { - bool replay_active = true; - struct dc_link *link = NULL; - struct amdgpu_dm_connector *aconnector = NULL; + unsigned int replay_events; - if (stream == NULL) + /* Validate all required parameters */ + if (!stream || !stream->link || + !stream->link->replay_settings.replay_feature_enabled) return false; - /* Check if replay is disabled by connector flag */ - aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; - if (!aconnector || aconnector->disallow_edp_enter_replay) { + /* Get current replay events */ + if (!mod_power_get_replay_event(dm->power_module, stream, &replay_events)) return false; - } - link = stream->link; - - if (link) { - link->dc->link_srv->dp_setup_replay(link, stream); - link->dc->link_srv->edp_set_coasting_vtotal(link, stream->timing.v_total, 0); - DRM_DEBUG_DRIVER("Enabling replay...\n"); - link->dc->link_srv->edp_set_replay_allow_active(link, &replay_active, wait, false, NULL); + /* If all events already in desired state, return true. */ + if ((replay_events & event) == (set_event ? event : 0)) return true; - } - return false; -} - -/* - * amdgpu_dm_replay_disable() - disable replay f/w - * @stream: stream state - * - * Return: true if success - */ -bool amdgpu_dm_replay_disable(struct dc_stream_state *stream) -{ - bool replay_active = false; - struct dc_link *link = NULL; - - if (stream == NULL) - return false; - - link = stream->link; - - if (link) { - DRM_DEBUG_DRIVER("Disabling replay...\n"); - link->dc->link_srv->edp_set_replay_allow_active(stream->link, &replay_active, true, false, NULL); - return true; - } - - return false; -} - -/* - * amdgpu_dm_replay_disable_all() - disable replay f/w - * if replay is enabled on any stream - * - * Return: true if success - */ -bool amdgpu_dm_replay_disable_all(struct amdgpu_display_manager *dm) -{ - DRM_DEBUG_DRIVER("Disabling replay if replay is enabled on any stream\n"); - return dc_set_replay_allow_active(dm->dc, false); + return mod_power_set_replay_event(dm->power_module, stream, + set_event, event, wait_for_disable); } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h index 73b6c67ae5e7..021bf0255516 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h @@ -28,22 +28,16 @@ #define AMDGPU_DM_AMDGPU_DM_REPLAY_H_ #include "amdgpu.h" +#include "dc.h" +#include "modules/inc/mod_power.h" -enum replay_enable_option { - pr_enable_option_static_screen = 0x1, - pr_enable_option_mpo_video = 0x2, - pr_enable_option_full_screen_video = 0x4, - pr_enable_option_general_ui = 0x8, - pr_enable_option_static_screen_coasting = 0x10000, - pr_enable_option_mpo_video_coasting = 0x20000, - pr_enable_option_full_screen_video_coasting = 0x40000, -}; - -bool amdgpu_dm_link_supports_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector); -bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool enable); -bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector); -bool amdgpu_dm_link_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector); -bool amdgpu_dm_replay_disable(struct dc_stream_state *stream); -bool amdgpu_dm_replay_disable_all(struct amdgpu_display_manager *dm); - +bool amdgpu_dm_link_supports_replay(struct dc_link *link, + struct amdgpu_dm_connector *aconnector); +bool amdgpu_dm_set_replay_caps(struct dc_link *link, + struct amdgpu_dm_connector *aconnector); +bool amdgpu_dm_link_setup_replay(struct dc_stream_state *stream, + struct mod_vrr_params *vrr_params); +bool amdgpu_dm_replay_set_event(struct amdgpu_display_manager *dm, + struct dc_stream_state *stream, bool set_event, + enum replay_event event, bool wait_for_disable); #endif /* AMDGPU_DM_AMDGPU_DM_REPLAY_H_ */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index 8550d5e8b753..84dcb573d98f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -62,3 +62,30 @@ void dm_trace_smu_exit(bool success, uint32_t response, struct dc_context *ctx) } /**** power component interfaces ****/ + +bool dm_query_extended_brightness_caps(struct dc_context *ctx, + enum dm_acpi_display_type display, struct dm_acpi_atif_backlight_caps *pCaps) +{ + struct amdgpu_device *adev; + struct amdgpu_display_manager *dm; + int bl_index = (display == AcpiDisplayType_LCD1) ? 0 : 1; + + if (!ctx || !pCaps || !ctx->driver_context) + return false; + + adev = (struct amdgpu_device *)ctx->driver_context; + dm = &adev->dm; + + amdgpu_dm_update_backlight_caps(dm, bl_index); + + pCaps->num_data_points = dm->backlight_caps[bl_index].data_points; + pCaps->max_input_signal = dm->backlight_caps[bl_index].max_input_signal; + pCaps->min_input_signal = dm->backlight_caps[bl_index].min_input_signal; + pCaps->ac_level_percentage = dm->backlight_caps[bl_index].ac_level; + pCaps->dc_level_percentage = dm->backlight_caps[bl_index].dc_level; + + if (pCaps->num_data_points > 0) + memcpy(pCaps->data_points, dm->backlight_caps[bl_index].luminance_data, + sizeof(struct dm_bl_data_point) * pCaps->num_data_points); + return true; +} diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index e0fab8878d19..f33a2c1e0da5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -108,7 +108,7 @@ TRACE_EVENT(amdgpu_dm_connector_atomic_check, TP_STRUCT__entry( __field(uint32_t, conn_id) __field(const struct drm_connector_state *, conn_state) - __field(const struct drm_atomic_state *, state) + __field(const struct drm_atomic_commit *, state) __field(const struct drm_crtc_commit *, commit) __field(uint32_t, crtc_id) __field(uint32_t, best_encoder_id) @@ -163,7 +163,7 @@ TRACE_EVENT(amdgpu_dm_crtc_atomic_check, TP_ARGS(state), TP_STRUCT__entry( - __field(const struct drm_atomic_state *, state) + __field(const struct drm_atomic_commit *, state) __field(const struct drm_crtc_state *, crtc_state) __field(const struct drm_crtc_commit *, commit) __field(uint32_t, crtc_id) @@ -229,7 +229,7 @@ DECLARE_EVENT_CLASS(amdgpu_dm_plane_state_template, __field(uint32_t, plane_id) __field(enum drm_plane_type, plane_type) __field(const struct drm_plane_state *, plane_state) - __field(const struct drm_atomic_state *, state) + __field(const struct drm_atomic_commit *, state) __field(uint32_t, crtc_id) __field(uint32_t, fb_id) __field(uint32_t, fb_format) @@ -315,11 +315,11 @@ DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_atomic_update_cursor, TP_ARGS(state)); TRACE_EVENT(amdgpu_dm_atomic_state_template, - TP_PROTO(const struct drm_atomic_state *state), + TP_PROTO(const struct drm_atomic_commit *state), TP_ARGS(state), TP_STRUCT__entry( - __field(const struct drm_atomic_state *, state) + __field(const struct drm_atomic_commit *, state) __field(bool, allow_modeset) __field(bool, legacy_cursor_update) __field(bool, async_update) @@ -347,23 +347,23 @@ TRACE_EVENT(amdgpu_dm_atomic_state_template, ); DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_begin, - TP_PROTO(const struct drm_atomic_state *state), + TP_PROTO(const struct drm_atomic_commit *state), TP_ARGS(state)); DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_finish, - TP_PROTO(const struct drm_atomic_state *state), + TP_PROTO(const struct drm_atomic_commit *state), TP_ARGS(state)); DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_check_begin, - TP_PROTO(const struct drm_atomic_state *state), + TP_PROTO(const struct drm_atomic_commit *state), TP_ARGS(state)); TRACE_EVENT(amdgpu_dm_atomic_check_finish, - TP_PROTO(const struct drm_atomic_state *state, int res), + TP_PROTO(const struct drm_atomic_commit *state, int res), TP_ARGS(state, res), TP_STRUCT__entry( - __field(const struct drm_atomic_state *, state) + __field(const struct drm_atomic_commit *, state) __field(int, res) __field(bool, async_update) __field(bool, allow_modeset) diff --git a/drivers/gpu/drm/amd/display/dc/basics/conversion.c b/drivers/gpu/drm/amd/display/dc/basics/conversion.c index bd1f60ecaba4..a1f2350388e2 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/conversion.c +++ b/drivers/gpu/drm/amd/display/dc/basics/conversion.c @@ -131,7 +131,7 @@ void convert_hw_matrix(struct fixed31_32 *matrix, uint16_t *reg, uint32_t buffer_size) { - for (int i = 0; i < buffer_size; ++i) + for (uint32_t i = 0; i < buffer_size; ++i) matrix[i] = int_frac_to_fixed_point(reg[i], 2, 13); } diff --git a/drivers/gpu/drm/amd/display/dc/basics/custom_float.c b/drivers/gpu/drm/amd/display/dc/basics/custom_float.c index ae05ded9a7f3..d313584335d3 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/custom_float.c +++ b/drivers/gpu/drm/amd/display/dc/basics/custom_float.c @@ -90,7 +90,7 @@ static bool build_custom_float(struct fixed31_32 value, dc_fixpt_lt(dc_fixpt_one, mantiss)) mantiss = dc_fixpt_zero; else - mantiss = dc_fixpt_shl(mantiss, format->mantissa_bits); + mantiss = dc_fixpt_shl(mantiss, (unsigned char)format->mantissa_bits); *mantissa = dc_fixpt_floor(mantiss); diff --git a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c index f37a43f4172e..1b8e843020d6 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c @@ -302,7 +302,7 @@ static void calculate_bandwidth( fbc_enabled = false; lpt_enabled = false; for (i = 4; i <= maximum_number_of_surfaces - 3; i++) { - if (i < data->number_of_displays + 4) { + if (i < (int32_t)(data->number_of_displays + 4)) { if (i == 4 && data->d0_underlay_mode == bw_def_underlay_only) { data->enable[i] = 0; data->use_alpha[i] = 0; @@ -2767,7 +2767,7 @@ static bool is_display_configuration_supported( const struct bw_calcs_vbios *vbios, const struct dce_bw_output *calcs_output) { - uint32_t int_max_clk; + int32_t int_max_clk; int_max_clk = bw_fixed_to_int(vbios->high_voltage_max_dispclk); int_max_clk *= 1000; /* MHz to kHz */ @@ -3077,7 +3077,7 @@ bool bw_calcs(struct dc_context *ctx, } calculate_bandwidth(dceip, vbios, data); - yclk_lvl = data->y_clk_level; + yclk_lvl = (uint8_t)data->y_clk_level; calcs_output->nbp_state_change_enable = data->nbp_state_change_enable; diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index dd362071a6c9..30567ef74e5c 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -794,17 +794,19 @@ static enum bp_result bios_parser_external_encoder_control( static enum bp_result bios_parser_dac_load_detection( struct dc_bios *dcb, - enum engine_id engine_id) + enum engine_id engine_id, + struct graphics_object_id ext_enc_id) { struct bios_parser *bp = BP_FROM_DCB(dcb); struct dc_context *ctx = dcb->ctx; struct bp_load_detection_parameters bp_params = {0}; + struct bp_external_encoder_control ext_cntl = {0}; enum bp_result bp_result = BP_RESULT_UNSUPPORTED; uint32_t bios_0_scratch; uint32_t device_id_mask = 0; - bp_params.device_id = get_support_mask_for_device_id( - DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1); + bp_params.device_id = (uint16_t)get_support_mask_for_device_id( + DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1); if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT) device_id_mask = ATOM_S0_CRT1_MASK; @@ -824,6 +826,13 @@ static enum bp_result bios_parser_dac_load_detection( bp_params.engine_id = engine_id; bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params); + } else if (ext_enc_id.id) { + if (!bp->cmd_tbl.external_encoder_control) + return BP_RESULT_UNSUPPORTED; + + ext_cntl.action = EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT; + ext_cntl.encoder_id = ext_enc_id; + bp_result = bp->cmd_tbl.external_encoder_control(bp, &ext_cntl); } if (bp_result != BP_RESULT_OK) @@ -1304,6 +1313,60 @@ static enum bp_result bios_parser_get_embedded_panel_info( return BP_RESULT_FAILURE; } +static enum bp_result get_embedded_panel_extra_info( + struct bios_parser *bp, + struct embedded_panel_info *info, + const uint32_t table_offset) +{ + uint8_t *record = bios_get_image(&bp->base, table_offset, 1); + ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; + ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; + + while (*record != ATOM_RECORD_END_TYPE) { + switch (*record) { + case LCD_MODE_PATCH_RECORD_MODE_TYPE: + record += sizeof(ATOM_PATCH_RECORD_MODE); + break; + case LCD_RTS_RECORD_TYPE: + record += sizeof(ATOM_LCD_RTS_RECORD); + break; + case LCD_CAP_RECORD_TYPE: + record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); + break; + case LCD_FAKE_EDID_PATCH_RECORD_TYPE: + fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; + if (fake_edid_record->ucFakeEDIDLength) { + if (fake_edid_record->ucFakeEDIDLength == 128) + info->fake_edid_size = + fake_edid_record->ucFakeEDIDLength; + else + info->fake_edid_size = + fake_edid_record->ucFakeEDIDLength * 128; + + info->fake_edid = fake_edid_record->ucFakeEDIDString; + + record += struct_size(fake_edid_record, + ucFakeEDIDString, + info->fake_edid_size); + } else { + /* empty fake edid record must be 3 bytes long */ + record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1; + } + break; + case LCD_PANEL_RESOLUTION_RECORD_TYPE: + panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; + info->panel_width_mm = panel_res_record->usHSize; + info->panel_height_mm = panel_res_record->usVSize; + record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); + break; + default: + return BP_RESULT_BADBIOSTABLE; + } + } + + return BP_RESULT_OK; +} + static enum bp_result get_embedded_panel_info_v1_2( struct bios_parser *bp, struct embedded_panel_info *info) @@ -1382,7 +1445,7 @@ static enum bp_result get_embedded_panel_info_v1_2( info->ss_id = lvds->ucSS_Id; { - uint8_t rr = le16_to_cpu(lvds->usSupportedRefreshRate); + uint16_t rr = le16_to_cpu(lvds->usSupportedRefreshRate); /* Get minimum supported refresh rate*/ if (SUPPORTED_LCD_REFRESHRATE_30Hz & rr) info->supported_rr.REFRESH_RATE_30HZ = 1; @@ -1420,6 +1483,10 @@ static enum bp_result get_embedded_panel_info_v1_2( if (ATOM_PANEL_MISC_API_ENABLED & lvds->ucLVDS_Misc) info->lcd_timing.misc_info.API_ENABLED = true; + if (lvds->usExtInfoTableOffset) + return get_embedded_panel_extra_info(bp, info, + le16_to_cpu(lvds->usExtInfoTableOffset) + DATA_TABLES(LCD_Info)); + return BP_RESULT_OK; } @@ -1545,6 +1612,10 @@ static enum bp_result get_embedded_panel_info_v1_3( (uint32_t) (ATOM_PANEL_MISC_V13_GREY_LEVEL & lvds->ucLCD_Misc) >> ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT; + if (lvds->usExtInfoTableOffset) + return get_embedded_panel_extra_info(bp, info, + le16_to_cpu(lvds->usExtInfoTableOffset) + DATA_TABLES(LCD_Info)); + return BP_RESULT_OK; } diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index a1c08e1cc411..1b09a7907cb4 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -157,7 +157,7 @@ static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) break; } - return count; + return (uint8_t)count; } static struct graphics_object_id bios_parser_get_connector_id( @@ -401,7 +401,7 @@ static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, return BP_RESULT_BADINPUT; if (id.type == OBJECT_TYPE_GENERIC) { - dummy_record.i2c_id = id.id; + dummy_record.i2c_id = (uint8_t)id.id; if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) return BP_RESULT_OK; @@ -1228,7 +1228,7 @@ static enum bp_result get_disp_caps_v4_1( if (!disp_cntl_tbl) return BP_RESULT_BADBIOSTABLE; - *dce_caps = disp_cntl_tbl->display_caps; + *dce_caps = (uint8_t)disp_cntl_tbl->display_caps; return result; } @@ -1252,7 +1252,7 @@ static enum bp_result get_disp_caps_v4_2( if (!disp_cntl_tbl) return BP_RESULT_BADBIOSTABLE; - *dce_caps = disp_cntl_tbl->display_caps; + *dce_caps = (uint8_t)disp_cntl_tbl->display_caps; return result; } @@ -1276,7 +1276,7 @@ static enum bp_result get_disp_caps_v4_3( if (!disp_cntl_tbl) return BP_RESULT_BADBIOSTABLE; - *dce_caps = disp_cntl_tbl->display_caps; + *dce_caps = (uint8_t)disp_cntl_tbl->display_caps; return result; } @@ -1300,7 +1300,7 @@ static enum bp_result get_disp_caps_v4_4( if (!disp_cntl_tbl) return BP_RESULT_BADBIOSTABLE; - *dce_caps = disp_cntl_tbl->display_caps; + *dce_caps = (uint8_t)disp_cntl_tbl->display_caps; return result; } @@ -1324,7 +1324,7 @@ static enum bp_result get_disp_caps_v4_5( if (!disp_cntl_tbl) return BP_RESULT_BADBIOSTABLE; - *dce_caps = disp_cntl_tbl->display_caps; + *dce_caps = (uint8_t)disp_cntl_tbl->display_caps; return result; } @@ -2585,7 +2585,7 @@ static enum bp_result get_integrated_info_v11( info->ext_disp_conn_info.path[i].channel_mapping.raw = info_v11->extdispconninfo.path[i].channelmapping; info->ext_disp_conn_info.path[i].caps = - le16_to_cpu(info_v11->extdispconninfo.path[i].caps); + (unsigned short)le16_to_cpu(info_v11->extdispconninfo.path[i].caps); } info->ext_disp_conn_info.checksum = info_v11->extdispconninfo.checksum; @@ -2790,7 +2790,7 @@ static enum bp_result get_integrated_info_v2_1( info->ext_disp_conn_info.path[i].channel_mapping.raw = info_v2_1->extdispconninfo.path[i].channelmapping; info->ext_disp_conn_info.path[i].caps = - le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); + (unsigned short)le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); } info->ext_disp_conn_info.checksum = @@ -2954,7 +2954,7 @@ static enum bp_result get_integrated_info_v2_2( info->ext_disp_conn_info.path[i].channel_mapping.raw = info_v2_2->extdispconninfo.path[i].channelmapping; info->ext_disp_conn_info.path[i].caps = - le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps); + (unsigned short)le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps); } info->ext_disp_conn_info.checksum = @@ -2977,6 +2977,7 @@ static enum bp_result get_integrated_info_v2_2( info->edp1_info.edp_panel_bpc = info_v2_2->edp1_info.edp_panel_bpc; info->edp1_info.edp_bootup_bl_level = + info_v2_2->edp1_info.edp_bootup_bl_level; info->edp2_info.edp_backlight_pwm_hz = le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz); diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c index f6e22dcecf29..0df84394a325 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c @@ -1521,8 +1521,8 @@ static enum bp_result adjust_display_pll_v2( if (pixel_clock_10KHz_in != 0) { bp_params->adjusted_pixel_clock = - div_u64(pixel_clk * pixel_clk_10_khz_out, - pixel_clock_10KHz_in); + (uint32_t)div_u64(pixel_clk * pixel_clk_10_khz_out, + pixel_clock_10KHz_in); } else { bp_params->adjusted_pixel_clock = 0; BREAK_TO_DEBUGGER(); @@ -1571,8 +1571,8 @@ static enum bp_result adjust_display_pll_v3( if (pixel_clk_10_kHz_in != 0) { bp_params->adjusted_pixel_clock = - div_u64(pixel_clk * pixel_clk_10_khz_out, - pixel_clk_10_kHz_in); + (uint32_t)div_u64(pixel_clk * pixel_clk_10_khz_out, + pixel_clk_10_kHz_in); } else { bp_params->adjusted_pixel_clock = 0; BREAK_TO_DEBUGGER(); @@ -2662,8 +2662,8 @@ static enum bp_result set_dce_clock_v2_1( !cmd->dc_clock_type_to_atom(bp_params->clock_type, &atom_clock_type)) return BP_RESULT_BADINPUT; - params.asParam.ucDCEClkSrc = atom_pll_id; - params.asParam.ucDCEClkType = atom_clock_type; + params.asParam.ucDCEClkSrc = (uint8_t)atom_pll_id; + params.asParam.ucDCEClkType = (uint8_t)atom_clock_type; if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) { if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK) diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c index 17ef515c6c69..88625daf5378 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c @@ -929,8 +929,8 @@ static enum bp_result set_dce_clock_v2_1( &atom_clock_type)) return BP_RESULT_BADINPUT; - params.param.dceclksrc = atom_pll_id; - params.param.dceclktype = atom_clock_type; + params.param.dceclksrc = (uint8_t)atom_pll_id; + params.param.dceclktype = (uint8_t)atom_clock_type; if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) { if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c index cd4c45516616..b35a44976477 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c @@ -63,11 +63,11 @@ static const struct state_dependent_clocks dce110_max_clks_by_state[] = { /*ClocksStatePerformance*/ { .display_clk_khz = 643000, .pixel_clk_khz = 400000 } }; -static int determine_sclk_from_bounding_box( +static uint32_t determine_sclk_from_bounding_box( const struct dc *dc, - int required_sclk) + uint32_t required_sclk) { - int i; + uint32_t i; /* * Some asics do not give us sclk levels, so we just report the actual @@ -127,7 +127,7 @@ void dce110_fill_display_configs( pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; - pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator; + pp_display_cfg->crtc_index = (uint8_t)dc->res_pool->res_cap->num_timing_generator; for (j = 0; j < context->stream_count; j++) { int k; @@ -151,7 +151,7 @@ void dce110_fill_display_configs( num_cfgs++; cfg->signal = pipe_ctx->stream->signal; - cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; + cfg->pipe_idx = (uint8_t)pipe_ctx->stream_res.tg->inst; cfg->src_height = stream->src.height; cfg->src_width = stream->src.width; cfg->ddi_channel_mapping = @@ -189,7 +189,7 @@ void dce110_fill_display_configs( pp_display_cfg->line_time_in_us = 0; } - pp_display_cfg->display_count = num_cfgs; + pp_display_cfg->display_count = (uint8_t)num_cfgs; } void dce11_pplib_apply_display_requirements( diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c index 369421e46c52..06a51f47aed7 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c @@ -88,7 +88,7 @@ static void ramp_up_dispclk_with_dpp( struct dc_clocks *new_clocks, bool safe_to_lower) { - int i; + uint32_t i; int dispclk_to_dpp_threshold = rv1_determine_dppclk_threshold(clk_mgr, new_clocks); bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index bb4f3bd7532e..c0abbdd2cf5c 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -104,7 +104,7 @@ uint32_t dentist_get_did_from_divider(int divider) void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower) { - int i; + uint32_t i; clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { @@ -255,9 +255,12 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, pp_smu->set_display_count(&pp_smu->pp_smu, display_count); } - if (dc->debug.force_min_dcfclk_mhz > 0) - new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? - new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + if (dc->debug.force_min_dcfclk_mhz > 0) { + int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000; + + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > force_min_dcfclk_khz) ? + new_clocks->dcfclk_khz : force_min_dcfclk_khz; + } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index 09e83097a623..b5378344d2bc 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -106,7 +106,7 @@ static void rn_set_low_power_state(struct clk_mgr *clk_mgr_base) static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, int ref_dpp_clk, bool safe_to_lower) { - int i; + uint32_t i; clk_mgr->dccg->ref_dppclk = ref_dpp_clk; @@ -462,8 +462,10 @@ static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_sm if (!bw_params->wm_table.entries[i].valid) continue; - ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; - ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; + ranges->reader_wm_sets[num_valid_sets].wm_inst = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + ranges->reader_wm_sets[num_valid_sets].wm_type = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; @@ -474,9 +476,11 @@ static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_sm ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0; else { /* add 1 to make it non-overlapping with next lvl */ - ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } - ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; + ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -640,6 +644,8 @@ static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsi static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info) { int i, j = 0; + unsigned int entry_idx; + unsigned int wm_idx; j = -1; @@ -663,28 +669,28 @@ static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params bw_params->clk_table.num_entries = j + 1; - for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { - bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq; - bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; - bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol; - bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol); - bw_params->clk_table.entries[i].socclk_mhz = find_socclk_for_voltage(clock_table, - bw_params->clk_table.entries[i].voltage); + for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++, j--) { + bw_params->clk_table.entries[entry_idx].fclk_mhz = clock_table->FClocks[j].Freq; + bw_params->clk_table.entries[entry_idx].memclk_mhz = clock_table->MemClocks[j].Freq; + bw_params->clk_table.entries[entry_idx].voltage = clock_table->FClocks[j].Vol; + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol); + bw_params->clk_table.entries[entry_idx].socclk_mhz = find_socclk_for_voltage(clock_table, + bw_params->clk_table.entries[entry_idx].voltage); } bw_params->vram_type = bios_info->memory_type; bw_params->num_channels = bios_info->ma_channel_number; - for (i = 0; i < WM_SET_COUNT; i++) { - bw_params->wm_table.entries[i].wm_inst = i; + for (wm_idx = 0; wm_idx < (unsigned int)WM_SET_COUNT; wm_idx++) { + bw_params->wm_table.entries[wm_idx].wm_inst = wm_idx; - if (i >= bw_params->clk_table.num_entries) { - bw_params->wm_table.entries[i].valid = false; + if (wm_idx >= bw_params->clk_table.num_entries) { + bw_params->wm_table.entries[wm_idx].valid = false; continue; } - bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; - bw_params->wm_table.entries[i].valid = true; + bw_params->wm_table.entries[wm_idx].wm_type = WM_TYPE_PSTATE_CHG; + bw_params->wm_table.entries[wm_idx].valid = true; } if (bw_params->vram_type == LpDdr4MemType) { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c index dcec9d0f8c34..5641f9089b0b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c @@ -78,9 +78,9 @@ static const struct clk_mgr_mask clk_mgr_mask = { /* Query SMU for all clock states for a particular clock */ -static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels) +static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, uint8_t *num_levels) { - unsigned int i; + uint8_t i; char *entry_i = (char *)entry_0; uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF); @@ -109,7 +109,7 @@ static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr) void dcn3_init_clocks(struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); - unsigned int num_levels; + uint8_t num_levels; memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); clk_mgr_base->clks.p_state_change_support = true; @@ -228,13 +228,16 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, if (enter_display_off == safe_to_lower) dcn30_smu_set_num_of_displays(clk_mgr, display_count); - if (dc->debug.force_min_dcfclk_mhz > 0) - new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? - new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + if (dc->debug.force_min_dcfclk_mhz > 0) { + int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000; + + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > force_min_dcfclk_khz) ? + new_clocks->dcfclk_khz : force_min_dcfclk_khz; + } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { @@ -251,8 +254,10 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, // invalidate the current P-State forced min in certain dc_mode_softmax situations if (dc->clk_mgr->dc_mode_softmax_enabled && safe_to_lower && !p_state_change_support) { - if ((new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) != - (clk_mgr_base->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)) + int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000; + + if ((new_clocks->dramclk_khz <= softmax_memclk_khz) != + (clk_mgr_base->clks.dramclk_khz <= softmax_memclk_khz)) update_pstate_unsupported_clk = true; } @@ -263,12 +268,13 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, /* to disable P-State switching, set UCLK min = max */ if (!clk_mgr_base->clks.p_state_change_support) { if (dc->clk_mgr->dc_mode_softmax_enabled && - new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) + new_clocks->dramclk_khz <= (int)(dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)) dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - dc->clk_mgr->bw_params->dc_mode_softmax_memclk); + (uint16_t)dc->clk_mgr->bw_params->dc_mode_softmax_memclk); else dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); + (uint16_t)clk_mgr_base->bw_params->clk_table.entries[ + clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); } } @@ -281,20 +287,20 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */ if (clk_mgr_base->clks.p_state_change_support && (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support)) - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz) dpp_clock_lowered = true; clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); update_dppclk = true; } if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz)); + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz)); update_dispclk = true; } @@ -323,7 +329,7 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, static void dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base) { - unsigned int i; + uint8_t i; struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table; @@ -363,13 +369,14 @@ static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_ if (current_mode) { if (clk_mgr_base->clks.p_state_change_support) dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); + (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); else dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); + (uint16_t)clk_mgr_base->bw_params->clk_table.entries[ + clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); } else { dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); + (uint16_t)clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); } } @@ -382,7 +389,8 @@ static void dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base) return; dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); + (uint16_t)clk_mgr_base->bw_params->clk_table.entries[ + clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); } static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) @@ -392,7 +400,7 @@ static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memcl if (!clk_mgr->smu_present) return; - dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); + dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz); } static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) { @@ -400,14 +408,14 @@ static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memcl if (!clk_mgr->smu_present) return; - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz); } /* Get current memclk states, update bounding box */ static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); - unsigned int num_levels; + uint8_t num_levels; if (!clk_mgr->smu_present) return; @@ -480,7 +488,7 @@ static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct d if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) { clk_mgr_base->clks.phyclk_khz = max_phyclk_req; - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz)); + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz)); } } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c index 57ba7bc4d16e..e40bbc495fc4 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c @@ -385,7 +385,7 @@ static void vg_init_clocks(struct clk_mgr *clk_mgr) static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table) { - int i, num_valid_sets; + uint8_t i, num_valid_sets; num_valid_sets = 0; @@ -394,8 +394,11 @@ static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct wa if (!bw_params->wm_table.entries[i].valid) continue; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; @@ -406,10 +409,10 @@ static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct wa else { /* add 1 to make it non-overlapping with next lvl */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = - bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = - bw_params->clk_table.entries[i].dcfclk_mhz; + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -530,7 +533,7 @@ static struct clk_bw_params vg_bw_params = { static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) { uint32_t max = 0; - int i; + uint32_t i; for (i = 0; i < num_clocks; ++i) { if (clocks[i] > max) @@ -562,6 +565,7 @@ static void vg_clk_mgr_helper_populate_bw_params( const struct vg_dpm_clocks *clock_table) { int i, j; + unsigned int entry_idx; struct clk_bw_params *bw_params = clk_mgr->base.bw_params; uint32_t max_dispclk = 0, max_dppclk = 0; @@ -596,16 +600,17 @@ static void vg_clk_mgr_helper_populate_bw_params( bw_params->clk_table.num_entries = j + 1; - for (i = 0; i < bw_params->clk_table.num_entries - 1; i++, j--) { - bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; - bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; - bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage; - bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage); + for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries - 1; entry_idx++, j--) { + bw_params->clk_table.entries[entry_idx].fclk_mhz = clock_table->DfPstateTable[j].fclk; + bw_params->clk_table.entries[entry_idx].memclk_mhz = clock_table->DfPstateTable[j].memclk; + bw_params->clk_table.entries[entry_idx].voltage = clock_table->DfPstateTable[j].voltage; + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage); /* Now update clocks we do read */ - bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; - bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; + bw_params->clk_table.entries[entry_idx].dispclk_mhz = max_dispclk; + bw_params->clk_table.entries[entry_idx].dppclk_mhz = max_dppclk; } + i = (int)entry_idx; bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage; @@ -616,16 +621,16 @@ static void vg_clk_mgr_helper_populate_bw_params( bw_params->vram_type = bios_info->memory_type; bw_params->num_channels = bios_info->ma_channel_number; - for (i = 0; i < WM_SET_COUNT; i++) { - bw_params->wm_table.entries[i].wm_inst = i; + for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) { + bw_params->wm_table.entries[entry_idx].wm_inst = entry_idx; - if (i >= bw_params->clk_table.num_entries) { - bw_params->wm_table.entries[i].valid = false; + if (entry_idx >= bw_params->clk_table.num_entries) { + bw_params->wm_table.entries[entry_idx].valid = false; continue; } - bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; - bw_params->wm_table.entries[i].valid = true; + bw_params->wm_table.entries[entry_idx].wm_type = WM_TYPE_PSTATE_CHG; + bw_params->wm_table.entries[entry_idx].valid = true; } if (bw_params->vram_type == LpDdr4MemType) { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c index 89fc482947ef..dc7f50095a13 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c @@ -114,7 +114,7 @@ static int dcn31_get_active_display_cnt_wa( static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable) { struct dc *dc = clk_mgr_base->ctx->dc; - int i; + uint8_t i; for (i = 0; i < dc->res_pool->pipe_count; ++i) { struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; @@ -424,7 +424,7 @@ static struct dcn31_watermarks dummy_wms = { 0 }; static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table) { - int i, num_valid_sets; + uint8_t i, num_valid_sets; num_valid_sets = 0; @@ -433,8 +433,10 @@ static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct if (!bw_params->wm_table.entries[i].valid) continue; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; @@ -445,10 +447,10 @@ static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct else { /* add 1 to make it non-overlapping with next lvl */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = - bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = - bw_params->clk_table.entries[i].dcfclk_mhz; + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -523,7 +525,7 @@ static void dcn31_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) { uint32_t max = 0; - int i; + uint32_t i; for (i = 0; i < num_clocks; ++i) { if (clocks[i] > max) @@ -539,8 +541,8 @@ static unsigned int find_clk_for_voltage( unsigned int voltage) { int i; - int max_voltage = 0; - int clock = 0; + unsigned int max_voltage = 0; + unsigned int clock = 0; for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) { if (clock_table->SocVoltage[i] == voltage) { @@ -561,6 +563,7 @@ static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk const DpmClocks_t *clock_table) { int i, j; + unsigned int entry_idx; struct clk_bw_params *bw_params = clk_mgr->base.bw_params; uint32_t max_dispclk = 0, max_dppclk = 0; @@ -595,24 +598,24 @@ static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk ASSERT(0); } - for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { - bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk; - bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; - bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage; + for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++, j--) { + bw_params->clk_table.entries[entry_idx].fclk_mhz = clock_table->DfPstateTable[j].FClk; + bw_params->clk_table.entries[entry_idx].memclk_mhz = clock_table->DfPstateTable[j].MemClk; + bw_params->clk_table.entries[entry_idx].voltage = clock_table->DfPstateTable[j].Voltage; switch (clock_table->DfPstateTable[j].WckRatio) { case WCK_RATIO_1_2: - bw_params->clk_table.entries[i].wck_ratio = 2; + bw_params->clk_table.entries[entry_idx].wck_ratio = 2; break; case WCK_RATIO_1_4: - bw_params->clk_table.entries[i].wck_ratio = 4; + bw_params->clk_table.entries[entry_idx].wck_ratio = 4; break; default: - bw_params->clk_table.entries[i].wck_ratio = 1; + bw_params->clk_table.entries[entry_idx].wck_ratio = 1; } - bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage); - bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage); - bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; - bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage); + bw_params->clk_table.entries[entry_idx].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage); + bw_params->clk_table.entries[entry_idx].dispclk_mhz = max_dispclk; + bw_params->clk_table.entries[entry_idx].dppclk_mhz = max_dppclk; } bw_params->vram_type = bios_info->memory_type; @@ -620,16 +623,16 @@ static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; //bw_params->dram_channel_width_bytes = dc->ctx->asic_id.vram_width; bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4; - for (i = 0; i < WM_SET_COUNT; i++) { - bw_params->wm_table.entries[i].wm_inst = i; + for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) { + bw_params->wm_table.entries[entry_idx].wm_inst = entry_idx; - if (i >= bw_params->clk_table.num_entries) { - bw_params->wm_table.entries[i].valid = false; + if (entry_idx >= bw_params->clk_table.num_entries) { + bw_params->wm_table.entries[entry_idx].valid = false; continue; } - bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; - bw_params->wm_table.entries[i].valid = true; + bw_params->wm_table.entries[entry_idx].wm_type = WM_TYPE_PSTATE_CHG; + bw_params->wm_table.entries[entry_idx].valid = true; } } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c index b08a70a2f571..5fe59adc862f 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c @@ -149,7 +149,7 @@ static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state bool safe_to_lower, bool disable) { struct dc *dc = clk_mgr_base->ctx->dc; - int i; + uint8_t i; for (i = 0; i < dc->res_pool->pipe_count; ++i) { struct pipe_ctx *pipe = safe_to_lower @@ -295,7 +295,7 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { - int requested_dispclk_khz = new_clocks->dispclk_khz; + uint32_t requested_dispclk_khz = new_clocks->dispclk_khz; dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); @@ -495,7 +495,7 @@ static struct dcn314_ss_info_table ss_info_table = { static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks *table) { - int i, num_valid_sets; + uint8_t i, num_valid_sets; num_valid_sets = 0; @@ -504,8 +504,10 @@ static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struc if (!bw_params->wm_table.entries[i].valid) continue; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; @@ -516,10 +518,10 @@ static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struc else { /* add 1 to make it non-overlapping with next lvl */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = - bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = - bw_params->clk_table.entries[i].dcfclk_mhz; + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -614,7 +616,7 @@ static unsigned int convert_wck_ratio(uint8_t wck_ratio) static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) { uint32_t max = 0; - int i; + uint32_t i; for (i = 0; i < num_clocks; ++i) { if (clocks[i] > max) @@ -632,6 +634,7 @@ static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *cl struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1]; uint32_t max_pstate = 0, max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0; int i; + unsigned int entry_idx; /* Find highest valid fclk pstate */ for (i = 0; i < clock_table->NumDfPstatesEnabled; i++) { @@ -721,26 +724,26 @@ static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *cl * Set any 0 clocks to max default setting. Not an issue for * power since we aren't doing switching in such case anyway */ - for (i = 0; i < bw_params->clk_table.num_entries; i++) { - if (!bw_params->clk_table.entries[i].fclk_mhz) { - bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz; - bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz; - bw_params->clk_table.entries[i].voltage = def_max.voltage; + for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++) { + if (!bw_params->clk_table.entries[entry_idx].fclk_mhz) { + bw_params->clk_table.entries[entry_idx].fclk_mhz = def_max.fclk_mhz; + bw_params->clk_table.entries[entry_idx].memclk_mhz = def_max.memclk_mhz; + bw_params->clk_table.entries[entry_idx].voltage = def_max.voltage; } - if (!bw_params->clk_table.entries[i].dcfclk_mhz) - bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; - if (!bw_params->clk_table.entries[i].socclk_mhz) - bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz; - if (!bw_params->clk_table.entries[i].dispclk_mhz) - bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz; - if (!bw_params->clk_table.entries[i].dppclk_mhz) - bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz; - if (!bw_params->clk_table.entries[i].phyclk_mhz) - bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz; - if (!bw_params->clk_table.entries[i].phyclk_d18_mhz) - bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz; - if (!bw_params->clk_table.entries[i].dtbclk_mhz) - bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dcfclk_mhz) + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = def_max.dcfclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].socclk_mhz) + bw_params->clk_table.entries[entry_idx].socclk_mhz = def_max.socclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dispclk_mhz) + bw_params->clk_table.entries[entry_idx].dispclk_mhz = def_max.dispclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dppclk_mhz) + bw_params->clk_table.entries[entry_idx].dppclk_mhz = def_max.dppclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].phyclk_mhz) + bw_params->clk_table.entries[entry_idx].phyclk_mhz = def_max.phyclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz) + bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz = def_max.phyclk_d18_mhz; + if (!bw_params->clk_table.entries[entry_idx].dtbclk_mhz) + bw_params->clk_table.entries[entry_idx].dtbclk_mhz = def_max.dtbclk_mhz; } ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); bw_params->vram_type = bios_info->memory_type; @@ -748,16 +751,16 @@ static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *cl bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4; - for (i = 0; i < WM_SET_COUNT; i++) { - bw_params->wm_table.entries[i].wm_inst = i; + for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) { + bw_params->wm_table.entries[entry_idx].wm_inst = entry_idx; - if (i >= bw_params->clk_table.num_entries) { - bw_params->wm_table.entries[i].valid = false; + if (entry_idx >= bw_params->clk_table.num_entries) { + bw_params->wm_table.entries[entry_idx].valid = false; continue; } - bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; - bw_params->wm_table.entries[i].valid = true; + bw_params->wm_table.entries[entry_idx].wm_type = WM_TYPE_PSTATE_CHG; + bw_params->wm_table.entries[entry_idx].valid = true; } } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c index 3a651c1a866d..b6f26475ac16 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c @@ -100,7 +100,7 @@ static bool should_disable_otg(struct pipe_ctx *pipe) static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable) { struct dc *dc = clk_mgr_base->ctx->dc; - int i; + uint8_t i; for (i = 0; i < dc->res_pool->pipe_count; ++i) { struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; @@ -203,7 +203,7 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { - int requested_dispclk_khz = new_clocks->dispclk_khz; + uint32_t requested_dispclk_khz = new_clocks->dispclk_khz; dcn315_disable_otg_wa(clk_mgr_base, context, true); @@ -384,7 +384,7 @@ static struct dcn315_watermarks dummy_wms = { 0 }; static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn315_watermarks *table) { - int i, num_valid_sets; + uint8_t i, num_valid_sets; num_valid_sets = 0; @@ -393,8 +393,11 @@ static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struc if (!bw_params->wm_table.entries[i].valid) continue; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; @@ -405,10 +408,10 @@ static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struc else { /* add 1 to make it non-overlapping with next lvl */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = - bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = - bw_params->clk_table.entries[i].dcfclk_mhz; + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -486,6 +489,7 @@ static void dcn315_clk_mgr_helper_populate_bw_params( const DpmClocks_315_t *clock_table) { int i; + unsigned int entry_idx; struct clk_bw_params *bw_params = clk_mgr->base.bw_params; uint32_t max_pstate = clock_table->NumDfPstatesEnabled - 1; struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1]; @@ -541,26 +545,26 @@ static void dcn315_clk_mgr_helper_populate_bw_params( /* Set any 0 clocks to max default setting. Not an issue for * power since we aren't doing switching in such case anyway */ - for (i = 0; i < bw_params->clk_table.num_entries; i++) { - if (!bw_params->clk_table.entries[i].fclk_mhz) { - bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz; - bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz; - bw_params->clk_table.entries[i].voltage = def_max.voltage; + for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++) { + if (!bw_params->clk_table.entries[entry_idx].fclk_mhz) { + bw_params->clk_table.entries[entry_idx].fclk_mhz = def_max.fclk_mhz; + bw_params->clk_table.entries[entry_idx].memclk_mhz = def_max.memclk_mhz; + bw_params->clk_table.entries[entry_idx].voltage = def_max.voltage; } - if (!bw_params->clk_table.entries[i].dcfclk_mhz) - bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; - if (!bw_params->clk_table.entries[i].socclk_mhz) - bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz; - if (!bw_params->clk_table.entries[i].dispclk_mhz) - bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz; - if (!bw_params->clk_table.entries[i].dppclk_mhz) - bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz; - if (!bw_params->clk_table.entries[i].phyclk_mhz) - bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz; - if (!bw_params->clk_table.entries[i].phyclk_d18_mhz) - bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz; - if (!bw_params->clk_table.entries[i].dtbclk_mhz) - bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dcfclk_mhz) + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = def_max.dcfclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].socclk_mhz) + bw_params->clk_table.entries[entry_idx].socclk_mhz = def_max.socclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dispclk_mhz) + bw_params->clk_table.entries[entry_idx].dispclk_mhz = def_max.dispclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dppclk_mhz) + bw_params->clk_table.entries[entry_idx].dppclk_mhz = def_max.dppclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].phyclk_mhz) + bw_params->clk_table.entries[entry_idx].phyclk_mhz = def_max.phyclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz) + bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz = def_max.phyclk_d18_mhz; + if (!bw_params->clk_table.entries[entry_idx].dtbclk_mhz) + bw_params->clk_table.entries[entry_idx].dtbclk_mhz = def_max.dtbclk_mhz; } /* Make sure all highest default clocks are included*/ @@ -572,16 +576,16 @@ static void dcn315_clk_mgr_helper_populate_bw_params( bw_params->num_channels = bios_info->ma_channel_number; bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; - for (i = 0; i < WM_SET_COUNT; i++) { - bw_params->wm_table.entries[i].wm_inst = i; + for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) { + bw_params->wm_table.entries[entry_idx].wm_inst = entry_idx; - if (i >= bw_params->clk_table.num_entries) { - bw_params->wm_table.entries[i].valid = false; + if (entry_idx >= bw_params->clk_table.num_entries) { + bw_params->wm_table.entries[entry_idx].valid = false; continue; } - bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; - bw_params->wm_table.entries[i].valid = true; + bw_params->wm_table.entries[entry_idx].wm_type = WM_TYPE_PSTATE_CHG; + bw_params->wm_table.entries[entry_idx].valid = true; } } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c index e9d492d8c8d4..72a38f7a761c 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c @@ -103,7 +103,7 @@ static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state bool safe_to_lower, bool disable) { struct dc *dc = clk_mgr_base->ctx->dc; - int i; + uint8_t i; for (i = 0; i < dc->res_pool->pipe_count; ++i) { struct pipe_ctx *pipe = safe_to_lower @@ -211,7 +211,7 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base, if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { - int requested_dispclk_khz = new_clocks->dispclk_khz; + uint32_t requested_dispclk_khz = new_clocks->dispclk_khz; dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); @@ -350,7 +350,7 @@ static struct dcn316_watermarks dummy_wms = { 0 }; static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table) { - int i, num_valid_sets; + uint8_t i, num_valid_sets; num_valid_sets = 0; @@ -359,8 +359,11 @@ static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struc if (!bw_params->wm_table.entries[i].valid) continue; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; @@ -371,10 +374,10 @@ static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struc else { /* add 1 to make it non-overlapping with next lvl */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = - bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = - bw_params->clk_table.entries[i].dcfclk_mhz; + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -449,7 +452,7 @@ static void dcn316_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) { uint32_t max = 0; - int i; + uint32_t i; for (i = 0; i < num_clocks; ++i) { if (clocks[i] > max) @@ -465,8 +468,8 @@ static unsigned int find_clk_for_voltage( unsigned int voltage) { int i; - int max_voltage = 0; - int clock = 0; + unsigned int max_voltage = 0; + unsigned int clock = 0; for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) { if (clock_table->SocVoltage[i] == voltage) { @@ -488,6 +491,7 @@ static void dcn316_clk_mgr_helper_populate_bw_params( const DpmClocks_316_t *clock_table) { int i, j; + unsigned int entry_idx; struct clk_bw_params *bw_params = clk_mgr->base.bw_params; uint32_t max_dispclk = 0, max_dppclk = 0; @@ -522,46 +526,46 @@ static void dcn316_clk_mgr_helper_populate_bw_params( ASSERT(0); } - for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { + for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++, j--) { int temp; - bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk; - bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; - bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage; + bw_params->clk_table.entries[entry_idx].fclk_mhz = clock_table->DfPstateTable[j].FClk; + bw_params->clk_table.entries[entry_idx].memclk_mhz = clock_table->DfPstateTable[j].MemClk; + bw_params->clk_table.entries[entry_idx].voltage = clock_table->DfPstateTable[j].Voltage; switch (clock_table->DfPstateTable[j].WckRatio) { case WCK_RATIO_1_2: - bw_params->clk_table.entries[i].wck_ratio = 2; + bw_params->clk_table.entries[entry_idx].wck_ratio = 2; break; case WCK_RATIO_1_4: - bw_params->clk_table.entries[i].wck_ratio = 4; + bw_params->clk_table.entries[entry_idx].wck_ratio = 4; break; default: - bw_params->clk_table.entries[i].wck_ratio = 1; + bw_params->clk_table.entries[entry_idx].wck_ratio = 1; } temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage); if (temp) - bw_params->clk_table.entries[i].dcfclk_mhz = temp; + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = temp; temp = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage); if (temp) - bw_params->clk_table.entries[i].socclk_mhz = temp; - bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; - bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; + bw_params->clk_table.entries[entry_idx].socclk_mhz = temp; + bw_params->clk_table.entries[entry_idx].dispclk_mhz = max_dispclk; + bw_params->clk_table.entries[entry_idx].dppclk_mhz = max_dppclk; } bw_params->vram_type = bios_info->memory_type; bw_params->num_channels = bios_info->ma_channel_number; bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; - for (i = 0; i < WM_SET_COUNT; i++) { - bw_params->wm_table.entries[i].wm_inst = i; + for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) { + bw_params->wm_table.entries[entry_idx].wm_inst = entry_idx; - if (i >= bw_params->clk_table.num_entries) { - bw_params->wm_table.entries[i].valid = false; + if (entry_idx >= bw_params->clk_table.num_entries) { + bw_params->wm_table.entries[entry_idx].valid = false; continue; } - bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; - bw_params->wm_table.entries[i].valid = true; + bw_params->wm_table.entries[entry_idx].wm_type = WM_TYPE_PSTATE_CHG; + bw_params->wm_table.entries[entry_idx].valid = true; } } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index fda6cade30a8..478527a0bca2 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -132,7 +132,7 @@ static const struct clk_mgr_mask clk_mgr_mask_dcn321 = { static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0, unsigned int *num_levels) { - unsigned int i; + uint8_t i; char *entry_i = (char *)entry_0; uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF); @@ -236,9 +236,9 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) { for (i = 0; i < num_levels; i++) if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz - < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz)) + < (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz)) clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz - = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz); + = (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz); } for (i = 0; i < num_levels; i++) if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950) @@ -247,9 +247,9 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) { for (i = 0; i < num_levels; i++) if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz - < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz)) + < (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz)) clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz - = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz); + = (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz); } for (i = 0; i < num_levels; i++) @@ -269,7 +269,7 @@ static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, { struct dccg *dccg = clk_mgr->dccg; uint32_t tg_mask = 0; - int i; + uint32_t i; for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; @@ -314,7 +314,7 @@ static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, s void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower) { - int i; + uint32_t i; clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { @@ -409,7 +409,7 @@ static void dcn32_update_clocks_update_dentist( * floored in Mhz to describe the intended clock. */ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, - khz_to_mhz_floor(temp_dispclk_khz)); + (uint16_t)khz_to_mhz_floor(temp_dispclk_khz)); if (dc->debug.override_dispclk_programming) { REG_GET(DENTIST_DISPCLK_CNTL, @@ -456,7 +456,7 @@ static void dcn32_update_clocks_update_dentist( * floored in Mhz to describe the intended clock. */ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, - khz_to_mhz_floor(clk_mgr->base.clks.dispclk_khz)); + (uint16_t)khz_to_mhz_floor(clk_mgr->base.clks.dispclk_khz)); if (dc->debug.override_dispclk_programming) { REG_GET(DENTIST_DISPCLK_CNTL, @@ -673,14 +673,17 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, } } - if (dc->debug.force_min_dcfclk_mhz > 0) - new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? - new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + if (dc->debug.force_min_dcfclk_mhz > 0) { + int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000; + + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > force_min_dcfclk_khz) ? + new_clocks->dcfclk_khz : force_min_dcfclk_khz; + } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc->work_arounds.clock_update_disable_mask.dcfclk) { clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; - dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) && @@ -715,13 +718,13 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, * frequency. */ if (dc->debug.disable_dc_mode_overwrite) { - dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz); - dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz); + dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz); } else dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - dc->clk_mgr->bw_params->dc_mode_softmax_memclk); + (uint16_t)dc->clk_mgr->bw_params->dc_mode_softmax_memclk); } else { - dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz); } } } @@ -755,9 +758,10 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, !dc->work_arounds.clock_update_disable_mask.uclk) { if (dc->clk_mgr->dc_mode_softmax_enabled && dc->debug.disable_dc_mode_overwrite) dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, - max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz))); + (uint16_t)max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, + khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz))); - dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); } if (clk_mgr_base->clks.num_ways != new_clocks->num_ways && @@ -783,7 +787,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, * floored in Mhz to describe the intended clock. */ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, - khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz)); + (uint16_t)khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz)); update_dppclk = true; } @@ -803,7 +807,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) { /* DCCG requires KHz precision for DTBCLK */ clk_mgr_base->clks.ref_dtbclk_khz = - dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz)); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz)); dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz); } @@ -822,7 +826,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, * floored in Mhz to describe the intended clock. */ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, - khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz)); + (uint16_t)khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz)); } else { /* if clock is being raised, increase refclk before lowering DTO */ if (update_dppclk || update_dispclk) @@ -968,7 +972,7 @@ static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr) } static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base) { - unsigned int i; + uint8_t i; struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table; @@ -1002,13 +1006,13 @@ static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current if (current_mode) { if (clk_mgr_base->clks.p_state_change_support) dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); + (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); else dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->max_memclk_mhz); + (uint16_t)clk_mgr_base->bw_params->max_memclk_mhz); } else { dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); + (uint16_t)clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); } } @@ -1020,7 +1024,7 @@ static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base) if (!clk_mgr->smu_present) return; - dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->max_memclk_mhz); + dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)clk_mgr_base->bw_params->max_memclk_mhz); } /* Get current memclk states, update bounding box */ @@ -1052,7 +1056,7 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) clk_mgr_base->bw_params->max_memclk_mhz = clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz; - clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1; + clk_mgr_base->bw_params->clk_table.num_entries = (uint8_t)(num_levels ? num_levels : 1); if (clk_mgr->dpm_present && !num_levels) clk_mgr->dpm_present = false; @@ -1109,7 +1113,7 @@ static void dcn32_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memc if (!clk_mgr->smu_present) return; - dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); + dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz); } static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) @@ -1119,7 +1123,7 @@ static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memc if (!clk_mgr->smu_present) return; - dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz); } static struct clk_mgr_funcs dcn32_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 2798088842f4..6c6848e375e1 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -190,7 +190,7 @@ void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context bool safe_to_lower, bool disable) { struct dc *dc = clk_mgr_base->ctx->dc; - int i; + uint8_t i; if (dc->ctx->dce_environment == DCE_ENV_DIAG) return; @@ -257,7 +257,7 @@ static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, { struct dccg *dccg = clk_mgr->dccg; uint32_t tg_mask = 0; - int i; + uint32_t i; for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; @@ -280,7 +280,7 @@ static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower) { - int i; + uint32_t i; bool dppclk_active[MAX_PIPES] = {0}; @@ -332,7 +332,7 @@ static uint8_t get_lowest_dpia_index(const struct dc_link *link) continue; if (idx > dc_struct->links[i]->link_index) - idx = dc_struct->links[i]->link_index; + idx = (uint8_t)dc_struct->links[i]->link_index; } return idx; @@ -450,9 +450,12 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; } } - if (dc->debug.force_min_dcfclk_mhz > 0) - new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? - new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + if (dc->debug.force_min_dcfclk_mhz > 0) { + int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000; + + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > force_min_dcfclk_khz) ? + new_clocks->dcfclk_khz : force_min_dcfclk_khz; + } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; @@ -478,7 +481,7 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { - int requested_dispclk_khz = new_clocks->dispclk_khz; + uint32_t requested_dispclk_khz = new_clocks->dispclk_khz; dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); @@ -863,7 +866,7 @@ static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr) static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table) { - int i, num_valid_sets; + uint8_t i, num_valid_sets; num_valid_sets = 0; @@ -872,8 +875,10 @@ static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct if (!bw_params->wm_table.entries[i].valid) continue; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; @@ -884,10 +889,10 @@ static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct else { /* add 1 to make it non-overlapping with next lvl */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = - bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = - bw_params->clk_table.entries[i].dcfclk_mhz; + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -978,7 +983,7 @@ static void dcn351_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) { uint32_t max = 0; - int i; + uint32_t i; for (i = 0; i < num_clocks; ++i) { if (clocks[i] > max) @@ -1025,28 +1030,29 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0; uint32_t num_memps, num_fclk, num_dcfclk; int i; + unsigned int entry_idx; /* Determine min/max p-state values. */ num_memps = (clock_table->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) ? NUM_MEM_PSTATE_LEVELS : clock_table->NumMemPstatesEnabled; - for (i = 0; i < num_memps; i++) { - uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]); + for (entry_idx = 0; entry_idx < num_memps; entry_idx++) { + uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[entry_idx]); if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts > max_dram_speed_mts) { max_dram_speed_mts = dram_speed_mts; - max_pstate = i; + max_pstate = entry_idx; } } min_dram_speed_mts = max_dram_speed_mts; min_pstate = max_pstate; - for (i = 0; i < num_memps; i++) { - uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]); + for (entry_idx = 0; entry_idx < num_memps; entry_idx++) { + uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[entry_idx]); if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts < min_dram_speed_mts) { min_dram_speed_mts = dram_speed_mts; - min_pstate = i; + min_pstate = entry_idx; } } @@ -1076,31 +1082,32 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk num_dcfclk = (clock_table->NumDcfClkLevelsEnabled > NUM_DCFCLK_DPM_LEVELS) ? NUM_DCFCLK_DPM_LEVELS : clock_table->NumDcfClkLevelsEnabled; - for (i = 0; i < num_dcfclk; i++) { + for (entry_idx = 0; entry_idx < num_dcfclk; entry_idx++) { int j; /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */ for (j = bw_params->clk_table.num_entries - 1; j > 0; j--) - if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) + if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[entry_idx]) break; - bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; - bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; - bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; + bw_params->clk_table.entries[entry_idx].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; + bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; + bw_params->clk_table.entries[entry_idx].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; /* Now update clocks we do read */ - bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk; - bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[min_pstate].Voltage; - bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i]; - bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i]; - bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; - bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; - bw_params->clk_table.entries[i].wck_ratio = + bw_params->clk_table.entries[entry_idx].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk; + bw_params->clk_table.entries[entry_idx].voltage = clock_table->MemPstateTable[min_pstate].Voltage; + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = clock_table->DcfClocks[entry_idx]; + bw_params->clk_table.entries[entry_idx].socclk_mhz = clock_table->SocClocks[entry_idx]; + bw_params->clk_table.entries[entry_idx].dispclk_mhz = max_dispclk; + bw_params->clk_table.entries[entry_idx].dppclk_mhz = max_dppclk; + bw_params->clk_table.entries[entry_idx].wck_ratio = convert_wck_ratio(clock_table->MemPstateTable[min_pstate].WckRatio); /* Dcfclk and Fclk are tied, but at a different ratio */ - bw_params->clk_table.entries[i].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[i]); + bw_params->clk_table.entries[entry_idx].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[entry_idx]); } + i = (int)entry_idx; /* Make sure to include at least one entry at highest pstate */ if (max_pstate != min_pstate || i == 0) { @@ -1146,44 +1153,44 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk * Set any 0 clocks to max default setting. Not an issue for * power since we aren't doing switching in such case anyway */ - for (i = 0; i < bw_params->clk_table.num_entries; i++) { - if (!bw_params->clk_table.entries[i].fclk_mhz) { - bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz; - bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz; - bw_params->clk_table.entries[i].voltage = def_max.voltage; + for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++) { + if (!bw_params->clk_table.entries[entry_idx].fclk_mhz) { + bw_params->clk_table.entries[entry_idx].fclk_mhz = def_max.fclk_mhz; + bw_params->clk_table.entries[entry_idx].memclk_mhz = def_max.memclk_mhz; + bw_params->clk_table.entries[entry_idx].voltage = def_max.voltage; } - if (!bw_params->clk_table.entries[i].dcfclk_mhz) - bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; - if (!bw_params->clk_table.entries[i].socclk_mhz) - bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz; - if (!bw_params->clk_table.entries[i].dispclk_mhz) - bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz; - if (!bw_params->clk_table.entries[i].dppclk_mhz) - bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz; - if (!bw_params->clk_table.entries[i].fclk_mhz) - bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz; - if (!bw_params->clk_table.entries[i].phyclk_mhz) - bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz; - if (!bw_params->clk_table.entries[i].phyclk_d18_mhz) - bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz; - if (!bw_params->clk_table.entries[i].dtbclk_mhz) - bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dcfclk_mhz) + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = def_max.dcfclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].socclk_mhz) + bw_params->clk_table.entries[entry_idx].socclk_mhz = def_max.socclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dispclk_mhz) + bw_params->clk_table.entries[entry_idx].dispclk_mhz = def_max.dispclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dppclk_mhz) + bw_params->clk_table.entries[entry_idx].dppclk_mhz = def_max.dppclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].fclk_mhz) + bw_params->clk_table.entries[entry_idx].fclk_mhz = def_max.fclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].phyclk_mhz) + bw_params->clk_table.entries[entry_idx].phyclk_mhz = def_max.phyclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz) + bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz = def_max.phyclk_d18_mhz; + if (!bw_params->clk_table.entries[entry_idx].dtbclk_mhz) + bw_params->clk_table.entries[entry_idx].dtbclk_mhz = def_max.dtbclk_mhz; } ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); bw_params->vram_type = bios_info->memory_type; bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4; - for (i = 0; i < WM_SET_COUNT; i++) { - bw_params->wm_table.entries[i].wm_inst = i; + for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) { + bw_params->wm_table.entries[entry_idx].wm_inst = entry_idx; - if (i >= bw_params->clk_table.num_entries) { - bw_params->wm_table.entries[i].valid = false; + if (entry_idx >= bw_params->clk_table.num_entries) { + bw_params->wm_table.entries[entry_idx].valid = false; continue; } - bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; - bw_params->wm_table.entries[i].valid = true; + bw_params->wm_table.entries[entry_idx].wm_type = WM_TYPE_PSTATE_CHG; + bw_params->wm_table.entries[entry_idx].valid = true; } } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c index 82c1a55a2271..6ad38cb28d23 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c @@ -174,7 +174,7 @@ static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e c /* if the initial message failed, num_levels will be 0 */ for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) { - *((unsigned int *)entry_i) = (dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF); + *((unsigned int *)entry_i) = (dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, (uint8_t)i) & 0xFFFF); entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); } } @@ -182,15 +182,15 @@ static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e c static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr) { /* For min clocks use as reported by PM FW and report those as min */ - uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz; - uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; + unsigned int min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz; + unsigned int min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; /* Set A - Normal - default values */ clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true; clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; - clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; + clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = (uint16_t)min_dcfclk_mhz; clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; - clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; + clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = (uint16_t)min_uclk_mhz; clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; /* Set B - Unused on dcn4 */ @@ -201,9 +201,9 @@ static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr) if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) { clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true; clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE; - clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; + clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = (uint16_t)min_dcfclk_mhz; clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_dcfclk = 0xFFFF; - clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = min_uclk_mhz; + clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = (uint16_t)min_uclk_mhz; clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_uclk = 0xFFFF; } else { clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = false; @@ -291,17 +291,17 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base) if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) { for (i = 0; i < num_entries_per_clk->num_dispclk_levels; i++) if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz - < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz)) + < (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz)) clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz - = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz); + = (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz); } if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) { for (i = 0; i < num_entries_per_clk->num_dppclk_levels; i++) if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz - < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz)) + < (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz)) clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz - = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz); + = (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz); } /* Get UCLK, update bounding box */ @@ -558,7 +558,7 @@ static void dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr static void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower, int ref_dppclk_khz) { - int i; + uint32_t i; clk_mgr->dccg->ref_dppclk = ref_dppclk_khz; for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { @@ -604,10 +604,10 @@ static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mg * clock returned is less than requested, then we will ceil the * requested value to mhz and call it again. */ - int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_floor(requested_clk_khz)); + int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, (uint16_t)khz_to_mhz_floor(requested_clk_khz)); if (actual_clk_khz < requested_clk_khz) - actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_ceil(requested_clk_khz)); + actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, (uint16_t)khz_to_mhz_ceil(requested_clk_khz)); return actual_clk_khz; } @@ -841,15 +841,18 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence( } /* UPDATE DCFCLK */ - if (dc->debug.force_min_dcfclk_mhz > 0) - new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? - new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + if (dc->debug.force_min_dcfclk_mhz > 0) { + int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000; + + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > force_min_dcfclk_khz) ? + new_clocks->dcfclk_khz : force_min_dcfclk_khz; + } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) { block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK; - block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz); + block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz); block_sequence[num_steps].params.update_hardmin_params.response = NULL; block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK; num_steps++; @@ -860,7 +863,7 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence( if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) { - block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz); + block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz); block_sequence[num_steps].func = CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK; num_steps++; } @@ -984,24 +987,24 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence( /* When idle DPM is enabled, need to send active and idle hardmins separately */ /* CLK_MGR401_UPDATE_ACTIVE_HARDMINS */ if ((update_active_uclk || update_active_fclk) && is_idle_dpm_enabled) { - block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = active_uclk_mhz; - block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = active_fclk_mhz; + block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)active_uclk_mhz; + block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)active_fclk_mhz; block_sequence[num_steps].func = CLK_MGR401_UPDATE_ACTIVE_HARDMINS; num_steps++; } /* CLK_MGR401_UPDATE_IDLE_HARDMINS */ if ((update_idle_uclk || update_idle_fclk) && is_idle_dpm_enabled) { - block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = idle_uclk_mhz; - block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = idle_fclk_mhz; + block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)idle_uclk_mhz; + block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)idle_fclk_mhz; block_sequence[num_steps].func = CLK_MGR401_UPDATE_IDLE_HARDMINS; num_steps++; } /* CLK_MGR401_UPDATE_SUBVP_HARDMINS */ if ((update_subvp_prefetch_dramclk || update_subvp_prefetch_fclk) && is_df_throttle_opt_enabled) { - block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = subvp_prefetch_dramclk_mhz; - block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = subvp_prefetch_fclk_mhz; + block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)subvp_prefetch_dramclk_mhz; + block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)subvp_prefetch_fclk_mhz; block_sequence[num_steps].func = CLK_MGR401_UPDATE_SUBVP_HARDMINS; num_steps++; } @@ -1010,7 +1013,7 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence( if (update_active_uclk || update_idle_uclk) { if (!is_idle_dpm_enabled) { block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_UCLK; - block_sequence[num_steps].params.update_hardmin_params.freq_mhz = active_uclk_mhz; + block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)active_uclk_mhz; block_sequence[num_steps].params.update_hardmin_params.response = NULL; block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK; num_steps++; @@ -1123,7 +1126,7 @@ static unsigned int dcn401_build_update_display_clocks_sequence( dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) { /* DCCG requires KHz precision for DTBCLK */ block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DTBCLK; - block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz); + block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz); block_sequence[num_steps].params.update_hardmin_params.response = &clk_mgr_base->clks.ref_dtbclk_khz; block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK; num_steps++; @@ -1318,7 +1321,7 @@ static void dcn401_notify_wm_ranges(struct clk_mgr *clk_mgr_base) /* collect valid ranges, place in pmfw table */ for (i = 0; i < WM_SET_COUNT; i++) if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { - table->Watermarks.WatermarkRow[i].WmSetting = i; + table->Watermarks.WatermarkRow[i].WmSetting = (uint8_t)i; table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type; } dcn401_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index 6a97ce69a562..41729426d08c 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -167,7 +167,7 @@ void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, void dcn42_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower) { - int i; + uint32_t i; bool dppclk_active[MAX_PIPES] = {0}; @@ -282,9 +282,12 @@ void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; } } - if (dc->debug.force_min_dcfclk_mhz > 0) - new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? - new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + if (dc->debug.force_min_dcfclk_mhz > 0) { + int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000; + + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > force_min_dcfclk_khz) ? + new_clocks->dcfclk_khz : force_min_dcfclk_khz; + } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; @@ -298,8 +301,9 @@ void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; /* Clamp the requested clock to PMFW based on DCN limit. */ - if (dc->debug.min_deep_sleep_dcfclk_khz > 0 && clk_mgr_base->clks.dcfclk_deep_sleep_khz < dc->debug.min_deep_sleep_dcfclk_khz) - clk_mgr_base->clks.dcfclk_deep_sleep_khz = dc->debug.min_deep_sleep_dcfclk_khz; + if (dc->debug.min_deep_sleep_dcfclk_khz > 0 && + clk_mgr_base->clks.dcfclk_deep_sleep_khz < (int)dc->debug.min_deep_sleep_dcfclk_khz) + clk_mgr_base->clks.dcfclk_deep_sleep_khz = (int)dc->debug.min_deep_sleep_dcfclk_khz; dcn42_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); } @@ -315,13 +319,13 @@ void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && (new_clocks->dispclk_khz > 0 || (safe_to_lower && has_active_display == false))) { - int requested_dispclk_khz = new_clocks->dispclk_khz; + uint32_t requested_dispclk_khz = new_clocks->dispclk_khz; dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); /* Clamp the requested clock to PMFW based on their limit. */ - if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz) - requested_dispclk_khz = dc->debug.min_disp_clk_khz; + if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < (uint32_t)dc->debug.min_disp_clk_khz) + requested_dispclk_khz = (uint32_t)dc->debug.min_disp_clk_khz; dcn42_smu_set_dispclk(clk_mgr, requested_dispclk_khz); clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; @@ -634,7 +638,7 @@ static void dcn42_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr) void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_watermarks *table) { - int i, num_valid_sets; + uint8_t i, num_valid_sets; num_valid_sets = 0; @@ -643,8 +647,10 @@ void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_ if (!bw_params->wm_table.entries[i].valid) continue; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; @@ -655,10 +661,10 @@ void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_ else { /* add 1 to make it non-overlapping with next lvl */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = - bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = - bw_params->clk_table.entries[i].dcfclk_mhz; + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -690,7 +696,7 @@ void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_ void dcn42_notify_wm_ranges(struct clk_mgr *clk_mgr_base) { - int i = 0; + unsigned int i = 0; struct dcn42_watermarks *table = NULL; struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); struct clk_mgr_dcn42 *clk_mgr_dcn42 = TO_CLK_MGR_DCN42(clk_mgr); @@ -734,9 +740,12 @@ void dcn42_notify_wm_ranges(struct clk_mgr *clk_mgr_base) clk_mgr_dcn42->smu_wm_set.mc_address.low_part); dcn42_smu_transfer_wm_table_dram_2_smu(clk_mgr); - if (clk_mgr_dcn42->smu_wm_set.wm_set && clk_mgr_dcn42->smu_wm_set.mc_address.quad_part != 0) + if (clk_mgr_dcn42->smu_wm_set.wm_set && clk_mgr_dcn42->smu_wm_set.mc_address.quad_part != 0) { dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART, clk_mgr_dcn42->smu_wm_set.wm_set); + clk_mgr_dcn42->smu_wm_set.wm_set = NULL; + clk_mgr_dcn42->smu_wm_set.mc_address.quad_part = 0; + } } @@ -1015,7 +1024,7 @@ static struct clk_mgr_funcs dcn42_funcs = { .init_clocks = dcn42_init_clocks, .enable_pme_wa = dcn42_enable_pme_wa, .are_clock_states_equal = dcn42_are_clock_states_equal, - .notify_wm_ranges = dcn42_notify_wm_ranges, + .notify_wm_ranges = NULL, .set_low_power_state = dcn42_set_low_power_state, .exit_low_power_state = dcn42_exit_low_power_state, .get_max_clock_khz = dcn42_get_max_clock_khz, @@ -1099,7 +1108,10 @@ void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) { struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42(clk_mgr_int); - if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) + if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) { dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_GART, clk_mgr->smu_wm_set.wm_set); + clk_mgr->smu_wm_set.wm_set = NULL; + clk_mgr->smu_wm_set.mc_address.quad_part = 0; + } } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c index c791bb1edb47..6d0012b7d6dc 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c @@ -428,4 +428,3 @@ void dcn42_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable) enable); smu_print("%s: smu_set_dtbclk = %d\n", __func__, enable ? 1 : 0); } - diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 419f894c87b0..92190ea451e8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -32,6 +32,7 @@ #include "core_types.h" #include "hw_sequencer.h" #include "dce/dce_hwseq.h" +#include "hw/dccg.h" #include "resource.h" #include "dc_state.h" @@ -61,6 +62,7 @@ #include "link_enc_cfg.h" #include "link_service.h" +#include "link/protocols/link_dp_capability.h" #include "dm_helpers.h" #include "mem_input.h" @@ -172,7 +174,7 @@ static void destroy_links(struct dc *dc) static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links) { - int i; + uint32_t i; uint32_t count = 0; for (i = 0; i < num_links; i++) { @@ -200,7 +202,7 @@ static bool create_links( struct dc *dc, uint32_t num_virtual_links) { - int i; + uint32_t i; int connectors_num; struct dc_bios *bios = dc->ctx->dc_bios; @@ -235,7 +237,7 @@ static bool create_links( * variants of the same card. */ for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) { - struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, i); + struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, (uint8_t)i); struct link_init_data link_init_params = {0}; struct dc_link *link; @@ -246,7 +248,7 @@ static bool create_links( link_init_params.ctx = dc->ctx; /* next BIOS object table connector */ - link_init_params.connector_index = i; + link_init_params.connector_index = (uint8_t)i; link_init_params.link_index = dc->link_count; link_init_params.dc = dc; link = dc->link_srv->create_link(&link_init_params); @@ -267,7 +269,7 @@ static bool create_links( struct dc_link *link; link_init_params.ctx = dc->ctx; - link_init_params.connector_index = i; + link_init_params.connector_index = (uint8_t)i; link_init_params.link_index = dc->link_count; link_init_params.dc = dc; link_init_params.is_dpia_link = true; @@ -341,7 +343,7 @@ static bool create_link_encoders(struct dc *dc) bool res = true; unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; - int i; + unsigned int i; /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG * link encoders and physical display endpoints and does not require @@ -381,7 +383,7 @@ static void destroy_link_encoders(struct dc *dc) { unsigned int num_usb4_dpia; unsigned int num_dig_link_enc; - int i; + unsigned int i; if (!dc->res_pool) return; @@ -659,12 +661,12 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, /* By default, capture the full frame */ param.windowa_x_start = 0; param.windowa_y_start = 0; - param.windowa_x_end = pipe->stream->timing.h_addressable; - param.windowa_y_end = pipe->stream->timing.v_addressable; + param.windowa_x_end = (uint16_t)pipe->stream->timing.h_addressable; + param.windowa_y_end = (uint16_t)pipe->stream->timing.v_addressable; param.windowb_x_start = 0; param.windowb_y_start = 0; - param.windowb_x_end = pipe->stream->timing.h_addressable; - param.windowb_y_end = pipe->stream->timing.v_addressable; + param.windowb_x_end = (uint16_t)pipe->stream->timing.h_addressable; + param.windowb_y_end = (uint16_t)pipe->stream->timing.v_addressable; param.crc_poly_mode = crc_poly_mode; if (crc_window) { @@ -1136,7 +1138,7 @@ static void disable_all_writeback_pipes_for_stream( { (void)dc; (void)context; - int i; + unsigned int i; for (i = 0; i < stream->num_wb_info; i++) stream->writeback_info[i].wb_enabled = false; @@ -1149,7 +1151,7 @@ static void apply_ctx_interdependent_lock(struct dc *dc, { (void)dc; (void)context; - int i; + unsigned int i; /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */ if (dc->hwss.interdependent_update_lock) @@ -1336,7 +1338,7 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, static void disable_dangling_plane(struct dc *dc, struct dc_state *context) { - int i, j; + unsigned int i, j; struct dc_state *dangling_context = dc_state_create_current_copy(dc); struct dc_state *current_ctx; struct pipe_ctx *pipe; @@ -1799,7 +1801,8 @@ bool dc_validate_boot_timing(const struct dc *dc, struct dc_crtc_timing hw_crtc_timing = {0}; struct dc_link *link = sink->link; - unsigned int i, enc_inst, tg_inst = 0; + unsigned int i, enc_inst; + unsigned int tg_inst = 0; /* Support seamless boot on EDP displays only */ if (sink->sink_signal != SIGNAL_TYPE_EDP) { @@ -1928,7 +1931,7 @@ bool dc_validate_boot_timing(const struct dc *dc, struct dcn_dsc_state dsc_state = {0}; /* Find DSC associated with this timing generator */ - if (tg_inst < dc->res_pool->res_cap->num_dsc) { + if (tg_inst < (unsigned int)dc->res_pool->res_cap->num_dsc) { dsc = dc->res_pool->dscs[tg_inst]; } @@ -2129,7 +2132,7 @@ void dc_trigger_sync(struct dc *dc, struct dc_state *context) static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; unsigned int stream_mask = 0; for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -2137,7 +2140,7 @@ static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context) stream_mask |= 1 << i; } - return stream_mask; + return (uint8_t)stream_mask; } void dc_z10_restore(const struct dc *dc) @@ -2203,7 +2206,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status result = DC_ERROR_UNEXPECTED; struct pipe_ctx *pipe; - int i, k, l; + unsigned int i, k, l; struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; struct dc_state *old_state; bool subvp_prev_use = false; @@ -2443,7 +2446,7 @@ static bool commit_minimal_transition_state(struct dc *dc, */ enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params) { - int i, j; + unsigned int i, j; struct dc_state *context; enum dc_status res = DC_OK; struct dc_validation_set set[MAX_STREAMS] = {0}; @@ -2482,8 +2485,8 @@ enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params set[i].stream = stream; if (status) { - set[i].plane_count = status->plane_count; - for (j = 0; j < status->plane_count; j++) + set[i].plane_count = (uint8_t)status->plane_count; + for (j = 0; j < (unsigned int)status->plane_count; j++) set[i].plane_states[j] = status->plane_states[j]; } } @@ -2541,7 +2544,7 @@ enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params for (i = 0; i < params->stream_count; i++) { for (j = 0; j < context->stream_count; j++) { if (params->streams[i]->stream_id == context->streams[j]->stream_id) - params->streams[i]->out.otg_offset = context->stream_status[j].primary_otg_inst; + params->streams[i]->out.otg_offset = (uint8_t)context->stream_status[j].primary_otg_inst; if (dc_is_embedded_signal(params->streams[i]->signal)) { struct dc_stream_status *status = dc_state_get_stream_status(context, params->streams[i]); @@ -2573,7 +2576,7 @@ bool dc_acquire_release_mpc_3dlut( struct dc_3dlut **lut, struct dc_transfer_func **shaper) { - int pipe_idx; + unsigned int pipe_idx; bool ret = false; bool found_pipe_idx = false; const struct resource_pool *pool = dc->res_pool; @@ -2645,7 +2648,7 @@ static void process_deferred_updates(struct dc *dc) void dc_post_update_surfaces_to_stream(struct dc *dc) { - int i; + unsigned int i; struct dc_state *context = dc->current_state; if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0) @@ -2669,7 +2672,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc) for (i = 0; i < dc->res_pool->pipe_count; i++) if (context->res_ctx.pipe_ctx[i].stream == NULL || context->res_ctx.pipe_ctx[i].plane_state == NULL) { - context->res_ctx.pipe_ctx[i].pipe_idx = i; + context->res_ctx.pipe_ctx[i].pipe_idx = (uint8_t)i; dc->hwss.disable_plane(dc, context, &context->res_ctx.pipe_ctx[i]); } @@ -2885,7 +2888,7 @@ static struct surface_update_descriptor get_scaling_info_update_type( /* Making dst rect smaller requires a bandwidth change */ update_flags->bits.bandwidth_change = 1; - if (u->scaling_info->src_rect.width > check_config->max_optimizable_video_width && + if (u->scaling_info->src_rect.width > (int)check_config->max_optimizable_video_width && (u->scaling_info->clip_rect.width > u->surface->clip_rect.width || u->scaling_info->clip_rect.height > u->surface->clip_rect.height)) /* Changing clip size of a large surface may result in MPC slice count change */ @@ -2946,6 +2949,11 @@ static struct surface_update_descriptor det_surface_update( elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } + if (u->cursor_csc_color_matrix) { + update_flags->bits.cursor_csc_color_matrix_change = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + if (u->coeff_reduction_factor) { update_flags->bits.coeff_reduction_change = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); @@ -2956,27 +2964,16 @@ static struct surface_update_descriptor det_surface_update( elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } - if (u->cm || (u->gamma && dce_use_lut(u->plane_info ? u->plane_info->format : u->surface->format))) { + if (u->blend_tf || (u->gamma && dce_use_lut(u->plane_info ? u->plane_info->format : u->surface->format))) { update_flags->bits.gamma_change = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } - if (u->cm && (u->cm->flags.bits.lut3d_enable || u->surface->cm.flags.bits.lut3d_enable)) { + if (u->lut3d_func || u->func_shaper) { update_flags->bits.lut_3d = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } - if (u->cm && u->cm->flags.bits.lut3d_dma_enable != u->surface->cm.flags.bits.lut3d_dma_enable && - u->cm->flags.bits.lut3d_enable && u->surface->cm.flags.bits.lut3d_enable) { - /* Toggling 3DLUT loading between DMA and Host is illegal */ - BREAK_TO_DEBUGGER(); - } - - if (u->cm && u->cm->flags.bits.lut3d_enable && !u->cm->flags.bits.lut3d_dma_enable) { - /* Host loading 3DLUT requires full update but only stream lock */ - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM); - } - if (u->hdr_mult.value) if (u->hdr_mult.value != u->surface->hdr_mult.value) { // TODO: Should be fast? @@ -2995,12 +2992,27 @@ static struct surface_update_descriptor det_surface_update( update_flags->bits.cm_hist_change = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } + if (u->cm2_params) { + if (u->cm2_params->component_settings.shaper_3dlut_setting != u->surface->mcm_shaper_3dlut_setting + || u->cm2_params->component_settings.lut1d_enable != u->surface->mcm_lut1d_enable + || u->cm2_params->cm2_luts.lut3d_data.lut3d_src != u->surface->mcm_luts.lut3d_data.lut3d_src) { + update_flags->bits.mcm_transfer_function_enable_change = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + } + } + + if (update_flags->bits.lut_3d && + u->surface->mcm_luts.lut3d_data.lut3d_src != DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + } + if (check_config->enable_legacy_fast_update && (update_flags->bits.gamma_change || update_flags->bits.gamut_remap_change || update_flags->bits.input_csc_change || update_flags->bits.cm_hist_change || - update_flags->bits.coeff_reduction_change)) { + update_flags->bits.coeff_reduction_change || + update_flags->bits.cursor_csc_color_matrix_change)) { elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } return overall_type; @@ -3073,7 +3085,7 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL | LOCK_DESCRIPTOR_LINK); } - if (stream_update->gamut_remap) + if (check_config->enable_legacy_fast_update && stream_update->gamut_remap) su_flags->bits.gamut_remap = 1; if (stream_update->wb_update) @@ -3090,8 +3102,10 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( stream_update->vrr_active_variable || stream_update->vrr_active_fixed)) su_flags->bits.fams_changed = 1; - if (stream_update->scaler_sharpener_update) + if (stream_update->scaler_sharpener_update) { su_flags->bits.scaler_sharpener = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM); + } if (stream_update->sharpening_required) su_flags->bits.sharpening_required = 1; @@ -3104,6 +3118,29 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); // Non-global cases + + if (stream_update->gamut_remap) { + su_flags->bits.gamut_remap = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + + if ((stream_update->hdr_static_metadata && !stream_update->stream->use_dynamic_meta) || + stream_update->vrr_infopacket || + stream_update->vsc_infopacket || + stream_update->vsp_infopacket || + stream_update->hfvsif_infopacket || + stream_update->adaptive_sync_infopacket || + stream_update->vtem_infopacket || + stream_update->avi_infopacket) { + su_flags->bits.info_frame = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->hdr_static_metadata && stream_update->stream->use_dynamic_meta) { + su_flags->bits.dmdata = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + if (stream_update->output_csc_transform) { su_flags->bits.out_csc = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); @@ -3113,6 +3150,36 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( su_flags->bits.out_tf = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } + + if (stream_update->periodic_interrupt) { + su_flags->bits.periodic_interrupt = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->dither_option) { + su_flags->bits.dither = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->cursor_attributes) { + su_flags->bits.cursor_attr = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->cursor_position) { + su_flags->bits.cursor_pos = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->func_shaper) { + su_flags->bits.func_shaper = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->lut3d_func) { + su_flags->bits.lut3d_func = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM); + } } for (int i = 0 ; i < surface_count; i++) { @@ -3170,10 +3237,10 @@ static void copy_surface_update_to_plane( surface->flip_immediate = srf_update->flip_addr->flip_immediate; surface->time.time_elapsed_in_us[surface->time.index] = - srf_update->flip_addr->flip_timestamp_in_us - - surface->time.prev_update_time_in_us; + (unsigned int)(srf_update->flip_addr->flip_timestamp_in_us - + surface->time.prev_update_time_in_us); surface->time.prev_update_time_in_us = - srf_update->flip_addr->flip_timestamp_in_us; + (unsigned int)srf_update->flip_addr->flip_timestamp_in_us; surface->time.index++; if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX) surface->time.index = 0; @@ -3250,12 +3317,24 @@ static void copy_surface_update_to_plane( sizeof(struct dc_transfer_func_distributed_points)); } - /* Shaper, 3DLUT, 1DLUT */ - if (srf_update->cm) { - memcpy(&surface->cm, srf_update->cm, - sizeof(surface->cm)); + if (srf_update->cm2_params) { + surface->mcm_shaper_3dlut_setting = srf_update->cm2_params->component_settings.shaper_3dlut_setting; + surface->mcm_lut1d_enable = srf_update->cm2_params->component_settings.lut1d_enable; + surface->mcm_luts = srf_update->cm2_params->cm2_luts; } + if (srf_update->func_shaper) { + memcpy(&surface->in_shaper_func, srf_update->func_shaper, + sizeof(surface->in_shaper_func)); + + if (surface->mcm_shaper_3dlut_setting >= DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER) + surface->mcm_luts.shaper = &surface->in_shaper_func; + } + + if (srf_update->lut3d_func) + memcpy(&surface->lut3d_func, srf_update->lut3d_func, + sizeof(surface->lut3d_func)); + if (srf_update->hdr_mult.value) surface->hdr_mult = srf_update->hdr_mult; @@ -3264,6 +3343,17 @@ static void copy_surface_update_to_plane( surface->sdr_white_level_nits = srf_update->sdr_white_level_nits; + if (srf_update->blend_tf) { + memcpy(&surface->blend_tf, srf_update->blend_tf, + sizeof(surface->blend_tf)); + + if (surface->mcm_lut1d_enable) + surface->mcm_luts.lut1d_func = &surface->blend_tf; + } + + if (srf_update->cm2_params || srf_update->blend_tf) + surface->lut_bank_a = !surface->lut_bank_a; + if (srf_update->input_csc_color_matrix) surface->input_csc_color_matrix = *srf_update->input_csc_color_matrix; @@ -3387,7 +3477,7 @@ static void copy_stream_update_to_stream(struct dc *dc, stream->test_pattern = *update->pending_test_pattern; /* update current stream with writeback info */ if (update->wb_update) { - int i; + unsigned int i; stream->num_wb_info = update->wb_update->num_wb_info; ASSERT(stream->num_wb_info <= MAX_DWB_PIPES); @@ -3582,7 +3672,8 @@ static bool update_planes_and_stream_state(struct dc *dc, struct dc_state **new_context) { struct dc_state *context; - int i, j; + int i; + unsigned int j; enum surface_update_type update_type; const struct dc_stream_status *stream_status; struct dc_context *dc_ctx = dc->ctx; @@ -3743,14 +3834,433 @@ static bool update_planes_and_stream_state(struct dc *dc, } +static void program_cursor_attributes_sequence( + struct dc *dc, + struct dc_stream_state *stream, + struct dc_state *context, + struct block_sequence_state *seq_state) +{ + int k; + struct pipe_ctx *pipe_to_program = NULL; + bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); + + for (k = 0; k < dc->res_pool->pipe_count; k++) { + struct pipe_ctx *tmp_pipe = &context->res_ctx.pipe_ctx[k]; + + if (tmp_pipe->stream != stream) + continue; + + if (!pipe_to_program) { + pipe_to_program = tmp_pipe; + + if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) { + hwss_add_begin_cursor_offload_update(seq_state, dc, tmp_pipe); + } else { + hwss_add_cursor_lock(seq_state, dc, pipe_to_program, true); + if (pipe_to_program->next_odm_pipe) + hwss_add_cursor_lock(seq_state, dc, pipe_to_program->next_odm_pipe, true); + } + } + + hwss_add_set_cursor_attribute(seq_state, dc, tmp_pipe); + if (dc->ctx->dmub_srv) + hwss_add_send_update_cursor_info_to_dmu(seq_state, tmp_pipe, k); + if (dc->hwss.set_cursor_sdr_white_level) + hwss_add_set_cursor_sdr_white_level(seq_state, dc, tmp_pipe); + if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) + hwss_add_update_cursor_offload_pipe(seq_state, dc, tmp_pipe); + } + + if (pipe_to_program) { + if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) { + hwss_add_commit_cursor_offload_update(seq_state, dc, pipe_to_program); + } else { + hwss_add_cursor_lock(seq_state, dc, pipe_to_program, false); + if (pipe_to_program->next_odm_pipe) + hwss_add_cursor_lock(seq_state, dc, pipe_to_program->next_odm_pipe, false); + } + } +} + +static void program_cursor_position_sequence( + struct dc *dc, + struct dc_stream_state *stream, + struct dc_state *context, + struct block_sequence_state *seq_state) +{ + int k; + struct pipe_ctx *pipe_to_program = NULL; + bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); + + for (k = 0; k < dc->res_pool->pipe_count; k++) { + struct pipe_ctx *tmp_pipe = &context->res_ctx.pipe_ctx[k]; + + if (tmp_pipe->stream != stream || + (!tmp_pipe->plane_res.mi && !tmp_pipe->plane_res.hubp) || + !tmp_pipe->plane_state || + (!tmp_pipe->plane_res.xfm && !tmp_pipe->plane_res.dpp) || + (!tmp_pipe->plane_res.ipp && !tmp_pipe->plane_res.dpp)) + continue; + + if (!pipe_to_program) { + pipe_to_program = tmp_pipe; + + if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) + hwss_add_begin_cursor_offload_update(seq_state, dc, tmp_pipe); + else + hwss_add_cursor_lock(seq_state, dc, pipe_to_program, true); + } + + hwss_add_set_cursor_position(seq_state, dc, tmp_pipe); + if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) + hwss_add_update_cursor_offload_pipe(seq_state, dc, tmp_pipe); + + if (dc->ctx->dmub_srv) + hwss_add_send_update_cursor_info_to_dmu(seq_state, tmp_pipe, k); + } + + if (pipe_to_program) { + if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) + hwss_add_commit_cursor_offload_update(seq_state, dc, pipe_to_program); + else + hwss_add_cursor_lock(seq_state, dc, pipe_to_program, false); + } +} + +static void add_update_info_frame_sequence( + struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + bool is_hdmi_tmds; + bool is_dp; + + if (!pipe_ctx || !pipe_ctx->stream) + return; + + if (pipe_ctx->stream_res.stream_enc == NULL) + return; + + is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); + is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); + + if (!is_hdmi_tmds && !is_dp) + return; + + if (is_hdmi_tmds) { + hwss_add_stream_enc_update_hdmi_info_packets(seq_state, pipe_ctx); + return; + } + + if (is_dp) { + if (dp_is_128b_132b_signal(pipe_ctx)) { + hwss_add_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(seq_state, pipe_ctx); + hwss_add_hpo_dp_stream_enc_update_dp_info_packets(seq_state, pipe_ctx); + } else { + hwss_add_stream_enc_update_dp_info_packets_sdp_line_num(seq_state, pipe_ctx); + hwss_add_stream_enc_update_dp_info_packets(seq_state, pipe_ctx); + } + } +} + +static void add_link_update_dsc_config_sequence( + struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, + struct dsc_config *dsc_cfg, + struct dsc_optc_config *dsc_optc_cfg) +{ + struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; + struct dc_stream_state *stream = pipe_ctx->stream; + struct dc *dc = stream->ctx->dc; + struct dccg *dccg = dc->res_pool->dccg; + struct pipe_ctx *top_pipe = pipe_ctx; + struct pipe_ctx *odm_pipe = NULL; + int opp_cnt = 1; + bool should_use_dto_dscclk = false; + struct dsc_config dsc_pps_cfg; + uint8_t *dsc_packed_pps = stream->dsc_packed_pps; + int last_dsc_set_config_step = 0; + + if (!stream->timing.flags.DSC || !dsc) + return; + + while (top_pipe->prev_odm_pipe) + top_pipe = top_pipe->prev_odm_pipe; + + for (odm_pipe = top_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) + opp_cnt++; + + memset(dsc_cfg, 0, sizeof(*dsc_cfg)); + memset(dsc_optc_cfg, 0, sizeof(*dsc_optc_cfg)); + + dsc_cfg->pic_width = (stream->timing.h_addressable + + top_pipe->dsc_padding_params.dsc_hactive_padding + + stream->timing.h_border_left + + stream->timing.h_border_right) / opp_cnt; + dsc_cfg->pic_height = stream->timing.v_addressable + + stream->timing.v_border_top + + stream->timing.v_border_bottom; + dsc_cfg->pixel_encoding = stream->timing.pixel_encoding; + dsc_cfg->color_depth = stream->timing.display_color_depth; + dsc_cfg->is_odm = top_pipe->next_odm_pipe ? true : false; + dsc_cfg->dc_dsc_cfg = stream->timing.dsc_cfg; + ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h % opp_cnt == 0); + dsc_cfg->dc_dsc_cfg.num_slices_h /= opp_cnt; + dsc_cfg->dsc_padding = 0; + + if (dccg && dccg->funcs->set_dto_dscclk && + stream->timing.pix_clk_100hz > 480000) + should_use_dto_dscclk = true; + + if (should_use_dto_dscclk) + hwss_add_dccg_set_dto_dscclk(seq_state, dccg, dsc->inst, + dsc_cfg->dc_dsc_cfg.num_slices_h); + + last_dsc_set_config_step = *seq_state->num_steps; + hwss_add_dsc_set_config(seq_state, dsc, dsc_cfg, dsc_optc_cfg); + hwss_add_dsc_enable_with_opp(seq_state, top_pipe); + + for (odm_pipe = top_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { + struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; + + if (should_use_dto_dscclk) + hwss_add_dccg_set_dto_dscclk(seq_state, dccg, odm_dsc->inst, + dsc_cfg->dc_dsc_cfg.num_slices_h); + + last_dsc_set_config_step = *seq_state->num_steps; + hwss_add_dsc_set_config(seq_state, odm_dsc, dsc_cfg, dsc_optc_cfg); + hwss_add_dsc_enable_with_opp(seq_state, odm_pipe); + } + + if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) + hwss_add_stream_enc_dp_set_dsc_config(seq_state, + pipe_ctx->stream_res.stream_enc, + &seq_state->steps[last_dsc_set_config_step].params.dsc_set_config_simple_params.dsc_optc_cfg); + + hwss_add_tg_set_dsc_config(seq_state, top_pipe->stream_res.tg, + &seq_state->steps[last_dsc_set_config_step].params.dsc_set_config_simple_params.dsc_optc_cfg, true); + + memset(&dsc_pps_cfg, 0, sizeof(dsc_pps_cfg)); + dsc_pps_cfg.pic_width = stream->timing.h_addressable + + stream->timing.h_border_left + stream->timing.h_border_right; + dsc_pps_cfg.pic_height = stream->timing.v_addressable + + stream->timing.v_border_top + stream->timing.v_border_bottom; + dsc_pps_cfg.pixel_encoding = stream->timing.pixel_encoding; + dsc_pps_cfg.color_depth = stream->timing.display_color_depth; + dsc_pps_cfg.is_odm = top_pipe->next_odm_pipe ? true : false; + dsc_pps_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; + dsc_pps_cfg.dsc_padding = top_pipe->dsc_padding_params.dsc_hactive_padding; + + if (dsc->funcs->dsc_get_packed_pps) { + dsc->funcs->dsc_get_packed_pps(dsc, &dsc_pps_cfg, dsc_packed_pps); + + if (dc_is_dp_signal(stream->signal)) { + if (dp_is_128b_132b_signal(pipe_ctx)) + hwss_add_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(seq_state, + pipe_ctx->stream_res.hpo_dp_stream_enc, + true, dsc_packed_pps, false); + else + hwss_add_stream_enc_dp_set_dsc_pps_info_packet(seq_state, + pipe_ctx->stream_res.stream_enc, + true, dsc_packed_pps, false); + } + } +} + +static void commit_planes_do_stream_update_sequence(struct dc *dc, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + enum surface_update_type update_type, + struct dc_state *context, + struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], + unsigned int *num_steps) +{ + int j; + struct block_sequence_state seq_state = { .steps = block_sequence, .num_steps = num_steps }; + struct dsc_config dsc_cfgs[MAX_PIPES]; + struct dsc_optc_config dsc_optc_cfgs[MAX_PIPES]; + unsigned int dsc_cfg_index = 0; + *num_steps = 0; // Initialize to 0 + + // Stream updates + for (j = 0; j < dc->res_pool->pipe_count; j++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; + + if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_ctx->stream == stream) { + + if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt) + hwss_add_setup_periodic_interrupt(&seq_state, dc, pipe_ctx); + + if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) || + stream_update->vrr_infopacket || + stream_update->vsc_infopacket || + stream_update->vsp_infopacket || + stream_update->hfvsif_infopacket || + stream_update->adaptive_sync_infopacket || + stream_update->vtem_infopacket || + stream_update->avi_infopacket) { + resource_build_info_frame(pipe_ctx); + add_update_info_frame_sequence(&seq_state, pipe_ctx); + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + hwss_add_dp_trace_source_sequence(&seq_state, + pipe_ctx->stream->link, + DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); + } + + if (stream_update->hdr_static_metadata && + stream->use_dynamic_meta && + dc->hwss.set_dmdata_attributes && + pipe_ctx->stream->dmdata_address.quad_part != 0) + hwss_add_set_dmdata_attributes(&seq_state, pipe_ctx); + + if (stream_update->gamut_remap) + hwss_add_dpp_program_gamut_remap(&seq_state, pipe_ctx); + + if (stream_update->output_csc_transform) + hwss_add_program_output_csc(&seq_state, dc, pipe_ctx, + stream->output_color_space, + stream->csc_color_matrix.matrix, + pipe_ctx->stream_res.opp->inst); + + if (stream_update->dither_option) { + struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; + resource_build_bit_depth_reduction_params(pipe_ctx->stream, + &pipe_ctx->stream->bit_depth_params); + hwss_add_opp_program_fmt(&seq_state, pipe_ctx->stream_res.opp, + &stream->bit_depth_params, + &stream->clamping); + while (odm_pipe) { + hwss_add_opp_program_fmt(&seq_state, odm_pipe->stream_res.opp, + &stream->bit_depth_params, + &stream->clamping); + odm_pipe = odm_pipe->next_odm_pipe; + } + } + + if (stream_update->cursor_attributes) + program_cursor_attributes_sequence(dc, stream, context, &seq_state); + + if (stream_update->cursor_position) + program_cursor_position_sequence(dc, stream, context, &seq_state); + + /* Full fe update*/ + if (update_type == UPDATE_TYPE_FAST) + continue; + + if (stream_update->dsc_config) + if (dsc_cfg_index < MAX_PIPES) { + add_link_update_dsc_config_sequence(&seq_state, + pipe_ctx, + &dsc_cfgs[dsc_cfg_index], + &dsc_optc_cfgs[dsc_cfg_index]); + dsc_cfg_index++; + } + + if (stream_update->mst_bw_update) { + if (stream_update->mst_bw_update->is_increase) + hwss_add_link_increase_mst_payload(&seq_state, + pipe_ctx, + stream_update->mst_bw_update->mst_stream_bw); + else + hwss_add_link_reduce_mst_payload(&seq_state, + pipe_ctx, + stream_update->mst_bw_update->mst_stream_bw); + } + + if (stream_update->pending_test_pattern) { + /* + * test pattern params depends on ODM topology + * changes that we could be applying to front + * end. Since at the current stage front end + * changes are not yet applied. We can only + * apply test pattern in hw based on current + * state and populate the final test pattern + * params in new state. If current and new test + * pattern params are different as result of + * different ODM topology being used, it will be + * detected and handle during front end + * programming update. + */ + hwss_add_dp_set_test_pattern(&seq_state, + stream->link, + stream->test_pattern.type, + stream->test_pattern.color_space, + stream->test_pattern.p_link_settings, + stream->test_pattern.p_custom_pattern, + stream->test_pattern.cust_pattern_size); + resource_build_test_pattern_params(&context->res_ctx, pipe_ctx); + } + + if (stream_update->dpms_off) { + // DPMS should not use partially updated pipe context + struct pipe_ctx *dpms_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j]; + + if (*stream_update->dpms_off) { + hwss_add_link_set_dpms_off(&seq_state, dpms_pipe_ctx); + /* for dpms, keep acquired resources*/ + if (dpms_pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only) + hwss_add_disable_audio_stream(&seq_state, dpms_pipe_ctx); + + hwss_add_dc_set_optimized_required(&seq_state, dc, true); + + } else { + if (get_seamless_boot_stream_count(context) == 0) + hwss_add_prepare_bandwidth(&seq_state, dc, dc->current_state); + hwss_add_link_set_dpms_on(&seq_state, dc->current_state, dpms_pipe_ctx); + } + } else if (pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && stream_update->output_color_space + && !stream->dpms_off && dc_is_dp_signal(pipe_ctx->stream->signal)) { + /* + * Workaround for firmware issue in some receivers where they don't pick up + * correct output color space unless DP link is disabled/re-enabled + */ + hwss_add_link_set_dpms_on(&seq_state, dc->current_state, pipe_ctx); + } + + if (stream_update->abm_level && pipe_ctx->stream_res.abm) { + bool should_program_abm = true; + + // if otg funcs defined check if blanked before programming + if (pipe_ctx->stream_res.tg->funcs->is_blanked) + if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) + should_program_abm = false; + + if (should_program_abm) { + if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) { + hwss_add_abm_set_immediate_disable(&seq_state, dc, pipe_ctx); + } else { + hwss_add_abm_set_level(&seq_state, pipe_ctx->stream_res.abm, stream->abm_level); + } + } + } + } + } +} + static void commit_planes_do_stream_update(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *stream_update, enum surface_update_type update_type, struct dc_state *context) { - int j; + unsigned int j; + // Check if block sequence programming is enabled + if (dc->debug.enable_block_sequence_programming) { + unsigned int num_steps = 0; + + // Build the block sequence using context's pre-allocated array + commit_planes_do_stream_update_sequence(dc, stream, stream_update, + update_type, context, context->block_sequence, &num_steps); + + // Execute the block sequence + if (num_steps > 0) + hwss_execute_sequence(dc, context->block_sequence, num_steps); + + return; + } + + // Legacy path (existing implementation) // Stream updates for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; @@ -3849,27 +4359,34 @@ static void commit_planes_do_stream_update(struct dc *dc, resource_build_test_pattern_params(&context->res_ctx, pipe_ctx); } + // DPMS should not use partially updated pipe context + struct pipe_ctx *dpms_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j]; + if (stream_update->dpms_off) { if (*stream_update->dpms_off) { - dc->link_srv->set_dpms_off(pipe_ctx); + dc->link_srv->set_dpms_off(dpms_pipe_ctx); /* for dpms, keep acquired resources*/ - if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only) - pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); + if (dpms_pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only) { + struct audio *audio = dpms_pipe_ctx->stream_res.audio; + + audio->funcs->az_disable(audio); + } dc->optimized_required = true; } else { if (get_seamless_boot_stream_count(context) == 0) dc->hwss.prepare_bandwidth(dc, dc->current_state); - dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx); + dc->link_srv->set_dpms_on(dc->current_state, dpms_pipe_ctx); } - } else if (pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && stream_update->output_color_space - && !stream->dpms_off && dc_is_dp_signal(pipe_ctx->stream->signal)) { + } else if (dpms_pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && + stream_update->output_color_space && + !stream->dpms_off && dc_is_dp_signal(dpms_pipe_ctx->stream->signal)) { /* * Workaround for firmware issue in some receivers where they don't pick up * correct output color space unless DP link is disabled/re-enabled */ - dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx); + dc->link_srv->set_dpms_on(dc->current_state, dpms_pipe_ctx); } if (stream_update->abm_level && pipe_ctx->stream_res.abm) { @@ -3918,7 +4435,8 @@ void dc_dmub_update_dirty_rect(struct dc *dc, { union dmub_rb_cmd cmd; struct dmub_cmd_update_dirty_rect_data *update_dirty_rect; - unsigned int i, j; + int i; + unsigned int j; unsigned int panel_inst = 0; if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream)) @@ -3949,7 +4467,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc, else update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; - update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; + update_dirty_rect->dirty_rect_count = (uint8_t)flip_addr->dirty_rect_count; memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects, sizeof(flip_addr->dirty_rects)); for (j = 0; j < dc->res_pool->pipe_count; j++) { @@ -3960,9 +4478,9 @@ void dc_dmub_update_dirty_rect(struct dc *dc, if (pipe_ctx->plane_state != plane_state) continue; - update_dirty_rect->panel_inst = panel_inst; - update_dirty_rect->pipe_idx = j; - update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst; + update_dirty_rect->panel_inst = (uint8_t)panel_inst; + update_dirty_rect->pipe_idx = (uint8_t)j; + update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); } } @@ -3979,7 +4497,8 @@ static void build_dmub_update_dirty_rect( { union dmub_rb_cmd cmd; struct dmub_cmd_update_dirty_rect_data *update_dirty_rect; - unsigned int i, j; + int i; + unsigned int j; unsigned int panel_inst = 0; if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream)) @@ -4010,7 +4529,7 @@ static void build_dmub_update_dirty_rect( else update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; - update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; + update_dirty_rect->dirty_rect_count = (uint8_t)flip_addr->dirty_rect_count; memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects, sizeof(flip_addr->dirty_rects)); for (j = 0; j < dc->res_pool->pipe_count; j++) { @@ -4020,9 +4539,9 @@ static void build_dmub_update_dirty_rect( continue; if (pipe_ctx->plane_state != plane_state) continue; - update_dirty_rect->panel_inst = panel_inst; - update_dirty_rect->pipe_idx = j; - update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst; + update_dirty_rect->panel_inst = (uint8_t)panel_inst; + update_dirty_rect->pipe_idx = (uint8_t)j; + update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd; dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT; (*dmub_cmd_count)++; @@ -4030,7 +4549,7 @@ static void build_dmub_update_dirty_rect( } } -static bool check_address_only_update(union surface_update_flags update_flags) +bool dc_check_address_only_update(union surface_update_flags update_flags) { union surface_update_flags addr_only_update_flags; addr_only_update_flags.raw = 0; @@ -4076,7 +4595,8 @@ static void commit_plane_for_stream_offload_fams2_flip(struct dc *dc, struct dc_stream_state *stream, struct dc_state *context) { - int i, j; + int i; + unsigned int j; /* update dirty rect for PSR */ dc_dmub_update_dirty_rect(dc, surface_count, stream, @@ -4117,7 +4637,8 @@ static void commit_planes_for_stream_fast(struct dc *dc, enum surface_update_type update_type, struct dc_state *context) { - int i, j; + int i; + unsigned int j; struct pipe_ctx *top_pipe_to_program = NULL; struct dc_stream_status *stream_status = NULL; bool should_offload_fams2_flip = false; @@ -4134,7 +4655,7 @@ static void commit_planes_for_stream_fast(struct dc *dc, for (i = 0; i < surface_count; i++) { if (srf_updates[i].surface && srf_updates[i].surface->update_flags.raw && - !check_address_only_update(srf_updates[i].surface->update_flags)) { + !dc_check_address_only_update(srf_updates[i].surface->update_flags)) { /* more than address update, need to acquire FAMS2 lock */ should_offload_fams2_flip = false; break; @@ -4157,7 +4678,7 @@ static void commit_planes_for_stream_fast(struct dc *dc, if (!top_pipe_to_program) return; - for (i = 0; i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < (int)dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; if (pipe->stream && pipe->plane_state) { @@ -4236,7 +4757,8 @@ static void commit_planes_for_stream(struct dc *dc, enum surface_update_type update_type, struct dc_state *context) { - int i, j; + int i; + unsigned int j, pipe_idx; struct pipe_ctx *top_pipe_to_program = NULL; bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST); bool subvp_prev_use = false; @@ -4258,8 +4780,8 @@ static void commit_planes_for_stream(struct dc *dc, if (update_type != UPDATE_TYPE_FAST && dc->res_pool->funcs->prepare_mcache_programming) dc->res_pool->funcs->prepare_mcache_programming(dc, context); - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[pipe_idx]; if (pipe->stream && pipe->plane_state) { if (!dc->debug.using_dml2) @@ -4290,8 +4812,8 @@ static void commit_planes_for_stream(struct dc *dc, stream); ASSERT(top_pipe_to_program != NULL); - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; + for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { + struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_idx]; // Check old context for SubVP subvp_prev_use |= (dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) == SUBVP_PHANTOM); @@ -4299,8 +4821,8 @@ static void commit_planes_for_stream(struct dc *dc, break; } - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[pipe_idx]; if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) { subvp_curr_use = true; @@ -4325,7 +4847,7 @@ static void commit_planes_for_stream(struct dc *dc, struct dmub_hw_lock_inst_flags inst_flags = { 0 }; hw_locks.bits.lock_dig = 1; - inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst; + inst_flags.dig_inst = (uint8_t)top_pipe_to_program->stream_res.tg->inst; dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, true, @@ -4502,16 +5024,16 @@ static void commit_planes_for_stream(struct dc *dc, } if (dc->debug.validate_dml_output) { - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; + for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { + struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; if (cur_pipe->stream == NULL) continue; cur_pipe->plane_res.hubp->funcs->validate_dml_output( cur_pipe->plane_res.hubp, dc->ctx, - &context->res_ctx.pipe_ctx[i].rq_regs, - &context->res_ctx.pipe_ctx[i].dlg_regs, - &context->res_ctx.pipe_ctx[i].ttu_regs); + &context->res_ctx.pipe_ctx[pipe_idx].rq_regs, + &context->res_ctx.pipe_ctx[pipe_idx].dlg_regs, + &context->res_ctx.pipe_ctx[pipe_idx].ttu_regs); } } } @@ -4550,9 +5072,11 @@ static void commit_planes_for_stream(struct dc *dc, if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state)) continue; - if (srf_updates[i].cm && - srf_updates[i].cm->flags.bits.lut3d_enable && - srf_updates[i].cm->flags.bits.lut3d_dma_enable && + if (srf_updates[i].cm2_params && + srf_updates[i].cm2_params->cm2_luts.lut3d_data.lut3d_src == + DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM && + srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting == + DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT && dc->hwss.trigger_3dlut_dma_load) dc->hwss.trigger_3dlut_dma_load(dc, pipe_ctx); @@ -4592,7 +5116,7 @@ static void commit_planes_for_stream(struct dc *dc, struct dmub_hw_lock_inst_flags inst_flags = { 0 }; hw_locks.bits.lock_dig = 1; - inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst; + inst_flags.dig_inst = (uint8_t)top_pipe_to_program->stream_res.tg->inst; dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, false, @@ -4831,7 +5355,7 @@ static void swap_and_release_current_context(struct dc *dc, struct dc_state *new_context, struct dc_stream_state *stream) { - int i; + unsigned int i; struct dc_state *old = dc->current_state; struct pipe_ctx *pipe_ctx; @@ -5091,7 +5615,7 @@ static bool commit_minimal_transition_state(struct dc *dc, /* force full surface update */ for (i = 0; i < dc->current_state->stream_count; i++) { - for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { + for (j = 0; j < (unsigned int)dc->current_state->stream_status[i].plane_count; j++) { dc->current_state->stream_status[i].plane_states[j]->update_flags.raw = 0xFFFFFFFF; } } @@ -5099,81 +5623,6 @@ static bool commit_minimal_transition_state(struct dc *dc, return true; } -void populate_fast_updates(struct dc_fast_update *fast_update, - struct dc_surface_update *srf_updates, - int surface_count, - struct dc_stream_update *stream_update) -{ - int i = 0; - - if (stream_update) { - fast_update[0].out_transfer_func = stream_update->out_transfer_func; - fast_update[0].output_csc_transform = stream_update->output_csc_transform; - } else { - fast_update[0].out_transfer_func = NULL; - fast_update[0].output_csc_transform = NULL; - } - - for (i = 0; i < surface_count; i++) { - fast_update[i].flip_addr = srf_updates[i].flip_addr; - fast_update[i].gamma = srf_updates[i].gamma; - fast_update[i].gamut_remap_matrix = srf_updates[i].gamut_remap_matrix; - fast_update[i].input_csc_color_matrix = srf_updates[i].input_csc_color_matrix; - fast_update[i].coeff_reduction_factor = srf_updates[i].coeff_reduction_factor; - fast_update[i].cursor_csc_color_matrix = srf_updates[i].cursor_csc_color_matrix; -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) - fast_update[i].cm_hist_control = srf_updates[i].cm_hist_control; -#endif - } -} - -static bool fast_updates_exist(const struct dc_fast_update *fast_update, int surface_count) -{ - int i; - - if (fast_update[0].out_transfer_func || - fast_update[0].output_csc_transform) - return true; - - for (i = 0; i < surface_count; i++) { - if (fast_update[i].flip_addr || - fast_update[i].gamma || - fast_update[i].gamut_remap_matrix || - fast_update[i].input_csc_color_matrix || - fast_update[i].cursor_csc_color_matrix || -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) - fast_update[i].cm_hist_control || -#endif - fast_update[i].coeff_reduction_factor) - return true; - } - - return false; -} - -bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count) -{ - int i; - - if (fast_update[0].out_transfer_func || - fast_update[0].output_csc_transform) - return true; - - for (i = 0; i < surface_count; i++) { - if (fast_update[i].input_csc_color_matrix || - fast_update[i].gamma || - fast_update[i].gamut_remap_matrix || - fast_update[i].coeff_reduction_factor || -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) - fast_update[i].cm_hist_control || -#endif - fast_update[i].cursor_csc_color_matrix) - return true; - } - - return false; -} - static bool full_update_required_weak( const struct dc *dc, const struct dc_surface_update *srf_updates, @@ -5202,87 +5651,6 @@ static bool full_update_required_weak( return false; } -static bool full_update_required( - const struct dc *dc, - const struct dc_surface_update *srf_updates, - int surface_count, - const struct dc_stream_update *stream_update, - const struct dc_stream_state *stream) -{ - const union dc_plane_cm_flags blend_only_flags = { - .bits = { - .blend_enable = 1, - } - }; - - if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream)) - return true; - - for (int i = 0; i < surface_count; i++) { - if (srf_updates && - (srf_updates[i].plane_info || - srf_updates[i].scaling_info || - (srf_updates[i].hdr_mult.value && - srf_updates[i].hdr_mult.value != srf_updates->surface->hdr_mult.value) || - (srf_updates[i].sdr_white_level_nits && - srf_updates[i].sdr_white_level_nits != srf_updates->surface->sdr_white_level_nits) || - srf_updates[i].in_transfer_func || - srf_updates[i].surface->force_full_update || - (srf_updates[i].flip_addr && - srf_updates[i].flip_addr->address.tmz_surface != srf_updates[i].surface->address.tmz_surface) || - (srf_updates[i].cm && - ((srf_updates[i].cm->flags.all != blend_only_flags.all && srf_updates[i].cm->flags.all != 0) || - (srf_updates[i].surface->cm.flags.all != blend_only_flags.all && srf_updates[i].surface->cm.flags.all != 0))))) - return true; - } - - if (stream_update && - (((stream_update->src.height != 0 && stream_update->src.width != 0) || - (stream_update->dst.height != 0 && stream_update->dst.width != 0) || - stream_update->integer_scaling_update) || - stream_update->hdr_static_metadata || - stream_update->abm_level || - stream_update->periodic_interrupt || - stream_update->vrr_infopacket || - stream_update->vsc_infopacket || - stream_update->vsp_infopacket || - stream_update->hfvsif_infopacket || - stream_update->vtem_infopacket || - stream_update->adaptive_sync_infopacket || - stream_update->avi_infopacket || - stream_update->dpms_off || - stream_update->allow_freesync || - stream_update->vrr_active_variable || - stream_update->vrr_active_fixed || - stream_update->gamut_remap || - stream_update->output_color_space || - stream_update->dither_option || - stream_update->wb_update || - stream_update->dsc_config || - stream_update->mst_bw_update || - stream_update->func_shaper || - stream_update->lut3d_func || - stream_update->pending_test_pattern || - stream_update->crtc_timing_adjust || - stream_update->scaler_sharpener_update || - stream_update->hw_cursor_req)) - return true; - - return false; -} - -static bool fast_update_only( - const struct dc *dc, - const struct dc_fast_update *fast_update, - const struct dc_surface_update *srf_updates, - int surface_count, - const struct dc_stream_update *stream_update, - const struct dc_stream_state *stream) -{ - return fast_updates_exist(fast_update, surface_count) - && !full_update_required(dc, srf_updates, surface_count, stream_update, stream); -} - static bool update_planes_and_stream_v2(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, struct dc_stream_state *stream, @@ -5290,7 +5658,6 @@ static bool update_planes_and_stream_v2(struct dc *dc, { struct dc_state *context; enum surface_update_type update_type; - struct dc_fast_update fast_update[MAX_SURFACES] = {0}; /* In cases where MPO and split or ODM are used transitions can * cause underflow. Apply stream configuration with minimal pipe @@ -5298,11 +5665,7 @@ static bool update_planes_and_stream_v2(struct dc *dc, */ bool force_minimal_pipe_splitting = 0; bool is_plane_addition = 0; - bool is_fast_update_only; - populate_fast_updates(fast_update, srf_updates, surface_count, stream_update); - is_fast_update_only = fast_update_only(dc, fast_update, srf_updates, - surface_count, stream_update, stream); force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes( dc, stream, @@ -5340,7 +5703,7 @@ static bool update_planes_and_stream_v2(struct dc *dc, commit_minimal_transition_state_in_dc_update(dc, context, stream, srf_updates, surface_count); - if (is_fast_update_only && !dc->check_config.enable_legacy_fast_update) { + if (update_type == UPDATE_TYPE_FAST && !dc->check_config.enable_legacy_fast_update) { commit_planes_for_stream_fast(dc, srf_updates, surface_count, @@ -5376,13 +5739,8 @@ static void commit_planes_and_stream_update_on_current_context(struct dc *dc, struct dc_stream_update *stream_update, enum surface_update_type update_type) { - struct dc_fast_update fast_update[MAX_SURFACES] = {0}; - ASSERT(update_type < UPDATE_TYPE_FULL); - populate_fast_updates(fast_update, srf_updates, surface_count, - stream_update); - if (fast_update_only(dc, fast_update, srf_updates, surface_count, - stream_update, stream) && + if (update_type == UPDATE_TYPE_FAST && !dc->check_config.enable_legacy_fast_update) commit_planes_for_stream_fast(dc, srf_updates, @@ -5766,7 +6124,8 @@ bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips) void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, char const *caller_name) { - int idle_fclk_khz = 0, idle_dramclk_khz = 0, i = 0; + int idle_fclk_khz = 0, idle_dramclk_khz = 0; + unsigned int i = 0; enum mall_stream_type subvp_pipe_type[MAX_PIPES] = {0}; struct pipe_ctx *pipe = NULL; struct dc_state *context = dc->current_state; @@ -5865,7 +6224,7 @@ static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memcl struct dc_state *context = dc->current_state; struct hubp *hubp; struct pipe_ctx *pipe; - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { pipe = &context->res_ctx.pipe_ctx[i]; @@ -6081,12 +6440,12 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc, else cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC; - cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst; + cmd.dp_aux_access.aux_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst; cmd.dp_aux_access.aux_control.sw_crc_enabled = 0; cmd.dp_aux_access.aux_control.timeout = 0; cmd.dp_aux_access.aux_control.dpaux.address = payload->address; cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux; - cmd.dp_aux_access.aux_control.dpaux.length = payload->length; + cmd.dp_aux_access.aux_control.dpaux.length = (uint8_t)payload->length; /* set aux action */ if (payload->i2c_over_aux) { @@ -6152,7 +6511,7 @@ bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_ } if (pipe_ctx) - otg_inst = pipe_ctx->stream_res.tg->inst; + otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; // before enable smart power OLED, we need to call set pipe for DMUB to set ABM config if (enable) { @@ -6169,11 +6528,11 @@ bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_ sizeof(struct dmub_rb_cmd_smart_power_oled_enable_data) - sizeof(struct dmub_cmd_header); cmd.smart_power_oled_enable.header.ret_status = 1; cmd.smart_power_oled_enable.data.enable = enable; - cmd.smart_power_oled_enable.data.panel_inst = panel_inst; + cmd.smart_power_oled_enable.data.panel_inst = (uint8_t)panel_inst; cmd.smart_power_oled_enable.data.peak_nits = peak_nits; cmd.smart_power_oled_enable.data.otg_inst = otg_inst; - cmd.smart_power_oled_enable.data.digfe_inst = link->link_enc->preferred_engine; - cmd.smart_power_oled_enable.data.digbe_inst = link->link_enc->transmitter; + cmd.smart_power_oled_enable.data.digfe_inst = (uint8_t)link->link_enc->preferred_engine; + cmd.smart_power_oled_enable.data.digbe_inst = (uint8_t)link->link_enc->transmitter; cmd.smart_power_oled_enable.data.debugcontrol = debug_control; cmd.smart_power_oled_enable.data.triggerline = triggerline; @@ -6182,6 +6541,10 @@ bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_ // send cmd status = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); + // Update firmware_controlled_hdr_info_packet state on successful command execution + if (status && pipe_ctx) + pipe_ctx->stream->firmware_controlled_hdr_info_packet = enable; + return status; } @@ -6204,7 +6567,7 @@ bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *p cmd.smart_power_oled_getmaxcll.header.payload_bytes = sizeof(cmd.smart_power_oled_getmaxcll.data); cmd.smart_power_oled_getmaxcll.header.ret_status = 1; - cmd.smart_power_oled_getmaxcll.data.input.panel_inst = panel_inst; + cmd.smart_power_oled_getmaxcll.data.input.panel_inst = (uint8_t)panel_inst; // send cmd and wait for reply status = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); @@ -6262,7 +6625,7 @@ bool dc_process_dmub_set_config_async(struct dc *dc, cmd.set_config_access.header.type = DMUB_CMD__DPIA; cmd.set_config_access.header.sub_type = DMUB_CMD__DPIA_SET_CONFIG_ACCESS; - cmd.set_config_access.set_config_control.instance = dc->links[link_index]->ddc_hw_inst; + cmd.set_config_access.set_config_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst; cmd.set_config_access.set_config_control.cmd_pkt.msg_type = payload->msg_type; cmd.set_config_access.set_config_control.cmd_pkt.msg_data = payload->msg_data; @@ -6306,7 +6669,7 @@ enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, cmd.set_mst_alloc_slots.header.type = DMUB_CMD__DPIA; cmd.set_mst_alloc_slots.header.sub_type = DMUB_CMD__DPIA_MST_ALLOC_SLOTS; - cmd.set_mst_alloc_slots.mst_slots_control.instance = dc->links[link_index]->ddc_hw_inst; + cmd.set_mst_alloc_slots.mst_slots_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst; cmd.set_mst_alloc_slots.mst_slots_control.mst_alloc_slots = mst_alloc_slots; if (!dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) @@ -6346,7 +6709,7 @@ void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t lin cmd.set_tps_notification.header.type = DMUB_CMD__DPIA; cmd.set_tps_notification.header.sub_type = DMUB_CMD__DPIA_SET_TPS_NOTIFICATION; - cmd.set_tps_notification.tps_notification.instance = dc->links[link_index]->ddc_hw_inst; + cmd.set_tps_notification.tps_notification.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst; cmd.set_tps_notification.tps_notification.tps = tps; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); @@ -6672,7 +7035,8 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa { struct dc_state *context; struct resource_context *res_ctx; - int i; + unsigned int i; + const unsigned int max_pipes = MAX_PIPES; if (!dc || !dc->current_state || !state) { if (state) @@ -6696,7 +7060,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa } /* Capture HUBP programming state for each pipe */ - for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; state->hubp[i].valid_stream = false; @@ -6818,7 +7182,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa /* Capture HUBBUB programming state */ if (dc->res_pool->hubbub) { /* Individual DET buffer sizes - software state variables that program DET registers */ - for (i = 0; i < 4 && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < 4u && i < dc->res_pool->pipe_count; i++) { uint32_t det_size = res_ctx->pipe_ctx[i].det_buffer_size_kb; switch (i) { case 0: @@ -6842,7 +7206,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa } /* Capture DPP programming state for each pipe */ - for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; if (!pipe_ctx->stream) @@ -6883,7 +7247,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa state->dccg.dispclk_khz = dc->clk_mgr->clks.dispclk_khz; /* Per-pipe clock configuration - only capture what's essential */ - for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; if (pipe_ctx->stream) { /* Essential clocks that directly affect underflow risk */ @@ -6910,7 +7274,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa } /* DSC clock state - only when actually using DSC */ - for (i = 0; i < MAX_PIPES; i++) { + for (i = 0; i < max_pipes; i++) { struct pipe_ctx *pipe_ctx = (i < dc->res_pool->pipe_count) ? &res_ctx->pipe_ctx[i] : NULL; if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) { state->dccg.dscclk_khz[i] = 400000; /* Typical DSC clock frequency */ @@ -6927,7 +7291,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa } /* Capture essential DSC configuration for underflow analysis */ - for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; if (pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) { @@ -6955,14 +7319,14 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa } /* Capture MPC programming state - comprehensive register field coverage */ - for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; if (pipe_ctx->plane_state && pipe_ctx->stream) { struct dc_plane_state *plane_state = pipe_ctx->plane_state; /* MPCC blending tree and mode control - capture actual blend configuration */ - state->mpc.mpcc_mode[i] = (plane_state->cm.blend_func.type != TF_TYPE_BYPASS) ? 1 : 0; + state->mpc.mpcc_mode[i] = (plane_state->blend_tf.type != TF_TYPE_BYPASS) ? 1 : 0; state->mpc.mpcc_alpha_blend_mode[i] = plane_state->per_pixel_alpha ? 1 : 0; state->mpc.mpcc_alpha_multiplied_mode[i] = plane_state->pre_multiplied_alpha ? 1 : 0; state->mpc.mpcc_blnd_active_overlap_only[i] = 0; /* Default - no overlap restriction */ @@ -7023,7 +7387,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa } /* Capture OPP programming state for each pipe - comprehensive register field coverage */ - for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; if (!pipe_ctx->stream) @@ -7141,7 +7505,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa } /* Capture OPTC programming state for each pipe - comprehensive register field coverage */ - for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; if (!pipe_ctx->stream) @@ -7237,7 +7601,8 @@ void dc_log_preos_dmcub_info(const struct dc *dc) bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info) { const struct dc_clocks *clk = &dc->current_state->bw_ctx.bw.dcn.clk; - struct memory_qos qos; + struct dc_measured_memory_qos measured = {}; + struct dc_requested_memory_qos requested = {}; memset(info, 0, sizeof(*info)); @@ -7246,20 +7611,38 @@ bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info) return false; } - // Call unified measurement function - dc->hwss.measure_memory_qos(dc, &qos); + dc->hwss.measure_memory_qos(dc, &measured); - // Populate info from measured qos - info->actual_peak_bw_in_mbps = qos.peak_bw_mbps; - info->actual_avg_bw_in_mbps = qos.avg_bw_mbps; - info->actual_min_latency_in_ns = qos.min_latency_ns; - info->actual_max_latency_in_ns = qos.max_latency_ns; - info->actual_avg_latency_in_ns = qos.avg_latency_ns; - info->dcn_bandwidth_ub_in_mbps = (uint32_t)(clk->fclk_khz / 1000 * 64); + info->actual_peak_bw_in_mbps = measured.peak_bw_mbps; + info->actual_avg_bw_in_mbps = measured.avg_bw_mbps; + info->actual_min_latency_in_ns = measured.min_latency_ns; + info->actual_max_latency_in_ns = measured.max_latency_ns; + info->actual_avg_latency_in_ns = measured.avg_latency_ns; + info->dcn_bandwidth_ub_in_mbps = (uint32_t)(clk->fclk_khz / 1000 * 64); + + if (dc->clk_mgr && dc->clk_mgr->funcs->get_requested_memory_qos) { + dc->clk_mgr->funcs->get_requested_memory_qos(dc->clk_mgr, &requested); + info->qos_bandwidth_lb_in_mbps = requested.bandwidth_lb_in_mbps; + info->calculated_avg_bw_in_mbps = requested.calculated_avg_bw_in_mbps; + info->qos_max_latency_ub_in_ns = requested.max_latency_ub_in_ns; + info->qos_avg_latency_ub_in_ns = requested.avg_latency_ub_in_ns; + info->qos_max_bw_budget_in_mbps = requested.max_bw_budget_in_mbps; + } return true; } +unsigned int dc_override_memory_bandwidth_request( + struct dc *dc, + unsigned int bw_mbps) +{ + if (!dc->clk_mgr || !dc->clk_mgr->funcs) + return 0; + + return dc->clk_mgr->funcs->override_memory_bandwidth_request( + dc->clk_mgr, bw_mbps * 1000) / 1000; +} + enum update_v3_flow { UPDATE_V3_FLOW_INVALID, UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST, @@ -7360,23 +7743,6 @@ static bool update_planes_and_stream_prepare_v3( ASSERT(scratch->flow == UPDATE_V3_FLOW_INVALID); dc_exit_ips_for_hw_access(scratch->dc); - /* HWSS path determination needs to be done prior to updating the surface and stream states. */ - struct dc_fast_update fast_update[MAX_SURFACES] = { 0 }; - - populate_fast_updates(fast_update, - scratch->surface_updates, - scratch->surface_count, - scratch->stream_update); - - const bool is_hwss_fast_path_only = - fast_update_only(scratch->dc, - fast_update, - scratch->surface_updates, - scratch->surface_count, - scratch->stream_update, - scratch->stream) && - !scratch->dc->check_config.enable_legacy_fast_update; - if (!update_planes_and_stream_state( scratch->dc, scratch->surface_updates, @@ -7392,7 +7758,8 @@ static bool update_planes_and_stream_prepare_v3( if (scratch->new_context == scratch->dc->current_state) { ASSERT(scratch->update_type < UPDATE_TYPE_FULL); - scratch->flow = is_hwss_fast_path_only + scratch->flow = (scratch->update_type == UPDATE_TYPE_FAST && + !scratch->dc->check_config.enable_legacy_fast_update) ? UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST : UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FULL; return true; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 7333f5905330..ffa3130853c2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -39,6 +39,7 @@ #include "abm.h" #include "dcn10/dcn10_hubbub.h" #include "dce/dmub_hw_lock_mgr.h" +#include "link_service.h" #define MAX_NUM_MCACHE 8 @@ -345,39 +346,39 @@ void get_surface_visual_confirm_color( switch (pipe_ctx->plane_res.scl_data.format) { case PIXEL_FORMAT_ARGB8888: /* set border color to red */ - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; if (pipe_ctx->plane_state->layer_index > 0) { /* set border color to pink */ - color->color_b_cb = color_value; - color->color_g_y = color_value * 0.5; + color->color_b_cb = (uint16_t)color_value; + color->color_g_y = (uint16_t)(color_value / 2); } break; case PIXEL_FORMAT_ARGB2101010: /* set border color to blue */ - color->color_b_cb = color_value; + color->color_b_cb = (uint16_t)color_value; if (pipe_ctx->plane_state->layer_index > 0) { /* set border color to cyan */ - color->color_g_y = color_value; + color->color_g_y = (uint16_t)color_value; } break; case PIXEL_FORMAT_420BPP8: /* set border color to green */ - color->color_g_y = color_value; + color->color_g_y = (uint16_t)color_value; break; case PIXEL_FORMAT_420BPP10: /* set border color to yellow */ - color->color_g_y = color_value; - color->color_r_cr = color_value; + color->color_g_y = (uint16_t)color_value; + color->color_r_cr = (uint16_t)color_value; break; case PIXEL_FORMAT_FP16: /* set border color to white */ - color->color_r_cr = color_value; - color->color_b_cb = color_value; - color->color_g_y = color_value; + color->color_r_cr = (uint16_t)color_value; + color->color_b_cb = (uint16_t)color_value; + color->color_g_y = (uint16_t)color_value; if (pipe_ctx->plane_state->layer_index > 0) { /* set border color to orange */ - color->color_g_y = 0.22 * color_value; + color->color_g_y = (uint16_t)((color_value * 22) / 100); color->color_b_cb = 0; } break; @@ -403,21 +404,21 @@ void get_hdr_visual_confirm_color( case PIXEL_FORMAT_ARGB2101010: if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) { /* HDR10, ARGB2101010 - set border color to red */ - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) { /* FreeSync 2 ARGB2101010 - set border color to pink */ - color->color_r_cr = color_value; - color->color_b_cb = color_value; + color->color_r_cr = (uint16_t)color_value; + color->color_b_cb = (uint16_t)color_value; } else is_sdr = true; break; case PIXEL_FORMAT_FP16: if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) { /* HDR10, FP16 - set border color to blue */ - color->color_b_cb = color_value; + color->color_b_cb = (uint16_t)color_value; } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) { /* FreeSync 2 HDR - set border color to green */ - color->color_g_y = color_value; + color->color_g_y = (uint16_t)color_value; } else is_sdr = true; break; @@ -428,9 +429,9 @@ void get_hdr_visual_confirm_color( if (is_sdr) { /* SDR - set border color to Gray */ - color->color_r_cr = color_value/2; - color->color_b_cb = color_value/2; - color->color_g_y = color_value/2; + color->color_r_cr = (uint16_t)(color_value / 2); + color->color_b_cb = (uint16_t)(color_value / 2); + color->color_g_y = (uint16_t)(color_value / 2); } } @@ -454,7 +455,7 @@ void get_smartmux_visual_confirm_color( *color = sm_ver_colors[dc->config.smart_mux_version]; } else { /* dGPU driving the eDP - red */ - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; color->color_g_y = 0; color->color_b_cb = 0; } @@ -476,19 +477,19 @@ void get_vabc_visual_confirm_color( if (edp_link) { switch (edp_link->backlight_control_type) { case BACKLIGHT_CONTROL_PWM: - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; color->color_g_y = 0; color->color_b_cb = 0; break; case BACKLIGHT_CONTROL_AMD_AUX: color->color_r_cr = 0; - color->color_g_y = color_value; + color->color_g_y = (uint16_t)color_value; color->color_b_cb = 0; break; case BACKLIGHT_CONTROL_VESA_AUX: color->color_r_cr = 0; color->color_g_y = 0; - color->color_b_cb = color_value; + color->color_b_cb = (uint16_t)color_value; break; } } else { @@ -506,19 +507,19 @@ void get_subvp_visual_confirm_color( if (pipe_ctx) { switch (pipe_ctx->p_state_type) { case P_STATE_SUB_VP: - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; color->color_g_y = 0; color->color_b_cb = 0; break; case P_STATE_DRR_SUB_VP: color->color_r_cr = 0; - color->color_g_y = color_value; + color->color_g_y = (uint16_t)color_value; color->color_b_cb = 0; break; case P_STATE_V_BLANK_SUB_VP: color->color_r_cr = 0; color->color_g_y = 0; - color->color_b_cb = color_value; + color->color_b_cb = (uint16_t)color_value; break; default: break; @@ -535,34 +536,34 @@ void get_mclk_switch_visual_confirm_color( if (pipe_ctx) { switch (pipe_ctx->p_state_type) { case P_STATE_V_BLANK: - color->color_r_cr = color_value; - color->color_g_y = color_value; + color->color_r_cr = (uint16_t)color_value; + color->color_g_y = (uint16_t)color_value; color->color_b_cb = 0; break; case P_STATE_FPO: color->color_r_cr = 0; - color->color_g_y = color_value; - color->color_b_cb = color_value; + color->color_g_y = (uint16_t)color_value; + color->color_b_cb = (uint16_t)color_value; break; case P_STATE_V_ACTIVE: - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; color->color_g_y = 0; - color->color_b_cb = color_value; + color->color_b_cb = (uint16_t)color_value; break; case P_STATE_SUB_VP: - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; color->color_g_y = 0; color->color_b_cb = 0; break; case P_STATE_DRR_SUB_VP: color->color_r_cr = 0; - color->color_g_y = color_value; + color->color_g_y = (uint16_t)color_value; color->color_b_cb = 0; break; case P_STATE_V_BLANK_SUB_VP: color->color_r_cr = 0; color->color_g_y = 0; - color->color_b_cb = color_value; + color->color_b_cb = (uint16_t)color_value; break; default: break; @@ -577,13 +578,13 @@ void get_cursor_visual_confirm_color( uint32_t color_value = MAX_TG_COLOR_VALUE; if (pipe_ctx->stream && pipe_ctx->stream->cursor_position.enable) { - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; color->color_g_y = 0; color->color_b_cb = 0; } else { color->color_r_cr = 0; color->color_g_y = 0; - color->color_b_cb = color_value; + color->color_b_cb = (uint16_t)color_value; } } @@ -665,7 +666,7 @@ void set_p_state_switch_method( /* SubVP */ enable_subvp = false; - for (int i = 0; i < dc->res_pool->pipe_count; i++) { + for (unsigned int i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; if (pipe->stream && dc_state_get_paired_subvp_stream(context, pipe->stream) && @@ -721,9 +722,9 @@ void get_fams2_visual_confirm_color( /* driver only handles visual confirm when FAMS2 is disabled */ if (!dc_state_is_fams2_in_use(dc, context)) { /* when FAMS2 is disabled, all pipes are grey */ - color->color_g_y = color_value / 2; - color->color_b_cb = color_value / 2; - color->color_r_cr = color_value / 2; + color->color_g_y = (uint16_t)(color_value / 2); + color->color_b_cb = (uint16_t)(color_value / 2); + color->color_r_cr = (uint16_t)(color_value / 2); } } @@ -789,8 +790,241 @@ void hwss_build_fast_sequence(struct dc *dc, (*num_steps)++; } + if (dc->hwss.setup_periodic_interrupt && stream->update_flags.bits.periodic_interrupt) { + block_sequence[*num_steps].params.setup_periodic_interrupt_params.dc = dc; + block_sequence[*num_steps].params.setup_periodic_interrupt_params.pipe_ctx = pipe_ctx; + block_sequence[*num_steps].func = HWSS_SETUP_PERIODIC_INTERRUPT; + (*num_steps)++; + } + + if (stream->update_flags.bits.info_frame) { + resource_build_info_frame(pipe_ctx); + block_sequence[*num_steps].params.update_info_frame_params.dc = dc; + block_sequence[*num_steps].params.update_info_frame_params.pipe_ctx = pipe_ctx; + block_sequence[*num_steps].func = HWSS_UPDATE_INFO_FRAME; + (*num_steps)++; + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) { + block_sequence[*num_steps].params.dp_trace_source_sequence_params.link = pipe_ctx->stream->link; + block_sequence[*num_steps].params.dp_trace_source_sequence_params.source = DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME; + block_sequence[*num_steps].func = DP_TRACE_SOURCE_SEQUENCE; + (*num_steps)++; + } + } + + if (dc->hwss.set_dmdata_attributes && stream->update_flags.bits.dmdata && + stream->use_dynamic_meta && pipe_ctx->stream->dmdata_address.quad_part != 0) { + struct dc_dmdata_attributes attr = { 0 }; + + attr.dmdata_mode = DMDATA_HW_MODE; + attr.dmdata_size = dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; + attr.address.quad_part = pipe_ctx->stream->dmdata_address.quad_part; + attr.dmdata_dl_delta = 0; + attr.dmdata_qos_mode = 0; + attr.dmdata_qos_level = 0; + attr.dmdata_repeat = 1; /* always repeat */ + attr.dmdata_updated = 1; + attr.dmdata_sw_data = NULL; + + block_sequence[*num_steps].params.set_dmdata_attributes_params.hubp = pipe_ctx->plane_res.hubp; + block_sequence[*num_steps].params.set_dmdata_attributes_params.attr = attr; + block_sequence[*num_steps].func = HUBP_SET_DMDATA_ATTRIBUTES; + (*num_steps)++; + } + + /* Track cursor lock state - separate locks for attribute and position updates */ + bool enable_cursor_offload = false; + + if ((dc->hwss.set_cursor_attribute && stream->update_flags.bits.cursor_attr) || + (dc->hwss.set_cursor_position && stream->update_flags.bits.cursor_pos)) + enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); + + /* Cursor attribute updates - separate lock/iterate/unlock */ + if (dc->hwss.set_cursor_attribute && stream->update_flags.bits.cursor_attr) { + struct pipe_ctx *cursor_pipe_to_program = NULL; + + for (i = 0; i < MAX_PIPES; i++) { + current_pipe = &context->res_ctx.pipe_ctx[i]; + + if (current_pipe->stream != stream) + continue; + + if (!cursor_pipe_to_program) { + cursor_pipe_to_program = current_pipe; + + if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) { + block_sequence[*num_steps].params.begin_cursor_offload_update_params.dc = dc; + block_sequence[*num_steps].params.begin_cursor_offload_update_params.pipe_ctx = + current_pipe; + block_sequence[*num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE; + (*num_steps)++; + } else { + block_sequence[*num_steps].params.cursor_lock_params.dc = dc; + block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = current_pipe; + block_sequence[*num_steps].params.cursor_lock_params.lock = true; + block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; + (*num_steps)++; + + if (current_pipe->next_odm_pipe) { + block_sequence[*num_steps].params.cursor_lock_params.dc = dc; + block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = + current_pipe->next_odm_pipe; + block_sequence[*num_steps].params.cursor_lock_params.lock = true; + block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; + (*num_steps)++; + } + } + } + + block_sequence[*num_steps].params.hubp_set_cursor_attributes_params.hubp = + current_pipe->plane_res.hubp; + block_sequence[*num_steps].params.hubp_set_cursor_attributes_params.attributes = + ¤t_pipe->stream->cursor_attributes; + block_sequence[*num_steps].func = HUBP_SET_CURSOR_ATTRIBUTES; + (*num_steps)++; + + block_sequence[*num_steps].params.dpp_set_cursor_attributes_params.dpp = + current_pipe->plane_res.dpp; + block_sequence[*num_steps].params.dpp_set_cursor_attributes_params.attributes = + ¤t_pipe->stream->cursor_attributes; + block_sequence[*num_steps].func = DPP_SET_CURSOR_ATTRIBUTES; + (*num_steps)++; + + if (dc->ctx->dmub_srv) { + block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx = + current_pipe; + block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_idx = + current_pipe->pipe_idx; + block_sequence[*num_steps].func = DC_SEND_CURSOR_INFO_TO_DMU; + (*num_steps)++; + } + + block_sequence[*num_steps].params.set_cursor_sdr_white_level_params.dc = dc; + block_sequence[*num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx = + current_pipe; + block_sequence[*num_steps].func = SET_CURSOR_SDR_WHITE_LEVEL; + (*num_steps)++; + + if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) { + block_sequence[*num_steps].params.update_cursor_offload_pipe_params.dc = dc; + block_sequence[*num_steps].params.update_cursor_offload_pipe_params.pipe_ctx = + current_pipe; + block_sequence[*num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE; + (*num_steps)++; + } + } + + /* Unlock cursor attributes after all pipes have been programmed */ + if (cursor_pipe_to_program) { + if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) { + block_sequence[*num_steps].params.commit_cursor_offload_update_params.dc = dc; + block_sequence[*num_steps].params.commit_cursor_offload_update_params.pipe_ctx = + cursor_pipe_to_program; + block_sequence[*num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE; + (*num_steps)++; + } else { + block_sequence[*num_steps].params.cursor_lock_params.dc = dc; + block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = cursor_pipe_to_program; + block_sequence[*num_steps].params.cursor_lock_params.lock = false; + block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; + (*num_steps)++; + + if (cursor_pipe_to_program->next_odm_pipe) { + block_sequence[*num_steps].params.cursor_lock_params.dc = dc; + block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = + cursor_pipe_to_program->next_odm_pipe; + block_sequence[*num_steps].params.cursor_lock_params.lock = false; + block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; + (*num_steps)++; + } + } + } + } + + /* Cursor position updates */ + if (dc->hwss.set_cursor_position && stream->update_flags.bits.cursor_pos) { + struct pipe_ctx *cursor_pipe_to_program = NULL; + + for (i = 0; i < MAX_PIPES; i++) { + current_pipe = &context->res_ctx.pipe_ctx[i]; + + if (current_pipe->stream != stream || + (!current_pipe->plane_res.mi && !current_pipe->plane_res.hubp) || + !current_pipe->plane_state || + (!current_pipe->plane_res.xfm && !current_pipe->plane_res.dpp) || + (!current_pipe->plane_res.ipp && !current_pipe->plane_res.dpp)) + continue; + + if (!cursor_pipe_to_program) { + cursor_pipe_to_program = current_pipe; + + if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) { + block_sequence[*num_steps].params.begin_cursor_offload_update_params.dc = dc; + block_sequence[*num_steps].params.begin_cursor_offload_update_params.pipe_ctx = + current_pipe; + block_sequence[*num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE; + (*num_steps)++; + } else { + block_sequence[*num_steps].params.cursor_lock_params.dc = dc; + block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = current_pipe; + block_sequence[*num_steps].params.cursor_lock_params.lock = true; + block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; + (*num_steps)++; + } + } + + block_sequence[*num_steps].params.set_cursor_position_params.dc = dc; + block_sequence[*num_steps].params.set_cursor_position_params.pipe_ctx = current_pipe; + block_sequence[*num_steps].func = SET_CURSOR_POSITION; + (*num_steps)++; + + if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) { + block_sequence[*num_steps].params.update_cursor_offload_pipe_params.dc = dc; + block_sequence[*num_steps].params.update_cursor_offload_pipe_params.pipe_ctx = + current_pipe; + block_sequence[*num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE; + (*num_steps)++; + } + + if (dc->ctx->dmub_srv) { + block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx = + current_pipe; + block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_idx = + current_pipe->pipe_idx; + block_sequence[*num_steps].func = DC_SEND_CURSOR_INFO_TO_DMU; + (*num_steps)++; + } + } + + /* Unlock cursor position after all pipes have been programmed */ + if (cursor_pipe_to_program) { + if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) { + block_sequence[*num_steps].params.commit_cursor_offload_update_params.dc = dc; + block_sequence[*num_steps].params.commit_cursor_offload_update_params.pipe_ctx = + cursor_pipe_to_program; + block_sequence[*num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE; + (*num_steps)++; + } else { + block_sequence[*num_steps].params.cursor_lock_params.dc = dc; + block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = cursor_pipe_to_program; + block_sequence[*num_steps].params.cursor_lock_params.lock = false; + block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; + (*num_steps)++; + } + } + } + current_pipe = pipe_ctx; while (current_pipe) { + if (current_pipe->stream->update_flags.bits.dither) { + resource_build_bit_depth_reduction_params(current_pipe->stream, ¤t_pipe->stream->bit_depth_params); + block_sequence[*num_steps].params.opp_program_fmt_params.opp = current_pipe->stream_res.opp; + block_sequence[*num_steps].params.opp_program_fmt_params.fmt_bit_depth = ¤t_pipe->stream->bit_depth_params; + block_sequence[*num_steps].params.opp_program_fmt_params.clamping = ¤t_pipe->stream->clamping; + block_sequence[*num_steps].func = OPP_PROGRAM_FMT; + (*num_steps)++; + } + current_mpc_pipe = current_pipe; while (current_mpc_pipe) { if (current_mpc_pipe->plane_state) { @@ -823,6 +1057,18 @@ void hwss_build_fast_sequence(struct dc *dc, (*num_steps)++; } + if (current_mpc_pipe->plane_state->update_flags.bits.lut_3d && + current_mpc_pipe->plane_state->mcm_luts.lut3d_data.lut3d_src == + DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM && + current_mpc_pipe->plane_state->mcm_shaper_3dlut_setting == + DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT && + current_mpc_pipe->plane_res.hubp->funcs->hubp_enable_3dlut_fl) { + block_sequence[*num_steps].params.hubp_enable_3dlut_fl_params.hubp = + current_mpc_pipe->plane_res.hubp; + block_sequence[*num_steps].func = HUBP_ENABLE_3DLUT_FL; + (*num_steps)++; + } + if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) { block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc; block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe; @@ -831,7 +1077,9 @@ void hwss_build_fast_sequence(struct dc *dc, (*num_steps)++; } - if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change) { + if (dc->hwss.program_gamut_remap && + (current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change || + current_mpc_pipe->stream->update_flags.bits.gamut_remap)) { block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe; block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP; (*num_steps)++; @@ -856,6 +1104,16 @@ void hwss_build_fast_sequence(struct dc *dc, block_sequence[*num_steps].func = DPP_PROGRAM_CM_HIST; (*num_steps)++; } + + if (current_mpc_pipe->plane_res.dpp && + current_mpc_pipe->plane_res.dpp->funcs->set_cursor_matrix && + current_mpc_pipe->plane_state->update_flags.bits.cursor_csc_color_matrix_change) { + block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.dpp = current_mpc_pipe->plane_res.dpp; + block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.color_space = current_mpc_pipe->plane_state->color_space; + block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.cursor_csc_color_matrix = ¤t_mpc_pipe->plane_state->cursor_csc_color_matrix; + block_sequence[*num_steps].func = DPP_SET_CURSOR_MATRIX; + (*num_steps)++; + } } if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) { block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc; @@ -953,7 +1211,7 @@ void hwss_execute_sequence(struct dc *dc, struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], int num_steps) { - unsigned int i; + int i; union block_sequence_params *params; struct dce_hwseq *hws = dc->hwseq; @@ -989,7 +1247,22 @@ void hwss_execute_sequence(struct dc *dc, params->set_input_transfer_func_params.plane_state); break; case DPP_PROGRAM_GAMUT_REMAP: - dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx); + hwss_program_gamut_remap(params); + break; + case HUBP_ENABLE_3DLUT_FL: + hwss_hubp_enable_3dlut_fl(params); + break; + case OTG_SETUP_VERTICAL_INTERRUPT: + hwss_tg_setup_vertical_interrupt0(params); + break; + case HWSS_SETUP_PERIODIC_INTERRUPT: + hwss_setup_periodic_interrupt(dc, params); + break; + case HWSS_UPDATE_INFO_FRAME: + hwss_update_info_frame(dc, params); + break; + case HUBP_SET_DMDATA_ATTRIBUTES: + hwss_set_dmdata_attributes(params); break; case DPP_SETUP_DPP: hwss_setup_dpp(params); @@ -1311,9 +1584,30 @@ void hwss_execute_sequence(struct dc *dc, case ABORT_CURSOR_OFFLOAD_UPDATE: hwss_abort_cursor_offload_update(params); break; + case HWSS_CURSOR_LOCK: + hwss_cursor_lock(params); + break; + case HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE: + hwss_begin_cursor_offload_update(params); + break; + case HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE: + hwss_commit_cursor_offload_update(params); + break; + case HWSS_UPDATE_CURSOR_OFFLOAD_PIPE: + hwss_update_cursor_offload_pipe(params); + break; + case DC_SEND_CURSOR_INFO_TO_DMU: + hwss_send_cursor_info_to_dmu(params); + break; case SET_CURSOR_ATTRIBUTE: hwss_set_cursor_attribute(params); break; + case HUBP_SET_CURSOR_ATTRIBUTES: + hwss_hubp_set_cursor_attributes(params); + break; + case DPP_SET_CURSOR_ATTRIBUTES: + hwss_dpp_set_cursor_attributes(params); + break; case SET_CURSOR_POSITION: hwss_set_cursor_position(params); break; @@ -1329,6 +1623,57 @@ void hwss_execute_sequence(struct dc *dc, case PHANTOM_HUBP_POST_ENABLE: hwss_phantom_hubp_post_enable(params); break; + case STREAM_ENC_UPDATE_HDMI_INFO_PACKETS: + hwss_stream_enc_update_hdmi_info_packets(params); + break; + case HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM: + hwss_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(params); + break; + case HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS: + hwss_hpo_dp_stream_enc_update_dp_info_packets(params); + break; + case STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM: + hwss_stream_enc_update_dp_info_packets_sdp_line_num(params); + break; + case STREAM_ENC_UPDATE_DP_INFO_PACKETS: + hwss_stream_enc_update_dp_info_packets(params); + break; + case DSC_SET_CONFIG_SIMPLE: + hwss_dsc_set_config_simple(params); + break; + case STREAM_ENC_DP_SET_DSC_CONFIG: + hwss_stream_enc_dp_set_dsc_config(params); + break; + case HPO_DP_STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET: + hwss_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(params); + break; + case STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET: + hwss_stream_enc_dp_set_dsc_pps_info_packet(params); + break; + case DP_TRACE_SOURCE_SEQUENCE: + hwss_dp_trace_source_sequence(params); + break; + case LINK_INCREASE_MST_PAYLOAD: + hwss_link_increase_mst_payload(params); + break; + case LINK_REDUCE_MST_PAYLOAD: + hwss_link_reduce_mst_payload(params); + break; + case DP_SET_TEST_PATTERN: + hwss_dp_set_test_pattern(params); + break; + case LINK_SET_DPMS_OFF: + hwss_link_set_dpms_off(params); + break; + case DISABLE_AUDIO_STREAM: + hwss_disable_audio_stream(dc, params); + break; + case PREPARE_BANDWIDTH: + hwss_prepare_bandwidth(dc, params); + break; + case LINK_SET_DPMS_ON: + hwss_link_set_dpms_on(params); + break; default: ASSERT(false); break; @@ -1732,6 +2077,21 @@ void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state, } } +/* + * Helper function to add OTG setup vertical interrupt0 to block sequence + */ +void hwss_add_vertical_interrupt_setup(struct block_sequence_state *seq_state, + struct timing_generator *tg, uint32_t start_line, uint32_t end_line) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt0_params.tg = tg; + seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt0_params.start_line = start_line; + seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt0_params.end_line = end_line; + seq_state->steps[*seq_state->num_steps].func = OTG_SETUP_VERTICAL_INTERRUPT; + (*seq_state->num_steps)++; + } +} + /* * Helper function to add TG setup vertical interrupt2 to block sequence */ @@ -1947,6 +2307,16 @@ void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_sta } } +void hwss_add_hubp_enable_3dlut_fl(struct block_sequence_state *seq_state, + struct hubp *hubp) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.hubp_enable_3dlut_fl_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].func = HUBP_ENABLE_3DLUT_FL; + (*seq_state->num_steps)++; + } +} + void hwss_program_manual_trigger(union block_sequence_params *params) { struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx; @@ -2091,7 +2461,7 @@ void get_surface_tile_visual_confirm_color( switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { case DC_SW_LINEAR: /* LINEAR Surface - set border color to red */ - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; break; default: break; @@ -2180,7 +2550,7 @@ void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_con * operations to complete. It should be invoked as a pre-amble prior * to full update programming before asserting any HW locks. */ - int pipe_idx; + unsigned int pipe_idx; int opp_inst; int opp_count = dc->res_pool->res_cap->num_opp; struct hubp *hubp; @@ -2416,6 +2786,40 @@ void hwss_tg_set_vtg_params(union block_sequence_params *params) tg->funcs->set_vtg_params(tg, timing, program_fp2); } +void hwss_hubp_enable_3dlut_fl(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_enable_3dlut_fl_params.hubp; + + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, true); +} + +void hwss_update_info_frame(struct dc *dc, union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->update_info_frame_params.pipe_ctx; + + if (dc->hwss.update_info_frame) + dc->hwss.update_info_frame(pipe_ctx); +} + +void hwss_setup_periodic_interrupt(struct dc *dc, union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->setup_periodic_interrupt_params.pipe_ctx; + + if (dc->hwss.setup_periodic_interrupt) + dc->hwss.setup_periodic_interrupt(dc, pipe_ctx); +} + +void hwss_tg_setup_vertical_interrupt0(union block_sequence_params *params) +{ + struct timing_generator *tg = params->tg_setup_vertical_interrupt0_params.tg; + uint32_t start_line = params->tg_setup_vertical_interrupt0_params.start_line; + uint32_t end_line = params->tg_setup_vertical_interrupt0_params.end_line; + + if (tg->funcs->setup_vertical_interrupt0) + tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line); +} + void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params) { struct timing_generator *tg = params->tg_setup_vertical_interrupt2_params.tg; @@ -2615,7 +3019,7 @@ void hwss_hubp_wait_flip_pending(union block_sequence_params *params) struct hubp *hubp = params->hubp_wait_flip_pending_params.hubp; unsigned int timeout_us = params->hubp_wait_flip_pending_params.timeout_us; unsigned int polling_interval_us = params->hubp_wait_flip_pending_params.polling_interval_us; - int j = 0; + unsigned int j = 0; for (j = 0; j < timeout_us / polling_interval_us && hubp->funcs->hubp_is_flip_pending(hubp); j++) @@ -2627,7 +3031,7 @@ void hwss_tg_wait_double_buffer_pending(union block_sequence_params *params) struct timing_generator *tg = params->tg_wait_double_buffer_pending_params.tg; unsigned int timeout_us = params->tg_wait_double_buffer_pending_params.timeout_us; unsigned int polling_interval_us = params->tg_wait_double_buffer_pending_params.polling_interval_us; - int j = 0; + unsigned int j = 0; if (tg->funcs->get_optc_double_buffer_pending) { for (j = 0; j < timeout_us / polling_interval_us @@ -3113,6 +3517,51 @@ void hwss_abort_cursor_offload_update(union block_sequence_params *params) dc->hwss.abort_cursor_offload_update(dc, pipe_ctx); } +void hwss_cursor_lock(union block_sequence_params *params) +{ + struct dc *dc = params->cursor_lock_params.dc; + struct pipe_ctx *pipe_ctx = params->cursor_lock_params.pipe_ctx; + bool lock = params->cursor_lock_params.lock; + + if (dc && dc->hwss.cursor_lock) + dc->hwss.cursor_lock(dc, pipe_ctx, lock); +} + +void hwss_begin_cursor_offload_update(union block_sequence_params *params) +{ + struct dc *dc = params->begin_cursor_offload_update_params.dc; + struct pipe_ctx *pipe_ctx = params->begin_cursor_offload_update_params.pipe_ctx; + + if (dc && dc->hwss.begin_cursor_offload_update) + dc->hwss.begin_cursor_offload_update(dc, pipe_ctx); +} + +void hwss_commit_cursor_offload_update(union block_sequence_params *params) +{ + struct dc *dc = params->commit_cursor_offload_update_params.dc; + struct pipe_ctx *pipe_ctx = params->commit_cursor_offload_update_params.pipe_ctx; + + if (dc && dc->hwss.commit_cursor_offload_update) + dc->hwss.commit_cursor_offload_update(dc, pipe_ctx); +} + +void hwss_update_cursor_offload_pipe(union block_sequence_params *params) +{ + struct dc *dc = params->update_cursor_offload_pipe_params.dc; + struct pipe_ctx *pipe_ctx = params->update_cursor_offload_pipe_params.pipe_ctx; + + if (dc && dc->hwss.update_cursor_offload_pipe) + dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx); +} + +void hwss_send_cursor_info_to_dmu(union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->send_cursor_info_to_dmu_params.pipe_ctx; + int pipe_idx = params->send_cursor_info_to_dmu_params.pipe_idx; + + dc_send_update_cursor_info_to_dmu(pipe_ctx, (uint8_t)pipe_idx); +} + void hwss_set_cursor_attribute(union block_sequence_params *params) { struct dc *dc = params->set_cursor_attribute_params.dc; @@ -3122,6 +3571,24 @@ void hwss_set_cursor_attribute(union block_sequence_params *params) dc->hwss.set_cursor_attribute(pipe_ctx); } +void hwss_hubp_set_cursor_attributes(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_set_cursor_attributes_params.hubp; + const struct dc_cursor_attributes *attributes = params->hubp_set_cursor_attributes_params.attributes; + + if (hubp && hubp->funcs->set_cursor_attributes) + hubp->funcs->set_cursor_attributes(hubp, attributes); +} + +void hwss_dpp_set_cursor_attributes(union block_sequence_params *params) +{ + struct dpp *dpp = params->dpp_set_cursor_attributes_params.dpp; + struct dc_cursor_attributes *attributes = params->dpp_set_cursor_attributes_params.attributes; + + if (dpp && dpp->funcs->set_cursor_attributes) + dpp->funcs->set_cursor_attributes(dpp, attributes); +} + void hwss_set_cursor_position(union block_sequence_params *params) { struct dc *dc = params->set_cursor_position_params.dc; @@ -3140,6 +3607,14 @@ void hwss_set_cursor_sdr_white_level(union block_sequence_params *params) dc->hwss.set_cursor_sdr_white_level(pipe_ctx); } +void hwss_program_gamut_remap(union block_sequence_params *params) +{ + struct dc *dc = params->program_gamut_remap_params.pipe_ctx->stream->ctx->dc; + + if (dc && dc->hwss.program_gamut_remap) + dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx); +} + void hwss_program_output_csc(union block_sequence_params *params) { struct dc *dc = params->program_output_csc_params.dc; @@ -3169,6 +3644,198 @@ void hwss_phantom_hubp_post_enable(union block_sequence_params *params) hubp->funcs->phantom_hubp_post_enable(hubp); } +void hwss_stream_enc_update_hdmi_info_packets(union block_sequence_params *params) +{ + if (params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc && + params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets) + params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( + params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc, + ¶ms->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.encoder_info_frame); +} + +void hwss_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(union block_sequence_params *params) +{ + if (params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc && + params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num) + params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num( + params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc, + ¶ms->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.encoder_info_frame); +} + +void hwss_hpo_dp_stream_enc_update_dp_info_packets(union block_sequence_params *params) +{ + if (params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc && + params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets) + params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets( + params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc, + ¶ms->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.encoder_info_frame); +} + +void hwss_stream_enc_update_dp_info_packets_sdp_line_num(union block_sequence_params *params) +{ + if (params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc && + params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) + params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( + params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc, + ¶ms->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.encoder_info_frame); +} + +void hwss_stream_enc_update_dp_info_packets(union block_sequence_params *params) +{ + if (params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc && + params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets) + params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( + params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc, + ¶ms->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.encoder_info_frame); +} + +void hwss_stream_enc_dp_set_dsc_config(union block_sequence_params *params) +{ + if (params->stream_enc_dp_set_dsc_config_params.stream_enc && + params->stream_enc_dp_set_dsc_config_params.stream_enc->funcs->dp_set_dsc_config) { + enum optc_dsc_mode dsc_mode = OPTC_DSC_DISABLED; + uint32_t dsc_bytes_per_pixel = 0; + uint32_t dsc_slice_width = 0; + const struct dsc_optc_config *dsc_optc_cfg = params->stream_enc_dp_set_dsc_config_params.dsc_optc_cfg; + + if (dsc_optc_cfg) { + dsc_mode = dsc_optc_cfg->is_pixel_format_444 ? + OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; + dsc_bytes_per_pixel = dsc_optc_cfg->bytes_per_pixel; + dsc_slice_width = dsc_optc_cfg->slice_width; + } + + params->stream_enc_dp_set_dsc_config_params.stream_enc->funcs->dp_set_dsc_config( + params->stream_enc_dp_set_dsc_config_params.stream_enc, + dsc_mode, dsc_bytes_per_pixel, dsc_slice_width); + } +} + +void hwss_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(union block_sequence_params *params) +{ + if (params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc && + params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet) + params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( + params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc, + params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.immediate_update, + params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.dsc_packed_pps, + params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.pps_sdp_stream); +} + +void hwss_stream_enc_dp_set_dsc_pps_info_packet(union block_sequence_params *params) +{ + if (params->stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc && + params->stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc->funcs->dp_set_dsc_pps_info_packet) + params->stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc->funcs->dp_set_dsc_pps_info_packet( + params->stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc, + params->stream_enc_dp_set_dsc_pps_info_packet_params.immediate_update, + params->stream_enc_dp_set_dsc_pps_info_packet_params.dsc_packed_pps, + params->stream_enc_dp_set_dsc_pps_info_packet_params.pps_sdp_stream); +} + +void hwss_set_dmdata_attributes(union block_sequence_params *params) +{ + struct hubp *hubp = params->set_dmdata_attributes_params.hubp; + + if (!hubp || !hubp->funcs->dmdata_set_attributes) + return; + + hubp->funcs->dmdata_set_attributes(hubp, + ¶ms->set_dmdata_attributes_params.attr); +} + +void hwss_dp_trace_source_sequence(union block_sequence_params *params) +{ + struct dc_link *link = params->dp_trace_source_sequence_params.link; + enum dpcd_source_sequence source = params->dp_trace_source_sequence_params.source; + + if (link && link->dc && link->dc->link_srv && link->dc->link_srv->dp_trace_source_sequence) + link->dc->link_srv->dp_trace_source_sequence(link, source); +} + +void hwss_link_increase_mst_payload(union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->link_increase_mst_payload_params.pipe_ctx; + uint32_t mst_stream_bw = params->link_increase_mst_payload_params.mst_stream_bw; + + if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link && + pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv && + pipe_ctx->stream->link->dc->link_srv->increase_mst_payload) + pipe_ctx->stream->link->dc->link_srv->increase_mst_payload(pipe_ctx, mst_stream_bw); +} + +void hwss_link_reduce_mst_payload(union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->link_reduce_mst_payload_params.pipe_ctx; + uint32_t mst_stream_bw = params->link_reduce_mst_payload_params.mst_stream_bw; + + if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link && + pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv && + pipe_ctx->stream->link->dc->link_srv->reduce_mst_payload) + pipe_ctx->stream->link->dc->link_srv->reduce_mst_payload(pipe_ctx, mst_stream_bw); +} + +void hwss_dp_set_test_pattern(union block_sequence_params *params) +{ + struct dc_link *link = params->dp_set_test_pattern_params.link; + enum dp_test_pattern test_pattern = params->dp_set_test_pattern_params.test_pattern; + enum dp_test_pattern_color_space test_pattern_color_space = + params->dp_set_test_pattern_params.test_pattern_color_space; + const struct link_training_settings *p_link_settings = + params->dp_set_test_pattern_params.p_link_settings; + const unsigned char *p_custom_pattern = params->dp_set_test_pattern_params.p_custom_pattern; + unsigned int cust_pattern_size = params->dp_set_test_pattern_params.cust_pattern_size; + + if (link && link->dc && link->dc->link_srv && link->dc->link_srv->dp_set_test_pattern) + link->dc->link_srv->dp_set_test_pattern(link, test_pattern, test_pattern_color_space, + p_link_settings, p_custom_pattern, cust_pattern_size); +} + +void hwss_link_set_dpms_off(union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->link_set_dpms_off_params.pipe_ctx; + + if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link && + pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv && + pipe_ctx->stream->link->dc->link_srv->set_dpms_off) + pipe_ctx->stream->link->dc->link_srv->set_dpms_off(pipe_ctx); +} + +void hwss_disable_audio_stream(struct dc *dc, union block_sequence_params *params) +{ + if (dc->hwss.disable_audio_stream) + dc->hwss.disable_audio_stream( + params->disable_audio_stream_params.pipe_ctx); +} + +void hwss_prepare_bandwidth(struct dc *dc, union block_sequence_params *params) +{ + if (dc && dc->hwss.prepare_bandwidth) + dc->hwss.prepare_bandwidth(dc, + params->prepare_bandwidth_params.context); +} + +void hwss_link_set_dpms_on(union block_sequence_params *params) +{ + struct dc_state *state = params->link_set_dpms_on_params.state; + struct pipe_ctx *pipe_ctx = params->link_set_dpms_on_params.pipe_ctx; + + if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link && + pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv && + pipe_ctx->stream->link->dc->link_srv->set_dpms_on) + pipe_ctx->stream->link->dc->link_srv->set_dpms_on(state, pipe_ctx); +} + +void hwss_dsc_set_config_simple(union block_sequence_params *params) +{ + struct display_stream_compressor *dsc = params->dsc_set_config_simple_params.dsc; + struct dsc_config *dsc_cfg = ¶ms->dsc_set_config_simple_params.dsc_cfg; + struct dsc_optc_config *dsc_optc_cfg = ¶ms->dsc_set_config_simple_params.dsc_optc_cfg; + + if (dsc && dsc->funcs && dsc->funcs->dsc_set_config) + dsc->funcs->dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg); +} + void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state, struct dccg *dccg, int inst, int num_slices_h) { @@ -4009,6 +4676,30 @@ void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state, } } +void hwss_add_hubp_set_cursor_attributes(struct block_sequence_state *seq_state, + struct hubp *hubp, + const struct dc_cursor_attributes *attributes) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_CURSOR_ATTRIBUTES; + seq_state->steps[*seq_state->num_steps].params.hubp_set_cursor_attributes_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_set_cursor_attributes_params.attributes = attributes; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dpp_set_cursor_attributes(struct block_sequence_state *seq_state, + struct dpp *dpp, + struct dc_cursor_attributes *attributes) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DPP_SET_CURSOR_ATTRIBUTES; + seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_attributes_params.dpp = dpp; + seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_attributes_params.attributes = attributes; + (*seq_state->num_steps)++; + } +} + void hwss_add_set_cursor_position(struct block_sequence_state *seq_state, struct dc *dc, struct pipe_ctx *pipe_ctx) @@ -4109,6 +4800,313 @@ void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state, } } +void hwss_add_begin_cursor_offload_update(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE; + seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_cursor_lock(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx, + bool lock) +{ + /* cursor lock is per MPCC tree, so only need to lock one pipe per stream */ + if (!pipe_ctx || pipe_ctx->top_pipe) + return; + + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HWSS_CURSOR_LOCK; + seq_state->steps[*seq_state->num_steps].params.cursor_lock_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.cursor_lock_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].params.cursor_lock_params.lock = lock; + (*seq_state->num_steps)++; + } +} + +void hwss_add_send_update_cursor_info_to_dmu(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, + int index) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DC_SEND_CURSOR_INFO_TO_DMU; + seq_state->steps[*seq_state->num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].params.send_cursor_info_to_dmu_params.pipe_idx = index; + (*seq_state->num_steps)++; + } +} + +void hwss_add_update_cursor_offload_pipe(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE; + seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_commit_cursor_offload_update(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE; + seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_stream_enc_update_hdmi_info_packets(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_UPDATE_HDMI_INFO_PACKETS; + seq_state->steps[*seq_state->num_steps].params.stream_enc_update_hdmi_info_packets_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM; + seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_hpo_dp_stream_enc_update_dp_info_packets(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS; + seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_stream_enc_update_dp_info_packets_sdp_line_num(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM; + seq_state->steps[*seq_state->num_steps].params.stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_stream_enc_update_dp_info_packets(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_UPDATE_DP_INFO_PACKETS; + seq_state->steps[*seq_state->num_steps].params.stream_enc_update_dp_info_packets_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dsc_set_config(struct block_sequence_state *seq_state, + struct display_stream_compressor *dsc, + const struct dsc_config *dsc_cfg, + const struct dsc_optc_config *dsc_optc_cfg) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DSC_SET_CONFIG_SIMPLE; + seq_state->steps[*seq_state->num_steps].params.dsc_set_config_simple_params.dsc = dsc; + seq_state->steps[*seq_state->num_steps].params.dsc_set_config_simple_params.dsc_cfg = *dsc_cfg; + seq_state->steps[*seq_state->num_steps].params.dsc_set_config_simple_params.dsc_optc_cfg = *dsc_optc_cfg; + (*seq_state->num_steps)++; + } +} + +void hwss_add_stream_enc_dp_set_dsc_config(struct block_sequence_state *seq_state, + struct stream_encoder *stream_enc, + const struct dsc_optc_config *dsc_optc_cfg) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_DP_SET_DSC_CONFIG; + seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_config_params.stream_enc = stream_enc; + seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_config_params.dsc_optc_cfg = dsc_optc_cfg; + (*seq_state->num_steps)++; + } +} + +void hwss_add_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(struct block_sequence_state *seq_state, + struct hpo_dp_stream_encoder *hpo_dp_stream_enc, + bool immediate_update, + uint8_t *dsc_packed_pps, + bool pps_sdp_stream) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HPO_DP_STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET; + seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc = hpo_dp_stream_enc; + seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.immediate_update = immediate_update; + seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.dsc_packed_pps = dsc_packed_pps; + seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.pps_sdp_stream = pps_sdp_stream; + (*seq_state->num_steps)++; + } +} + +void hwss_add_stream_enc_dp_set_dsc_pps_info_packet(struct block_sequence_state *seq_state, + struct stream_encoder *stream_enc, + bool immediate_update, + uint8_t *dsc_packed_pps, + bool pps_sdp_stream) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET; + seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc = stream_enc; + seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.immediate_update = immediate_update; + seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.dsc_packed_pps = dsc_packed_pps; + seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.pps_sdp_stream = pps_sdp_stream; + (*seq_state->num_steps)++; + } +} + +void hwss_add_setup_periodic_interrupt(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HWSS_SETUP_PERIODIC_INTERRUPT; + seq_state->steps[*seq_state->num_steps].params.setup_periodic_interrupt_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.setup_periodic_interrupt_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dp_trace_source_sequence(struct block_sequence_state *seq_state, + struct dc_link *link, + enum dpcd_source_sequence source) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DP_TRACE_SOURCE_SEQUENCE; + seq_state->steps[*seq_state->num_steps].params.dp_trace_source_sequence_params.link = link; + seq_state->steps[*seq_state->num_steps].params.dp_trace_source_sequence_params.source = source; + (*seq_state->num_steps)++; + } +} + +void hwss_add_set_dmdata_attributes(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + struct dc_dmdata_attributes *attr = + &seq_state->steps[*seq_state->num_steps].params.set_dmdata_attributes_params.attr; + + memset(attr, 0, sizeof(*attr)); + attr->dmdata_mode = DMDATA_HW_MODE; + attr->dmdata_size = dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; + attr->address.quad_part = pipe_ctx->stream->dmdata_address.quad_part; + attr->dmdata_repeat = 1; /* always repeat */ + attr->dmdata_updated = 1; + + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_DMDATA_ATTRIBUTES; + seq_state->steps[*seq_state->num_steps].params.set_dmdata_attributes_params.hubp = + pipe_ctx->plane_res.hubp; + (*seq_state->num_steps)++; + } +} + +void hwss_add_link_increase_mst_payload(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, + uint32_t mst_stream_bw) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = LINK_INCREASE_MST_PAYLOAD; + seq_state->steps[*seq_state->num_steps].params.link_increase_mst_payload_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].params.link_increase_mst_payload_params.mst_stream_bw = mst_stream_bw; + (*seq_state->num_steps)++; + } +} + +void hwss_add_link_reduce_mst_payload(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, + uint32_t mst_stream_bw) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = LINK_REDUCE_MST_PAYLOAD; + seq_state->steps[*seq_state->num_steps].params.link_reduce_mst_payload_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].params.link_reduce_mst_payload_params.mst_stream_bw = mst_stream_bw; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dp_set_test_pattern(struct block_sequence_state *seq_state, + struct dc_link *link, + enum dp_test_pattern test_pattern, + enum dp_test_pattern_color_space test_pattern_color_space, + const struct link_training_settings *p_link_settings, + const unsigned char *p_custom_pattern, + unsigned int cust_pattern_size) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DP_SET_TEST_PATTERN; + seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.link = link; + seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.test_pattern = test_pattern; + seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.test_pattern_color_space = test_pattern_color_space; + seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.p_link_settings = p_link_settings; + seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.p_custom_pattern = p_custom_pattern; + seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.cust_pattern_size = cust_pattern_size; + (*seq_state->num_steps)++; + } +} + +void hwss_add_link_set_dpms_off(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = LINK_SET_DPMS_OFF; + seq_state->steps[*seq_state->num_steps].params.link_set_dpms_off_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_disable_audio_stream(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DISABLE_AUDIO_STREAM; + seq_state->steps[*seq_state->num_steps].params.disable_audio_stream_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_prepare_bandwidth(struct block_sequence_state *seq_state, + struct dc *dc, + struct dc_state *context) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = PREPARE_BANDWIDTH; + seq_state->steps[*seq_state->num_steps].params.prepare_bandwidth_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.prepare_bandwidth_params.context = context; + (*seq_state->num_steps)++; + } +} + +void hwss_add_link_set_dpms_on(struct block_sequence_state *seq_state, + struct dc_state *state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = LINK_SET_DPMS_ON; + seq_state->steps[*seq_state->num_steps].params.link_set_dpms_on_params.state = state; + seq_state->steps[*seq_state->num_steps].params.link_set_dpms_on_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + void get_refresh_rate_confirm_color(struct pipe_ctx *pipe_ctx, struct tg_color *color) { @@ -4124,8 +5122,8 @@ void get_refresh_rate_confirm_color(struct pipe_ctx *pipe_ctx, struct tg_color * if (max_refresh_rate - min_refresh_rate) scaling_factor = MAX_TG_COLOR_VALUE * (refresh_rate - min_refresh_rate) / (max_refresh_rate - min_refresh_rate); - pipe_ctx->visual_confirm_color.color_r_cr = color_value; - pipe_ctx->visual_confirm_color.color_g_y = scaling_factor; - pipe_ctx->visual_confirm_color.color_b_cb = color_value; + pipe_ctx->visual_confirm_color.color_r_cr = (uint16_t)color_value; + pipe_ctx->visual_confirm_color.color_g_y = (uint16_t)scaling_factor; + pipe_ctx->visual_confirm_color.color_b_cb = (uint16_t)color_value; } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c index deb23d20bca6..afdf9f8b16d7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c @@ -33,7 +33,7 @@ static bool is_dig_link_enc_stream(struct dc_stream_state *stream) { bool is_dig_stream = false; struct link_encoder *link_enc = NULL; - int i; + unsigned int i; /* Loop over created link encoder objects. */ if (stream) { @@ -161,7 +161,7 @@ static enum engine_id find_first_avail_link_enc( enum engine_id eng_id_requested) { enum engine_id eng_id = ENGINE_ID_UNKNOWN; - int i; + unsigned int i; if (eng_id_requested != ENGINE_ID_UNKNOWN) { @@ -248,7 +248,7 @@ static struct link_encoder *get_link_enc_used_by_link( /* Clear all link encoder assignments. */ static void clear_enc_assignments(const struct dc *dc, struct dc_state *state) { - int i; + unsigned int i; for (i = 0; i < MAX_PIPES; i++) { state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].valid = false; @@ -523,7 +523,7 @@ struct link_encoder *link_enc_cfg_get_next_avail_link_enc(struct dc *dc) { struct link_encoder *link_enc = NULL; enum engine_id encs_assigned[MAX_LINK_ENCODERS]; - int i; + unsigned int i; for (i = 0; i < MAX_LINK_ENCODERS; i++) encs_assigned[i] = ENGINE_ID_UNKNOWN; @@ -624,7 +624,8 @@ bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state) bool valid_uniqueness = true; bool valid_avail = true; bool valid_streams = true; - int i, j; + int i; + unsigned int j; uint8_t valid_count = 0; uint8_t dig_stream_count = 0; int eng_ids_per_ep_id[MAX_PIPES] = {0}; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 05991a10f8bf..ad377a991451 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -286,34 +286,34 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, #endif case DCE_VERSION_8_0: res_pool = dce80_create_resource_pool( - init_data->num_virtual_links, dc); + (uint8_t)init_data->num_virtual_links, dc); break; case DCE_VERSION_8_1: res_pool = dce81_create_resource_pool( - init_data->num_virtual_links, dc); + (uint8_t)init_data->num_virtual_links, dc); break; case DCE_VERSION_8_3: res_pool = dce83_create_resource_pool( - init_data->num_virtual_links, dc); + (uint8_t)init_data->num_virtual_links, dc); break; case DCE_VERSION_10_0: res_pool = dce100_create_resource_pool( - init_data->num_virtual_links, dc); + (uint8_t)init_data->num_virtual_links, dc); break; case DCE_VERSION_11_0: res_pool = dce110_create_resource_pool( - init_data->num_virtual_links, dc, + (uint8_t)init_data->num_virtual_links, dc, init_data->asic_id); break; case DCE_VERSION_11_2: case DCE_VERSION_11_22: res_pool = dce112_create_resource_pool( - init_data->num_virtual_links, dc); + (uint8_t)init_data->num_virtual_links, dc); break; case DCE_VERSION_12_0: case DCE_VERSION_12_1: res_pool = dce120_create_resource_pool( - init_data->num_virtual_links, dc); + (uint8_t)init_data->num_virtual_links, dc); break; #if defined(CONFIG_DRM_AMD_DC_FP) @@ -446,7 +446,7 @@ bool resource_construct( { struct dc_context *ctx = dc->ctx; const struct resource_caps *caps = pool->res_cap; - int i; + unsigned int i; unsigned int num_audio = caps->num_audio; struct resource_straps straps = {0}; @@ -463,7 +463,7 @@ bool resource_construct( * PORT_CONNECTIVITY == 1 (as instructed by HW team). */ update_num_audio(&straps, &num_audio, &pool->audio_support); - for (i = 0; i < caps->num_audio; i++) { + for (i = 0; i < (unsigned int)caps->num_audio; i++) { struct audio *aud = create_funcs->create_audio(ctx, i); if (aud == NULL) { @@ -481,14 +481,14 @@ bool resource_construct( pool->stream_enc_count = 0; if (create_funcs->create_stream_encoder) { - for (i = 0; i < caps->num_stream_encoder; i++) { + for (i = 0; i < (unsigned int)caps->num_stream_encoder; i++) { pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx); if (pool->stream_enc[i] == NULL) DC_ERR("DC: failed to create stream_encoder!\n"); pool->stream_enc_count++; } - for (i = 0; i < caps->num_analog_stream_encoder; i++) { + for (i = 0; i < (unsigned int)caps->num_analog_stream_encoder; i++) { pool->stream_enc[caps->num_stream_encoder + i] = create_funcs->create_stream_encoder(ENGINE_ID_DACA + i, ctx); if (pool->stream_enc[caps->num_stream_encoder + i] == NULL) @@ -499,7 +499,7 @@ bool resource_construct( pool->hpo_dp_stream_enc_count = 0; if (create_funcs->create_hpo_dp_stream_encoder) { - for (i = 0; i < caps->num_hpo_dp_stream_encoder; i++) { + for (i = 0; i < (unsigned int)caps->num_hpo_dp_stream_encoder; i++) { pool->hpo_dp_stream_enc[i] = create_funcs->create_hpo_dp_stream_encoder(i+ENGINE_ID_HPO_DP_0, ctx); if (pool->hpo_dp_stream_enc[i] == NULL) DC_ERR("DC: failed to create HPO DP stream encoder!\n"); @@ -510,15 +510,15 @@ bool resource_construct( pool->hpo_dp_link_enc_count = 0; if (create_funcs->create_hpo_dp_link_encoder) { - for (i = 0; i < caps->num_hpo_dp_link_encoder; i++) { - pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx); + for (i = 0; i < (unsigned int)caps->num_hpo_dp_link_encoder; i++) { + pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder((uint8_t)i, ctx); if (pool->hpo_dp_link_enc[i] == NULL) DC_ERR("DC: failed to create HPO DP link encoder!\n"); pool->hpo_dp_link_enc_count++; } } - for (i = 0; i < caps->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)caps->num_mpc_3dlut; i++) { pool->mpc_lut[i] = dc_create_3dlut_func(); if (pool->mpc_lut[i] == NULL) DC_ERR("DC: failed to create MPC 3dlut!\n"); @@ -551,11 +551,11 @@ static int find_matching_clock_source( struct clock_source *clock_source) { - int i; + unsigned int i; for (i = 0; i < pool->clk_src_count; i++) { if (pool->clock_sources[i] == clock_source) - return i; + return (int)i; } return -1; } @@ -610,7 +610,7 @@ bool resource_are_vblanks_synchronizable( { uint32_t base60_refresh_rates[] = {10, 20, 5}; uint8_t i; - uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates); + uint8_t rr_count = (uint8_t)ARRAY_SIZE(base60_refresh_rates); uint64_t frame_time_diff; if (stream1->ctx->dc->config.vblank_alignment_dto_params && @@ -1801,7 +1801,7 @@ struct pipe_ctx *resource_find_free_secondary_pipe_legacy( int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; - secondary_pipe->pipe_idx = preferred_pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx; } } @@ -1813,7 +1813,7 @@ struct pipe_ctx *resource_find_free_secondary_pipe_legacy( for (i = pool->pipe_count - 1; i >= 0; i--) { if (res_ctx->pipe_ctx[i].stream == NULL) { secondary_pipe = &res_ctx->pipe_ctx[i]; - secondary_pipe->pipe_idx = i; + secondary_pipe->pipe_idx = (uint8_t)i; break; } } @@ -1876,7 +1876,7 @@ int recource_find_free_pipe_not_used_in_cur_res_ctx( { int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; const struct pipe_ctx *new_pipe, *cur_pipe; - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { cur_pipe = &cur_res_ctx->pipe_ctx[i]; @@ -1899,7 +1899,7 @@ int recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx( { int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; const struct pipe_ctx *new_pipe, *cur_pipe; - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { cur_pipe = &cur_res_ctx->pipe_ctx[i]; @@ -1922,7 +1922,7 @@ int resource_find_free_pipe_used_as_cur_sec_dpp( { int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; const struct pipe_ctx *new_pipe, *cur_pipe; - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { cur_pipe = &cur_res_ctx->pipe_ctx[i]; @@ -1946,7 +1946,7 @@ int resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine( { int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; const struct pipe_ctx *new_pipe, *cur_pipe; - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { cur_pipe = &cur_res_ctx->pipe_ctx[i]; @@ -1969,7 +1969,7 @@ int resource_find_any_free_pipe(struct resource_context *new_res_ctx, { int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; const struct pipe_ctx *new_pipe; - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { new_pipe = &new_res_ctx->pipe_ctx[i]; @@ -2564,7 +2564,7 @@ static bool update_pipe_params_after_odm_slice_count_change( struct dc_state *context, const struct resource_pool *pool) { - int i; + unsigned int i; struct pipe_ctx *pipe; bool result = true; @@ -2587,7 +2587,7 @@ static bool update_pipe_params_after_mpc_slice_count_change( struct dc_state *context, const struct resource_pool *pool) { - int i; + unsigned int i; struct pipe_ctx *pipe; bool result = true; @@ -2604,7 +2604,7 @@ static int acquire_first_split_pipe( const struct resource_pool *pool, struct dc_stream_state *stream) { - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i]; @@ -2624,11 +2624,11 @@ static int acquire_first_split_pipe( split_pipe->plane_res.ipp = pool->ipps[i]; split_pipe->plane_res.dpp = pool->dpps[i]; split_pipe->stream_res.opp = pool->opps[i]; - split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; - split_pipe->pipe_idx = i; + split_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[i]->inst; + split_pipe->pipe_idx = (uint8_t)i; split_pipe->stream = stream; - return i; + return (int)i; } } return FREE_PIPE_INDEX_NOT_FOUND; @@ -2640,7 +2640,7 @@ static void update_stream_engine_usage( struct stream_encoder *stream_enc, bool acquired) { - int i; + unsigned int i; for (i = 0; i < pool->stream_enc_count; i++) { if (pool->stream_enc[i] == stream_enc) @@ -2654,7 +2654,7 @@ static void update_hpo_dp_stream_engine_usage( struct hpo_dp_stream_encoder *hpo_dp_stream_enc, bool acquired) { - int i; + unsigned int i; for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) { if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc) @@ -2679,14 +2679,14 @@ static inline int find_acquired_hpo_dp_link_enc_for_link( static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx, const struct resource_pool *pool) { - int i; + unsigned int i; for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++) if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0) break; return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) && - i < pool->hpo_dp_link_enc_count) ? i : -1; + i < pool->hpo_dp_link_enc_count) ? (int)i : -1; } static inline void acquire_hpo_dp_link_enc( @@ -2773,9 +2773,10 @@ static inline int find_fixed_dio_link_enc(const struct dc_link *link) static inline int find_free_dio_link_enc(const struct resource_context *res_ctx, const struct dc_link *link, const struct resource_pool *pool, struct dc_stream_state *stream) { - int i, j = -1; + unsigned int i; + int j = -1; int stream_enc_inst = -1; - int enc_count = pool->dig_link_enc_count; + unsigned int enc_count = pool->dig_link_enc_count; /* Find stream encoder instance for the stream */ if (stream) { @@ -2931,7 +2932,7 @@ static void remove_dio_link_enc_from_ctx(struct resource_context *res_ctx, static int get_num_of_free_pipes(const struct resource_pool *pool, const struct dc_state *context) { - int i; + unsigned int i; int count = 0; for (i = 0; i < pool->pipe_count; i++) @@ -3608,7 +3609,7 @@ void update_audio_usage( struct audio *audio, bool acquired) { - int i; + unsigned int i; for (i = 0; i < pool->audio_count; i++) { if (pool->audios[i] == audio) res_ctx->is_audio_acquired[i] = acquired; @@ -3621,7 +3622,7 @@ static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for struct dc_stream_state *stream) { (void)stream; - int i; + unsigned int i; for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) { if (!res_ctx->is_hpo_dp_stream_enc_acquired[i] && @@ -3804,7 +3805,7 @@ static int acquire_resource_from_hw_enabled_state( pipe_ctx->stream_res.opp = pool->opps[id_src[i]]; if (pool->dpps[id_src[i]]) { - pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst; + pipe_ctx->plane_res.mpcc_inst = (uint8_t)pool->dpps[id_src[i]]->inst; if (pool->mpc->funcs->read_mpcc_state) { struct mpcc_state s = {0}; @@ -3823,7 +3824,7 @@ static int acquire_resource_from_hw_enabled_state( pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id; } } - pipe_ctx->pipe_idx = id_src[i]; + pipe_ctx->pipe_idx = (uint8_t)id_src[i]; if (id_src[i] >= pool->timing_generator_count) { id_src[i] = pool->timing_generator_count - 1; @@ -3939,7 +3940,7 @@ static bool acquire_otg_master_pipe_for_stream( if (pipe_idx != FREE_PIPE_INDEX_NOT_FOUND) { pipe_ctx = &new_ctx->res_ctx.pipe_ctx[pipe_idx]; memset(pipe_ctx, 0, sizeof(*pipe_ctx)); - pipe_ctx->pipe_idx = pipe_idx; + pipe_ctx->pipe_idx = (uint8_t)pipe_idx; pipe_ctx->stream_res.tg = pool->timing_generators[pipe_idx]; pipe_ctx->plane_res.mi = pool->mis[pipe_idx]; pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx]; @@ -3948,9 +3949,9 @@ static bool acquire_otg_master_pipe_for_stream( pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx]; pipe_ctx->stream_res.opp = pool->opps[pipe_idx]; if (pool->dpps[pipe_idx]) - pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; + pipe_ctx->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst; - if (pipe_idx >= pool->timing_generator_count && pool->timing_generator_count != 0) { + if ((unsigned int)pipe_idx >= pool->timing_generator_count && pool->timing_generator_count != 0) { int tg_inst = pool->timing_generator_count - 1; pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; @@ -4194,7 +4195,8 @@ enum dc_status dc_validate_with_context(struct dc *dc, int del_streams_count = 0; int add_streams_count = 0; bool found = false; - int i, j, k; + int i, j; + unsigned int k; DC_LOGGER_INIT(dc->ctx->logger); @@ -4421,7 +4423,8 @@ enum dc_status dc_validate_global_state( enum dc_validate_mode validate_mode) { enum dc_status result = DC_ERROR_UNEXPECTED; - int i, j; + int i; + unsigned int j; if (!new_ctx) return DC_ERROR_UNEXPECTED; @@ -4497,7 +4500,7 @@ static void patch_gamut_packet_checksum( for (i = 0; i <= gamut_packet->sb[1]; i++) chk_sum += ptr[i]; - gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum); + gamut_packet->sb[2] = (uint8_t)(0x100 - chk_sum); } } @@ -4562,7 +4565,7 @@ static void set_avi_info_frame( /* Y0_Y1_Y2 : The pixel encoding */ /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */ - hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding; + hdmi_info.bits.Y0_Y1_Y2 = (uint8_t)pixel_encoding; /* A0 = 1 Active Format Information valid */ hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID; @@ -4692,7 +4695,7 @@ static void set_avi_info_frame( } } /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/ - hdmi_info.bits.VIC0_VIC7 = vic; + hdmi_info.bits.VIC0_VIC7 = (uint8_t)vic; if (vic >= 128) hdmi_info.bits.header.version = 3; /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1), @@ -4710,7 +4713,7 @@ static void set_avi_info_frame( hdmi_info.bits.FR0_FR3 = fr_ind & 0xF; hdmi_info.bits.FR4 = (fr_ind >> 4) & 0x1; - hdmi_info.bits.RID0_RID5 = rid; + hdmi_info.bits.RID0_RID5 = (uint8_t)rid; } /* pixel repetition @@ -4723,11 +4726,11 @@ static void set_avi_info_frame( * barBottom: Line Number of Start of Bottom Bar. * barLeft: Pixel Number of End of Left Bar. * barRight: Pixel Number of Start of Right Bar. */ - hdmi_info.bits.bar_top = stream->timing.v_border_top; - hdmi_info.bits.bar_bottom = (stream->timing.v_total + hdmi_info.bits.bar_top = (uint16_t)stream->timing.v_border_top; + hdmi_info.bits.bar_bottom = (uint16_t)(stream->timing.v_total - stream->timing.v_border_bottom + 1); - hdmi_info.bits.bar_left = stream->timing.h_border_left; - hdmi_info.bits.bar_right = (stream->timing.h_total + hdmi_info.bits.bar_left = (uint16_t)stream->timing.h_border_left; + hdmi_info.bits.bar_right = (uint16_t)(stream->timing.h_total - stream->timing.h_border_right + 1); /* Additional Colorimetry Extension @@ -4746,7 +4749,7 @@ static void set_avi_info_frame( *check_sum += hdmi_info.packet_raw_data.sb[byte_index]; /* one byte complement */ - *check_sum = (uint8_t) (0x100 - *check_sum); + *check_sum = (uint8_t)(0x100 - *check_sum); /* Store in hw_path_mode */ info_packet->hb0 = hdmi_info.packet_raw_data.hb0; @@ -4880,7 +4883,7 @@ struct clock_source *dc_resource_find_first_free_pll( struct resource_context *res_ctx, const struct resource_pool *pool) { - int i; + unsigned int i; for (i = 0; i < pool->clk_src_count; ++i) { if (res_ctx->clock_source_ref_count[i] == 0) @@ -5369,7 +5372,7 @@ bool get_temp_dp_link_res(struct dc_link *link, void reset_syncd_pipes_from_disabled_pipes(struct dc *dc, struct dc_state *context) { - int i, j; + uint8_t i, j; struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd; /* If pipe backend is reset, need to reset pipe syncd status */ @@ -5398,7 +5401,7 @@ void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc, struct dc_state *context, uint8_t disabled_master_pipe_idx) { - int i; + unsigned int i; struct pipe_ctx *pipe_ctx, *pipe_ctx_check; pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx]; @@ -5432,7 +5435,7 @@ void reset_sync_context_for_pipe(const struct dc *dc, struct dc_state *context, uint8_t pipe_idx) { - int i; + uint8_t i; struct pipe_ctx *pipe_ctx_reset; /* reset the otg sync context for the pipe and its slave pipes if any */ @@ -5448,7 +5451,7 @@ void reset_sync_context_for_pipe(const struct dc *dc, uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter) { /* TODO - get transmitter to phy idx mapping from DMUB */ - uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A; + uint8_t phy_idx = (uint8_t)(transmitter - TRANSMITTER_UNIPHY_A); if (dc->ctx->dce_version == DCN_VERSION_3_1 && dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { @@ -5515,8 +5518,8 @@ const struct link_hwss *get_link_hwss(const struct dc_link *link, bool is_h_timing_divisible_by_2(struct dc_stream_state *stream) { bool divisible = false; - uint16_t h_blank_start = 0; - uint16_t h_blank_end = 0; + uint32_t h_blank_start = 0; + uint32_t h_blank_end = 0; if (stream) { h_blank_start = stream->timing.h_total - stream->timing.h_front_porch; @@ -5570,13 +5573,13 @@ bool dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy( sec_pipe->next_odm_pipe = sec_next; sec_pipe->prev_odm_pipe = sec_prev; - sec_pipe->pipe_idx = pipe_idx; + sec_pipe->pipe_idx = (uint8_t)pipe_idx; sec_pipe->plane_res.mi = pool->mis[pipe_idx]; sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; - sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; + sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst; sec_pipe->stream_res.dsc = NULL; if (odm) { if (!sec_pipe->top_pipe) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c index 40f7aa732258..ad2c0a93a41b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c @@ -953,7 +953,7 @@ bool dc_state_remove_phantom_streams_and_planes( const struct dc *dc, struct dc_state *state) { - int i; + unsigned int i; bool removed_phantom = false; struct dc_stream_state *phantom_stream = NULL; @@ -978,7 +978,7 @@ void dc_state_release_phantom_streams_and_planes( unsigned int phantom_count; struct dc_stream_state *phantom_streams[MAX_PHANTOM_PIPES]; struct dc_plane_state *phantom_planes[MAX_PHANTOM_PIPES]; - int i; + unsigned int i; phantom_count = state->phantom_stream_count; memcpy(phantom_streams, state->phantom_streams, sizeof(struct dc_stream_state *) * MAX_PHANTOM_PIPES); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index e16de323f39c..21dcb47f671a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -259,11 +259,17 @@ const struct dc_stream_status *dc_stream_get_status_const( return dc_state_get_stream_status(dc->current_state, stream); } +struct dc_link *dc_stream_get_link( + const struct dc_stream_state *stream) +{ + return stream->link; +} + void program_cursor_attributes( struct dc *dc, struct dc_stream_state *stream) { - int i; + uint8_t i; struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); @@ -410,7 +416,7 @@ void program_cursor_position( struct dc *dc, struct dc_stream_state *stream) { - int i; + uint8_t i; struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); @@ -508,7 +514,7 @@ bool dc_stream_program_cursor_position( /* apply/update visual confirm */ if (dc->debug.visual_confirm == VISUAL_CONFIRM_HW_CURSOR) { /* update software state */ - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; @@ -527,7 +533,7 @@ bool dc_stream_program_cursor_position( if (stream->drr_trigger_mode == DRR_TRIGGER_ON_FLIP_AND_CURSOR) { /* apply manual trigger */ - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; @@ -553,7 +559,7 @@ bool dc_stream_add_writeback(struct dc *dc, struct dc_writeback_info *wb_info) { bool isDrc = false; - int i = 0; + unsigned int i = 0; struct dwbc *dwb; if (stream == NULL) { @@ -962,7 +968,7 @@ struct dc_rmcm_3dlut *dc_stream_get_3dlut_for_stream( unsigned int num_rmcm = dc->caps.color.mpc.num_rmcm_3dluts; // see if one is allocated for this stream - for (int i = 0; i < num_rmcm; i++) { + for (unsigned int i = 0; i < num_rmcm; i++) { if (dc->res_pool->rmcm_3dlut[i].isInUse && dc->res_pool->rmcm_3dlut[i].stream == stream) return &dc->res_pool->rmcm_3dlut[i]; @@ -973,7 +979,7 @@ struct dc_rmcm_3dlut *dc_stream_get_3dlut_for_stream( return NULL; //see if there is an unused 3dlut, allocate - for (int i = 0; i < num_rmcm; i++) { + for (unsigned int i = 0; i < num_rmcm; i++) { if (!dc->res_pool->rmcm_3dlut[i].isInUse) { dc->res_pool->rmcm_3dlut[i].isInUse = true; dc->res_pool->rmcm_3dlut[i].stream = stream; @@ -996,6 +1002,7 @@ void dc_stream_release_3dlut_for_stream( if (rmcm_3dlut) { rmcm_3dlut->isInUse = false; rmcm_3dlut->stream = NULL; + rmcm_3dlut->protection_bits = 0; } } @@ -1004,9 +1011,10 @@ void dc_stream_init_rmcm_3dlut(struct dc *dc) { unsigned int num_rmcm = dc->caps.color.mpc.num_rmcm_3dluts; - for (int i = 0; i < num_rmcm; i++) { + for (unsigned int i = 0; i < num_rmcm; i++) { dc->res_pool->rmcm_3dlut[i].isInUse = false; dc->res_pool->rmcm_3dlut[i].stream = NULL; + dc->res_pool->rmcm_3dlut[i].protection_bits = 0; } } @@ -1032,14 +1040,18 @@ static int dc_stream_get_brightness_millinits_linear_interpolation (struct dc_st int refresh_hz) { long long slope = 0; + long long y_intercept = 0; + long long brightness_millinits = 0; + if (stream->lumin_data.refresh_rate_hz[index2] != stream->lumin_data.refresh_rate_hz[index1]) { slope = (stream->lumin_data.luminance_millinits[index2] - stream->lumin_data.luminance_millinits[index1]) / (stream->lumin_data.refresh_rate_hz[index2] - stream->lumin_data.refresh_rate_hz[index1]); } - int y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2]; + y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2]; + brightness_millinits = y_intercept + (long long)refresh_hz * slope; - return (y_intercept + refresh_hz * slope); + return (int)brightness_millinits; } /* @@ -1051,14 +1063,18 @@ static int dc_stream_get_refresh_hz_linear_interpolation (struct dc_stream_state int brightness_millinits) { long long slope = 1; + long long y_intercept = 0; + long long refresh_hz = 0; + if (stream->lumin_data.refresh_rate_hz[index2] != stream->lumin_data.refresh_rate_hz[index1]) { slope = (stream->lumin_data.luminance_millinits[index2] - stream->lumin_data.luminance_millinits[index1]) / (stream->lumin_data.refresh_rate_hz[index2] - stream->lumin_data.refresh_rate_hz[index1]); } - int y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2]; + y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2]; + refresh_hz = div64_s64((brightness_millinits - y_intercept), slope); - return ((int)div64_s64((brightness_millinits - y_intercept), slope)); + return (int)refresh_hz; } /* diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index a59b176d8e55..72845fc788f3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -69,13 +69,13 @@ void dc_plane_destruct(struct dc_plane_state *plane_state) uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state) { uint8_t pipe_mask = 0; - int i; + unsigned int i; for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i]; if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp) - pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst; + pipe_mask |= (uint8_t)(1 << pipe_ctx->plane_res.hubp->inst); } return pipe_mask; @@ -115,7 +115,7 @@ const struct dc_plane_status *dc_plane_get_status( { const struct dc_plane_status *plane_status; struct dc *dc; - int i; + unsigned int i; if (!plane_state || !plane_state->ctx || @@ -286,7 +286,7 @@ void dc_plane_force_dcc_and_tiling_disable(struct dc_plane_state *plane_state, bool clear_tiling) { struct dc *dc; - int i; + unsigned int i; if (!plane_state) return; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7f55ba09b191..9bd4b0bb47df 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.378" +#define DC_VER "3.2.381" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC @@ -971,6 +971,7 @@ struct dc_qos_info { uint32_t actual_avg_latency_in_ns; uint32_t qos_avg_latency_ub_in_ns; uint32_t dcn_bandwidth_ub_in_mbps; + uint32_t qos_max_bw_budget_in_mbps; }; struct dc_state; @@ -1407,50 +1408,15 @@ struct lut_mem_mapping { struct dc_rmcm_3dlut { bool isInUse; const struct dc_stream_state *stream; + uint8_t protection_bits; }; struct dc_3dlut { struct kref refcount; struct tetrahedral_params lut_3d; + struct fixed31_32 hdr_multiplier; union dc_3dlut_state state; }; - -/* 3DLUT DMA (Fast Load) params */ -struct dc_3dlut_dma { - struct dc_plane_address addr; - enum dc_cm_lut_swizzle swizzle; - enum dc_cm_lut_pixel_format format; - uint16_t bias; /* FP1.5.10 */ - uint16_t scale; /* FP1.5.10 */ - enum dc_cm_lut_size size; -}; - -/* color manager */ -union dc_plane_cm_flags { - unsigned int all; - struct { - unsigned int shaper_enable : 1; - unsigned int lut3d_enable : 1; - unsigned int blend_enable : 1; - /* whether legacy (lut3d_func) or DMA is valid */ - unsigned int lut3d_dma_enable : 1; - /* RMCM lut to be used instead of MCM */ - unsigned int rmcm_enable : 1; - unsigned int reserved: 27; - } bits; -}; - -struct dc_plane_cm { - struct kref refcount; - struct dc_transfer_func shaper_func; - union { - struct dc_3dlut lut3d_func; - struct dc_3dlut_dma lut3d_dma; - }; - struct dc_transfer_func blend_func; - union dc_plane_cm_flags flags; -}; - /* * This structure is filled in by dc_surface_get_status and contains * the last requested address and the currently active address so the called @@ -1485,6 +1451,7 @@ union surface_update_flags { uint32_t pixel_format_change:1; uint32_t plane_size_change:1; uint32_t gamut_remap_change:1; + uint32_t cursor_csc_color_matrix_change:1; /* Full updates */ uint32_t new_plane:1; @@ -1499,11 +1466,14 @@ union surface_update_flags { uint32_t full_update:1; uint32_t sdr_white_level_nits:1; uint32_t cm_hist_change:1; + uint32_t reserved:2; /* adjust when adding new flags */ } bits; uint32_t raw; }; +bool dc_check_address_only_update(union surface_update_flags update_flags); + #define DC_REMOVE_PLANE_POINTERS 1 struct dc_plane_state { @@ -1528,18 +1498,14 @@ struct dc_plane_state { struct fixed31_32 hdr_mult; struct colorspace_transform gamut_remap_matrix; + // TODO: No longer used, remove + struct dc_hdr_static_metadata hdr_static_ctx; + enum dc_color_space color_space; - bool lut_bank_a; - struct dc_hdr_static_metadata hdr_static_ctx; struct dc_3dlut lut3d_func; struct dc_transfer_func in_shaper_func; struct dc_transfer_func blend_tf; - enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; - bool mcm_lut1d_enable; - struct dc_cm2_func_luts mcm_luts; - enum mpcc_movable_cm_location mcm_location; - struct dc_plane_cm cm; struct dc_transfer_func *gamcor_tf; enum surface_pixel_format format; @@ -1576,6 +1542,11 @@ struct dc_plane_state { bool is_statically_allocated; enum chroma_cositing cositing; + enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; + bool mcm_lut1d_enable; + struct dc_cm2_func_luts mcm_luts; + bool lut_bank_a; + enum mpcc_movable_cm_location mcm_location; struct dc_csc_transform cursor_csc_color_matrix; bool adaptive_sharpness_en; int adaptive_sharpness_policy; @@ -1682,7 +1653,7 @@ struct dc_scratch_space { struct dc_link_training_overrides preferred_training_settings; struct dp_audio_test_data audio_test_data; - uint8_t ddc_hw_inst; + enum gpio_ddc_line ddc_hw_inst; uint8_t hpd_src; @@ -1882,20 +1853,6 @@ struct dc_scaling_info { struct scaling_taps scaling_quality; }; -struct dc_fast_update { - const struct dc_flip_addrs *flip_addr; - const struct dc_gamma *gamma; - const struct colorspace_transform *gamut_remap_matrix; - const struct dc_csc_transform *input_csc_color_matrix; - const struct fixed31_32 *coeff_reduction_factor; - struct dc_transfer_func *out_transfer_func; - struct dc_csc_transform *output_csc_transform; - const struct dc_csc_transform *cursor_csc_color_matrix; -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) - struct cm_hist_control *cm_hist_control; -#endif -}; - struct dc_surface_update { struct dc_plane_state *surface; @@ -1968,10 +1925,6 @@ struct dc_3dlut *dc_create_3dlut_func(void); void dc_3dlut_func_release(struct dc_3dlut *lut); void dc_3dlut_func_retain(struct dc_3dlut *lut); -struct dc_plane_cm *dc_plane_cm_create(void); -void dc_plane_cm_release(struct dc_plane_cm *cm); -void dc_plane_cm_retain(struct dc_plane_cm *cm); - void dc_post_update_surfaces_to_stream( struct dc *dc); @@ -2034,11 +1987,6 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); void get_audio_check(struct audio_info *aud_modes, struct audio_check *aud_chk); -bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); -void populate_fast_updates(struct dc_fast_update *fast_update, - struct dc_surface_update *srf_updates, - int surface_count, - struct dc_stream_update *stream_update); /* * Set up streams and links associated to drive sinks * The streams parameter is an absolute set of all active streams. @@ -3436,4 +3384,17 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa */ bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info); +/** + * dc_override_memory_bandwidth_request - Override the DCN nominal memory + * bandwidth request sent to PMFW, independent of the current display mode. + * For debug use only. + * @dc: DC instance + * @bw_mbps: requested bandwidth in MB/s; 0 clears the override + * + * Return: capped bandwidth value actually applied (MB/s) + */ +unsigned int dc_override_memory_bandwidth_request( + struct dc *dc, + unsigned int bw_mbps); + #endif /* DC_INTERFACE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h index 6f96c5cf39fe..526f71616f94 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h @@ -102,7 +102,8 @@ struct dc_vbios_funcs { struct bp_external_encoder_control *cntl); enum bp_result (*dac_load_detection)( struct dc_bios *bios, - enum engine_id engine_id); + enum engine_id engine_id, + struct graphics_object_id ext_enc_id); enum bp_result (*transmitter_control)( struct dc_bios *bios, struct bp_transmitter_control *cntl); diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index 79c8b4cab053..9d4e7badb9f9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -151,7 +151,7 @@ static bool dc_dmub_srv_reg_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_s struct dc_context *dc_ctx; struct dmub_srv *dmub; enum dmub_status status = DMUB_STATUS_OK; - int i; + unsigned int i; if (!dc_dmub_srv || !dc_dmub_srv->dmub) return false; @@ -193,7 +193,7 @@ static bool dc_dmub_srv_fb_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_sr struct dc_context *dc_ctx; struct dmub_srv *dmub; enum dmub_status status; - int i; + unsigned int i; if (!dc_dmub_srv || !dc_dmub_srv->dmub) return false; @@ -336,7 +336,7 @@ bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv) return false; } - return boot_status.bits.optimized_init_done; + return (bool)boot_status.bits.optimized_init_done; } bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, @@ -346,7 +346,7 @@ bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, return false; return dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK, - stream_mask, NULL, DM_DMUB_WAIT_TYPE_WAIT); + (uint16_t)stream_mask, NULL, DM_DMUB_WAIT_TYPE_WAIT); } bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) @@ -368,7 +368,7 @@ bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) return false; } - return boot_status.bits.restore_required; + return (bool)boot_status.bits.restore_required; } bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) @@ -415,7 +415,7 @@ void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst) static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream) { uint8_t pipes = 0; - int i = 0; + uint8_t i = 0; for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; @@ -430,25 +430,26 @@ static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state * struct pipe_ctx *head_pipe, struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data) { - int j; + unsigned int j; int pipe_idx = 0; - fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst; + fams_pipe_data->pipe_index[pipe_idx++] = (uint8_t)head_pipe->plane_res.hubp->inst; for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j]; if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) { - fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst; + fams_pipe_data->pipe_index[pipe_idx++] = (uint8_t)split_pipe->plane_res.hubp->inst; } } - fams_pipe_data->pipe_count = pipe_idx; + fams_pipe_data->pipe_count = (uint8_t)pipe_idx; } bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context) { union dmub_rb_cmd cmd = { 0 }; struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data; - int i = 0, k = 0; + unsigned int i = 0; + int k = 0; int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it. uint8_t visual_confirm_enabled; struct dc_stream_status *stream_status = NULL; @@ -456,7 +457,7 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru if (dc == NULL) return false; - visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS; + visual_confirm_enabled = (uint8_t)(dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS); // Format command. cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; @@ -477,7 +478,8 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru */ stream_status = dc_state_get_stream_status(context, pipe->stream); if (stream_status && !stream_status->fpo_in_use) { - cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us; + cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = + (uint16_t)dc->debug.fpo_vactive_margin_us; break; } } @@ -492,11 +494,13 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru stream_status = dc_state_get_stream_status(context, pipe->stream); if (stream_status && stream_status->fpo_in_use) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; - uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000; + uint8_t min_refresh_in_hz; + + min_refresh_in_hz = (uint8_t)((pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000); config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz; config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz; - config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps; + config_data->pipe_data[k].max_ramp_step = (uint8_t)ramp_up_num_steps; config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream); dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]); k++; @@ -551,7 +555,7 @@ void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pi cmd.visual_confirm_color.header.sub_type = 0; cmd.visual_confirm_color.header.ret_status = 1; cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data); - cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst; + cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = (uint16_t)panel_inst; // If command was processed, copy feature caps to dmub srv if (dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) && @@ -589,17 +593,17 @@ static void populate_subvp_cmd_drr_info(struct dc *dc, struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; struct dc_crtc_timing *phantom_timing; struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; - uint16_t drr_frame_us = 0; - uint16_t min_drr_supported_us = 0; - uint16_t max_drr_supported_us = 0; - uint16_t max_drr_vblank_us = 0; - uint16_t max_drr_mallregion_us = 0; - uint16_t mall_region_us = 0; - uint16_t prefetch_us = 0; - uint16_t subvp_active_us = 0; - uint16_t drr_active_us = 0; - uint16_t min_vtotal_supported = 0; - uint16_t max_vtotal_supported = 0; + uint64_t drr_frame_us = 0; + uint64_t min_drr_supported_us = 0; + uint64_t max_drr_supported_us = 0; + uint64_t max_drr_vblank_us = 0; + uint64_t max_drr_mallregion_us = 0; + uint64_t mall_region_us = 0; + uint64_t prefetch_us = 0; + uint64_t subvp_active_us = 0; + uint64_t drr_active_us = 0; + uint64_t min_vtotal_supported = 0; + uint64_t max_vtotal_supported = 0; if (!phantom_stream) return; @@ -639,9 +643,10 @@ static void populate_subvp_cmd_drr_info(struct dc *dc, */ max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us; - pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; - pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; - pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us; + pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = (uint16_t)min_vtotal_supported; + pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = (uint16_t)max_vtotal_supported; + pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = + (uint16_t)dc->caps.subvp_drr_vblank_start_margin_us; } /** @@ -686,14 +691,15 @@ static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc, pipe_data->mode = VBLANK; pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; - pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - - vblank_pipe->stream->timing.v_front_porch; - pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; - pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; + pipe_data->pipe_config.vblank_data.vblank_start = (uint16_t)(vblank_pipe->stream->timing.v_total - + vblank_pipe->stream->timing.v_front_porch); + pipe_data->pipe_config.vblank_data.vtotal = (uint16_t)vblank_pipe->stream->timing.v_total; + pipe_data->pipe_config.vblank_data.htotal = (uint16_t)vblank_pipe->stream->timing.h_total; pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; - pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; + pipe_data->pipe_config.vblank_data.vstartup_start = (uint16_t)vblank_pipe->pipe_dlg_param.vstartup_start; pipe_data->pipe_config.vblank_data.vblank_end = - vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable; + (uint16_t)(vblank_pipe->stream->timing.v_total - + vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable); if (vblank_pipe->stream->ignore_msa_timing_param && (vblank_pipe->stream->allow_freesync || vblank_pipe->stream->vrr_active_variable || vblank_pipe->stream->vrr_active_fixed)) @@ -739,10 +745,10 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, phantom_timing0 = &phantom_stream0->timing; phantom_timing1 = &phantom_stream1->timing; - subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) * + subvp0_prefetch_us = (uint32_t)div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) * (uint64_t)phantom_timing0->h_total * 1000000), (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); - subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) * + subvp1_prefetch_us = (uint32_t)div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) * (uint64_t)phantom_timing1->h_total * 1000000), (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); @@ -751,8 +757,8 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, if (subvp0_prefetch_us > subvp1_prefetch_us) { pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1]; prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us; - pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = - div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * +pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = + (uint16_t)div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)), ((uint64_t)phantom_timing1->h_total * 1000000)); @@ -760,7 +766,7 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0]; prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us; pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = - div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * + (uint16_t)div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)), ((uint64_t)phantom_timing0->h_total * 1000000)); } @@ -800,14 +806,14 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc, pipe_data->mode = SUBVP; pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz; - pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total; - pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total; + pipe_data->pipe_config.subvp_data.htotal = (uint16_t)subvp_pipe->stream->timing.h_total; + pipe_data->pipe_config.subvp_data.vtotal = (uint16_t)subvp_pipe->stream->timing.v_total; pipe_data->pipe_config.subvp_data.main_vblank_start = - main_timing->v_total - main_timing->v_front_porch; + (uint16_t)(main_timing->v_total - main_timing->v_front_porch); pipe_data->pipe_config.subvp_data.main_vblank_end = - main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable; - pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable; - pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst; + (uint16_t)(main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable); + pipe_data->pipe_config.subvp_data.mall_region_lines = (uint16_t)phantom_timing->v_addressable; + pipe_data->pipe_config.subvp_data.main_pipe_index = (uint8_t)subvp_pipe->stream_res.tg->inst; pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param && (subvp_pipe->stream->allow_freesync || subvp_pipe->stream->vrr_active_variable || subvp_pipe->stream->vrr_active_fixed); @@ -822,25 +828,25 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc, reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height, &out_num_plane, &out_den_plane); reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den); - pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num; - pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den; + pipe_data->pipe_config.subvp_data.scale_factor_numerator = (uint8_t)out_num; + pipe_data->pipe_config.subvp_data.scale_factor_denominator = (uint8_t)out_den; // Prefetch lines is equal to VACTIVE + BP + VSYNC pipe_data->pipe_config.subvp_data.prefetch_lines = - phantom_timing->v_total - phantom_timing->v_front_porch; + (uint16_t)(phantom_timing->v_total - phantom_timing->v_front_porch); // Round up pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = - div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + + (uint16_t)div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); pipe_data->pipe_config.subvp_data.processing_delay_lines = - div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + + (uint16_t)div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); if (subvp_pipe->bottom_pipe) { - pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx; + pipe_data->pipe_config.subvp_data.main_split_pipe_index = (uint8_t)subvp_pipe->bottom_pipe->pipe_idx; } else if (subvp_pipe->next_odm_pipe) { - pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx; + pipe_data->pipe_config.subvp_data.main_split_pipe_index = (uint8_t)subvp_pipe->next_odm_pipe->pipe_idx; } else { pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0xF; } @@ -851,11 +857,11 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc, if (resource_is_pipe_type(phantom_pipe, OTG_MASTER) && phantom_pipe->stream == dc_state_get_paired_subvp_stream(context, subvp_pipe->stream)) { - pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst; + pipe_data->pipe_config.subvp_data.phantom_pipe_index = (uint8_t)phantom_pipe->stream_res.tg->inst; if (phantom_pipe->bottom_pipe) { - pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst; + pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = (uint8_t)phantom_pipe->bottom_pipe->plane_res.hubp->inst; } else if (phantom_pipe->next_odm_pipe) { - pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst; + pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = (uint8_t)phantom_pipe->next_odm_pipe->plane_res.hubp->inst; } else { pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0xF; } @@ -933,15 +939,15 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc, if (subvp_count == 2) { update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes); } - cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; - cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us; + cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = (uint8_t)dc->caps.subvp_pstate_allow_width_us; + cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = (uint8_t)dc->caps.subvp_vertical_int_margin_us; // Store the original watermark value for this SubVP config so we can lower it when the // MCLK switch starts wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000; - cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF; + cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = (uint16_t)(wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF); } dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); @@ -1060,10 +1066,10 @@ static void dc_build_cursor_update_payload0( payload->cursor_rect.width = hubp->cur_rect.w; payload->cursor_rect.height = hubp->cur_rect.h; - payload->enable = hubp->pos.cur_ctl.bits.cur_enable; + payload->enable = (uint8_t)hubp->pos.cur_ctl.bits.cur_enable; payload->pipe_idx = p_idx; - payload->panel_inst = panel_inst; - payload->otg_inst = pipe_ctx->stream_res.tg->inst; + payload->panel_inst = (uint8_t)panel_inst; + payload->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; } static void dc_build_cursor_position_update_payload0( @@ -1645,7 +1651,7 @@ bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv) if (dc_dmub_srv->dmub->shared_state && dc_dmub_srv->dmub->meta_info.feature_bits.bits.shared_state_link_detection) { ips_fw = &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw; - return ips_fw->signals.bits.detection_required; + return (bool)ips_fw->signals.bits.detection_required; } /* Detection may require reading scratch 0 - exit out of idle prior to the read. */ @@ -1807,7 +1813,7 @@ static void dc_dmub_srv_rb_based_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable) { - uint8_t num_cmds = 1; + uint32_t num_cmds = 1; uint32_t i; union dmub_rb_cmd cmd[2 * MAX_STREAMS + 1]; struct dmub_rb_cmd_fams2 *global_cmd = &cmd[0].fams2_config; @@ -1940,7 +1946,7 @@ void dc_dmub_srv_fams2_drr_update(struct dc *dc, cmd.fams2_drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; cmd.fams2_drr_update.header.sub_type = DMUB_CMD__FAMS2_DRR_UPDATE; - cmd.fams2_drr_update.dmub_optc_state_req.tg_inst = tg_inst; + cmd.fams2_drr_update.dmub_optc_state_req.tg_inst = (uint8_t)tg_inst; cmd.fams2_drr_update.dmub_optc_state_req.v_total_max = vtotal_max; cmd.fams2_drr_update.dmub_optc_state_req.v_total_min = vtotal_min; cmd.fams2_drr_update.dmub_optc_state_req.v_total_mid = vtotal_mid; @@ -1991,10 +1997,10 @@ void dc_dmub_srv_fams2_passthrough_flip( cmds[num_cmds].fams2_flip.header.multi_cmd_pending = 1; /* set topology info */ - cmds[num_cmds].fams2_flip.flip_info.pipe_mask = dc_plane_get_pipe_mask(state, plane_state); - if (stream_status) - cmds[num_cmds].fams2_flip.flip_info.otg_inst = stream_status->primary_otg_inst; - + cmds[num_cmds].fams2_flip.flip_info.pipe_mask = (uint8_t)dc_plane_get_pipe_mask(state, plane_state); + if (stream_status) { + cmds[num_cmds].fams2_flip.flip_info.otg_inst = (uint8_t)stream_status->primary_otg_inst; + } cmds[num_cmds].fams2_flip.flip_info.config.bits.is_immediate = plane_state->flip_immediate; /* build address info for command */ @@ -2249,6 +2255,8 @@ bool dmub_lsdma_send_tiled_to_tiled_copy_command( lsdma_data->u.tiled_copy_data.data_format = params.data_format; lsdma_data->u.tiled_copy_data.max_com = params.max_com; lsdma_data->u.tiled_copy_data.max_uncom = params.max_uncom; + lsdma_data->u.tiled_copy_data.cache_policy_src = params.src_cache_policy; + lsdma_data->u.tiled_copy_data.cache_policy_dst = params.dst_cache_policy; result = dc_wake_and_execute_dmub_cmd(dc_ctx, &cmd, wait_type); diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h index 6579cf9cce3c..ebcaf49e5961 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h @@ -240,11 +240,11 @@ struct lsdma_linear_sub_window_copy_params { uint32_t src_slice_pitch; uint32_t dst_slice_pitch; - uint32_t tmz : 1; + uint32_t tmz : 4; uint32_t element_size : 3; uint32_t src_cache_policy : 3; uint32_t dst_cache_policy : 3; - uint32_t padding : 22; + uint32_t padding : 19; }; bool dmub_lsdma_send_linear_sub_window_copy_command( @@ -286,12 +286,13 @@ struct lsdma_send_tiled_to_tiled_copy_command_params { uint32_t swizzle_mode : 5; uint32_t element_size : 3; uint32_t dcc : 1; - uint32_t tmz : 1; + uint32_t tmz : 4; uint32_t read_compress : 2; uint32_t write_compress : 2; uint32_t max_com : 2; uint32_t max_uncom : 1; - uint32_t padding : 9; + uint32_t src_cache_policy : 3; + uint32_t dst_cache_policy : 3; }; bool dmub_lsdma_send_tiled_to_tiled_copy_command( diff --git a/drivers/gpu/drm/amd/display/dc/dc_fused_io.c b/drivers/gpu/drm/amd/display/dc/dc_fused_io.c index fee69642fb93..664cb4abf623 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_fused_io.c +++ b/drivers/gpu/drm/amd/display/dc/dc_fused_io.c @@ -23,11 +23,11 @@ static bool op_i2c_convert( req->type = type; loc->is_aux = false; - loc->ddc_line = ddc_line; + loc->ddc_line = (uint8_t)ddc_line; loc->over_aux = over_aux; loc->address = op->address; loc->offset = op->offset; - loc->length = op->size; + loc->length = (uint8_t)op->size; memcpy(req->buffer, op->data, op->size); return true; @@ -84,7 +84,7 @@ static bool atomic_write_poll_read( timeout_us += timeout_per_aux_transaction_us * (io->request.u.aux.length / 16); } - if (!dm_helpers_execute_fused_io(link->ctx, link, commands, count, timeout_us)) + if (!dm_helpers_execute_fused_io(link->ctx, link, commands, count, (uint32_t)timeout_us)) return false; return commands[0].fused_io.request.status == FUSED_REQUEST_STATUS_SUCCESS; diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 77299767096f..9650cccf1b8d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -122,7 +122,7 @@ static void set_reg_field_values(struct dc_reg_value_masks *field_value_mask, field_value = va_arg(ap, uint32_t); set_reg_field_value_masks(field_value_mask, - field_value, mask, shift); + field_value, mask, (uint8_t)shift); i++; } } @@ -432,7 +432,7 @@ void generic_reg_wait(const struct dc_context *ctx, { uint32_t field_value; uint32_t reg_val; - int i; + unsigned int i; if (ctx->dmub_srv && ctx->dmub_srv->reg_helper_offload.gather_in_progress) { @@ -447,7 +447,7 @@ void generic_reg_wait(const struct dc_context *ctx, * This value comes from experiments. * */ - ASSERT(delay_between_poll_us * time_out_num_tries <= 3000000); + ASSERT(delay_between_poll_us * time_out_num_tries <= 3000000u); for (i = 0; i <= time_out_num_tries; i++) { if (i) { @@ -459,7 +459,7 @@ void generic_reg_wait(const struct dc_context *ctx, reg_val = dm_read_reg(ctx, addr); - field_value = get_reg_field_value_ex(reg_val, mask, shift); + field_value = get_reg_field_value_ex(reg_val, mask, (uint8_t)shift); if (field_value == condition_value) { if (i * delay_between_poll_us > 1000) @@ -525,7 +525,7 @@ uint32_t generic_indirect_reg_get(const struct dc_context *ctx, mask = va_arg(ap, uint32_t); field_value = va_arg(ap, uint32_t *); - *field_value = get_reg_field_value_ex(value, mask, shift); + *field_value = get_reg_field_value_ex(value, mask, (uint8_t)shift); i++; } @@ -554,7 +554,7 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx, mask = va_arg(ap, uint32_t); field_value = va_arg(ap, uint32_t); - reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift); + reg_val = set_reg_field_value_ex(reg_val, field_value, mask, (uint8_t)shift); i++; } @@ -584,7 +584,7 @@ uint32_t generic_indirect_reg_update_ex_sync(const struct dc_context *ctx, mask = va_arg(ap, uint32_t); field_value = va_arg(ap, uint32_t); - reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift); + reg_val = set_reg_field_value_ex(reg_val, field_value, mask, (uint8_t)shift); i++; } @@ -615,7 +615,7 @@ uint32_t generic_indirect_reg_get_sync(const struct dc_context *ctx, mask = va_arg(ap, uint32_t); field_value = va_arg(ap, uint32_t *); - *field_value = get_reg_field_value_ex(value, mask, shift); + *field_value = get_reg_field_value_ex(value, mask, (uint8_t)shift); i++; } diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 7c38fa6f8cb1..32f7c7c076c8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -64,35 +64,6 @@ struct dc_stream_status { bool fpo_in_use; }; -enum hubp_dmdata_mode { - DMDATA_SW_MODE, - DMDATA_HW_MODE -}; - -struct dc_dmdata_attributes { - /* Specifies whether dynamic meta data will be updated by software - * or has to be fetched by hardware (DMA mode) - */ - enum hubp_dmdata_mode dmdata_mode; - /* Specifies if current dynamic meta data is to be used only for the current frame */ - bool dmdata_repeat; - /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */ - uint32_t dmdata_size; - /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */ - bool dmdata_updated; - /* If hardware mode is used, the base address where DMDATA surface is located */ - PHYSICAL_ADDRESS_LOC address; - /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */ - bool dmdata_qos_mode; - /* If qos_mode = 1, this is the QOS value to be used: */ - uint32_t dmdata_qos_level; - /* Specifies the value in unit of REFCLK cycles to be added to the - * current time to produce the Amortized deadline for Dynamic Metadata chunk request - */ - uint32_t dmdata_dl_delta; - /* An unbounded array of uint32s, represents software dmdata to be loaded */ - uint32_t *dmdata_sw_data; -}; struct dc_writeback_info { bool wb_enabled; @@ -146,6 +117,15 @@ union stream_update_flags { uint32_t fams_changed : 1; uint32_t scaler_sharpener : 1; uint32_t sharpening_required : 1; + uint32_t cursor_attr : 1; + uint32_t cursor_pos : 1; + uint32_t periodic_interrupt : 1; + uint32_t info_frame : 1; + uint32_t dmdata : 1; + uint32_t dither : 1; + uint32_t func_shaper : 1; + uint32_t lut3d_func : 1; + uint32_t reserved : 11; /* adjust when adding new flags */ } bits; uint32_t raw; @@ -324,6 +304,7 @@ struct dc_stream_state { enum dc_drr_trigger_mode drr_trigger_mode; struct dc_update_scratch_space *update_scratch; + bool firmware_controlled_hdr_info_packet; }; #define ABM_LEVEL_IMMEDIATE_DISABLE 255 @@ -517,6 +498,9 @@ struct surface_update_descriptor dc_check_update_surfaces_for_stream( int surface_count, struct dc_stream_update *stream_update); +struct dc_link *dc_stream_get_link( + const struct dc_stream_state *dc_stream); + /** * Create a new default stream for the requested sink */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index c08d5c005df6..12ce4a059231 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -790,6 +790,36 @@ struct dc_clock_config { uint32_t current_clock_khz;/*current clock in use*/ }; +enum hubp_dmdata_mode { + DMDATA_SW_MODE, + DMDATA_HW_MODE +}; + +struct dc_dmdata_attributes { + /* Specifies whether dynamic meta data will be updated by software + * or has to be fetched by hardware (DMA mode) + */ + enum hubp_dmdata_mode dmdata_mode; + /* Specifies if current dynamic meta data is to be used only for the current frame */ + bool dmdata_repeat; + /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */ + uint32_t dmdata_size; + /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */ + bool dmdata_updated; + /* If hardware mode is used, the base address where DMDATA surface is located */ + PHYSICAL_ADDRESS_LOC address; + /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */ + bool dmdata_qos_mode; + /* If qos_mode = 1, this is the QOS value to be used: */ + uint32_t dmdata_qos_level; + /* Specifies the value in unit of REFCLK cycles to be added to the + * current time to produce the Amortized deadline for Dynamic Metadata chunk request + */ + uint32_t dmdata_dl_delta; + /* An unbounded array of uint32s, represents software dmdata to be loaded */ + uint32_t *dmdata_sw_data; +}; + struct hw_asic_id { uint32_t chip_id; uint32_t chip_family; @@ -1493,28 +1523,4 @@ struct dc_validation_dpia_set { uint32_t required_bw; }; -enum dc_cm_lut_swizzle { - CM_LUT_3D_SWIZZLE_LINEAR_RGB, - CM_LUT_3D_SWIZZLE_LINEAR_BGR, - CM_LUT_1D_PACKED_LINEAR -}; - -enum dc_cm_lut_pixel_format { - CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB, - CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB, - CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB, - CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB, - CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10, - CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10 -}; - -enum dc_cm_lut_size { - CM_LUT_SIZE_NONE, - CM_LUT_SIZE_999, - CM_LUT_SIZE_171717, - CM_LUT_SIZE_333333, - CM_LUT_SIZE_454545, - CM_LUT_SIZE_656565, -}; - #endif /* DC_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c index a72bf413fad6..21dcb812fbf7 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c @@ -576,7 +576,7 @@ void dccg31_set_dtbclk_dto( // phase / modulo = dtbclk / dtbclk ref modulo = params->ref_dtbclk_khz * 1000; - phase = div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1), + phase = (uint32_t)div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1), params->ref_dtbclk_khz); REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], @@ -620,7 +620,7 @@ void dccg31_set_audio_dtbclk_dto( // phase / modulo = dtbclk / dtbclk ref modulo = params->ref_dtbclk_khz * 1000; - phase = div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1), + phase = (uint32_t)div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1), params->ref_dtbclk_khz); diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c index 97605a416031..417ed9d0e6bb 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c @@ -610,11 +610,13 @@ void dccg401_set_dp_dto( * int = target_pix_rate / reference_clock * phase = target_pix_rate - int * reference_clock, * modulo = reference_clock */ - dto_integer = div_u64(params->pixclk_hz, dto_modulo_hz); + + /* dto_modulo_hz = refclk (~100 MHz), well within uint32_t range */ + dto_integer = div_u64(params->pixclk_hz, (uint32_t)dto_modulo_hz); dto_phase_hz = params->pixclk_hz - dto_integer * dto_modulo_hz; - if (dto_phase_hz <= 0 && dto_integer <= 0) { - /* negative pixel rate should never happen */ + if (dto_phase_hz == 0 && dto_integer == 0) { + /* zero pixel rate should never happen */ BREAK_TO_DEBUGGER(); return; } @@ -656,25 +658,25 @@ void dccg401_set_dp_dto( dccg401_set_dtbclk_p_src(dccg, params->clk_src, params->otg_inst); - REG_WRITE(DP_DTO_PHASE[params->otg_inst], dto_phase_hz); - REG_WRITE(DP_DTO_MODULO[params->otg_inst], dto_modulo_hz); + REG_WRITE(DP_DTO_PHASE[params->otg_inst], (uint32_t)dto_phase_hz); + REG_WRITE(DP_DTO_MODULO[params->otg_inst], (uint32_t)dto_modulo_hz); switch (params->otg_inst) { case 0: REG_UPDATE(OTG_PIXEL_RATE_DIV, - DPDTO0_INT, dto_integer); + DPDTO0_INT, (uint32_t)dto_integer); break; case 1: REG_UPDATE(OTG_PIXEL_RATE_DIV, - DPDTO1_INT, dto_integer); + DPDTO1_INT, (uint32_t)dto_integer); break; case 2: REG_UPDATE(OTG_PIXEL_RATE_DIV, - DPDTO2_INT, dto_integer); + DPDTO2_INT, (uint32_t)dto_integer); break; case 3: REG_UPDATE(OTG_PIXEL_RATE_DIV, - DPDTO3_INT, dto_integer); + DPDTO3_INT, (uint32_t)dto_integer); break; default: BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c index b813310763e5..9612f4498ef6 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c @@ -6,6 +6,7 @@ #include "core_types.h" #include "dcn35/dcn35_dccg.h" #include "dcn42_dccg.h" +#include "dcn20/dcn20_dccg.h" #define TO_DCN_DCCG(dccg)\ container_of(dccg, struct dcn_dccg, base) @@ -306,6 +307,7 @@ static const struct dccg_funcs dccg42_funcs = { .dccg_root_gate_disable_control = dccg35_root_gate_disable_control, .dccg_read_reg_state = dccg31_read_reg_state, .dccg_enable_global_fgcg = dccg42_enable_global_fgcg, + .allow_clock_gating = dccg2_allow_clock_gating }; struct dccg *dccg42_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c index 673bb87d2c17..eee58f946fae 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c @@ -321,7 +321,7 @@ static int read_channel_reply(struct dce_aux *engine, uint32_t size, uint32_t aux_sw_data_val; REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val); - buffer[i] = aux_sw_data_val; + buffer[i] = (uint8_t)aux_sw_data_val; ++i; } @@ -375,7 +375,7 @@ static enum aux_return_code_type get_channel_status( (value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK)) return AUX_RET_ERROR_INVALID_REPLY; - *returned_bytes = get_reg_field_value(value, + *returned_bytes = (uint8_t)get_reg_field_value(value, AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 25c13822fede..ac9eed58c415 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -162,11 +162,9 @@ static bool calculate_fb_and_fractional_fb_divider( feedback_divider *= (uint64_t) (calc_pll_cs->fract_fb_divider_precision_factor); - *feedback_divider_param = - div_u64_rem( - feedback_divider, - calc_pll_cs->fract_fb_divider_factor, - fract_feedback_divider_param); + *feedback_divider_param = (uint32_t)div_u64_rem( + feedback_divider, calc_pll_cs->fract_fb_divider_factor, + fract_feedback_divider_param); if (*feedback_divider_param != 0) return true; @@ -240,7 +238,7 @@ static bool calc_fb_divider_checking_tolerance( pll_settings->calculated_pix_clk_100hz = actual_calculated_clock_100hz; pll_settings->vco_freq = - div_u64((u64)actual_calculated_clock_100hz * post_divider, 10); + (uint32_t)div_u64((u64)actual_calculated_clock_100hz * post_divider, 10); return true; } return false; @@ -440,8 +438,7 @@ static bool pll_adjust_pix_clk( bp_adjust_pixel_clock_params. encoder_object_id = pix_clk_params->encoder_object_id; bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type; - bp_adjust_pixel_clock_params. - ss_enable = pix_clk_params->flags.ENABLE_SS; + bp_adjust_pixel_clock_params.ss_enable = pix_clk_params->flags.ENABLE_SS != 0; bp_result = clk_src->bios->funcs->adjust_pixel_clock( clk_src->bios, &bp_adjust_pixel_clock_params); if (bp_result == BP_RESULT_OK) { @@ -958,7 +955,7 @@ static bool dce112_program_pix_clk( dce112_program_pixel_clk_resync(clk_src, pix_clk_params->signal_type, pix_clk_params->color_depth, - pix_clk_params->flags.SUPPORT_YCBCR420); + pix_clk_params->flags.SUPPORT_YCBCR420 != 0); return true; } @@ -1059,7 +1056,7 @@ static bool dcn31_program_pix_clk( dce112_program_pixel_clk_resync(clk_src, pix_clk_params->signal_type, pix_clk_params->color_depth, - pix_clk_params->flags.SUPPORT_YCBCR420); + pix_clk_params->flags.SUPPORT_YCBCR420 != 0); } return true; @@ -1162,7 +1159,7 @@ static bool dcn401_program_pix_clk( dce112_program_pixel_clk_resync(clk_src, pix_clk_params->signal_type, pix_clk_params->color_depth, - pix_clk_params->flags.SUPPORT_YCBCR420); + pix_clk_params->flags.SUPPORT_YCBCR420 != 0); } return true; @@ -1211,9 +1208,8 @@ static bool get_pixel_clk_frequency_100hz( */ modulo_hz = REG_READ(MODULO[inst]); if (modulo_hz) - *pixel_clk_khz = div_u64((uint64_t)clock_hz* - dp_dto_ref_khz*10, - modulo_hz); + *pixel_clk_khz = (unsigned int)div_u64((uint64_t)clock_hz * + dp_dto_ref_khz * 10, modulo_hz); else *pixel_clk_khz = 0; } else { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c index fe239a96121e..05892ab4529f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c @@ -120,7 +120,7 @@ static void process_channel_reply( uint32_t i2c_data; REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); - *buffer++ = i2c_data; + *buffer++ = (uint8_t)i2c_data; --length; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c index 52e05b9185f1..e64b3b6bff5c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c @@ -75,7 +75,7 @@ static void release_engine_dce_sw( static bool wait_for_scl_high_sw( struct dc_context *ctx, struct ddc *ddc, - uint16_t clock_delay_div_4) + uint32_t clock_delay_div_4) { (void)ctx; uint32_t scl_retry = 0; @@ -97,7 +97,7 @@ static bool wait_for_scl_high_sw( static bool write_byte_sw( struct dc_context *ctx, struct ddc *ddc_handle, - uint16_t clock_delay_div_4, + uint32_t clock_delay_div_4, uint8_t byte) { int32_t shift = 7; @@ -154,7 +154,7 @@ static bool write_byte_sw( static bool read_byte_sw( struct dc_context *ctx, struct ddc *ddc_handle, - uint16_t clock_delay_div_4, + uint32_t clock_delay_div_4, uint8_t *byte, bool more) { @@ -214,7 +214,7 @@ static bool read_byte_sw( static bool stop_sync_sw( struct dc_context *ctx, struct ddc *ddc_handle, - uint16_t clock_delay_div_4) + uint32_t clock_delay_div_4) { uint32_t retry = 0; @@ -251,7 +251,7 @@ static bool stop_sync_sw( static bool i2c_write_sw( struct dc_context *ctx, struct ddc *ddc_handle, - uint16_t clock_delay_div_4, + uint32_t clock_delay_div_4, uint8_t address, uint32_t length, const uint8_t *data) @@ -273,7 +273,7 @@ static bool i2c_write_sw( static bool i2c_read_sw( struct dc_context *ctx, struct ddc *ddc_handle, - uint16_t clock_delay_div_4, + uint32_t clock_delay_div_4, uint8_t address, uint32_t length, uint8_t *data) @@ -298,7 +298,7 @@ static bool i2c_read_sw( static bool start_sync_sw( struct dc_context *ctx, struct ddc *ddc_handle, - uint16_t clock_delay_div_4) + uint32_t clock_delay_div_4) { uint32_t retry = 0; @@ -399,7 +399,7 @@ static void dce_i2c_sw_engine_submit_channel_request(struct dce_i2c_sw *engine, struct i2c_request_transaction_data *req) { struct ddc *ddc = engine->ddc; - uint16_t clock_delay_div_4 = engine->clock_delay >> 2; + uint32_t clock_delay_div_4 = engine->clock_delay >> 2; /* send sync (start / repeated start) */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c index ee55ec21d270..72c0950808ec 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c @@ -171,7 +171,7 @@ static void dce_ipp_program_input_lut( struct input_pixel_processor *ipp, const struct dc_gamma *gamma) { - int i; + unsigned int i; struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); /* power on LUT memory */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 5f40ae9e3120..c6a20378121b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -815,6 +815,7 @@ static bool dce110_link_encoder_validate_hdmi_output( { enum dc_color_depth max_deep_color = enc110->base.features.max_hdmi_deep_color; + int max_hdmi_pixel_clock_khz = (int)enc110->base.features.max_hdmi_pixel_clock; if (max_deep_color < crtc_timing->display_color_depth) return false; @@ -825,7 +826,7 @@ static bool dce110_link_encoder_validate_hdmi_output( return false; if ((adjusted_pix_clk_khz == 0) || - (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock)) + (adjusted_pix_clk_khz > max_hdmi_pixel_clock_khz)) return false; /* DCE11 HW does not support 420 */ @@ -1102,7 +1103,9 @@ void dce110_link_encoder_hw_init( ASSERT(result == BP_RESULT_OK); } - aux_initialize(enc110); + + if (enc110->aux_regs) + aux_initialize(enc110); /* reinitialize HPD. * hpd_initialize() will pass DIG_FE id to HW context. diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c index de31fb1b6819..31a9181c6a2b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c @@ -209,7 +209,7 @@ static void dce_driver_set_backlight(struct panel_cntl *panel_cntl, if (pwm_period_bitcnt == 0) bit_count = 16; else - bit_count = pwm_period_bitcnt; + bit_count = (uint8_t)pwm_period_bitcnt; /* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */ masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1); @@ -224,7 +224,7 @@ static void dce_driver_set_backlight(struct panel_cntl *panel_cntl, * components shift by bitCount then mask 16 bits and add rounding bit * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0 */ - backlight_16bit = active_duty_cycle >> bit_count; + backlight_16bit = (uint32_t)(active_duty_cycle >> bit_count); backlight_16bit &= 0xFFFF; backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index c1448ae47366..b3640682fa60 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -802,7 +802,7 @@ static void program_bit_depth_reduction( ASSERT(depth <= COLOR_DEPTH_121212); /* Invalid clamp bit depth */ - spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED; + spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED != 0; /* Default to 12 bit truncation without rounding */ trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_12BIT; trunc_mode = DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE; @@ -835,9 +835,9 @@ static void program_bit_depth_reduction( spatial_dither_enable, DCP_SPATIAL_DITHER_MODE_A_AA_A, DCP_SPATIAL_DITHER_DEPTH_30BPP, - bit_depth_params->flags.FRAME_RANDOM, - bit_depth_params->flags.RGB_RANDOM, - bit_depth_params->flags.HIGHPASS_RANDOM); + bit_depth_params->flags.FRAME_RANDOM != 0, + bit_depth_params->flags.RGB_RANDOM != 0, + bit_depth_params->flags.HIGHPASS_RANDOM != 0); } #if defined(CONFIG_DRM_AMD_DC_SI) @@ -1173,13 +1173,13 @@ bool dce_transform_get_optimal_number_of_taps( { struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); int pixel_width = scl_data->viewport.width; - int max_num_of_lines; + uint32_t max_num_of_lines; if (xfm_dce->prescaler_on && (scl_data->viewport.width > scl_data->recout.width)) pixel_width = scl_data->recout.width; - max_num_of_lines = dce_transform_get_max_num_of_supported_lines( + max_num_of_lines = (uint32_t)dce_transform_get_max_num_of_supported_lines( xfm_dce, scl_data->lb_params.depth, pixel_width); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c index 806b5709c9e7..2f4d368bd3fd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c @@ -58,7 +58,7 @@ static void dmub_abm_enable_fractional_pwm(struct dc_context *dc) union dmub_rb_cmd cmd; uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == false) ? 1 : 0; uint32_t edp_id_count = dc->dc_edp_id_count; - int i; + unsigned int i; uint8_t panel_mask = 0; for (i = 0; i < edp_id_count; i++) @@ -176,7 +176,7 @@ void dmub_abm_init_config(struct abm *abm, cmd.abm_init_config.header.type = DMUB_CMD__ABM; cmd.abm_init_config.header.sub_type = DMUB_CMD__ABM_INIT_CONFIG; cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr; - cmd.abm_init_config.abm_init_config_data.bytes = bytes; + cmd.abm_init_config.abm_init_config_data.bytes = (uint16_t)bytes; cmd.abm_init_config.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; cmd.abm_init_config.abm_init_config_data.panel_mask = panel_mask; @@ -237,7 +237,7 @@ bool dmub_abm_save_restore( cmd.abm_save_restore.header.sub_type = DMUB_CMD__ABM_SAVE_RESTORE; cmd.abm_save_restore.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr; - cmd.abm_save_restore.abm_init_config_data.bytes = bytes; + cmd.abm_save_restore.abm_init_config_data.bytes = (uint16_t)bytes; cmd.abm_save_restore.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; cmd.abm_save_restore.abm_init_config_data.panel_mask = panel_mask; @@ -265,10 +265,10 @@ bool dmub_abm_set_pipe(struct abm *abm, memset(&cmd, 0, sizeof(cmd)); cmd.abm_set_pipe.header.type = DMUB_CMD__ABM; cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE; - cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst; - cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = pwrseq_inst; - cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = option; - cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = panel_inst; + cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = (uint8_t)otg_inst; + cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = (uint8_t)pwrseq_inst; + cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = (uint8_t)option; + cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = (uint8_t)panel_inst; cmd.abm_set_pipe.abm_set_pipe_data.ramping_boundary = ramping_boundary; cmd.abm_set_pipe.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pipe_data); @@ -308,7 +308,7 @@ bool dmub_abm_set_event(struct abm *abm, unsigned int scaling_enable, unsigned i memset(&cmd, 0, sizeof(cmd)); cmd.abm_set_event.header.type = DMUB_CMD__ABM; cmd.abm_set_event.header.sub_type = DMUB_CMD__ABM_SET_EVENT; - cmd.abm_set_event.abm_set_event_data.vb_scaling_enable = scaling_enable; + cmd.abm_set_event.abm_set_event_data.vb_scaling_enable = (uint8_t)scaling_enable; cmd.abm_set_event.abm_set_event_data.vb_scaling_strength_mapping = scaling_strength_map; cmd.abm_set_event.abm_set_event_data.panel_mask = (1<mpcc_inst = pipe_ctx->plane_res.mpcc_inst; if (pipe_ctx->plane_res.dpp) - copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; + copy_settings_data->dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst; else copy_settings_data->dpp_inst = 0; if (pipe_ctx->stream_res.opp) - copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst; + copy_settings_data->opp_inst = (uint8_t)pipe_ctx->stream_res.opp->inst; else copy_settings_data->opp_inst = 0; if (pipe_ctx->stream_res.tg) - copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; + copy_settings_data->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; else copy_settings_data->otg_inst = 0; // Misc copy_settings_data->use_phy_fsm = link->ctx->dc->debug.psr_power_use_phy_fsm; - copy_settings_data->psr_level = psr_context->psr_level.u32all; + copy_settings_data->psr_level = (uint16_t)psr_context->psr_level.u32all; copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations; copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations; - copy_settings_data->frame_delay = psr_context->frame_delay; + copy_settings_data->frame_delay = (uint8_t)psr_context->frame_delay; copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq; - copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline; + copy_settings_data->init_sdp_deadline = (uint16_t)psr_context->sdpTransmitLineNumDeadline; copy_settings_data->debug.u32All = 0; copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR; copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c index 0af1b8e0a49e..9b50bf1d80fc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c @@ -151,22 +151,23 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub, copy_settings_data->digfe_inst = replay_context->digfe_inst; if (pipe_ctx->plane_res.dpp) - copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; + copy_settings_data->dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst; else copy_settings_data->dpp_inst = 0; + if (pipe_ctx->stream_res.tg) - copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; + copy_settings_data->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; else copy_settings_data->otg_inst = 0; copy_settings_data->dpphy_inst = link->link_enc->transmitter; // Misc - copy_settings_data->line_time_in_ns = replay_context->line_time_in_ns; - copy_settings_data->panel_inst = panel_inst; - copy_settings_data->debug.u32All = link->replay_settings.config.debug_flags; + copy_settings_data->line_time_in_ns = (uint16_t)replay_context->line_time_in_ns; + copy_settings_data->panel_inst = (uint16_t)panel_inst; + copy_settings_data->debug.u32All = (uint16_t)link->replay_settings.config.debug_flags; copy_settings_data->pixel_deviation_per_line = link->dpcd_caps.pr_info.pixel_deviation_per_line; - copy_settings_data->max_deviation_line = link->dpcd_caps.pr_info.max_deviation_line; + copy_settings_data->max_deviation_line = (uint16_t)link->dpcd_caps.pr_info.max_deviation_line; copy_settings_data->smu_optimizations_en = link->replay_settings.replay_smu_opt_enable; copy_settings_data->replay_timing_sync_supported = link->replay_settings.config.replay_timing_sync_supported; copy_settings_data->replay_support_fast_resync_in_ultra_sleep_mode = link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode; @@ -193,13 +194,13 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub, copy_settings_data->flags.bitfields.alpm_mode = (enum dmub_alpm_mode)link->replay_settings.config.alpm_mode; if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) { - copy_settings_data->auxless_alpm_data.lfps_setup_ns = dc->dc->debug.auxless_alpm_lfps_setup_ns; - copy_settings_data->auxless_alpm_data.lfps_period_ns = dc->dc->debug.auxless_alpm_lfps_period_ns; - copy_settings_data->auxless_alpm_data.lfps_silence_ns = dc->dc->debug.auxless_alpm_lfps_silence_ns; + copy_settings_data->auxless_alpm_data.lfps_setup_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_setup_ns; + copy_settings_data->auxless_alpm_data.lfps_period_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_period_ns; + copy_settings_data->auxless_alpm_data.lfps_silence_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_silence_ns; copy_settings_data->auxless_alpm_data.lfps_t1_t2_override_us = - dc->dc->debug.auxless_alpm_lfps_t1t2_us; + (uint16_t)dc->dc->debug.auxless_alpm_lfps_t1t2_us; copy_settings_data->auxless_alpm_data.lfps_t1_t2_offset_us = - dc->dc->debug.auxless_alpm_lfps_t1t2_offset_us; + (uint16_t)dc->dc->debug.auxless_alpm_lfps_t1t2_offset_us; copy_settings_data->auxless_alpm_data.lttpr_count = link->dc->link_srv->dp_get_lttpr_count(link); } diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c index 53c03364f5d4..20c18ac87998 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c @@ -98,7 +98,7 @@ static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz) set_reg_field_value( value, - pix_dur, + (uint32_t)pix_dur, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c index c702a30563f9..502a2d9b155f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c @@ -75,8 +75,8 @@ void cm_helper_read_color_matrices(struct dc_context *ctx, csc_c11, ®val0, csc_c12, ®val1); - regval[2 * i] = regval0; - regval[(2 * i) + 1] = regval1; + regval[2 * i] = (uint16_t)regval0; + regval[(2 * i) + 1] = (uint16_t)regval1; i++; } @@ -342,8 +342,8 @@ bool cm_helper_translate_curve_to_hw_format(struct dc_context *ctx, struct pwl_result_data *rgb_minus_1; int32_t region_start, region_end; - int32_t i; - uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; + int32_t k; + uint32_t i, j, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; if (output_tf == NULL || lut_params == NULL || output_tf->type == TF_TYPE_BYPASS) return false; @@ -398,8 +398,8 @@ bool cm_helper_translate_curve_to_hw_format(struct dc_context *ctx, if (j == hw_points - 1) break; if (i >= TRANSFER_FUNC_POINTS) { - DC_LOG_ERROR("Index out of bounds: i=%d, TRANSFER_FUNC_POINTS=%d\n", - i, TRANSFER_FUNC_POINTS); + DC_LOG_ERROR("Index out of bounds: i=%u, TRANSFER_FUNC_POINTS=%u\n", + i, (uint32_t)TRANSFER_FUNC_POINTS); return false; } rgb_resulted[j].red = output_tf->tf_pts.red[i]; @@ -547,8 +547,8 @@ bool cm_helper_translate_curve_to_degamma_hw_format( struct pwl_result_data *rgb_plus_1; int32_t region_start, region_end; - int32_t i; - uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; + int32_t k; + uint32_t i, j, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; if (output_tf == NULL || lut_params == NULL || output_tf->type == TF_TYPE_BYPASS) return false; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c index baf663b661c8..feb6ca92802c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c @@ -59,7 +59,7 @@ unsigned int snprintf_count(char *pbuf, unsigned int bufsize, const char *fmt, . va_end(args); if (ret_vsnprintf > 0) { - if (ret_vsnprintf < bufsize) + if ((unsigned int)ret_vsnprintf < bufsize) chars_printed = ret_vsnprintf; else chars_printed = bufsize - 1; @@ -73,7 +73,7 @@ static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned i { struct dc_context *dc_ctx = dc->ctx; struct dcn_hubbub_wm wm; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -111,7 +111,7 @@ static unsigned int dcn10_get_hubp_states(struct dc *dc, char *pBuf, unsigned in { struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -189,7 +189,7 @@ static unsigned int dcn10_get_hubp_states(struct dc *dc, char *pBuf, unsigned in static unsigned int dcn10_get_rq_states(struct dc *dc, char *pBuf, unsigned int bufSize) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -231,7 +231,7 @@ static unsigned int dcn10_get_rq_states(struct dc *dc, char *pBuf, unsigned int static unsigned int dcn10_get_dlg_states(struct dc *dc, char *pBuf, unsigned int bufSize) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -288,7 +288,7 @@ static unsigned int dcn10_get_dlg_states(struct dc *dc, char *pBuf, unsigned int static unsigned int dcn10_get_ttu_states(struct dc *dc, char *pBuf, unsigned int bufSize) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -328,7 +328,7 @@ static unsigned int dcn10_get_ttu_states(struct dc *dc, char *pBuf, unsigned int static unsigned int dcn10_get_cm_states(struct dc *dc, char *pBuf, unsigned int bufSize) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -383,7 +383,7 @@ static unsigned int dcn10_get_cm_states(struct dc *dc, char *pBuf, unsigned int static unsigned int dcn10_get_mpcc_states(struct dc *dc, char *pBuf, unsigned int bufSize) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -414,7 +414,7 @@ static unsigned int dcn10_get_mpcc_states(struct dc *dc, char *pBuf, unsigned in static unsigned int dcn10_get_otg_states(struct dc *dc, char *pBuf, unsigned int bufSize) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -491,7 +491,7 @@ static unsigned int dcn10_get_clock_states(struct dc *dc, char *pBuf, unsigned i static void dcn10_clear_otpc_underflow(struct dc *dc) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; for (i = 0; i < pool->timing_generator_count; i++) { struct timing_generator *tg = pool->timing_generators[i]; @@ -508,7 +508,7 @@ static void dcn10_clear_otpc_underflow(struct dc *dc) static void dcn10_clear_hubp_underflow(struct dc *dc) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { struct hubp *hubp = pool->hubps[i]; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c index f73c5f42ea68..7163426a0920 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c @@ -696,7 +696,7 @@ static void wbscl_set_scaler_filter( for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) { for (pair = 0; pair < tap_pairs; pair++) { even_coef = filter[phase * taps + 2 * pair]; - if ((pair * 2 + 1) < taps) + if ((uint32_t)(pair * 2 + 1) < taps) odd_coef = filter[phase * taps + 2 * pair + 1]; else odd_coef = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c index 9dbccf58dde5..bfd5515c2f4f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c @@ -172,11 +172,13 @@ bool cm3_helper_translate_curve_to_hw_format(struct dc_context *ctx, hw_points = fixpoint ? (hw_points - 1) : hw_points; j = 0; - for (k = 0; k < (region_end - region_start); k++) { + uint32_t region_span = (uint32_t)(region_end - region_start); + for (k = 0; k < region_span; k++) { increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); start_index = (region_start + k + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; - for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; + int32_t index_end = (int32_t)(start_index + NUMBER_SW_SEGMENTS); + for (i = start_index; i < index_end; i += increment) { if (j == hw_points) break; @@ -258,7 +260,7 @@ bool cm3_helper_translate_curve_to_hw_format(struct dc_context *ctx, uint32_t green_clamp; uint32_t blue_clamp; - if (i >= hw_points) { + if ((uint32_t)i >= hw_points) { if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) rgb_plus_1->red = dc_fixpt_add(rgb->red, rgb_minus_1->delta_red); diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c index 6f2a0d5d963b..62fe5c3b18dc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c @@ -40,8 +40,8 @@ #define FN(reg_name, field_name) \ mcif_wb30->mcif_wb_shift->field_name, mcif_wb30->mcif_wb_mask->field_name -#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8 -#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40 +#define MCIF_ADDR(addr) ((uint32_t)((((unsigned long long)(addr) & 0xffffffffffULL) + 0xFEULL) >> 8)) +#define MCIF_ADDR_HIGH(addr) ((uint32_t)(((unsigned long long)(addr)) >> 40)) /* wbif programming guide: * 1. set up wbif parameter: diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c index 13e14aad3daa..872ea3646023 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c @@ -622,10 +622,11 @@ static bool dcn10_link_encoder_validate_hdmi_output( { enum dc_color_depth max_deep_color = enc10->base.features.max_hdmi_deep_color; + uint32_t pix_clk_100hz = (uint32_t)adjusted_pix_clk_100hz; // check pixel clock against edid specified max TMDS clk if (edid_caps->max_tmds_clk_mhz != 0 && - adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000) + pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000) return false; if (max_deep_color < crtc_timing->display_color_depth) @@ -633,11 +634,11 @@ static bool dcn10_link_encoder_validate_hdmi_output( if (crtc_timing->display_color_depth < COLOR_DEPTH_888) return false; - if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10)) + if (pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10)) return false; - if ((adjusted_pix_clk_100hz == 0) || - (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10))) + if ((pix_clk_100hz == 0) || + (pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10))) return false; /* DCE11 HW does not support 420 */ @@ -647,7 +648,7 @@ static bool dcn10_link_encoder_validate_hdmi_output( if ((!enc10->base.features.flags.bits.HDMI_6GB_EN || enc10->base.ctx->dc->debug.hdmi20_disable) && - adjusted_pix_clk_100hz >= 3000000) + pix_clk_100hz >= 3000000) return false; if (enc10->base.ctx->dc->debug.hdmi20_disable && crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c index e93be7b6d9b0..c14fb51c2611 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c @@ -470,7 +470,11 @@ void enc3_stream_encoder_update_dp_info_packets( &info_frame->spd, true); } - if (info_frame->hdrsmd.valid) { + /* While smart power oled is enabled DMUB is scanning the contents of each frame + * and updating the HDR infopacket contents. Therefore we transition the infopacket + * programming control to DMUB while Smart Power OLED is enabled. + */ + if (info_frame->hdrsmd.valid && !info_frame->firmware_controlled_hdr_info_packet) { enc->vpg->funcs->update_generic_info_packet( enc->vpg, 3, /* packetIndex */ diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c index 2d33ed0c062d..79d0c2896d29 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c @@ -43,7 +43,7 @@ #undef FN #define FN(reg_name, field_name) \ - enc1->se_shift->field_name, enc1->se_mask->field_name + (uint8_t)enc1->se_shift->field_name, enc1->se_mask->field_name #define VBI_LINE_0 0 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h index 4b5a9594f279..9c607b24ec1c 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h @@ -121,8 +121,6 @@ LE_SF(DIO_CLK_CNTL, SYMCLKC_G_HDCP_GATE_DIS, mask_sh),\ LE_SF(DIO_CLK_CNTL, SYMCLKD_G_HDCP_GATE_DIS, mask_sh),\ LE_SF(DIO_CLK_CNTL, SYMCLKE_G_HDCP_GATE_DIS, mask_sh),\ - LE_SF(DIO_CLK_CNTL, SYMCLKF_G_HDCP_GATE_DIS, mask_sh),\ - LE_SF(DIO_CLK_CNTL, SYMCLKG_G_HDCP_GATE_DIS, mask_sh) void dcn42_link_encoder_construct( struct dcn20_link_encoder *enc20, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c index 65afbfcaa96b..55ddb9cf8a52 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c @@ -23,7 +23,7 @@ #undef FN #define FN(reg_name, field_name) \ - enc1->se_shift->field_name, enc1->se_mask->field_name + (uint8_t)enc1->se_shift->field_name, enc1->se_mask->field_name #define VBI_LINE_0 0 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 @@ -401,7 +401,7 @@ void enc42_se_enable_audio_clock( { struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - REG_UPDATE(DIG_FE_AUDIO_CNTL, APG_CLOCK_ENABLE, !!enable); + REG_UPDATE(DIG_FE_AUDIO_CNTL, APG_CLOCK_ENABLE, enable); } diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c index 288d22a16cf2..5c00ef423968 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c +++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c @@ -45,25 +45,22 @@ void scaler_settings_calculation(struct dcn_bw_internal_vars *v) if (v->source_scan[k] == dcn_bw_hor) { v->h_ratio[k] = v->viewport_width[k] / v->scaler_rec_out_width[k]; v->v_ratio[k] = v->viewport_height[k] / v->scaler_recout_height[k]; - } - else { + } else { v->h_ratio[k] = v->viewport_height[k] / v->scaler_rec_out_width[k]; v->v_ratio[k] = v->viewport_width[k] / v->scaler_recout_height[k]; } - } - else { + } else { if (v->source_scan[k] == dcn_bw_hor) { - v->h_ratio[k] =dcn_bw_max2(v->viewport_width[k] / v->scaler_rec_out_width[k], v->viewport_height[k] / v->scaler_recout_height[k]); - } - else { - v->h_ratio[k] =dcn_bw_max2(v->viewport_height[k] / v->scaler_rec_out_width[k], v->viewport_width[k] / v->scaler_recout_height[k]); + v->h_ratio[k] = dcn_bw_max2(v->viewport_width[k] / v->scaler_rec_out_width[k], v->viewport_height[k] / v->scaler_recout_height[k]); + } else { + v->h_ratio[k] = dcn_bw_max2(v->viewport_height[k] / v->scaler_rec_out_width[k], v->viewport_width[k] / v->scaler_recout_height[k]); } v->v_ratio[k] = v->h_ratio[k]; } - if (v->interlace_output[k] == 1.0) { - v->v_ratio[k] = 2.0 * v->v_ratio[k]; + if (v->interlace_output[k] == 1.0f) { + v->v_ratio[k] = 2.0f * v->v_ratio[k]; } - if (v->underscan_output[k] == 1.0) { + if (v->underscan_output[k] == 1.0f) { v->h_ratio[k] = v->h_ratio[k] * v->under_scan_factor; v->v_ratio[k] = v->v_ratio[k] * v->under_scan_factor; } @@ -71,46 +68,38 @@ void scaler_settings_calculation(struct dcn_bw_internal_vars *v) /*scaler taps calculation*/ for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->h_ratio[k] > 1.0) { - v->acceptable_quality_hta_ps =dcn_bw_min2(v->max_hscl_taps, 2.0 *dcn_bw_ceil2(v->h_ratio[k], 1.0)); - } - else if (v->h_ratio[k] < 1.0) { - v->acceptable_quality_hta_ps = 4.0; - } - else { - v->acceptable_quality_hta_ps = 1.0; + if (v->h_ratio[k] > 1.0f) { + v->acceptable_quality_hta_ps = dcn_bw_min2(v->max_hscl_taps, 2.0f * dcn_bw_ceil2(v->h_ratio[k], 1.0f)); + } else if (v->h_ratio[k] < 1.0f) { + v->acceptable_quality_hta_ps = 4.0f; + } else { + v->acceptable_quality_hta_ps = 1.0f; } if (v->ta_pscalculation == dcn_bw_override) { v->htaps[k] = v->override_hta_ps[k]; - } - else { + } else { v->htaps[k] = v->acceptable_quality_hta_ps; } - if (v->v_ratio[k] > 1.0) { - v->acceptable_quality_vta_ps =dcn_bw_min2(v->max_vscl_taps, 2.0 *dcn_bw_ceil2(v->v_ratio[k], 1.0)); - } - else if (v->v_ratio[k] < 1.0) { - v->acceptable_quality_vta_ps = 4.0; - } - else { - v->acceptable_quality_vta_ps = 1.0; + if (v->v_ratio[k] > 1.0f) { + v->acceptable_quality_vta_ps = dcn_bw_min2(v->max_vscl_taps, 2.0f * dcn_bw_ceil2(v->v_ratio[k], 1.0f)); + } else if (v->v_ratio[k] < 1.0f) { + v->acceptable_quality_vta_ps = 4.0f; + } else { + v->acceptable_quality_vta_ps = 1.0f; } if (v->ta_pscalculation == dcn_bw_override) { v->vtaps[k] = v->override_vta_ps[k]; - } - else { + } else { v->vtaps[k] = v->acceptable_quality_vta_ps; } if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { - v->vta_pschroma[k] = 0.0; - v->hta_pschroma[k] = 0.0; - } - else { + v->vta_pschroma[k] = 0.0f; + v->hta_pschroma[k] = 0.0f; + } else { if (v->ta_pscalculation == dcn_bw_override) { v->vta_pschroma[k] = v->override_vta_pschroma[k]; v->hta_pschroma[k] = v->override_hta_pschroma[k]; - } - else { + } else { v->vta_pschroma[k] = v->acceptable_quality_vta_ps; v->hta_pschroma[k] = v->acceptable_quality_hta_ps; } @@ -129,7 +118,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) v->scale_ratio_support = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->h_ratio[k] > v->max_hscl_ratio || v->v_ratio[k] > v->max_vscl_ratio || v->h_ratio[k] > v->htaps[k] || v->v_ratio[k] > v->vtaps[k] || (v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16 && (v->h_ratio[k] / 2.0 > v->hta_pschroma[k] || v->v_ratio[k] / 2.0 > v->vta_pschroma[k]))) { + if (v->h_ratio[k] > v->max_hscl_ratio || v->v_ratio[k] > v->max_vscl_ratio || v->h_ratio[k] > v->htaps[k] || v->v_ratio[k] > v->vtaps[k] || (v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16 && (v->h_ratio[k] / 2.0f > v->hta_pschroma[k] || v->v_ratio[k] / 2.0f > v->vta_pschroma[k]))) { v->scale_ratio_support = dcn_bw_no; } } @@ -146,60 +135,51 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->source_scan[k] == dcn_bw_hor) { v->swath_width_ysingle_dpp[k] = v->viewport_width[k]; - } - else { + } else { v->swath_width_ysingle_dpp[k] = v->viewport_height[k]; } if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { - v->byte_per_pixel_in_dety[k] = 8.0; - v->byte_per_pixel_in_detc[k] = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { - v->byte_per_pixel_in_dety[k] = 4.0; - v->byte_per_pixel_in_detc[k] = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { - v->byte_per_pixel_in_dety[k] = 2.0; - v->byte_per_pixel_in_detc[k] = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { - v->byte_per_pixel_in_dety[k] = 1.0; - v->byte_per_pixel_in_detc[k] = 2.0; - } - else { + v->byte_per_pixel_in_dety[k] = 8.0f; + v->byte_per_pixel_in_detc[k] = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { + v->byte_per_pixel_in_dety[k] = 4.0f; + v->byte_per_pixel_in_detc[k] = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { + v->byte_per_pixel_in_dety[k] = 2.0f; + v->byte_per_pixel_in_detc[k] = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { + v->byte_per_pixel_in_dety[k] = 1.0f; + v->byte_per_pixel_in_detc[k] = 2.0f; + } else { v->byte_per_pixel_in_dety[k] = 4.0f / 3.0f; v->byte_per_pixel_in_detc[k] = 8.0f / 3.0f; } } - v->total_read_bandwidth_consumed_gbyte_per_second = 0.0; + v->total_read_bandwidth_consumed_gbyte_per_second = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->read_bandwidth[k] = v->swath_width_ysingle_dpp[k] * (dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) * v->v_ratio[k] +dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0 * v->v_ratio[k] / 2) / (v->htotal[k] / v->pixel_clock[k]); + v->read_bandwidth[k] = v->swath_width_ysingle_dpp[k] * (dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) * v->v_ratio[k] + dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 2.0f * v->v_ratio[k] / 2) / (v->htotal[k] / v->pixel_clock[k]); if (v->dcc_enable[k] == dcn_bw_yes) { v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256); } if (v->pte_enable == dcn_bw_yes && v->source_scan[k] != dcn_bw_hor && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x)) { v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 64); - } - else if (v->pte_enable == dcn_bw_yes && v->source_scan[k] == dcn_bw_hor && (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32) && (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x)) { + } else if (v->pte_enable == dcn_bw_yes && v->source_scan[k] == dcn_bw_hor && (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32) && (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x)) { v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256); - } - else if (v->pte_enable == dcn_bw_yes) { + } else if (v->pte_enable == dcn_bw_yes) { v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 512); } - v->total_read_bandwidth_consumed_gbyte_per_second = v->total_read_bandwidth_consumed_gbyte_per_second + v->read_bandwidth[k] / 1000.0; + v->total_read_bandwidth_consumed_gbyte_per_second = v->total_read_bandwidth_consumed_gbyte_per_second + v->read_bandwidth[k] / 1000.0f; } - v->total_write_bandwidth_consumed_gbyte_per_second = 0.0; + v->total_write_bandwidth_consumed_gbyte_per_second = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) { - v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0; + v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0f; + } else if (v->output[k] == dcn_bw_writeback) { + v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5f; + } else { + v->write_bandwidth[k] = 0.0f; } - else if (v->output[k] == dcn_bw_writeback) { - v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5; - } - else { - v->write_bandwidth[k] = 0.0; - } - v->total_write_bandwidth_consumed_gbyte_per_second = v->total_write_bandwidth_consumed_gbyte_per_second + v->write_bandwidth[k] / 1000.0; + v->total_write_bandwidth_consumed_gbyte_per_second = v->total_write_bandwidth_consumed_gbyte_per_second + v->write_bandwidth[k] / 1000.0f; } v->total_bandwidth_consumed_gbyte_per_second = v->total_read_bandwidth_consumed_gbyte_per_second + v->total_write_bandwidth_consumed_gbyte_per_second; v->dcc_enabled_in_any_plane = dcn_bw_no; @@ -209,29 +189,28 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) } } for (i = 0; i <= number_of_states_plus_one; i++) { - v->return_bw_todcn_per_state =dcn_bw_min2(v->return_bus_width * v->dcfclk_per_state[i], v->fabric_and_dram_bandwidth_per_state[i] * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0); + v->return_bw_todcn_per_state = dcn_bw_min2(v->return_bus_width * v->dcfclk_per_state[i], v->fabric_and_dram_bandwidth_per_state[i] * 1000.0f * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0f); v->return_bw_per_state[i] = v->return_bw_todcn_per_state; - if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0) { - v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], v->return_bw_todcn_per_state * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bw_todcn_per_state - v->dcfclk_per_state[i] * v->return_bus_width / 4.0) + v->urgent_latency))); + if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0f) { + v->return_bw_per_state[i] = dcn_bw_min2(v->return_bw_per_state[i], v->return_bw_todcn_per_state * 4.0f * (1.0f - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f / (v->return_bw_todcn_per_state - v->dcfclk_per_state[i] * v->return_bus_width / 4.0f) + v->urgent_latency))); } - v->critical_point = 2.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0); - if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0 && v->critical_point < 4.0) { - v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], dcn_bw_pow(4.0 * v->return_bw_todcn_per_state * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2)); + v->critical_point = 2.0f * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f); + if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0f && v->critical_point < 4.0f) { + v->return_bw_per_state[i] = dcn_bw_min2(v->return_bw_per_state[i], dcn_bw_pow(4.0f * v->return_bw_todcn_per_state * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f), 2)); } - v->return_bw_todcn_per_state =dcn_bw_min2(v->return_bus_width * v->dcfclk_per_state[i], v->fabric_and_dram_bandwidth_per_state[i] * 1000.0); - if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0) { - v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], v->return_bw_todcn_per_state * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bw_todcn_per_state - v->dcfclk_per_state[i] * v->return_bus_width / 4.0) + v->urgent_latency))); + v->return_bw_todcn_per_state = dcn_bw_min2(v->return_bus_width * v->dcfclk_per_state[i], v->fabric_and_dram_bandwidth_per_state[i] * 1000.0f); + if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0f) { + v->return_bw_per_state[i] = dcn_bw_min2(v->return_bw_per_state[i], v->return_bw_todcn_per_state * 4.0f * (1.0f - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f / (v->return_bw_todcn_per_state - v->dcfclk_per_state[i] * v->return_bus_width / 4.0f) + v->urgent_latency))); } - v->critical_point = 2.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0); - if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0 && v->critical_point < 4.0) { - v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], dcn_bw_pow(4.0 * v->return_bw_todcn_per_state * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2)); + v->critical_point = 2.0f * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f); + if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0f && v->critical_point < 4.0f) { + v->return_bw_per_state[i] = dcn_bw_min2(v->return_bw_per_state[i], dcn_bw_pow(4.0f * v->return_bw_todcn_per_state * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f), 2)); } } for (i = 0; i <= number_of_states_plus_one; i++) { - if ((v->total_read_bandwidth_consumed_gbyte_per_second * 1000.0 <= v->return_bw_per_state[i]) && (v->total_bandwidth_consumed_gbyte_per_second * 1000.0 <= v->fabric_and_dram_bandwidth_per_state[i] * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0)) { + if ((v->total_read_bandwidth_consumed_gbyte_per_second * 1000.0f <= v->return_bw_per_state[i]) && (v->total_bandwidth_consumed_gbyte_per_second * 1000.0f <= v->fabric_and_dram_bandwidth_per_state[i] * 1000.0f * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0f)) { v->bandwidth_support[i] = dcn_bw_yes; - } - else { + } else { v->bandwidth_support[i] = dcn_bw_no; } } @@ -239,21 +218,19 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) v->writeback_latency_support = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444 && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0 > (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) { + if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444 && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0f > (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0f / v->write_back_latency) { v->writeback_latency_support = dcn_bw_no; - } - else if (v->output[k] == dcn_bw_writeback && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) >dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) { + } else if (v->output[k] == dcn_bw_writeback && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) > dcn_bw_min2(v->writeback_luma_buffer_size, 2.0f * v->writeback_chroma_buffer_size) * 1024.0f / v->write_back_latency) { v->writeback_latency_support = dcn_bw_no; } } /*re-ordering buffer support check*/ for (i = 0; i <= number_of_states_plus_one; i++) { - v->urgent_round_trip_and_out_of_order_latency_per_state[i] = (v->round_trip_ping_latency_cycles + 32.0) / v->dcfclk_per_state[i] + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw_per_state[i]; - if ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / v->return_bw_per_state[i] > v->urgent_round_trip_and_out_of_order_latency_per_state[i]) { + v->urgent_round_trip_and_out_of_order_latency_per_state[i] = (v->round_trip_ping_latency_cycles + 32.0f) / v->dcfclk_per_state[i] + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw_per_state[i]; + if ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f / v->return_bw_per_state[i] > v->urgent_round_trip_and_out_of_order_latency_per_state[i]) { v->rob_support[i] = dcn_bw_yes; - } - else { + } else { v->rob_support[i] = dcn_bw_no; } } @@ -262,229 +239,201 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->output[k] == dcn_bw_dp && v->dsc_capability == dcn_bw_yes) { if (v->output_format[k] == dcn_bw_420) { - v->required_output_bw = v->pixel_clock[k] / 2.0; - } - else { + v->required_output_bw = v->pixel_clock[k] / 2.0f; + } else { v->required_output_bw = v->pixel_clock[k]; } - } - else if (v->output_format[k] == dcn_bw_420) { - v->required_output_bw = v->pixel_clock[k] * 3.0 / 2.0; - } - else { - v->required_output_bw = v->pixel_clock[k] * 3.0; + } else if (v->output_format[k] == dcn_bw_420) { + v->required_output_bw = v->pixel_clock[k] * 3.0f / 2.0f; + } else { + v->required_output_bw = v->pixel_clock[k] * 3.0f; } if (v->output[k] == dcn_bw_hdmi) { v->required_phyclk[k] = v->required_output_bw; switch (v->output_deep_color[k]) { case dcn_bw_encoder_10bpc: - v->required_phyclk[k] = v->required_phyclk[k] * 5.0 / 4; + v->required_phyclk[k] = v->required_phyclk[k] * 5.0f / 4; break; case dcn_bw_encoder_12bpc: - v->required_phyclk[k] = v->required_phyclk[k] * 3.0 / 2; + v->required_phyclk[k] = v->required_phyclk[k] * 3.0f / 2; break; default: break; } - v->required_phyclk[k] = v->required_phyclk[k] / 3.0; - } - else if (v->output[k] == dcn_bw_dp) { - v->required_phyclk[k] = v->required_output_bw / 4.0; - } - else { - v->required_phyclk[k] = 0.0; + v->required_phyclk[k] = v->required_phyclk[k] / 3.0f; + } else if (v->output[k] == dcn_bw_dp) { + v->required_phyclk[k] = v->required_output_bw / 4.0f; + } else { + v->required_phyclk[k] = 0.0f; } } for (i = 0; i <= number_of_states_plus_one; i++) { v->dio_support[i] = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->required_phyclk[k] > v->phyclk_per_state[i] || (v->output[k] == dcn_bw_hdmi && v->required_phyclk[k] > 600.0)) { + if (v->required_phyclk[k] > v->phyclk_per_state[i] || (v->output[k] == dcn_bw_hdmi && v->required_phyclk[k] > 600.0f)) { v->dio_support[i] = dcn_bw_no; } } } /*total available writeback support check*/ - v->total_number_of_active_writeback = 0.0; + v->total_number_of_active_writeback = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->output[k] == dcn_bw_writeback) { - v->total_number_of_active_writeback = v->total_number_of_active_writeback + 1.0; + v->total_number_of_active_writeback = v->total_number_of_active_writeback + 1.0f; } } if (v->total_number_of_active_writeback <= v->max_num_writeback) { v->total_available_writeback_support = dcn_bw_yes; - } - else { + } else { v->total_available_writeback_support = dcn_bw_no; } /*maximum dispclk/dppclk support check*/ for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->h_ratio[k] > 1.0) { - v->pscl_factor[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] /dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0)); + if (v->h_ratio[k] > 1.0f) { + v->pscl_factor[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / dcn_bw_ceil2(v->htaps[k] / 6.0f, 1.0f)); + } else { + v->pscl_factor[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); } - else { - v->pscl_factor[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); - } - if (v->byte_per_pixel_in_detc[k] == 0.0) { - v->pscl_factor_chroma[k] = 0.0; - v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], 1.0); - } - else { - if (v->h_ratio[k] / 2.0 > 1.0) { - v->pscl_factor_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0 /dcn_bw_ceil2(v->hta_pschroma[k] / 6.0, 1.0)); + if (v->byte_per_pixel_in_detc[k] == 0.0f) { + v->pscl_factor_chroma[k] = 0.0f; + v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] * dcn_bw_max3(v->vtaps[k] / 6.0f * dcn_bw_min2(1.0f, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], 1.0f); + } else { + if (v->h_ratio[k] / 2.0f > 1.0f) { + v->pscl_factor_chroma[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0f / dcn_bw_ceil2(v->hta_pschroma[k] / 6.0f, 1.0f)); + } else { + v->pscl_factor_chroma[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); } - else { - v->pscl_factor_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); - } - v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max5(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_factor_chroma[k], 1.0); + v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] * dcn_bw_max5(v->vtaps[k] / 6.0f * dcn_bw_min2(1.0f, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], v->vta_pschroma[k] / 6.0f * dcn_bw_min2(1.0f, v->h_ratio[k] / 2.0f), v->h_ratio[k] * v->v_ratio[k] / 4.0f / v->pscl_factor_chroma[k], 1.0f); } } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->read256_block_height_y[k] = 1.0; + v->read256_block_height_y[k] = 1.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { + v->read256_block_height_y[k] = 4.0f; + } else { + v->read256_block_height_y[k] = 8.0f; } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { - v->read256_block_height_y[k] = 4.0; - } - else { - v->read256_block_height_y[k] = 8.0; - } - v->read256_block_width_y[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->read256_block_height_y[k]; - v->read256_block_height_c[k] = 0.0; - v->read256_block_width_c[k] = 0.0; - } - else { + v->read256_block_width_y[k] = 256.0f / dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / v->read256_block_height_y[k]; + v->read256_block_height_c[k] = 0.0f; + v->read256_block_width_c[k] = 0.0f; + } else { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->read256_block_height_y[k] = 1.0; - v->read256_block_height_c[k] = 1.0; + v->read256_block_height_y[k] = 1.0f; + v->read256_block_height_c[k] = 1.0f; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { + v->read256_block_height_y[k] = 16.0f; + v->read256_block_height_c[k] = 8.0f; + } else { + v->read256_block_height_y[k] = 8.0f; + v->read256_block_height_c[k] = 8.0f; } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { - v->read256_block_height_y[k] = 16.0; - v->read256_block_height_c[k] = 8.0; - } - else { - v->read256_block_height_y[k] = 8.0; - v->read256_block_height_c[k] = 8.0; - } - v->read256_block_width_y[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->read256_block_height_y[k]; - v->read256_block_width_c[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->read256_block_height_c[k]; + v->read256_block_width_y[k] = 256.0f / dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / v->read256_block_height_y[k]; + v->read256_block_width_c[k] = 256.0f / dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / v->read256_block_height_c[k]; } if (v->source_scan[k] == dcn_bw_hor) { v->max_swath_height_y[k] = v->read256_block_height_y[k]; v->max_swath_height_c[k] = v->read256_block_height_c[k]; - } - else { + } else { v->max_swath_height_y[k] = v->read256_block_width_y[k]; v->max_swath_height_c[k] = v->read256_block_width_c[k]; } if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) { if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) { v->min_swath_height_y[k] = v->max_swath_height_y[k]; - } - else { - v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0; + } else { + v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0f; } v->min_swath_height_c[k] = v->max_swath_height_c[k]; - } - else { + } else { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { v->min_swath_height_y[k] = v->max_swath_height_y[k]; v->min_swath_height_c[k] = v->max_swath_height_c[k]; - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) { - v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) { + v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0f; if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) { v->min_swath_height_c[k] = v->max_swath_height_c[k]; + } else { + v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0f; } - else { - v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0; - } - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) { - v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) { + v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0f; if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) { v->min_swath_height_y[k] = v->max_swath_height_y[k]; + } else { + v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0f; } - else { - v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0; - } - } - else { + } else { v->min_swath_height_y[k] = v->max_swath_height_y[k]; v->min_swath_height_c[k] = v->max_swath_height_c[k]; } } if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->maximum_swath_width = 8192.0; + v->maximum_swath_width = 8192.0f; + } else { + v->maximum_swath_width = 5120.0f; } - else { - v->maximum_swath_width = 5120.0; + v->number_of_dpp_required_for_det_size = dcn_bw_ceil2(v->swath_width_ysingle_dpp[k] / dcn_bw_min2(v->maximum_swath_width, v->det_buffer_size_in_kbyte * 1024.0f / 2.0f / (v->byte_per_pixel_in_dety[k] * v->min_swath_height_y[k] + v->byte_per_pixel_in_detc[k] / 2.0f * v->min_swath_height_c[k])), 1.0f); + if (v->byte_per_pixel_in_detc[k] == 0.0f) { + v->number_of_dpp_required_for_lb_size = dcn_bw_ceil2((v->vtaps[k] + dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0f) - 2, 0.0f)) * v->swath_width_ysingle_dpp[k] / dcn_bw_max2(v->h_ratio[k], 1.0f) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0f); + } else { + v->number_of_dpp_required_for_lb_size = dcn_bw_max2(dcn_bw_ceil2((v->vtaps[k] + dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0f) - 2, 0.0f)) * v->swath_width_ysingle_dpp[k] / dcn_bw_max2(v->h_ratio[k], 1.0f) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0f), dcn_bw_ceil2((v->vta_pschroma[k] + dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k] / 2.0f, 1.0f) - 2, 0.0f)) * v->swath_width_ysingle_dpp[k] / 2.0f / dcn_bw_max2(v->h_ratio[k] / 2.0f, 1.0f) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0f)); } - v->number_of_dpp_required_for_det_size =dcn_bw_ceil2(v->swath_width_ysingle_dpp[k] /dcn_bw_min2(v->maximum_swath_width, v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / (v->byte_per_pixel_in_dety[k] * v->min_swath_height_y[k] + v->byte_per_pixel_in_detc[k] / 2.0 * v->min_swath_height_c[k])), 1.0); - if (v->byte_per_pixel_in_detc[k] == 0.0) { - v->number_of_dpp_required_for_lb_size =dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0); - } - else { - v->number_of_dpp_required_for_lb_size =dcn_bw_max2(dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0),dcn_bw_ceil2((v->vta_pschroma[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k] / 2.0, 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0)); - } - v->number_of_dpp_required_for_det_and_lb_size[k] =dcn_bw_max2(v->number_of_dpp_required_for_det_size, v->number_of_dpp_required_for_lb_size); + v->number_of_dpp_required_for_det_and_lb_size[k] = dcn_bw_max2(v->number_of_dpp_required_for_det_size, v->number_of_dpp_required_for_lb_size); } for (i = 0; i <= number_of_states_plus_one; i++) { for (j = 0; j <= 1; j++) { - v->total_number_of_active_dpp[i][j] = 0.0; - v->required_dispclk[i][j] = 0.0; + v->total_number_of_active_dpp[i][j] = 0.0f; + v->required_dispclk[i][j] = 0.0f; v->dispclk_dppclk_support[i][j] = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0); + v->min_dispclk_using_single_dpp = dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0f + v->downspreading / 100.0f); if (v->odm_capability == dcn_bw_yes) { - v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k] / 2.0, v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0); - } - else { - v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0); + v->min_dispclk_using_dual_dpp = dcn_bw_max2(v->pixel_clock[k] / 2.0f, v->min_dppclk_using_single_dpp[k] / 2.0f * (j + 1)) * (1.0f + v->downspreading / 100.0f); + } else { + v->min_dispclk_using_dual_dpp = dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0f * (j + 1)) * (1.0f + v->downspreading / 100.0f); } if (i < number_of_states) { - v->min_dispclk_using_single_dpp = v->min_dispclk_using_single_dpp * (1.0 + v->dispclk_ramping_margin / 100.0); - v->min_dispclk_using_dual_dpp = v->min_dispclk_using_dual_dpp * (1.0 + v->dispclk_ramping_margin / 100.0); + v->min_dispclk_using_single_dpp = v->min_dispclk_using_single_dpp * (1.0f + v->dispclk_ramping_margin / 100.0f); + v->min_dispclk_using_dual_dpp = v->min_dispclk_using_dual_dpp * (1.0f + v->dispclk_ramping_margin / 100.0f); } - if (v->min_dispclk_using_single_dpp <=dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i]) && v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0) { - v->no_of_dpp[i][j][k] = 1.0; - v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_single_dpp); - } - else if (v->min_dispclk_using_dual_dpp <=dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) { - v->no_of_dpp[i][j][k] = 2.0; - v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp); - } - else { - v->no_of_dpp[i][j][k] = 2.0; - v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp); + if (v->min_dispclk_using_single_dpp <= dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i]) && v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0f) { + v->no_of_dpp[i][j][k] = 1.0f; + v->required_dispclk[i][j] = dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_single_dpp); + } else if (v->min_dispclk_using_dual_dpp <= dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) { + v->no_of_dpp[i][j][k] = 2.0f; + v->required_dispclk[i][j] = dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp); + } else { + v->no_of_dpp[i][j][k] = 2.0f; + v->required_dispclk[i][j] = dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp); v->dispclk_dppclk_support[i][j] = dcn_bw_no; } v->total_number_of_active_dpp[i][j] = v->total_number_of_active_dpp[i][j] + v->no_of_dpp[i][j][k]; } if (v->total_number_of_active_dpp[i][j] > v->max_num_dpp) { - v->total_number_of_active_dpp[i][j] = 0.0; - v->required_dispclk[i][j] = 0.0; + v->total_number_of_active_dpp[i][j] = 0.0f; + v->required_dispclk[i][j] = 0.0f; v->dispclk_dppclk_support[i][j] = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0); - v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0); + v->min_dispclk_using_single_dpp = dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0f + v->downspreading / 100.0f); + v->min_dispclk_using_dual_dpp = dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0f * (j + 1)) * (1.0f + v->downspreading / 100.0f); if (i < number_of_states) { - v->min_dispclk_using_single_dpp = v->min_dispclk_using_single_dpp * (1.0 + v->dispclk_ramping_margin / 100.0); - v->min_dispclk_using_dual_dpp = v->min_dispclk_using_dual_dpp * (1.0 + v->dispclk_ramping_margin / 100.0); + v->min_dispclk_using_single_dpp = v->min_dispclk_using_single_dpp * (1.0f + v->dispclk_ramping_margin / 100.0f); + v->min_dispclk_using_dual_dpp = v->min_dispclk_using_dual_dpp * (1.0f + v->dispclk_ramping_margin / 100.0f); } - if (v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0) { - v->no_of_dpp[i][j][k] = 1.0; - v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_single_dpp); - if (v->min_dispclk_using_single_dpp >dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) { + if (v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0f) { + v->no_of_dpp[i][j][k] = 1.0f; + v->required_dispclk[i][j] = dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_single_dpp); + if (v->min_dispclk_using_single_dpp > dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) { v->dispclk_dppclk_support[i][j] = dcn_bw_no; } - } - else { - v->no_of_dpp[i][j][k] = 2.0; - v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp); - if (v->min_dispclk_using_dual_dpp >dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) { + } else { + v->no_of_dpp[i][j][k] = 2.0f; + v->required_dispclk[i][j] = dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp); + if (v->min_dispclk_using_dual_dpp > dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) { v->dispclk_dppclk_support[i][j] = dcn_bw_no; } } @@ -497,7 +446,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) v->viewport_size_support = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->number_of_dpp_required_for_det_and_lb_size[k] > 2.0) { + if (v->number_of_dpp_required_for_det_and_lb_size[k] > 2.0f) { v->viewport_size_support = dcn_bw_no; } } @@ -507,8 +456,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) for (j = 0; j <= 1; j++) { if (v->total_number_of_active_dpp[i][j] <= v->max_num_dpp) { v->total_available_pipes_support[i][j] = dcn_bw_yes; - } - else { + } else { v->total_available_pipes_support[i][j] = dcn_bw_no; } } @@ -519,47 +467,43 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) for (i = 0; i <= number_of_states_plus_one; i++) { for (j = 0; j <= 1; j++) { v->swath_width_yper_state[i][j][k] = v->swath_width_ysingle_dpp[k] / v->no_of_dpp[i][j][k]; - v->swath_width_granularity_y = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->max_swath_height_y[k]; - v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] - 1.0, v->swath_width_granularity_y) + v->swath_width_granularity_y) * v->byte_per_pixel_in_dety[k] * v->max_swath_height_y[k]; + v->swath_width_granularity_y = 256.0f / dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / v->max_swath_height_y[k]; + v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] - 1.0f, v->swath_width_granularity_y) + v->swath_width_granularity_y) * v->byte_per_pixel_in_dety[k] * v->max_swath_height_y[k]; if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) { - v->rounded_up_max_swath_size_bytes_y =dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_y, 256.0) + 256; + v->rounded_up_max_swath_size_bytes_y = dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_y, 256.0f) + 256; } - if (v->max_swath_height_c[k] > 0.0) { - v->swath_width_granularity_c = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->max_swath_height_c[k]; - v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] / 2.0 - 1.0, v->swath_width_granularity_c) + v->swath_width_granularity_c) * v->byte_per_pixel_in_detc[k] * v->max_swath_height_c[k]; + if (v->max_swath_height_c[k] > 0.0f) { + v->swath_width_granularity_c = 256.0f / dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / v->max_swath_height_c[k]; + v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] / 2.0f - 1.0f, v->swath_width_granularity_c) + v->swath_width_granularity_c) * v->byte_per_pixel_in_detc[k] * v->max_swath_height_c[k]; if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) { - v->rounded_up_max_swath_size_bytes_c = dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_c, 256.0) + 256; + v->rounded_up_max_swath_size_bytes_c = dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_c, 256.0f) + 256; } } - if (v->rounded_up_max_swath_size_bytes_y + v->rounded_up_max_swath_size_bytes_c <= v->det_buffer_size_in_kbyte * 1024.0 / 2.0) { + if (v->rounded_up_max_swath_size_bytes_y + v->rounded_up_max_swath_size_bytes_c <= v->det_buffer_size_in_kbyte * 1024.0f / 2.0f) { v->swath_height_yper_state[i][j][k] = v->max_swath_height_y[k]; v->swath_height_cper_state[i][j][k] = v->max_swath_height_c[k]; - } - else { + } else { v->swath_height_yper_state[i][j][k] = v->min_swath_height_y[k]; v->swath_height_cper_state[i][j][k] = v->min_swath_height_c[k]; } - if (v->byte_per_pixel_in_detc[k] == 0.0) { - v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k]; - v->lines_in_det_chroma = 0.0; + if (v->byte_per_pixel_in_detc[k] == 0.0f) { + v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0f / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k]; + v->lines_in_det_chroma = 0.0f; + } else if (v->swath_height_yper_state[i][j][k] <= v->swath_height_cper_state[i][j][k]) { + v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0f / 2.0f / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k]; + v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0f / 2.0f / v->byte_per_pixel_in_detc[k] / (v->swath_width_yper_state[i][j][k] / 2.0f); + } else { + v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0f * 2.0f / 3.0f / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k]; + v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0f / 3.0f / v->byte_per_pixel_in_dety[k] / (v->swath_width_yper_state[i][j][k] / 2.0f); } - else if (v->swath_height_yper_state[i][j][k] <= v->swath_height_cper_state[i][j][k]) { - v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k]; - v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / v->byte_per_pixel_in_detc[k] / (v->swath_width_yper_state[i][j][k] / 2.0); - } - else { - v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k]; - v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0 / 3.0 / v->byte_per_pixel_in_dety[k] / (v->swath_width_yper_state[i][j][k] / 2.0); - } - v->effective_lb_latency_hiding_source_lines_luma =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0); - v->effective_detlb_lines_luma =dcn_bw_floor2(v->lines_in_det_luma +dcn_bw_min2(v->lines_in_det_luma * v->required_dispclk[i][j] * v->byte_per_pixel_in_dety[k] * v->pscl_factor[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_yper_state[i][j][k]); - if (v->byte_per_pixel_in_detc[k] == 0.0) { - v->urgent_latency_support_us_per_state[i][j][k] = v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]); - } - else { - v->effective_lb_latency_hiding_source_lines_chroma = dcn_bw_min2(v->max_line_buffer_lines, dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] / 2.0 / dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0)), 1.0)) - (v->vta_pschroma[k] - 1.0); + v->effective_lb_latency_hiding_source_lines_luma = dcn_bw_min2(v->max_line_buffer_lines, dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] / dcn_bw_max2(v->h_ratio[k], 1.0f)), 1.0f)) - (v->vtaps[k] - 1.0f); + v->effective_detlb_lines_luma = dcn_bw_floor2(v->lines_in_det_luma + dcn_bw_min2(v->lines_in_det_luma * v->required_dispclk[i][j] * v->byte_per_pixel_in_dety[k] * v->pscl_factor[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_yper_state[i][j][k]); + if (v->byte_per_pixel_in_detc[k] == 0.0f) { + v->urgent_latency_support_us_per_state[i][j][k] = v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]); + } else { + v->effective_lb_latency_hiding_source_lines_chroma = dcn_bw_min2(v->max_line_buffer_lines, dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] / 2.0f / dcn_bw_max2(v->h_ratio[k] / 2.0f, 1.0f)), 1.0f)) - (v->vta_pschroma[k] - 1.0f); v->effective_detlb_lines_chroma = dcn_bw_floor2(v->lines_in_det_chroma + dcn_bw_min2(v->lines_in_det_chroma * v->required_dispclk[i][j] * v->byte_per_pixel_in_detc[k] * v->pscl_factor_chroma[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_cper_state[i][j][k]); - v->urgent_latency_support_us_per_state[i][j][k] = dcn_bw_min2(v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]), v->effective_detlb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0) - v->effective_detlb_lines_chroma * v->swath_width_yper_state[i][j][k] / 2.0 * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k])); + v->urgent_latency_support_us_per_state[i][j][k] = dcn_bw_min2(v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]), v->effective_detlb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0f) - v->effective_detlb_lines_chroma * v->swath_width_yper_state[i][j][k] / 2.0f * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k])); } } } @@ -568,7 +512,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) for (j = 0; j <= 1; j++) { v->urgent_latency_support[i][j] = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->urgent_latency_support_us_per_state[i][j][k] < v->urgent_latency / 1.0) { + if (v->urgent_latency_support_us_per_state[i][j][k] < v->urgent_latency / 1.0f) { v->urgent_latency_support[i][j] = dcn_bw_no; } } @@ -578,7 +522,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) for (i = 0; i <= number_of_states_plus_one; i++) { for (j = 0; j <= 1; j++) { - v->total_number_of_dcc_active_dpp[i][j] = 0.0; + v->total_number_of_dcc_active_dpp[i][j] = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->dcc_enable[k] == dcn_bw_yes) { v->total_number_of_dcc_active_dpp[i][j] = v->total_number_of_dcc_active_dpp[i][j] + v->no_of_dpp[i][j][k]; @@ -588,228 +532,198 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) } for (i = 0; i <= number_of_states_plus_one; i++) { for (j = 0; j <= 1; j++) { - v->projected_dcfclk_deep_sleep = 8.0; + v->projected_dcfclk_deep_sleep = 8.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, v->pixel_clock[k] / 16.0); - if (v->byte_per_pixel_in_detc[k] == 0.0) { - if (v->v_ratio[k] <= 1.0) { - v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 64.0 * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]); + v->projected_dcfclk_deep_sleep = dcn_bw_max2(v->projected_dcfclk_deep_sleep, v->pixel_clock[k] / 16.0f); + if (v->byte_per_pixel_in_detc[k] == 0.0f) { + if (v->v_ratio[k] <= 1.0f) { + v->projected_dcfclk_deep_sleep = dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1f * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / 64.0f * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]); + } else { + v->projected_dcfclk_deep_sleep = dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1f * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / 64.0f * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j)); } - else { - v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 64.0 * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j)); + } else { + if (v->v_ratio[k] <= 1.0f) { + v->projected_dcfclk_deep_sleep = dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1f * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / 32.0f * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]); + } else { + v->projected_dcfclk_deep_sleep = dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1f * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / 32.0f * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j)); } - } - else { - if (v->v_ratio[k] <= 1.0) { - v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 32.0 * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]); - } - else { - v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 32.0 * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j)); - } - if (v->v_ratio[k] / 2.0 <= 1.0) { - v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 32.0 * v->h_ratio[k] / 2.0 * v->pixel_clock[k] / v->no_of_dpp[i][j][k]); - } - else { - v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 32.0 * v->pscl_factor_chroma[k] * v->required_dispclk[i][j] / (1 + j)); + if (v->v_ratio[k] / 2.0f <= 1.0f) { + v->projected_dcfclk_deep_sleep = dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1f * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 32.0f * v->h_ratio[k] / 2.0f * v->pixel_clock[k] / v->no_of_dpp[i][j][k]); + } else { + v->projected_dcfclk_deep_sleep = dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1f * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 32.0f * v->pscl_factor_chroma[k] * v->required_dispclk[i][j] / (1 + j)); } } } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->dcc_enable[k] == dcn_bw_yes) { - v->meta_req_height_y = 8.0 * v->read256_block_height_y[k]; - v->meta_req_width_y = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->meta_req_height_y; - v->meta_surface_width_y =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0, v->meta_req_width_y) + v->meta_req_width_y; - v->meta_surface_height_y =dcn_bw_ceil2(v->viewport_height[k] - 1.0, v->meta_req_height_y) + v->meta_req_height_y; + v->meta_req_height_y = 8.0f * v->read256_block_height_y[k]; + v->meta_req_width_y = 64.0f * 256.0f / dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / v->meta_req_height_y; + v->meta_surface_width_y = dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0f, v->meta_req_width_y) + v->meta_req_width_y; + v->meta_surface_height_y = dcn_bw_ceil2(v->viewport_height[k] - 1.0f, v->meta_req_height_y) + v->meta_req_height_y; if (v->pte_enable == dcn_bw_yes) { - v->meta_pte_bytes_per_frame_y = (dcn_bw_ceil2((v->meta_surface_width_y * v->meta_surface_height_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0; - } - else { - v->meta_pte_bytes_per_frame_y = 0.0; + v->meta_pte_bytes_per_frame_y = (dcn_bw_ceil2((v->meta_surface_width_y * v->meta_surface_height_y * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / 256.0f - 4096.0f) / 8.0f / 4096.0f, 1.0f) + 1) * 64.0f; + } else { + v->meta_pte_bytes_per_frame_y = 0.0f; } if (v->source_scan[k] == dcn_bw_hor) { - v->meta_row_bytes_y = v->meta_surface_width_y * v->meta_req_height_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0; + v->meta_row_bytes_y = v->meta_surface_width_y * v->meta_req_height_y * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / 256.0f; + } else { + v->meta_row_bytes_y = v->meta_surface_height_y * v->meta_req_width_y * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / 256.0f; } - else { - v->meta_row_bytes_y = v->meta_surface_height_y * v->meta_req_width_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0; - } - } - else { - v->meta_pte_bytes_per_frame_y = 0.0; - v->meta_row_bytes_y = 0.0; + } else { + v->meta_pte_bytes_per_frame_y = 0.0f; + v->meta_row_bytes_y = 0.0f; } if (v->pte_enable == dcn_bw_yes) { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->macro_tile_block_size_bytes_y = 256.0; - v->macro_tile_block_height_y = 1.0; + v->macro_tile_block_size_bytes_y = 256.0f; + v->macro_tile_block_height_y = 1.0f; + } else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { + v->macro_tile_block_size_bytes_y = 4096.0f; + v->macro_tile_block_height_y = 4.0f * v->read256_block_height_y[k]; + } else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { + v->macro_tile_block_size_bytes_y = 64.0f * 1024; + v->macro_tile_block_height_y = 16.0f * v->read256_block_height_y[k]; + } else { + v->macro_tile_block_size_bytes_y = 256.0f * 1024; + v->macro_tile_block_height_y = 32.0f * v->read256_block_height_y[k]; } - else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { - v->macro_tile_block_size_bytes_y = 4096.0; - v->macro_tile_block_height_y = 4.0 * v->read256_block_height_y[k]; - } - else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { - v->macro_tile_block_size_bytes_y = 64.0 * 1024; - v->macro_tile_block_height_y = 16.0 * v->read256_block_height_y[k]; - } - else { - v->macro_tile_block_size_bytes_y = 256.0 * 1024; - v->macro_tile_block_height_y = 32.0 * v->read256_block_height_y[k]; - } - if (v->macro_tile_block_size_bytes_y <= 65536.0) { + if (v->macro_tile_block_size_bytes_y <= 65536.0f) { v->data_pte_req_height_y = v->macro_tile_block_height_y; + } else { + v->data_pte_req_height_y = 16.0f * v->read256_block_height_y[k]; } - else { - v->data_pte_req_height_y = 16.0 * v->read256_block_height_y[k]; - } - v->data_pte_req_width_y = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->data_pte_req_height_y * 8; + v->data_pte_req_width_y = 4096.0f / dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / v->data_pte_req_height_y * 8; if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] *dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_y / (v->viewport_width[k] / v->no_of_dpp[i][j][k]), 2.0), 1.0))) - 1.0) / v->data_pte_req_width_y, 1.0) + 1); + v->dpte_bytes_per_row_y = 64.0f * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] * dcn_bw_min2(128.0f, dcn_bw_pow(2.0f, dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_y / (v->viewport_width[k] / v->no_of_dpp[i][j][k]), 2.0f), 1.0f))) - 1.0f) / v->data_pte_req_width_y, 1.0f) + 1); + } else if (v->source_scan[k] == dcn_bw_hor) { + v->dpte_bytes_per_row_y = 64.0f * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0f) / v->data_pte_req_width_y, 1.0f) + 1); + } else { + v->dpte_bytes_per_row_y = 64.0f * (dcn_bw_ceil2((v->viewport_height[k] - 1.0f) / v->data_pte_req_height_y, 1.0f) + 1); } - else if (v->source_scan[k] == dcn_bw_hor) { - v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0) / v->data_pte_req_width_y, 1.0) + 1); - } - else { - v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] - 1.0) / v->data_pte_req_height_y, 1.0) + 1); - } - } - else { - v->dpte_bytes_per_row_y = 0.0; + } else { + v->dpte_bytes_per_row_y = 0.0f; } if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) { if (v->dcc_enable[k] == dcn_bw_yes) { - v->meta_req_height_c = 8.0 * v->read256_block_height_c[k]; - v->meta_req_width_c = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->meta_req_height_c; - v->meta_surface_width_c =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 - 1.0, v->meta_req_width_c) + v->meta_req_width_c; - v->meta_surface_height_c =dcn_bw_ceil2(v->viewport_height[k] / 2.0 - 1.0, v->meta_req_height_c) + v->meta_req_height_c; + v->meta_req_height_c = 8.0f * v->read256_block_height_c[k]; + v->meta_req_width_c = 64.0f * 256.0f / dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / v->meta_req_height_c; + v->meta_surface_width_c = dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0f - 1.0f, v->meta_req_width_c) + v->meta_req_width_c; + v->meta_surface_height_c = dcn_bw_ceil2(v->viewport_height[k] / 2.0f - 1.0f, v->meta_req_height_c) + v->meta_req_height_c; if (v->pte_enable == dcn_bw_yes) { - v->meta_pte_bytes_per_frame_c = (dcn_bw_ceil2((v->meta_surface_width_c * v->meta_surface_height_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0; - } - else { - v->meta_pte_bytes_per_frame_c = 0.0; + v->meta_pte_bytes_per_frame_c = (dcn_bw_ceil2((v->meta_surface_width_c * v->meta_surface_height_c * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 256.0f - 4096.0f) / 8.0f / 4096.0f, 1.0f) + 1) * 64.0f; + } else { + v->meta_pte_bytes_per_frame_c = 0.0f; } if (v->source_scan[k] == dcn_bw_hor) { - v->meta_row_bytes_c = v->meta_surface_width_c * v->meta_req_height_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0; + v->meta_row_bytes_c = v->meta_surface_width_c * v->meta_req_height_c * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 256.0f; + } else { + v->meta_row_bytes_c = v->meta_surface_height_c * v->meta_req_width_c * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 256.0f; } - else { - v->meta_row_bytes_c = v->meta_surface_height_c * v->meta_req_width_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0; - } - } - else { - v->meta_pte_bytes_per_frame_c = 0.0; - v->meta_row_bytes_c = 0.0; + } else { + v->meta_pte_bytes_per_frame_c = 0.0f; + v->meta_row_bytes_c = 0.0f; } if (v->pte_enable == dcn_bw_yes) { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->macro_tile_block_size_bytes_c = 256.0; - v->macro_tile_block_height_c = 1.0; + v->macro_tile_block_size_bytes_c = 256.0f; + v->macro_tile_block_height_c = 1.0f; + } else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { + v->macro_tile_block_size_bytes_c = 4096.0f; + v->macro_tile_block_height_c = 4.0f * v->read256_block_height_c[k]; + } else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { + v->macro_tile_block_size_bytes_c = 64.0f * 1024; + v->macro_tile_block_height_c = 16.0f * v->read256_block_height_c[k]; + } else { + v->macro_tile_block_size_bytes_c = 256.0f * 1024; + v->macro_tile_block_height_c = 32.0f * v->read256_block_height_c[k]; } - else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { - v->macro_tile_block_size_bytes_c = 4096.0; - v->macro_tile_block_height_c = 4.0 * v->read256_block_height_c[k]; - } - else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { - v->macro_tile_block_size_bytes_c = 64.0 * 1024; - v->macro_tile_block_height_c = 16.0 * v->read256_block_height_c[k]; - } - else { - v->macro_tile_block_size_bytes_c = 256.0 * 1024; - v->macro_tile_block_height_c = 32.0 * v->read256_block_height_c[k]; - } - v->macro_tile_block_width_c = v->macro_tile_block_size_bytes_c /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->macro_tile_block_height_c; - if (v->macro_tile_block_size_bytes_c <= 65536.0) { + v->macro_tile_block_width_c = v->macro_tile_block_size_bytes_c / dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / v->macro_tile_block_height_c; + if (v->macro_tile_block_size_bytes_c <= 65536.0f) { v->data_pte_req_height_c = v->macro_tile_block_height_c; + } else { + v->data_pte_req_height_c = 16.0f * v->read256_block_height_c[k]; } - else { - v->data_pte_req_height_c = 16.0 * v->read256_block_height_c[k]; - } - v->data_pte_req_width_c = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->data_pte_req_height_c * 8; + v->data_pte_req_width_c = 4096.0f / dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / v->data_pte_req_height_c * 8; if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 * dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_c / (v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0), 2.0), 1.0))) - 1.0) / v->data_pte_req_width_c, 1.0) + 1); - } - else if (v->source_scan[k] == dcn_bw_hor) { - v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 - 1.0) / v->data_pte_req_width_c, 1.0) + 1); - } - else { - v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] / 2.0 - 1.0) / v->data_pte_req_height_c, 1.0) + 1); + v->dpte_bytes_per_row_c = 64.0f * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0f * dcn_bw_min2(128.0f, dcn_bw_pow(2.0f, dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_c / (v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0f), 2.0f), 1.0f))) - 1.0f) / v->data_pte_req_width_c, 1.0f) + 1); + } else if (v->source_scan[k] == dcn_bw_hor) { + v->dpte_bytes_per_row_c = 64.0f * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0f - 1.0f) / v->data_pte_req_width_c, 1.0f) + 1); + } else { + v->dpte_bytes_per_row_c = 64.0f * (dcn_bw_ceil2((v->viewport_height[k] / 2.0f - 1.0f) / v->data_pte_req_height_c, 1.0f) + 1); } + } else { + v->dpte_bytes_per_row_c = 0.0f; } - else { - v->dpte_bytes_per_row_c = 0.0; - } - } - else { - v->dpte_bytes_per_row_c = 0.0; - v->meta_pte_bytes_per_frame_c = 0.0; - v->meta_row_bytes_c = 0.0; + } else { + v->dpte_bytes_per_row_c = 0.0f; + v->meta_pte_bytes_per_frame_c = 0.0f; + v->meta_row_bytes_c = 0.0f; } v->dpte_bytes_per_row[k] = v->dpte_bytes_per_row_y + v->dpte_bytes_per_row_c; v->meta_pte_bytes_per_frame[k] = v->meta_pte_bytes_per_frame_y + v->meta_pte_bytes_per_frame_c; v->meta_row_bytes[k] = v->meta_row_bytes_y + v->meta_row_bytes_c; - v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0; - v->prefill_y[k] =dcn_bw_floor2(v->v_init_y, 1.0); - v->max_num_sw_y[k] =dcn_bw_ceil2((v->prefill_y[k] - 1.0) / v->swath_height_yper_state[i][j][k], 1.0) + 1; - if (v->prefill_y[k] > 1.0) { - v->max_partial_sw_y =dcn_bw_mod((v->prefill_y[k] - 2.0), v->swath_height_yper_state[i][j][k]); + v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0f + v->interlace_output[k] * 0.5f * v->v_ratio[k]) / 2.0f; + v->prefill_y[k] = dcn_bw_floor2(v->v_init_y, 1.0f); + v->max_num_sw_y[k] = dcn_bw_ceil2((v->prefill_y[k] - 1.0f) / v->swath_height_yper_state[i][j][k], 1.0f) + 1; + if (v->prefill_y[k] > 1.0f) { + v->max_partial_sw_y = dcn_bw_mod((v->prefill_y[k] - 2.0f), v->swath_height_yper_state[i][j][k]); + } else { + v->max_partial_sw_y = dcn_bw_mod((v->prefill_y[k] + v->swath_height_yper_state[i][j][k] - 2.0f), v->swath_height_yper_state[i][j][k]); } - else { - v->max_partial_sw_y =dcn_bw_mod((v->prefill_y[k] + v->swath_height_yper_state[i][j][k] - 2.0), v->swath_height_yper_state[i][j][k]); - } - v->max_partial_sw_y =dcn_bw_max2(1.0, v->max_partial_sw_y); + v->max_partial_sw_y = dcn_bw_max2(1.0f, v->max_partial_sw_y); v->prefetch_lines_y[k] = v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k] + v->max_partial_sw_y; if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) { - v->v_init_c = (v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k] / 2.0) / 2.0; - v->prefill_c[k] =dcn_bw_floor2(v->v_init_c, 1.0); - v->max_num_sw_c[k] =dcn_bw_ceil2((v->prefill_c[k] - 1.0) / v->swath_height_cper_state[i][j][k], 1.0) + 1; - if (v->prefill_c[k] > 1.0) { - v->max_partial_sw_c =dcn_bw_mod((v->prefill_c[k] - 2.0), v->swath_height_cper_state[i][j][k]); + v->v_init_c = (v->v_ratio[k] / 2.0f + v->vtaps[k] + 1.0f + v->interlace_output[k] * 0.5f * v->v_ratio[k] / 2.0f) / 2.0f; + v->prefill_c[k] = dcn_bw_floor2(v->v_init_c, 1.0f); + v->max_num_sw_c[k] = dcn_bw_ceil2((v->prefill_c[k] - 1.0f) / v->swath_height_cper_state[i][j][k], 1.0f) + 1; + if (v->prefill_c[k] > 1.0f) { + v->max_partial_sw_c = dcn_bw_mod((v->prefill_c[k] - 2.0f), v->swath_height_cper_state[i][j][k]); + } else { + v->max_partial_sw_c = dcn_bw_mod((v->prefill_c[k] + v->swath_height_cper_state[i][j][k] - 2.0f), v->swath_height_cper_state[i][j][k]); } - else { - v->max_partial_sw_c =dcn_bw_mod((v->prefill_c[k] + v->swath_height_cper_state[i][j][k] - 2.0), v->swath_height_cper_state[i][j][k]); - } - v->max_partial_sw_c =dcn_bw_max2(1.0, v->max_partial_sw_c); + v->max_partial_sw_c = dcn_bw_max2(1.0f, v->max_partial_sw_c); v->prefetch_lines_c[k] = v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k] + v->max_partial_sw_c; + } else { + v->prefetch_lines_c[k] = 0.0f; } - else { - v->prefetch_lines_c[k] = 0.0; - } - v->dst_x_after_scaler = 90.0 * v->pixel_clock[k] / (v->required_dispclk[i][j] / (j + 1)) + 42.0 * v->pixel_clock[k] / v->required_dispclk[i][j]; - if (v->no_of_dpp[i][j][k] > 1.0) { - v->dst_x_after_scaler = v->dst_x_after_scaler + v->scaler_rec_out_width[k] / 2.0; + v->dst_x_after_scaler = 90.0f * v->pixel_clock[k] / (v->required_dispclk[i][j] / (j + 1)) + 42.0f * v->pixel_clock[k] / v->required_dispclk[i][j]; + if (v->no_of_dpp[i][j][k] > 1.0f) { + v->dst_x_after_scaler = v->dst_x_after_scaler + v->scaler_rec_out_width[k] / 2.0f; } if (v->output_format[k] == dcn_bw_420) { - v->dst_y_after_scaler = 1.0; + v->dst_y_after_scaler = 1.0f; + } else { + v->dst_y_after_scaler = 0.0f; } - else { - v->dst_y_after_scaler = 0.0; - } - v->time_calc = 24.0 / v->projected_dcfclk_deep_sleep; - v->v_update_offset[k][j] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0); - v->total_repeater_delay = v->max_inter_dcn_tile_repeaters * (2.0 / (v->required_dispclk[i][j] / (j + 1)) + 3.0 / v->required_dispclk[i][j]); - v->v_update_width[k][j] = (14.0 / v->projected_dcfclk_deep_sleep + 12.0 / (v->required_dispclk[i][j] / (j + 1)) + v->total_repeater_delay) * v->pixel_clock[k]; - v->v_ready_offset[k][j] = dcn_bw_max2(150.0 / (v->required_dispclk[i][j] / (j + 1)), v->total_repeater_delay + 20.0 / v->projected_dcfclk_deep_sleep + 10.0 / (v->required_dispclk[i][j] / (j + 1))) * v->pixel_clock[k]; + v->time_calc = 24.0f / v->projected_dcfclk_deep_sleep; + v->v_update_offset[k][j] = dcn_bw_ceil2(v->htotal[k] / 4.0f, 1.0f); + v->total_repeater_delay = v->max_inter_dcn_tile_repeaters * (2.0f / (v->required_dispclk[i][j] / (j + 1)) + 3.0f / v->required_dispclk[i][j]); + v->v_update_width[k][j] = (14.0f / v->projected_dcfclk_deep_sleep + 12.0f / (v->required_dispclk[i][j] / (j + 1)) + v->total_repeater_delay) * v->pixel_clock[k]; + v->v_ready_offset[k][j] = dcn_bw_max2(150.0f / (v->required_dispclk[i][j] / (j + 1)), v->total_repeater_delay + 20.0f / v->projected_dcfclk_deep_sleep + 10.0f / (v->required_dispclk[i][j] / (j + 1))) * v->pixel_clock[k]; v->time_setup = (v->v_update_offset[k][j] + v->v_update_width[k][j] + v->v_ready_offset[k][j]) / v->pixel_clock[k]; - v->extra_latency = v->urgent_round_trip_and_out_of_order_latency_per_state[i] + (v->total_number_of_active_dpp[i][j] * v->pixel_chunk_size_in_kbyte + v->total_number_of_dcc_active_dpp[i][j] * v->meta_chunk_size) * 1024.0 / v->return_bw_per_state[i]; + v->extra_latency = v->urgent_round_trip_and_out_of_order_latency_per_state[i] + (v->total_number_of_active_dpp[i][j] * v->pixel_chunk_size_in_kbyte + v->total_number_of_dcc_active_dpp[i][j] * v->meta_chunk_size) * 1024.0f / v->return_bw_per_state[i]; if (v->pte_enable == dcn_bw_yes) { - v->extra_latency = v->extra_latency + v->total_number_of_active_dpp[i][j] * v->pte_chunk_size * 1024.0 / v->return_bw_per_state[i]; + v->extra_latency = v->extra_latency + v->total_number_of_active_dpp[i][j] * v->pte_chunk_size * 1024.0f / v->return_bw_per_state[i]; } if (v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes) { - v->maximum_vstartup = v->vtotal[k] - v->vactive[k] - 1.0; - } - else { - v->maximum_vstartup = v->v_sync_plus_back_porch[k] - 1.0; + v->maximum_vstartup = v->vtotal[k] - v->vactive[k] - 1.0f; + } else { + v->maximum_vstartup = v->v_sync_plus_back_porch[k] - 1.0f; } do { v->line_times_for_prefetch[k] = v->maximum_vstartup - v->urgent_latency / (v->htotal[k] / v->pixel_clock[k]) - (v->time_calc + v->time_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dst_y_after_scaler + v->dst_x_after_scaler / v->htotal[k]); - v->line_times_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->line_times_for_prefetch[k] + 0.125), 1.0) / 4; - v->prefetch_bw[k] = (v->meta_pte_bytes_per_frame[k] + 2.0 * v->meta_row_bytes[k] + 2.0 * v->dpte_bytes_per_row[k] + v->prefetch_lines_y[k] * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] * v->swath_width_yper_state[i][j][k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0)) / (v->line_times_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]); + v->line_times_for_prefetch[k] = dcn_bw_floor2(4.0f * (v->line_times_for_prefetch[k] + 0.125f), 1.0f) / 4; + v->prefetch_bw[k] = (v->meta_pte_bytes_per_frame[k] + 2.0f * v->meta_row_bytes[k] + 2.0f * v->dpte_bytes_per_row[k] + v->prefetch_lines_y[k] * v->swath_width_yper_state[i][j][k] * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) + v->prefetch_lines_c[k] * v->swath_width_yper_state[i][j][k] / 2.0f * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f)) / (v->line_times_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]); if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) { v->time_for_meta_pte_without_immediate_flip = dcn_bw_max3( v->meta_pte_bytes_frame[k] / v->prefetch_bw[k], v->extra_latency, - v->htotal[k] / v->pixel_clock[k] / 4.0); + v->htotal[k] / v->pixel_clock[k] / 4.0f); } else { - v->time_for_meta_pte_without_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0; + v->time_for_meta_pte_without_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0f; } if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) { @@ -823,11 +737,11 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) v->extra_latency - v->time_for_meta_pte_with_immediate_flip); } - v->lines_for_meta_pte_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; - v->lines_for_meta_and_dpte_row_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; + v->lines_for_meta_pte_without_immediate_flip[k] = dcn_bw_floor2(4.0f * (v->time_for_meta_pte_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125f), 1.0f) / 4; + v->lines_for_meta_and_dpte_row_without_immediate_flip[k] = dcn_bw_floor2(4.0f * (v->time_for_meta_and_dpte_row_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125f), 1.0f) / 4; v->maximum_vstartup = v->maximum_vstartup - 1; - if (v->lines_for_meta_pte_without_immediate_flip[k] < 32.0 && v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0) + if (v->lines_for_meta_pte_without_immediate_flip[k] < 32.0f && v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0f) break; } while(1); @@ -837,100 +751,91 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) v->bw_available_for_immediate_flip = v->bw_available_for_immediate_flip -dcn_bw_max2(v->read_bandwidth[k], v->prefetch_bw[k]); } for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->total_immediate_flip_bytes[k] = 0.0; + v->total_immediate_flip_bytes[k] = 0.0f; if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { v->total_immediate_flip_bytes[k] = v->total_immediate_flip_bytes[k] + v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]; } } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) { - v->time_for_meta_pte_with_immediate_flip =dcn_bw_max5(v->meta_pte_bytes_per_frame[k] / v->prefetch_bw[k], v->meta_pte_bytes_per_frame[k] * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0); - } - else { - v->time_for_meta_pte_with_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0; + v->time_for_meta_pte_with_immediate_flip = dcn_bw_max5(v->meta_pte_bytes_per_frame[k] / v->prefetch_bw[k], v->meta_pte_bytes_per_frame[k] * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0f); + } else { + v->time_for_meta_pte_with_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0f; } if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) { - v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max5((v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k], (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency, 2.0 * v->urgent_latency); + v->time_for_meta_and_dpte_row_with_immediate_flip = dcn_bw_max5((v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k], (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency, 2.0f * v->urgent_latency); + } else { + v->time_for_meta_and_dpte_row_with_immediate_flip = dcn_bw_max2(v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency - v->time_for_meta_pte_with_immediate_flip); } - else { - v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max2(v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency - v->time_for_meta_pte_with_immediate_flip); - } - v->lines_for_meta_pte_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; - v->lines_for_meta_and_dpte_row_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; + v->lines_for_meta_pte_with_immediate_flip[k] = dcn_bw_floor2(4.0f * (v->time_for_meta_pte_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125f), 1.0f) / 4; + v->lines_for_meta_and_dpte_row_with_immediate_flip[k] = dcn_bw_floor2(4.0f * (v->time_for_meta_and_dpte_row_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125f), 1.0f) / 4; v->line_times_to_request_prefetch_pixel_data_with_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_with_immediate_flip[k] - v->lines_for_meta_and_dpte_row_with_immediate_flip[k]; v->line_times_to_request_prefetch_pixel_data_without_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_without_immediate_flip[k] - v->lines_for_meta_and_dpte_row_without_immediate_flip[k]; - if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip > 0.0) { + if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip > 0.0f) { v->v_ratio_pre_ywith_immediate_flip[i][j][k] = v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip; - if ((v->swath_height_yper_state[i][j][k] > 4.0)) { - if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0 > 0.0) { - v->v_ratio_pre_ywith_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_ywith_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0)); - } - else { - v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0; + if ((v->swath_height_yper_state[i][j][k] > 4.0f)) { + if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0f) / 2.0f > 0.0f) { + v->v_ratio_pre_ywith_immediate_flip[i][j][k] = dcn_bw_max2(v->v_ratio_pre_ywith_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0f) / 2.0f)); + } else { + v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0f; } } v->v_ratio_pre_cwith_immediate_flip[i][j][k] = v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip; - if ((v->swath_height_cper_state[i][j][k] > 4.0)) { - if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0 > 0.0) { - v->v_ratio_pre_cwith_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_cwith_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0)); - } - else { - v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0; + if ((v->swath_height_cper_state[i][j][k] > 4.0f)) { + if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0f) / 2.0f > 0.0f) { + v->v_ratio_pre_cwith_immediate_flip[i][j][k] = dcn_bw_max2(v->v_ratio_pre_cwith_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0f) / 2.0f)); + } else { + v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0f; } } - v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]); + v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 2.0f) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]); + } else { + v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0f; + v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0f; + v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = 999999.0f; } - else { - v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0; - v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0; - v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = 999999.0; - } - if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip > 0.0) { + if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip > 0.0f) { v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip; - if ((v->swath_height_yper_state[i][j][k] > 4.0)) { - if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0 > 0.0) { - v->v_ratio_pre_ywithout_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_ywithout_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0)); - } - else { - v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0; + if ((v->swath_height_yper_state[i][j][k] > 4.0f)) { + if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0f) / 2.0f > 0.0f) { + v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = dcn_bw_max2(v->v_ratio_pre_ywithout_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0f) / 2.0f)); + } else { + v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0f; } } v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip; - if ((v->swath_height_cper_state[i][j][k] > 4.0)) { - if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0 > 0.0) { - v->v_ratio_pre_cwithout_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_cwithout_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0)); - } - else { - v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0; + if ((v->swath_height_cper_state[i][j][k] > 4.0f)) { + if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0f) / 2.0f > 0.0f) { + v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = dcn_bw_max2(v->v_ratio_pre_cwithout_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0f) / 2.0f)); + } else { + v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0f; } } - v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]); - } - else { - v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0; - v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0; - v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = 999999.0; + v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 2.0f) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]); + } else { + v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0f; + v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0f; + v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = 999999.0f; } } - v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = 0.0; + v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { - v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k]) +dcn_bw_max2(v->meta_pte_bytes_per_frame[k] / (v->lines_for_meta_pte_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / (v->lines_for_meta_and_dpte_row_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k])); - } - else { - v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]); + v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip + dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k]) + dcn_bw_max2(v->meta_pte_bytes_per_frame[k] / (v->lines_for_meta_pte_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / (v->lines_for_meta_and_dpte_row_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k])); + } else { + v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip + dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]); } } - v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = 0.0; + v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = v->maximum_read_bandwidth_with_prefetch_without_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]); + v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = v->maximum_read_bandwidth_with_prefetch_without_immediate_flip + dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]); } v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_yes; if (v->maximum_read_bandwidth_with_prefetch_with_immediate_flip > v->return_bw_per_state[i]) { v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no; } for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->line_times_for_prefetch[k] < 2.0 || v->lines_for_meta_pte_with_immediate_flip[k] >= 8.0 || v->lines_for_meta_and_dpte_row_with_immediate_flip[k] >= 16.0) { + if (v->line_times_for_prefetch[k] < 2.0f || v->lines_for_meta_pte_with_immediate_flip[k] >= 8.0f || v->lines_for_meta_and_dpte_row_with_immediate_flip[k] >= 16.0f) { v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no; } } @@ -939,7 +844,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no; } for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->line_times_for_prefetch[k] < 2.0 || v->lines_for_meta_pte_without_immediate_flip[k] >= 8.0 || v->lines_for_meta_and_dpte_row_without_immediate_flip[k] >= 16.0) { + if (v->line_times_for_prefetch[k] < 2.0f || v->lines_for_meta_pte_without_immediate_flip[k] >= 8.0f || v->lines_for_meta_and_dpte_row_without_immediate_flip[k] >= 16.0f) { v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no; } } @@ -949,13 +854,13 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) for (j = 0; j <= 1; j++) { v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if ((((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywith_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwith_immediate_flip[i][j][k] > 4.0)) || ((v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 || v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0)))) { + if ((((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywith_immediate_flip[i][j][k] > 4.0f || v->v_ratio_pre_cwith_immediate_flip[i][j][k] > 4.0f)) || ((v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 || v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0f || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0f)))) { v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no; } } v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if ((v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0)) { + if ((v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0f || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0f)) { v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no; } } @@ -968,18 +873,15 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) if (v->scale_ratio_support == dcn_bw_yes && v->source_format_pixel_and_scan_support == dcn_bw_yes && v->viewport_size_support == dcn_bw_yes && v->bandwidth_support[i] == dcn_bw_yes && v->dio_support[i] == dcn_bw_yes && v->urgent_latency_support[i][j] == dcn_bw_yes && v->rob_support[i] == dcn_bw_yes && v->dispclk_dppclk_support[i][j] == dcn_bw_yes && v->total_available_pipes_support[i][j] == dcn_bw_yes && v->total_available_writeback_support == dcn_bw_yes && v->writeback_latency_support == dcn_bw_yes) { if (v->prefetch_supported_with_immediate_flip[i][j] == dcn_bw_yes && v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] == dcn_bw_yes) { v->mode_support_with_immediate_flip[i][j] = dcn_bw_yes; - } - else { + } else { v->mode_support_with_immediate_flip[i][j] = dcn_bw_no; } if (v->prefetch_supported_without_immediate_flip[i][j] == dcn_bw_yes && v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] == dcn_bw_yes) { v->mode_support_without_immediate_flip[i][j] = dcn_bw_yes; - } - else { + } else { v->mode_support_without_immediate_flip[i][j] = dcn_bw_no; } - } - else { + } else { v->mode_support_with_immediate_flip[i][j] = dcn_bw_no; v->mode_support_without_immediate_flip[i][j] = dcn_bw_no; } @@ -987,21 +889,20 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) } for (i = number_of_states_plus_one; i >= 0; i--) { if ((i == number_of_states_plus_one || v->mode_support_with_immediate_flip[i][1] == dcn_bw_yes || v->mode_support_with_immediate_flip[i][0] == dcn_bw_yes) && i >= v->voltage_override_level) { - v->voltage_level_with_immediate_flip = i; + v->voltage_level_with_immediate_flip = (float)i; } } for (i = number_of_states_plus_one; i >= 0; i--) { if ((i == number_of_states_plus_one || v->mode_support_without_immediate_flip[i][1] == dcn_bw_yes || v->mode_support_without_immediate_flip[i][0] == dcn_bw_yes) && i >= v->voltage_override_level) { - v->voltage_level_without_immediate_flip = i; + v->voltage_level_without_immediate_flip = (float)i; } } if (v->voltage_level_with_immediate_flip == number_of_states_plus_one) { v->immediate_flip_supported = dcn_bw_no; - v->voltage_level = v->voltage_level_without_immediate_flip; - } - else { + v->voltage_level = (int)v->voltage_level_without_immediate_flip; + } else { v->immediate_flip_supported = dcn_bw_yes; - v->voltage_level = v->voltage_level_with_immediate_flip; + v->voltage_level = (int)v->voltage_level_with_immediate_flip; } v->dcfclk = v->dcfclk_per_state[v->voltage_level]; v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level]; @@ -1021,16 +922,15 @@ void display_pipe_configuration(struct dcn_bw_internal_vars *v) /*display pipe configuration*/ for (j = 0; j <= 1; j++) { - v->total_number_of_active_dpp_per_ratio[j] = 0.0; + v->total_number_of_active_dpp_per_ratio[j] = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { v->total_number_of_active_dpp_per_ratio[j] = v->total_number_of_active_dpp_per_ratio[j] + v->dpp_per_plane_per_ratio[j][k]; } } - if ((v->dispclk_dppclk_support_per_ratio[0] == dcn_bw_yes && v->dispclk_dppclk_support_per_ratio[1] == dcn_bw_no) || (v->dispclk_dppclk_support_per_ratio[0] == v->dispclk_dppclk_support_per_ratio[1] && (v->total_number_of_active_dpp_per_ratio[0] < v->total_number_of_active_dpp_per_ratio[1] || (((v->total_number_of_active_dpp_per_ratio[0] == v->total_number_of_active_dpp_per_ratio[1]) && v->required_dispclk_per_ratio[0] <= 0.5 * v->required_dispclk_per_ratio[1]))))) { + if ((v->dispclk_dppclk_support_per_ratio[0] == dcn_bw_yes && v->dispclk_dppclk_support_per_ratio[1] == dcn_bw_no) || (v->dispclk_dppclk_support_per_ratio[0] == v->dispclk_dppclk_support_per_ratio[1] && (v->total_number_of_active_dpp_per_ratio[0] < v->total_number_of_active_dpp_per_ratio[1] || (((v->total_number_of_active_dpp_per_ratio[0] == v->total_number_of_active_dpp_per_ratio[1]) && v->required_dispclk_per_ratio[0] <= 0.5f * v->required_dispclk_per_ratio[1]))))) { v->dispclk_dppclk_ratio = 1; v->final_error_message = v->error_message[0]; - } - else { + } else { v->dispclk_dppclk_ratio = 2; v->final_error_message = v->error_message[1]; } @@ -1039,137 +939,116 @@ void display_pipe_configuration(struct dcn_bw_internal_vars *v) } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { - v->byte_per_pix_dety = 8.0; - v->byte_per_pix_detc = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { - v->byte_per_pix_dety = 4.0; - v->byte_per_pix_detc = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { - v->byte_per_pix_dety = 2.0; - v->byte_per_pix_detc = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { - v->byte_per_pix_dety = 1.0; - v->byte_per_pix_detc = 2.0; - } - else { + v->byte_per_pix_dety = 8.0f; + v->byte_per_pix_detc = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { + v->byte_per_pix_dety = 4.0f; + v->byte_per_pix_detc = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { + v->byte_per_pix_dety = 2.0f; + v->byte_per_pix_detc = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { + v->byte_per_pix_dety = 1.0f; + v->byte_per_pix_detc = 2.0f; + } else { v->byte_per_pix_dety = 4.0f / 3.0f; v->byte_per_pix_detc = 8.0f / 3.0f; } if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->read256_bytes_block_height_y = 1.0; + v->read256_bytes_block_height_y = 1.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { + v->read256_bytes_block_height_y = 4.0f; + } else { + v->read256_bytes_block_height_y = 8.0f; } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { - v->read256_bytes_block_height_y = 4.0; - } - else { - v->read256_bytes_block_height_y = 8.0; - } - v->read256_bytes_block_width_y = 256.0 /dcn_bw_ceil2(v->byte_per_pix_dety, 1.0) / v->read256_bytes_block_height_y; - v->read256_bytes_block_height_c = 0.0; - v->read256_bytes_block_width_c = 0.0; - } - else { + v->read256_bytes_block_width_y = 256.0f / dcn_bw_ceil2(v->byte_per_pix_dety, 1.0f) / v->read256_bytes_block_height_y; + v->read256_bytes_block_height_c = 0.0f; + v->read256_bytes_block_width_c = 0.0f; + } else { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->read256_bytes_block_height_y = 1.0; - v->read256_bytes_block_height_c = 1.0; + v->read256_bytes_block_height_y = 1.0f; + v->read256_bytes_block_height_c = 1.0f; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { + v->read256_bytes_block_height_y = 16.0f; + v->read256_bytes_block_height_c = 8.0f; + } else { + v->read256_bytes_block_height_y = 8.0f; + v->read256_bytes_block_height_c = 8.0f; } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { - v->read256_bytes_block_height_y = 16.0; - v->read256_bytes_block_height_c = 8.0; - } - else { - v->read256_bytes_block_height_y = 8.0; - v->read256_bytes_block_height_c = 8.0; - } - v->read256_bytes_block_width_y = 256.0 /dcn_bw_ceil2(v->byte_per_pix_dety, 1.0) / v->read256_bytes_block_height_y; - v->read256_bytes_block_width_c = 256.0 /dcn_bw_ceil2(v->byte_per_pix_detc, 2.0) / v->read256_bytes_block_height_c; + v->read256_bytes_block_width_y = 256.0f / dcn_bw_ceil2(v->byte_per_pix_dety, 1.0f) / v->read256_bytes_block_height_y; + v->read256_bytes_block_width_c = 256.0f / dcn_bw_ceil2(v->byte_per_pix_detc, 2.0f) / v->read256_bytes_block_height_c; } if (v->source_scan[k] == dcn_bw_hor) { v->maximum_swath_height_y = v->read256_bytes_block_height_y; v->maximum_swath_height_c = v->read256_bytes_block_height_c; - } - else { + } else { v->maximum_swath_height_y = v->read256_bytes_block_width_y; v->maximum_swath_height_c = v->read256_bytes_block_width_c; } if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) { if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) { v->minimum_swath_height_y = v->maximum_swath_height_y; - } - else { - v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0; + } else { + v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0f; } v->minimum_swath_height_c = v->maximum_swath_height_c; - } - else { + } else { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { v->minimum_swath_height_y = v->maximum_swath_height_y; v->minimum_swath_height_c = v->maximum_swath_height_c; - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) { - v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) { + v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0f; if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) { v->minimum_swath_height_c = v->maximum_swath_height_c; + } else { + v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0f; } - else { - v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0; - } - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) { - v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) { + v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0f; if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) { v->minimum_swath_height_y = v->maximum_swath_height_y; + } else { + v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0f; } - else { - v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0; - } - } - else { + } else { v->minimum_swath_height_y = v->maximum_swath_height_y; v->minimum_swath_height_c = v->maximum_swath_height_c; } } if (v->source_scan[k] == dcn_bw_hor) { v->swath_width = v->viewport_width[k] / v->dpp_per_plane[k]; - } - else { + } else { v->swath_width = v->viewport_height[k] / v->dpp_per_plane[k]; } - v->swath_width_granularity_y = 256.0 /dcn_bw_ceil2(v->byte_per_pix_dety, 1.0) / v->maximum_swath_height_y; - v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(v->swath_width - 1.0, v->swath_width_granularity_y) + v->swath_width_granularity_y) * v->byte_per_pix_dety * v->maximum_swath_height_y; + v->swath_width_granularity_y = 256.0f / dcn_bw_ceil2(v->byte_per_pix_dety, 1.0f) / v->maximum_swath_height_y; + v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(v->swath_width - 1.0f, v->swath_width_granularity_y) + v->swath_width_granularity_y) * v->byte_per_pix_dety * v->maximum_swath_height_y; if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) { - v->rounded_up_max_swath_size_bytes_y =dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_y, 256.0) + 256; + v->rounded_up_max_swath_size_bytes_y = dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_y, 256.0f) + 256; } - if (v->maximum_swath_height_c > 0.0) { - v->swath_width_granularity_c = 256.0 /dcn_bw_ceil2(v->byte_per_pix_detc, 2.0) / v->maximum_swath_height_c; - v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(v->swath_width / 2.0 - 1.0, v->swath_width_granularity_c) + v->swath_width_granularity_c) * v->byte_per_pix_detc * v->maximum_swath_height_c; + if (v->maximum_swath_height_c > 0.0f) { + v->swath_width_granularity_c = 256.0f / dcn_bw_ceil2(v->byte_per_pix_detc, 2.0f) / v->maximum_swath_height_c; + v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(v->swath_width / 2.0f - 1.0f, v->swath_width_granularity_c) + v->swath_width_granularity_c) * v->byte_per_pix_detc * v->maximum_swath_height_c; if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) { - v->rounded_up_max_swath_size_bytes_c = dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_c, 256.0) + 256; + v->rounded_up_max_swath_size_bytes_c = dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_c, 256.0f) + 256; } } - if (v->rounded_up_max_swath_size_bytes_y + v->rounded_up_max_swath_size_bytes_c <= v->det_buffer_size_in_kbyte * 1024.0 / 2.0) { + if (v->rounded_up_max_swath_size_bytes_y + v->rounded_up_max_swath_size_bytes_c <= v->det_buffer_size_in_kbyte * 1024.0f / 2.0f) { v->swath_height_y[k] = v->maximum_swath_height_y; v->swath_height_c[k] = v->maximum_swath_height_c; - } - else { + } else { v->swath_height_y[k] = v->minimum_swath_height_y; v->swath_height_c[k] = v->minimum_swath_height_c; } - if (v->swath_height_c[k] == 0.0) { - v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0; - v->det_buffer_size_c[k] = 0.0; - } - else if (v->swath_height_y[k] <= v->swath_height_c[k]) { - v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0; - v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0; - } - else { - v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0; - v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 3.0; + if (v->swath_height_c[k] == 0.0f) { + v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0f; + v->det_buffer_size_c[k] = 0.0f; + } else if (v->swath_height_y[k] <= v->swath_height_c[k]) { + v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0f / 2.0f; + v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0f / 2.0f; + } else { + v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0f * 2.0f / 3.0f; + v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0f / 3.0f; } } } @@ -1178,52 +1057,46 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan int k; /*dispclk and dppclk calculation*/ - v->dispclk_with_ramping = 0.0; - v->dispclk_without_ramping = 0.0; + v->dispclk_with_ramping = 0.0f; + v->dispclk_without_ramping = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->h_ratio[k] > 1.0) { - v->pscl_throughput[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] /dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0)); + if (v->h_ratio[k] > 1.0f) { + v->pscl_throughput[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / dcn_bw_ceil2(v->htaps[k] / 6.0f, 1.0f)); + } else { + v->pscl_throughput[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); } - else { - v->pscl_throughput[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); - } - v->dppclk_using_single_dpp_luma = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_throughput[k], 1.0); + v->dppclk_using_single_dpp_luma = v->pixel_clock[k] * dcn_bw_max3(v->vtaps[k] / 6.0f * dcn_bw_min2(1.0f, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_throughput[k], 1.0f); if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { - v->pscl_throughput_chroma[k] = 0.0; + v->pscl_throughput_chroma[k] = 0.0f; v->dppclk_using_single_dpp = v->dppclk_using_single_dpp_luma; - } - else { - if (v->h_ratio[k] > 1.0) { - v->pscl_throughput_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0 /dcn_bw_ceil2(v->hta_pschroma[k] / 6.0, 1.0)); + } else { + if (v->h_ratio[k] > 1.0f) { + v->pscl_throughput_chroma[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0f / dcn_bw_ceil2(v->hta_pschroma[k] / 6.0f, 1.0f)); + } else { + v->pscl_throughput_chroma[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); } - else { - v->pscl_throughput_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); - } - v->dppclk_using_single_dpp_chroma = v->pixel_clock[k] *dcn_bw_max3(v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_throughput_chroma[k], 1.0); - v->dppclk_using_single_dpp =dcn_bw_max2(v->dppclk_using_single_dpp_luma, v->dppclk_using_single_dpp_chroma); + v->dppclk_using_single_dpp_chroma = v->pixel_clock[k] * dcn_bw_max3(v->vta_pschroma[k] / 6.0f * dcn_bw_min2(1.0f, v->h_ratio[k] / 2.0f), v->h_ratio[k] * v->v_ratio[k] / 4.0f / v->pscl_throughput_chroma[k], 1.0f); + v->dppclk_using_single_dpp = dcn_bw_max2(v->dppclk_using_single_dpp_luma, v->dppclk_using_single_dpp_chroma); } if (v->odm_capable == dcn_bw_yes) { - v->dispclk_with_ramping =dcn_bw_max2(v->dispclk_with_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0 + v->downspreading / 100.0) * (1.0 + v->dispclk_ramping_margin / 100.0)); - v->dispclk_without_ramping =dcn_bw_max2(v->dispclk_without_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0 + v->downspreading / 100.0)); - } - else { - v->dispclk_with_ramping =dcn_bw_max2(v->dispclk_with_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0 + v->downspreading / 100.0) * (1.0 + v->dispclk_ramping_margin / 100.0)); - v->dispclk_without_ramping =dcn_bw_max2(v->dispclk_without_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0 + v->downspreading / 100.0)); + v->dispclk_with_ramping = dcn_bw_max2(v->dispclk_with_ramping, dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0f + v->downspreading / 100.0f) * (1.0f + v->dispclk_ramping_margin / 100.0f)); + v->dispclk_without_ramping = dcn_bw_max2(v->dispclk_without_ramping, dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0f + v->downspreading / 100.0f)); + } else { + v->dispclk_with_ramping = dcn_bw_max2(v->dispclk_with_ramping, dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0f + v->downspreading / 100.0f) * (1.0f + v->dispclk_ramping_margin / 100.0f)); + v->dispclk_without_ramping = dcn_bw_max2(v->dispclk_without_ramping, dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0f + v->downspreading / 100.0f)); } } if (v->dispclk_without_ramping > v->max_dispclk[number_of_states]) { v->dispclk = v->dispclk_without_ramping; - } - else if (v->dispclk_with_ramping > v->max_dispclk[number_of_states]) { + } else if (v->dispclk_with_ramping > v->max_dispclk[number_of_states]) { v->dispclk = v->max_dispclk[number_of_states]; - } - else { + } else { v->dispclk = v->dispclk_with_ramping; } v->dppclk = v->dispclk / v->dispclk_dppclk_ratio; /*urgent watermark*/ - v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0); + v->return_bandwidth_to_dcn = dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0f * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0f); v->dcc_enabled_any_plane = dcn_bw_no; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->dcc_enable[k] == dcn_bw_yes) { @@ -1231,129 +1104,119 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan } } v->return_bw = v->return_bandwidth_to_dcn; - if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) { - v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency))); + if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0f) { + v->return_bw = dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0f * (1.0f - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0f) + v->urgent_latency))); } - v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0); - if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0 && v->critical_compression < 4.0) { - v->return_bw =dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0 * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2)); + v->critical_compression = 2.0f * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f); + if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0f && v->critical_compression < 4.0f) { + v->return_bw = dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0f * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f), 2)); } - v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0); - if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) { - v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency))); + v->return_bandwidth_to_dcn = dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0f); + if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0f) { + v->return_bw = dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0f * (1.0f - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0f) + v->urgent_latency))); } - v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0); - if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0 && v->critical_compression < 4.0) { - v->return_bw =dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0 * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2)); + v->critical_compression = 2.0f * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f); + if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0f && v->critical_compression < 4.0f) { + v->return_bw = dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0f * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f), 2)); } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->source_scan[k] == dcn_bw_hor) { v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k]; - } - else { + } else { v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k]; } } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { - v->byte_per_pixel_dety[k] = 8.0; - v->byte_per_pixel_detc[k] = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { - v->byte_per_pixel_dety[k] = 4.0; - v->byte_per_pixel_detc[k] = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { - v->byte_per_pixel_dety[k] = 2.0; - v->byte_per_pixel_detc[k] = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { - v->byte_per_pixel_dety[k] = 1.0; - v->byte_per_pixel_detc[k] = 2.0; - } - else { + v->byte_per_pixel_dety[k] = 8.0f; + v->byte_per_pixel_detc[k] = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { + v->byte_per_pixel_dety[k] = 4.0f; + v->byte_per_pixel_detc[k] = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { + v->byte_per_pixel_dety[k] = 2.0f; + v->byte_per_pixel_detc[k] = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { + v->byte_per_pixel_dety[k] = 1.0f; + v->byte_per_pixel_detc[k] = 2.0f; + } else { v->byte_per_pixel_dety[k] = 4.0f / 3.0f; v->byte_per_pixel_detc[k] = 8.0f / 3.0f; } } - v->total_data_read_bandwidth = 0.0; + v->total_data_read_bandwidth = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k]; - v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0; + v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k]; + v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0f * v->dpp_per_plane[k] * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0f; v->total_data_read_bandwidth = v->total_data_read_bandwidth + v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k]; } - v->total_active_dpp = 0.0; - v->total_dcc_active_dpp = 0.0; + v->total_active_dpp = 0.0f; + v->total_dcc_active_dpp = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { v->total_active_dpp = v->total_active_dpp + v->dpp_per_plane[k]; if (v->dcc_enable[k] == dcn_bw_yes) { v->total_dcc_active_dpp = v->total_dcc_active_dpp + v->dpp_per_plane[k]; } } - v->urgent_round_trip_and_out_of_order_latency = (v->round_trip_ping_latency_cycles + 32.0) / v->dcfclk + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw; - v->last_pixel_of_line_extra_watermark = 0.0; + v->urgent_round_trip_and_out_of_order_latency = (v->round_trip_ping_latency_cycles + 32.0f) / v->dcfclk + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw; + v->last_pixel_of_line_extra_watermark = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->v_ratio[k] <= 1.0) { + if (v->v_ratio[k] <= 1.0f) { v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k]; - } - else { + } else { v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; } - v->data_fabric_line_delivery_time_luma = v->swath_width_y[k] * v->swath_height_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->return_bw * v->read_bandwidth_plane_luma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth); - v->last_pixel_of_line_extra_watermark =dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_luma - v->display_pipe_line_delivery_time_luma[k]); - if (v->byte_per_pixel_detc[k] == 0.0) { - v->display_pipe_line_delivery_time_chroma[k] = 0.0; - } - else { - if (v->v_ratio[k] / 2.0 <= 1.0) { - v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] / (v->h_ratio[k] / 2.0) / v->pixel_clock[k]; + v->data_fabric_line_delivery_time_luma = v->swath_width_y[k] * v->swath_height_y[k] * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / (v->return_bw * v->read_bandwidth_plane_luma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth); + v->last_pixel_of_line_extra_watermark = dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_luma - v->display_pipe_line_delivery_time_luma[k]); + if (v->byte_per_pixel_detc[k] == 0.0f) { + v->display_pipe_line_delivery_time_chroma[k] = 0.0f; + } else { + if (v->v_ratio[k] / 2.0f <= 1.0f) { + v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0f * v->dpp_per_plane[k] / (v->h_ratio[k] / 2.0f) / v->pixel_clock[k]; + } else { + v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0f / v->pscl_throughput_chroma[k] / v->dppclk; } - else { - v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 / v->pscl_throughput_chroma[k] / v->dppclk; - } - v->data_fabric_line_delivery_time_chroma = v->swath_width_y[k] / 2.0 * v->swath_height_c[k] *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->return_bw * v->read_bandwidth_plane_chroma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth); - v->last_pixel_of_line_extra_watermark =dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_chroma - v->display_pipe_line_delivery_time_chroma[k]); + v->data_fabric_line_delivery_time_chroma = v->swath_width_y[k] / 2.0f * v->swath_height_c[k] * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / (v->return_bw * v->read_bandwidth_plane_chroma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth); + v->last_pixel_of_line_extra_watermark = dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_chroma - v->display_pipe_line_delivery_time_chroma[k]); } } - v->urgent_extra_latency = v->urgent_round_trip_and_out_of_order_latency + (v->total_active_dpp * v->pixel_chunk_size_in_kbyte + v->total_dcc_active_dpp * v->meta_chunk_size) * 1024.0 / v->return_bw; + v->urgent_extra_latency = v->urgent_round_trip_and_out_of_order_latency + (v->total_active_dpp * v->pixel_chunk_size_in_kbyte + v->total_dcc_active_dpp * v->meta_chunk_size) * 1024.0f / v->return_bw; if (v->pte_enable == dcn_bw_yes) { - v->urgent_extra_latency = v->urgent_extra_latency + v->total_active_dpp * v->pte_chunk_size * 1024.0 / v->return_bw; + v->urgent_extra_latency = v->urgent_extra_latency + v->total_active_dpp * v->pte_chunk_size * 1024.0f / v->return_bw; } v->urgent_watermark = v->urgent_latency + v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency; - v->ptemeta_urgent_watermark = v->urgent_watermark + 2.0 * v->urgent_latency; + v->ptemeta_urgent_watermark = v->urgent_watermark + 2.0f * v->urgent_latency; /*nb p-state/dram clock change watermark*/ v->dram_clock_change_watermark = v->dram_clock_change_latency + v->urgent_watermark; - v->total_active_writeback = 0.0; + v->total_active_writeback = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->output[k] == dcn_bw_writeback) { - v->total_active_writeback = v->total_active_writeback + 1.0; + v->total_active_writeback = v->total_active_writeback + 1.0f; } } - if (v->total_active_writeback <= 1.0) { + if (v->total_active_writeback <= 1.0f) { v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency + v->write_back_latency; - } - else { - v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency + v->write_back_latency + v->writeback_chunk_size * 1024.0 / 32.0 / v->socclk; + } else { + v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency + v->write_back_latency + v->writeback_chunk_size * 1024.0f / 32.0f / v->socclk; } /*stutter efficiency*/ for (k = 0; k <= v->number_of_active_planes - 1; k++) { v->lines_in_dety[k] = v->det_buffer_size_y[k] / v->byte_per_pixel_dety[k] / v->swath_width_y[k]; - v->lines_in_dety_rounded_down_to_swath[k] =dcn_bw_floor2(v->lines_in_dety[k], v->swath_height_y[k]); + v->lines_in_dety_rounded_down_to_swath[k] = dcn_bw_floor2(v->lines_in_dety[k], v->swath_height_y[k]); v->full_det_buffering_time_y[k] = v->lines_in_dety_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k]; - if (v->byte_per_pixel_detc[k] > 0.0) { - v->lines_in_detc[k] = v->det_buffer_size_c[k] / v->byte_per_pixel_detc[k] / (v->swath_width_y[k] / 2.0); - v->lines_in_detc_rounded_down_to_swath[k] =dcn_bw_floor2(v->lines_in_detc[k], v->swath_height_c[k]); - v->full_det_buffering_time_c[k] = v->lines_in_detc_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0); - } - else { - v->lines_in_detc[k] = 0.0; - v->lines_in_detc_rounded_down_to_swath[k] = 0.0; - v->full_det_buffering_time_c[k] = 999999.0; + if (v->byte_per_pixel_detc[k] > 0.0f) { + v->lines_in_detc[k] = v->det_buffer_size_c[k] / v->byte_per_pixel_detc[k] / (v->swath_width_y[k] / 2.0f); + v->lines_in_detc_rounded_down_to_swath[k] = dcn_bw_floor2(v->lines_in_detc[k], v->swath_height_c[k]); + v->full_det_buffering_time_c[k] = v->lines_in_detc_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0f); + } else { + v->lines_in_detc[k] = 0.0f; + v->lines_in_detc_rounded_down_to_swath[k] = 0.0f; + v->full_det_buffering_time_c[k] = 999999.0f; } } - v->min_full_det_buffering_time = 999999.0; + v->min_full_det_buffering_time = 999999.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->full_det_buffering_time_y[k] < v->min_full_det_buffering_time) { v->min_full_det_buffering_time = v->full_det_buffering_time_y[k]; @@ -1364,76 +1227,71 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k] / v->pixel_clock[k]; } } - v->average_read_bandwidth_gbyte_per_second = 0.0; + v->average_read_bandwidth_gbyte_per_second = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->dcc_enable[k] == dcn_bw_yes) { - v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / v->dcc_rate[k] / 1000.0 + v->read_bandwidth_plane_chroma[k] / v->dcc_rate[k] / 1000.0; - } - else { - v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 + v->read_bandwidth_plane_chroma[k] / 1000.0; + v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / v->dcc_rate[k] / 1000.0f + v->read_bandwidth_plane_chroma[k] / v->dcc_rate[k] / 1000.0f; + } else { + v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0f + v->read_bandwidth_plane_chroma[k] / 1000.0f; } if (v->dcc_enable[k] == dcn_bw_yes) { - v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 / 256.0 + v->read_bandwidth_plane_chroma[k] / 1000.0 / 256.0; + v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0f / 256.0f + v->read_bandwidth_plane_chroma[k] / 1000.0f / 256.0f; } if (v->pte_enable == dcn_bw_yes) { - v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 / 512.0 + v->read_bandwidth_plane_chroma[k] / 1000.0 / 512.0; + v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0f / 512.0f + v->read_bandwidth_plane_chroma[k] / 1000.0f / 512.0f; } } - v->part_of_burst_that_fits_in_rob =dcn_bw_min2(v->min_full_det_buffering_time * v->total_data_read_bandwidth, v->rob_buffer_size_in_kbyte * 1024.0 * v->total_data_read_bandwidth / (v->average_read_bandwidth_gbyte_per_second * 1000.0)); - v->stutter_burst_time = v->part_of_burst_that_fits_in_rob * (v->average_read_bandwidth_gbyte_per_second * 1000.0) / v->total_data_read_bandwidth / v->return_bw + (v->min_full_det_buffering_time * v->total_data_read_bandwidth - v->part_of_burst_that_fits_in_rob) / (v->dcfclk * 64.0); - if (v->total_active_writeback == 0.0) { - v->stutter_efficiency_not_including_vblank = (1.0 - (v->sr_exit_time + v->stutter_burst_time) / v->min_full_det_buffering_time) * 100.0; + v->part_of_burst_that_fits_in_rob = dcn_bw_min2(v->min_full_det_buffering_time * v->total_data_read_bandwidth, v->rob_buffer_size_in_kbyte * 1024.0f * v->total_data_read_bandwidth / (v->average_read_bandwidth_gbyte_per_second * 1000.0f)); + v->stutter_burst_time = v->part_of_burst_that_fits_in_rob * (v->average_read_bandwidth_gbyte_per_second * 1000.0f) / v->total_data_read_bandwidth / v->return_bw + (v->min_full_det_buffering_time * v->total_data_read_bandwidth - v->part_of_burst_that_fits_in_rob) / (v->dcfclk * 64.0f); + if (v->total_active_writeback == 0.0f) { + v->stutter_efficiency_not_including_vblank = (1.0f - (v->sr_exit_time + v->stutter_burst_time) / v->min_full_det_buffering_time) * 100.0f; + } else { + v->stutter_efficiency_not_including_vblank = 0.0f; } - else { - v->stutter_efficiency_not_including_vblank = 0.0; - } - v->smallest_vblank = 999999.0; + v->smallest_vblank = 999999.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->synchronized_vblank == dcn_bw_yes || v->number_of_active_planes == 1) { v->v_blank_time = (v->vtotal[k] - v->vactive[k]) * v->htotal[k] / v->pixel_clock[k]; + } else { + v->v_blank_time = 0.0f; } - else { - v->v_blank_time = 0.0; - } - v->smallest_vblank =dcn_bw_min2(v->smallest_vblank, v->v_blank_time); + v->smallest_vblank = dcn_bw_min2(v->smallest_vblank, v->v_blank_time); } - v->stutter_efficiency = (v->stutter_efficiency_not_including_vblank / 100.0 * (v->frame_time_for_min_full_det_buffering_time - v->smallest_vblank) + v->smallest_vblank) / v->frame_time_for_min_full_det_buffering_time * 100.0; + v->stutter_efficiency = (v->stutter_efficiency_not_including_vblank / 100.0f * (v->frame_time_for_min_full_det_buffering_time - v->smallest_vblank) + v->smallest_vblank) / v->frame_time_for_min_full_det_buffering_time * 100.0f; /*dcfclk deep sleep*/ for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->byte_per_pixel_detc[k] > 0.0) { - v->dcfclk_deep_sleep_per_plane[k] =dcn_bw_max2(1.1 * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 32.0 / v->display_pipe_line_delivery_time_luma[k], 1.1 * v->swath_width_y[k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 32.0 / v->display_pipe_line_delivery_time_chroma[k]); + if (v->byte_per_pixel_detc[k] > 0.0f) { + v->dcfclk_deep_sleep_per_plane[k] = dcn_bw_max2(1.1f * v->swath_width_y[k] * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / 32.0f / v->display_pipe_line_delivery_time_luma[k], 1.1f * v->swath_width_y[k] / 2.0f * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / 32.0f / v->display_pipe_line_delivery_time_chroma[k]); + } else { + v->dcfclk_deep_sleep_per_plane[k] = 1.1f * v->swath_width_y[k] * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / 64.0f / v->display_pipe_line_delivery_time_luma[k]; } - else { - v->dcfclk_deep_sleep_per_plane[k] = 1.1 * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 64.0 / v->display_pipe_line_delivery_time_luma[k]; - } - v->dcfclk_deep_sleep_per_plane[k] =dcn_bw_max2(v->dcfclk_deep_sleep_per_plane[k], v->pixel_clock[k] / 16.0); + v->dcfclk_deep_sleep_per_plane[k] = dcn_bw_max2(v->dcfclk_deep_sleep_per_plane[k], v->pixel_clock[k] / 16.0f); } - v->dcf_clk_deep_sleep = 8.0; + v->dcf_clk_deep_sleep = 8.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->dcf_clk_deep_sleep =dcn_bw_max2(v->dcf_clk_deep_sleep, v->dcfclk_deep_sleep_per_plane[k]); + v->dcf_clk_deep_sleep = dcn_bw_max2(v->dcf_clk_deep_sleep, v->dcfclk_deep_sleep_per_plane[k]); } /*stutter watermark*/ - v->stutter_exit_watermark = v->sr_exit_time + v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency + 10.0 / v->dcf_clk_deep_sleep; + v->stutter_exit_watermark = v->sr_exit_time + v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency + 10.0f / v->dcf_clk_deep_sleep; v->stutter_enter_plus_exit_watermark = v->sr_enter_plus_exit_time + v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency; /*urgent latency supported*/ for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->effective_det_plus_lb_lines_luma =dcn_bw_floor2(v->lines_in_dety[k] +dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixel_dety[k] * v->pscl_throughput[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_y[k]); + v->effective_det_plus_lb_lines_luma = dcn_bw_floor2(v->lines_in_dety[k] + dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixel_dety[k] * v->pscl_throughput[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_y[k]); v->urgent_latency_support_us_luma = v->effective_det_plus_lb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_det_plus_lb_lines_luma * v->swath_width_y[k] * v->byte_per_pixel_dety[k] / (v->return_bw / v->dpp_per_plane[k]); - if (v->byte_per_pixel_detc[k] > 0.0) { - v->effective_det_plus_lb_lines_chroma =dcn_bw_floor2(v->lines_in_detc[k] +dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixel_detc[k] * v->pscl_throughput_chroma[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_c[k]); - v->urgent_latency_support_us_chroma = v->effective_det_plus_lb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0) - v->effective_det_plus_lb_lines_chroma * (v->swath_width_y[k] / 2.0) * v->byte_per_pixel_detc[k] / (v->return_bw / v->dpp_per_plane[k]); - v->urgent_latency_support_us[k] =dcn_bw_min2(v->urgent_latency_support_us_luma, v->urgent_latency_support_us_chroma); - } - else { + if (v->byte_per_pixel_detc[k] > 0.0f) { + v->effective_det_plus_lb_lines_chroma = dcn_bw_floor2(v->lines_in_detc[k] + dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixel_detc[k] * v->pscl_throughput_chroma[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_c[k]); + v->urgent_latency_support_us_chroma = v->effective_det_plus_lb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0f) - v->effective_det_plus_lb_lines_chroma * (v->swath_width_y[k] / 2.0f) * v->byte_per_pixel_detc[k] / (v->return_bw / v->dpp_per_plane[k]); + v->urgent_latency_support_us[k] = dcn_bw_min2(v->urgent_latency_support_us_luma, v->urgent_latency_support_us_chroma); + } else { v->urgent_latency_support_us[k] = v->urgent_latency_support_us_luma; } } - v->min_urgent_latency_support_us = 999999.0; + v->min_urgent_latency_support_us = 999999.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->min_urgent_latency_support_us =dcn_bw_min2(v->min_urgent_latency_support_us, v->urgent_latency_support_us[k]); + v->min_urgent_latency_support_us = dcn_bw_min2(v->min_urgent_latency_support_us, v->urgent_latency_support_us[k]); } /*non-urgent latency tolerance*/ @@ -1443,195 +1301,165 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan for (k = 0; k <= v->number_of_active_planes - 1; k++) { if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->block_height256_bytes_y = 1.0; + v->block_height256_bytes_y = 1.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { + v->block_height256_bytes_y = 4.0f; + } else { + v->block_height256_bytes_y = 8.0f; } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { - v->block_height256_bytes_y = 4.0; - } - else { - v->block_height256_bytes_y = 8.0; - } - v->block_height256_bytes_c = 0.0; - } - else { + v->block_height256_bytes_c = 0.0f; + } else { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->block_height256_bytes_y = 1.0; - v->block_height256_bytes_c = 1.0; - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { - v->block_height256_bytes_y = 16.0; - v->block_height256_bytes_c = 8.0; - } - else { - v->block_height256_bytes_y = 8.0; - v->block_height256_bytes_c = 8.0; + v->block_height256_bytes_y = 1.0f; + v->block_height256_bytes_c = 1.0f; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { + v->block_height256_bytes_y = 16.0f; + v->block_height256_bytes_c = 8.0f; + } else { + v->block_height256_bytes_y = 8.0f; + v->block_height256_bytes_c = 8.0f; } } if (v->dcc_enable[k] == dcn_bw_yes) { - v->meta_request_width_y = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (8.0 * v->block_height256_bytes_y); - v->meta_surf_width_y =dcn_bw_ceil2(v->swath_width_y[k] - 1.0, v->meta_request_width_y) + v->meta_request_width_y; - v->meta_surf_height_y =dcn_bw_ceil2(v->viewport_height[k] - 1.0, 8.0 * v->block_height256_bytes_y) + 8.0 * v->block_height256_bytes_y; + v->meta_request_width_y = 64.0f * 256.0f / dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / (8.0f * v->block_height256_bytes_y); + v->meta_surf_width_y = dcn_bw_ceil2(v->swath_width_y[k] - 1.0f, v->meta_request_width_y) + v->meta_request_width_y; + v->meta_surf_height_y = dcn_bw_ceil2(v->viewport_height[k] - 1.0f, 8.0f * v->block_height256_bytes_y) + 8.0f * v->block_height256_bytes_y; if (v->pte_enable == dcn_bw_yes) { - v->meta_pte_bytes_frame_y = (dcn_bw_ceil2((v->meta_surf_width_y * v->meta_surf_height_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0; - } - else { - v->meta_pte_bytes_frame_y = 0.0; + v->meta_pte_bytes_frame_y = (dcn_bw_ceil2((v->meta_surf_width_y * v->meta_surf_height_y * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / 256.0f - 4096.0f) / 8.0f / 4096.0f, 1.0f) + 1) * 64.0f; + } else { + v->meta_pte_bytes_frame_y = 0.0f; } if (v->source_scan[k] == dcn_bw_hor) { - v->meta_row_byte_y = v->meta_surf_width_y * 8.0 * v->block_height256_bytes_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0; + v->meta_row_byte_y = v->meta_surf_width_y * 8.0f * v->block_height256_bytes_y * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / 256.0f; + } else { + v->meta_row_byte_y = v->meta_surf_height_y * v->meta_request_width_y * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / 256.0f; } - else { - v->meta_row_byte_y = v->meta_surf_height_y * v->meta_request_width_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0; - } - } - else { - v->meta_pte_bytes_frame_y = 0.0; - v->meta_row_byte_y = 0.0; + } else { + v->meta_pte_bytes_frame_y = 0.0f; + v->meta_row_byte_y = 0.0f; } if (v->pte_enable == dcn_bw_yes) { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->macro_tile_size_byte_y = 256.0; - v->macro_tile_height_y = 1.0; + v->macro_tile_size_byte_y = 256.0f; + v->macro_tile_height_y = 1.0f; + } else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { + v->macro_tile_size_byte_y = 4096.0f; + v->macro_tile_height_y = 4.0f * v->block_height256_bytes_y; + } else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { + v->macro_tile_size_byte_y = 64.0f * 1024; + v->macro_tile_height_y = 16.0f * v->block_height256_bytes_y; + } else { + v->macro_tile_size_byte_y = 256.0f * 1024; + v->macro_tile_height_y = 32.0f * v->block_height256_bytes_y; } - else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { - v->macro_tile_size_byte_y = 4096.0; - v->macro_tile_height_y = 4.0 * v->block_height256_bytes_y; - } - else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { - v->macro_tile_size_byte_y = 64.0 * 1024; - v->macro_tile_height_y = 16.0 * v->block_height256_bytes_y; - } - else { - v->macro_tile_size_byte_y = 256.0 * 1024; - v->macro_tile_height_y = 32.0 * v->block_height256_bytes_y; - } - if (v->macro_tile_size_byte_y <= 65536.0) { + if (v->macro_tile_size_byte_y <= 65536.0f) { v->pixel_pte_req_height_y = v->macro_tile_height_y; + } else { + v->pixel_pte_req_height_y = 16.0f * v->block_height256_bytes_y; } - else { - v->pixel_pte_req_height_y = 16.0 * v->block_height256_bytes_y; - } - v->pixel_pte_req_width_y = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / v->pixel_pte_req_height_y * 8; + v->pixel_pte_req_width_y = 4096.0f / dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / v->pixel_pte_req_height_y * 8; if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] *dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_y / v->swath_width_y[k], 2.0), 1.0))) - 1.0) / v->pixel_pte_req_width_y, 1.0) + 1); + v->pixel_pte_bytes_per_row_y = 64.0f * (dcn_bw_ceil2((v->swath_width_y[k] * dcn_bw_min2(128.0f, dcn_bw_pow(2.0f, dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_y / v->swath_width_y[k], 2.0f), 1.0f))) - 1.0f) / v->pixel_pte_req_width_y, 1.0f) + 1); + } else if (v->source_scan[k] == dcn_bw_hor) { + v->pixel_pte_bytes_per_row_y = 64.0f * (dcn_bw_ceil2((v->swath_width_y[k] - 1.0f) / v->pixel_pte_req_width_y, 1.0f) + 1); + } else { + v->pixel_pte_bytes_per_row_y = 64.0f * (dcn_bw_ceil2((v->viewport_height[k] - 1.0f) / v->pixel_pte_req_height_y, 1.0f) + 1); } - else if (v->source_scan[k] == dcn_bw_hor) { - v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] - 1.0) / v->pixel_pte_req_width_y, 1.0) + 1); - } - else { - v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] - 1.0) / v->pixel_pte_req_height_y, 1.0) + 1); - } - } - else { - v->pixel_pte_bytes_per_row_y = 0.0; + } else { + v->pixel_pte_bytes_per_row_y = 0.0f; } if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) { if (v->dcc_enable[k] == dcn_bw_yes) { - v->meta_request_width_c = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (8.0 * v->block_height256_bytes_c); - v->meta_surf_width_c =dcn_bw_ceil2(v->swath_width_y[k] / 2.0 - 1.0, v->meta_request_width_c) + v->meta_request_width_c; - v->meta_surf_height_c =dcn_bw_ceil2(v->viewport_height[k] / 2.0 - 1.0, 8.0 * v->block_height256_bytes_c) + 8.0 * v->block_height256_bytes_c; + v->meta_request_width_c = 64.0f * 256.0f / dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / (8.0f * v->block_height256_bytes_c); + v->meta_surf_width_c = dcn_bw_ceil2(v->swath_width_y[k] / 2.0f - 1.0f, v->meta_request_width_c) + v->meta_request_width_c; + v->meta_surf_height_c = dcn_bw_ceil2(v->viewport_height[k] / 2.0f - 1.0f, 8.0f * v->block_height256_bytes_c) + 8.0f * v->block_height256_bytes_c; if (v->pte_enable == dcn_bw_yes) { - v->meta_pte_bytes_frame_c = (dcn_bw_ceil2((v->meta_surf_width_c * v->meta_surf_height_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0; - } - else { - v->meta_pte_bytes_frame_c = 0.0; + v->meta_pte_bytes_frame_c = (dcn_bw_ceil2((v->meta_surf_width_c * v->meta_surf_height_c * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / 256.0f - 4096.0f) / 8.0f / 4096.0f, 1.0f) + 1) * 64.0f; + } else { + v->meta_pte_bytes_frame_c = 0.0f; } if (v->source_scan[k] == dcn_bw_hor) { - v->meta_row_byte_c = v->meta_surf_width_c * 8.0 * v->block_height256_bytes_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0; + v->meta_row_byte_c = v->meta_surf_width_c * 8.0f * v->block_height256_bytes_c * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / 256.0f; + } else { + v->meta_row_byte_c = v->meta_surf_height_c * v->meta_request_width_c * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / 256.0f; } - else { - v->meta_row_byte_c = v->meta_surf_height_c * v->meta_request_width_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0; - } - } - else { - v->meta_pte_bytes_frame_c = 0.0; - v->meta_row_byte_c = 0.0; + } else { + v->meta_pte_bytes_frame_c = 0.0f; + v->meta_row_byte_c = 0.0f; } if (v->pte_enable == dcn_bw_yes) { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->macro_tile_size_bytes_c = 256.0; - v->macro_tile_height_c = 1.0; + v->macro_tile_size_bytes_c = 256.0f; + v->macro_tile_height_c = 1.0f; + } else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { + v->macro_tile_size_bytes_c = 4096.0f; + v->macro_tile_height_c = 4.0f * v->block_height256_bytes_c; + } else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { + v->macro_tile_size_bytes_c = 64.0f * 1024; + v->macro_tile_height_c = 16.0f * v->block_height256_bytes_c; + } else { + v->macro_tile_size_bytes_c = 256.0f * 1024; + v->macro_tile_height_c = 32.0f * v->block_height256_bytes_c; } - else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { - v->macro_tile_size_bytes_c = 4096.0; - v->macro_tile_height_c = 4.0 * v->block_height256_bytes_c; - } - else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { - v->macro_tile_size_bytes_c = 64.0 * 1024; - v->macro_tile_height_c = 16.0 * v->block_height256_bytes_c; - } - else { - v->macro_tile_size_bytes_c = 256.0 * 1024; - v->macro_tile_height_c = 32.0 * v->block_height256_bytes_c; - } - if (v->macro_tile_size_bytes_c <= 65536.0) { + if (v->macro_tile_size_bytes_c <= 65536.0f) { v->pixel_pte_req_height_c = v->macro_tile_height_c; + } else { + v->pixel_pte_req_height_c = 16.0f * v->block_height256_bytes_c; } - else { - v->pixel_pte_req_height_c = 16.0 * v->block_height256_bytes_c; - } - v->pixel_pte_req_width_c = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / v->pixel_pte_req_height_c * 8; + v->pixel_pte_req_width_c = 4096.0f / dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / v->pixel_pte_req_height_c * 8; if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0 * dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_c / (v->swath_width_y[k] / 2.0), 2.0), 1.0))) - 1.0) / v->pixel_pte_req_width_c, 1.0) + 1); - } - else if (v->source_scan[k] == dcn_bw_hor) { - v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0 - 1.0) / v->pixel_pte_req_width_c, 1.0) + 1); - } - else { - v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] / 2.0 - 1.0) / v->pixel_pte_req_height_c, 1.0) + 1); + v->pixel_pte_bytes_per_row_c = 64.0f * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0f * dcn_bw_min2(128.0f, dcn_bw_pow(2.0f, dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_c / (v->swath_width_y[k] / 2.0f), 2.0f), 1.0f))) - 1.0f) / v->pixel_pte_req_width_c, 1.0f) + 1); + } else if (v->source_scan[k] == dcn_bw_hor) { + v->pixel_pte_bytes_per_row_c = 64.0f * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0f - 1.0f) / v->pixel_pte_req_width_c, 1.0f) + 1); + } else { + v->pixel_pte_bytes_per_row_c = 64.0f * (dcn_bw_ceil2((v->viewport_height[k] / 2.0f - 1.0f) / v->pixel_pte_req_height_c, 1.0f) + 1); } + } else { + v->pixel_pte_bytes_per_row_c = 0.0f; } - else { - v->pixel_pte_bytes_per_row_c = 0.0; - } - } - else { - v->pixel_pte_bytes_per_row_c = 0.0; - v->meta_pte_bytes_frame_c = 0.0; - v->meta_row_byte_c = 0.0; + } else { + v->pixel_pte_bytes_per_row_c = 0.0f; + v->meta_pte_bytes_frame_c = 0.0f; + v->meta_row_byte_c = 0.0f; } v->pixel_pte_bytes_per_row[k] = v->pixel_pte_bytes_per_row_y + v->pixel_pte_bytes_per_row_c; v->meta_pte_bytes_frame[k] = v->meta_pte_bytes_frame_y + v->meta_pte_bytes_frame_c; v->meta_row_byte[k] = v->meta_row_byte_y + v->meta_row_byte_c; - v->v_init_pre_fill_y[k] =dcn_bw_floor2((v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0, 1.0); - v->max_num_swath_y[k] =dcn_bw_ceil2((v->v_init_pre_fill_y[k] - 1.0) / v->swath_height_y[k], 1.0) + 1; - if (v->v_init_pre_fill_y[k] > 1.0) { - v->max_partial_swath_y =dcn_bw_mod((v->v_init_pre_fill_y[k] - 2.0), v->swath_height_y[k]); + v->v_init_pre_fill_y[k] = dcn_bw_floor2((v->v_ratio[k] + v->vtaps[k] + 1.0f + v->interlace_output[k] * 0.5f * v->v_ratio[k]) / 2.0f, 1.0f); + v->max_num_swath_y[k] = dcn_bw_ceil2((v->v_init_pre_fill_y[k] - 1.0f) / v->swath_height_y[k], 1.0f) + 1; + if (v->v_init_pre_fill_y[k] > 1.0f) { + v->max_partial_swath_y = dcn_bw_mod((v->v_init_pre_fill_y[k] - 2.0f), v->swath_height_y[k]); + } else { + v->max_partial_swath_y = dcn_bw_mod((v->v_init_pre_fill_y[k] + v->swath_height_y[k] - 2.0f), v->swath_height_y[k]); } - else { - v->max_partial_swath_y =dcn_bw_mod((v->v_init_pre_fill_y[k] + v->swath_height_y[k] - 2.0), v->swath_height_y[k]); - } - v->max_partial_swath_y =dcn_bw_max2(1.0, v->max_partial_swath_y); + v->max_partial_swath_y = dcn_bw_max2(1.0f, v->max_partial_swath_y); v->prefetch_source_lines_y[k] = v->max_num_swath_y[k] * v->swath_height_y[k] + v->max_partial_swath_y; if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) { - v->v_init_pre_fill_c[k] =dcn_bw_floor2((v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k] / 2.0) / 2.0, 1.0); - v->max_num_swath_c[k] =dcn_bw_ceil2((v->v_init_pre_fill_c[k] - 1.0) / v->swath_height_c[k], 1.0) + 1; - if (v->v_init_pre_fill_c[k] > 1.0) { - v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] - 2.0), v->swath_height_c[k]); + v->v_init_pre_fill_c[k] = dcn_bw_floor2((v->v_ratio[k] / 2.0f + v->vtaps[k] + 1.0f + v->interlace_output[k] * 0.5f * v->v_ratio[k] / 2.0f) / 2.0f, 1.0f); + v->max_num_swath_c[k] = dcn_bw_ceil2((v->v_init_pre_fill_c[k] - 1.0f) / v->swath_height_c[k], 1.0f) + 1; + if (v->v_init_pre_fill_c[k] > 1.0f) { + v->max_partial_swath_c = dcn_bw_mod((v->v_init_pre_fill_c[k] - 2.0f), v->swath_height_c[k]); + } else { + v->max_partial_swath_c = dcn_bw_mod((v->v_init_pre_fill_c[k] + v->swath_height_c[k] - 2.0f), v->swath_height_c[k]); } - else { - v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] + v->swath_height_c[k] - 2.0), v->swath_height_c[k]); - } - v->max_partial_swath_c =dcn_bw_max2(1.0, v->max_partial_swath_c); - } - else { - v->max_num_swath_c[k] = 0.0; - v->max_partial_swath_c = 0.0; + v->max_partial_swath_c = dcn_bw_max2(1.0f, v->max_partial_swath_c); + } else { + v->max_num_swath_c[k] = 0.0f; + v->max_partial_swath_c = 0.0f; } v->prefetch_source_lines_c[k] = v->max_num_swath_c[k] * v->swath_height_c[k] + v->max_partial_swath_c; } - v->t_calc = 24.0 / v->dcf_clk_deep_sleep; + v->t_calc = 24.0f / v->dcf_clk_deep_sleep; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes) { - v->max_vstartup_lines[k] = v->vtotal[k] - v->vactive[k] - 1.0; - } - else { - v->max_vstartup_lines[k] = v->v_sync_plus_back_porch[k] - 1.0; + v->max_vstartup_lines[k] = v->vtotal[k] - v->vactive[k] - 1.0f; + } else { + v->max_vstartup_lines[k] = v->v_sync_plus_back_porch[k] - 1.0f; } } - v->next_prefetch_mode = 0.0; + v->next_prefetch_mode = 0.0f; do { - v->v_startup_lines = 13.0; + v->v_startup_lines = 13.0f; do { v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw = dcn_bw_yes; v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 = dcn_bw_no; @@ -1640,159 +1468,142 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan v->destination_line_times_for_prefetch_less_than2 = dcn_bw_no; v->prefetch_mode = v->next_prefetch_mode; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispclk; - if (v->dpp_per_plane[k] > 1.0) { - v->dstx_after_scaler = v->dstx_after_scaler + v->scaler_rec_out_width[k] / 2.0; + v->dstx_after_scaler = 90.0f * v->pixel_clock[k] / v->dppclk + 42.0f * v->pixel_clock[k] / v->dispclk; + if (v->dpp_per_plane[k] > 1.0f) { + v->dstx_after_scaler = v->dstx_after_scaler + v->scaler_rec_out_width[k] / 2.0f; } if (v->output_format[k] == dcn_bw_420) { - v->dsty_after_scaler = 1.0; + v->dsty_after_scaler = 1.0f; + } else { + v->dsty_after_scaler = 0.0f; } - else { - v->dsty_after_scaler = 0.0; - } - v->v_update_offset_pix[k] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0); - v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispclk); - v->v_update_width_pix[k] = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk + v->total_repeater_delay_time) * v->pixel_clock[k]; - v->v_ready_offset_pix[k] = dcn_bw_max2(150.0 / v->dppclk, v->total_repeater_delay_time + 20.0 / v->dcf_clk_deep_sleep + 10.0 / v->dppclk) * v->pixel_clock[k]; + v->v_update_offset_pix[k] = dcn_bw_ceil2(v->htotal[k] / 4.0f, 1.0f); + v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0f / v->dppclk + 3.0f / v->dispclk); + v->v_update_width_pix[k] = (14.0f / v->dcf_clk_deep_sleep + 12.0f / v->dppclk + v->total_repeater_delay_time) * v->pixel_clock[k]; + v->v_ready_offset_pix[k] = dcn_bw_max2(150.0f / v->dppclk, v->total_repeater_delay_time + 20.0f / v->dcf_clk_deep_sleep + 10.0f / v->dppclk) * v->pixel_clock[k]; v->t_setup = (v->v_update_offset_pix[k] + v->v_update_width_pix[k] + v->v_ready_offset_pix[k]) / v->pixel_clock[k]; - v->v_startup[k] =dcn_bw_min2(v->v_startup_lines, v->max_vstartup_lines[k]); - if (v->prefetch_mode == 0.0) { - v->t_wait =dcn_bw_max3(v->dram_clock_change_latency + v->urgent_latency, v->sr_enter_plus_exit_time, v->urgent_latency); - } - else if (v->prefetch_mode == 1.0) { - v->t_wait =dcn_bw_max2(v->sr_enter_plus_exit_time, v->urgent_latency); - } - else { + v->v_startup[k] = dcn_bw_min2(v->v_startup_lines, v->max_vstartup_lines[k]); + if (v->prefetch_mode == 0.0f) { + v->t_wait = dcn_bw_max3(v->dram_clock_change_latency + v->urgent_latency, v->sr_enter_plus_exit_time, v->urgent_latency); + } else if (v->prefetch_mode == 1.0f) { + v->t_wait = dcn_bw_max2(v->sr_enter_plus_exit_time, v->urgent_latency); + } else { v->t_wait = v->urgent_latency; } - v->destination_lines_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->v_startup[k] - v->t_wait / (v->htotal[k] / v->pixel_clock[k]) - (v->t_calc + v->t_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dsty_after_scaler + v->dstx_after_scaler / v->htotal[k]) + 0.125), 1.0) / 4; - if (v->destination_lines_for_prefetch[k] > 0.0) { - v->prefetch_bandwidth[k] = (v->meta_pte_bytes_frame[k] + 2.0 * v->meta_row_byte[k] + 2.0 * v->pixel_pte_bytes_per_row[k] + v->prefetch_source_lines_y[k] * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) + v->prefetch_source_lines_c[k] * v->swath_width_y[k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)) / (v->destination_lines_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]); - } - else { - v->prefetch_bandwidth[k] = 999999.0; + v->destination_lines_for_prefetch[k] = dcn_bw_floor2(4.0f * (v->v_startup[k] - v->t_wait / (v->htotal[k] / v->pixel_clock[k]) - (v->t_calc + v->t_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dsty_after_scaler + v->dstx_after_scaler / v->htotal[k]) + 0.125f), 1.0f) / 4; + if (v->destination_lines_for_prefetch[k] > 0.0f) { + v->prefetch_bandwidth[k] = (v->meta_pte_bytes_frame[k] + 2.0f * v->meta_row_byte[k] + 2.0f * v->pixel_pte_bytes_per_row[k] + v->prefetch_source_lines_y[k] * v->swath_width_y[k] * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) + v->prefetch_source_lines_c[k] * v->swath_width_y[k] / 2.0f * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f)) / (v->destination_lines_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]); + } else { + v->prefetch_bandwidth[k] = 999999.0f; } } v->bandwidth_available_for_immediate_flip = v->return_bw; for (k = 0; k <= v->number_of_active_planes - 1; k++) { v->bandwidth_available_for_immediate_flip = v->bandwidth_available_for_immediate_flip -dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->prefetch_bandwidth[k]); } - v->tot_immediate_flip_bytes = 0.0; + v->tot_immediate_flip_bytes = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { v->tot_immediate_flip_bytes = v->tot_immediate_flip_bytes + v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]; } } - v->max_rd_bandwidth = 0.0; + v->max_rd_bandwidth = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) { if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { - v->time_for_fetching_meta_pte =dcn_bw_max5(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->meta_pte_bytes_frame[k] * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0); - } - else { - v->time_for_fetching_meta_pte =dcn_bw_max3(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] / 4.0); + v->time_for_fetching_meta_pte = dcn_bw_max5(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->meta_pte_bytes_frame[k] * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0f); + } else { + v->time_for_fetching_meta_pte = dcn_bw_max3(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] / 4.0f); } + } else { + v->time_for_fetching_meta_pte = v->htotal[k] / v->pixel_clock[k] / 4.0f; } - else { - v->time_for_fetching_meta_pte = v->htotal[k] / v->pixel_clock[k] / 4.0; - } - v->destination_lines_to_request_vm_inv_blank[k] =dcn_bw_floor2(4.0 * (v->time_for_fetching_meta_pte / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; + v->destination_lines_to_request_vm_inv_blank[k] = dcn_bw_floor2(4.0f * (v->time_for_fetching_meta_pte / (v->htotal[k] / v->pixel_clock[k]) + 0.125f), 1.0f) / 4; if ((v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes)) { if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { - v->time_for_fetching_row_in_vblank =dcn_bw_max5((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, 2.0 * v->urgent_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte); - } - else { - v->time_for_fetching_row_in_vblank =dcn_bw_max3((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte); + v->time_for_fetching_row_in_vblank = dcn_bw_max5((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, 2.0f * v->urgent_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte); + } else { + v->time_for_fetching_row_in_vblank = dcn_bw_max3((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte); } + } else { + v->time_for_fetching_row_in_vblank = dcn_bw_max2(v->urgent_extra_latency - v->time_for_fetching_meta_pte, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte); } - else { - v->time_for_fetching_row_in_vblank =dcn_bw_max2(v->urgent_extra_latency - v->time_for_fetching_meta_pte, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte); - } - v->destination_lines_to_request_row_in_vblank[k] =dcn_bw_floor2(4.0 * (v->time_for_fetching_row_in_vblank / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; + v->destination_lines_to_request_row_in_vblank[k] = dcn_bw_floor2(4.0f * (v->time_for_fetching_row_in_vblank / (v->htotal[k] / v->pixel_clock[k]) + 0.125f), 1.0f) / 4; v->lines_to_request_prefetch_pixel_data = v->destination_lines_for_prefetch[k] - v->destination_lines_to_request_vm_inv_blank[k] - v->destination_lines_to_request_row_in_vblank[k]; - if (v->lines_to_request_prefetch_pixel_data > 0.0) { + if (v->lines_to_request_prefetch_pixel_data > 0.0f) { v->v_ratio_prefetch_y[k] = v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data; - if ((v->swath_height_y[k] > 4.0)) { - if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_y[k] - 3.0) / 2.0) { - v->v_ratio_prefetch_y[k] =dcn_bw_max2(v->v_ratio_prefetch_y[k], v->max_num_swath_y[k] * v->swath_height_y[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_y[k] - 3.0) / 2.0)); - } - else { - v->v_ratio_prefetch_y[k] = 999999.0; + if ((v->swath_height_y[k] > 4.0f)) { + if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_y[k] - 3.0f) / 2.0f) { + v->v_ratio_prefetch_y[k] = dcn_bw_max2(v->v_ratio_prefetch_y[k], v->max_num_swath_y[k] * v->swath_height_y[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_y[k] - 3.0f) / 2.0f)); + } else { + v->v_ratio_prefetch_y[k] = 999999.0f; } } + } else { + v->v_ratio_prefetch_y[k] = 999999.0f; } - else { - v->v_ratio_prefetch_y[k] = 999999.0; - } - v->v_ratio_prefetch_y[k] =dcn_bw_max2(v->v_ratio_prefetch_y[k], 1.0); - if (v->lines_to_request_prefetch_pixel_data > 0.0) { + v->v_ratio_prefetch_y[k] = dcn_bw_max2(v->v_ratio_prefetch_y[k], 1.0f); + if (v->lines_to_request_prefetch_pixel_data > 0.0f) { v->v_ratio_prefetch_c[k] = v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data; - if ((v->swath_height_c[k] > 4.0)) { - if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_c[k] - 3.0) / 2.0) { - v->v_ratio_prefetch_c[k] =dcn_bw_max2(v->v_ratio_prefetch_c[k], v->max_num_swath_c[k] * v->swath_height_c[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_c[k] - 3.0) / 2.0)); - } - else { - v->v_ratio_prefetch_c[k] = 999999.0; + if ((v->swath_height_c[k] > 4.0f)) { + if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_c[k] - 3.0f) / 2.0f) { + v->v_ratio_prefetch_c[k] = dcn_bw_max2(v->v_ratio_prefetch_c[k], v->max_num_swath_c[k] * v->swath_height_c[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_c[k] - 3.0f) / 2.0f)); + } else { + v->v_ratio_prefetch_c[k] = 999999.0f; } } + } else { + v->v_ratio_prefetch_c[k] = 999999.0f; } - else { - v->v_ratio_prefetch_c[k] = 999999.0; + v->v_ratio_prefetch_c[k] = dcn_bw_max2(v->v_ratio_prefetch_c[k], 1.0f); + if (v->lines_to_request_prefetch_pixel_data > 0.0f) { + v->required_prefetch_pix_data_bw = v->dpp_per_plane[k] * (v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) + v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / 2.0f) * v->swath_width_y[k] / (v->htotal[k] / v->pixel_clock[k]); + } else { + v->required_prefetch_pix_data_bw = 999999.0f; } - v->v_ratio_prefetch_c[k] =dcn_bw_max2(v->v_ratio_prefetch_c[k], 1.0); - if (v->lines_to_request_prefetch_pixel_data > 0.0) { - v->required_prefetch_pix_data_bw = v->dpp_per_plane[k] * (v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) + v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 2.0) * v->swath_width_y[k] / (v->htotal[k] / v->pixel_clock[k]); - } - else { - v->required_prefetch_pix_data_bw = 999999.0; - } - v->max_rd_bandwidth = v->max_rd_bandwidth +dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->required_prefetch_pix_data_bw); + v->max_rd_bandwidth = v->max_rd_bandwidth + dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->required_prefetch_pix_data_bw); if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { - v->max_rd_bandwidth = v->max_rd_bandwidth +dcn_bw_max2(v->meta_pte_bytes_frame[k] / (v->destination_lines_to_request_vm_inv_blank[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / (v->destination_lines_to_request_row_in_vblank[k] * v->htotal[k] / v->pixel_clock[k])); + v->max_rd_bandwidth = v->max_rd_bandwidth + dcn_bw_max2(v->meta_pte_bytes_frame[k] / (v->destination_lines_to_request_vm_inv_blank[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / (v->destination_lines_to_request_row_in_vblank[k] * v->htotal[k] / v->pixel_clock[k])); } - if (v->v_ratio_prefetch_y[k] > 4.0 || v->v_ratio_prefetch_c[k] > 4.0) { + if (v->v_ratio_prefetch_y[k] > 4.0f || v->v_ratio_prefetch_c[k] > 4.0f) { v->v_ratio_prefetch_more_than4 = dcn_bw_yes; } - if (v->destination_lines_for_prefetch[k] < 2.0) { + if (v->destination_lines_for_prefetch[k] < 2.0f) { v->destination_line_times_for_prefetch_less_than2 = dcn_bw_yes; } if (v->max_vstartup_lines[k] > v->v_startup_lines) { if (v->required_prefetch_pix_data_bw > (v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k])) { v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw = dcn_bw_no; } - if (v->v_ratio_prefetch_y[k] > 4.0 || v->v_ratio_prefetch_c[k] > 4.0) { + if (v->v_ratio_prefetch_y[k] > 4.0f || v->v_ratio_prefetch_c[k] > 4.0f) { v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 = dcn_bw_yes; } - if (v->destination_lines_for_prefetch[k] < 2.0) { + if (v->destination_lines_for_prefetch[k] < 2.0f) { v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 = dcn_bw_yes; } } } if (v->max_rd_bandwidth <= v->return_bw && v->v_ratio_prefetch_more_than4 == dcn_bw_no && v->destination_line_times_for_prefetch_less_than2 == dcn_bw_no) { v->prefetch_mode_supported = dcn_bw_yes; - } - else { + } else { v->prefetch_mode_supported = dcn_bw_no; } - v->v_startup_lines = v->v_startup_lines + 1.0; + v->v_startup_lines = v->v_startup_lines + 1.0f; } while (!(v->prefetch_mode_supported == dcn_bw_yes || (v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw == dcn_bw_yes && v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 == dcn_bw_no && v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 == dcn_bw_no))); - v->next_prefetch_mode = v->next_prefetch_mode + 1.0; - } while (!(v->prefetch_mode_supported == dcn_bw_yes || v->prefetch_mode == 2.0)); + v->next_prefetch_mode = v->next_prefetch_mode + 1.0f; + } while (!(v->prefetch_mode_supported == dcn_bw_yes || v->prefetch_mode == 2.0f)); for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->v_ratio_prefetch_y[k] <= 1.0) { + if (v->v_ratio_prefetch_y[k] <= 1.0f) { v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k]; - } - else { + } else { v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; } - if (v->byte_per_pixel_detc[k] == 0.0) { - v->display_pipe_line_delivery_time_chroma_prefetch[k] = 0.0; - } - else { - if (v->v_ratio_prefetch_c[k] <= 1.0) { + if (v->byte_per_pixel_detc[k] == 0.0f) { + v->display_pipe_line_delivery_time_chroma_prefetch[k] = 0.0f; + } else { + if (v->v_ratio_prefetch_c[k] <= 1.0f) { v->display_pipe_line_delivery_time_chroma_prefetch[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k]; - } - else { + } else { v->display_pipe_line_delivery_time_chroma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; } } @@ -1800,17 +1611,15 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan /*min ttuv_blank*/ for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->prefetch_mode == 0.0) { + if (v->prefetch_mode == 0.0f) { v->allow_dram_clock_change_during_vblank[k] = dcn_bw_yes; v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes; - v->min_ttuv_blank[k] = v->t_calc +dcn_bw_max3(v->dram_clock_change_watermark, v->stutter_enter_plus_exit_watermark, v->urgent_watermark); - } - else if (v->prefetch_mode == 1.0) { + v->min_ttuv_blank[k] = v->t_calc + dcn_bw_max3(v->dram_clock_change_watermark, v->stutter_enter_plus_exit_watermark, v->urgent_watermark); + } else if (v->prefetch_mode == 1.0f) { v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no; v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes; - v->min_ttuv_blank[k] = v->t_calc +dcn_bw_max2(v->stutter_enter_plus_exit_watermark, v->urgent_watermark); - } - else { + v->min_ttuv_blank[k] = v->t_calc + dcn_bw_max2(v->stutter_enter_plus_exit_watermark, v->urgent_watermark); + } else { v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no; v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_no; v->min_ttuv_blank[k] = v->t_calc + v->urgent_watermark; @@ -1818,115 +1627,102 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan } /*nb p-state/dram clock change support*/ - v->active_dp_ps = 0.0; + v->active_dp_ps = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { v->active_dp_ps = v->active_dp_ps + v->dpp_per_plane[k]; } for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->lb_latency_hiding_source_lines_y =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0); - v->lb_latency_hiding_source_lines_c =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0)), 1.0)) - (v->vta_pschroma[k] - 1.0); + v->lb_latency_hiding_source_lines_y = dcn_bw_min2(v->max_line_buffer_lines, dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] / dcn_bw_max2(v->h_ratio[k], 1.0f)), 1.0f)) - (v->vtaps[k] - 1.0f); + v->lb_latency_hiding_source_lines_c = dcn_bw_min2(v->max_line_buffer_lines, dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] / 2.0f / dcn_bw_max2(v->h_ratio[k] / 2.0f, 1.0f)), 1.0f)) - (v->vta_pschroma[k] - 1.0f); v->effective_lb_latency_hiding_y = v->lb_latency_hiding_source_lines_y / v->v_ratio[k] * (v->htotal[k] / v->pixel_clock[k]); - v->effective_lb_latency_hiding_c = v->lb_latency_hiding_source_lines_c / (v->v_ratio[k] / 2.0) * (v->htotal[k] / v->pixel_clock[k]); - if (v->swath_width_y[k] > 2.0 * v->dpp_output_buffer_pixels) { + v->effective_lb_latency_hiding_c = v->lb_latency_hiding_source_lines_c / (v->v_ratio[k] / 2.0f) * (v->htotal[k] / v->pixel_clock[k]); + if (v->swath_width_y[k] > 2.0f * v->dpp_output_buffer_pixels) { v->dpp_output_buffer_lines_y = v->dpp_output_buffer_pixels / v->swath_width_y[k]; + } else if (v->swath_width_y[k] > v->dpp_output_buffer_pixels) { + v->dpp_output_buffer_lines_y = 0.5f; + } else { + v->dpp_output_buffer_lines_y = 1.0f; } - else if (v->swath_width_y[k] > v->dpp_output_buffer_pixels) { - v->dpp_output_buffer_lines_y = 0.5; - } - else { - v->dpp_output_buffer_lines_y = 1.0; - } - if (v->swath_width_y[k] / 2.0 > 2.0 * v->dpp_output_buffer_pixels) { - v->dpp_output_buffer_lines_c = v->dpp_output_buffer_pixels / (v->swath_width_y[k] / 2.0); - } - else if (v->swath_width_y[k] / 2.0 > v->dpp_output_buffer_pixels) { - v->dpp_output_buffer_lines_c = 0.5; - } - else { - v->dpp_output_buffer_lines_c = 1.0; + if (v->swath_width_y[k] / 2.0f > 2.0f * v->dpp_output_buffer_pixels) { + v->dpp_output_buffer_lines_c = v->dpp_output_buffer_pixels / (v->swath_width_y[k] / 2.0f); + } else if (v->swath_width_y[k] / 2.0f > v->dpp_output_buffer_pixels) { + v->dpp_output_buffer_lines_c = 0.5f; + } else { + v->dpp_output_buffer_lines_c = 1.0f; } v->dppopp_buffering_y = (v->htotal[k] / v->pixel_clock[k]) * (v->dpp_output_buffer_lines_y + v->opp_output_buffer_lines); v->max_det_buffering_time_y = v->full_det_buffering_time_y[k] + (v->lines_in_dety[k] - v->lines_in_dety_rounded_down_to_swath[k]) / v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]); v->active_dram_clock_change_latency_margin_y = v->dppopp_buffering_y + v->effective_lb_latency_hiding_y + v->max_det_buffering_time_y - v->dram_clock_change_watermark; - if (v->active_dp_ps > 1.0) { - v->active_dram_clock_change_latency_margin_y = v->active_dram_clock_change_latency_margin_y - (1.0 - 1.0 / (v->active_dp_ps - 1.0)) * v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]); + if (v->active_dp_ps > 1.0f) { + v->active_dram_clock_change_latency_margin_y = v->active_dram_clock_change_latency_margin_y - (1.0f - 1.0f / (v->active_dp_ps - 1.0f)) * v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]); } - if (v->byte_per_pixel_detc[k] > 0.0) { + if (v->byte_per_pixel_detc[k] > 0.0f) { v->dppopp_buffering_c = (v->htotal[k] / v->pixel_clock[k]) * (v->dpp_output_buffer_lines_c + v->opp_output_buffer_lines); v->max_det_buffering_time_c = v->full_det_buffering_time_c[k] + (v->lines_in_detc[k] - v->lines_in_detc_rounded_down_to_swath[k]) / v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]); v->active_dram_clock_change_latency_margin_c = v->dppopp_buffering_c + v->effective_lb_latency_hiding_c + v->max_det_buffering_time_c - v->dram_clock_change_watermark; - if (v->active_dp_ps > 1.0) { - v->active_dram_clock_change_latency_margin_c = v->active_dram_clock_change_latency_margin_c - (1.0 - 1.0 / (v->active_dp_ps - 1.0)) * v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]); + if (v->active_dp_ps > 1.0f) { + v->active_dram_clock_change_latency_margin_c = v->active_dram_clock_change_latency_margin_c - (1.0f - 1.0f / (v->active_dp_ps - 1.0f)) * v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]); } - v->active_dram_clock_change_latency_margin[k] =dcn_bw_min2(v->active_dram_clock_change_latency_margin_y, v->active_dram_clock_change_latency_margin_c); - } - else { + v->active_dram_clock_change_latency_margin[k] = dcn_bw_min2(v->active_dram_clock_change_latency_margin_y, v->active_dram_clock_change_latency_margin_c); + } else { v->active_dram_clock_change_latency_margin[k] = v->active_dram_clock_change_latency_margin_y; } if (v->output_format[k] == dcn_bw_444) { - v->writeback_dram_clock_change_latency_margin = (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0) - v->writeback_dram_clock_change_watermark; - } - else { - v->writeback_dram_clock_change_latency_margin =dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k])) - v->writeback_dram_clock_change_watermark; + v->writeback_dram_clock_change_latency_margin = (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0f / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0f) - v->writeback_dram_clock_change_watermark; + } else { + v->writeback_dram_clock_change_latency_margin = dcn_bw_min2(v->writeback_luma_buffer_size, 2.0f * v->writeback_chroma_buffer_size) * 1024.0f / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k])) - v->writeback_dram_clock_change_watermark; } if (v->output[k] == dcn_bw_writeback) { - v->active_dram_clock_change_latency_margin[k] =dcn_bw_min2(v->active_dram_clock_change_latency_margin[k], v->writeback_dram_clock_change_latency_margin); + v->active_dram_clock_change_latency_margin[k] = dcn_bw_min2(v->active_dram_clock_change_latency_margin[k], v->writeback_dram_clock_change_latency_margin); } } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->allow_dram_clock_change_during_vblank[k] == dcn_bw_yes) { v->v_blank_dram_clock_change_latency_margin[k] = (v->vtotal[k] - v->scaler_recout_height[k]) * (v->htotal[k] / v->pixel_clock[k]) -dcn_bw_max2(v->dram_clock_change_watermark, v->writeback_dram_clock_change_watermark); - } - else { - v->v_blank_dram_clock_change_latency_margin[k] = 0.0; + } else { + v->v_blank_dram_clock_change_latency_margin[k] = 0.0f; } } - v->min_active_dram_clock_change_margin = 999999.0; - v->v_blank_of_min_active_dram_clock_change_margin = 999999.0; - v->second_min_active_dram_clock_change_margin = 999999.0; + v->min_active_dram_clock_change_margin = 999999.0f; + v->v_blank_of_min_active_dram_clock_change_margin = 999999.0f; + v->second_min_active_dram_clock_change_margin = 999999.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->active_dram_clock_change_latency_margin[k] < v->min_active_dram_clock_change_margin) { v->second_min_active_dram_clock_change_margin = v->min_active_dram_clock_change_margin; v->min_active_dram_clock_change_margin = v->active_dram_clock_change_latency_margin[k]; v->v_blank_of_min_active_dram_clock_change_margin = v->v_blank_dram_clock_change_latency_margin[k]; - } - else if (v->active_dram_clock_change_latency_margin[k] < v->second_min_active_dram_clock_change_margin) { + } else if (v->active_dram_clock_change_latency_margin[k] < v->second_min_active_dram_clock_change_margin) { v->second_min_active_dram_clock_change_margin = v->active_dram_clock_change_latency_margin[k]; } } - v->min_vblank_dram_clock_change_margin = 999999.0; + v->min_vblank_dram_clock_change_margin = 999999.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->min_vblank_dram_clock_change_margin > v->v_blank_dram_clock_change_latency_margin[k]) { v->min_vblank_dram_clock_change_margin = v->v_blank_dram_clock_change_latency_margin[k]; } } if (v->synchronized_vblank == dcn_bw_yes || v->number_of_active_planes == 1) { - v->dram_clock_change_margin =dcn_bw_max2(v->min_active_dram_clock_change_margin, v->min_vblank_dram_clock_change_margin); - } - else if (v->v_blank_of_min_active_dram_clock_change_margin > v->min_active_dram_clock_change_margin) { - v->dram_clock_change_margin =dcn_bw_min2(v->second_min_active_dram_clock_change_margin, v->v_blank_of_min_active_dram_clock_change_margin); - } - else { + v->dram_clock_change_margin = dcn_bw_max2(v->min_active_dram_clock_change_margin, v->min_vblank_dram_clock_change_margin); + } else if (v->v_blank_of_min_active_dram_clock_change_margin > v->min_active_dram_clock_change_margin) { + v->dram_clock_change_margin = dcn_bw_min2(v->second_min_active_dram_clock_change_margin, v->v_blank_of_min_active_dram_clock_change_margin); + } else { v->dram_clock_change_margin = v->min_active_dram_clock_change_margin; } - if (v->min_active_dram_clock_change_margin > 0.0) { + if (v->min_active_dram_clock_change_margin > 0.0f) { v->dram_clock_change_support = dcn_bw_supported_in_v_active; - } - else if (v->dram_clock_change_margin > 0.0) { + } else if (v->dram_clock_change_margin > 0.0f) { v->dram_clock_change_support = dcn_bw_supported_in_v_blank; - } - else { + } else { v->dram_clock_change_support = dcn_bw_not_supported; } /*maximum bandwidth used*/ - v->wr_bandwidth = 0.0; + v->wr_bandwidth = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) { - v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0; - } - else if (v->output[k] == dcn_bw_writeback) { - v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5; + v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0f; + } else if (v->output[k] == dcn_bw_writeback) { + v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5f; } } v->max_used_bw = v->max_rd_bandwidth + v->wr_bandwidth; diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_math.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_math.c index cac72413a097..16b990147d1d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_math.c +++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_math.c @@ -76,12 +76,12 @@ float dcn_bw_floor2(const float arg, const float significance) } float dcn_bw_floor(const float arg) { - return ((int) (arg)); + return (float)((int)(arg)); } float dcn_bw_ceil(const float arg) { - return (int) (arg + 0.99999); + return (float)((int)(arg + 0.99999f)); } float dcn_bw_ceil2(const float arg, const float significance) @@ -107,7 +107,7 @@ float dcn_bw_pow(float a, float exp) /*ASSERT(exp == (int)exp);*/ if ((int)exp == 0) return 1; - temp = dcn_bw_pow(a, (int)(exp / 2)); + temp = dcn_bw_pow(a, (float)((int)(exp / 2))); if (((int)exp % 2) == 0) { return temp * temp; } else { diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c index 61553e24d53e..dcca23d53261 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c @@ -72,21 +72,21 @@ const struct dcn_soc_bounding_box dcn10_soc_defaults = { * Use these value if fused value doesn't make sense as earlier * part don't have correct value fused */ /* default DCF CLK DPM on RV*/ - .dcfclkv_max0p9 = 655, /* MHz, = 3600/5.5 */ - .dcfclkv_nom0p8 = 626, /* MHz, = 3600/5.75 */ + .dcfclkv_max0p9 = 655, /* MHz, = 3600/5.5f */ + .dcfclkv_nom0p8 = 626, /* MHz, = 3600/5.75f */ .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */ .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */ /* default DISP CLK voltage state on RV */ - .max_dispclk_vmax0p9 = 1108, /* MHz, = 3600/3.25 */ - .max_dispclk_vnom0p8 = 1029, /* MHz, = 3600/3.5 */ - .max_dispclk_vmid0p72 = 960, /* MHz, = 3600/3.75 */ - .max_dispclk_vmin0p65 = 626, /* MHz, = 3600/5.75 */ + .max_dispclk_vmax0p9 = 1108, /* MHz, = 3600/3.25f */ + .max_dispclk_vnom0p8 = 1029, /* MHz, = 3600/3.5f */ + .max_dispclk_vmid0p72 = 960, /* MHz, = 3600/3.75f */ + .max_dispclk_vmin0p65 = 626, /* MHz, = 3600/5.75f */ /* default DPP CLK voltage state on RV */ .max_dppclk_vmax0p9 = 720, /* MHz, = 3600/5 */ - .max_dppclk_vnom0p8 = 686, /* MHz, = 3600/5.25 */ - .max_dppclk_vmid0p72 = 626, /* MHz, = 3600/5.75 */ + .max_dppclk_vnom0p8 = 686, /* MHz, = 3600/5.25f */ + .max_dppclk_vmid0p72 = 626, /* MHz, = 3600/5.75f */ .max_dppclk_vmin0p65 = 400, /* MHz, = 3600/9 */ /* default PHY CLK voltage state on RV */ @@ -326,7 +326,7 @@ static void pipe_ctx_to_e2e_pipe_params ( * allow us to disable dcc on the fly without re-calculating WM * * extra overhead for DCC is quite small. for 1080p WM without - * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us) + * DCC is only 0.417fus lower (urgent goes from 6.979fus to 6.562fus) */ unsigned int bpe; @@ -396,18 +396,18 @@ static void pipe_ctx_to_e2e_pipe_params ( } input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; - input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; - input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; - input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; - if (input->scale_ratio_depth.vinit < 1.0) + input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0f; + input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0f; + input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0f; + if (input->scale_ratio_depth.vinit < 1.0f) input->scale_ratio_depth.vinit = 1; input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c; input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c; - input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0; - input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0; - input->scale_ratio_depth.vinit_c = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0; - if (input->scale_ratio_depth.vinit_c < 1.0) + input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0f; + input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0f; + input->scale_ratio_depth.vinit_c = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0f; + if (input->scale_ratio_depth.vinit_c < 1.0f) input->scale_ratio_depth.vinit_c = 1; switch (pipe->plane_res.scl_data.lb_params.depth) { case LB_PIXEL_DEPTH_30BPP: @@ -441,7 +441,7 @@ static void pipe_ctx_to_e2e_pipe_params ( - pipe->stream->timing.v_addressable - pipe->stream->timing.v_border_bottom - pipe->stream->timing.v_border_top; - input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0; + input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0f; input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start; input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; @@ -477,10 +477,10 @@ static void dcn_bw_calc_rq_dlg_ttu( for (i = 0; i < number_of_planes; i++) { total_active_bw += v->read_bandwidth[i]; total_prefetch_bw += v->prefetch_bandwidth[i]; - total_flip_bytes += v->total_immediate_flip_bytes[i]; + total_flip_bytes += (int)v->total_immediate_flip_bytes[i]; } dlg_sys_param->total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw); - if (dlg_sys_param->total_flip_bw < 0.0) + if (dlg_sys_param->total_flip_bw < 0.0f) dlg_sys_param->total_flip_bw = 0; dlg_sys_param->t_mclk_wm_us = v->dram_clock_change_watermark; @@ -494,7 +494,7 @@ static void dcn_bw_calc_rq_dlg_ttu( input->clks_cfg.dcfclk_mhz = v->dcfclk; input->clks_cfg.dispclk_mhz = v->dispclk; input->clks_cfg.dppclk_mhz = v->dppclk; - input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; + input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0f; input->clks_cfg.socclk_mhz = v->socclk; input->clks_cfg.voltage = v->voltage_level; // dc->dml.logger = pool->base.logger; @@ -533,13 +533,14 @@ static void split_stream_across_pipes( *secondary_pipe = *primary_pipe; - secondary_pipe->pipe_idx = pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)pipe_idx; secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; - secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; + secondary_pipe->plane_res.mpcc_inst = + (uint8_t)pool->dpps[secondary_pipe->pipe_idx]->inst; if (primary_pipe->bottom_pipe) { ASSERT(primary_pipe->bottom_pipe != secondary_pipe); secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; @@ -643,7 +644,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc) if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns && dc->debug.sr_exit_time_ns) { updated = true; - dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0; + dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0f; } if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000) @@ -651,13 +652,13 @@ static bool dcn_bw_apply_registry_override(struct dc *dc) && dc->debug.sr_enter_plus_exit_time_ns) { updated = true; dc->dcn_soc->sr_enter_plus_exit_time = - dc->debug.sr_enter_plus_exit_time_ns / 1000.0; + dc->debug.sr_enter_plus_exit_time_ns / 1000.0f; } if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns && dc->debug.urgent_latency_ns) { updated = true; - dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0; + dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0f; } if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000) @@ -665,7 +666,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc) && dc->debug.percent_of_ideal_drambw) { updated = true; dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency = - dc->debug.percent_of_ideal_drambw; + (float)dc->debug.percent_of_ideal_drambw; } if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000) @@ -673,7 +674,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc) && dc->debug.dram_clock_change_latency_ns) { updated = true; dc->dcn_soc->dram_clock_change_latency = - dc->debug.dram_clock_change_latency_ns / 1000.0; + dc->debug.dram_clock_change_latency_ns / 1000.0f; } return updated; @@ -691,7 +692,7 @@ static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v) static void hack_force_pipe_split(struct dcn_bw_internal_vars *v, unsigned int pixel_rate_100hz) { - float pixel_rate_mhz = pixel_rate_100hz / 10000.0; + float pixel_rate_mhz = pixel_rate_100hz / 10000.0f; /* * force enabling pipe split by lower dpp clock for DPM0 to just @@ -759,7 +760,8 @@ bool dcn_validate_bandwidth( const struct resource_pool *pool = dc->res_pool; struct dcn_bw_internal_vars *v = &context->dcn_bw_vars; - int i, input_idx, k; + unsigned int i; + int input_idx, k; int vesa_sync_start, asic_blank_end, asic_blank_start; bool bw_limit_pass; float bw_limit; @@ -808,12 +810,12 @@ bool dcn_validate_bandwidth( v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9; v->downspreading = dc->dcn_soc->downspreading; - v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles; - v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel; - v->number_of_channels = dc->dcn_soc->number_of_channels; - v->vmm_page_size = dc->dcn_soc->vmm_page_size; + v->round_trip_ping_latency_cycles = (float)dc->dcn_soc->round_trip_ping_latency_cycles; + v->urgent_out_of_order_return_per_channel = (float)dc->dcn_soc->urgent_out_of_order_return_per_channel; + v->number_of_channels = (float)dc->dcn_soc->number_of_channels; + v->vmm_page_size = (float)dc->dcn_soc->vmm_page_size; v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency; - v->return_bus_width = dc->dcn_soc->return_bus_width; + v->return_bus_width = (float)dc->dcn_soc->return_bus_width; v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte; v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte; @@ -821,31 +823,31 @@ bool dcn_validate_bandwidth( v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines; v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte; v->pte_enable = dc->dcn_ip->pte_enable; - v->pte_chunk_size = dc->dcn_ip->pte_chunk_size; - v->meta_chunk_size = dc->dcn_ip->meta_chunk_size; - v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size; + v->pte_chunk_size = (float)dc->dcn_ip->pte_chunk_size; + v->meta_chunk_size = (float)dc->dcn_ip->meta_chunk_size; + v->writeback_chunk_size = (float)dc->dcn_ip->writeback_chunk_size; v->odm_capability = dc->dcn_ip->odm_capability; v->dsc_capability = dc->dcn_ip->dsc_capability; - v->line_buffer_size = dc->dcn_ip->line_buffer_size; + v->line_buffer_size = (float)dc->dcn_ip->line_buffer_size; v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed; - v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp; - v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines; - v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size; - v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size; - v->max_num_dpp = dc->dcn_ip->max_num_dpp; - v->max_num_writeback = dc->dcn_ip->max_num_writeback; - v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput; - v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput; - v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput; - v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput; + v->line_buffer_fixed_bpp = (float)dc->dcn_ip->line_buffer_fixed_bpp; + v->max_line_buffer_lines = (float)dc->dcn_ip->max_line_buffer_lines; + v->writeback_luma_buffer_size = (float)dc->dcn_ip->writeback_luma_buffer_size; + v->writeback_chroma_buffer_size = (float)dc->dcn_ip->writeback_chroma_buffer_size; + v->max_num_dpp = (float)dc->dcn_ip->max_num_dpp; + v->max_num_writeback = (float)dc->dcn_ip->max_num_writeback; + v->max_dchub_topscl_throughput = (float)dc->dcn_ip->max_dchub_topscl_throughput; + v->max_pscl_tolb_throughput = (float)dc->dcn_ip->max_pscl_tolb_throughput; + v->max_lb_tovscl_throughput = (float)dc->dcn_ip->max_lb_tovscl_throughput; + v->max_vscl_tohscl_throughput = (float)dc->dcn_ip->max_vscl_tohscl_throughput; v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio; v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio; - v->max_hscl_taps = dc->dcn_ip->max_hscl_taps; - v->max_vscl_taps = dc->dcn_ip->max_vscl_taps; + v->max_hscl_taps = (float)dc->dcn_ip->max_hscl_taps; + v->max_vscl_taps = (float)dc->dcn_ip->max_vscl_taps; v->under_scan_factor = dc->dcn_ip->under_scan_factor; - v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests; - v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin; - v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters; + v->pte_buffer_size_in_requests = (float)dc->dcn_ip->pte_buffer_size_in_requests; + v->dispclk_ramping_margin = (float)dc->dcn_ip->dispclk_ramping_margin; + v->max_inter_dcn_tile_repeaters = (float)dc->dcn_ip->max_inter_dcn_tile_repeaters; v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; v->bug_forcing_luma_and_chroma_request_to_same_size_fixed = @@ -903,14 +905,14 @@ bool dcn_validate_bandwidth( v->underscan_output[input_idx] = false; /* taken care of in recout already*/ v->interlace_output[input_idx] = false; - v->htotal[input_idx] = pipe->stream->timing.h_total; - v->vtotal[input_idx] = pipe->stream->timing.v_total; - v->vactive[input_idx] = pipe->stream->timing.v_addressable + - pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom; - v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total + v->htotal[input_idx] = (float)pipe->stream->timing.h_total; + v->vtotal[input_idx] = (float)pipe->stream->timing.v_total; + v->vactive[input_idx] = (float)(pipe->stream->timing.v_addressable + + pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom); + v->v_sync_plus_back_porch[input_idx] = (float)(pipe->stream->timing.v_total - v->vactive[input_idx] - - pipe->stream->timing.v_front_porch; - v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0; + - pipe->stream->timing.v_front_porch); + v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0f; if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) v->pixel_clock[input_idx] *= 2; if (!pipe->plane_state) { @@ -918,8 +920,8 @@ bool dcn_validate_bandwidth( v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32; v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s; v->lb_bit_per_pixel[input_idx] = 30; - v->viewport_width[input_idx] = pipe->stream->timing.h_addressable; - v->viewport_height[input_idx] = pipe->stream->timing.v_addressable; + v->viewport_width[input_idx] = (float)pipe->stream->timing.h_addressable; + v->viewport_height[input_idx] = (float)pipe->stream->timing.v_addressable; /* * for cases where we have no plane, we want to validate up to 1080p * source size because here we are only interested in if the output @@ -933,17 +935,17 @@ bool dcn_validate_bandwidth( v->viewport_height[input_idx] = 1080; v->scaler_rec_out_width[input_idx] = v->viewport_width[input_idx]; v->scaler_recout_height[input_idx] = v->viewport_height[input_idx]; - v->override_hta_ps[input_idx] = 1; - v->override_vta_ps[input_idx] = 1; - v->override_hta_pschroma[input_idx] = 1; - v->override_vta_pschroma[input_idx] = 1; + v->override_hta_ps[input_idx] = 1.0f; + v->override_vta_ps[input_idx] = 1.0f; + v->override_hta_pschroma[input_idx] = 1.0f; + v->override_vta_pschroma[input_idx] = 1.0f; v->source_scan[input_idx] = dcn_bw_hor; } else { - v->viewport_height[input_idx] = pipe->plane_res.scl_data.viewport.height; - v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width; - v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width; - v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height; + v->viewport_height[input_idx] = (float)pipe->plane_res.scl_data.viewport.height; + v->viewport_width[input_idx] = (float)pipe->plane_res.scl_data.viewport.width; + v->scaler_rec_out_width[input_idx] = (float)pipe->plane_res.scl_data.recout.width; + v->scaler_recout_height[input_idx] = (float)pipe->plane_res.scl_data.recout.height; if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) { if (pipe->plane_state->rotation % 2 == 0) { int viewport_end = pipe->plane_res.scl_data.viewport.width @@ -952,11 +954,11 @@ bool dcn_validate_bandwidth( + pipe->bottom_pipe->plane_res.scl_data.viewport.x; if (viewport_end > viewport_b_end) - v->viewport_width[input_idx] = viewport_end - - pipe->bottom_pipe->plane_res.scl_data.viewport.x; + v->viewport_width[input_idx] = (float)(viewport_end + - pipe->bottom_pipe->plane_res.scl_data.viewport.x); else - v->viewport_width[input_idx] = viewport_b_end - - pipe->plane_res.scl_data.viewport.x; + v->viewport_width[input_idx] = (float)(viewport_b_end + - pipe->plane_res.scl_data.viewport.x); } else { int viewport_end = pipe->plane_res.scl_data.viewport.height + pipe->plane_res.scl_data.viewport.y; @@ -964,14 +966,14 @@ bool dcn_validate_bandwidth( + pipe->bottom_pipe->plane_res.scl_data.viewport.y; if (viewport_end > viewport_b_end) - v->viewport_height[input_idx] = viewport_end - - pipe->bottom_pipe->plane_res.scl_data.viewport.y; + v->viewport_height[input_idx] = (float)(viewport_end + - pipe->bottom_pipe->plane_res.scl_data.viewport.y); else - v->viewport_height[input_idx] = viewport_b_end - - pipe->plane_res.scl_data.viewport.y; + v->viewport_height[input_idx] = (float)(viewport_b_end + - pipe->plane_res.scl_data.viewport.y); } - v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width - + pipe->bottom_pipe->plane_res.scl_data.recout.width; + v->scaler_rec_out_width[input_idx] = (float)(pipe->plane_res.scl_data.recout.width + + pipe->bottom_pipe->plane_res.scl_data.recout.width); } if (pipe->plane_state->rotation % 2 == 0) { @@ -997,7 +999,7 @@ bool dcn_validate_bandwidth( * allow us to disable dcc on the fly without re-calculating WM * * extra overhead for DCC is quite small. for 1080p WM without - * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us) + * DCC is only 0.417fus lower (urgent goes from 6.979fus to 6.562fus) */ unsigned int bpe; @@ -1009,11 +1011,11 @@ bool dcn_validate_bandwidth( pipe->plane_state->format); v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs( pipe->plane_state->tiling_info.gfx9.swizzle); - v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth); - v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps; - v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps; - v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c; - v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c; + v->lb_bit_per_pixel[input_idx] = (float)tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth); + v->override_hta_ps[input_idx] = (float)pipe->plane_res.scl_data.taps.h_taps; + v->override_vta_ps[input_idx] = (float)pipe->plane_res.scl_data.taps.v_taps; + v->override_hta_pschroma[input_idx] = (float)pipe->plane_res.scl_data.taps.h_taps_c; + v->override_vta_pschroma[input_idx] = (float)pipe->plane_res.scl_data.taps.v_taps_c; /* * Spreadsheet doesn't handle taps_c is one properly, * need to force Chroma to always be scaled to pass @@ -1091,29 +1093,29 @@ bool dcn_validate_bandwidth( } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { - v->byte_per_pixel_dety[k] = 8.0; - v->byte_per_pixel_detc[k] = 0.0; + v->byte_per_pixel_dety[k] = 8.0f; + v->byte_per_pixel_detc[k] = 0.0f; } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { - v->byte_per_pixel_dety[k] = 4.0; - v->byte_per_pixel_detc[k] = 0.0; + v->byte_per_pixel_dety[k] = 4.0f; + v->byte_per_pixel_detc[k] = 0.0f; } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { - v->byte_per_pixel_dety[k] = 2.0; - v->byte_per_pixel_detc[k] = 0.0; + v->byte_per_pixel_dety[k] = 2.0f; + v->byte_per_pixel_detc[k] = 0.0f; } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { - v->byte_per_pixel_dety[k] = 1.0; - v->byte_per_pixel_detc[k] = 2.0; + v->byte_per_pixel_dety[k] = 1.0f; + v->byte_per_pixel_detc[k] = 2.0f; } else { v->byte_per_pixel_dety[k] = 4.0f / 3.0f; v->byte_per_pixel_detc[k] = 8.0f / 3.0f; } } - v->total_data_read_bandwidth = 0.0; + v->total_data_read_bandwidth = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] * - dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k]; - v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] * - dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0; + dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k]; + v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0f * v->dpp_per_plane[k] * + dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0f; v->total_data_read_bandwidth = v->total_data_read_bandwidth + v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k]; } @@ -1144,13 +1146,13 @@ bool dcn_validate_bandwidth( dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = - v->stutter_exit_watermark * 1000; + (uint32_t)(v->stutter_exit_watermark * 1000.0f); context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = - v->stutter_enter_plus_exit_watermark * 1000; + (uint32_t)(v->stutter_enter_plus_exit_watermark * 1000.0f); context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = - v->dram_clock_change_watermark * 1000; - context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; - context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000; + (uint32_t)(v->dram_clock_change_watermark * 1000.0f); + context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = (uint32_t)(v->ptemeta_urgent_watermark * 1000.0f); + context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = (uint32_t)(v->urgent_watermark * 1000.0f); context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; @@ -1168,14 +1170,14 @@ bool dcn_validate_bandwidth( context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000); if (context->bw_ctx.bw.dcn.clk.dispclk_khz < - dc->debug.min_disp_clk_khz) { + (int)dc->debug.min_disp_clk_khz) { context->bw_ctx.bw.dcn.clk.dispclk_khz = - dc->debug.min_disp_clk_khz; + (int)dc->debug.min_disp_clk_khz; } context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz / v->dispclk_dppclk_ratio; - context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level]; + context->bw_ctx.bw.dcn.clk.phyclk_khz = (int)v->phyclk_per_state[v->voltage_level]; switch (v->voltage_level) { case 0: context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = @@ -1207,10 +1209,10 @@ bool dcn_validate_bandwidth( if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) continue; - pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx]; - pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx]; - pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx]; - pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; + pipe->pipe_dlg_param.vupdate_width = (unsigned int)v->v_update_width_pix[input_idx]; + pipe->pipe_dlg_param.vupdate_offset = (unsigned int)v->v_update_offset_pix[input_idx]; + pipe->pipe_dlg_param.vready_offset = (unsigned int)v->v_ready_offset_pix[input_idx]; + pipe->pipe_dlg_param.vstartup_start = (unsigned int)v->v_startup[input_idx]; pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; @@ -1248,10 +1250,10 @@ bool dcn_validate_bandwidth( TIMING_3D_FORMAT_SIDE_BY_SIDE))) { if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { /* update previously split pipe */ - hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx]; - hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx]; - hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx]; - hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; + hsplit_pipe->pipe_dlg_param.vupdate_width = (unsigned int)v->v_update_width_pix[input_idx]; + hsplit_pipe->pipe_dlg_param.vupdate_offset = (unsigned int)v->v_update_offset_pix[input_idx]; + hsplit_pipe->pipe_dlg_param.vready_offset = (unsigned int)v->v_ready_offset_pix[input_idx]; + hsplit_pipe->pipe_dlg_param.vstartup_start = (unsigned int)v->v_startup[input_idx]; hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; @@ -1302,12 +1304,12 @@ bool dcn_validate_bandwidth( */ bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9; - bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit; + bw_limit_pass = (v->total_data_read_bandwidth / 1000.0f) < bw_limit; PERFORMANCE_TRACE_END(); BW_VAL_TRACE_FINISH(); - if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->config.is_vmin_only_asic)) + if (bw_limit_pass && v->voltage_level <= (int)get_highest_allowed_voltage_level(dc->config.is_vmin_only_asic)) return true; else return false; @@ -1327,19 +1329,19 @@ void dcn_bw_update_from_pplib_fclks( vmax0p9_idx = fclks->num_levels > 0 ? fclks->num_levels - 1 : 0; dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = - 32 * (fclks->data[vmin0p65_idx].clocks_in_khz / 1000.0) / 1000.0; + 32 * (fclks->data[vmin0p65_idx].clocks_in_khz / 1000.0f) / 1000.0f; dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels * - (fclks->data[vmid0p72_idx].clocks_in_khz / 1000.0) - * ddr4_dram_factor_single_Channel / 1000.0; + (fclks->data[vmid0p72_idx].clocks_in_khz / 1000.0f) + * ddr4_dram_factor_single_Channel / 1000.0f; dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels * - (fclks->data[vnom0p8_idx].clocks_in_khz / 1000.0) - * ddr4_dram_factor_single_Channel / 1000.0; + (fclks->data[vnom0p8_idx].clocks_in_khz / 1000.0f) + * ddr4_dram_factor_single_Channel / 1000.0f; dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels * - (fclks->data[vmax0p9_idx].clocks_in_khz / 1000.0) - * ddr4_dram_factor_single_Channel / 1000.0; + (fclks->data[vmax0p9_idx].clocks_in_khz / 1000.0f) + * ddr4_dram_factor_single_Channel / 1000.0f; } void dcn_bw_update_from_pplib_dcfclks( @@ -1347,10 +1349,10 @@ void dcn_bw_update_from_pplib_dcfclks( struct dm_pp_clock_levels_with_voltage *dcfclks) { if (dcfclks->num_levels >= 3) { - dc->dcn_soc->dcfclkv_min0p65 = dcfclks->data[0].clocks_in_khz / 1000.0; - dc->dcn_soc->dcfclkv_mid0p72 = dcfclks->data[dcfclks->num_levels - 3].clocks_in_khz / 1000.0; - dc->dcn_soc->dcfclkv_nom0p8 = dcfclks->data[dcfclks->num_levels - 2].clocks_in_khz / 1000.0; - dc->dcn_soc->dcfclkv_max0p9 = dcfclks->data[dcfclks->num_levels - 1].clocks_in_khz / 1000.0; + dc->dcn_soc->dcfclkv_min0p65 = dcfclks->data[0].clocks_in_khz / 1000.0f; + dc->dcn_soc->dcfclkv_mid0p72 = dcfclks->data[dcfclks->num_levels - 3].clocks_in_khz / 1000.0f; + dc->dcn_soc->dcfclkv_nom0p8 = dcfclks->data[dcfclks->num_levels - 2].clocks_in_khz / 1000.0f; + dc->dcn_soc->dcfclkv_max0p9 = dcfclks->data[dcfclks->num_levels - 1].clocks_in_khz / 1000.0f; } } @@ -1360,9 +1362,9 @@ void dcn_get_soc_clks( int *min_dcfclk_khz, int *socclk_khz) { - *min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32; - *min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000; - *socclk_khz = dc->dcn_soc->socclk * 1000; + *min_fclk_khz = (int)(dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000.0f / 32.0f); + *min_dcfclk_khz = (int)(dc->dcn_soc->dcfclkv_min0p65 * 1000.0f); + *socclk_khz = (int)(dc->dcn_soc->socclk * 1000.0f); } void dcn_bw_notify_pplib_of_wm_ranges( @@ -1391,15 +1393,15 @@ void dcn_bw_notify_pplib_of_wm_ranges( ranges.num_reader_wm_sets = WM_SET_COUNT; ranges.num_writer_wm_sets = WM_SET_COUNT; ranges.reader_wm_sets[0].wm_inst = WM_A; - ranges.reader_wm_sets[0].min_drain_clk_mhz = min_dcfclk_khz / 1000; - ranges.reader_wm_sets[0].max_drain_clk_mhz = overdrive / 1000; - ranges.reader_wm_sets[0].min_fill_clk_mhz = min_fclk_khz / 1000; - ranges.reader_wm_sets[0].max_fill_clk_mhz = overdrive / 1000; + ranges.reader_wm_sets[0].min_drain_clk_mhz = (uint16_t)(min_dcfclk_khz / 1000); + ranges.reader_wm_sets[0].max_drain_clk_mhz = (uint16_t)(overdrive / 1000); + ranges.reader_wm_sets[0].min_fill_clk_mhz = (uint16_t)(min_fclk_khz / 1000); + ranges.reader_wm_sets[0].max_fill_clk_mhz = (uint16_t)(overdrive / 1000); ranges.writer_wm_sets[0].wm_inst = WM_A; - ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000; - ranges.writer_wm_sets[0].max_fill_clk_mhz = overdrive / 1000; - ranges.writer_wm_sets[0].min_drain_clk_mhz = min_fclk_khz / 1000; - ranges.writer_wm_sets[0].max_drain_clk_mhz = overdrive / 1000; + ranges.writer_wm_sets[0].min_fill_clk_mhz = (uint16_t)(socclk_khz / 1000); + ranges.writer_wm_sets[0].max_fill_clk_mhz = (uint16_t)(overdrive / 1000); + ranges.writer_wm_sets[0].min_drain_clk_mhz = (uint16_t)(min_fclk_khz / 1000); + ranges.writer_wm_sets[0].max_drain_clk_mhz = (uint16_t)(overdrive / 1000); if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) { ranges.reader_wm_sets[0].wm_inst = WM_A; @@ -1583,14 +1585,14 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc) dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency; dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width; - dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte; - dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte; - dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels; - dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines; - dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte; + dc->dml.ip.rob_buffer_size_kbytes = (unsigned int)dc->dcn_ip->rob_buffer_size_in_kbyte; + dc->dml.ip.det_buffer_size_kbytes = (unsigned int)dc->dcn_ip->det_buffer_size_in_kbyte; + dc->dml.ip.dpp_output_buffer_pixels = (unsigned int)dc->dcn_ip->dpp_output_buffer_pixels; + dc->dml.ip.opp_output_buffer_lines = (unsigned int)dc->dcn_ip->opp_output_buffer_lines; + dc->dml.ip.pixel_chunk_size_kbytes = (unsigned int)dc->dcn_ip->pixel_chunk_size_in_kbyte; dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes; - dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size; - dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size; + dc->dml.ip.pte_chunk_size_kbytes = (unsigned int)dc->dcn_ip->pte_chunk_size; + dc->dml.ip.meta_chunk_size_kbytes = (unsigned int)dc->dcn_ip->meta_chunk_size; dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size; dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size; dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index e82f2d531211..fac5a50fefb2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -990,7 +990,8 @@ void dcn20_populate_dml_writeback_from_context(struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) { - int pipe_cnt, i; + unsigned int i; + int pipe_cnt; dc_assert_fp_enabled(); @@ -1036,15 +1037,15 @@ void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params, dc_assert_fp_enabled(); for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { - wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + wb_arb_params->cli_watermark[k] = (unsigned int)(get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + wb_arb_params->pstate_watermark[k] = (unsigned int)(get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); } - wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */ + wb_arb_params->time_per_pixel = (unsigned int)(16.0 * 1000.0 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000)); /* 4 bit fraction, ms */ } static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { if (!context->res_ctx.pipe_ctx[i].stream) continue; @@ -1134,7 +1135,7 @@ static void dcn20_adjust_freesync_v_startup( /* The newVStartUp is 1 line before vsync point */ newVstartup = asic_blank_end + 1; - *vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup : *vstartup_start); + *vstartup_start = (((int)newVstartup > *vstartup_start) ? (int)newVstartup : *vstartup_start); } void dcn20_calculate_dlg_params(struct dc *dc, @@ -1143,23 +1144,24 @@ void dcn20_calculate_dlg_params(struct dc *dc, int pipe_cnt, int vlevel) { - int i, pipe_idx, active_hubp_count = 0; + int pipe_idx, active_hubp_count = 0; + unsigned int i; dc_assert_fp_enabled(); /* Writeback MCIF_WB arbitration parameters */ dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); - context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; - context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; - context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; - context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; + context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(context->bw_ctx.dml.vba.DISPCLK * 1000.0); + context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(context->bw_ctx.dml.vba.DCFCLK * 1000.0); + context->bw_ctx.bw.dcn.clk.socclk_khz = (int)(context->bw_ctx.dml.vba.SOCCLK * 1000.0); + context->bw_ctx.bw.dcn.clk.dramclk_khz = (int)(context->bw_ctx.dml.vba.DRAMSpeed * 1000.0 / 16.0); - if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz) + if ((int)dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz) context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz; - context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; - context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; + context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000.0); + context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(context->bw_ctx.dml.vba.FabricClock * 1000.0); context->bw_ctx.bw.dcn.clk.p_state_change_support = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != dm_dram_clock_change_unsupported; @@ -1173,18 +1175,18 @@ void dcn20_calculate_dlg_params(struct dc *dc, context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); - if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) - context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; + if ((unsigned int)context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) + context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)dc->debug.min_disp_clk_khz; for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { if (!context->res_ctx.pipe_ctx[i].stream) continue; if (context->res_ctx.pipe_ctx[i].plane_state) active_hubp_count++; - pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); - pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); - pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); - pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + pipes[pipe_idx].pipe.dest.vstartup_start = (unsigned int)get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + pipes[pipe_idx].pipe.dest.vupdate_offset = (unsigned int)get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + pipes[pipe_idx].pipe.dest.vupdate_width = (unsigned int)get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + pipes[pipe_idx].pipe.dest.vready_offset = (unsigned int)get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) { // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests @@ -1196,9 +1198,9 @@ void dcn20_calculate_dlg_params(struct dc *dc, } if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) - context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; + context->bw_ctx.bw.dcn.clk.dppclk_khz = (int)(pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000.0); context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = - pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; + (int)(pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000.0); context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; if (dc->ctx->dce_version < DCN_VERSION_3_1 && context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid) @@ -1215,8 +1217,8 @@ void dcn20_calculate_dlg_params(struct dc *dc, /*save a original dppclock copy*/ context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; - context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; - context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; + context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = (int)(context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000.0); + context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = (int)(context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000.0); context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx; @@ -1317,7 +1319,8 @@ int dcn20_populate_dml_pipes_from_context(struct dc *dc, enum dc_validate_mode validate_mode) { (void)validate_mode; - int pipe_cnt, i; + int pipe_cnt; + unsigned int i; bool synchronized_vblank = true; struct resource_context *res_ctx = &context->res_ctx; @@ -1402,11 +1405,12 @@ int dcn20_populate_dml_pipes_from_context(struct dc *dc, timing->h_addressable + timing->h_border_left + timing->h_border_right; pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; - pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; + pipes[pipe_cnt].pipe.dest.interlaced = (unsigned char)timing->flags.INTERLACE; pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0; if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; - pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; + pipes[pipe_cnt].pipe.dest.otg_inst = + (unsigned char)res_ctx->pipe_ctx[i].stream_res.tg->inst; pipes[pipe_cnt].dout.dp_lanes = 4; pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na; pipes[pipe_cnt].dout.is_virtual = 0; @@ -1735,7 +1739,8 @@ void dcn20_calculate_wm(struct dc *dc, struct dc_state *context, int vlevel, enum dc_validate_mode validate_mode) { - int pipe_cnt, i, pipe_idx; + int pipe_cnt, pipe_idx; + unsigned int i; dc_assert_fp_enabled(); @@ -1798,51 +1803,51 @@ void dcn20_calculate_wm(struct dc *dc, struct dc_state *context, pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; } - context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); if (vlevel < 2) { pipes[0].clks_cfg.voltage = 2; pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; } - context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); if (vlevel < 3) { pipes[0].clks_cfg.voltage = 3; pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; } - context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); pipes[0].clks_cfg.voltage = vlevel; pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; - context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); } void dcn20_update_bounding_box(struct dc *dc, @@ -1853,7 +1858,7 @@ void dcn20_update_bounding_box(struct dc *dc, { int num_calculated_states = 0; int min_dcfclk = 0; - int i; + unsigned int i; dc_assert_fp_enabled(); @@ -1879,7 +1884,7 @@ void dcn20_update_bounding_box(struct dc *dc, bb->clock_limits[i].dram_speed_mts = uclk_states[i] * 16 / 1000; // FCLK:UCLK ratio is 1.08 - min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080, + min_fclk_required_by_uclk = (int)div_u64(((unsigned long long)uclk_states[i]) * 1080, 1000000); bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? @@ -1914,7 +1919,7 @@ void dcn20_update_bounding_box(struct dc *dc, void dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st *bb, struct pp_smu_nv_clock_table max_clocks) { - int i; + unsigned int i; dc_assert_fp_enabled(); @@ -2134,8 +2139,8 @@ void dcn20_fpu_set_wm_ranges(int i, { dc_assert_fp_enabled(); - ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; - ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; + ranges->reader_wm_sets[i].min_fill_clk_mhz = (uint16_t)((i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0); + ranges->reader_wm_sets[i].max_fill_clk_mhz = (uint16_t)(loaded_bb->clock_limits[i].dram_speed_mts / 16); } void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v, @@ -2158,7 +2163,7 @@ int dcn21_populate_dml_pipes_from_context(struct dc *dc, enum dc_validate_mode validate_mode) { uint32_t pipe_cnt; - int i; + unsigned int i; dc_assert_fp_enabled(); @@ -2222,14 +2227,14 @@ static void calculate_wm_set_for_vlevel(int vlevel, dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; - wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; - wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; - wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; - wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; - wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; - wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; - wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; - wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; + wm_set->urgent_ns = (uint32_t)(get_wm_urgent(dml, pipes, pipe_cnt) * 1000.0); + wm_set->cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000.0); + wm_set->cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000.0); + wm_set->cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000.0); + wm_set->pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000.0); + wm_set->frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000.0); + wm_set->frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000.0); + wm_set->urgent_latency_ns = (uint32_t)(get_urgent_latency(dml, pipes, pipe_cnt) * 1000.0); dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; } @@ -2240,7 +2245,8 @@ static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context, int vlevel_req, enum dc_validate_mode validate_mode) { - int pipe_cnt, i, pipe_idx; + int pipe_cnt, pipe_idx; + unsigned int i; int vlevel, vlevel_max; struct wm_range_table_entry *table_entry; struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; @@ -2476,7 +2482,8 @@ void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) { - int pipe_cnt, i, j; + int pipe_cnt; + unsigned int i, j; double max_calc_writeback_dispclk; double writeback_dispclk; struct writeback_st dout_wb = {0}; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c index f5f636afe33c..ac37a2134351 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c @@ -326,7 +326,7 @@ static unsigned int dscceComputeDelay( pixelsPerClock = 1; //initial transmit delay as per PPS - initalXmitDelay = dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock); + initalXmitDelay = (unsigned int)dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock); //compute ssm delay if (bpc == 8) @@ -519,13 +519,13 @@ static bool CalculatePrefetchSchedule( double LinesToRequestPrefetchPixelData = 0; if (ScalerEnabled) - DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCL; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotal + DPPCLKDelaySCL); else - DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly); - DPPCycles = DPPCycles + DPPCLKDelayCNVCFormater + NumberOfCursors * DPPCLKDelayCNVCCursor; + DPPCycles = (unsigned int)(DPPCycles + DPPCLKDelayCNVCFormater + NumberOfCursors * DPPCLKDelayCNVCCursor); - DISPCLKCycles = DISPCLKDelaySubtotal; + DISPCLKCycles = (unsigned int)DISPCLKDelaySubtotal; if (DPPCLK == 0.0 || DISPCLK == 0.0) return true; @@ -545,7 +545,7 @@ static bool CalculatePrefetchSchedule( *DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / HTotal, 1); *DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * HTotal)); - *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1); + *VUpdateOffsetPix = (unsigned int)dml_ceil(HTotal / 4.0, 1); TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK); *VUpdateWidthPix = (14.0 / DCFCLKDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime) * PixelClock; @@ -574,10 +574,10 @@ static bool CalculatePrefetchSchedule( if (VStartup * LineTime < Tsetup + TWait + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) { MyError = true; - *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (Tsetup + TWait - + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) / LineTime; + *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (unsigned int)((Tsetup + TWait + + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) / LineTime); } else - *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = 0.0; + *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (unsigned int)0.0; } else Tdm = 0; @@ -828,14 +828,13 @@ static double CalculatePrefetchSourceLines( if (!mode_lib->vba.IgnoreViewportPositioning) { - *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; + *MaxNumSwath = (unsigned int)(dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0); if (*VInitPreFill > 1.0) - MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight; + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill - 2) % SwathHeight); else - MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) - % SwathHeight; - MaxPartialSwath = dml_max(1U, MaxPartialSwath); + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill + SwathHeight - 2) % SwathHeight); + MaxPartialSwath = (unsigned int)dml_max(1U, MaxPartialSwath); } else { @@ -843,13 +842,12 @@ static double CalculatePrefetchSourceLines( dml_print( "WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n"); - *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); + *MaxNumSwath = (unsigned int)dml_ceil(*VInitPreFill / SwathHeight, 1); if (*VInitPreFill > 1.0) - MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight; + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill - 1) % SwathHeight); else - MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 1) - % SwathHeight; + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill + SwathHeight - 1) % SwathHeight); } return *MaxNumSwath * SwathHeight + MaxPartialSwath; @@ -899,34 +897,34 @@ static unsigned int CalculateVMAndRowBytes( MetaRequestHeight = 8 * BlockHeight256Bytes; MetaRequestWidth = 8 * BlockWidth256Bytes; if (ScanDirection == dm_horz) { - *meta_row_height = MetaRequestHeight; - MetaSurfWidth = dml_ceil((double) SwathWidth - 1, MetaRequestWidth) - + MetaRequestWidth; - *MetaRowByte = MetaSurfWidth * MetaRequestHeight * BytePerPixel / 256.0; + *meta_row_height = (unsigned int)MetaRequestHeight; + MetaSurfWidth = (unsigned int)(dml_ceil((double) SwathWidth - 1, MetaRequestWidth) + + MetaRequestWidth); + *MetaRowByte = (unsigned int)(MetaSurfWidth * MetaRequestHeight * BytePerPixel / 256.0); } else { - *meta_row_height = MetaRequestWidth; - MetaSurfHeight = dml_ceil((double) SwathWidth - 1, MetaRequestHeight) - + MetaRequestHeight; - *MetaRowByte = MetaSurfHeight * MetaRequestWidth * BytePerPixel / 256.0; + *meta_row_height = (unsigned int)MetaRequestWidth; + MetaSurfHeight = (unsigned int)(dml_ceil((double) SwathWidth - 1, MetaRequestHeight) + + MetaRequestHeight); + *MetaRowByte = (unsigned int)(MetaSurfHeight * MetaRequestWidth * BytePerPixel / 256.0); } if (ScanDirection == dm_horz) { - DCCMetaSurfaceBytes = DCCMetaPitch + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel - / 256; + / 256); } else { - DCCMetaSurfaceBytes = DCCMetaPitch + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil( (double) ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel - / 256; + / 256); } if (GPUVMEnable == true) { - MetaPTEBytesFrame = (dml_ceil( + MetaPTEBytesFrame = (unsigned int)((dml_ceil( (double) (DCCMetaSurfaceBytes - VMMPageSize) / (8 * VMMPageSize), - 1) + 1) * 64; + 1) + 1) * 64); MPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 1); } else { MetaPTEBytesFrame = 0; @@ -960,7 +958,7 @@ static unsigned int CalculateVMAndRowBytes( if (GPUVMEnable == true && mode_lib->vba.GPUVMMaxPageTableLevels > 1) { if (ScanDirection == dm_horz) { DPDE0BytesFrame = - 64 + (unsigned int)(64 * (dml_ceil( ((Pitch * (dml_ceil( @@ -972,10 +970,10 @@ static unsigned int CalculateVMAndRowBytes( - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } else { DPDE0BytesFrame = - 64 + (unsigned int)(64 * (dml_ceil( ((Pitch * (dml_ceil( @@ -987,7 +985,7 @@ static unsigned int CalculateVMAndRowBytes( - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } ExtraDPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 2); } else { @@ -1007,7 +1005,7 @@ static unsigned int CalculateVMAndRowBytes( if (SurfaceTiling == dm_sw_linear) { PixelPTEReqHeight = 1; - PixelPTEReqWidth = 8.0 * VMMPageSize / BytePerPixel; + PixelPTEReqWidth = (unsigned int)8.0 * VMMPageSize / BytePerPixel; PTERequestSize = 64; FractionOfPTEReturnDrop = 0; } else if (MacroTileSizeBytes == 4096) { @@ -1036,7 +1034,7 @@ static unsigned int CalculateVMAndRowBytes( EffectivePDEProcessingBufIn64KBReqs = PDEProcessingBufIn64KBReqs; if (SurfaceTiling == dm_sw_linear) { - *dpte_row_height = + *dpte_row_height = (unsigned int)( dml_min( 128, 1 @@ -1049,21 +1047,21 @@ static unsigned int CalculateVMAndRowBytes( * 65536.0 / BytePerPixel) / Pitch), - 1)); + 1))); *PixelPTEBytesPerRow = PTERequestSize - * (dml_ceil( + * (unsigned int)(dml_ceil( (double) (Pitch * *dpte_row_height - 1) / PixelPTEReqWidth, 1) + 1); } else if (ScanDirection == dm_horz) { *dpte_row_height = PixelPTEReqHeight; *PixelPTEBytesPerRow = PTERequestSize - * (dml_ceil(((double) SwathWidth - 1) / PixelPTEReqWidth, 1) + * (unsigned int)(dml_ceil(((double) SwathWidth - 1) / PixelPTEReqWidth, 1) + 1); } else { - *dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth); + *dpte_row_height = (unsigned int)dml_min(PixelPTEReqWidth, *MacroTileWidth); *PixelPTEBytesPerRow = PTERequestSize - * (dml_ceil( + * (unsigned int)(dml_ceil( ((double) SwathWidth - 1) / PixelPTEReqHeight, 1) + 1); @@ -1539,10 +1537,10 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer / mode_lib->vba.PixelClock[k]) / mode_lib->vba.VRatio[k]; if (mode_lib->vba.BytePerPixelDETC[k] > 0) { - mode_lib->vba.LinesInDETC[k] = mode_lib->vba.DETBufferSizeC[k] + mode_lib->vba.LinesInDETC[k] = (unsigned int)(mode_lib->vba.DETBufferSizeC[k] / mode_lib->vba.BytePerPixelDETC[k] - / (mode_lib->vba.SwathWidthY[k] / 2); - mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = dml_floor( + / (mode_lib->vba.SwathWidthY[k] / 2)); + mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = (unsigned int)dml_floor( mode_lib->vba.LinesInDETC[k], mode_lib->vba.SwathHeightC[k]); mode_lib->vba.FullDETBufferingTimeC[k] = @@ -1811,7 +1809,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], bpp, - dml_ceil( + (unsigned int)dml_ceil( (double) mode_lib->vba.HActive[k] / mode_lib->vba.NumberOfDSCSlices[k], 1), @@ -1821,22 +1819,22 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.OutputFormat[k]); } else { mode_lib->vba.DSCDelay[k] = - 2 + (unsigned int)(2 * (dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], bpp, - dml_ceil( + (unsigned int)dml_ceil( (double) mode_lib->vba.HActive[k] / mode_lib->vba.NumberOfDSCSlices[k], 1), - slices / 2.0, + (unsigned int)(slices / 2.0), mode_lib->vba.OutputFormat[k]) + dscComputeDelay( - mode_lib->vba.OutputFormat[k])); + mode_lib->vba.OutputFormat[k]))); } - mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[k] + mode_lib->vba.DSCDelay[k] = (unsigned int)(mode_lib->vba.DSCDelay[k] * mode_lib->vba.PixelClock[k] - / mode_lib->vba.PixelClockBackEnd[k]; + / mode_lib->vba.PixelClockBackEnd[k]); } else { mode_lib->vba.DSCDelay[k] = 0; } @@ -1860,8 +1858,8 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer Calculate256BBlockSizes( mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), - dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2), &mode_lib->vba.BlockHeight256BytesY[k], &mode_lib->vba.BlockHeight256BytesC[k], &mode_lib->vba.BlockWidth256BytesY[k], @@ -1873,11 +1871,11 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.BlockWidth256BytesY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k], mode_lib->vba.ViewportHeight[k], - mode_lib->vba.SwathWidthY[k], + (unsigned int)mode_lib->vba.SwathWidthY[k], mode_lib->vba.GPUVMEnable, mode_lib->vba.VMMPageSize, mode_lib->vba.PTEBufferSizeInRequestsLuma, @@ -1913,13 +1911,13 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.BlockWidth256BytesC[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil( + (unsigned int)dml_ceil( mode_lib->vba.BytePerPixelDETC[k], 2), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k] / 2, mode_lib->vba.ViewportHeight[k] / 2, - mode_lib->vba.SwathWidthY[k] / 2, + (unsigned int)mode_lib->vba.SwathWidthY[k] / 2, mode_lib->vba.GPUVMEnable, mode_lib->vba.VMMPageSize, mode_lib->vba.PTEBufferSizeInRequestsLuma, @@ -1989,7 +1987,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.WritebackLumaVTaps[k], mode_lib->vba.WritebackChromaHTaps[k], mode_lib->vba.WritebackChromaVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k]) + (unsigned int)mode_lib->vba.WritebackDestinationWidth[k]) / mode_lib->vba.DISPCLK; } else mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0; @@ -2008,7 +2006,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.WritebackLumaVTaps[j], mode_lib->vba.WritebackChromaHTaps[j], mode_lib->vba.WritebackChromaVTaps[j], - mode_lib->vba.WritebackDestinationWidth[j]) + (unsigned int)mode_lib->vba.WritebackDestinationWidth[j]) / mode_lib->vba.DISPCLK); } } @@ -2023,7 +2021,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.VStartupLines = 13; for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { - mode_lib->vba.MaxVStartupLines[k] = + mode_lib->vba.MaxVStartupLines[k] = (unsigned int)( mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] - dml_max( 1.0, @@ -2031,11 +2029,11 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), - 1)); + 1))); } for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) - mode_lib->vba.MaximumMaxVStartupLines = dml_max( + mode_lib->vba.MaximumMaxVStartupLines = (unsigned int)dml_max( mode_lib->vba.MaximumMaxVStartupLines, mode_lib->vba.MaxVStartupLines[k]); @@ -2111,7 +2109,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer - mode_lib->vba.VActive[k], mode_lib->vba.HTotal[k], mode_lib->vba.MaxInterDCNTileRepeaters, - dml_min( + (unsigned int)dml_min( mode_lib->vba.VStartupLines, mode_lib->vba.MaxVStartupLines[k]), mode_lib->vba.GPUVMMaxPageTableLevels, @@ -2123,11 +2121,11 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.UrgentLatencyPixelDataOnly, mode_lib->vba.UrgentExtraLatency, mode_lib->vba.TCalc, - mode_lib->vba.PDEAndMetaPTEBytesFrame[k], - mode_lib->vba.MetaRowByte[k], - mode_lib->vba.PixelPTEBytesPerRow[k], + (unsigned int)mode_lib->vba.PDEAndMetaPTEBytesFrame[k], + (unsigned int)mode_lib->vba.MetaRowByte[k], + (unsigned int)mode_lib->vba.PixelPTEBytesPerRow[k], mode_lib->vba.PrefetchSourceLinesY[k], - mode_lib->vba.SwathWidthY[k], + (unsigned int)mode_lib->vba.SwathWidthY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.VInitPreFillY[k], mode_lib->vba.MaxNumSwathY[k], @@ -2157,7 +2155,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer &mode_lib->vba.VUpdateWidthPix[k], &mode_lib->vba.VReadyOffsetPix[k]); if (mode_lib->vba.BlendingAndTiming[k] == k) { - mode_lib->vba.VStartup[k] = dml_min( + mode_lib->vba.VStartup[k] = (unsigned int)dml_min( mode_lib->vba.VStartupLines, mode_lib->vba.MaxVStartupLines[k]); if (mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata @@ -2166,7 +2164,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata; } } else { - mode_lib->vba.VStartup[k] = + mode_lib->vba.VStartup[k] = (unsigned int) dml_min( mode_lib->vba.VStartupLines, mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]); @@ -2253,10 +2251,10 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer ImmediateFlipBytes[k] = 0; if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { - ImmediateFlipBytes[k] = + ImmediateFlipBytes[k] = (unsigned int)( mode_lib->vba.PDEAndMetaPTEBytesFrame[k] + mode_lib->vba.MetaRowByte[k] - + mode_lib->vba.PixelPTEBytesPerRow[k]; + + mode_lib->vba.PixelPTEBytesPerRow[k]); } } mode_lib->vba.TotImmediateFlipBytes = 0; @@ -2264,8 +2262,8 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { mode_lib->vba.TotImmediateFlipBytes = - mode_lib->vba.TotImmediateFlipBytes - + ImmediateFlipBytes[k]; + (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + + ImmediateFlipBytes[k]); } } for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { @@ -2284,8 +2282,8 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.VRatio[k], mode_lib->vba.Tno_bw[k], mode_lib->vba.PDEAndMetaPTEBytesFrame[k], - mode_lib->vba.MetaRowByte[k], - mode_lib->vba.PixelPTEBytesPerRow[k], + (unsigned int)mode_lib->vba.MetaRowByte[k], + (unsigned int)mode_lib->vba.PixelPTEBytesPerRow[k], mode_lib->vba.DCCEnable[k], mode_lib->vba.dpte_row_height[k], mode_lib->vba.meta_row_height[k], @@ -2409,7 +2407,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer double MaxDETBufferingTimeY; double ActiveDRAMClockChangeLatencyMarginY; - mode_lib->vba.LBLatencyHidingSourceLinesY = + mode_lib->vba.LBLatencyHidingSourceLinesY = (unsigned int)( dml_min( mode_lib->vba.MaxLineBufferLines, (unsigned int) dml_floor( @@ -2419,9 +2417,9 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer / dml_max( mode_lib->vba.HRatio[k], 1.0)), - 1)) - (mode_lib->vba.vtaps[k] - 1); + 1)) -(mode_lib->vba.vtaps[k] - 1)); - mode_lib->vba.LBLatencyHidingSourceLinesC = + mode_lib->vba.LBLatencyHidingSourceLinesC = (unsigned int)( dml_min( mode_lib->vba.MaxLineBufferLines, (unsigned int) dml_floor( @@ -2434,7 +2432,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer / 2, 1.0)), 1)) - - (mode_lib->vba.VTAPsChroma[k] - 1); + -(mode_lib->vba.VTAPsChroma[k] - 1)); EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY / mode_lib->vba.VRatio[k] @@ -2691,14 +2689,14 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { if (mode_lib->vba.BlendingAndTiming[k] == k) { - unsigned int Margin = (mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k]) - * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]; + unsigned int Margin = (unsigned int)((mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k]) + * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]); if (FirstMainPlane) { VStartupMargin = Margin; FirstMainPlane = false; } else - VStartupMargin = dml_min(VStartupMargin, Margin); + VStartupMargin = (unsigned int)dml_min(VStartupMargin, Margin); } if (mode_lib->vba.UseMaximumVStartup) { @@ -2896,26 +2894,26 @@ static void dml20_DisplayPipeConfiguration(struct display_mode_lib *mode_lib) if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) { - mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY; - mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC; + mode_lib->vba.SwathHeightY[k] = (unsigned int)MaximumSwathHeightY; + mode_lib->vba.SwathHeightC[k] = (unsigned int)MaximumSwathHeightC; } else { - mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY; - mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC; + mode_lib->vba.SwathHeightY[k] = (unsigned int)MinimumSwathHeightY; + mode_lib->vba.SwathHeightC[k] = (unsigned int)MinimumSwathHeightC; } if (mode_lib->vba.SwathHeightC[k] == 0) { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024; - mode_lib->vba.DETBufferSizeC[k] = 0; + mode_lib->vba.DETBufferSizeY[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] * 1024); + mode_lib->vba.DETBufferSizeC[k] = 0; } else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 / 2; - mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 / 2; + mode_lib->vba.DETBufferSizeY[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 / 2); + mode_lib->vba.DETBufferSizeC[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 / 2); } else { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 * 2 / 3; - mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 / 3; + mode_lib->vba.DETBufferSizeY[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 * 2 / 3); + mode_lib->vba.DETBufferSizeC[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 / 3); } } } @@ -3233,23 +3231,23 @@ static unsigned int TruncToValidBPP( if (DecimalBPP < 6) return BPP_INVALID; else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1.0 / 16) - return 1.5 * DSCInputBitPerComponent - 1.0 / 16; + return (unsigned int)(1.5 * DSCInputBitPerComponent - 1.0 / 16); else - return dml_floor(16 * DecimalBPP, 1) / 16; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16); } else if (Format == dm_n422) { if (DecimalBPP < 7) return BPP_INVALID; else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1.0 / 16) - return 2 * DSCInputBitPerComponent - 1.0 / 16; + return (unsigned int)(2 * DSCInputBitPerComponent - 1.0 / 16); else - return dml_floor(16 * DecimalBPP, 1) / 16; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16); } else { if (DecimalBPP < 8) return BPP_INVALID; else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1.0 / 16) - return 3 * DSCInputBitPerComponent - 1.0 / 16; + return (unsigned int)(3 * DSCInputBitPerComponent - 1.0 / 16); else - return dml_floor(16 * DecimalBPP, 1) / 16; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16); } } else if (Format == dm_420) { if (DecimalBPP >= 18) @@ -3288,8 +3286,8 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l { struct vba_vars_st *locals = &mode_lib->vba; - int i; - unsigned int j, k, m; + int idx; + unsigned int i, j, k, m; /*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/ @@ -3752,8 +3750,8 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l Calculate256BBlockSizes( mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(locals->BytePerPixelInDETY[k], 1.0), - dml_ceil(locals->BytePerPixelInDETC[k], 2.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETY[k], 1.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETC[k], 2.0), &locals->Read256BlockHeightY[k], &locals->Read256BlockHeightC[k], &locals->Read256BlockWidthY[k], @@ -3930,7 +3928,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l locals->DISPCLK_DPPCLK_Support[i][j] = false; } } - locals->TotalNumberOfActiveDPP[i][j] = 0.0; + locals->TotalNumberOfActiveDPP[i][j] = (unsigned int)0.0; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; if (j == 1) { @@ -3985,7 +3983,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l || mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) locals->DISPCLK_DPPCLK_Support[i][j] = false; } - locals->TotalNumberOfActiveDPP[i][j] = 0.0; + locals->TotalNumberOfActiveDPP[i][j] = (unsigned int)0.0; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; } @@ -4239,17 +4237,17 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l || locals->RequiresDSC[i][k] == false) { mode_lib->vba.slices = 0; } else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) { - mode_lib->vba.slices = dml_ceil( + mode_lib->vba.slices = (unsigned int)dml_ceil( mode_lib->vba.PixelClockBackEnd[k] / 400.0, 4.0); } else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) { - mode_lib->vba.slices = 8.0; + mode_lib->vba.slices = (unsigned int)8.0; } else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) { - mode_lib->vba.slices = 4.0; + mode_lib->vba.slices = (unsigned int)4.0; } else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) { - mode_lib->vba.slices = 2.0; + mode_lib->vba.slices = (unsigned int)2.0; } else { - mode_lib->vba.slices = 1.0; + mode_lib->vba.slices = (unsigned int)1.0; } if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE || locals->OutputBppPerState[i][k] == BPP_INVALID) { @@ -4263,7 +4261,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], mode_lib->vba.bpp, - dml_ceil( + (unsigned int)dml_ceil( mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), @@ -4276,7 +4274,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 2.0 * (dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], mode_lib->vba.bpp, - dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), + (unsigned int)dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), mode_lib->vba.slices / 2, mode_lib->vba.OutputFormat[k]) + dscComputeDelay(mode_lib->vba.OutputFormat[k])); @@ -4302,9 +4300,9 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (j = 0; j < 2; j++) { for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) - locals->SwathWidthYPerState[i][j][k] = dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k])); + locals->SwathWidthYPerState[i][j][k] = (unsigned int)dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k])); else - locals->SwathWidthYPerState[i][j][k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k]; + locals->SwathWidthYPerState[i][j][k] = (unsigned int)locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k]; locals->SwathWidthGranularityY = 256 / dml_ceil(locals->BytePerPixelInDETY[k], 1) / locals->MaxSwathHeightY[k]; locals->RoundedUpMaxSwathSizeBytesY = (dml_ceil(locals->SwathWidthYPerState[i][j][k] - 1, locals->SwathWidthGranularityY) + locals->SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k]; @@ -4324,11 +4322,11 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } if (locals->RoundedUpMaxSwathSizeBytesY + locals->RoundedUpMaxSwathSizeBytesC <= locals->DETBufferSizeInKByte[0] * 1024.0 / 2) { - locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k]; - locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k]; + locals->SwathHeightYPerState[i][j][k] = (unsigned int)locals->MaxSwathHeightY[k]; + locals->SwathHeightCPerState[i][j][k] = (unsigned int)locals->MaxSwathHeightC[k]; } else { - locals->SwathHeightYPerState[i][j][k] = locals->MinSwathHeightY[k]; - locals->SwathHeightCPerState[i][j][k] = locals->MinSwathHeightC[k]; + locals->SwathHeightYPerState[i][j][k] = (unsigned int)locals->MinSwathHeightY[k]; + locals->SwathHeightCPerState[i][j][k] = (unsigned int)locals->MinSwathHeightC[k]; } if (locals->BytePerPixelInDETC[k] == 0) { @@ -4343,16 +4341,16 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2); } - locals->EffectiveLBLatencyHidingSourceLinesLuma = dml_min(locals->MaxLineBufferLines, + locals->EffectiveLBLatencyHidingSourceLinesLuma = (unsigned int)dml_min(locals->MaxLineBufferLines, dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k] / dml_max(locals->HRatio[k], 1)), 1)) - (locals->vtaps[k] - 1); - locals->EffectiveLBLatencyHidingSourceLinesChroma = dml_min(locals->MaxLineBufferLines, + locals->EffectiveLBLatencyHidingSourceLinesChroma = (unsigned int)dml_min(locals->MaxLineBufferLines, dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k] / 2 / dml_max(locals->HRatio[k] / 2, 1)), 1)) - (locals->VTAPsChroma[k] - 1); - locals->EffectiveDETLBLinesLuma = dml_floor(locals->LinesInDETLuma + dml_min( + locals->EffectiveDETLBLinesLuma = (unsigned int)dml_floor(locals->LinesInDETLuma + dml_min( locals->LinesInDETLuma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETY[k] * locals->PSCL_FACTOR[k] / locals->ReturnBWPerState[i][0], locals->EffectiveLBLatencyHidingSourceLinesLuma), @@ -4507,7 +4505,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.Read256BlockWidthY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k], mode_lib->vba.ViewportHeight[k], @@ -4546,17 +4544,17 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.Read256BlockWidthY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0), mode_lib->vba.SourceScan[k], - mode_lib->vba.ViewportWidth[k] / 2.0, - mode_lib->vba.ViewportHeight[k] / 2.0, - mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0, + (unsigned int)(mode_lib->vba.ViewportWidth[k] / 2.0), + (unsigned int)(mode_lib->vba.ViewportHeight[k] / 2.0), + (unsigned int)(mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0), mode_lib->vba.GPUVMEnable, mode_lib->vba.VMMPageSize, mode_lib->vba.PTEBufferSizeInRequestsLuma, mode_lib->vba.PDEProcessingBufIn64KBReqs, mode_lib->vba.PitchC[k], - 0.0, + (unsigned int)0.0, &mode_lib->vba.MacroTileWidthC[k], &mode_lib->vba.MetaRowBytesC, &mode_lib->vba.DPTEBytesPerRowC, @@ -4575,8 +4573,8 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l &mode_lib->vba.MaxNumSwC[k]); } else { mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = 0.0; - mode_lib->vba.MetaRowBytesC = 0.0; - mode_lib->vba.DPTEBytesPerRowC = 0.0; + mode_lib->vba.MetaRowBytesC = (unsigned int)0.0; + mode_lib->vba.DPTEBytesPerRowC = (unsigned int)0.0; locals->PrefetchLinesC[0][0][k] = 0.0; locals->PTEBufferSizeNotExceededC[i][j][k] = true; locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma + mode_lib->vba.PTEBufferSizeInRequestsChroma; @@ -4632,7 +4630,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.WritebackLumaVTaps[k], mode_lib->vba.WritebackChromaHTaps[k], mode_lib->vba.WritebackChromaVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; + (unsigned int)mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; } else { locals->WritebackDelay[i][k] = 0.0; } @@ -4649,7 +4647,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.WritebackLumaVTaps[m], mode_lib->vba.WritebackChromaHTaps[m], mode_lib->vba.WritebackChromaVTaps[m], - mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]); + (unsigned int)mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]); } } } @@ -4714,7 +4712,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.RequiredDISPCLK[i][j], mode_lib->vba.PixelClock[k], mode_lib->vba.ProjectedDCFCLKDeepSleep[0][0], - mode_lib->vba.DSCDelayPerState[i][k], + (unsigned int)mode_lib->vba.DSCDelayPerState[i][k], mode_lib->vba.NoOfDPP[i][j][k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k], @@ -4724,14 +4722,14 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DPPCLKDelayCNVCFormater, mode_lib->vba.DPPCLKDelayCNVCCursor, mode_lib->vba.DISPCLKDelaySubtotal, - mode_lib->vba.SwathWidthYPerState[i][j][k] - / mode_lib->vba.HRatio[k], + (unsigned int)(mode_lib->vba.SwathWidthYPerState[i][j][k] + / mode_lib->vba.HRatio[k]), mode_lib->vba.OutputFormat[k], mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k], mode_lib->vba.HTotal[k], mode_lib->vba.MaxInterDCNTileRepeaters, - mode_lib->vba.MaximumVStartup[0][0][k], + (unsigned int)mode_lib->vba.MaximumVStartup[0][0][k], mode_lib->vba.GPUVMMaxPageTableLevels, mode_lib->vba.GPUVMEnable, mode_lib->vba.DynamicMetadataEnable[k], @@ -4741,9 +4739,9 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.UrgentLatencyPixelDataOnly, mode_lib->vba.ExtraLatency, mode_lib->vba.TimeCalc, - mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k], - mode_lib->vba.MetaRowBytes[0][0][k], - mode_lib->vba.DPTEBytesPerRow[0][0][k], + (unsigned int)mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k], + (unsigned int)mode_lib->vba.MetaRowBytes[0][0][k], + (unsigned int)mode_lib->vba.DPTEBytesPerRow[0][0][k], mode_lib->vba.PrefetchLinesY[0][0][k], mode_lib->vba.SwathWidthYPerState[i][j][k], mode_lib->vba.BytePerPixelInDETY[k], @@ -4852,16 +4850,16 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.PrefetchBW[k]); } for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { - mode_lib->vba.ImmediateFlipBytes[k] = 0.0; + mode_lib->vba.ImmediateFlipBytes[k] = (unsigned int)0.0; if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { mode_lib->vba.ImmediateFlipBytes[k] = - mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k] + (unsigned int)(mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k] + mode_lib->vba.MetaRowBytes[0][0][k] - + mode_lib->vba.DPTEBytesPerRow[0][0][k]; + + mode_lib->vba.DPTEBytesPerRow[0][0][k]); } } - mode_lib->vba.TotImmediateFlipBytes = 0.0; + mode_lib->vba.TotImmediateFlipBytes = 0; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { @@ -4887,8 +4885,8 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.VRatio[k], mode_lib->vba.Tno_bw[k], mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k], - mode_lib->vba.MetaRowBytes[0][0][k], - mode_lib->vba.DPTEBytesPerRow[0][0][k], + (unsigned int)mode_lib->vba.MetaRowBytes[0][0][k], + (unsigned int)mode_lib->vba.DPTEBytesPerRow[0][0][k], mode_lib->vba.DCCEnable[k], mode_lib->vba.dpte_row_height[k], mode_lib->vba.meta_row_height[k], @@ -5018,7 +5016,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } /*Mode Support, Voltage State and SOC Configuration*/ - for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { + for (idx = mode_lib->vba.soc.num_states; idx >= 0; idx--) { for (j = 0; j < 2; j++) { enum dm_validation_status status = DML_VALIDATION_OK; @@ -5026,21 +5024,21 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l status = DML_FAIL_SCALE_RATIO_TAP; } else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) { status = DML_FAIL_SOURCE_PIXEL_FORMAT; - } else if (locals->ViewportSizeSupport[i][0] != true) { + } else if (locals->ViewportSizeSupport[idx][0] != true) { status = DML_FAIL_VIEWPORT_SIZE; - } else if (locals->DIOSupport[i] != true) { + } else if (locals->DIOSupport[idx] != true) { status = DML_FAIL_DIO_SUPPORT; - } else if (locals->NotEnoughDSCUnits[i] != false) { + } else if (locals->NotEnoughDSCUnits[idx] != false) { status = DML_FAIL_NOT_ENOUGH_DSC; - } else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) { + } else if (locals->DSCCLKRequiredMoreThanSupported[idx] != false) { status = DML_FAIL_DSC_CLK_REQUIRED; - } else if (locals->UrgentLatencySupport[i][j] != true) { + } else if (locals->UrgentLatencySupport[idx][j] != true) { status = DML_FAIL_URGENT_LATENCY; - } else if (locals->ROBSupport[i][0] != true) { + } else if (locals->ROBSupport[idx][0] != true) { status = DML_FAIL_REORDERING_BUFFER; - } else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) { + } else if (locals->DISPCLK_DPPCLK_Support[idx][j] != true) { status = DML_FAIL_DISPCLK_DPPCLK; - } else if (locals->TotalAvailablePipesSupport[i][j] != true) { + } else if (locals->TotalAvailablePipesSupport[idx][j] != true) { status = DML_FAIL_TOTAL_AVAILABLE_PIPES; } else if (mode_lib->vba.NumberOfOTGSupport != true) { status = DML_FAIL_NUM_OTG; @@ -5054,24 +5052,24 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l status = DML_FAIL_CURSOR_SUPPORT; } else if (mode_lib->vba.PitchSupport != true) { status = DML_FAIL_PITCH_SUPPORT; - } else if (locals->PrefetchSupported[i][j] != true) { + } else if (locals->PrefetchSupported[idx][j] != true) { status = DML_FAIL_PREFETCH_SUPPORT; - } else if (locals->TotalVerticalActiveBandwidthSupport[i][0] != true) { + } else if (locals->TotalVerticalActiveBandwidthSupport[idx][0] != true) { status = DML_FAIL_TOTAL_V_ACTIVE_BW; - } else if (locals->VRatioInPrefetchSupported[i][j] != true) { + } else if (locals->VRatioInPrefetchSupported[idx][j] != true) { status = DML_FAIL_V_RATIO_PREFETCH; - } else if (locals->PTEBufferSizeNotExceeded[i][j] != true) { + } else if (locals->PTEBufferSizeNotExceeded[idx][j] != true) { status = DML_FAIL_PTE_BUFFER_SIZE; } else if (mode_lib->vba.NonsupportedDSCInputBPC != false) { status = DML_FAIL_DSC_INPUT_BPC; } if (status == DML_VALIDATION_OK) { - locals->ModeSupport[i][j] = true; + locals->ModeSupport[idx][j] = true; } else { - locals->ModeSupport[i][j] = false; + locals->ModeSupport[idx][j] = false; } - locals->ValidationStatus[i] = status; + locals->ValidationStatus[idx] = status; } } { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c index 95b0a3501880..a6b8b5ddd945 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c @@ -350,7 +350,7 @@ static unsigned int dscceComputeDelay( pixelsPerClock = 1; //initial transmit delay as per PPS - initalXmitDelay = dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock); + initalXmitDelay = (unsigned int)dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock); //compute ssm delay if (bpc == 8) @@ -510,13 +510,13 @@ static bool CalculateDelayAfterScaler( } if (ScalerEnabled) - DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCL; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotal + DPPCLKDelaySCL); else - DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly); - DPPCycles = DPPCycles + DPPCLKDelayCNVCFormater + NumberOfCursors * DPPCLKDelayCNVCCursor; + DPPCycles = (unsigned int)(DPPCycles + DPPCLKDelayCNVCFormater + NumberOfCursors * DPPCLKDelayCNVCCursor); - DISPCLKCycles = DISPCLKDelaySubtotal; + DISPCLKCycles = (unsigned int)DISPCLKDelaySubtotal; if (DPPCLK == 0.0 || DISPCLK == 0.0) return true; @@ -609,7 +609,7 @@ static bool CalculatePrefetchSchedule( double TimeForFetchingRowInVBlank = 0; double LinesToRequestPrefetchPixelData = 0; - *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1); + *VUpdateOffsetPix = (unsigned int)dml_ceil(HTotal / 4.0, 1); TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK); *VUpdateWidthPix = (14.0 / DCFCLKDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime) * PixelClock; @@ -889,14 +889,13 @@ static double CalculatePrefetchSourceLines( if (!mode_lib->vba.IgnoreViewportPositioning) { - *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; + *MaxNumSwath = (unsigned int)(dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0); if (*VInitPreFill > 1.0) - MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight; + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill - 2) % SwathHeight); else - MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) - % SwathHeight; - MaxPartialSwath = dml_max(1U, MaxPartialSwath); + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill + SwathHeight - 2) % SwathHeight); + MaxPartialSwath = (unsigned int)dml_max(1U, MaxPartialSwath); } else { @@ -904,13 +903,12 @@ static double CalculatePrefetchSourceLines( dml_print( "WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n"); - *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); + *MaxNumSwath = (unsigned int)dml_ceil(*VInitPreFill / SwathHeight, 1); if (*VInitPreFill > 1.0) - MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight; + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill - 1) % SwathHeight); else - MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 1) - % SwathHeight; + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill + SwathHeight - 1) % SwathHeight); } return *MaxNumSwath * SwathHeight + MaxPartialSwath; @@ -960,34 +958,34 @@ static unsigned int CalculateVMAndRowBytes( MetaRequestHeight = 8 * BlockHeight256Bytes; MetaRequestWidth = 8 * BlockWidth256Bytes; if (ScanDirection == dm_horz) { - *meta_row_height = MetaRequestHeight; - MetaSurfWidth = dml_ceil((double) SwathWidth - 1, MetaRequestWidth) - + MetaRequestWidth; - *MetaRowByte = MetaSurfWidth * MetaRequestHeight * BytePerPixel / 256.0; + *meta_row_height = (unsigned int)MetaRequestHeight; + MetaSurfWidth = (unsigned int)(dml_ceil((double) SwathWidth - 1, MetaRequestWidth) + + MetaRequestWidth); + *MetaRowByte = (unsigned int)(MetaSurfWidth * MetaRequestHeight * BytePerPixel / 256.0); } else { - *meta_row_height = MetaRequestWidth; - MetaSurfHeight = dml_ceil((double) SwathWidth - 1, MetaRequestHeight) - + MetaRequestHeight; - *MetaRowByte = MetaSurfHeight * MetaRequestWidth * BytePerPixel / 256.0; + *meta_row_height = (unsigned int)MetaRequestWidth; + MetaSurfHeight = (unsigned int)(dml_ceil((double) SwathWidth - 1, MetaRequestHeight) + + MetaRequestHeight); + *MetaRowByte = (unsigned int)(MetaSurfHeight * MetaRequestWidth * BytePerPixel / 256.0); } if (ScanDirection == dm_horz) { - DCCMetaSurfaceBytes = DCCMetaPitch + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel - / 256; + / 256); } else { - DCCMetaSurfaceBytes = DCCMetaPitch + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil( (double) ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel - / 256; + / 256); } if (GPUVMEnable == true) { - MetaPTEBytesFrame = (dml_ceil( + MetaPTEBytesFrame = (unsigned int)((dml_ceil( (double) (DCCMetaSurfaceBytes - VMMPageSize) / (8 * VMMPageSize), - 1) + 1) * 64; + 1) + 1) * 64); MPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 1); } else { MetaPTEBytesFrame = 0; @@ -1021,7 +1019,7 @@ static unsigned int CalculateVMAndRowBytes( if (GPUVMEnable == true && mode_lib->vba.GPUVMMaxPageTableLevels > 1) { if (ScanDirection == dm_horz) { DPDE0BytesFrame = - 64 + (unsigned int)(64 * (dml_ceil( ((Pitch * (dml_ceil( @@ -1033,10 +1031,10 @@ static unsigned int CalculateVMAndRowBytes( - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } else { DPDE0BytesFrame = - 64 + (unsigned int)(64 * (dml_ceil( ((Pitch * (dml_ceil( @@ -1048,7 +1046,7 @@ static unsigned int CalculateVMAndRowBytes( - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } ExtraDPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 2); } else { @@ -1068,7 +1066,7 @@ static unsigned int CalculateVMAndRowBytes( if (SurfaceTiling == dm_sw_linear) { PixelPTEReqHeight = 1; - PixelPTEReqWidth = 8.0 * VMMPageSize / BytePerPixel; + PixelPTEReqWidth = (unsigned int)8.0 * VMMPageSize / BytePerPixel; PTERequestSize = 64; FractionOfPTEReturnDrop = 0; } else if (MacroTileSizeBytes == 4096) { @@ -1097,7 +1095,7 @@ static unsigned int CalculateVMAndRowBytes( EffectivePDEProcessingBufIn64KBReqs = PDEProcessingBufIn64KBReqs; if (SurfaceTiling == dm_sw_linear) { - *dpte_row_height = + *dpte_row_height = (unsigned int)( dml_min( 128, 1 @@ -1110,21 +1108,21 @@ static unsigned int CalculateVMAndRowBytes( * 65536.0 / BytePerPixel) / Pitch), - 1)); + 1))); *PixelPTEBytesPerRow = PTERequestSize - * (dml_ceil( + * (unsigned int)(dml_ceil( (double) (Pitch * *dpte_row_height - 1) / PixelPTEReqWidth, 1) + 1); } else if (ScanDirection == dm_horz) { *dpte_row_height = PixelPTEReqHeight; *PixelPTEBytesPerRow = PTERequestSize - * (dml_ceil(((double) SwathWidth - 1) / PixelPTEReqWidth, 1) + * (unsigned int)(dml_ceil(((double) SwathWidth - 1) / PixelPTEReqWidth, 1) + 1); } else { - *dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth); + *dpte_row_height = (unsigned int)dml_min(PixelPTEReqWidth, *MacroTileWidth); *PixelPTEBytesPerRow = PTERequestSize - * (dml_ceil( + * (unsigned int)(dml_ceil( ((double) SwathWidth - 1) / PixelPTEReqHeight, 1) + 1); @@ -1576,10 +1574,10 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP / mode_lib->vba.PixelClock[k]) / mode_lib->vba.VRatio[k]; if (mode_lib->vba.BytePerPixelDETC[k] > 0) { - mode_lib->vba.LinesInDETC[k] = mode_lib->vba.DETBufferSizeC[k] + mode_lib->vba.LinesInDETC[k] = (unsigned int)(mode_lib->vba.DETBufferSizeC[k] / mode_lib->vba.BytePerPixelDETC[k] - / (mode_lib->vba.SwathWidthY[k] / 2); - mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = dml_floor( + / (mode_lib->vba.SwathWidthY[k] / 2)); + mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = (unsigned int)dml_floor( mode_lib->vba.LinesInDETC[k], mode_lib->vba.SwathHeightC[k]); mode_lib->vba.FullDETBufferingTimeC[k] = @@ -1848,7 +1846,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], bpp, - dml_ceil( + (unsigned int)dml_ceil( (double) mode_lib->vba.HActive[k] / mode_lib->vba.NumberOfDSCSlices[k], 1), @@ -1862,18 +1860,18 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP * (dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], bpp, - dml_ceil( + (unsigned int)dml_ceil( (double) mode_lib->vba.HActive[k] / mode_lib->vba.NumberOfDSCSlices[k], 1), - slices / 2.0, + (unsigned int)(slices / 2.0), mode_lib->vba.OutputFormat[k]) + dscComputeDelay( mode_lib->vba.OutputFormat[k])); } - mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[k] + mode_lib->vba.DSCDelay[k] = (unsigned int)(mode_lib->vba.DSCDelay[k] * mode_lib->vba.PixelClock[k] - / mode_lib->vba.PixelClockBackEnd[k]; + / mode_lib->vba.PixelClockBackEnd[k]); } else { mode_lib->vba.DSCDelay[k] = 0; } @@ -1897,8 +1895,8 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP Calculate256BBlockSizes( mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), - dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2), &mode_lib->vba.BlockHeight256BytesY[k], &mode_lib->vba.BlockHeight256BytesC[k], &mode_lib->vba.BlockWidth256BytesY[k], @@ -1910,11 +1908,11 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.BlockWidth256BytesY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k], mode_lib->vba.ViewportHeight[k], - mode_lib->vba.SwathWidthY[k], + (unsigned int)mode_lib->vba.SwathWidthY[k], mode_lib->vba.GPUVMEnable, mode_lib->vba.VMMPageSize, mode_lib->vba.PTEBufferSizeInRequestsLuma, @@ -1950,13 +1948,13 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.BlockWidth256BytesC[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil( + (unsigned int)dml_ceil( mode_lib->vba.BytePerPixelDETC[k], 2), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k] / 2, mode_lib->vba.ViewportHeight[k] / 2, - mode_lib->vba.SwathWidthY[k] / 2, + (unsigned int)mode_lib->vba.SwathWidthY[k] / 2, mode_lib->vba.GPUVMEnable, mode_lib->vba.VMMPageSize, mode_lib->vba.PTEBufferSizeInRequestsLuma, @@ -2026,7 +2024,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.WritebackLumaVTaps[k], mode_lib->vba.WritebackChromaHTaps[k], mode_lib->vba.WritebackChromaVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k]) + (unsigned int)mode_lib->vba.WritebackDestinationWidth[k]) / mode_lib->vba.DISPCLK; } else mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0; @@ -2045,7 +2043,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.WritebackLumaVTaps[j], mode_lib->vba.WritebackChromaHTaps[j], mode_lib->vba.WritebackChromaVTaps[j], - mode_lib->vba.WritebackDestinationWidth[j]) + (unsigned int)mode_lib->vba.WritebackDestinationWidth[j]) / mode_lib->vba.DISPCLK); } } @@ -2060,7 +2058,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.VStartupLines = 13; for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { - mode_lib->vba.MaxVStartupLines[k] = + mode_lib->vba.MaxVStartupLines[k] = (unsigned int)( mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] - dml_max( 1.0, @@ -2068,11 +2066,11 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), - 1)); + 1))); } for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) - mode_lib->vba.MaximumMaxVStartupLines = dml_max( + mode_lib->vba.MaximumMaxVStartupLines = (unsigned int)dml_max( mode_lib->vba.MaximumMaxVStartupLines, mode_lib->vba.MaxVStartupLines[k]); @@ -2129,8 +2127,8 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k], mode_lib->vba.DPPCLK[k], mode_lib->vba.DISPCLK, mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelay[k], mode_lib->vba.DPPPerPlane[k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k], mode_lib->vba.DPPCLKDelaySubtotal, mode_lib->vba.DPPCLKDelaySCL, mode_lib->vba.DPPCLKDelaySCLLBOnly, mode_lib->vba.DPPCLKDelayCNVCFormater, mode_lib->vba.DPPCLKDelayCNVCCursor, mode_lib->vba.DISPCLKDelaySubtotal, - mode_lib->vba.SwathWidthY[k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k], - mode_lib->vba.SwathWidthSingleDPPY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.BytePerPixelDETC[k], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], mode_lib->vba.Interlace[k], + (unsigned int)(mode_lib->vba.SwathWidthY[k] / mode_lib->vba.HRatio[k]), mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k], + (unsigned int)mode_lib->vba.SwathWidthSingleDPPY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.BytePerPixelDETC[k], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], mode_lib->vba.Interlace[k], mode_lib->vba.ProgressiveToInterlaceUnitInOPP, &mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]); mode_lib->vba.ErrorResult[k] = @@ -2146,7 +2144,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP - mode_lib->vba.VActive[k], mode_lib->vba.HTotal[k], mode_lib->vba.MaxInterDCNTileRepeaters, - dml_min( + (unsigned int)dml_min( mode_lib->vba.VStartupLines, mode_lib->vba.MaxVStartupLines[k]), mode_lib->vba.GPUVMMaxPageTableLevels, @@ -2158,11 +2156,11 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.UrgentLatencyPixelDataOnly, mode_lib->vba.UrgentExtraLatency, mode_lib->vba.TCalc, - mode_lib->vba.PDEAndMetaPTEBytesFrame[k], - mode_lib->vba.MetaRowByte[k], - mode_lib->vba.PixelPTEBytesPerRow[k], + (unsigned int)mode_lib->vba.PDEAndMetaPTEBytesFrame[k], + (unsigned int)mode_lib->vba.MetaRowByte[k], + (unsigned int)mode_lib->vba.PixelPTEBytesPerRow[k], mode_lib->vba.PrefetchSourceLinesY[k], - mode_lib->vba.SwathWidthY[k], + (unsigned int)mode_lib->vba.SwathWidthY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.VInitPreFillY[k], mode_lib->vba.MaxNumSwathY[k], @@ -2192,7 +2190,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP &mode_lib->vba.VReadyOffsetPix[k]); if (mode_lib->vba.BlendingAndTiming[k] == k) { - mode_lib->vba.VStartup[k] = dml_min( + mode_lib->vba.VStartup[k] = (unsigned int)dml_min( mode_lib->vba.VStartupLines, mode_lib->vba.MaxVStartupLines[k]); if (mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata @@ -2201,7 +2199,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata; } } else { - mode_lib->vba.VStartup[k] = + mode_lib->vba.VStartup[k] = (unsigned int) dml_min( mode_lib->vba.VStartupLines, mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]); @@ -2288,10 +2286,10 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP ImmediateFlipBytes[k] = 0; if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { - ImmediateFlipBytes[k] = + ImmediateFlipBytes[k] = (unsigned int)( mode_lib->vba.PDEAndMetaPTEBytesFrame[k] + mode_lib->vba.MetaRowByte[k] - + mode_lib->vba.PixelPTEBytesPerRow[k]; + + mode_lib->vba.PixelPTEBytesPerRow[k]); } } mode_lib->vba.TotImmediateFlipBytes = 0; @@ -2319,8 +2317,8 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.VRatio[k], mode_lib->vba.Tno_bw[k], mode_lib->vba.PDEAndMetaPTEBytesFrame[k], - mode_lib->vba.MetaRowByte[k], - mode_lib->vba.PixelPTEBytesPerRow[k], + (unsigned int)mode_lib->vba.MetaRowByte[k], + (unsigned int)mode_lib->vba.PixelPTEBytesPerRow[k], mode_lib->vba.DCCEnable[k], mode_lib->vba.dpte_row_height[k], mode_lib->vba.meta_row_height[k], @@ -2444,7 +2442,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP double MaxDETBufferingTimeY; double ActiveDRAMClockChangeLatencyMarginY; - mode_lib->vba.LBLatencyHidingSourceLinesY = + mode_lib->vba.LBLatencyHidingSourceLinesY = (unsigned int)( dml_min( mode_lib->vba.MaxLineBufferLines, (unsigned int) dml_floor( @@ -2454,9 +2452,9 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP / dml_max( mode_lib->vba.HRatio[k], 1.0)), - 1)) - (mode_lib->vba.vtaps[k] - 1); + 1)) -(mode_lib->vba.vtaps[k] - 1)); - mode_lib->vba.LBLatencyHidingSourceLinesC = + mode_lib->vba.LBLatencyHidingSourceLinesC = (unsigned int)( dml_min( mode_lib->vba.MaxLineBufferLines, (unsigned int) dml_floor( @@ -2469,7 +2467,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP / 2, 1.0)), 1)) - - (mode_lib->vba.VTAPsChroma[k] - 1); + -(mode_lib->vba.VTAPsChroma[k] - 1)); EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY / mode_lib->vba.VRatio[k] @@ -2631,7 +2629,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP && mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) { SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = - mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]; + (float)mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]; } } @@ -2765,14 +2763,14 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { if (mode_lib->vba.BlendingAndTiming[k] == k) { - unsigned int Margin = (mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k]) - * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]; + unsigned int Margin = (unsigned int)((mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k]) + * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]); if (FirstMainPlane) { VStartupMargin = Margin; FirstMainPlane = false; } else - VStartupMargin = dml_min(VStartupMargin, Margin); + VStartupMargin = (unsigned int)dml_min(VStartupMargin, Margin); } if (mode_lib->vba.UseMaximumVStartup) { @@ -2970,26 +2968,26 @@ static void dml20v2_DisplayPipeConfiguration(struct display_mode_lib *mode_lib) if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) { - mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY; - mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC; + mode_lib->vba.SwathHeightY[k] = (unsigned int)MaximumSwathHeightY; + mode_lib->vba.SwathHeightC[k] = (unsigned int)MaximumSwathHeightC; } else { - mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY; - mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC; + mode_lib->vba.SwathHeightY[k] = (unsigned int)MinimumSwathHeightY; + mode_lib->vba.SwathHeightC[k] = (unsigned int)MinimumSwathHeightC; } if (mode_lib->vba.SwathHeightC[k] == 0) { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024; - mode_lib->vba.DETBufferSizeC[k] = 0; + mode_lib->vba.DETBufferSizeY[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] * 1024); + mode_lib->vba.DETBufferSizeC[k] = 0; } else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 / 2; - mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 / 2; + mode_lib->vba.DETBufferSizeY[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 / 2); + mode_lib->vba.DETBufferSizeC[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 / 2); } else { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 * 2 / 3; - mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 / 3; + mode_lib->vba.DETBufferSizeY[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 * 2 / 3); + mode_lib->vba.DETBufferSizeC[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 / 3); } } } @@ -3309,9 +3307,9 @@ static unsigned int TruncToValidBPP( if (DecimalBPP < 6) return BPP_INVALID; else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1.0 / 16.0) - return 1.5 * DSCInputBitPerComponent - 1.0 / 16.0; + return (unsigned int)(1.5 * DSCInputBitPerComponent - 1.0 / 16.0); else - return dml_floor(16 * DecimalBPP, 1) / 16.0; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16.0); } else { if (DecimalBPP < 6 || DesiredBPP < 6 @@ -3319,7 +3317,7 @@ static unsigned int TruncToValidBPP( || DecimalBPP < DesiredBPP) { return BPP_INVALID; } else { - return DesiredBPP; + return (unsigned int)DesiredBPP; } } } else if (Format == dm_n422) { @@ -3327,9 +3325,9 @@ static unsigned int TruncToValidBPP( if (DecimalBPP < 7) return BPP_INVALID; else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1.0 / 16.0) - return 2 * DSCInputBitPerComponent - 1.0 / 16.0; + return (unsigned int)(2 * DSCInputBitPerComponent - 1.0 / 16.0); else - return dml_floor(16 * DecimalBPP, 1) / 16.0; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16.0); } else { if (DecimalBPP < 7 || DesiredBPP < 7 @@ -3337,7 +3335,7 @@ static unsigned int TruncToValidBPP( || DecimalBPP < DesiredBPP) { return BPP_INVALID; } else { - return DesiredBPP; + return (unsigned int)DesiredBPP; } } } else { @@ -3345,9 +3343,9 @@ static unsigned int TruncToValidBPP( if (DecimalBPP < 8) return BPP_INVALID; else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1.0 / 16.0) - return 3 * DSCInputBitPerComponent - 1.0 / 16.0; + return (unsigned int)(3 * DSCInputBitPerComponent - 1.0 / 16.0); else - return dml_floor(16 * DecimalBPP, 1) / 16.0; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16.0); } else { if (DecimalBPP < 8 || DesiredBPP < 8 @@ -3355,7 +3353,7 @@ static unsigned int TruncToValidBPP( || DecimalBPP < DesiredBPP) { return BPP_INVALID; } else { - return DesiredBPP; + return (unsigned int)DesiredBPP; } } } @@ -3396,8 +3394,8 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode { struct vba_vars_st *locals = &mode_lib->vba; - int i; - unsigned int j, k, m; + int idx; + unsigned int i, j, k, m; /*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/ @@ -3860,8 +3858,8 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode Calculate256BBlockSizes( mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(locals->BytePerPixelInDETY[k], 1.0), - dml_ceil(locals->BytePerPixelInDETC[k], 2.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETY[k], 1.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETC[k], 2.0), &locals->Read256BlockHeightY[k], &locals->Read256BlockHeightC[k], &locals->Read256BlockWidthY[k], @@ -4045,7 +4043,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode locals->DISPCLK_DPPCLK_Support[i][j] = false; } } - locals->TotalNumberOfActiveDPP[i][j] = 0.0; + locals->TotalNumberOfActiveDPP[i][j] = (unsigned int)0.0; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; if (j == 1) { @@ -4100,7 +4098,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode || mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) locals->DISPCLK_DPPCLK_Support[i][j] = false; } - locals->TotalNumberOfActiveDPP[i][j] = 0.0; + locals->TotalNumberOfActiveDPP[i][j] = (unsigned int)0.0; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; } @@ -4361,17 +4359,17 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode || locals->RequiresDSC[i][k] == false) { mode_lib->vba.slices = 0; } else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) { - mode_lib->vba.slices = dml_ceil( + mode_lib->vba.slices = (unsigned int)dml_ceil( mode_lib->vba.PixelClockBackEnd[k] / 400.0, 4.0); } else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) { - mode_lib->vba.slices = 8.0; + mode_lib->vba.slices = (unsigned int)8.0; } else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) { - mode_lib->vba.slices = 4.0; + mode_lib->vba.slices = (unsigned int)4.0; } else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) { - mode_lib->vba.slices = 2.0; + mode_lib->vba.slices = (unsigned int)2.0; } else { - mode_lib->vba.slices = 1.0; + mode_lib->vba.slices = (unsigned int)1.0; } if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE || locals->OutputBppPerState[i][k] == BPP_INVALID) { @@ -4385,7 +4383,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], mode_lib->vba.bpp, - dml_ceil( + (unsigned int)dml_ceil( mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), @@ -4398,7 +4396,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode 2.0 * (dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], mode_lib->vba.bpp, - dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), + (unsigned int)dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), mode_lib->vba.slices / 2, mode_lib->vba.OutputFormat[k]) + dscComputeDelay(mode_lib->vba.OutputFormat[k])); @@ -4424,9 +4422,9 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode for (j = 0; j < 2; j++) { for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) - locals->SwathWidthYPerState[i][j][k] = dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k])); + locals->SwathWidthYPerState[i][j][k] = (unsigned int)dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k])); else - locals->SwathWidthYPerState[i][j][k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k]; + locals->SwathWidthYPerState[i][j][k] = (unsigned int)locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k]; locals->SwathWidthGranularityY = 256 / dml_ceil(locals->BytePerPixelInDETY[k], 1) / locals->MaxSwathHeightY[k]; locals->RoundedUpMaxSwathSizeBytesY = (dml_ceil(locals->SwathWidthYPerState[i][j][k] - 1, locals->SwathWidthGranularityY) + locals->SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k]; @@ -4446,11 +4444,11 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode } if (locals->RoundedUpMaxSwathSizeBytesY + locals->RoundedUpMaxSwathSizeBytesC <= locals->DETBufferSizeInKByte[0] * 1024.0 / 2) { - locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k]; - locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k]; + locals->SwathHeightYPerState[i][j][k] = (unsigned int)locals->MaxSwathHeightY[k]; + locals->SwathHeightCPerState[i][j][k] = (unsigned int)locals->MaxSwathHeightC[k]; } else { - locals->SwathHeightYPerState[i][j][k] = locals->MinSwathHeightY[k]; - locals->SwathHeightCPerState[i][j][k] = locals->MinSwathHeightC[k]; + locals->SwathHeightYPerState[i][j][k] = (unsigned int)locals->MinSwathHeightY[k]; + locals->SwathHeightCPerState[i][j][k] = (unsigned int)locals->MinSwathHeightC[k]; } if (locals->BytePerPixelInDETC[k] == 0) { @@ -4465,16 +4463,16 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2); } - locals->EffectiveLBLatencyHidingSourceLinesLuma = dml_min(locals->MaxLineBufferLines, + locals->EffectiveLBLatencyHidingSourceLinesLuma = (unsigned int)dml_min(locals->MaxLineBufferLines, dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k] / dml_max(locals->HRatio[k], 1)), 1)) - (locals->vtaps[k] - 1); - locals->EffectiveLBLatencyHidingSourceLinesChroma = dml_min(locals->MaxLineBufferLines, + locals->EffectiveLBLatencyHidingSourceLinesChroma = (unsigned int)dml_min(locals->MaxLineBufferLines, dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k] / 2 / dml_max(locals->HRatio[k] / 2, 1)), 1)) - (locals->VTAPsChroma[k] - 1); - locals->EffectiveDETLBLinesLuma = dml_floor(locals->LinesInDETLuma + dml_min( + locals->EffectiveDETLBLinesLuma = (unsigned int)dml_floor(locals->LinesInDETLuma + dml_min( locals->LinesInDETLuma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETY[k] * locals->PSCL_FACTOR[k] / locals->ReturnBWPerState[i][0], locals->EffectiveLBLatencyHidingSourceLinesLuma), @@ -4630,7 +4628,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.Read256BlockWidthY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k], mode_lib->vba.ViewportHeight[k], @@ -4669,17 +4667,17 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.Read256BlockWidthY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0), mode_lib->vba.SourceScan[k], - mode_lib->vba.ViewportWidth[k] / 2.0, - mode_lib->vba.ViewportHeight[k] / 2.0, - mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0, + (unsigned int)(mode_lib->vba.ViewportWidth[k] / 2.0), + (unsigned int)(mode_lib->vba.ViewportHeight[k] / 2.0), + (unsigned int)(mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0), mode_lib->vba.GPUVMEnable, mode_lib->vba.VMMPageSize, mode_lib->vba.PTEBufferSizeInRequestsLuma, mode_lib->vba.PDEProcessingBufIn64KBReqs, mode_lib->vba.PitchC[k], - 0.0, + (unsigned int)0.0, &mode_lib->vba.MacroTileWidthC[k], &mode_lib->vba.MetaRowBytesC, &mode_lib->vba.DPTEBytesPerRowC, @@ -4698,8 +4696,8 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode &mode_lib->vba.MaxNumSwC[k]); } else { mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = 0.0; - mode_lib->vba.MetaRowBytesC = 0.0; - mode_lib->vba.DPTEBytesPerRowC = 0.0; + mode_lib->vba.MetaRowBytesC = (unsigned int)0.0; + mode_lib->vba.DPTEBytesPerRowC = (unsigned int)0.0; locals->PrefetchLinesC[0][0][k] = 0.0; locals->PTEBufferSizeNotExceededC[i][j][k] = true; locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma + mode_lib->vba.PTEBufferSizeInRequestsChroma; @@ -4755,7 +4753,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.WritebackLumaVTaps[k], mode_lib->vba.WritebackChromaHTaps[k], mode_lib->vba.WritebackChromaVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; + (unsigned int)mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; } else { locals->WritebackDelay[i][k] = 0.0; } @@ -4772,7 +4770,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.WritebackLumaVTaps[m], mode_lib->vba.WritebackChromaHTaps[m], mode_lib->vba.WritebackChromaVTaps[m], - mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]); + (unsigned int)mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]); } } } @@ -4833,10 +4831,10 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode CalculateDelayAfterScaler(mode_lib, mode_lib->vba.ReturnBWPerState[i][0], mode_lib->vba.ReadBandwidthLuma[k], mode_lib->vba.ReadBandwidthChroma[k], mode_lib->vba.MaxTotalVActiveRDBandwidth, mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k], - mode_lib->vba.RequiredDPPCLK[i][j][k], mode_lib->vba.RequiredDISPCLK[i][j], mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelayPerState[i][k], mode_lib->vba.NoOfDPP[i][j][k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k], + (unsigned int)mode_lib->vba.RequiredDPPCLK[i][j][k], (unsigned int)mode_lib->vba.RequiredDISPCLK[i][j], mode_lib->vba.PixelClock[k], (unsigned int)mode_lib->vba.DSCDelayPerState[i][k], mode_lib->vba.NoOfDPP[i][j][k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k], mode_lib->vba.DPPCLKDelaySubtotal, mode_lib->vba.DPPCLKDelaySCL, mode_lib->vba.DPPCLKDelaySCLLBOnly, mode_lib->vba.DPPCLKDelayCNVCFormater, mode_lib->vba.DPPCLKDelayCNVCCursor, mode_lib->vba.DISPCLKDelaySubtotal, - mode_lib->vba.SwathWidthYPerState[i][j][k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k], - mode_lib->vba.SwathWidthYSingleDPP[k], mode_lib->vba.BytePerPixelInDETY[k], mode_lib->vba.BytePerPixelInDETC[k], mode_lib->vba.SwathHeightYThisState[k], mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.Interlace[k], mode_lib->vba.ProgressiveToInterlaceUnitInOPP, + (unsigned int)(mode_lib->vba.SwathWidthYPerState[i][j][k] / mode_lib->vba.HRatio[k]), mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k], + (unsigned int)mode_lib->vba.SwathWidthYSingleDPP[k], mode_lib->vba.BytePerPixelInDETY[k], mode_lib->vba.BytePerPixelInDETC[k], mode_lib->vba.SwathHeightYThisState[k], mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.Interlace[k], mode_lib->vba.ProgressiveToInterlaceUnitInOPP, &mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]); mode_lib->vba.IsErrorResult[i][j][k] = @@ -4852,7 +4850,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode - mode_lib->vba.VActive[k], mode_lib->vba.HTotal[k], mode_lib->vba.MaxInterDCNTileRepeaters, - mode_lib->vba.MaximumVStartup[0][0][k], + (unsigned int)mode_lib->vba.MaximumVStartup[0][0][k], mode_lib->vba.GPUVMMaxPageTableLevels, mode_lib->vba.GPUVMEnable, mode_lib->vba.DynamicMetadataEnable[k], @@ -4862,9 +4860,9 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.UrgentLatencyPixelDataOnly, mode_lib->vba.ExtraLatency, mode_lib->vba.TimeCalc, - mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k], - mode_lib->vba.MetaRowBytes[0][0][k], - mode_lib->vba.DPTEBytesPerRow[0][0][k], + (unsigned int)mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k], + (unsigned int)mode_lib->vba.MetaRowBytes[0][0][k], + (unsigned int)mode_lib->vba.DPTEBytesPerRow[0][0][k], mode_lib->vba.PrefetchLinesY[0][0][k], mode_lib->vba.SwathWidthYPerState[i][j][k], mode_lib->vba.BytePerPixelInDETY[k], @@ -4972,16 +4970,16 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.PrefetchBW[k]); } for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { - mode_lib->vba.ImmediateFlipBytes[k] = 0.0; + mode_lib->vba.ImmediateFlipBytes[k] = (unsigned int)0.0; if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { - mode_lib->vba.ImmediateFlipBytes[k] = + mode_lib->vba.ImmediateFlipBytes[k] = (unsigned int)( mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k] + mode_lib->vba.MetaRowBytes[0][0][k] - + mode_lib->vba.DPTEBytesPerRow[0][0][k]; + + mode_lib->vba.DPTEBytesPerRow[0][0][k]); } } - mode_lib->vba.TotImmediateFlipBytes = 0.0; + mode_lib->vba.TotImmediateFlipBytes = 0; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { @@ -5007,8 +5005,8 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.VRatio[k], mode_lib->vba.Tno_bw[k], mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k], - mode_lib->vba.MetaRowBytes[0][0][k], - mode_lib->vba.DPTEBytesPerRow[0][0][k], + (unsigned int)mode_lib->vba.MetaRowBytes[0][0][k], + (unsigned int)mode_lib->vba.DPTEBytesPerRow[0][0][k], mode_lib->vba.DCCEnable[k], mode_lib->vba.dpte_row_height[k], mode_lib->vba.meta_row_height[k], @@ -5135,7 +5133,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode } /*Mode Support, Voltage State and SOC Configuration*/ - for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { + for (idx = mode_lib->vba.soc.num_states; idx >= 0; idx--) { for (j = 0; j < 2; j++) { enum dm_validation_status status = DML_VALIDATION_OK; @@ -5143,21 +5141,21 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode status = DML_FAIL_SCALE_RATIO_TAP; } else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) { status = DML_FAIL_SOURCE_PIXEL_FORMAT; - } else if (locals->ViewportSizeSupport[i][0] != true) { + } else if (locals->ViewportSizeSupport[idx][0] != true) { status = DML_FAIL_VIEWPORT_SIZE; - } else if (locals->DIOSupport[i] != true) { + } else if (locals->DIOSupport[idx] != true) { status = DML_FAIL_DIO_SUPPORT; - } else if (locals->NotEnoughDSCUnits[i] != false) { + } else if (locals->NotEnoughDSCUnits[idx] != false) { status = DML_FAIL_NOT_ENOUGH_DSC; - } else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) { + } else if (locals->DSCCLKRequiredMoreThanSupported[idx] != false) { status = DML_FAIL_DSC_CLK_REQUIRED; - } else if (locals->UrgentLatencySupport[i][j] != true) { + } else if (locals->UrgentLatencySupport[idx][j] != true) { status = DML_FAIL_URGENT_LATENCY; - } else if (locals->ROBSupport[i][0] != true) { + } else if (locals->ROBSupport[idx][0] != true) { status = DML_FAIL_REORDERING_BUFFER; - } else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) { + } else if (locals->DISPCLK_DPPCLK_Support[idx][j] != true) { status = DML_FAIL_DISPCLK_DPPCLK; - } else if (locals->TotalAvailablePipesSupport[i][j] != true) { + } else if (locals->TotalAvailablePipesSupport[idx][j] != true) { status = DML_FAIL_TOTAL_AVAILABLE_PIPES; } else if (mode_lib->vba.NumberOfOTGSupport != true) { status = DML_FAIL_NUM_OTG; @@ -5171,24 +5169,24 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode status = DML_FAIL_CURSOR_SUPPORT; } else if (mode_lib->vba.PitchSupport != true) { status = DML_FAIL_PITCH_SUPPORT; - } else if (locals->PrefetchSupported[i][j] != true) { + } else if (locals->PrefetchSupported[idx][j] != true) { status = DML_FAIL_PREFETCH_SUPPORT; - } else if (locals->TotalVerticalActiveBandwidthSupport[i][0] != true) { + } else if (locals->TotalVerticalActiveBandwidthSupport[idx][0] != true) { status = DML_FAIL_TOTAL_V_ACTIVE_BW; - } else if (locals->VRatioInPrefetchSupported[i][j] != true) { + } else if (locals->VRatioInPrefetchSupported[idx][j] != true) { status = DML_FAIL_V_RATIO_PREFETCH; - } else if (locals->PTEBufferSizeNotExceeded[i][j] != true) { + } else if (locals->PTEBufferSizeNotExceeded[idx][j] != true) { status = DML_FAIL_PTE_BUFFER_SIZE; } else if (mode_lib->vba.NonsupportedDSCInputBPC != false) { status = DML_FAIL_DSC_INPUT_BPC; } if (status == DML_VALIDATION_OK) { - locals->ModeSupport[i][j] = true; + locals->ModeSupport[idx][j] = true; } else { - locals->ModeSupport[i][j] = false; + locals->ModeSupport[idx][j] = false; } - locals->ValidationStatus[i] = status; + locals->ValidationStatus[idx] = status; } } { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c index 591d9618bdc0..59edfcf27d91 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c @@ -196,13 +196,13 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), - 1) - 3; + rq_regs->rq_regs_l.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), + 1) - 3); if (rq_param->yuv420) { extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), - 1) - 3; + rq_regs->rq_regs_c.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), + 1) - 3); } rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); @@ -222,11 +222,11 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, if (rq_param->yuv420) { if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma } else { - detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), - 256, - 0) / 64.0; // 2/3 to chroma + detile_buf_plane1_addr = (unsigned int)(dml_round_to_multiple((unsigned int)((2.0 * detile_buf_size_in_bytes) / 3.0), + 256, + 0) / 64.0); // 2/3 to chroma } } rq_regs->plane1_base_address = detile_buf_plane1_addr; @@ -451,8 +451,8 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, // "/2" is like square root // blk is vertical biased if (tiling != dm_sw_linear) - log2_blk_height = log2_blk256_height - + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); + log2_blk_height = (unsigned int)(log2_blk256_height + + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1)); else log2_blk_height = 0; // blk height of 1 @@ -601,7 +601,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, if (surf_linear) { unsigned int dpte_row_height; - log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries + log2_dpte_row_height_linear = (unsigned int)dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries / bytes_per_element, dpte_buf_in_pte_reqs * dpte_req_width) @@ -671,7 +671,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, // the upper bound for the dpte groups per row is as follows. - rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, + rq_dlg_param->dpte_groups_per_row_ub = (unsigned int)dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); } @@ -1018,11 +1018,11 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, if (dout->dsc_enable) { double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dispclk_delay_subtotal += dsc_delay; + dispclk_delay_subtotal += (unsigned int)dsc_delay; } - pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz - + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; + pixel_rate_delay_subtotal = (unsigned int)(dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz + + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz); vstartup_start = dst->vstartup_start; if (interlaced) { @@ -1043,7 +1043,7 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, // TODO: Where is this coming from? if (interlaced) - vstartup_start = vstartup_start / 2; + vstartup_start = (unsigned int)(vstartup_start / 2); // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? if (vstartup_start >= min_vblank) { @@ -1062,8 +1062,8 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, min_vblank); } - dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_x_after_scaler = (unsigned int)get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_y_after_scaler = (unsigned int)get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); dml_print("DML_DLG: %s: pixel_rate_delay_subtotal = %d\n", @@ -1376,57 +1376,57 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, // Assignment to register structures disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line - disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + disp_dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); // in terms of refclk ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); - disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); + disp_dlg_regs->dst_y_prefetch = (unsigned int)(dst_y_prefetch * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int)(dst_y_per_vm_vblank * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_row_vblank = (unsigned int)(dst_y_per_row_vblank * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_vm_flip = (unsigned int)(dst_y_per_vm_flip * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_row_flip = (unsigned int)(dst_y_per_row_flip * dml_pow(2, 2)); - disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); - disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); + disp_dlg_regs->vratio_prefetch = (unsigned int)(vratio_pre_l * dml_pow(2, 19)); + disp_dlg_regs->vratio_prefetch_c = (unsigned int)(vratio_pre_c * dml_pow(2, 19)); disp_dlg_regs->refcyc_per_pte_group_vblank_l = - (unsigned int) (dst_y_per_row_vblank * (double) htotal - * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); + (unsigned int)(dst_y_per_row_vblank * (double) htotal + * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); if (dual_plane) { - disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank - * (double) htotal * ref_freq_to_pix_freq - / (double) dpte_groups_per_row_ub_c); + disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int)(dst_y_per_row_vblank + * (double) htotal * ref_freq_to_pix_freq + / (double) dpte_groups_per_row_ub_c); ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13)); } disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = - (unsigned int) (dst_y_per_row_vblank * (double) htotal - * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); + (unsigned int)(dst_y_per_row_vblank * (double) htotal + * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now - disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal - * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; - disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal - * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; + disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int)((dst_y_per_row_flip * htotal + * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l); + disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int)((dst_y_per_row_flip * htotal + * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l); if (dual_plane) { - disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip - * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; - disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip - * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; + disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int)((dst_y_per_row_flip + * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c); + disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int)((dst_y_per_row_flip + * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c); } - disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l - / (double) vratio_l * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int)(((double) dpte_row_height_l + / (double) vratio_l * dml_pow(2, 2))); ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); if (dual_plane) { - disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c - / (double) vratio_c * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int)(((double) dpte_row_height_c + / (double) vratio_c * dml_pow(2, 2))); if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n", __func__, @@ -1435,38 +1435,38 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, } } - disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l - / (double) vratio_l * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int)(((double) meta_row_height_l + / (double) vratio_l * dml_pow(2, 2))); ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now - disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l - / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq - / (double) dpte_groups_per_row_ub_l); + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(((double) dpte_row_height_l + / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq + / (double) dpte_groups_per_row_ub_l)); if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l - / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq - / (double) meta_chunks_per_row_ub_l); + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1); + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(((double) meta_row_height_l + / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq + / (double) meta_chunks_per_row_ub_l)); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (dual_plane) { - disp_dlg_regs->refcyc_per_pte_group_nom_c = - (unsigned int) ((double) dpte_row_height_c / (double) vratio_c - * (double) htotal * ref_freq_to_pix_freq - / (double) dpte_groups_per_row_ub_c); + disp_dlg_regs->refcyc_per_pte_group_nom_c = + (unsigned int)(((double) dpte_row_height_c / (double) vratio_c + * (double) htotal * ref_freq_to_pix_freq + / (double) dpte_groups_per_row_ub_c)); if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1); // TODO: Is this the right calculation? Does htotal need to be halved? - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = - (unsigned int) ((double) meta_row_height_c / (double) vratio_c - * (double) htotal * ref_freq_to_pix_freq - / (double) meta_chunks_per_row_ub_c); + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = + (unsigned int)(((double) meta_row_height_c / (double) vratio_c + * (double) htotal * ref_freq_to_pix_freq + / (double) meta_chunks_per_row_ub_c)); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1); } disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, @@ -1490,22 +1490,22 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off - disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l - * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l - * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c - * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c - * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int)(refcyc_per_req_delivery_pre_l + * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int)(refcyc_per_req_delivery_l + * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int)(refcyc_per_req_delivery_pre_c + * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int)(refcyc_per_req_delivery_c + * dml_pow(2, 10)); disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = - (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 - * dml_pow(2, 10)); + (unsigned int)(refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int)(refcyc_per_req_delivery_cur0 + * dml_pow(2, 10)); disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = - (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 - * dml_pow(2, 10)); + (unsigned int)(refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int)(refcyc_per_req_delivery_cur1 + * dml_pow(2, 10)); disp_ttu_regs->qos_level_low_wm = 0; ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal @@ -1520,7 +1520,7 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs->qos_ramp_disable_cur0 = 0; - disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + disp_ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); print__ttu_regs_st(mode_lib, disp_ttu_regs); @@ -1557,7 +1557,7 @@ void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes); - dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, + dlg_sys_param.total_flip_bytes = (unsigned int)get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); @@ -1620,7 +1620,7 @@ static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, cur_req_size = 256; } - cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); + cur_req_width = (unsigned int)((double) cur_req_size / ((double) cur_bit_per_pixel / 8.0)); cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width; cur_req_per_width = cur_width_ub / (double) cur_req_width; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c index d4dddc9d535a..1d2e477da032 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c @@ -196,13 +196,13 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), - 1) - 3; + rq_regs->rq_regs_l.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), + 1) - 3); if (rq_param->yuv420) { extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), - 1) - 3; + rq_regs->rq_regs_c.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), + 1) - 3); } rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); @@ -222,11 +222,11 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, if (rq_param->yuv420) { if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma } else { - detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), - 256, - 0) / 64.0; // 2/3 to chroma + detile_buf_plane1_addr = (unsigned int)(dml_round_to_multiple((unsigned int)((2.0 * detile_buf_size_in_bytes) / 3.0), + 256, + 0) / 64.0); // 2/3 to chroma } } rq_regs->plane1_base_address = detile_buf_plane1_addr; @@ -451,8 +451,8 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, // "/2" is like square root // blk is vertical biased if (tiling != dm_sw_linear) - log2_blk_height = log2_blk256_height - + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); + log2_blk_height = (unsigned int)(log2_blk256_height + + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1)); else log2_blk_height = 0; // blk height of 1 @@ -601,7 +601,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, if (surf_linear) { unsigned int dpte_row_height; - log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries + log2_dpte_row_height_linear = (unsigned int)dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries / bytes_per_element, dpte_buf_in_pte_reqs * dpte_req_width) @@ -671,7 +671,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, // the upper bound for the dpte groups per row is as follows. - rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, + rq_dlg_param->dpte_groups_per_row_ub = (unsigned int)dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); } @@ -1019,11 +1019,11 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, if (dout->dsc_enable) { double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dispclk_delay_subtotal += dsc_delay; + dispclk_delay_subtotal += (unsigned int)dsc_delay; } - pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz - + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; + pixel_rate_delay_subtotal = (unsigned int)(dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz + + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz); vstartup_start = dst->vstartup_start; if (interlaced) { @@ -1044,7 +1044,7 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, // TODO: Where is this coming from? if (interlaced) - vstartup_start = vstartup_start / 2; + vstartup_start = (unsigned int)(vstartup_start / 2); // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? if (vstartup_start >= min_vblank) { @@ -1063,8 +1063,8 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, min_vblank); } - dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_x_after_scaler = (unsigned int)get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_y_after_scaler = (unsigned int)get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); dml_print("DML_DLG: %s: pixel_rate_delay_subtotal = %d\n", @@ -1377,57 +1377,57 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, // Assignment to register structures disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line - disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + disp_dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); // in terms of refclk ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); - disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); + disp_dlg_regs->dst_y_prefetch = (unsigned int)(dst_y_prefetch * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int)(dst_y_per_vm_vblank * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_row_vblank = (unsigned int)(dst_y_per_row_vblank * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_vm_flip = (unsigned int)(dst_y_per_vm_flip * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_row_flip = (unsigned int)(dst_y_per_row_flip * dml_pow(2, 2)); - disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); - disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); + disp_dlg_regs->vratio_prefetch = (unsigned int)(vratio_pre_l * dml_pow(2, 19)); + disp_dlg_regs->vratio_prefetch_c = (unsigned int)(vratio_pre_c * dml_pow(2, 19)); disp_dlg_regs->refcyc_per_pte_group_vblank_l = - (unsigned int) (dst_y_per_row_vblank * (double) htotal - * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); + (unsigned int)(dst_y_per_row_vblank * (double) htotal + * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); if (dual_plane) { - disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank - * (double) htotal * ref_freq_to_pix_freq - / (double) dpte_groups_per_row_ub_c); + disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int)(dst_y_per_row_vblank + * (double) htotal * ref_freq_to_pix_freq + / (double) dpte_groups_per_row_ub_c); ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13)); } disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = - (unsigned int) (dst_y_per_row_vblank * (double) htotal - * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); + (unsigned int)(dst_y_per_row_vblank * (double) htotal + * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now - disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal - * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; - disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal - * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; + disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int)((dst_y_per_row_flip * htotal + * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l); + disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int)((dst_y_per_row_flip * htotal + * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l); if (dual_plane) { - disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip - * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; - disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip - * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; + disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int)((dst_y_per_row_flip + * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c); + disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int)((dst_y_per_row_flip + * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c); } - disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l - / (double) vratio_l * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int)(((double) dpte_row_height_l + / (double) vratio_l * dml_pow(2, 2))); ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); if (dual_plane) { - disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c - / (double) vratio_c * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int)(((double) dpte_row_height_c + / (double) vratio_c * dml_pow(2, 2))); if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n", __func__, @@ -1436,38 +1436,38 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, } } - disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l - / (double) vratio_l * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int)(((double) meta_row_height_l + / (double) vratio_l * dml_pow(2, 2))); ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now - disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l - / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq - / (double) dpte_groups_per_row_ub_l); + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(((double) dpte_row_height_l + / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq + / (double) dpte_groups_per_row_ub_l)); if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l - / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq - / (double) meta_chunks_per_row_ub_l); + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1); + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(((double) meta_row_height_l + / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq + / (double) meta_chunks_per_row_ub_l)); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (dual_plane) { - disp_dlg_regs->refcyc_per_pte_group_nom_c = - (unsigned int) ((double) dpte_row_height_c / (double) vratio_c - * (double) htotal * ref_freq_to_pix_freq - / (double) dpte_groups_per_row_ub_c); + disp_dlg_regs->refcyc_per_pte_group_nom_c = + (unsigned int)(((double) dpte_row_height_c / (double) vratio_c + * (double) htotal * ref_freq_to_pix_freq + / (double) dpte_groups_per_row_ub_c)); if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1); // TODO: Is this the right calculation? Does htotal need to be halved? - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = - (unsigned int) ((double) meta_row_height_c / (double) vratio_c - * (double) htotal * ref_freq_to_pix_freq - / (double) meta_chunks_per_row_ub_c); + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = + (unsigned int)(((double) meta_row_height_c / (double) vratio_c + * (double) htotal * ref_freq_to_pix_freq + / (double) meta_chunks_per_row_ub_c)); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1); } disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, @@ -1491,22 +1491,22 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off - disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l - * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l - * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c - * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c - * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int)(refcyc_per_req_delivery_pre_l + * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int)(refcyc_per_req_delivery_l + * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int)(refcyc_per_req_delivery_pre_c + * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int)(refcyc_per_req_delivery_c + * dml_pow(2, 10)); disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = - (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 - * dml_pow(2, 10)); + (unsigned int)(refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int)(refcyc_per_req_delivery_cur0 + * dml_pow(2, 10)); disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = - (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 - * dml_pow(2, 10)); + (unsigned int)(refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int)(refcyc_per_req_delivery_cur1 + * dml_pow(2, 10)); disp_ttu_regs->qos_level_low_wm = 0; ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal @@ -1521,7 +1521,7 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs->qos_ramp_disable_cur0 = 0; - disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + disp_ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); print__ttu_regs_st(mode_lib, disp_ttu_regs); @@ -1558,7 +1558,7 @@ void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes); - dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, + dlg_sys_param.total_flip_bytes = (unsigned int)get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); @@ -1621,7 +1621,7 @@ static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, cur_req_size = 256; } - cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); + cur_req_width = (unsigned int)((double) cur_req_size / ((double) cur_bit_per_pixel / 8.0)); cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width; cur_req_per_width = cur_width_ub / (double) cur_req_width; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index 11570a0c9427..df23ced2ff5a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -521,7 +521,7 @@ static unsigned int dscceComputeDelay( pixelsPerClock = 1; //initial transmit delay as per PPS - initalXmitDelay = dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock); + initalXmitDelay = (unsigned int)dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock); //compute ssm delay if (bpc == 8) @@ -729,22 +729,22 @@ static bool CalculatePrefetchSchedule( } if (myPipe->ScalerEnabled) - DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCL; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotal + DPPCLKDelaySCL); else - DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly); - DPPCycles = DPPCycles + DPPCLKDelayCNVCFormater + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor; + DPPCycles = (unsigned int)(DPPCycles + DPPCLKDelayCNVCFormater + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor); - DISPCLKCycles = DISPCLKDelaySubtotal; + DISPCLKCycles = (unsigned int)(DISPCLKDelaySubtotal); if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0) return true; - *DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK - + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay; + *DSTXAfterScaler = (unsigned int)(DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay); - if (myPipe->DPPPerPlane > 1) - *DSTXAfterScaler = *DSTXAfterScaler + ScalerRecoutWidth; + if (myPipe->DPPPerPlane > 1) + *DSTXAfterScaler = (unsigned int)(*DSTXAfterScaler + ScalerRecoutWidth); if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && ProgressiveToInterlaceUnitInOPP)) *DSTYAfterScaler = 1; @@ -755,7 +755,7 @@ static bool CalculatePrefetchSchedule( *DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1); *DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * myPipe->HTotal)); - *VUpdateOffsetPix = dml_ceil(myPipe->HTotal / 4.0, 1); + *VUpdateOffsetPix = (unsigned int)(dml_ceil(myPipe->HTotal / 4.0, 1)); TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / myPipe->DPPCLK + 3.0 / myPipe->DISPCLK); *VUpdateWidthPix = (14.0 / myPipe->DCFCLKDeepSleep + 12.0 / myPipe->DPPCLK + TotalRepeaterDelayTime) * myPipe->PixelClock; @@ -783,11 +783,11 @@ static bool CalculatePrefetchSchedule( Tdmsks = Tdmsks / 2; if (VStartup * LineTime < Tsetup + TWait + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) { - MyError = true; - *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (Tsetup + TWait - + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) / LineTime; + MyError = (unsigned int)(true); + *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (unsigned int)((Tsetup + TWait + + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) / LineTime); } else - *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = 0.0; + *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (unsigned int)(0U); } else Tdm = 0; @@ -808,13 +808,13 @@ static bool CalculatePrefetchSchedule( Tsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime; if (myPipe->SourceScan == dm_horz) { - *swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockWidth256BytesY) + myPipe->BlockWidth256BytesY; + *swath_width_luma_ub = (unsigned int)(dml_ceil(SwathWidthY - 1, myPipe->BlockWidth256BytesY) + myPipe->BlockWidth256BytesY); if (myPipe->BlockWidth256BytesC > 0) - *swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockWidth256BytesC) + myPipe->BlockWidth256BytesC; + *swath_width_chroma_ub = (unsigned int)(dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockWidth256BytesC) + myPipe->BlockWidth256BytesC); } else { - *swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockHeight256BytesY) + myPipe->BlockHeight256BytesY; + *swath_width_luma_ub = (unsigned int)(dml_ceil(SwathWidthY - 1, myPipe->BlockHeight256BytesY) + myPipe->BlockHeight256BytesY); if (myPipe->BlockHeight256BytesC > 0) - *swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockHeight256BytesC) + myPipe->BlockHeight256BytesC; + *swath_width_chroma_ub = (unsigned int)(dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockHeight256BytesC) + myPipe->BlockHeight256BytesC); } prefetch_bw_oto = (PrefetchSourceLinesY * *swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) + PrefetchSourceLinesC * *swath_width_chroma_ub * dml_ceil(BytePerPixelDETC, 2)) / Tsw_oto; @@ -1228,14 +1228,14 @@ static double CalculatePrefetchSourceLines( if (!mode_lib->vba.IgnoreViewportPositioning) { - *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; + *MaxNumSwath = (unsigned int)(dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight; else MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight; - MaxPartialSwath = dml_max(1U, MaxPartialSwath); + MaxPartialSwath = (unsigned int)(dml_max(1U, MaxPartialSwath)); } else { @@ -1243,7 +1243,7 @@ static double CalculatePrefetchSourceLines( dml_print( "WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n"); - *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); + *MaxNumSwath = (unsigned int)(dml_ceil(*VInitPreFill / SwathHeight, 1)); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight; @@ -1252,7 +1252,7 @@ static double CalculatePrefetchSourceLines( % SwathHeight; } - return *MaxNumSwath * SwathHeight + MaxPartialSwath; + return (unsigned int)(*MaxNumSwath * SwathHeight + MaxPartialSwath); } static unsigned int CalculateVMAndRowBytes( @@ -1307,34 +1307,34 @@ static unsigned int CalculateVMAndRowBytes( *MetaRequestHeight = 8 * BlockHeight256Bytes; *MetaRequestWidth = 8 * BlockWidth256Bytes; if (ScanDirection == dm_horz) { - *meta_row_height = *MetaRequestHeight; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) - + *MetaRequestWidth; - *MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0; + *meta_row_height = (unsigned int)(*MetaRequestHeight); + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) + + *MetaRequestWidth); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0); } else { - *meta_row_height = *MetaRequestWidth; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) - + *MetaRequestHeight; - *MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0; + *meta_row_height = (unsigned int)(*MetaRequestWidth); + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) + + *MetaRequestHeight); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0); } if (ScanDirection == dm_horz) { - DCCMetaSurfaceBytes = DCCMetaPitch + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel - / 256; + / 256); } else { - DCCMetaSurfaceBytes = DCCMetaPitch + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil( (double) ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel - / 256; + / 256); } if (GPUVMEnable == true) { - *MetaPTEBytesFrame = (dml_ceil( + *MetaPTEBytesFrame = (unsigned int)((dml_ceil( (double) (DCCMetaSurfaceBytes - VMMPageSize) / (8 * VMMPageSize), - 1) + 1) * 64; + 1) + 1) * 64); MPDEBytesFrame = 128 * ((mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) - 2); } else { *MetaPTEBytesFrame = 0; @@ -1367,9 +1367,9 @@ static unsigned int CalculateVMAndRowBytes( if (GPUVMEnable == true && (mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) > 2) { if (ScanDirection == dm_horz) { - *DPDE0BytesFrame = 64 * (dml_ceil(((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1); + *DPDE0BytesFrame = (unsigned int)(64 * (dml_ceil(((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1)); } else { - *DPDE0BytesFrame = 64 * (dml_ceil(((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1); + *DPDE0BytesFrame = (unsigned int)(64 * (dml_ceil(((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1)); } ExtraDPDEBytesFrame = 128 * ((mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) - 3); } else { @@ -1390,7 +1390,7 @@ static unsigned int CalculateVMAndRowBytes( if (SurfaceTiling == dm_sw_linear) { PixelPTEReqHeightPTEs = 1; *PixelPTEReqHeight = 1; - *PixelPTEReqWidth = 8.0 * VMMPageSize / BytePerPixel; + *PixelPTEReqWidth = (unsigned int)(8.0 * VMMPageSize / BytePerPixel); *PTERequestSize = 64; FractionOfPTEReturnDrop = 0; } else if (MacroTileSizeBytes == 4096) { @@ -1417,20 +1417,20 @@ static unsigned int CalculateVMAndRowBytes( } if (SurfaceTiling == dm_sw_linear) { - *dpte_row_height = dml_min(128, + *dpte_row_height = (unsigned int)dml_min(128, 1 << (unsigned int) dml_floor( dml_log2( (double) PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); - *dpte_row_width_ub = (dml_ceil((double) (Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_width_ub = (unsigned int)((dml_ceil((double) (Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else if (ScanDirection == dm_horz) { *dpte_row_height = *PixelPTEReqHeight; - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_width_ub = (unsigned int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else { - *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth); - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight; + *dpte_row_height = (unsigned int)(dml_min(*PixelPTEReqWidth, *MacroTileWidth)); + *dpte_row_width_ub = (unsigned int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize; } if (*PixelPTEBytesPerRow * (1 - FractionOfPTEReturnDrop) @@ -1805,7 +1805,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], bpp, - dml_ceil( + (unsigned int)dml_ceil( (double) mode_lib->vba.HActive[k] / mode_lib->vba.NumberOfDSCSlices[k], 1), @@ -1819,18 +1819,18 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman * (dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], bpp, - dml_ceil( + (unsigned int)dml_ceil( (double) mode_lib->vba.HActive[k] / mode_lib->vba.NumberOfDSCSlices[k], 1), - slices / 2.0, + (unsigned int)(slices / 2.0), mode_lib->vba.OutputFormat[k]) + dscComputeDelay( mode_lib->vba.OutputFormat[k])); } - locals->DSCDelay[k] = locals->DSCDelay[k] + locals->DSCDelay[k] = (unsigned int)(locals->DSCDelay[k] * mode_lib->vba.PixelClock[k] - / mode_lib->vba.PixelClockBackEnd[k]; + / mode_lib->vba.PixelClockBackEnd[k]); } else { locals->DSCDelay[k] = 0; } @@ -1856,8 +1856,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman Calculate256BBlockSizes( mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(locals->BytePerPixelDETY[k], 1), - dml_ceil(locals->BytePerPixelDETC[k], 2), + (unsigned int)dml_ceil(locals->BytePerPixelDETY[k], 1), + (unsigned int)dml_ceil(locals->BytePerPixelDETC[k], 2), &locals->BlockHeight256BytesY[k], &locals->BlockHeight256BytesC[k], &locals->BlockWidth256BytesY[k], @@ -1886,13 +1886,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman locals->BlockWidth256BytesC[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil( + (unsigned int)dml_ceil( locals->BytePerPixelDETC[k], 2), mode_lib->vba.SourceScan[k], - mode_lib->vba.ViewportWidth[k] / 2, + (unsigned int)(mode_lib->vba.ViewportWidth[k] / 2), mode_lib->vba.ViewportHeight[k] / 2, - locals->SwathWidthY[k] / 2, + (unsigned int)(locals->SwathWidthY[k] / 2), mode_lib->vba.GPUVMEnable, mode_lib->vba.HostVMEnable, mode_lib->vba.HostVMMaxPageTableLevels, @@ -1945,11 +1945,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman locals->BlockWidth256BytesY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(locals->BytePerPixelDETY[k], 1), + (unsigned int)dml_ceil(locals->BytePerPixelDETY[k], 1), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k], mode_lib->vba.ViewportHeight[k], - locals->SwathWidthY[k], + (unsigned int)locals->SwathWidthY[k], mode_lib->vba.GPUVMEnable, mode_lib->vba.HostVMEnable, mode_lib->vba.HostVMMaxPageTableLevels, @@ -2053,7 +2053,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.WritebackLumaVTaps[k], mode_lib->vba.WritebackChromaHTaps[k], mode_lib->vba.WritebackChromaVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k]) + (unsigned int)mode_lib->vba.WritebackDestinationWidth[k]) / mode_lib->vba.DISPCLK; } else locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0; @@ -2072,7 +2072,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.WritebackLumaVTaps[j], mode_lib->vba.WritebackChromaHTaps[j], mode_lib->vba.WritebackChromaVTaps[j], - mode_lib->vba.WritebackDestinationWidth[j]) + (unsigned int)mode_lib->vba.WritebackDestinationWidth[j]) / mode_lib->vba.DISPCLK); } } @@ -2087,11 +2087,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.VStartupLines = 13; for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { - locals->MaxVStartupLines[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] - dml_max(1.0, dml_ceil(locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1)); + locals->MaxVStartupLines[k] = (unsigned int)(mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] - dml_max(1.0, dml_ceil(locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1))); } for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) - locals->MaximumMaxVStartupLines = dml_max(locals->MaximumMaxVStartupLines, locals->MaxVStartupLines[k]); + locals->MaximumMaxVStartupLines = (unsigned int)(dml_max(locals->MaximumMaxVStartupLines, locals->MaxVStartupLines[k])); // We don't really care to iterate between the various prefetch modes //mode_lib->vba.PrefetchERROR = CalculateMinAndMaxPrefetchMode(mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, &mode_lib->vba.MinPrefetchMode, &mode_lib->vba.MaxPrefetchMode); @@ -2177,7 +2177,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman / mode_lib->vba.HRatio[k]), mode_lib->vba.OutputFormat[k], mode_lib->vba.MaxInterDCNTileRepeaters, - dml_min(mode_lib->vba.VStartupLines, locals->MaxVStartupLines[k]), + (unsigned int)dml_min(mode_lib->vba.VStartupLines, locals->MaxVStartupLines[k]), locals->MaxVStartupLines[k], mode_lib->vba.GPUVMMaxPageTableLevels, mode_lib->vba.GPUVMEnable, @@ -2189,11 +2189,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.UrgentLatency, mode_lib->vba.UrgentExtraLatency, mode_lib->vba.TCalc, - locals->PDEAndMetaPTEBytesFrame[k], - locals->MetaRowByte[k], - locals->PixelPTEBytesPerRow[k], + (unsigned int)locals->PDEAndMetaPTEBytesFrame[k], + (unsigned int)locals->MetaRowByte[k], + (unsigned int)locals->PixelPTEBytesPerRow[k], locals->PrefetchSourceLinesY[k], - locals->SwathWidthY[k], + (unsigned int)locals->SwathWidthY[k], locals->BytePerPixelDETY[k], locals->VInitPreFillY[k], locals->MaxNumSwathY[k], @@ -2226,7 +2226,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman &mode_lib->vba.VUpdateWidthPix[k], &mode_lib->vba.VReadyOffsetPix[k]); if (mode_lib->vba.BlendingAndTiming[k] == k) { - locals->VStartup[k] = dml_min( + locals->VStartup[k] = (unsigned int)dml_min( mode_lib->vba.VStartupLines, locals->MaxVStartupLines[k]); if (locals->VStartupRequiredWhenNotEnoughTimeForDynamicMetadata @@ -2236,7 +2236,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman } } else { locals->VStartup[k] = - dml_min( + (unsigned int)dml_min( mode_lib->vba.VStartupLines, locals->MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]); } @@ -2256,13 +2256,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.DETBufferSizeInKByte[0], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], - locals->SwathWidthY[k], + (unsigned int)locals->SwathWidthY[k], mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], mode_lib->vba.UrgentLatency, mode_lib->vba.CursorBufferSize, mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1], - dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]), + (unsigned int)dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]), mode_lib->vba.VRatio[k], locals->VRatioPrefetchY[k], locals->VRatioPrefetchC[k], @@ -2333,7 +2333,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.TotImmediateFlipBytes = 0; for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { - mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes + locals->PDEAndMetaPTEBytesFrame[k] + locals->MetaRowByte[k] + locals->PixelPTEBytesPerRow[k]; + mode_lib->vba.TotImmediateFlipBytes = (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + locals->PDEAndMetaPTEBytesFrame[k] + locals->MetaRowByte[k] + locals->PixelPTEBytesPerRow[k]); } for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { CalculateFlipSchedule( @@ -2600,7 +2600,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman locals->BlockHeight256BytesY[k], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SurfaceTiling[k], - locals->BytePerPixelDETY[k], + (unsigned int)locals->BytePerPixelDETY[k], mode_lib->vba.SourceScan[k], &locals->DCCYMaxUncompressedBlock[k], &locals->DCCYMaxCompressedBlock[k], @@ -2722,7 +2722,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.FrameTimeForMinFullDETBufferingTime = (double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]; - locals->BytePerPixelYCriticalPlane = dml_ceil(locals->BytePerPixelDETY[k], 1); + locals->BytePerPixelYCriticalPlane = (unsigned int)(dml_ceil(locals->BytePerPixelDETY[k], 1)); locals->SwathWidthYCriticalPlane = locals->SwathWidthY[k]; locals->LinesToFinishSwathTransferStutterCriticalPlane = mode_lib->vba.SwathHeightY[k] - (locals->LinesInDETY[k] - locals->LinesInDETYRoundedDownToSwath[k]); @@ -2993,11 +2993,11 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib) if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) { - mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY; - mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC; + mode_lib->vba.SwathHeightY[k] = (unsigned int)(MaximumSwathHeightY); + mode_lib->vba.SwathHeightC[k] = (unsigned int)(MaximumSwathHeightC); } else { - mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY; - mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC; + mode_lib->vba.SwathHeightY[k] = (unsigned int)(MinimumSwathHeightY); + mode_lib->vba.SwathHeightC[k] = (unsigned int)(MinimumSwathHeightC); } CalculateDETBufferSize( @@ -3317,9 +3317,9 @@ static unsigned int TruncToValidBPP( if (DecimalBPP < 6) return BPP_INVALID; else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1.0 / 16.0) - return 1.5 * DSCInputBitPerComponent - 1.0 / 16.0; + return (unsigned int)(1.5 * DSCInputBitPerComponent - 1.0 / 16.0); else - return dml_floor(16 * DecimalBPP, 1) / 16.0; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16.0); } else { if (DecimalBPP < 6 || DesiredBPP < 6 @@ -3327,7 +3327,7 @@ static unsigned int TruncToValidBPP( || DecimalBPP < DesiredBPP) { return BPP_INVALID; } else { - return DesiredBPP; + return (unsigned int)(DesiredBPP); } } } else if (Format == dm_n422) { @@ -3335,9 +3335,9 @@ static unsigned int TruncToValidBPP( if (DecimalBPP < 7) return BPP_INVALID; else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1.0 / 16.0) - return 2 * DSCInputBitPerComponent - 1.0 / 16.0; + return (unsigned int)(2 * DSCInputBitPerComponent - 1.0 / 16.0); else - return dml_floor(16 * DecimalBPP, 1) / 16.0; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16.0); } else { if (DecimalBPP < 7 || DesiredBPP < 7 @@ -3345,7 +3345,7 @@ static unsigned int TruncToValidBPP( || DecimalBPP < DesiredBPP) { return BPP_INVALID; } else { - return DesiredBPP; + return (unsigned int)(DesiredBPP); } } } else { @@ -3353,9 +3353,9 @@ static unsigned int TruncToValidBPP( if (DecimalBPP < 8) return BPP_INVALID; else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1.0 / 16.0) - return 3 * DSCInputBitPerComponent - 1.0 / 16.0; + return (unsigned int)(3 * DSCInputBitPerComponent - 1.0 / 16.0); else - return dml_floor(16 * DecimalBPP, 1) / 16.0; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16.0); } else { if (DecimalBPP < 8 || DesiredBPP < 8 @@ -3363,7 +3363,7 @@ static unsigned int TruncToValidBPP( || DecimalBPP < DesiredBPP) { return BPP_INVALID; } else { - return DesiredBPP; + return (unsigned int)(DesiredBPP); } } } @@ -3462,18 +3462,18 @@ static noinline void CalculatePrefetchSchedulePerPlane( mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, &myPipe, - locals->DSCDelayPerState[i][k], + (unsigned int)locals->DSCDelayPerState[i][k], mode_lib->vba.DPPCLKDelaySubtotal, mode_lib->vba.DPPCLKDelaySCL, mode_lib->vba.DPPCLKDelaySCLLBOnly, mode_lib->vba.DPPCLKDelayCNVCFormater, mode_lib->vba.DPPCLKDelayCNVCCursor, mode_lib->vba.DISPCLKDelaySubtotal, - locals->SwathWidthYThisState[k] / mode_lib->vba.HRatio[k], + (unsigned int)(locals->SwathWidthYThisState[k] / mode_lib->vba.HRatio[k]), mode_lib->vba.OutputFormat[k], mode_lib->vba.MaxInterDCNTileRepeaters, - dml_min(mode_lib->vba.MaxVStartup, locals->MaximumVStartup[0][0][k]), - locals->MaximumVStartup[0][0][k], + (unsigned int)dml_min(mode_lib->vba.MaxVStartup, locals->MaximumVStartup[0][0][k]), + (unsigned int)locals->MaximumVStartup[0][0][k], mode_lib->vba.GPUVMMaxPageTableLevels, mode_lib->vba.GPUVMEnable, &myHostVM, @@ -3484,11 +3484,11 @@ static noinline void CalculatePrefetchSchedulePerPlane( mode_lib->vba.UrgentLatency, mode_lib->vba.ExtraLatency, mode_lib->vba.TimeCalc, - locals->PDEAndMetaPTEBytesPerFrame[0][0][k], - locals->MetaRowBytes[0][0][k], - locals->DPTEBytesPerRow[0][0][k], + (unsigned int)locals->PDEAndMetaPTEBytesPerFrame[0][0][k], + (unsigned int)locals->MetaRowBytes[0][0][k], + (unsigned int)locals->DPTEBytesPerRow[0][0][k], locals->PrefetchLinesY[0][0][k], - locals->SwathWidthYThisState[k], + (unsigned int)locals->SwathWidthYThisState[k], locals->BytePerPixelInDETY[k], locals->PrefillY[k], locals->MaxNumSwY[k], @@ -3525,8 +3525,8 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l { struct vba_vars_st *locals = &mode_lib->vba; - int i; - unsigned int j, k, m; + int idx; + unsigned int i, j, k, m; /*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/ @@ -3951,8 +3951,8 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l Calculate256BBlockSizes( mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(locals->BytePerPixelInDETY[k], 1.0), - dml_ceil(locals->BytePerPixelInDETC[k], 2.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETY[k], 1.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETC[k], 2.0), &locals->Read256BlockHeightY[k], &locals->Read256BlockHeightC[k], &locals->Read256BlockWidthY[k], @@ -4141,7 +4141,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l locals->DISPCLK_DPPCLK_Support[i][j] = false; } } - locals->TotalNumberOfActiveDPP[i][j] = 0.0; + locals->TotalNumberOfActiveDPP[i][j] = (unsigned int)(0.0); for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; if (j == 1) { @@ -4196,7 +4196,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l || mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) locals->DISPCLK_DPPCLK_Support[i][j] = false; } - locals->TotalNumberOfActiveDPP[i][j] = 0.0; + locals->TotalNumberOfActiveDPP[i][j] = (unsigned int)(0.0); for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; } @@ -4455,19 +4455,19 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.slices = 0; } else if (locals->RequiresDSC[i][k] == 0 || locals->RequiresDSC[i][k] == false) { - mode_lib->vba.slices = 0; + mode_lib->vba.slices = (unsigned int)(0); } else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) { - mode_lib->vba.slices = dml_ceil( + mode_lib->vba.slices = (unsigned int)dml_ceil( mode_lib->vba.PixelClockBackEnd[k] / 400.0, 4.0); } else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) { - mode_lib->vba.slices = 8.0; + mode_lib->vba.slices = (unsigned int)(8.0); } else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) { - mode_lib->vba.slices = 4.0; + mode_lib->vba.slices = (unsigned int)(4.0); } else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) { - mode_lib->vba.slices = 2.0; + mode_lib->vba.slices = (unsigned int)(2.0); } else { - mode_lib->vba.slices = 1.0; + mode_lib->vba.slices = (unsigned int)(1.0); } if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE || locals->OutputBppPerState[i][k] == BPP_INVALID) { @@ -4481,7 +4481,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], mode_lib->vba.bpp, - dml_ceil( + (unsigned int)dml_ceil( mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), @@ -4494,7 +4494,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 2.0 * (dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], mode_lib->vba.bpp, - dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), + (unsigned int)dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), mode_lib->vba.slices / 2, mode_lib->vba.OutputFormat[k]) + dscComputeDelay(mode_lib->vba.OutputFormat[k])); @@ -4569,13 +4569,13 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } if (mode_lib->vba.RoundedUpMaxSwathSizeBytesY + mode_lib->vba.RoundedUpMaxSwathSizeBytesC <= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) { - locals->SwathHeightYThisState[k] = locals->MaxSwathHeightY[k]; - locals->SwathHeightCThisState[k] = locals->MaxSwathHeightC[k]; + locals->SwathHeightYThisState[k] = (unsigned int)(locals->MaxSwathHeightY[k]); + locals->SwathHeightCThisState[k] = (unsigned int)(locals->MaxSwathHeightC[k]); } else { locals->SwathHeightYThisState[k] = - locals->MinSwathHeightY[k]; + (unsigned int)locals->MinSwathHeightY[k]; locals->SwathHeightCThisState[k] = - locals->MinSwathHeightC[k]; + (unsigned int)locals->MinSwathHeightC[k]; } } @@ -4607,11 +4607,11 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l locals->Read256BlockWidthC[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(locals->BytePerPixelInDETC[k], 2.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETC[k], 2.0), mode_lib->vba.SourceScan[k], - mode_lib->vba.ViewportWidth[k] / 2.0, - mode_lib->vba.ViewportHeight[k] / 2.0, - locals->SwathWidthYThisState[k] / 2.0, + (unsigned int)(mode_lib->vba.ViewportWidth[k] / 2.0), + (unsigned int)(mode_lib->vba.ViewportHeight[k] / 2.0), + (unsigned int)(locals->SwathWidthYThisState[k] / 2.0), mode_lib->vba.GPUVMEnable, mode_lib->vba.HostVMEnable, mode_lib->vba.HostVMMaxPageTableLevels, @@ -4619,7 +4619,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.VMMPageSize, mode_lib->vba.PTEBufferSizeInRequestsChroma, mode_lib->vba.PitchC[k], - 0.0, + 0, &locals->MacroTileWidthC[k], &mode_lib->vba.MetaRowBytesC, &mode_lib->vba.DPTEBytesPerRowC, @@ -4650,8 +4650,8 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma; } else { mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = 0.0; - mode_lib->vba.MetaRowBytesC = 0.0; - mode_lib->vba.DPTEBytesPerRowC = 0.0; + mode_lib->vba.MetaRowBytesC = (unsigned int)(0.0); + mode_lib->vba.DPTEBytesPerRowC = (unsigned int)(0.0); locals->PrefetchLinesC[0][0][k] = 0.0; locals->PTEBufferSizeNotExceededC[i][j][k] = true; locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma + mode_lib->vba.PTEBufferSizeInRequestsChroma; @@ -4663,11 +4663,11 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l locals->Read256BlockWidthY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(locals->BytePerPixelInDETY[k], 1.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETY[k], 1.0), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k], mode_lib->vba.ViewportHeight[k], - locals->SwathWidthYThisState[k], + (unsigned int)locals->SwathWidthYThisState[k], mode_lib->vba.GPUVMEnable, mode_lib->vba.HostVMEnable, mode_lib->vba.HostVMMaxPageTableLevels, @@ -4756,7 +4756,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.WritebackLumaVTaps[k], mode_lib->vba.WritebackChromaHTaps[k], mode_lib->vba.WritebackChromaVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; + (unsigned int)mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; } else { locals->WritebackDelay[i][k] = 0.0; } @@ -4773,7 +4773,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.WritebackLumaVTaps[m], mode_lib->vba.WritebackChromaHTaps[m], mode_lib->vba.WritebackChromaVTaps[m], - mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]); + (unsigned int)mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]); } } } @@ -4824,12 +4824,12 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DETBufferSizeInKByte[0], locals->SwathHeightYThisState[k], locals->SwathHeightCThisState[k], - locals->SwathWidthYThisState[k], + (unsigned int)locals->SwathWidthYThisState[k], mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], mode_lib->vba.UrgentLatency, mode_lib->vba.CursorBufferSize, mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1], - dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]), + (unsigned int)dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]), mode_lib->vba.VRatio[k], locals->VRatioPreY[i][j][k], locals->VRatioPreC[i][j][k], @@ -4922,10 +4922,10 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l + locals->RequiredPrefetchPixelDataBWChroma[i][j][k] * locals->UrgentBurstFactorChromaPre[k] + locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]); } - mode_lib->vba.TotImmediateFlipBytes = 0.0; + mode_lib->vba.TotImmediateFlipBytes = (unsigned int)(0.0); for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { - mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes - + locals->PDEAndMetaPTEBytesPerFrame[0][0][k] + locals->MetaRowBytes[0][0][k] + locals->DPTEBytesPerRow[0][0][k]; + mode_lib->vba.TotImmediateFlipBytes = (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + + locals->PDEAndMetaPTEBytesPerFrame[0][0][k] + locals->MetaRowBytes[0][0][k] + locals->DPTEBytesPerRow[0][0][k]); } for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { @@ -5138,7 +5138,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } /*Mode Support, Voltage State and SOC Configuration*/ - for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { + for (idx = mode_lib->vba.soc.num_states; idx >= 0; idx--) { for (j = 0; j < 2; j++) { enum dm_validation_status status = DML_VALIDATION_OK; @@ -5146,19 +5146,19 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l status = DML_FAIL_SCALE_RATIO_TAP; } else if (!mode_lib->vba.SourceFormatPixelAndScanSupport) { status = DML_FAIL_SOURCE_PIXEL_FORMAT; - } else if (!locals->ViewportSizeSupport[i][0]) { + } else if (!locals->ViewportSizeSupport[idx][0]) { status = DML_FAIL_VIEWPORT_SIZE; - } else if (!locals->DIOSupport[i]) { + } else if (!locals->DIOSupport[idx]) { status = DML_FAIL_DIO_SUPPORT; - } else if (locals->NotEnoughDSCUnits[i]) { + } else if (locals->NotEnoughDSCUnits[idx]) { status = DML_FAIL_NOT_ENOUGH_DSC; - } else if (locals->DSCCLKRequiredMoreThanSupported[i]) { + } else if (locals->DSCCLKRequiredMoreThanSupported[idx]) { status = DML_FAIL_DSC_CLK_REQUIRED; - } else if (!locals->ROBSupport[i][0]) { + } else if (!locals->ROBSupport[idx][0]) { status = DML_FAIL_REORDERING_BUFFER; - } else if (!locals->DISPCLK_DPPCLK_Support[i][j]) { + } else if (!locals->DISPCLK_DPPCLK_Support[idx][j]) { status = DML_FAIL_DISPCLK_DPPCLK; - } else if (!locals->TotalAvailablePipesSupport[i][j]) { + } else if (!locals->TotalAvailablePipesSupport[idx][j]) { status = DML_FAIL_TOTAL_AVAILABLE_PIPES; } else if (!mode_lib->vba.NumberOfOTGSupport) { status = DML_FAIL_NUM_OTG; @@ -5172,27 +5172,27 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l status = DML_FAIL_CURSOR_SUPPORT; } else if (!mode_lib->vba.PitchSupport) { status = DML_FAIL_PITCH_SUPPORT; - } else if (!locals->TotalVerticalActiveBandwidthSupport[i][0]) { + } else if (!locals->TotalVerticalActiveBandwidthSupport[idx][0]) { status = DML_FAIL_TOTAL_V_ACTIVE_BW; - } else if (!locals->PTEBufferSizeNotExceeded[i][j]) { + } else if (!locals->PTEBufferSizeNotExceeded[idx][j]) { status = DML_FAIL_PTE_BUFFER_SIZE; } else if (mode_lib->vba.NonsupportedDSCInputBPC) { status = DML_FAIL_DSC_INPUT_BPC; } else if ((mode_lib->vba.HostVMEnable - && !locals->ImmediateFlipSupportedForState[i][j])) { + && !locals->ImmediateFlipSupportedForState[idx][j])) { status = DML_FAIL_HOST_VM_IMMEDIATE_FLIP; - } else if (!locals->PrefetchSupported[i][j]) { + } else if (!locals->PrefetchSupported[idx][j]) { status = DML_FAIL_PREFETCH_SUPPORT; - } else if (!locals->VRatioInPrefetchSupported[i][j]) { + } else if (!locals->VRatioInPrefetchSupported[idx][j]) { status = DML_FAIL_V_RATIO_PREFETCH; } if (status == DML_VALIDATION_OK) { - locals->ModeSupport[i][j] = true; + locals->ModeSupport[idx][j] = true; } else { - locals->ModeSupport[i][j] = false; + locals->ModeSupport[idx][j] = false; } - locals->ValidationStatus[i] = status; + locals->ValidationStatus[idx] = status; } } { @@ -5373,13 +5373,13 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( for (k = 0; k < NumberOfActivePlanes; ++k) { - mode_lib->vba.LBLatencyHidingSourceLinesY = dml_min((double) MaxLineBufferLines, + mode_lib->vba.LBLatencyHidingSourceLinesY = (unsigned int)(dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - - (vtaps[k] - 1); + - (vtaps[k] - 1)); - mode_lib->vba.LBLatencyHidingSourceLinesC = dml_min((double) MaxLineBufferLines, + mode_lib->vba.LBLatencyHidingSourceLinesC = (unsigned int)(dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / 2 / dml_max(HRatio[k] / 2, 1.0)), 1)) - - (VTAPsChroma[k] - 1); + - (VTAPsChroma[k] - 1)); EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY / VRatio[k] * (HTotal[k] / PixelClock[k]); @@ -5412,12 +5412,12 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( &DETBufferSizeC); LinesInDETY[k] = (double)DETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; - LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); + LinesInDETYRoundedDownToSwath[k] = (unsigned int)(dml_floor(LinesInDETY[k], SwathHeightY[k])); FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k]; if (BytePerPixelDETC[k] > 0) { LinesInDETC = (double)DETBufferSizeC / BytePerPixelDETC[k] / (SwathWidthY[k] / 2.0); - LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]); + LinesInDETCRoundedDownToSwath = (unsigned int)(dml_floor(LinesInDETC, SwathHeightC[k])); FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / (VRatio[k] / 2); } else { @@ -5939,10 +5939,10 @@ static void CalculateMetaAndPTETimes( for (k = 0; k < NumberOfActivePlanes; ++k) { if (DCCEnable[k] == true) { - meta_chunk_width = MetaChunkSize * 1024 * 256 - / dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k]; - min_meta_chunk_width = MinMetaChunkSizeBytes * 256 - / dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k]; + meta_chunk_width = (unsigned int)(MetaChunkSize * 1024 * 256 + / dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k]); + min_meta_chunk_width = (unsigned int)(MinMetaChunkSizeBytes * 256 + / dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k]); meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width; meta_row_remainder = meta_row_width[k] % meta_chunk_width; if (SourceScan[k] == dm_horz) { @@ -5978,7 +5978,7 @@ static void CalculateMetaAndPTETimes( dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k]; } - dpte_groups_per_row_luma_ub = dml_ceil( + dpte_groups_per_row_luma_ub = (unsigned int)dml_ceil( (float) dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1); time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] @@ -6002,7 +6002,7 @@ static void CalculateMetaAndPTETimes( / PTERequestSizeC[k] * PixelPTEReqHeightC[k]; } - dpte_groups_per_row_chroma_ub = dml_ceil( + dpte_groups_per_row_chroma_ub = (unsigned int)dml_ceil( (float) dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1); @@ -6032,34 +6032,32 @@ static void CalculateMetaAndPTETimes( if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) { if (DCCEnable[k] == false) { if (BytePerPixelDETC[k] > 0) { - num_group_per_lower_vm_stage = + num_group_per_lower_vm_stage = (unsigned int)( dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = - dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (unsigned int)dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (GPUVMMaxPageTableLevels == 1) { if (BytePerPixelDETC[k] > 0) { - num_group_per_lower_vm_stage = + num_group_per_lower_vm_stage = (unsigned int)( dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = - dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (unsigned int)dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (BytePerPixelDETC[k] > 0) { - num_group_per_lower_vm_stage = + num_group_per_lower_vm_stage = (unsigned int)( dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = + num_group_per_lower_vm_stage = (unsigned int)( dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)); } } } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c index 8a611b3bec33..189b0157fcf3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c @@ -174,19 +174,19 @@ static void extract_rq_regs( extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor( + rq_regs->rq_regs_l.pte_row_height_linear = (unsigned int)(dml_floor( dml_log2(rq_param->dlg.rq_l.dpte_row_height), - 1) - 3; + 1) - 3); if (rq_param->yuv420) { extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor( + rq_regs->rq_regs_c.pte_row_height_linear = (unsigned int)(dml_floor( dml_log2(rq_param->dlg.rq_c.dpte_row_height), - 1) - 3; + 1) - 3); } - rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); - rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height); + rq_regs->rq_regs_l.swath_height = (unsigned int)dml_log2(rq_param->dlg.rq_l.swath_height); + rq_regs->rq_regs_c.swath_height = (unsigned int)dml_log2(rq_param->dlg.rq_c.swath_height); // FIXME: take the max between luma, chroma chunk size? // okay for now, as we are setting chunk_bytes to 8kb anyways @@ -202,12 +202,12 @@ static void extract_rq_regs( if (rq_param->yuv420) { if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma } else { - detile_buf_plane1_addr = dml_round_to_multiple( + detile_buf_plane1_addr = (unsigned int)(dml_round_to_multiple( (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 256, - 0) / 64.0; // 2/3 to chroma + 0) / 64.0); // 2/3 to chroma } } rq_regs->plane1_base_address = detile_buf_plane1_addr; @@ -443,8 +443,8 @@ static void get_meta_and_pte_attr( // "/2" is like square root // blk is vertical biased if (tiling != dm_sw_linear) - log2_blk_height = log2_blk256_height - + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); + log2_blk_height = (unsigned int)(log2_blk256_height + + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1)); else log2_blk_height = 0; // blk height of 1 @@ -599,7 +599,7 @@ static void get_meta_and_pte_attr( if (surf_linear) { unsigned int dpte_row_height; - log2_dpte_row_height_linear = dml_floor( + log2_dpte_row_height_linear = (unsigned int)dml_floor( dml_log2( dml_min( 64 * 1024 * pde_buf_entries @@ -678,7 +678,7 @@ static void get_meta_and_pte_attr( // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, // the upper bound for the dpte groups per row is as follows. - rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( + rq_dlg_param->dpte_groups_per_row_ub = (unsigned int)dml_ceil( (double) dpte_row_width_ub / dpte_group_width, 1); } @@ -718,18 +718,18 @@ static void get_surf_rq_param( access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed hactive_half = pipe_param->dest.hactive / 2; if (is_chroma) { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width; - src_hactive_half = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_half; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width); + src_hactive_half = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_half); } else { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width; - src_hactive_half = pipe_param->scale_ratio_depth.hscl_ratio * hactive_half; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width); + src_hactive_half = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * hactive_half); } if (access_dir == 0) { - vp_width = dml_min(full_src_vp_width, src_hactive_half); + vp_width = (unsigned int)dml_min(full_src_vp_width, src_hactive_half); dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width); } else { - vp_height = dml_min(full_src_vp_width, src_hactive_half); + vp_height = (unsigned int)dml_min(full_src_vp_width, src_hactive_half); dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height); } @@ -1058,11 +1058,11 @@ static void dml_rq_dlg_get_dlg_params( if (dout->dsc_enable) { double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dispclk_delay_subtotal += dsc_delay; + dispclk_delay_subtotal += (unsigned int)dsc_delay; } - pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz - + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; + pixel_rate_delay_subtotal = (unsigned int)(dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz + + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz); vstartup_start = dst->vstartup_start; if (interlaced) { @@ -1105,8 +1105,8 @@ static void dml_rq_dlg_get_dlg_params( min_vblank); } - dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_x_after_scaler = (unsigned int)get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_y_after_scaler = (unsigned int)get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); dml_print( @@ -1446,7 +1446,7 @@ static void dml_rq_dlg_get_dlg_params( // Assignment to register structures disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line - disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + disp_dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); // in terms of refclk ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); @@ -1506,23 +1506,23 @@ static void dml_rq_dlg_get_dlg_params( * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; } - disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; - disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; - disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); - disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // Clamp to max for now if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)dml_pow(2, 23) - 1; if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)dml_pow(2, 23) - 1; if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)dml_pow(2, 23) - 1; if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)dml_pow(2, 23) - 1; disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2)); ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); @@ -1553,12 +1553,12 @@ static void dml_rq_dlg_get_dlg_params( / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)dml_pow(2, 23) - 1; disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)dml_pow(2, 23) - 1; if (dual_plane) { disp_dlg_regs->refcyc_per_pte_group_nom_c = @@ -1566,7 +1566,7 @@ static void dml_rq_dlg_get_dlg_params( * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c); if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)dml_pow(2, 23) - 1; // TODO: Is this the right calculation? Does htotal need to be halved? disp_dlg_regs->refcyc_per_meta_chunk_nom_c = @@ -1574,7 +1574,7 @@ static void dml_rq_dlg_get_dlg_params( * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_c); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)dml_pow(2, 23) - 1; } disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor( @@ -1628,7 +1628,7 @@ static void dml_rq_dlg_get_dlg_params( disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs->qos_ramp_disable_cur0 = 0; - disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + disp_ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); print__ttu_regs_st(mode_lib, disp_ttu_regs); @@ -1668,7 +1668,7 @@ void dml21_rq_dlg_get_dlg_reg( mode_lib, e2e_pipe_param, num_pipes); - dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes( + dlg_sys_param.total_flip_bytes = (unsigned int)get_total_immediate_flip_bytes( mode_lib, e2e_pipe_param, num_pipes); @@ -1734,7 +1734,7 @@ static void calculate_ttu_cursor( cur_req_size = 256; } - cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); + cur_req_width = (unsigned int)((double) cur_req_size / ((double) cur_bit_per_pixel / 8.0)); cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width; cur_req_per_width = cur_width_ub / (double) cur_req_width; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c index 0cdd60869ce1..79c567b6806e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c @@ -181,7 +181,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = { void dcn30_fpu_populate_dml_writeback_from_context( struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) { - int pipe_cnt, i, j; + int pipe_cnt; + unsigned int i, j; double max_calc_writeback_dispclk; double writeback_dispclk; struct writeback_st dout_wb = {0}; @@ -279,11 +280,11 @@ void dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params, dc_assert_fp_enabled(); for (i = 0; i < ARRAY_SIZE(wb_arb_params->cli_watermark); i++) { - wb_arb_params->cli_watermark[i] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000; - wb_arb_params->pstate_watermark[i] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000; + wb_arb_params->cli_watermark[i] = (unsigned int)(get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000); + wb_arb_params->pstate_watermark[i] = (unsigned int)(get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000); } - wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[cur_pipe] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */ + wb_arb_params->dram_speed_change_duration = (unsigned int)(dml->vba.WritebackAllowDRAMClockChangeEndPosition[cur_pipe] * pipes[0].clks_cfg.refclk_mhz); /* num_clock_cycles = us * MHz */ } void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) @@ -308,6 +309,7 @@ void dcn30_fpu_calculate_wm_and_dlg( { int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; int i, pipe_idx; + unsigned int pipe_i, state_i; double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported; unsigned int dummy_latency_index = 0; @@ -367,14 +369,14 @@ void dcn30_fpu_calculate_wm_and_dlg( context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; } - context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); pipes[0].clks_cfg.voltage = vlevel; pipes[0].clks_cfg.dcfclk_mhz = dcfclk; @@ -406,7 +408,7 @@ void dcn30_fpu_calculate_wm_and_dlg( * pstate latency overridden to 5us */ if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { - unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; + unsigned int min_dram_speed_mts = (unsigned int)context->bw_ctx.dml.vba.DRAMSpeed; unsigned int min_dram_speed_mts_margin = 160; context->bw_ctx.dml.soc.dram_clock_change_latency_us = @@ -437,14 +439,14 @@ void dcn30_fpu_calculate_wm_and_dlg( context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; } - context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); if (!pstate_en) { /* The only difference between A and C is p-state latency, if p-state is not supported we want to @@ -460,23 +462,23 @@ void dcn30_fpu_calculate_wm_and_dlg( * Set A calculated last so that following calculations are based on Set A */ dc->res_pool->funcs->update_soc_for_wm_a(dc, context); - context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); } - context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; + context->perf_params.stutter_period_us = (unsigned int)context->bw_ctx.dml.vba.StutterPeriod; /* Make set D = set A until set D is enabled */ context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; - for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { - if (!context->res_ctx.pipe_ctx[i].stream) + for (pipe_i = 0, pipe_idx = 0; pipe_i < dc->res_pool->pipe_count; pipe_i++) { + if (!context->res_ctx.pipe_ctx[pipe_i].stream) continue; pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); @@ -500,9 +502,9 @@ void dcn30_fpu_calculate_wm_and_dlg( context->bw_ctx.dml.vba.DRAMSpeed <= 1700 && context->bw_ctx.dml.vba.DRAMSpeed >= 1500) { - for (i = 0; i < dc->dml.soc.num_states; i++) { - if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) { - context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts; + for (state_i = 0; state_i < dc->dml.soc.num_states; state_i++) { + if (dc->dml.soc.clock_limits[state_i].dram_speed_mts > 1700) { + context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[state_i].dram_speed_mts; break; } } @@ -532,13 +534,13 @@ void dcn30_fpu_update_max_clk(struct dc_bounding_box_max_clk *dcn30_bb_max_clk) dc_assert_fp_enabled(); if (!dcn30_bb_max_clk->max_dcfclk_mhz) - dcn30_bb_max_clk->max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; + dcn30_bb_max_clk->max_dcfclk_mhz = (int)dcn3_0_soc.clock_limits[0].dcfclk_mhz; if (!dcn30_bb_max_clk->max_dispclk_mhz) - dcn30_bb_max_clk->max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz; + dcn30_bb_max_clk->max_dispclk_mhz = (int)dcn3_0_soc.clock_limits[0].dispclk_mhz; if (!dcn30_bb_max_clk->max_dppclk_mhz) - dcn30_bb_max_clk->max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz; + dcn30_bb_max_clk->max_dppclk_mhz = (int)dcn3_0_soc.clock_limits[0].dppclk_mhz; if (!dcn30_bb_max_clk->max_phyclk_mhz) - dcn30_bb_max_clk->max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz; + dcn30_bb_max_clk->max_phyclk_mhz = (int)dcn3_0_soc.clock_limits[0].phyclk_mhz; } void dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, @@ -557,12 +559,12 @@ void dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; if (optimal_fclk) - *optimal_fclk = bw_from_dram / - (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100)); + *optimal_fclk = (unsigned int)(bw_from_dram / + (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100))); if (optimal_dcfclk) - *optimal_dcfclk = bw_from_dram / - (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100)); + *optimal_dcfclk = (unsigned int)(bw_from_dram / + (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100))); } void dcn30_fpu_update_bw_bounding_box(struct dc *dc, @@ -662,7 +664,7 @@ void dcn3_fpu_build_wm_range_table(struct clk_mgr *base) double pstate_latency_us = base->ctx->dc->dml.soc.dram_clock_change_latency_us; double sr_exit_time_us = base->ctx->dc->dml.soc.sr_exit_time_us; double sr_enter_plus_exit_time_us = base->ctx->dc->dml.soc.sr_enter_plus_exit_time_us; - uint16_t min_uclk_mhz = base->bw_params->clk_table.entries[0].memclk_mhz; + uint16_t min_uclk_mhz = (uint16_t)base->bw_params->clk_table.entries[0].memclk_mhz; dc_assert_fp_enabled(); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index 634982173190..3c9040117cc4 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -366,7 +366,7 @@ static void CalculatePixelDeliveryTimes( double CursorRequestDeliveryTimePrefetch[]); static void CalculateMetaAndPTETimes( - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, @@ -439,7 +439,7 @@ static void CalculateVMGroupAndRequestTimes( double TimePerVMRequestFlip[]); static void CalculateStutterEfficiency( - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, long ROBBufferSizeInKByte, double TotalDataReadBandwidth, double DCFCLK, @@ -479,7 +479,7 @@ static void CalculateStutterEfficiency( static void CalculateSwathAndDETConfiguration( bool ForceSingleDPP, - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, unsigned int DETBufferSizeInKByte, double MaximumSwathWidthLuma[], double MaximumSwathWidthChroma[], @@ -518,7 +518,7 @@ static void CalculateSwathAndDETConfiguration( bool *ViewportSizeSupport); static void CalculateSwathWidth( bool ForceSingleDPP, - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, enum source_format_class SourcePixelFormat[], enum scan_direction_class SourceScan[], unsigned int ViewportWidth[], @@ -572,7 +572,7 @@ static double CalculateExtraLatencyBytes( int MetaChunkSize, bool GPUVMEnable, bool HostVMEnable, - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, int NumberOfDPP[], int dpte_group_bytes[], double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, @@ -630,7 +630,7 @@ static unsigned int dscceComputeDelay( pixelsPerClock = 1; //initial transmit delay as per PPS - initalXmitDelay = dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); + initalXmitDelay = (unsigned int)dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); //compute ssm delay if (bpc == 8) @@ -866,13 +866,13 @@ static bool CalculatePrefetchSchedule( v->Tdmdl_vm[k] = (v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true && v->GPUVMEnable == true ? TWait + Tvm_trips : 0); if (myPipe->ScalerEnabled) - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCL; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCL); else - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCLLBOnly; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCLLBOnly); - DPPCycles = DPPCycles + myPipe->NumberOfCursors * v->DPPCLKDelayCNVCCursor; + DPPCycles = (unsigned int)(DPPCycles + myPipe->NumberOfCursors * v->DPPCLKDelayCNVCCursor); - DISPCLKCycles = v->DISPCLKDelaySubtotal; + DISPCLKCycles = (unsigned int)v->DISPCLKDelaySubtotal; if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0) return true; @@ -1302,14 +1302,14 @@ static void CalculateDCCConfiguration( horz_div_c = 0; if (BytePerPixelC == 0) { - swath_buf_size = DETBufferSize / 2 - 2 * 256; + swath_buf_size = (long)(DETBufferSize / 2 - 2 * 256); detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l)); detile_buf_vp_vert_limit = (double) swath_buf_size / (256.0 / RequestHeight256ByteLuma / (1 + vert_div_l)); } else { - swath_buf_size = DETBufferSize / 2 - 2 * 2 * 256; + swath_buf_size = (long)(DETBufferSize / 2 - 2 * 2 * 256); detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l) @@ -1332,14 +1332,15 @@ static void CalculateDCCConfiguration( MAS_vp_horz_limit = 5760; MAS_vp_vert_limit = (BytePerPixelC > 0 ? 2880 : 5760); - max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); - max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); + max_vp_horz_width = (long)dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); + max_vp_vert_height = (long)dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); eff_surf_width_l = - (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma); + (SurfaceWidthLuma > (unsigned long)max_vp_horz_width ? + (unsigned long)max_vp_horz_width : SurfaceWidthLuma); eff_surf_width_c = eff_surf_width_l / (1 + yuv420); eff_surf_height_l = ( - SurfaceHeightLuma > max_vp_vert_height ? - max_vp_vert_height : SurfaceHeightLuma); + SurfaceHeightLuma > (unsigned long)max_vp_vert_height ? + (unsigned long)max_vp_vert_height : SurfaceHeightLuma); eff_surf_height_c = eff_surf_height_l / (1 + yuv420); full_swath_bytes_horz_wc_l = eff_surf_width_l * RequestHeight256ByteLuma * BytePerPixelY; @@ -1354,10 +1355,10 @@ static void CalculateDCCConfiguration( } if (SourcePixelFormat == dm_420_10) { - full_swath_bytes_horz_wc_l = dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256); - full_swath_bytes_horz_wc_c = dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256); - full_swath_bytes_vert_wc_l = dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256); - full_swath_bytes_vert_wc_c = dml_ceil(full_swath_bytes_vert_wc_c * 2 / 3, 256); + full_swath_bytes_horz_wc_l = (long)dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256); + full_swath_bytes_horz_wc_c = (long)dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256); + full_swath_bytes_vert_wc_l = (long)dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256); + full_swath_bytes_vert_wc_c = (long)dml_ceil(full_swath_bytes_vert_wc_c * 2 / 3, 256); } if (2 * full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSize) { @@ -1537,14 +1538,14 @@ static double CalculatePrefetchSourceLines( if (!mode_lib->vba.IgnoreViewportPositioning) { - *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; + *MaxNumSwath = (unsigned int)(dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight; else MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight; - MaxPartialSwath = dml_max(1U, MaxPartialSwath); + MaxPartialSwath = (unsigned int)dml_max(1U, MaxPartialSwath); } else { @@ -1552,7 +1553,7 @@ static double CalculatePrefetchSourceLines( dml_print( "WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n"); - *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); + *MaxNumSwath = (unsigned int)dml_ceil(*VInitPreFill / SwathHeight, 1); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight; @@ -1617,9 +1618,9 @@ static unsigned int CalculateVMAndRowBytes( if (HostVMMinPageSize < 2048) { HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; } else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); } else { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } } @@ -1627,19 +1628,19 @@ static unsigned int CalculateVMAndRowBytes( *MetaRequestWidth = 8 * BlockWidth256Bytes; if (ScanDirection != dm_vert) { *meta_row_height = *MetaRequestHeight; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) - + *MetaRequestWidth; - *MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0; + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) + + *MetaRequestWidth); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0); } else { *meta_row_height = *MetaRequestWidth; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) - + *MetaRequestHeight; - *MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0; + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) + + *MetaRequestHeight); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0); } - DCCMetaSurfaceBytes = DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) - + 64 * BlockHeight256Bytes) * BytePerPixel / 256; + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + + 64 * BlockHeight256Bytes) * BytePerPixel / 256); if (GPUVMEnable == true) { - *MetaPTEBytesFrame = (dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64; + *MetaPTEBytesFrame = (unsigned int)((dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64); MPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 1); } else { *MetaPTEBytesFrame = 0; @@ -1663,9 +1664,9 @@ static unsigned int CalculateVMAndRowBytes( if (GPUVMEnable == true && mode_lib->vba.GPUVMMaxPageTableLevels > 1) { if (ScanDirection != dm_vert) { - *DPDE0BytesFrame = 64 * (dml_ceil(((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1); + *DPDE0BytesFrame = (unsigned int)(64 * (dml_ceil(((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1)); } else { - *DPDE0BytesFrame = 64 * (dml_ceil(((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1); + *DPDE0BytesFrame = (unsigned int)(64 * (dml_ceil(((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1)); } ExtraDPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 2); } else { @@ -1683,7 +1684,7 @@ static unsigned int CalculateVMAndRowBytes( if (SurfaceTiling == dm_sw_linear) { PixelPTEReqHeightPTEs = 1; *PixelPTEReqHeight = 1; - *PixelPTEReqWidth = 32768.0 / BytePerPixel; + *PixelPTEReqWidth = (unsigned int)(32768.0 / BytePerPixel); *PTERequestSize = 64; FractionOfPTEReturnDrop = 0; } else if (GPUVMMinPageSize == 4 && MacroTileSizeBytes > 4096) { @@ -1704,16 +1705,16 @@ static unsigned int CalculateVMAndRowBytes( if (PTEBufferSizeInRequests == 0) *dpte_row_height = 1; else - *dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); - *dpte_row_width_ub = (dml_ceil(((double) SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_height = (unsigned int)dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); + *dpte_row_width_ub = (unsigned int)((dml_ceil(((double) SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else if (ScanDirection != dm_vert) { *dpte_row_height = *PixelPTEReqHeight; - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_width_ub = (unsigned int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else { - *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth); - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight; + *dpte_row_height = (unsigned int)dml_min(*PixelPTEReqWidth, *MacroTileWidth); + *dpte_row_width_ub = (unsigned int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize; } if (*PixelPTEBytesPerRow * (1 - FractionOfPTEReturnDrop) @@ -1793,9 +1794,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHTaps[k], v->WritebackVTaps[k], v->WritebackSourceWidth[k], - v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationWidth[k], v->HTotal[k], - v->WritebackLineBufferSize)); + (unsigned int)v->WritebackLineBufferSize)); } } @@ -2002,7 +2003,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->DPPCLK, v->ReadBandwidthPlaneLuma, v->ReadBandwidthPlaneChroma, - v->ReturnBusWidth, + (int)v->ReturnBusWidth, &v->DCFCLKDeepSleep); // DSCCLK @@ -2038,7 +2039,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_disabled) { v->DSCDelay[k] = dscceComputeDelay(v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), v->NumberOfDSCSlices[k], v->OutputFormat[k], v->Output[k]) @@ -2046,21 +2047,21 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman } else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) { v->DSCDelay[k] = 2 * dscceComputeDelay(v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), - v->NumberOfDSCSlices[k] / 2.0, + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)(v->NumberOfDSCSlices[k] / 2.0), v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); } else { v->DSCDelay[k] = 4 * dscceComputeDelay(v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), - v->NumberOfDSCSlices[k] / 4.0, + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)(v->NumberOfDSCSlices[k] / 4.0), v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); } - v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]; + v->DSCDelay[k] = (unsigned int)(v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]); } else { v->DSCDelay[k] = 0; } @@ -2102,13 +2103,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->SurfaceTiling[k], v->BytePerPixelC[k], v->SourceScan[k], - v->SwathWidthC[k], + (unsigned int)v->SwathWidthC[k], v->ViewportHeightChroma[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForChroma, v->PitchC[k], v->DCCMetaPitchC[k], @@ -2159,13 +2160,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->SurfaceTiling[k], v->BytePerPixelY[k], v->SourceScan[k], - v->SwathWidthY[k], + (unsigned int)v->SwathWidthY[k], v->ViewportHeight[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForLuma, v->PitchY[k], v->DCCMetaPitchY[k], @@ -2232,13 +2233,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman } - ReorderBytes = v->NumberOfChannels * dml_max3( + ReorderBytes = (long)(v->NumberOfChannels * dml_max3( v->UrgentOutOfOrderReturnPerChannelPixelDataOnly, v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - v->UrgentOutOfOrderReturnPerChannelVMDataOnly); + v->UrgentOutOfOrderReturnPerChannelVMDataOnly)); v->UrgentExtraLatency = CalculateExtraLatency( - v->RoundTripPingLatencyCycles, + (long)v->RoundTripPingLatencyCycles, ReorderBytes, v->DCFCLK, v->TotalActiveDPP, @@ -2266,9 +2267,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHRatio[k], v->WritebackVRatio[k], v->WritebackVTaps[k], - v->WritebackDestinationWidth[k], - v->WritebackDestinationHeight[k], - v->WritebackSourceHeight[k], + (long)v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationHeight[k], + (long)v->WritebackSourceHeight[k], v->HTotal[k]) / v->DISPCLK; } else v->WritebackDelay[v->VoltageLevel][k] = 0; @@ -2281,9 +2282,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHRatio[j], v->WritebackVRatio[j], v->WritebackVTaps[j], - v->WritebackDestinationWidth[j], - v->WritebackDestinationHeight[j], - v->WritebackSourceHeight[j], + (long)v->WritebackDestinationWidth[j], + (long)v->WritebackDestinationHeight[j], + (long)v->WritebackSourceHeight[j], v->HTotal[k]) / v->DISPCLK); } } @@ -2296,12 +2297,12 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j]; for (k = 0; k < v->NumberOfActivePlanes; ++k) { - v->MaxVStartupLines[k] = v->VTotal[k] - v->VActive[k] - dml_max(1.0, dml_ceil((double) v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1)); + v->MaxVStartupLines[k] = (unsigned int)(v->VTotal[k] - v->VActive[k] - dml_max(1.0, dml_ceil((double) v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1))); } v->MaximumMaxVStartupLines = 0; for (k = 0; k < v->NumberOfActivePlanes; ++k) - v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); + v->MaximumMaxVStartupLines = (unsigned int)dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); if (v->DRAMClockChangeLatencyOverride > 0.0) { v->FinalDRAMClockChangeLatency = v->DRAMClockChangeLatencyOverride; @@ -2354,21 +2355,21 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman &myPipe, v->DSCDelay[k], (unsigned int) (v->SwathWidthY[k] / v->HRatio[k]), - dml_min(v->VStartupLines, v->MaxVStartupLines[k]), + (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]), v->MaxVStartupLines[k], v->UrgentLatency, v->UrgentExtraLatency, v->TCalc, - v->PDEAndMetaPTEBytesFrame[k], - v->MetaRowByte[k], - v->PixelPTEBytesPerRow[k], + (unsigned int)v->PDEAndMetaPTEBytesFrame[k], + (unsigned int)v->MetaRowByte[k], + (unsigned int)v->PixelPTEBytesPerRow[k], v->PrefetchSourceLinesY[k], - v->SwathWidthY[k], + (unsigned int)v->SwathWidthY[k], v->BytePerPixelY[k], v->VInitPreFillY[k], v->MaxNumSwathY[k], v->PrefetchSourceLinesC[k], - v->SwathWidthC[k], + (unsigned int)v->SwathWidthC[k], v->VInitPreFillC[k], v->MaxNumSwathC[k], v->swath_width_luma_ub[k], @@ -2389,17 +2390,17 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman double TotalRepeaterDelayTime = v->MaxInterDCNTileRepeaters * (2 / v->DPPCLK[k] + 3 / v->DISPCLK); v->VUpdateWidthPix[k] = (14 / v->DCFCLKDeepSleep + 12 / v->DPPCLK[k] + TotalRepeaterDelayTime) * v->PixelClock[k]; v->VReadyOffsetPix[k] = dml_max(150.0 / v->DPPCLK[k], TotalRepeaterDelayTime + 20 / v->DCFCLKDeepSleep + 10 / v->DPPCLK[k]) * v->PixelClock[k]; - v->VUpdateOffsetPix[k] = dml_ceil(v->HTotal[k] / 4.0, 1); - v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]); + v->VUpdateOffsetPix[k] = (unsigned int)dml_ceil(v->HTotal[k] / 4.0, 1); + v->VStartup[k] = (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]); } else { int x = v->BlendingAndTiming[k]; double TotalRepeaterDelayTime = v->MaxInterDCNTileRepeaters * (2 / v->DPPCLK[k] + 3 / v->DISPCLK); v->VUpdateWidthPix[k] = (14 / v->DCFCLKDeepSleep + 12 / v->DPPCLK[k] + TotalRepeaterDelayTime) * v->PixelClock[x]; v->VReadyOffsetPix[k] = dml_max(150.0 / v->DPPCLK[k], TotalRepeaterDelayTime + 20 / v->DCFCLKDeepSleep + 10 / v->DPPCLK[k]) * v->PixelClock[x]; - v->VUpdateOffsetPix[k] = dml_ceil(v->HTotal[x] / 4.0, 1); + v->VUpdateOffsetPix[k] = (unsigned int)dml_ceil(v->HTotal[x] / 4.0, 1); if (!v->MaxVStartupLines[x]) v->MaxVStartupLines[x] = v->MaxVStartupLines[k]; - v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[x]); + v->VStartup[k] = (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[x]); } } @@ -2524,7 +2525,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->TotImmediateFlipBytes = 0; for (k = 0; k < v->NumberOfActivePlanes; ++k) { - v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]); + v->TotImmediateFlipBytes = (unsigned int)(v->TotImmediateFlipBytes + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k])); } for (k = 0; k < v->NumberOfActivePlanes; ++k) { CalculateFlipSchedule( @@ -3381,8 +3382,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l { struct vba_vars_st *v = &mode_lib->vba; int MinPrefetchMode, MaxPrefetchMode; - int i, start_state; - unsigned int j, k, m; + int idx, start_state; + unsigned int i, j, k, m; bool EnoughWritebackUnits = true; bool WritebackModeSupport = true; bool ViewportExceedsSurface = false; @@ -3590,9 +3591,9 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->WritebackHTaps[k], v->WritebackVTaps[k], v->WritebackSourceWidth[k], - v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationWidth[k], v->HTotal[k], - v->WritebackLineBufferSize)); + (unsigned int)v->WritebackLineBufferSize)); } } for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { @@ -3631,15 +3632,15 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l int MaximumSwathWidthSupportChroma = 0; if (v->SurfaceTiling[k] == dm_sw_linear) { - MaximumSwathWidthSupportLuma = 8192.0; + MaximumSwathWidthSupportLuma = (int)8192.0; } else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) { - MaximumSwathWidthSupportLuma = 2880.0; + MaximumSwathWidthSupportLuma = (int)2880.0; } else { - MaximumSwathWidthSupportLuma = 5760.0; + MaximumSwathWidthSupportLuma = (int)5760.0; } if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) { - MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma / 2.0; + MaximumSwathWidthSupportChroma = (int)(MaximumSwathWidthSupportLuma / 2.0); } else { MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma; } @@ -3837,7 +3838,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->DISPCLK_DPPCLK_Support[i][j] = false; } } - v->TotalNumberOfActiveDPP[i][j] = 0.0; + v->TotalNumberOfActiveDPP[i][j] = (unsigned int)0.0; for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k]; } @@ -3875,7 +3876,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (k = 0; k < v->NumberOfActivePlanes; ++k) { if (v->BlendingAndTiming[k] == k) { if (v->PixelClockBackEnd[k] > 3200) { - v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); + v->NumberOfDSCSlices[k] = (unsigned int)dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); } else if (v->PixelClockBackEnd[k] > 1360) { v->NumberOfDSCSlices[k] = 8; } else if (v->PixelClockBackEnd[k] > 680) { @@ -3932,7 +3933,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l if (v->PHYCLKPerState[i] >= 270.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 2700, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -3952,7 +3953,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 5400, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -3972,7 +3973,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 8100, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -3994,7 +3995,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 8100, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4073,7 +4074,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->DSCDelayPerState[i][k] = dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k], v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); @@ -4082,7 +4083,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l * dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k] / 2, v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); @@ -4091,7 +4092,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l * (dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k] / 4, v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); @@ -4163,8 +4164,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (k = 0; k < v->NumberOfActivePlanes; ++k) { v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k]; v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k]; - v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k]; - v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k]; + v->SwathWidthYAllStates[i][j][k] = (unsigned int)v->SwathWidthYThisState[k]; + v->SwathWidthCAllStates[i][j][k] = (unsigned int)v->SwathWidthCThisState[k]; v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k]; v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k]; v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k]; @@ -4186,8 +4187,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k]; v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k]; v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k]; - v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k]; - v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k]; + v->DETBufferSizeYThisState[k] = (unsigned int)v->DETBufferSizeYAllStates[i][j][k]; + v->DETBufferSizeCThisState[k] = (unsigned int)v->DETBufferSizeCAllStates[i][j][k]; } v->TotalNumberOfDCCActiveDPP[i][j] = 0; @@ -4218,16 +4219,16 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SurfaceTiling[k], v->BytePerPixelC[k], v->SourceScan[k], - v->SwathWidthCThisState[k], + (unsigned int)v->SwathWidthCThisState[k], v->ViewportHeightChroma[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForChroma, v->PitchC[k], - 0.0, + (unsigned int)0, &v->MacroTileWidthC[k], &v->MetaRowBytesC, &v->DPTEBytesPerRowC, @@ -4260,8 +4261,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma; v->PTEBufferSizeInRequestsForChroma = 0; v->PDEAndMetaPTEBytesPerFrameC = 0.0; - v->MetaRowBytesC = 0.0; - v->DPTEBytesPerRowC = 0.0; + v->MetaRowBytesC = (unsigned int)0; + v->DPTEBytesPerRowC = (unsigned int)0; v->PrefetchLinesC[i][j][k] = 0.0; v->PTEBufferSizeNotExceededC[i][j][k] = true; } @@ -4274,13 +4275,13 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SurfaceTiling[k], v->BytePerPixelY[k], v->SourceScan[k], - v->SwathWidthYThisState[k], + (unsigned int)v->SwathWidthYThisState[k], v->ViewportHeight[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForLuma, v->PitchY[k], v->DCCMetaPitchY[k], @@ -4408,7 +4409,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->RequiredDPPCLKThisState, v->ReadBandwidthLuma, v->ReadBandwidthChroma, - v->ReturnBusWidth, + (int)v->ReturnBusWidth, &v->ProjectedDCFCLKDeepSleep[i][j]); } } @@ -4426,9 +4427,9 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->WritebackHRatio[k], v->WritebackVRatio[k], v->WritebackVTaps[k], - v->WritebackDestinationWidth[k], - v->WritebackDestinationHeight[k], - v->WritebackSourceHeight[k], + (long)v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationHeight[k], + (long)v->WritebackSourceHeight[k], v->HTotal[k]) / v->RequiredDISPCLK[i][j]; } else { v->WritebackDelayTime[k] = 0.0; @@ -4443,9 +4444,9 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->WritebackHRatio[m], v->WritebackVRatio[m], v->WritebackVTaps[m], - v->WritebackDestinationWidth[m], - v->WritebackDestinationHeight[m], - v->WritebackSourceHeight[m], + (long)v->WritebackDestinationWidth[m], + (long)v->WritebackDestinationHeight[m], + (long)v->WritebackSourceHeight[m], v->HTotal[m]) / v->RequiredDISPCLK[i][j]); } } @@ -4467,11 +4468,11 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } - ReorderingBytes = v->NumberOfChannels + ReorderingBytes = (long)(v->NumberOfChannels * dml_max3( v->UrgentOutOfOrderReturnPerChannelPixelDataOnly, v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - v->UrgentOutOfOrderReturnPerChannelVMDataOnly); + v->UrgentOutOfOrderReturnPerChannelVMDataOnly)); v->FinalDRAMClockChangeLatency = (v->DRAMClockChangeLatencyOverride > 0 ? v->DRAMClockChangeLatencyOverride : v->DRAMClockChangeLatency); for (i = start_state; i < mode_lib->soc.num_states; ++i) { @@ -4567,13 +4568,13 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k]; v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k]; v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k]; - v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k]; - v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k]; + v->DETBufferSizeYThisState[k] = (unsigned int)v->DETBufferSizeYAllStates[i][j][k]; + v->DETBufferSizeCThisState[k] = (unsigned int)v->DETBufferSizeCAllStates[i][j][k]; v->ODMCombineEnabled[k] = v->ODMCombineEnablePerState[i][k]; } v->ExtraLatency = CalculateExtraLatency( - v->RoundTripPingLatencyCycles, + (long)v->RoundTripPingLatencyCycles, ReorderingBytes, v->DCFCLKState[i][j], v->TotalNumberOfActiveDPP[i][j], @@ -4623,23 +4624,23 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib, k, &myPipe, - v->DSCDelayPerState[i][k], - v->SwathWidthYThisState[k] / v->HRatio[k], - dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), - v->MaximumVStartup[i][j][k], + (unsigned int)v->DSCDelayPerState[i][k], + (unsigned int)(v->SwathWidthYThisState[k] / v->HRatio[k]), + (unsigned int)dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), + (unsigned int)v->MaximumVStartup[i][j][k], v->UrgLatency[i], v->ExtraLatency, v->TimeCalc, - v->PDEAndMetaPTEBytesPerFrame[i][j][k], - v->MetaRowBytes[i][j][k], - v->DPTEBytesPerRow[i][j][k], + (unsigned int)v->PDEAndMetaPTEBytesPerFrame[i][j][k], + (unsigned int)v->MetaRowBytes[i][j][k], + (unsigned int)v->DPTEBytesPerRow[i][j][k], v->PrefetchLinesY[i][j][k], - v->SwathWidthYThisState[k], + (unsigned int)v->SwathWidthYThisState[k], v->BytePerPixelY[k], v->PrefillY[k], v->MaxNumSwY[k], v->PrefetchLinesC[i][j][k], - v->SwathWidthCThisState[k], + (unsigned int)v->SwathWidthCThisState[k], v->PrefillC[k], v->MaxNumSwC[k], v->swath_width_luma_ub_this_state[k], @@ -4751,10 +4752,10 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l * v->UrgentBurstFactorChromaPre[k]) + v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]); } - v->TotImmediateFlipBytes = 0.0; + v->TotImmediateFlipBytes = (unsigned int)0; for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { - v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] - + v->MetaRowBytes[i][j][k] + v->DPTEBytesPerRow[i][j][k]); + v->TotImmediateFlipBytes = (unsigned int)(v->TotImmediateFlipBytes + v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] + + v->MetaRowBytes[i][j][k] + v->DPTEBytesPerRow[i][j][k])); } for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { @@ -4913,33 +4914,39 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } /*Mode Support, Voltage State and SOC Configuration*/ - for (i = v->soc.num_states - 1; i >= start_state; i--) { + for (idx = v->soc.num_states - 1; idx >= start_state; idx--) { for (j = 0; j < 2; j++) { - if (v->ScaleRatioAndTapsSupport == 1 && v->SourceFormatPixelAndScanSupport == 1 && v->ViewportSizeSupport[i][j] == 1 - && v->DIOSupport[i] == 1 && v->ODMCombine4To1SupportCheckOK[i] == 1 - && v->NotEnoughDSCUnits[i] == 0 - && v->DTBCLKRequiredMoreThanSupported[i] == 0 - && v->ROBSupport[i][j] == 1 && v->DISPCLK_DPPCLK_Support[i][j] == 1 && v->TotalAvailablePipesSupport[i][j] == 1 + if (v->ScaleRatioAndTapsSupport == 1 && v->SourceFormatPixelAndScanSupport == 1 + && v->ViewportSizeSupport[idx][j] == 1 + && v->DIOSupport[idx] == 1 && v->ODMCombine4To1SupportCheckOK[idx] == 1 + && v->NotEnoughDSCUnits[idx] == 0 + && v->DTBCLKRequiredMoreThanSupported[idx] == 0 + && v->ROBSupport[idx][j] == 1 && v->DISPCLK_DPPCLK_Support[idx][j] == 1 + && v->TotalAvailablePipesSupport[idx][j] == 1 && EnoughWritebackUnits == 1 && WritebackModeSupport == 1 - && v->WritebackLatencySupport == 1 && v->WritebackScaleRatioAndTapsSupport == 1 && v->CursorSupport == 1 && v->PitchSupport == 1 - && ViewportExceedsSurface == 0 && v->PrefetchSupported[i][j] == 1 && v->DynamicMetadataSupported[i][j] == 1 - && v->TotalVerticalActiveBandwidthSupport[i][j] == 1 && v->VRatioInPrefetchSupported[i][j] == 1 - && v->PTEBufferSizeNotExceeded[i][j] == 1 && v->NonsupportedDSCInputBPC == 0 + && v->WritebackLatencySupport == 1 && v->WritebackScaleRatioAndTapsSupport == 1 + && v->CursorSupport == 1 && v->PitchSupport == 1 + && ViewportExceedsSurface == 0 && v->PrefetchSupported[idx][j] == 1 + && v->DynamicMetadataSupported[idx][j] == 1 + && v->TotalVerticalActiveBandwidthSupport[idx][j] == 1 + && v->VRatioInPrefetchSupported[idx][j] == 1 + && v->PTEBufferSizeNotExceeded[idx][j] == 1 && v->NonsupportedDSCInputBPC == 0 && ((v->HostVMEnable == 0 && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required) - || v->ImmediateFlipSupportedForState[i][j] == true)) { - v->ModeSupport[i][j] = true; + || v->ImmediateFlipSupportedForState[idx][j] == true)) { + v->ModeSupport[idx][j] = true; } else { - v->ModeSupport[i][j] = false; + v->ModeSupport[idx][j] = false; } } } { unsigned int MaximumMPCCombine = 0; - for (i = v->soc.num_states; i >= start_state; i--) { - if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) { - v->VoltageLevel = i; - v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true; - if (v->ModeSupport[i][1] == true) { + for (idx = v->soc.num_states; idx >= start_state; idx--) { + if (idx == (int)v->soc.num_states || v->ModeSupport[idx][0] == true + || v->ModeSupport[idx][1] == true) { + v->VoltageLevel = idx; + v->ModeIsSupported = v->ModeSupport[idx][0] == true || v->ModeSupport[idx][1] == true; + if (v->ModeSupport[idx][1] == true) { MaximumMPCCombine = 1; } else { MaximumMPCCombine = 0; @@ -5038,20 +5045,20 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( for (k = 0; k < v->NumberOfActivePlanes; ++k) { - v->LBLatencyHidingSourceLinesY = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1); + v->LBLatencyHidingSourceLinesY = (unsigned int)(dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1)); - v->LBLatencyHidingSourceLinesC = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1); + v->LBLatencyHidingSourceLinesC = (unsigned int)(dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1)); EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]); EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]); LinesInDETY[k] = (double) DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k]; - LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); + LinesInDETYRoundedDownToSwath[k] = (unsigned int)dml_floor(LinesInDETY[k], SwathHeightY[k]); FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k]; if (BytePerPixelDETC[k] > 0) { LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k]; - LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]); + LinesInDETCRoundedDownToSwath = (unsigned int)dml_floor(LinesInDETC, SwathHeightC[k]); FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k]; } else { LinesInDETC = 0; @@ -5380,7 +5387,7 @@ static void CalculatePixelDeliveryTimes( for (k = 0; k < NumberOfActivePlanes; ++k) { int cursor_req_per_width = 0; - cursor_req_per_width = dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1); + cursor_req_per_width = (int)dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1); if (NumberOfCursors[k] > 0) { if (VRatio[k] <= 1) { CursorRequestDeliveryTime[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width; @@ -5400,7 +5407,7 @@ static void CalculatePixelDeliveryTimes( } static void CalculateMetaAndPTETimes( - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, @@ -5509,7 +5516,7 @@ static void CalculateMetaAndPTETimes( } else { meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; - meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / meta_chunk_width_chroma; + meta_chunk_per_row_int_chroma = (unsigned int)((double) meta_row_width_chroma[k] / meta_chunk_width_chroma); meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma; if (SourceScan[k] != dm_vert) { meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k]; @@ -5542,7 +5549,7 @@ static void CalculateMetaAndPTETimes( } else { dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k]; } - dpte_groups_per_row_luma_ub = dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1); + dpte_groups_per_row_luma_ub = (unsigned int)dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1); time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; @@ -5556,7 +5563,7 @@ static void CalculateMetaAndPTETimes( } else { dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqHeightC[k]; } - dpte_groups_per_row_chroma_ub = dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1); + dpte_groups_per_row_chroma_ub = (unsigned int)dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1); time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; @@ -5604,32 +5611,32 @@ static void CalculateVMGroupAndRequestTimes( if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) { if (DCCEnable[k] == false) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) + num_group_per_lower_vm_stage = (int)(dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) - / (double) (vm_group_bytes[k]), 1); + / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) + num_group_per_lower_vm_stage = (int)dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (GPUVMMaxPageTableLevels == 1) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) + num_group_per_lower_vm_stage = (int)(dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) - / (double) (vm_group_bytes[k]), 1); + / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) + num_group_per_lower_vm_stage = (int)dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = 2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + num_group_per_lower_vm_stage = (int)(2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + + (int)dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = 1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)(1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)); } } } @@ -5686,7 +5693,7 @@ static void CalculateVMGroupAndRequestTimes( } static void CalculateStutterEfficiency( - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, long ROBBufferSizeInKByte, double TotalDataReadBandwidth, double DCFCLK, @@ -5840,7 +5847,7 @@ static void CalculateStutterEfficiency( static void CalculateSwathAndDETConfiguration( bool ForceSingleDPP, - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, unsigned int DETBufferSizeInKByte, double MaximumSwathWidthLuma[], double MaximumSwathWidthChroma[], @@ -5891,7 +5898,7 @@ static void CalculateSwathAndDETConfiguration( long RoundedUpSwathSizeBytesC = 0; double SwathWidthSingleDPP[DC__NUM_DPP__MAX] = { 0 }; double SwathWidthSingleDPPChroma[DC__NUM_DPP__MAX] = { 0 }; - int k; + unsigned int k; CalculateSwathWidth( ForceSingleDPP, @@ -5962,39 +5969,39 @@ static void CalculateSwathAndDETConfiguration( } } - RoundedUpMaxSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] - * MaximumSwathHeightY[k]; - RoundedUpMinSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] - * MinimumSwathHeightY; + RoundedUpMaxSwathSizeBytesY = (long)(swath_width_luma_ub[k] * BytePerPixDETY[k] + * MaximumSwathHeightY[k]); + RoundedUpMinSwathSizeBytesY = (long)(swath_width_luma_ub[k] * BytePerPixDETY[k] + * MinimumSwathHeightY); if (SourcePixelFormat[k] == dm_420_10) { - RoundedUpMaxSwathSizeBytesY = dml_ceil((double) RoundedUpMaxSwathSizeBytesY, 256); - RoundedUpMinSwathSizeBytesY = dml_ceil((double) RoundedUpMinSwathSizeBytesY, 256); + RoundedUpMaxSwathSizeBytesY = (long)dml_ceil((double) RoundedUpMaxSwathSizeBytesY, 256); + RoundedUpMinSwathSizeBytesY = (long)dml_ceil((double) RoundedUpMinSwathSizeBytesY, 256); } - RoundedUpMaxSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] - * MaximumSwathHeightC[k]; - RoundedUpMinSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] - * MinimumSwathHeightC; + RoundedUpMaxSwathSizeBytesC = (long)(swath_width_chroma_ub[k] * BytePerPixDETC[k] + * MaximumSwathHeightC[k]); + RoundedUpMinSwathSizeBytesC = (long)(swath_width_chroma_ub[k] * BytePerPixDETC[k] + * MinimumSwathHeightC); if (SourcePixelFormat[k] == dm_420_10) { - RoundedUpMaxSwathSizeBytesC = dml_ceil(RoundedUpMaxSwathSizeBytesC, 256); - RoundedUpMinSwathSizeBytesC = dml_ceil(RoundedUpMinSwathSizeBytesC, 256); + RoundedUpMaxSwathSizeBytesC = (long)dml_ceil(RoundedUpMaxSwathSizeBytesC, 256); + RoundedUpMinSwathSizeBytesC = (long)dml_ceil(RoundedUpMinSwathSizeBytesC, 256); } if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC - <= DETBufferSizeInKByte * 1024 / 2) { + <= (long)DETBufferSizeInKByte * 1024 / 2) { SwathHeightY[k] = MaximumSwathHeightY[k]; SwathHeightC[k] = MaximumSwathHeightC[k]; RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY; RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC; } else if (RoundedUpMaxSwathSizeBytesY >= 1.5 * RoundedUpMaxSwathSizeBytesC && RoundedUpMinSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC - <= DETBufferSizeInKByte * 1024 / 2) { + <= (long)DETBufferSizeInKByte * 1024 / 2) { SwathHeightY[k] = MinimumSwathHeightY; SwathHeightC[k] = MaximumSwathHeightC[k]; RoundedUpSwathSizeBytesY = RoundedUpMinSwathSizeBytesY; RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC; } else if (RoundedUpMaxSwathSizeBytesY < 1.5 * RoundedUpMaxSwathSizeBytesC && RoundedUpMaxSwathSizeBytesY + RoundedUpMinSwathSizeBytesC - <= DETBufferSizeInKByte * 1024 / 2) { + <= (long)DETBufferSizeInKByte * 1024 / 2) { SwathHeightY[k] = MaximumSwathHeightY[k]; SwathHeightC[k] = MinimumSwathHeightC; RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY; @@ -6018,7 +6025,7 @@ static void CalculateSwathAndDETConfiguration( } if (RoundedUpMinSwathSizeBytesY + RoundedUpMinSwathSizeBytesC - > DETBufferSizeInKByte * 1024 / 2 + > (long)DETBufferSizeInKByte * 1024 / 2 || SwathWidth[k] > MaximumSwathWidthLuma[k] || (SwathHeightC[k] > 0 && SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) { @@ -6032,7 +6039,7 @@ static void CalculateSwathAndDETConfiguration( static void CalculateSwathWidth( bool ForceSingleDPP, - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, enum source_format_class SourcePixelFormat[], enum scan_direction_class SourceScan[], unsigned int ViewportWidth[], @@ -6107,17 +6114,17 @@ static void CalculateSwathWidth( SwathWidthC[k] = SwathWidthSingleDPPC[k]; } - surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); - surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); + surface_width_ub_l = (long)dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); + surface_height_ub_l = (long)dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); if (SourceScan[k] != dm_vert) { MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k]; MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k]; - swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (long) dml_ceil(SwathWidthY[k] - 1, + swath_width_luma_ub[k] = (unsigned int)dml_min(surface_width_ub_l, (long) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]); if (BytePerPixC[k] > 0) { - surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); - swath_width_chroma_ub[k] = dml_min(surface_width_ub_c, (long) dml_ceil(SwathWidthC[k] - 1, + surface_width_ub_c = (long)dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); + swath_width_chroma_ub[k] = (unsigned int)dml_min(surface_width_ub_c, (long) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]); } else { swath_width_chroma_ub[k] = 0; @@ -6125,11 +6132,11 @@ static void CalculateSwathWidth( } else { MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k]; MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k]; - swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (long) dml_ceil(SwathWidthY[k] - 1, + swath_width_luma_ub[k] = (unsigned int)dml_min(surface_height_ub_l, (long) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]); if (BytePerPixC[k] > 0) { - surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); - swath_width_chroma_ub[k] = dml_min(surface_height_ub_c, (long) dml_ceil(SwathWidthC[k] - 1, + surface_height_ub_c = (long)dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); + swath_width_chroma_ub[k] = (unsigned int)dml_min(surface_height_ub_c, (long) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]); } else { swath_width_chroma_ub[k] = 0; @@ -6185,7 +6192,7 @@ static double CalculateExtraLatencyBytes( int MetaChunkSize, bool GPUVMEnable, bool HostVMEnable, - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, int NumberOfDPP[], int dpte_group_bytes[], double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, @@ -6203,9 +6210,9 @@ static double CalculateExtraLatencyBytes( if (HostVMMinPageSize < 2048) { HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; } else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); } else { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } } else { HostVMInefficiencyFactor = 1; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c index 472ac5ee165f..a373df0aebf1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c @@ -120,13 +120,13 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), - 1) - 3; + rq_regs->rq_regs_l.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), + 1) - 3); if (rq_param->yuv420) { extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), - 1) - 3; + rq_regs->rq_regs_c.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), + 1) - 3); } rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); @@ -146,11 +146,11 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, if (rq_param->yuv420) { if ((double)rq_param->misc.rq_l.stored_swath_bytes / (double)rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma } else { - detile_buf_plane1_addr = dml_round_to_multiple((unsigned int)((2.0 * detile_buf_size_in_bytes) / 3.0), + detile_buf_plane1_addr = (unsigned int)(dml_round_to_multiple((unsigned int)((2.0 * detile_buf_size_in_bytes) / 3.0), 256, - 0) / 64.0; // 2/3 to chroma + 0) / 64.0); // 2/3 to chroma } } rq_regs->plane1_base_address = detile_buf_plane1_addr; @@ -177,10 +177,10 @@ static void handle_det_buf_split(struct display_mode_lib *mode_lib, full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; if (rq_param->yuv420_10bpc) { - full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0, + full_swath_bytes_packed_l = (unsigned int)dml_round_to_multiple((unsigned int)(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0), 256, 1) + 256; - full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0, + full_swath_bytes_packed_c = (unsigned int)dml_round_to_multiple((unsigned int)(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0), 256, 1) + 256; } @@ -400,8 +400,8 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, // "/2" is like square root // blk is vertical biased if (tiling != dm_sw_linear) - log2_blk_height = log2_blk256_height - + dml_ceil((double)(log2_blk_bytes - 8) / 2.0, 1); + log2_blk_height = (unsigned int)(log2_blk256_height + + dml_ceil((double)(log2_blk_bytes - 8) / 2.0, 1)); else log2_blk_height = 0; // blk height of 1 @@ -573,7 +573,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, if (surf_linear) { unsigned int dpte_row_height = 0; - log2_dpte_row_height_linear = dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); + log2_dpte_row_height_linear = (unsigned int)dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); dml_print("DML_DLG: %s: is_chroma = %d\n", __func__, is_chroma); dml_print("DML_DLG: %s: dpte_buf_in_pte_reqs = %d\n", __func__, dpte_buf_in_pte_reqs); @@ -645,7 +645,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, // the upper bound for the dpte groups per row is as follows. - rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double)dpte_row_width_ub / dpte_group_width, + rq_dlg_param->dpte_groups_per_row_ub = (unsigned int)dml_ceil((double)dpte_row_width_ub / dpte_group_width, 1); } @@ -670,7 +670,7 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib, vp_height = pipe_param->src.viewport_height_c; data_pitch = pipe_param->src.data_pitch_c; meta_pitch = pipe_param->src.meta_pitch_c; - surface_height = pipe_param->src.surface_height_y / 2.0; + surface_height = (unsigned int)(pipe_param->src.surface_height_y / 2.0); } else { vp_width = pipe_param->src.viewport_width / ppe; vp_height = pipe_param->src.viewport_height; @@ -687,18 +687,18 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib, access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed hactive_odm = pipe_param->dest.hactive / ((unsigned int) pipe_param->dest.odm_combine*2); if (is_chroma) { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width; - src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width); + src_hactive_odm = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm); } else { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width; - src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width); + src_hactive_odm = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm); } if (access_dir == 0) { - vp_width = dml_min(full_src_vp_width, src_hactive_odm); + vp_width = (unsigned int)dml_min(full_src_vp_width, src_hactive_odm); dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width); } else { - vp_height = dml_min(full_src_vp_width, src_hactive_odm); + vp_height = (unsigned int)dml_min(full_src_vp_width, src_hactive_odm); dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height); } dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width); @@ -833,7 +833,7 @@ static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, cur_req_size = 256; } - cur_req_width = (double)cur_req_size / ((double)cur_bit_per_pixel / 8.0); + cur_req_width = (unsigned int)((double)cur_req_size / ((double)cur_bit_per_pixel / 8.0)); cur_width_ub = dml_ceil((double)cur_src_width / (double)cur_req_width, 1) * (double)cur_req_width; cur_req_per_width = cur_width_ub / (double)cur_req_width; @@ -1123,11 +1123,11 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, if (dout->dsc_enable) { double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dispclk_delay_subtotal += dsc_delay; + dispclk_delay_subtotal += (unsigned int)dsc_delay; } - pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz - + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; + pixel_rate_delay_subtotal = (unsigned int)(dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz) + + (unsigned int)(dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz); vstartup_start = dst->vstartup_start; if (interlaced) { @@ -1167,8 +1167,8 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, min_vblank); } - dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_x_after_scaler = (unsigned int)get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_y_after_scaler = (int)get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); if (dst_y_after_scaler < 0) dst_y_after_scaler = 0; @@ -1552,7 +1552,7 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, // Assignment to register structures disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8); - disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + disp_dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); // in terms of refclk ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); disp_dlg_regs->dst_y_prefetch = (unsigned int)(dst_y_prefetch * dml_pow(2, 2)); disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int)(dst_y_per_vm_vblank * dml_pow(2, 2)); @@ -1601,23 +1601,23 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; } - disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; - disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; - disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); - disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // Clamp to max for now if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int)((double)dpte_row_height_l / (double)vratio_l * dml_pow(2, 2)); @@ -1646,12 +1646,12 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, / (double)vratio_l * (double)htotal * ref_freq_to_pix_freq / (double)dpte_groups_per_row_ub_l); if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)((double)meta_row_height_l / (double)vratio_l * (double)htotal * ref_freq_to_pix_freq / (double)meta_chunks_per_row_ub_l); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (dual_plane) { disp_dlg_regs->refcyc_per_pte_group_nom_c = @@ -1659,7 +1659,7 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, * (double)htotal * ref_freq_to_pix_freq / (double)dpte_groups_per_row_ub_c); if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1); // TODO: Is this the right calculation? Does htotal need to be halved? disp_dlg_regs->refcyc_per_meta_chunk_nom_c = @@ -1667,7 +1667,7 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, * (double)htotal * ref_freq_to_pix_freq / (double)meta_chunks_per_row_ub_c); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1); } disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int)dml_floor(refcyc_per_line_delivery_pre_l, @@ -1721,7 +1721,7 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs->qos_ramp_disable_cur0 = 0; - disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + disp_ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); print__ttu_regs_st(mode_lib, disp_ttu_regs); @@ -1755,7 +1755,7 @@ void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes); - dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, + dlg_sys_param.total_flip_bytes = (unsigned int)get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c index 1aaa77265eed..81ef95f51d05 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c @@ -308,14 +308,14 @@ static void calculate_wm_set_for_vlevel(int vlevel, dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; - wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; - wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; - wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; - wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; - wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; - wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; - wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; - wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; + wm_set->urgent_ns = (uint32_t)(get_wm_urgent(dml, pipes, pipe_cnt) * 1000); + wm_set->cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000); + wm_set->cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000); + wm_set->cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000); + wm_set->pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000); + wm_set->frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000); + wm_set->frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000); + wm_set->urgent_latency_ns = (uint32_t)(get_urgent_latency(dml, pipes, pipe_cnt) * 1000); dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; } @@ -326,7 +326,8 @@ void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool); struct clk_limit_table *clk_table = &bw_params->clk_table; unsigned int i, closest_clk_lvl; - int j = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0; + int j = 0; + unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0; dc_assert_fp_enabled(); @@ -405,8 +406,8 @@ void dcn301_fpu_set_wm_ranges(int i, { dc_assert_fp_enabled(); - ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; - ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; + ranges->reader_wm_sets[i].min_fill_clk_mhz = (uint16_t)((i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0); + ranges->reader_wm_sets[i].max_fill_clk_mhz = (uint16_t)(loaded_bb->clock_limits[i].dram_speed_mts / 16); } void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info) @@ -429,7 +430,7 @@ void dcn301_fpu_calculate_wm_and_dlg(struct dc *dc, int pipe_cnt, int vlevel_req) { - int i, pipe_idx; + unsigned int i, pipe_idx; int vlevel, vlevel_max; struct wm_range_table_entry *table_entry; struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c index 8d7c59ec701d..90a7b29ebe74 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c @@ -182,14 +182,14 @@ static void dcn302_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; if (optimal_fclk) - *optimal_fclk = bw_from_dram / + *optimal_fclk = (unsigned int)(bw_from_dram / (dcn3_02_soc.fabric_datapath_to_dcn_data_return_bytes * - (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100)); + (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100))); if (optimal_dcfclk) - *optimal_dcfclk = bw_from_dram / + *optimal_dcfclk = (unsigned int)(bw_from_dram / (dcn3_02_soc.return_bus_width_bytes * - (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100)); + (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100))); } void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) @@ -218,7 +218,7 @@ void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; if (bw_params->clk_table.entries[0].memclk_mhz) { - int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; + unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; for (i = 0; i < MAX_NUM_DPM_LVL; i++) { if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) @@ -231,13 +231,13 @@ void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; } if (!max_dcfclk_mhz) - max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz; + max_dcfclk_mhz = (int)dcn3_02_soc.clock_limits[0].dcfclk_mhz; if (!max_dispclk_mhz) - max_dispclk_mhz = dcn3_02_soc.clock_limits[0].dispclk_mhz; + max_dispclk_mhz = (int)dcn3_02_soc.clock_limits[0].dispclk_mhz; if (!max_dppclk_mhz) - max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz; + max_dppclk_mhz = (int)dcn3_02_soc.clock_limits[0].dppclk_mhz; if (!max_phyclk_mhz) - max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz; + max_phyclk_mhz = (int)dcn3_02_soc.clock_limits[0].phyclk_mhz; if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { /* If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array */ diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c index b5d3fd4c3694..e42419c7868d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c @@ -178,13 +178,13 @@ static void dcn303_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; if (optimal_fclk) - *optimal_fclk = bw_from_dram / + *optimal_fclk = (unsigned int)(bw_from_dram / (dcn3_03_soc.fabric_datapath_to_dcn_data_return_bytes * - (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100)); + (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100))); if (optimal_dcfclk) - *optimal_dcfclk = bw_from_dram / - (dcn3_03_soc.return_bus_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100)); + *optimal_dcfclk = (unsigned int)(bw_from_dram / + (dcn3_03_soc.return_bus_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100))); } @@ -214,7 +214,7 @@ void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; if (bw_params->clk_table.entries[0].memclk_mhz) { - int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; + unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; for (i = 0; i < MAX_NUM_DPM_LVL; i++) { if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) @@ -227,13 +227,13 @@ void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; } if (!max_dcfclk_mhz) - max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz; + max_dcfclk_mhz = (int)dcn3_03_soc.clock_limits[0].dcfclk_mhz; if (!max_dispclk_mhz) - max_dispclk_mhz = dcn3_03_soc.clock_limits[0].dispclk_mhz; + max_dispclk_mhz = (int)dcn3_03_soc.clock_limits[0].dispclk_mhz; if (!max_dppclk_mhz) - max_dppclk_mhz = dcn3_03_soc.clock_limits[0].dppclk_mhz; + max_dppclk_mhz = (int)dcn3_03_soc.clock_limits[0].dppclk_mhz; if (!max_phyclk_mhz) - max_phyclk_mhz = dcn3_03_soc.clock_limits[0].phyclk_mhz; + max_phyclk_mhz = (int)dcn3_03_soc.clock_limits[0].phyclk_mhz; if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c index ad23215da9f8..f9b2da6b2bb8 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c @@ -485,9 +485,12 @@ void dcn31_calculate_wm_and_dlg_fp( int pipe_cnt, int vlevel) { - int i, pipe_idx, total_det = 0, active_hubp_count = 0; + int total_det = 0, active_hubp_count = 0; + unsigned int i, pipe_idx; double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; uint32_t cstate_enter_plus_exit_z8_ns; + uint32_t minimum_z8_residency_time_ns = + (uint32_t)dc->debug.minimum_z8_residency_time * 1000U; dc_assert_fp_enabled(); @@ -499,7 +502,7 @@ void dcn31_calculate_wm_and_dlg_fp( * Override any clocks that can block S0i3 to min here */ if (pipe_cnt == 0) { - context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0 + context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)dcfclk; // always should be vlevel 0 return; } @@ -508,11 +511,11 @@ void dcn31_calculate_wm_and_dlg_fp( pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; cstate_enter_plus_exit_z8_ns = - get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + (uint32_t)(get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); if (get_stutter_period(&context->bw_ctx.dml, pipes, pipe_cnt) < dc->debug.minimum_z8_residency_time && - cstate_enter_plus_exit_z8_ns < dc->debug.minimum_z8_residency_time * 1000) - cstate_enter_plus_exit_z8_ns = dc->debug.minimum_z8_residency_time * 1000; + cstate_enter_plus_exit_z8_ns < minimum_z8_residency_time_ns) + cstate_enter_plus_exit_z8_ns = minimum_z8_residency_time_ns; /* Set A: * All clocks min required @@ -520,16 +523,16 @@ void dcn31_calculate_wm_and_dlg_fp( * Set A calculated last so that following calculations are based on Set A */ dc->res_pool->funcs->update_soc_for_wm_a(dc, context); - context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus_exit_z8_ns; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = (uint32_t)(get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; @@ -578,7 +581,7 @@ void dcn31_calculate_wm_and_dlg_fp( continue; context->res_ctx.pipe_ctx[i].det_buffer_size_kb = - get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + (int)get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); if (context->res_ctx.pipe_ctx[i].det_buffer_size_kb > 384) context->res_ctx.pipe_ctx[i].det_buffer_size_kb /= 2; total_det += context->res_ctx.pipe_ctx[i].det_buffer_size_kb; @@ -592,7 +595,7 @@ void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits; struct clk_limit_table *clk_table = &bw_params->clk_table; unsigned int i, closest_clk_lvl; - int max_dispclk_mhz = 0, max_dppclk_mhz = 0; + unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0; int j; dc_assert_fp_enabled(); @@ -668,7 +671,7 @@ void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa void dcn315_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) { struct clk_limit_table *clk_table = &bw_params->clk_table; - int i, max_dispclk_mhz = 0, max_dppclk_mhz = 0; + unsigned int i, max_dispclk_mhz = 0, max_dppclk_mhz = 0; dc_assert_fp_enabled(); @@ -731,7 +734,7 @@ void dcn316_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits; struct clk_limit_table *clk_table = &bw_params->clk_table; unsigned int i, closest_clk_lvl; - int max_dispclk_mhz = 0, max_dppclk_mhz = 0; + unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0; int j; dc_assert_fp_enabled(); @@ -810,7 +813,7 @@ int dcn_get_max_non_odm_pix_rate_100hz(struct _vcs_dpi_soc_bounding_box_st *soc) { dc_assert_fp_enabled(); - return soc->clock_limits[0].dispclk_mhz * 10000.0 / (1.0 + soc->dcn_downspread_percent / 100.0); + return (int)(soc->clock_limits[0].dispclk_mhz * 10000.0 / (1.0 + soc->dcn_downspread_percent / 100.0)); } int dcn_get_approx_det_segs_required_for_pstate( diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index 9833467722b9..173251d738f2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -700,7 +700,7 @@ static unsigned int dscceComputeDelay( pixelsPerClock = 1; //initial transmit delay as per PPS - initalXmitDelay = dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); + initalXmitDelay = (unsigned int)dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); //compute ssm delay if (bpc == 8) @@ -985,13 +985,13 @@ static bool CalculatePrefetchSchedule( *Tdmdl_vm = (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true && GPUVMEnable == true ? TWait + Tvm_trips : 0); if (myPipe->ScalerEnabled) - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL); else - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly); - DPPCycles = DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor; + DPPCycles = (unsigned int)(DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor); - DISPCLKCycles = DISPCLKDelaySubtotal; + DISPCLKCycles = (unsigned int)DISPCLKDelaySubtotal; if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0) return true; @@ -1510,10 +1510,10 @@ static void CalculateDCCConfiguration( double detile_buf_vp_horz_limit; double detile_buf_vp_vert_limit; - int MAS_vp_horz_limit; - int MAS_vp_vert_limit; - int max_vp_horz_width; - int max_vp_vert_height; + unsigned int MAS_vp_horz_limit; + unsigned int MAS_vp_vert_limit; + unsigned int max_vp_horz_width; + unsigned int max_vp_vert_height; int eff_surf_width_l; int eff_surf_width_c; int eff_surf_height_l; @@ -1554,11 +1554,11 @@ static void CalculateDCCConfiguration( horz_div_c = 0; if (BytePerPixelC == 0) { - swath_buf_size = DETBufferSize / 2 - 2 * 256; + swath_buf_size = (int)(DETBufferSize / 2 - 2 * 256); detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l)); detile_buf_vp_vert_limit = (double) swath_buf_size / (256.0 / RequestHeight256ByteLuma / (1 + vert_div_l)); } else { - swath_buf_size = DETBufferSize / 2 - 2 * 2 * 256; + swath_buf_size = (int)(DETBufferSize / 2 - 2 * 2 * 256); detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l) + (double) RequestHeight256ByteChroma * BytePerPixelC / (1 + horz_div_c) / (1 + yuv420)); @@ -1576,8 +1576,8 @@ static void CalculateDCCConfiguration( MAS_vp_horz_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : 5760; MAS_vp_vert_limit = (BytePerPixelC > 0 ? 2880 : 5760); - max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); - max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); + max_vp_horz_width = (int)dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); + max_vp_vert_height = (int)dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); eff_surf_width_l = (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma); eff_surf_width_c = eff_surf_width_l / (1 + yuv420); eff_surf_height_l = (SurfaceHeightLuma > max_vp_vert_height ? max_vp_vert_height : SurfaceHeightLuma); @@ -1594,10 +1594,10 @@ static void CalculateDCCConfiguration( } if (SourcePixelFormat == dm_420_10) { - full_swath_bytes_horz_wc_l = dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256); - full_swath_bytes_horz_wc_c = dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256); - full_swath_bytes_vert_wc_l = dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256); - full_swath_bytes_vert_wc_c = dml_ceil(full_swath_bytes_vert_wc_c * 2 / 3, 256); + full_swath_bytes_horz_wc_l = (int)dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256); + full_swath_bytes_horz_wc_c = (int)dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256); + full_swath_bytes_vert_wc_l = (int)dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256); + full_swath_bytes_vert_wc_c = (int)dml_ceil(full_swath_bytes_vert_wc_c * 2 / 3, 256); } if (2 * full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSize) { @@ -1760,20 +1760,20 @@ static double CalculatePrefetchSourceLines( if (!v->IgnoreViewportPositioning) { - *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; + *MaxNumSwath = (unsigned int)(dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight; else MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight; - MaxPartialSwath = dml_max(1U, MaxPartialSwath); + MaxPartialSwath = (unsigned int)dml_max(1U, MaxPartialSwath); } else { if (ViewportYStart != 0) dml_print("WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n"); - *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); + *MaxNumSwath = (unsigned int)dml_ceil(*VInitPreFill / SwathHeight, 1); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight; @@ -1848,9 +1848,9 @@ static unsigned int CalculateVMAndRowBytes( if (HostVMMinPageSize < 2048) { HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; } else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); } else { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } } @@ -1858,16 +1858,16 @@ static unsigned int CalculateVMAndRowBytes( *MetaRequestWidth = 8 * BlockWidth256Bytes; if (ScanDirection != dm_vert) { *meta_row_height = *MetaRequestHeight; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth; - *MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0; + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0); } else { *meta_row_height = *MetaRequestWidth; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight; - *MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0; + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0); } - DCCMetaSurfaceBytes = DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel / 256; + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel / 256); if (GPUVMEnable == true) { - *MetaPTEBytesFrame = (dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64; + *MetaPTEBytesFrame = (int)((dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64); MPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 1); } else { *MetaPTEBytesFrame = 0; @@ -1891,17 +1891,17 @@ static unsigned int CalculateVMAndRowBytes( if (GPUVMEnable == true && v->GPUVMMaxPageTableLevels > 1) { if (ScanDirection != dm_vert) { - *DPDE0BytesFrame = 64 + *DPDE0BytesFrame = (int)(64 * (dml_ceil( ((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } else { - *DPDE0BytesFrame = 64 + *DPDE0BytesFrame = (int)(64 * (dml_ceil( ((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } ExtraDPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 2); } else { @@ -1929,7 +1929,7 @@ static unsigned int CalculateVMAndRowBytes( if (SurfaceTiling == dm_sw_linear) { PixelPTEReqHeightPTEs = 1; *PixelPTEReqHeight = 1; - *PixelPTEReqWidth = 32768.0 / BytePerPixel; + *PixelPTEReqWidth = (unsigned int)(32768.0 / BytePerPixel); *PTERequestSize = 64; FractionOfPTEReturnDrop = 0; } else if (GPUVMMinPageSize == 4 && MacroTileSizeBytes > 4096) { @@ -1947,16 +1947,16 @@ static unsigned int CalculateVMAndRowBytes( } if (SurfaceTiling == dm_sw_linear) { - *dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); - *dpte_row_width_ub = (dml_ceil((double)(Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_height = (unsigned int)dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); + *dpte_row_width_ub = (int)((dml_ceil((double)(Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else if (ScanDirection != dm_vert) { *dpte_row_height = *PixelPTEReqHeight; - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_width_ub = (int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else { - *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth); - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight; + *dpte_row_height = (unsigned int)dml_min(*PixelPTEReqWidth, *MacroTileWidth); + *dpte_row_width_ub = (int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize; } @@ -2041,9 +2041,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHTaps[k], v->WritebackVTaps[k], v->WritebackSourceWidth[k], - v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationWidth[k], v->HTotal[k], - v->WritebackLineBufferSize)); + (unsigned int)v->WritebackLineBufferSize)); } } @@ -2229,7 +2229,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->DPPCLK, v->ReadBandwidthPlaneLuma, v->ReadBandwidthPlaneChroma, - v->ReturnBusWidth, + (int)v->ReturnBusWidth, &v->DCFCLKDeepSleep); // DSCCLK @@ -2266,7 +2266,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->DSCDelay[k] = dscceComputeDelay( v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), v->NumberOfDSCSlices[k], v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); @@ -2275,8 +2275,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman * (dscceComputeDelay( v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), - v->NumberOfDSCSlices[k] / 2.0, + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)(v->NumberOfDSCSlices[k] / 2.0), v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); } else { @@ -2284,12 +2284,12 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman * (dscceComputeDelay( v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), - v->NumberOfDSCSlices[k] / 4.0, + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)(v->NumberOfDSCSlices[k] / 4.0), v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); } - v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]; + v->DSCDelay[k] = (unsigned int)(v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]); } else { v->DSCDelay[k] = 0; } @@ -2330,13 +2330,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->SurfaceTiling[k], v->BytePerPixelC[k], v->SourceScan[k], - v->SwathWidthC[k], + (unsigned int)v->SwathWidthC[k], v->ViewportHeightChroma[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForChroma, v->PitchC[k], v->DCCMetaPitchC[k], @@ -2387,13 +2387,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->SurfaceTiling[k], v->BytePerPixelY[k], v->SourceScan[k], - v->SwathWidthY[k], + (unsigned int)v->SwathWidthY[k], v->ViewportHeight[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForLuma, v->PitchY[k], v->DCCMetaPitchY[k], @@ -2459,11 +2459,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman NoChromaPlanes = false; } - ReorderBytes = v->NumberOfChannels + ReorderBytes = (int)(v->NumberOfChannels * dml_max3( v->UrgentOutOfOrderReturnPerChannelPixelDataOnly, v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - v->UrgentOutOfOrderReturnPerChannelVMDataOnly); + v->UrgentOutOfOrderReturnPerChannelVMDataOnly)); VMDataOnlyReturnBW = dml_min( dml_min(v->ReturnBusWidth * v->DCFCLK, v->FabricClock * v->FabricDatapathToDCNDataReturn) @@ -2489,7 +2489,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman HostVMInefficiencyFactor = v->ReturnBW / VMDataOnlyReturnBW; v->UrgentExtraLatency = CalculateExtraLatency( - v->RoundTripPingLatencyCycles, + (int)v->RoundTripPingLatencyCycles, ReorderBytes, v->DCFCLK, v->TotalActiveDPP, @@ -2517,9 +2517,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHRatio[k], v->WritebackVRatio[k], v->WritebackVTaps[k], - v->WritebackDestinationWidth[k], - v->WritebackDestinationHeight[k], - v->WritebackSourceHeight[k], + (int)v->WritebackDestinationWidth[k], + (int)v->WritebackDestinationHeight[k], + (int)v->WritebackSourceHeight[k], v->HTotal[k]) / v->DISPCLK; } else v->WritebackDelay[v->VoltageLevel][k] = 0; @@ -2533,9 +2533,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHRatio[j], v->WritebackVRatio[j], v->WritebackVTaps[j], - v->WritebackDestinationWidth[j], - v->WritebackDestinationHeight[j], - v->WritebackSourceHeight[j], + (int)v->WritebackDestinationWidth[j], + (int)v->WritebackDestinationHeight[j], + (int)v->WritebackSourceHeight[j], v->HTotal[k]) / v->DISPCLK); } } @@ -2548,7 +2548,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j]; for (k = 0; k < v->NumberOfActivePlanes; ++k) { - v->MaxVStartupLines[k] = + v->MaxVStartupLines[k] = (unsigned int)( (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ? dml_floor((v->VTotal[k] - v->VActive[k]) / 2.0, 1.0) : v->VTotal[k] - v->VActive[k] @@ -2557,7 +2557,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman dml_ceil( (double) v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), - 1)); + 1))); if (v->MaxVStartupLines[k] > 1023) v->MaxVStartupLines[k] = 1023; @@ -2570,7 +2570,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->MaximumMaxVStartupLines = 0; for (k = 0; k < v->NumberOfActivePlanes; ++k) - v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); + v->MaximumMaxVStartupLines = (unsigned int)dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); // VBA_DELTA // We don't really care to iterate between the various prefetch modes @@ -2639,7 +2639,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman (unsigned int) (v->SwathWidthY[k] / v->HRatio[k]), v->OutputFormat[k], v->MaxInterDCNTileRepeaters, - dml_min(v->VStartupLines, v->MaxVStartupLines[k]), + (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]), v->MaxVStartupLines[k], v->GPUVMMaxPageTableLevels, v->GPUVMEnable, @@ -2653,15 +2653,15 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->UrgentLatency, v->UrgentExtraLatency, v->TCalc, - v->PDEAndMetaPTEBytesFrame[k], - v->MetaRowByte[k], - v->PixelPTEBytesPerRow[k], + (unsigned int)v->PDEAndMetaPTEBytesFrame[k], + (unsigned int)v->MetaRowByte[k], + (unsigned int)v->PixelPTEBytesPerRow[k], v->PrefetchSourceLinesY[k], - v->SwathWidthY[k], + (unsigned int)v->SwathWidthY[k], v->VInitPreFillY[k], v->MaxNumSwathY[k], v->PrefetchSourceLinesC[k], - v->SwathWidthC[k], + (unsigned int)v->SwathWidthC[k], v->VInitPreFillC[k], v->MaxNumSwathC[k], v->swath_width_luma_ub[k], @@ -2692,7 +2692,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%0d Prefetch cal result=%0d\n", __func__, k, v->ErrorResult[k]); #endif - v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]); + v->VStartup[k] = (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]); } v->NoEnoughUrgentLatencyHiding = false; @@ -2846,8 +2846,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->TotImmediateFlipBytes = 0; for (k = 0; k < v->NumberOfActivePlanes; ++k) { - v->TotImmediateFlipBytes = v->TotImmediateFlipBytes - + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]); + v->TotImmediateFlipBytes = (unsigned int)(v->TotImmediateFlipBytes + + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k])); } for (k = 0; k < v->NumberOfActivePlanes; ++k) { CalculateFlipSchedule( @@ -3159,10 +3159,10 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP); - v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((v->VTotal[k] - v->VFrontPorch[k]) / 2.0, 1.0) : v->VTotal[k]) + v->MIN_DST_Y_NEXT_START[k] = (unsigned int)(((isInterlaceTiming ? dml_floor((v->VTotal[k] - v->VFrontPorch[k]) / 2.0, 1.0) : v->VTotal[k]) - v->VFrontPorch[k]) + dml_max(1.0, dml_ceil(v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1.0)) - + dml_floor(4.0 * v->TSetup[k] / (v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0; + + dml_floor(4.0 * v->TSetup[k] / (v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0); v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]); @@ -3438,7 +3438,7 @@ static void CalculateVupdateAndDynamicMetadataParameters( TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2 / DPPCLK + 3 / DISPCLK); *VUpdateWidthPix = dml_ceil((14.0 / DCFClkDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime) * PixelClock, 1.0); *VReadyOffsetPix = dml_ceil(dml_max(150.0 / DPPCLK, TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / DPPCLK) * PixelClock, 1.0); - *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1); + *VUpdateOffsetPix = (unsigned int)dml_ceil(HTotal / 4.0, 1); *TSetup = (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock; *Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK; *Tdmec = HTotal / PixelClock; @@ -3723,17 +3723,17 @@ static noinline void CalculatePrefetchSchedulePerPlane( mode_lib, HostVMInefficiencyFactor, &myPipe, - v->DSCDelayPerState[i][k], + (unsigned int)v->DSCDelayPerState[i][k], v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater, v->DPPCLKDelaySCL, v->DPPCLKDelaySCLLBOnly, v->DPPCLKDelayCNVCCursor, v->DISPCLKDelaySubtotal, - v->SwathWidthYThisState[k] / v->HRatio[k], + (unsigned int)(v->SwathWidthYThisState[k] / v->HRatio[k]), v->OutputFormat[k], v->MaxInterDCNTileRepeaters, - dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), - v->MaximumVStartup[i][j][k], + (unsigned int)dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), + (unsigned int)v->MaximumVStartup[i][j][k], v->GPUVMMaxPageTableLevels, v->GPUVMEnable, v->HostVMEnable, @@ -3746,15 +3746,15 @@ static noinline void CalculatePrefetchSchedulePerPlane( v->UrgLatency[i], v->ExtraLatency, v->TimeCalc, - v->PDEAndMetaPTEBytesPerFrame[i][j][k], - v->MetaRowBytes[i][j][k], - v->DPTEBytesPerRow[i][j][k], + (unsigned int)v->PDEAndMetaPTEBytesPerFrame[i][j][k], + (unsigned int)v->MetaRowBytes[i][j][k], + (unsigned int)v->DPTEBytesPerRow[i][j][k], v->PrefetchLinesY[i][j][k], - v->SwathWidthYThisState[k], + (unsigned int)v->SwathWidthYThisState[k], v->PrefillY[k], v->MaxNumSwY[k], v->PrefetchLinesC[i][j][k], - v->SwathWidthCThisState[k], + (unsigned int)v->SwathWidthCThisState[k], v->PrefillC[k], v->MaxNumSwC[k], v->swath_width_luma_ub_this_state[k], @@ -3785,7 +3785,8 @@ static noinline void CalculatePrefetchSchedulePerPlane( static void PatchDETBufferSizeInKByte(unsigned int NumberOfActivePlanes, int NoOfDPPThisState[], unsigned int config_return_buffer_size_in_kbytes, unsigned int DETBufferSizeInKByte[]) { - int i, total_pipes = 0; + int total_pipes = 0; + unsigned int i; for (i = 0; i < NumberOfActivePlanes; i++) total_pipes += NoOfDPPThisState[i]; DETBufferSizeInKByte[0] = ((config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB) / 64 / total_pipes) * 64; @@ -3800,8 +3801,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l { struct vba_vars_st *v = &mode_lib->vba; - int i, j; - unsigned int k, m; + int idx; + unsigned int i, j, k, m; int ReorderingBytes; int MinPrefetchMode = 0, MaxPrefetchMode = 2; bool NoChroma = true; @@ -3954,9 +3955,9 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->WritebackHTaps[k], v->WritebackVTaps[k], v->WritebackSourceWidth[k], - v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationWidth[k], v->HTotal[k], - v->WritebackLineBufferSize)); + (unsigned int)v->WritebackLineBufferSize)); } } for (k = 0; k < v->NumberOfActivePlanes; k++) { @@ -4003,17 +4004,17 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l int MaximumSwathWidthSupportChroma; if (v->SurfaceTiling[k] == dm_sw_linear) { - MaximumSwathWidthSupportLuma = 8192.0; + MaximumSwathWidthSupportLuma = (int)8192.0; } else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) { - MaximumSwathWidthSupportLuma = 2880.0; + MaximumSwathWidthSupportLuma = (int)2880.0; } else if (v->SourcePixelFormat[k] == dm_rgbe_alpha) { - MaximumSwathWidthSupportLuma = 3840.0; + MaximumSwathWidthSupportLuma = (int)3840.0; } else { - MaximumSwathWidthSupportLuma = 5760.0; + MaximumSwathWidthSupportLuma = (int)5760.0; } if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) { - MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma / 2.0; + MaximumSwathWidthSupportChroma = (int)(MaximumSwathWidthSupportLuma / 2.0); } else { MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma; } @@ -4245,7 +4246,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->DISPCLK_DPPCLK_Support[i][j] = false; } } - v->TotalNumberOfActiveDPP[i][j] = 0.0; + v->TotalNumberOfActiveDPP[i][j] = 0; for (k = 0; k < v->NumberOfActivePlanes; k++) { v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k]; } @@ -4282,7 +4283,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (k = 0; k < v->NumberOfActivePlanes; ++k) { if (v->BlendingAndTiming[k] == k) { if (v->PixelClockBackEnd[k] > 3200) { - v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); + v->NumberOfDSCSlices[k] = (unsigned int)dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); } else if (v->PixelClockBackEnd[k] > 1360) { v->NumberOfDSCSlices[k] = 8; } else if (v->PixelClockBackEnd[k] > 680) { @@ -4344,7 +4345,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->PHYCLKD18PerState[k] >= 10000.0 / 18.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 10000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4363,7 +4364,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->LinkDSCEnable = true; v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 10000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4386,7 +4387,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->PHYCLKD18PerState[k] >= 13500.0 / 18.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 13500, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4405,7 +4406,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->LinkDSCEnable = true; v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 13500, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4428,7 +4429,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->PHYCLKD18PerState[k] >= 20000.0 / 18.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 20000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4447,7 +4448,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->LinkDSCEnable = true; v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 20000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4470,7 +4471,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l if (v->PHYCLKPerState[i] >= 270.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 2700, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4490,7 +4491,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 5400, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4510,7 +4511,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 8100, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4608,7 +4609,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->DSCDelayPerState[i][k] = dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k], v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); @@ -4617,7 +4618,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l * (dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k] / 2, v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); @@ -4626,7 +4627,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l * (dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k] / 4, v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); @@ -4716,14 +4717,14 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->RequiredDPPCLKThisState, v->ReadBandwidthLuma, v->ReadBandwidthChroma, - v->ReturnBusWidth, + (int)v->ReturnBusWidth, &v->ProjectedDCFCLKDeepSleep[i][j]); for (k = 0; k < v->NumberOfActivePlanes; ++k) { v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k]; v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k]; - v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k]; - v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k]; + v->SwathWidthYAllStates[i][j][k] = (unsigned int)v->SwathWidthYThisState[k]; + v->SwathWidthCAllStates[i][j][k] = (unsigned int)v->SwathWidthCThisState[k]; v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k]; v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k]; v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k]; @@ -4748,8 +4749,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k]; v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k]; v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k]; - v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k]; - v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k]; + v->DETBufferSizeYThisState[k] = (unsigned int)v->DETBufferSizeYAllStates[i][j][k]; + v->DETBufferSizeCThisState[k] = (unsigned int)v->DETBufferSizeCAllStates[i][j][k]; } v->TotalNumberOfDCCActiveDPP[i][j] = 0; @@ -4782,16 +4783,16 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SurfaceTiling[k], v->BytePerPixelC[k], v->SourceScan[k], - v->SwathWidthCThisState[k], + (unsigned int)v->SwathWidthCThisState[k], v->ViewportHeightChroma[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForChroma, v->PitchC[k], - 0.0, + 0, &v->MacroTileWidthC[k], &v->MetaRowBytesC, &v->DPTEBytesPerRowC, @@ -4824,8 +4825,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma; v->PTEBufferSizeInRequestsForChroma = 0; v->PDEAndMetaPTEBytesPerFrameC = 0.0; - v->MetaRowBytesC = 0.0; - v->DPTEBytesPerRowC = 0.0; + v->MetaRowBytesC = 0; + v->DPTEBytesPerRowC = 0; v->PrefetchLinesC[i][j][k] = 0.0; v->PTEBufferSizeNotExceededC[i][j][k] = true; } @@ -4838,13 +4839,13 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SurfaceTiling[k], v->BytePerPixelY[k], v->SourceScan[k], - v->SwathWidthYThisState[k], + (unsigned int)v->SwathWidthYThisState[k], v->ViewportHeight[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForLuma, v->PitchY[k], v->DCCMetaPitchY[k], @@ -4978,9 +4979,9 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->WritebackHRatio[k], v->WritebackVRatio[k], v->WritebackVTaps[k], - v->WritebackDestinationWidth[k], - v->WritebackDestinationHeight[k], - v->WritebackSourceHeight[k], + (int)v->WritebackDestinationWidth[k], + (int)v->WritebackDestinationHeight[k], + (int)v->WritebackSourceHeight[k], v->HTotal[k]) / v->RequiredDISPCLK[i][j]; } else { v->WritebackDelayTime[k] = 0.0; @@ -4995,9 +4996,9 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->WritebackHRatio[m], v->WritebackVRatio[m], v->WritebackVTaps[m], - v->WritebackDestinationWidth[m], - v->WritebackDestinationHeight[m], - v->WritebackSourceHeight[m], + (int)v->WritebackDestinationWidth[m], + (int)v->WritebackDestinationHeight[m], + (int)v->WritebackSourceHeight[m], v->HTotal[m]) / v->RequiredDISPCLK[i][j]); } } @@ -5030,11 +5031,11 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } - ReorderingBytes = v->NumberOfChannels + ReorderingBytes = (int)(v->NumberOfChannels * dml_max3( v->UrgentOutOfOrderReturnPerChannelPixelDataOnly, v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - v->UrgentOutOfOrderReturnPerChannelVMDataOnly); + v->UrgentOutOfOrderReturnPerChannelVMDataOnly)); for (i = 0; i < v->soc.num_states; ++i) { for (j = 0; j <= 1; ++j) { @@ -5137,8 +5138,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k]; v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k]; v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k]; - v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k]; - v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k]; + v->DETBufferSizeYThisState[k] = (unsigned int)v->DETBufferSizeYAllStates[i][j][k]; + v->DETBufferSizeCThisState[k] = (unsigned int)v->DETBufferSizeCAllStates[i][j][k]; } VMDataOnlyReturnBWPerState = dml_min( @@ -5152,7 +5153,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l HostVMInefficiencyFactor = v->ReturnBWPerState[i][j] / VMDataOnlyReturnBWPerState; v->ExtraLatency = CalculateExtraLatency( - v->RoundTripPingLatencyCycles, + (int)v->RoundTripPingLatencyCycles, ReorderingBytes, v->DCFCLKState[i][j], v->TotalNumberOfActiveDPP[i][j], @@ -5285,11 +5286,11 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l * v->UrgentBurstFactorChromaPre[k]) + v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]); } - v->TotImmediateFlipBytes = 0.0; + v->TotImmediateFlipBytes = 0; for (k = 0; k < v->NumberOfActivePlanes; k++) { - v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + v->TotImmediateFlipBytes = (unsigned int)(v->TotImmediateFlipBytes + v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] + v->MetaRowBytes[i][j][k] - + v->DPTEBytesPerRow[i][j][k]); + + v->DPTEBytesPerRow[i][j][k])); } for (k = 0; k < v->NumberOfActivePlanes; k++) { @@ -5451,46 +5452,53 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } /*Mode Support, Voltage State and SOC Configuration*/ - for (i = v->soc.num_states - 1; i >= 0; i--) { + for (idx = (int)v->soc.num_states - 1; idx >= 0; idx--) { for (j = 0; j < 2; j++) { - if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true && v->ViewportSizeSupport[i][j] == true - && v->LinkCapacitySupport[i] == true && !P2IWith420 && !DSCOnlyIfNecessaryWithBPP - && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false - && v->DTBCLKRequiredMoreThanSupported[i] == false - && v->ROBSupport[i][j] == true && v->DISPCLK_DPPCLK_Support[i][j] == true - && v->TotalAvailablePipesSupport[i][j] == true && EnoughWritebackUnits == true + if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true + && v->ViewportSizeSupport[idx][j] == true + && v->LinkCapacitySupport[idx] == true && !P2IWith420 + && !DSCOnlyIfNecessaryWithBPP + && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[idx] == true + && v->NotEnoughDSCUnits[idx] == false + && v->DTBCLKRequiredMoreThanSupported[idx] == false + && v->ROBSupport[idx][j] == true && v->DISPCLK_DPPCLK_Support[idx][j] == true + && v->TotalAvailablePipesSupport[idx][j] == true && EnoughWritebackUnits == true && v->WritebackLatencySupport == true && v->WritebackScaleRatioAndTapsSupport == true - && v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false - && v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true - && v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true - && v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false + && v->CursorSupport == true && v->PitchSupport == true + && ViewportExceedsSurface == false + && v->PrefetchSupported[idx][j] == true + && v->DynamicMetadataSupported[idx][j] == true + && v->TotalVerticalActiveBandwidthSupport[idx][j] == true + && v->VRatioInPrefetchSupported[idx][j] == true + && v->PTEBufferSizeNotExceeded[idx][j] == true + && v->NonsupportedDSCInputBPC == false && ((v->HostVMEnable == false && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required) - || v->ImmediateFlipSupportedForState[i][j] == true) + || v->ImmediateFlipSupportedForState[idx][j] == true) && FMTBufferExceeded == false) { - v->ModeSupport[i][j] = true; + v->ModeSupport[idx][j] = true; } else { - v->ModeSupport[i][j] = false; + v->ModeSupport[idx][j] = false; #ifdef __DML_VBA_DEBUG__ if (v->ScaleRatioAndTapsSupport == false) dml_print("DML SUPPORT: ScaleRatioAndTapsSupport failed"); if (v->SourceFormatPixelAndScanSupport == false) dml_print("DML SUPPORT: SourceFormatPixelAndScanSupport failed"); - if (v->ViewportSizeSupport[i][j] == false) + if (v->ViewportSizeSupport[idx][j] == false) dml_print("DML SUPPORT: ViewportSizeSupport failed"); - if (v->LinkCapacitySupport[i] == false) + if (v->LinkCapacitySupport[idx] == false) dml_print("DML SUPPORT: LinkCapacitySupport failed"); - if (v->ODMCombine4To1SupportCheckOK[i] == false) + if (v->ODMCombine4To1SupportCheckOK[idx] == false) dml_print("DML SUPPORT: DSC422NativeNotSupported failed"); - if (v->NotEnoughDSCUnits[i] == true) + if (v->NotEnoughDSCUnits[idx] == true) dml_print("DML SUPPORT: NotEnoughDSCUnits"); - if (v->DTBCLKRequiredMoreThanSupported[i] == true) + if (v->DTBCLKRequiredMoreThanSupported[idx] == true) dml_print("DML SUPPORT: DTBCLKRequiredMoreThanSupported"); - if (v->ROBSupport[i][j] == false) + if (v->ROBSupport[idx][j] == false) dml_print("DML SUPPORT: ROBSupport failed"); - if (v->DISPCLK_DPPCLK_Support[i][j] == false) + if (v->DISPCLK_DPPCLK_Support[idx][j] == false) dml_print("DML SUPPORT: DISPCLK_DPPCLK_Support failed"); - if (v->TotalAvailablePipesSupport[i][j] == false) + if (v->TotalAvailablePipesSupport[idx][j] == false) dml_print("DML SUPPORT: DSC422NativeNotSupported failed"); if (EnoughWritebackUnits == false) dml_print("DML SUPPORT: DSC422NativeNotSupported failed"); @@ -5504,21 +5512,21 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l dml_print("DML SUPPORT: PitchSupport failed"); if (ViewportExceedsSurface == true) dml_print("DML SUPPORT: ViewportExceedsSurface failed"); - if (v->PrefetchSupported[i][j] == false) + if (v->PrefetchSupported[idx][j] == false) dml_print("DML SUPPORT: PrefetchSupported failed"); - if (v->DynamicMetadataSupported[i][j] == false) + if (v->DynamicMetadataSupported[idx][j] == false) dml_print("DML SUPPORT: DSC422NativeNotSupported failed"); - if (v->TotalVerticalActiveBandwidthSupport[i][j] == false) + if (v->TotalVerticalActiveBandwidthSupport[idx][j] == false) dml_print("DML SUPPORT: TotalVerticalActiveBandwidthSupport failed"); - if (v->VRatioInPrefetchSupported[i][j] == false) + if (v->VRatioInPrefetchSupported[idx][j] == false) dml_print("DML SUPPORT: VRatioInPrefetchSupported failed"); - if (v->PTEBufferSizeNotExceeded[i][j] == false) + if (v->PTEBufferSizeNotExceeded[idx][j] == false) dml_print("DML SUPPORT: PTEBufferSizeNotExceeded failed"); if (v->NonsupportedDSCInputBPC == true) dml_print("DML SUPPORT: NonsupportedDSCInputBPC failed"); if (!((v->HostVMEnable == false && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required) - || v->ImmediateFlipSupportedForState[i][j] == true)) + || v->ImmediateFlipSupportedForState[idx][j] == true)) dml_print("DML SUPPORT: ImmediateFlipRequirement failed"); if (FMTBufferExceeded == true) dml_print("DML SUPPORT: FMTBufferExceeded failed"); @@ -5529,11 +5537,12 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l { unsigned int MaximumMPCCombine = 0; - for (i = v->soc.num_states; i >= 0; i--) { - if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) { - v->VoltageLevel = i; - v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true; - if (v->ModeSupport[i][0] == true) { + for (idx = (int)v->soc.num_states; idx >= 0; idx--) { + if (idx == (int)v->soc.num_states || v->ModeSupport[idx][0] == true + || v->ModeSupport[idx][1] == true) { + v->VoltageLevel = idx; + v->ModeIsSupported = v->ModeSupport[idx][0] == true || v->ModeSupport[idx][1] == true; + if (v->ModeSupport[idx][0] == true) { MaximumMPCCombine = 0; } else { MaximumMPCCombine = 1; @@ -5541,7 +5550,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine]; - for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { + for (k = 0; k < v->NumberOfActivePlanes; k++) { v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k]; v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k]; } @@ -5599,7 +5608,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank; double WritebackDRAMClockChangeLatencyHiding; double TotalPixelBW = 0.0; - int k, j; + unsigned int k, j; v->UrgentWatermark = UrgentLatency + ExtraLatency; @@ -5644,13 +5653,13 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( for (k = 0; k < v->NumberOfActivePlanes; ++k) { double EffectiveDETBufferSizeY = DETBufferSizeY[k]; - v->LBLatencyHidingSourceLinesY = dml_min( + v->LBLatencyHidingSourceLinesY = (unsigned int)(dml_min( (double) v->MaxLineBufferLines, - dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1); + dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1)); - v->LBLatencyHidingSourceLinesC = dml_min( + v->LBLatencyHidingSourceLinesC = (unsigned int)(dml_min( (double) v->MaxLineBufferLines, - dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1); + dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1)); EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]); @@ -5662,11 +5671,11 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( } LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; - LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); + LinesInDETYRoundedDownToSwath[k] = (unsigned int)dml_floor(LinesInDETY[k], SwathHeightY[k]); FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k]; if (BytePerPixelDETC[k] > 0) { LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k]; - LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]); + LinesInDETCRoundedDownToSwath = (unsigned int)dml_floor(LinesInDETC, SwathHeightC[k]); FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k]; } else { LinesInDETC = 0; @@ -5787,7 +5796,7 @@ static void CalculateDCFCLKDeepSleep( double DisplayPipeLineDeliveryTimeLuma; double DisplayPipeLineDeliveryTimeChroma; double ReadBandwidth = 0.0; - int k; + unsigned int k; for (k = 0; k < NumberOfActivePlanes; ++k) { @@ -5938,7 +5947,7 @@ static void CalculatePixelDeliveryTimes( double CursorRequestDeliveryTimePrefetch[]) { double req_per_swath_ub; - int k; + unsigned int k; for (k = 0; k < NumberOfActivePlanes; ++k) { if (VRatio[k] <= 1) { @@ -6012,7 +6021,7 @@ static void CalculatePixelDeliveryTimes( for (k = 0; k < NumberOfActivePlanes; ++k) { int cursor_req_per_width; - cursor_req_per_width = dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1); + cursor_req_per_width = (int)dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1); if (NumberOfCursors[k] > 0) { if (VRatio[k] <= 1) { CursorRequestDeliveryTime[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width; @@ -6146,7 +6155,7 @@ static void CalculateMetaAndPTETimes( } else { meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; - meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / meta_chunk_width_chroma; + meta_chunk_per_row_int_chroma = (unsigned int)((double) meta_row_width_chroma[k] / meta_chunk_width_chroma); meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma; if (SourceScan[k] != dm_vert) { meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k]; @@ -6179,7 +6188,7 @@ static void CalculateMetaAndPTETimes( } else { dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k]; } - dpte_groups_per_row_luma_ub = dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1); + dpte_groups_per_row_luma_ub = (unsigned int)dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1); time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; @@ -6193,7 +6202,7 @@ static void CalculateMetaAndPTETimes( } else { dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqHeightC[k]; } - dpte_groups_per_row_chroma_ub = dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1); + dpte_groups_per_row_chroma_ub = (unsigned int)dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1); time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; @@ -6235,34 +6244,34 @@ static void CalculateVMGroupAndRequestTimes( (void)dpte_row_width_chroma_ub; int num_group_per_lower_vm_stage; int num_req_per_lower_vm_stage; - int k; + unsigned int k; for (k = 0; k < NumberOfActivePlanes; ++k) { if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) { if (DCCEnable[k] == false) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)(dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (GPUVMMaxPageTableLevels == 1) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)(dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = 2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + num_group_per_lower_vm_stage = (int)(2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = 1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)(1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)); } } } @@ -6573,8 +6582,8 @@ static void CalculateStutterEfficiency( #endif *StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitTime + StutterBurstTime) / *StutterPeriod) * 100; *Z8StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitZ8Time + StutterBurstTime) / *StutterPeriod) * 100; - *NumberOfStutterBurstsPerFrame = (*StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); - *Z8NumberOfStutterBurstsPerFrame = (*Z8StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); + *NumberOfStutterBurstsPerFrame = (int)(*StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); + *Z8NumberOfStutterBurstsPerFrame = (int)(*Z8StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); } else { *StutterEfficiencyNotIncludingVBlank = 0.; *Z8StutterEfficiencyNotIncludingVBlank = 0.; @@ -6676,12 +6685,12 @@ static void CalculateSwathAndDETConfiguration( int MaximumSwathHeightC[DC__NUM_DPP__MAX]; int MinimumSwathHeightY; int MinimumSwathHeightC; - int RoundedUpMaxSwathSizeBytesY; - int RoundedUpMaxSwathSizeBytesC; - int RoundedUpMinSwathSizeBytesY; - int RoundedUpMinSwathSizeBytesC; - int RoundedUpSwathSizeBytesY; - int RoundedUpSwathSizeBytesC; + unsigned int RoundedUpMaxSwathSizeBytesY; + unsigned int RoundedUpMaxSwathSizeBytesC; + unsigned int RoundedUpMinSwathSizeBytesY; + unsigned int RoundedUpMinSwathSizeBytesC; + unsigned int RoundedUpSwathSizeBytesY; + unsigned int RoundedUpSwathSizeBytesC; double SwathWidthSingleDPP[DC__NUM_DPP__MAX]; double SwathWidthSingleDPPChroma[DC__NUM_DPP__MAX]; int k; @@ -6755,17 +6764,17 @@ static void CalculateSwathAndDETConfiguration( } } - RoundedUpMaxSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k]; - RoundedUpMinSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MinimumSwathHeightY; + RoundedUpMaxSwathSizeBytesY = (int)(swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k]); + RoundedUpMinSwathSizeBytesY = (int)(swath_width_luma_ub[k] * BytePerPixDETY[k] * MinimumSwathHeightY); if (SourcePixelFormat[k] == dm_420_10) { - RoundedUpMaxSwathSizeBytesY = dml_ceil((double) RoundedUpMaxSwathSizeBytesY, 256); - RoundedUpMinSwathSizeBytesY = dml_ceil((double) RoundedUpMinSwathSizeBytesY, 256); + RoundedUpMaxSwathSizeBytesY = (int)dml_ceil((double) RoundedUpMaxSwathSizeBytesY, 256); + RoundedUpMinSwathSizeBytesY = (int)dml_ceil((double) RoundedUpMinSwathSizeBytesY, 256); } - RoundedUpMaxSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k]; - RoundedUpMinSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MinimumSwathHeightC; + RoundedUpMaxSwathSizeBytesC = (int)(swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k]); + RoundedUpMinSwathSizeBytesC = (int)(swath_width_chroma_ub[k] * BytePerPixDETC[k] * MinimumSwathHeightC); if (SourcePixelFormat[k] == dm_420_10) { - RoundedUpMaxSwathSizeBytesC = dml_ceil(RoundedUpMaxSwathSizeBytesC, 256); - RoundedUpMinSwathSizeBytesC = dml_ceil(RoundedUpMinSwathSizeBytesC, 256); + RoundedUpMaxSwathSizeBytesC = (int)dml_ceil(RoundedUpMaxSwathSizeBytesC, 256); + RoundedUpMinSwathSizeBytesC = (int)dml_ceil(RoundedUpMinSwathSizeBytesC, 256); } if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= DETBufferSizeInKByte * 1024 / 2) { @@ -6794,14 +6803,14 @@ static void CalculateSwathAndDETConfiguration( { double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64); if (SwathHeightC[k] == 0) { - DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024; + DETBufferSizeY[k] = (unsigned int)(actDETBufferSizeInKByte * 1024); DETBufferSizeC[k] = 0; } else if (RoundedUpSwathSizeBytesY <= 1.5 * RoundedUpSwathSizeBytesC) { - DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024 / 2; - DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 2; + DETBufferSizeY[k] = (unsigned int)(actDETBufferSizeInKByte * 1024 / 2); + DETBufferSizeC[k] = (unsigned int)(actDETBufferSizeInKByte * 1024 / 2); } else { - DETBufferSizeY[k] = dml_floor(actDETBufferSizeInKByte * 1024 * 2 / 3, 1024); - DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 3; + DETBufferSizeY[k] = (unsigned int)dml_floor(actDETBufferSizeInKByte * 1024 * 2 / 3, 1024); + DETBufferSizeC[k] = (unsigned int)(actDETBufferSizeInKByte * 1024 / 3); } if (RoundedUpMinSwathSizeBytesY + RoundedUpMinSwathSizeBytesC > actDETBufferSizeInKByte * 1024 / 2 || SwathWidth[k] > MaximumSwathWidthLuma[k] @@ -6901,8 +6910,8 @@ static void CalculateSwathWidth( SwathWidthC[k] = SwathWidthSingleDPPC[k]; } { - int surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); - int surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); + int surface_width_ub_l = (int)dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); + int surface_height_ub_l = (int)dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l); @@ -6911,11 +6920,11 @@ static void CalculateSwathWidth( if (SourceScan[k] != dm_vert) { MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k]; MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k]; - swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]); + swath_width_luma_ub[k] = (int)dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]); if (BytePerPixC[k] > 0) { - int surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); + int surface_width_ub_c = (int)dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); - swath_width_chroma_ub[k] = dml_min( + swath_width_chroma_ub[k] = (int)dml_min( surface_width_ub_c, (int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]); } else { @@ -6924,11 +6933,11 @@ static void CalculateSwathWidth( } else { MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k]; MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k]; - swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]); + swath_width_luma_ub[k] = (int)dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]); if (BytePerPixC[k] > 0) { - int surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); + int surface_height_ub_c = (int)dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); - swath_width_chroma_ub[k] = dml_min( + swath_width_chroma_ub[k] = (int)dml_min( surface_height_ub_c, (int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]); } else { @@ -7010,9 +7019,9 @@ static double CalculateExtraLatencyBytes( if (HostVMMinPageSize < 2048) { HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; } else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); } else { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } } else { HostVMDynamicLevels = 0; @@ -7052,7 +7061,9 @@ static noinline_for_stack void UseMinimumDCFCLK( int ReorderingBytes) { struct vba_vars_st *v = &mode_lib->vba; - int dummy1, i, j, k; + int dummy1; + unsigned int j, k; + unsigned int i; double NormalEfficiency, dummy2, dummy3; double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2]; @@ -7079,9 +7090,8 @@ static noinline_for_stack void UseMinimumDCFCLK( + v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]); } - for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) { + for (k = 0; k < v->NumberOfActivePlanes; ++k) NoOfDPPState[k] = v->NoOfDPP[i][j][k]; - } MinimumTWait = CalculateTWait(MaxPrefetchMode, v->FinalDRAMClockChangeLatency, v->UrgLatency[i], v->SREnterPlusExitTime); NonDPTEBandwidth = v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j]; @@ -7182,9 +7192,8 @@ static noinline_for_stack void UseMinimumDCFCLK( } } DCFCLKRequiredForPeakBandwidth = 0; - for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) { + for (k = 0; k < v->NumberOfActivePlanes; ++k) DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k]; - } MinimumTvmPlus2Tr0 = v->UrgLatency[i] * (v->GPUVMEnable == true ? (v->HostVMEnable == true ? @@ -7222,7 +7231,7 @@ static void CalculateUnboundedRequestAndCompressedBufferSize( double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64); *UnboundedRequestEnabled = UnboundedRequest(UseUnboundedRequestingFinal, TotalActiveDPP, NoChromaPlanes, Output[0]); - *CompressedBufferSizeInkByte = ( + *CompressedBufferSizeInkByte = (int)( *UnboundedRequestEnabled == true ? ConfigReturnBufferSizeInKByte - TotalActiveDPP * actDETBufferSizeInKByte : ConfigReturnBufferSizeInKByte - MaxNumDPP * actDETBufferSizeInKByte); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c index dfa1bc31eb0a..ada80b3086ff 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c @@ -117,11 +117,11 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_s extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 1) - 3; + rq_regs->rq_regs_l.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 1) - 3); if (rq_param->yuv420) { extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 1) - 3; + rq_regs->rq_regs_c.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 1) - 3); } rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); @@ -141,12 +141,12 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_s // Note: detile_buf_plane1_addr is in unit of 1KB if (rq_param->yuv420) { if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/2 to chroma)\n", __func__, detile_buf_plane1_addr); #endif } else { - detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0; // 2/3 to luma + detile_buf_plane1_addr = (unsigned int)(dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0); // 2/3 to luma #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/3 chroma)\n", __func__, detile_buf_plane1_addr); #endif @@ -189,8 +189,8 @@ static void handle_det_buf_split(struct display_mode_lib *mode_lib, display_rq_p #endif if (rq_param->yuv420_10bpc) { - full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256; - full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256; + full_swath_bytes_packed_l = (unsigned int)(dml_round_to_multiple((unsigned int)(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0), 256, 1) + 256); + full_swath_bytes_packed_c = (unsigned int)(dml_round_to_multiple((unsigned int)(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0), 256, 1) + 256); #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_l); dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_c); @@ -421,7 +421,7 @@ static void get_meta_and_pte_attr( // "/2" is like square root // blk is vertical biased if (tiling != dm_sw_linear) - log2_blk_height = log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); + log2_blk_height = (unsigned int)(log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1)); else log2_blk_height = 0; // blk height of 1 @@ -574,7 +574,7 @@ static void get_meta_and_pte_attr( if (surf_linear) { unsigned int dpte_row_height; - log2_dpte_row_height_linear = dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); + log2_dpte_row_height_linear = (unsigned int)(dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1)); dml_print("DML_DLG: %s: is_chroma = %d\n", __func__, is_chroma); dml_print("DML_DLG: %s: dpte_buf_in_pte_reqs = %d\n", __func__, dpte_buf_in_pte_reqs); @@ -640,7 +640,7 @@ static void get_meta_and_pte_attr( // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, // the upper bound for the dpte groups per row is as follows. - rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); + rq_dlg_param->dpte_groups_per_row_ub = (unsigned int)dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); } static void get_surf_rq_param( @@ -665,7 +665,7 @@ static void get_surf_rq_param( vp_height = pipe_param->src.viewport_height_c; data_pitch = pipe_param->src.data_pitch_c; meta_pitch = pipe_param->src.meta_pitch_c; - surface_height = pipe_param->src.surface_height_y / 2.0; + surface_height = (unsigned int)(pipe_param->src.surface_height_y / 2.0); } else { vp_width = pipe_param->src.viewport_width / ppe; vp_height = pipe_param->src.viewport_height; @@ -683,18 +683,18 @@ static void get_surf_rq_param( access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed hactive_odm = pipe_param->dest.hactive / ((unsigned int) pipe_param->dest.odm_combine * 2); if (is_chroma) { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width; - src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width); + src_hactive_odm = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm); } else { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width; - src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width); + src_hactive_odm = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm); } if (access_dir == 0) { - vp_width = dml_min(full_src_vp_width, src_hactive_odm); + vp_width = (unsigned int)dml_min(full_src_vp_width, src_hactive_odm); dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width); } else { - vp_height = dml_min(full_src_vp_width, src_hactive_odm); + vp_height = (unsigned int)dml_min(full_src_vp_width, src_hactive_odm); dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height); } @@ -814,7 +814,7 @@ static void calculate_ttu_cursor( cur_req_size = 256; } - cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); + cur_req_width = (unsigned int)((double) cur_req_size / ((double) cur_bit_per_pixel / 8.0)); cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width; cur_req_per_width = cur_width_ub / (double) cur_req_width; hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor @@ -1051,8 +1051,8 @@ static void dml_rq_dlg_get_dlg_params( if (interlaced) vstartup_start = vstartup_start / 2; - dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA - dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dst_x_after_scaler = (unsigned int)get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dst_y_after_scaler = (unsigned int)get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA // do some adjustment on the dst_after scaler to account for odm combine mode dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n", __func__, dst_x_after_scaler); @@ -1278,9 +1278,9 @@ static void dml_rq_dlg_get_dlg_params( } if (src->dynamic_metadata_enable && src->gpuvm) - disp_dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + disp_dlg_regs->refcyc_per_vm_dmdata = (unsigned int)(get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA - disp_dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + disp_dlg_regs->dmdata_dl_delta = (unsigned int)(get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA // TTU - Luma / Chroma if (access_dir) { // vertical access @@ -1386,8 +1386,8 @@ static void dml_rq_dlg_get_dlg_params( src->cur0_src_width, (enum cursor_bpp) (src->cur0_bpp)); - vba__refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - vba__refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + vba__refcyc_per_req_delivery_pre_cur0 = (float)(get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + vba__refcyc_per_req_delivery_cur0 = (float)(get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_pre_cur0); dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_cur0); @@ -1407,7 +1407,7 @@ static void dml_rq_dlg_get_dlg_params( // Assignment to register structures disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8); - disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + disp_dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); // in terms of refclk ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); @@ -1444,23 +1444,23 @@ static void dml_rq_dlg_get_dlg_params( disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; } - disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA - disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA // Clamp to max for now if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2)); ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); @@ -1484,23 +1484,23 @@ static void dml_rq_dlg_get_dlg_params( disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (dual_plane) { disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c); if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1); // TODO: Is this the right calculation? Does htotal need to be halved? disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_c); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1); } disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1); @@ -1541,7 +1541,7 @@ static void dml_rq_dlg_get_dlg_params( disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs->qos_ramp_disable_cur0 = 0; - disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + disp_ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); print__ttu_regs_st(mode_lib, disp_ttu_regs); @@ -1572,7 +1572,7 @@ void dml31_rq_dlg_get_dlg_reg( dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes); - dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); + dlg_sys_param.total_flip_bytes = (unsigned int)get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); print__dlg_sys_params_st(mode_lib, &dlg_sys_param); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c index ab016c294ba7..29334772408e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c @@ -185,7 +185,7 @@ void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p struct _vcs_dpi_voltage_scaling_st *clock_limits = dcn3_14_soc.clock_limits; unsigned int i, closest_clk_lvl; - int max_dispclk_mhz = 0, max_dppclk_mhz = 0; + unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0; int j; dc_assert_fp_enabled(); @@ -284,11 +284,11 @@ static bool is_dual_plane(enum surface_pixel_format format) static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing) { unsigned int num_lines = 0; - unsigned int lines_time_in_ns = 1000.0 * - (((float)timing->h_total * 1000.0) / - ((float)timing->pix_clk_100hz / 10.0)); + double lines_time_in_ns = 1000.0 * + (((double)timing->h_total * 1000.0) / + ((double)timing->pix_clk_100hz / 10.0)); - num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); + num_lines = (unsigned int)dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); return num_lines; } @@ -308,7 +308,8 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt; + int pipe_cnt; + unsigned int i; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = 0; bool upscaled = false; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c index 033fde774337..d6dcebb1ab14 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c @@ -407,7 +407,7 @@ static void CalculatePixelDeliveryTimes( double CursorRequestDeliveryTimePrefetch[]); static void CalculateMetaAndPTETimes( - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, @@ -718,7 +718,7 @@ static unsigned int dscceComputeDelay( pixelsPerClock = 1; //initial transmit delay as per PPS - initalXmitDelay = dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); + initalXmitDelay = (unsigned int)dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); //compute ssm delay if (bpc == 8) @@ -1003,13 +1003,13 @@ static bool CalculatePrefetchSchedule( *Tdmdl_vm = (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true && GPUVMEnable == true ? TWait + Tvm_trips : 0); if (myPipe->ScalerEnabled) - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL); else - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly); - DPPCycles = DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor; + DPPCycles = (unsigned int)(DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor); - DISPCLKCycles = DISPCLKDelaySubtotal; + DISPCLKCycles = (unsigned int)DISPCLKDelaySubtotal; if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0) return true; @@ -1527,14 +1527,14 @@ static void CalculateDCCConfiguration( double detile_buf_vp_horz_limit; double detile_buf_vp_vert_limit; - int MAS_vp_horz_limit; - int MAS_vp_vert_limit; - int max_vp_horz_width; - int max_vp_vert_height; - int eff_surf_width_l; - int eff_surf_width_c; - int eff_surf_height_l; - int eff_surf_height_c; + unsigned int MAS_vp_horz_limit; + unsigned int MAS_vp_vert_limit; + unsigned int max_vp_horz_width; + unsigned int max_vp_vert_height; + unsigned int eff_surf_width_l; + unsigned int eff_surf_width_c; + unsigned int eff_surf_height_l; + unsigned int eff_surf_height_c; int full_swath_bytes_horz_wc_l; int full_swath_bytes_horz_wc_c; @@ -1571,11 +1571,11 @@ static void CalculateDCCConfiguration( horz_div_c = 0; if (BytePerPixelC == 0) { - swath_buf_size = DETBufferSize / 2 - 2 * 256; + swath_buf_size = (int)(DETBufferSize / 2 - 2 * 256); detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l)); detile_buf_vp_vert_limit = (double) swath_buf_size / (256.0 / RequestHeight256ByteLuma / (1 + vert_div_l)); } else { - swath_buf_size = DETBufferSize / 2 - 2 * 2 * 256; + swath_buf_size = (int)(DETBufferSize / 2 - 2 * 2 * 256); detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l) + (double) RequestHeight256ByteChroma * BytePerPixelC / (1 + horz_div_c) / (1 + yuv420)); @@ -1593,8 +1593,8 @@ static void CalculateDCCConfiguration( MAS_vp_horz_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : 5760; MAS_vp_vert_limit = (BytePerPixelC > 0 ? 2880 : 5760); - max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); - max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); + max_vp_horz_width = (int)dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); + max_vp_vert_height = (int)dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); eff_surf_width_l = (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma); eff_surf_width_c = eff_surf_width_l / (1 + yuv420); eff_surf_height_l = (SurfaceHeightLuma > max_vp_vert_height ? max_vp_vert_height : SurfaceHeightLuma); @@ -1611,10 +1611,10 @@ static void CalculateDCCConfiguration( } if (SourcePixelFormat == dm_420_10) { - full_swath_bytes_horz_wc_l = dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256); - full_swath_bytes_horz_wc_c = dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256); - full_swath_bytes_vert_wc_l = dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256); - full_swath_bytes_vert_wc_c = dml_ceil(full_swath_bytes_vert_wc_c * 2 / 3, 256); + full_swath_bytes_horz_wc_l = (int)dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256); + full_swath_bytes_horz_wc_c = (int)dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256); + full_swath_bytes_vert_wc_l = (int)dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256); + full_swath_bytes_vert_wc_c = (int)dml_ceil(full_swath_bytes_vert_wc_c * 2 / 3, 256); } if (2 * full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSize) { @@ -1777,20 +1777,20 @@ static double CalculatePrefetchSourceLines( if (!v->IgnoreViewportPositioning) { - *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; + *MaxNumSwath = (unsigned int)(dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight; else MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight; - MaxPartialSwath = dml_max(1U, MaxPartialSwath); + MaxPartialSwath = (unsigned int)dml_max(1U, MaxPartialSwath); } else { if (ViewportYStart != 0) dml_print("WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n"); - *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); + *MaxNumSwath = (unsigned int)dml_ceil(*VInitPreFill / SwathHeight, 1); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight; @@ -1865,9 +1865,9 @@ static unsigned int CalculateVMAndRowBytes( if (HostVMMinPageSize < 2048) { HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; } else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); } else { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } } @@ -1875,16 +1875,16 @@ static unsigned int CalculateVMAndRowBytes( *MetaRequestWidth = 8 * BlockWidth256Bytes; if (ScanDirection != dm_vert) { *meta_row_height = *MetaRequestHeight; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth; - *MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0; + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0); } else { *meta_row_height = *MetaRequestWidth; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight; - *MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0; + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0); } - DCCMetaSurfaceBytes = DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel / 256; + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel / 256); if (GPUVMEnable == true) { - *MetaPTEBytesFrame = (dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64; + *MetaPTEBytesFrame = (int)((dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64); MPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 1); } else { *MetaPTEBytesFrame = 0; @@ -1908,17 +1908,17 @@ static unsigned int CalculateVMAndRowBytes( if (GPUVMEnable == true && v->GPUVMMaxPageTableLevels > 1) { if (ScanDirection != dm_vert) { - *DPDE0BytesFrame = 64 + *DPDE0BytesFrame = (int)(64 * (dml_ceil( ((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } else { - *DPDE0BytesFrame = 64 + *DPDE0BytesFrame = (int)(64 * (dml_ceil( ((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } ExtraDPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 2); } else { @@ -1946,7 +1946,7 @@ static unsigned int CalculateVMAndRowBytes( if (SurfaceTiling == dm_sw_linear) { PixelPTEReqHeightPTEs = 1; *PixelPTEReqHeight = 1; - *PixelPTEReqWidth = 32768.0 / BytePerPixel; + *PixelPTEReqWidth = (unsigned int)(32768.0 / BytePerPixel); *PTERequestSize = 64; FractionOfPTEReturnDrop = 0; } else if (GPUVMMinPageSize == 4 && MacroTileSizeBytes > 4096) { @@ -1964,16 +1964,16 @@ static unsigned int CalculateVMAndRowBytes( } if (SurfaceTiling == dm_sw_linear) { - *dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); - *dpte_row_width_ub = (dml_ceil((double)(Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_height = (unsigned int)dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); + *dpte_row_width_ub = (int)((dml_ceil((double)(Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else if (ScanDirection != dm_vert) { *dpte_row_height = *PixelPTEReqHeight; - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_width_ub = (int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else { - *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth); - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight; + *dpte_row_height = (unsigned int)dml_min(*PixelPTEReqWidth, *MacroTileWidth); + *dpte_row_width_ub = (int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize; } @@ -2059,9 +2059,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHTaps[k], v->WritebackVTaps[k], v->WritebackSourceWidth[k], - v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationWidth[k], v->HTotal[k], - v->WritebackLineBufferSize)); + (unsigned int)v->WritebackLineBufferSize)); } } @@ -2247,7 +2247,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->DPPCLK, v->ReadBandwidthPlaneLuma, v->ReadBandwidthPlaneChroma, - v->ReturnBusWidth, + (int)v->ReturnBusWidth, &v->DCFCLKDeepSleep); // DSCCLK @@ -2284,7 +2284,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->DSCDelay[k] = dscceComputeDelay( v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), v->NumberOfDSCSlices[k], v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); @@ -2293,8 +2293,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman * (dscceComputeDelay( v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), - v->NumberOfDSCSlices[k] / 2.0, + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)(v->NumberOfDSCSlices[k] / 2.0), v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); } else { @@ -2302,13 +2302,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman * (dscceComputeDelay( v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), - v->NumberOfDSCSlices[k] / 4.0, + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)(v->NumberOfDSCSlices[k] / 4.0), v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); } - v->DSCDelay[k] = v->DSCDelay[k] + (v->HTotal[k] - v->HActive[k]) * dml_ceil((double) v->DSCDelay[k] / v->HActive[k], 1); - v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]; + v->DSCDelay[k] = (unsigned int)(v->DSCDelay[k] + (v->HTotal[k] - v->HActive[k]) * dml_ceil((double) v->DSCDelay[k] / v->HActive[k], 1)); + v->DSCDelay[k] = (unsigned int)(v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]); } else { v->DSCDelay[k] = 0; } @@ -2349,13 +2349,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->SurfaceTiling[k], v->BytePerPixelC[k], v->SourceScan[k], - v->SwathWidthC[k], + (unsigned int)v->SwathWidthC[k], v->ViewportHeightChroma[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForChroma, v->PitchC[k], v->DCCMetaPitchC[k], @@ -2406,13 +2406,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->SurfaceTiling[k], v->BytePerPixelY[k], v->SourceScan[k], - v->SwathWidthY[k], + (unsigned int)v->SwathWidthY[k], v->ViewportHeight[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForLuma, v->PitchY[k], v->DCCMetaPitchY[k], @@ -2478,11 +2478,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman NoChromaPlanes = false; } - ReorderBytes = v->NumberOfChannels + ReorderBytes = (int)(v->NumberOfChannels * dml_max3( v->UrgentOutOfOrderReturnPerChannelPixelDataOnly, v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - v->UrgentOutOfOrderReturnPerChannelVMDataOnly); + v->UrgentOutOfOrderReturnPerChannelVMDataOnly)); VMDataOnlyReturnBW = dml_min( dml_min(v->ReturnBusWidth * v->DCFCLK, v->FabricClock * v->FabricDatapathToDCNDataReturn) @@ -2508,7 +2508,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman HostVMInefficiencyFactor = v->ReturnBW / VMDataOnlyReturnBW; v->UrgentExtraLatency = CalculateExtraLatency( - v->RoundTripPingLatencyCycles, + (int)v->RoundTripPingLatencyCycles, ReorderBytes, v->DCFCLK, v->TotalActiveDPP, @@ -2536,9 +2536,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHRatio[k], v->WritebackVRatio[k], v->WritebackVTaps[k], - v->WritebackDestinationWidth[k], - v->WritebackDestinationHeight[k], - v->WritebackSourceHeight[k], + (int)v->WritebackDestinationWidth[k], + (int)v->WritebackDestinationHeight[k], + (int)v->WritebackSourceHeight[k], v->HTotal[k]) / v->DISPCLK; } else v->WritebackDelay[v->VoltageLevel][k] = 0; @@ -2552,9 +2552,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHRatio[j], v->WritebackVRatio[j], v->WritebackVTaps[j], - v->WritebackDestinationWidth[j], - v->WritebackDestinationHeight[j], - v->WritebackSourceHeight[j], + (int)v->WritebackDestinationWidth[j], + (int)v->WritebackDestinationHeight[j], + (int)v->WritebackSourceHeight[j], v->HTotal[k]) / v->DISPCLK); } } @@ -2588,7 +2588,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->MaximumMaxVStartupLines = 0; for (k = 0; k < v->NumberOfActivePlanes; ++k) - v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); + v->MaximumMaxVStartupLines = (unsigned int)dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); // VBA_DELTA // We don't really care to iterate between the various prefetch modes @@ -2658,7 +2658,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman (unsigned int) (v->SwathWidthY[k] / v->HRatio[k]), v->OutputFormat[k], v->MaxInterDCNTileRepeaters, - dml_min(v->VStartupLines, v->MaxVStartupLines[k]), + (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]), v->MaxVStartupLines[k], v->GPUVMMaxPageTableLevels, v->GPUVMEnable, @@ -2672,15 +2672,15 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->UrgentLatency, v->UrgentExtraLatency, v->TCalc, - v->PDEAndMetaPTEBytesFrame[k], - v->MetaRowByte[k], - v->PixelPTEBytesPerRow[k], + (unsigned int)v->PDEAndMetaPTEBytesFrame[k], + (unsigned int)v->MetaRowByte[k], + (unsigned int)v->PixelPTEBytesPerRow[k], v->PrefetchSourceLinesY[k], - v->SwathWidthY[k], + (unsigned int)v->SwathWidthY[k], v->VInitPreFillY[k], v->MaxNumSwathY[k], v->PrefetchSourceLinesC[k], - v->SwathWidthC[k], + (unsigned int)v->SwathWidthC[k], v->VInitPreFillC[k], v->MaxNumSwathC[k], v->swath_width_luma_ub[k], @@ -2711,7 +2711,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%0d Prefetch cal result=%0d\n", __func__, k, v->ErrorResult[k]); #endif - v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]); + v->VStartup[k] = (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]); } v->NoEnoughUrgentLatencyHiding = false; @@ -2865,8 +2865,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->TotImmediateFlipBytes = 0; for (k = 0; k < v->NumberOfActivePlanes; ++k) { - v->TotImmediateFlipBytes = v->TotImmediateFlipBytes - + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]); + v->TotImmediateFlipBytes = (unsigned int)(v->TotImmediateFlipBytes + + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k])); } for (k = 0; k < v->NumberOfActivePlanes; ++k) { CalculateFlipSchedule( @@ -3179,11 +3179,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP); v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]); if (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) { - v->MIN_DST_Y_NEXT_START[k] = dml_floor((v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->VStartup[k]) / 2.0, 1.0); + v->MIN_DST_Y_NEXT_START[k] = (unsigned int)dml_floor((v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->VStartup[k]) / 2.0, 1.0); } else { v->MIN_DST_Y_NEXT_START[k] = v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->VStartup[k]; } - v->MIN_DST_Y_NEXT_START[k] += dml_floor(4.0 * v->TSetup[k] / ((double)v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0; + v->MIN_DST_Y_NEXT_START[k] += (unsigned int)(dml_floor(4.0 * v->TSetup[k] / ((double)v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0); if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k]) / v->HTotal[k]) <= (isInterlaceTiming ? dml_floor((v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) : @@ -3544,7 +3544,7 @@ static void CalculateVupdateAndDynamicMetadataParameters( TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2 / DPPCLK + 3 / DISPCLK); *VUpdateWidthPix = dml_ceil((14.0 / DCFClkDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime) * PixelClock, 1.0); *VReadyOffsetPix = dml_ceil(dml_max(150.0 / DPPCLK, TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / DPPCLK) * PixelClock, 1.0); - *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1); + *VUpdateOffsetPix = (unsigned int)dml_ceil(HTotal / 4.0, 1); *TSetup = (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock; *Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK; *Tdmec = HTotal / PixelClock; @@ -3829,17 +3829,17 @@ static noinline void CalculatePrefetchSchedulePerPlane( mode_lib, HostVMInefficiencyFactor, &myPipe, - v->DSCDelayPerState[i][k], + (unsigned int)v->DSCDelayPerState[i][k], v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater, v->DPPCLKDelaySCL, v->DPPCLKDelaySCLLBOnly, v->DPPCLKDelayCNVCCursor, v->DISPCLKDelaySubtotal, - v->SwathWidthYThisState[k] / v->HRatio[k], + (unsigned int)(v->SwathWidthYThisState[k] / v->HRatio[k]), v->OutputFormat[k], v->MaxInterDCNTileRepeaters, - dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), - v->MaximumVStartup[i][j][k], + (unsigned int)dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), + (unsigned int)v->MaximumVStartup[i][j][k], v->GPUVMMaxPageTableLevels, v->GPUVMEnable, v->HostVMEnable, @@ -3852,15 +3852,15 @@ static noinline void CalculatePrefetchSchedulePerPlane( v->UrgLatency[i], v->ExtraLatency, v->TimeCalc, - v->PDEAndMetaPTEBytesPerFrame[i][j][k], - v->MetaRowBytes[i][j][k], - v->DPTEBytesPerRow[i][j][k], + (unsigned int)v->PDEAndMetaPTEBytesPerFrame[i][j][k], + (unsigned int)v->MetaRowBytes[i][j][k], + (unsigned int)v->DPTEBytesPerRow[i][j][k], v->PrefetchLinesY[i][j][k], - v->SwathWidthYThisState[k], + (unsigned int)v->SwathWidthYThisState[k], v->PrefillY[k], v->MaxNumSwY[k], v->PrefetchLinesC[i][j][k], - v->SwathWidthCThisState[k], + (unsigned int)v->SwathWidthCThisState[k], v->PrefillC[k], v->MaxNumSwC[k], v->swath_width_luma_ub_this_state[k], @@ -3893,7 +3893,8 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ { struct vba_vars_st *v = &mode_lib->vba; - int i, j; + int j; + unsigned int i; unsigned int k, m; int ReorderingBytes; int MinPrefetchMode = 0, MaxPrefetchMode = 2; @@ -4045,9 +4046,9 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->WritebackHTaps[k], v->WritebackVTaps[k], v->WritebackSourceWidth[k], - v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationWidth[k], v->HTotal[k], - v->WritebackLineBufferSize)); + (unsigned int)v->WritebackLineBufferSize)); } } for (k = 0; k < v->NumberOfActivePlanes; k++) { @@ -4094,17 +4095,17 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ int MaximumSwathWidthSupportChroma; if (v->SurfaceTiling[k] == dm_sw_linear) { - MaximumSwathWidthSupportLuma = 8192.0; + MaximumSwathWidthSupportLuma = (int)8192.0; } else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) { - MaximumSwathWidthSupportLuma = 2880.0; + MaximumSwathWidthSupportLuma = (int)2880.0; } else if (v->SourcePixelFormat[k] == dm_rgbe_alpha) { - MaximumSwathWidthSupportLuma = 3840.0; + MaximumSwathWidthSupportLuma = (int)3840.0; } else { - MaximumSwathWidthSupportLuma = 5760.0; + MaximumSwathWidthSupportLuma = (int)5760.0; } if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) { - MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma / 2.0; + MaximumSwathWidthSupportChroma = (int)(MaximumSwathWidthSupportLuma / 2.0); } else { MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma; } @@ -4332,7 +4333,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->DISPCLK_DPPCLK_Support[i][j] = false; } } - v->TotalNumberOfActiveDPP[i][j] = 0.0; + v->TotalNumberOfActiveDPP[i][j] = 0; for (k = 0; k < v->NumberOfActivePlanes; k++) { v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k]; } @@ -4369,7 +4370,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ for (k = 0; k < v->NumberOfActivePlanes; ++k) { if (v->BlendingAndTiming[k] == k) { if (v->PixelClockBackEnd[k] > 3200) { - v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); + v->NumberOfDSCSlices[k] = (unsigned int)dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); } else if (v->PixelClockBackEnd[k] > 1360) { v->NumberOfDSCSlices[k] = 8; } else if (v->PixelClockBackEnd[k] > 680) { @@ -4431,7 +4432,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->PHYCLKD18PerState[k] >= 10000.0 / 18.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 10000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4450,7 +4451,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->LinkDSCEnable = true; v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 10000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4473,7 +4474,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->PHYCLKD18PerState[k] >= 13500.0 / 18.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 13500, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4492,7 +4493,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->LinkDSCEnable = true; v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 13500, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4515,7 +4516,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->PHYCLKD18PerState[k] >= 20000.0 / 18.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 20000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4534,7 +4535,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->LinkDSCEnable = true; v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 20000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4557,7 +4558,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ if (v->PHYCLKPerState[i] >= 270.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 2700, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4577,7 +4578,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 5400, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4597,7 +4598,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 8100, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4696,7 +4697,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->DSCDelayPerState[i][k] = dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k], v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); @@ -4705,7 +4706,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ * (dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k] / 2, v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); @@ -4714,7 +4715,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ * (dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k] / 4, v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); @@ -4802,14 +4803,14 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->RequiredDPPCLKThisState, v->ReadBandwidthLuma, v->ReadBandwidthChroma, - v->ReturnBusWidth, + (int)v->ReturnBusWidth, &v->ProjectedDCFCLKDeepSleep[i][j]); for (k = 0; k < v->NumberOfActivePlanes; ++k) { v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k]; v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k]; - v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k]; - v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k]; + v->SwathWidthYAllStates[i][j][k] = (unsigned int)v->SwathWidthYThisState[k]; + v->SwathWidthCAllStates[i][j][k] = (unsigned int)v->SwathWidthCThisState[k]; v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k]; v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k]; v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k]; @@ -4834,8 +4835,8 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k]; v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k]; v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k]; - v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k]; - v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k]; + v->DETBufferSizeYThisState[k] = (unsigned int)v->DETBufferSizeYAllStates[i][j][k]; + v->DETBufferSizeCThisState[k] = (unsigned int)v->DETBufferSizeCAllStates[i][j][k]; } v->TotalNumberOfDCCActiveDPP[i][j] = 0; @@ -4868,16 +4869,16 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->SurfaceTiling[k], v->BytePerPixelC[k], v->SourceScan[k], - v->SwathWidthCThisState[k], + (unsigned int)v->SwathWidthCThisState[k], v->ViewportHeightChroma[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForChroma, v->PitchC[k], - 0.0, + 0, &v->MacroTileWidthC[k], &v->MetaRowBytesC, &v->DPTEBytesPerRowC, @@ -4910,8 +4911,8 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma; v->PTEBufferSizeInRequestsForChroma = 0; v->PDEAndMetaPTEBytesPerFrameC = 0.0; - v->MetaRowBytesC = 0.0; - v->DPTEBytesPerRowC = 0.0; + v->MetaRowBytesC = 0; + v->DPTEBytesPerRowC = 0; v->PrefetchLinesC[i][j][k] = 0.0; v->PTEBufferSizeNotExceededC[i][j][k] = true; } @@ -4924,13 +4925,13 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->SurfaceTiling[k], v->BytePerPixelY[k], v->SourceScan[k], - v->SwathWidthYThisState[k], + (unsigned int)v->SwathWidthYThisState[k], v->ViewportHeight[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForLuma, v->PitchY[k], v->DCCMetaPitchY[k], @@ -5066,9 +5067,9 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->WritebackHRatio[k], v->WritebackVRatio[k], v->WritebackVTaps[k], - v->WritebackDestinationWidth[k], - v->WritebackDestinationHeight[k], - v->WritebackSourceHeight[k], + (int)v->WritebackDestinationWidth[k], + (int)v->WritebackDestinationHeight[k], + (int)v->WritebackSourceHeight[k], v->HTotal[k]) / v->RequiredDISPCLK[i][j]; } else { v->WritebackDelayTime[k] = 0.0; @@ -5083,9 +5084,9 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->WritebackHRatio[m], v->WritebackVRatio[m], v->WritebackVTaps[m], - v->WritebackDestinationWidth[m], - v->WritebackDestinationHeight[m], - v->WritebackSourceHeight[m], + (int)v->WritebackDestinationWidth[m], + (int)v->WritebackDestinationHeight[m], + (int)v->WritebackSourceHeight[m], v->HTotal[m]) / v->RequiredDISPCLK[i][j]); } } @@ -5116,11 +5117,11 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ } } - ReorderingBytes = v->NumberOfChannels + ReorderingBytes = (int)(v->NumberOfChannels * dml_max3( v->UrgentOutOfOrderReturnPerChannelPixelDataOnly, v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - v->UrgentOutOfOrderReturnPerChannelVMDataOnly); + v->UrgentOutOfOrderReturnPerChannelVMDataOnly)); for (i = 0; i < v->soc.num_states; ++i) { for (j = 0; j <= 1; ++j) { @@ -5223,8 +5224,8 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k]; v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k]; v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k]; - v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k]; - v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k]; + v->DETBufferSizeYThisState[k] = (unsigned int)v->DETBufferSizeYAllStates[i][j][k]; + v->DETBufferSizeCThisState[k] = (unsigned int)v->DETBufferSizeCAllStates[i][j][k]; } VMDataOnlyReturnBWPerState = dml_min( @@ -5238,7 +5239,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ HostVMInefficiencyFactor = v->ReturnBWPerState[i][j] / VMDataOnlyReturnBWPerState; v->ExtraLatency = CalculateExtraLatency( - v->RoundTripPingLatencyCycles, + (int)v->RoundTripPingLatencyCycles, ReorderingBytes, v->DCFCLKState[i][j], v->TotalNumberOfActiveDPP[i][j], @@ -5371,11 +5372,11 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ * v->UrgentBurstFactorChromaPre[k]) + v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]); } - v->TotImmediateFlipBytes = 0.0; + v->TotImmediateFlipBytes = 0; for (k = 0; k < v->NumberOfActivePlanes; k++) { - v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + v->TotImmediateFlipBytes = (unsigned int)(v->TotImmediateFlipBytes + v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] + v->MetaRowBytes[i][j][k] - + v->DPTEBytesPerRow[i][j][k]); + + v->DPTEBytesPerRow[i][j][k])); } for (k = 0; k < v->NumberOfActivePlanes; k++) { @@ -5537,30 +5538,37 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ } /*Mode Support, Voltage State and SOC Configuration*/ - for (i = v->soc.num_states - 1; i >= 0; i--) { + for (int idx = (int)v->soc.num_states - 1; idx >= 0; idx--) { for (j = 0; j < 2; j++) { - if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true && v->ViewportSizeSupport[i][j] == true - && v->LinkCapacitySupport[i] == true && !P2IWith420 && !DSCOnlyIfNecessaryWithBPP - && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false - && v->DTBCLKRequiredMoreThanSupported[i] == false - && v->ROBSupport[i][j] == true && v->DISPCLK_DPPCLK_Support[i][j] == true - && v->TotalAvailablePipesSupport[i][j] == true && EnoughWritebackUnits == true + if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true + && v->ViewportSizeSupport[idx][j] == true + && v->LinkCapacitySupport[idx] == true && !P2IWith420 + && !DSCOnlyIfNecessaryWithBPP + && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[idx] == true + && v->NotEnoughDSCUnits[idx] == false + && v->DTBCLKRequiredMoreThanSupported[idx] == false + && v->ROBSupport[idx][j] == true && v->DISPCLK_DPPCLK_Support[idx][j] == true + && v->TotalAvailablePipesSupport[idx][j] == true && EnoughWritebackUnits == true && v->WritebackLatencySupport == true && v->WritebackScaleRatioAndTapsSupport == true - && v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false - && v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true - && v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true - && v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false + && v->CursorSupport == true && v->PitchSupport == true + && ViewportExceedsSurface == false + && v->PrefetchSupported[idx][j] == true + && v->DynamicMetadataSupported[idx][j] == true + && v->TotalVerticalActiveBandwidthSupport[idx][j] == true + && v->VRatioInPrefetchSupported[idx][j] == true + && v->PTEBufferSizeNotExceeded[idx][j] == true + && v->NonsupportedDSCInputBPC == false && ((v->HostVMEnable == false && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required) - || v->ImmediateFlipSupportedForState[i][j] == true) + || v->ImmediateFlipSupportedForState[idx][j] == true) && FMTBufferExceeded == false) { - v->ModeSupport[i][j] = true; + v->ModeSupport[idx][j] = true; } else { - v->ModeSupport[i][j] = false; + v->ModeSupport[idx][j] = false; } } } - for (i = v->soc.num_states; i >= 0; i--) { + for (int idx = (int)v->soc.num_states; idx >= 0; idx--) { for (j = 0; j < 2; j++) { enum dm_validation_status status = DML_VALIDATION_OK; @@ -5568,7 +5576,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ status = DML_FAIL_SCALE_RATIO_TAP; } else if (!v->SourceFormatPixelAndScanSupport) { status = DML_FAIL_SOURCE_PIXEL_FORMAT; - } else if (!v->ViewportSizeSupport[i][j]) { + } else if (!v->ViewportSizeSupport[idx][j]) { status = DML_FAIL_VIEWPORT_SIZE; } else if (P2IWith420) { status = DML_FAIL_P2I_WITH_420; @@ -5576,15 +5584,15 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ status = DML_FAIL_DSC_ONLY_IF_NECESSARY_WITH_BPP; } else if (DSC422NativeNotSupported) { status = DML_FAIL_NOT_DSC422_NATIVE; - } else if (!v->ODMCombine4To1SupportCheckOK[i]) { + } else if (!v->ODMCombine4To1SupportCheckOK[idx]) { status = DML_FAIL_ODM_COMBINE4TO1; - } else if (v->NotEnoughDSCUnits[i]) { + } else if (v->NotEnoughDSCUnits[idx]) { status = DML_FAIL_NOT_ENOUGH_DSC; - } else if (!v->ROBSupport[i][j]) { + } else if (!v->ROBSupport[idx][j]) { status = DML_FAIL_REORDERING_BUFFER; - } else if (!v->DISPCLK_DPPCLK_Support[i][j]) { + } else if (!v->DISPCLK_DPPCLK_Support[idx][j]) { status = DML_FAIL_DISPCLK_DPPCLK; - } else if (!v->TotalAvailablePipesSupport[i][j]) { + } else if (!v->TotalAvailablePipesSupport[idx][j]) { status = DML_FAIL_TOTAL_AVAILABLE_PIPES; } else if (!EnoughWritebackUnits) { status = DML_FAIL_ENOUGH_WRITEBACK_UNITS; @@ -5598,36 +5606,36 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ status = DML_FAIL_PITCH_SUPPORT; } else if (ViewportExceedsSurface) { status = DML_FAIL_VIEWPORT_EXCEEDS_SURFACE; - } else if (!v->PrefetchSupported[i][j]) { + } else if (!v->PrefetchSupported[idx][j]) { status = DML_FAIL_PREFETCH_SUPPORT; - } else if (!v->DynamicMetadataSupported[i][j]) { + } else if (!v->DynamicMetadataSupported[idx][j]) { status = DML_FAIL_DYNAMIC_METADATA; - } else if (!v->TotalVerticalActiveBandwidthSupport[i][j]) { + } else if (!v->TotalVerticalActiveBandwidthSupport[idx][j]) { status = DML_FAIL_TOTAL_V_ACTIVE_BW; - } else if (!v->VRatioInPrefetchSupported[i][j]) { + } else if (!v->VRatioInPrefetchSupported[idx][j]) { status = DML_FAIL_V_RATIO_PREFETCH; - } else if (!v->PTEBufferSizeNotExceeded[i][j]) { + } else if (!v->PTEBufferSizeNotExceeded[idx][j]) { status = DML_FAIL_PTE_BUFFER_SIZE; } else if (v->NonsupportedDSCInputBPC) { status = DML_FAIL_DSC_INPUT_BPC; } else if ((v->HostVMEnable - && !v->ImmediateFlipSupportedForState[i][j])) { + && !v->ImmediateFlipSupportedForState[idx][j])) { status = DML_FAIL_HOST_VM_IMMEDIATE_FLIP; } else if (FMTBufferExceeded) { status = DML_FAIL_FMT_BUFFER_EXCEEDED; } - mode_lib->vba.ValidationStatus[i] = status; + mode_lib->vba.ValidationStatus[idx] = status; } } { unsigned int MaximumMPCCombine = 0; - - for (i = v->soc.num_states; i >= 0; i--) { - if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) { - v->VoltageLevel = i; - v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true; - if (v->ModeSupport[i][0] == true) { + for (int idx = (int)v->soc.num_states; idx >= 0; idx--) { + if (idx == (int)v->soc.num_states || v->ModeSupport[idx][0] == true + || v->ModeSupport[idx][1] == true) { + v->VoltageLevel = idx; + v->ModeIsSupported = v->ModeSupport[idx][0] == true || v->ModeSupport[idx][1] == true; + if (v->ModeSupport[idx][0] == true) { MaximumMPCCombine = 0; } else { MaximumMPCCombine = 1; @@ -5635,7 +5643,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ } } v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine]; - for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { + for (k = 0; k < v->NumberOfActivePlanes; k++) { v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k]; v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k]; } @@ -5693,7 +5701,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank; double WritebackDRAMClockChangeLatencyHiding; double TotalPixelBW = 0.0; - int k, j; + unsigned int k, j; v->UrgentWatermark = UrgentLatency + ExtraLatency; @@ -5738,13 +5746,13 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( for (k = 0; k < v->NumberOfActivePlanes; ++k) { double EffectiveDETBufferSizeY = DETBufferSizeY[k]; - v->LBLatencyHidingSourceLinesY = dml_min( + v->LBLatencyHidingSourceLinesY = (unsigned int)(dml_min( (double) v->MaxLineBufferLines, - dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1); + dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1)); - v->LBLatencyHidingSourceLinesC = dml_min( + v->LBLatencyHidingSourceLinesC = (unsigned int)(dml_min( (double) v->MaxLineBufferLines, - dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1); + dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1)); EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]); @@ -5756,11 +5764,11 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( } LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; - LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); + LinesInDETYRoundedDownToSwath[k] = (unsigned int)dml_floor(LinesInDETY[k], SwathHeightY[k]); FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k]; if (BytePerPixelDETC[k] > 0) { LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k]; - LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]); + LinesInDETCRoundedDownToSwath = (unsigned int)dml_floor(LinesInDETC, SwathHeightC[k]); FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k]; } else { LinesInDETC = 0; @@ -5881,7 +5889,7 @@ static void CalculateDCFCLKDeepSleep( double DisplayPipeLineDeliveryTimeLuma; double DisplayPipeLineDeliveryTimeChroma; double ReadBandwidth = 0.0; - int k; + unsigned int k; for (k = 0; k < NumberOfActivePlanes; ++k) { @@ -6032,7 +6040,7 @@ static void CalculatePixelDeliveryTimes( double CursorRequestDeliveryTimePrefetch[]) { double req_per_swath_ub; - int k; + unsigned int k; for (k = 0; k < NumberOfActivePlanes; ++k) { if (VRatio[k] <= 1) { @@ -6107,7 +6115,7 @@ static void CalculatePixelDeliveryTimes( for (k = 0; k < NumberOfActivePlanes; ++k) { int cursor_req_per_width; - cursor_req_per_width = dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1); + cursor_req_per_width = (int)dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1); if (NumberOfCursors[k] > 0) { if (VRatio[k] <= 1) { CursorRequestDeliveryTime[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width; @@ -6132,7 +6140,7 @@ static void CalculatePixelDeliveryTimes( } static void CalculateMetaAndPTETimes( - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, @@ -6198,7 +6206,7 @@ static void CalculateMetaAndPTETimes( unsigned int dpte_groups_per_row_luma_ub; unsigned int dpte_group_width_chroma; unsigned int dpte_groups_per_row_chroma_ub; - int k; + unsigned int k; for (k = 0; k < NumberOfActivePlanes; ++k) { DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k]; @@ -6241,7 +6249,7 @@ static void CalculateMetaAndPTETimes( } else { meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; - meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / meta_chunk_width_chroma; + meta_chunk_per_row_int_chroma = (unsigned int)((double) meta_row_width_chroma[k] / meta_chunk_width_chroma); meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma; if (SourceScan[k] != dm_vert) { meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k]; @@ -6274,7 +6282,7 @@ static void CalculateMetaAndPTETimes( } else { dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k]; } - dpte_groups_per_row_luma_ub = dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1); + dpte_groups_per_row_luma_ub = (unsigned int)dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1); time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; @@ -6288,7 +6296,7 @@ static void CalculateMetaAndPTETimes( } else { dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqHeightC[k]; } - dpte_groups_per_row_chroma_ub = dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1); + dpte_groups_per_row_chroma_ub = (unsigned int)dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1); time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; @@ -6330,34 +6338,34 @@ static void CalculateVMGroupAndRequestTimes( (void)dpte_row_width_chroma_ub; int num_group_per_lower_vm_stage; int num_req_per_lower_vm_stage; - int k; + unsigned int k; for (k = 0; k < NumberOfActivePlanes; ++k) { if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) { if (DCCEnable[k] == false) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)(dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (GPUVMMaxPageTableLevels == 1) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)(dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = 2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + num_group_per_lower_vm_stage = (int)(2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = 1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)(1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)); } } } @@ -6668,8 +6676,8 @@ static void CalculateStutterEfficiency( #endif *StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitTime + StutterBurstTime) / *StutterPeriod) * 100; *Z8StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitZ8Time + StutterBurstTime) / *StutterPeriod) * 100; - *NumberOfStutterBurstsPerFrame = (*StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); - *Z8NumberOfStutterBurstsPerFrame = (*Z8StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); + *NumberOfStutterBurstsPerFrame = (int)(*StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); + *Z8NumberOfStutterBurstsPerFrame = (int)(*Z8StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); } else { *StutterEfficiencyNotIncludingVBlank = 0.; *Z8StutterEfficiencyNotIncludingVBlank = 0.; @@ -6770,12 +6778,12 @@ static void CalculateSwathAndDETConfiguration( int MaximumSwathHeightC[DC__NUM_DPP__MAX]; int MinimumSwathHeightY; int MinimumSwathHeightC; - int RoundedUpMaxSwathSizeBytesY; - int RoundedUpMaxSwathSizeBytesC; - int RoundedUpMinSwathSizeBytesY; - int RoundedUpMinSwathSizeBytesC; - int RoundedUpSwathSizeBytesY; - int RoundedUpSwathSizeBytesC; + unsigned int RoundedUpMaxSwathSizeBytesY; + unsigned int RoundedUpMaxSwathSizeBytesC; + unsigned int RoundedUpMinSwathSizeBytesY; + unsigned int RoundedUpMinSwathSizeBytesC; + unsigned int RoundedUpSwathSizeBytesY; + unsigned int RoundedUpSwathSizeBytesC; double SwathWidthSingleDPP[DC__NUM_DPP__MAX]; double SwathWidthSingleDPPChroma[DC__NUM_DPP__MAX]; int k; @@ -6845,17 +6853,17 @@ static void CalculateSwathAndDETConfiguration( } } - RoundedUpMaxSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k]; - RoundedUpMinSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MinimumSwathHeightY; + RoundedUpMaxSwathSizeBytesY = (int)(swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k]); + RoundedUpMinSwathSizeBytesY = (int)(swath_width_luma_ub[k] * BytePerPixDETY[k] * MinimumSwathHeightY); if (SourcePixelFormat[k] == dm_420_10) { - RoundedUpMaxSwathSizeBytesY = dml_ceil((double) RoundedUpMaxSwathSizeBytesY, 256); - RoundedUpMinSwathSizeBytesY = dml_ceil((double) RoundedUpMinSwathSizeBytesY, 256); + RoundedUpMaxSwathSizeBytesY = (int)dml_ceil((double) RoundedUpMaxSwathSizeBytesY, 256); + RoundedUpMinSwathSizeBytesY = (int)dml_ceil((double) RoundedUpMinSwathSizeBytesY, 256); } - RoundedUpMaxSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k]; - RoundedUpMinSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MinimumSwathHeightC; + RoundedUpMaxSwathSizeBytesC = (int)(swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k]); + RoundedUpMinSwathSizeBytesC = (int)(swath_width_chroma_ub[k] * BytePerPixDETC[k] * MinimumSwathHeightC); if (SourcePixelFormat[k] == dm_420_10) { - RoundedUpMaxSwathSizeBytesC = dml_ceil(RoundedUpMaxSwathSizeBytesC, 256); - RoundedUpMinSwathSizeBytesC = dml_ceil(RoundedUpMinSwathSizeBytesC, 256); + RoundedUpMaxSwathSizeBytesC = (int)dml_ceil(RoundedUpMaxSwathSizeBytesC, 256); + RoundedUpMinSwathSizeBytesC = (int)dml_ceil(RoundedUpMinSwathSizeBytesC, 256); } if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= DETBufferSizeInKByte * 1024 / 2) { @@ -6885,14 +6893,14 @@ static void CalculateSwathAndDETConfiguration( double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64); if (SwathHeightC[k] == 0) { - DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024; + DETBufferSizeY[k] = (unsigned int)(actDETBufferSizeInKByte * 1024); DETBufferSizeC[k] = 0; } else if (RoundedUpSwathSizeBytesY <= 1.5 * RoundedUpSwathSizeBytesC) { - DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024 / 2; - DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 2; + DETBufferSizeY[k] = (unsigned int)(actDETBufferSizeInKByte * 1024 / 2); + DETBufferSizeC[k] = (unsigned int)(actDETBufferSizeInKByte * 1024 / 2); } else { - DETBufferSizeY[k] = dml_floor(actDETBufferSizeInKByte * 1024 * 2 / 3, 1024); - DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 3; + DETBufferSizeY[k] = (unsigned int)dml_floor(actDETBufferSizeInKByte * 1024 * 2 / 3, 1024); + DETBufferSizeC[k] = (unsigned int)(actDETBufferSizeInKByte * 1024 / 3); } if (RoundedUpMinSwathSizeBytesY + RoundedUpMinSwathSizeBytesC > actDETBufferSizeInKByte * 1024 / 2 || SwathWidth[k] > MaximumSwathWidthLuma[k] @@ -6991,8 +6999,8 @@ static void CalculateSwathWidth( SwathWidthC[k] = SwathWidthSingleDPPC[k]; } { - int surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); - int surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); + int surface_width_ub_l = (int)dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); + int surface_height_ub_l = (int)dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l); @@ -7001,11 +7009,11 @@ static void CalculateSwathWidth( if (SourceScan[k] != dm_vert) { MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k]; MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k]; - swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]); + swath_width_luma_ub[k] = (int)dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]); if (BytePerPixC[k] > 0) { - int surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); + int surface_width_ub_c = (int)dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); - swath_width_chroma_ub[k] = dml_min( + swath_width_chroma_ub[k] = (int)dml_min( surface_width_ub_c, (int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]); } else { @@ -7014,11 +7022,11 @@ static void CalculateSwathWidth( } else { MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k]; MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k]; - swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]); + swath_width_luma_ub[k] = (int)dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]); if (BytePerPixC[k] > 0) { - int surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); + int surface_height_ub_c = (int)dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); - swath_width_chroma_ub[k] = dml_min( + swath_width_chroma_ub[k] = (int)dml_min( surface_height_ub_c, (int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]); } else { @@ -7100,9 +7108,9 @@ static double CalculateExtraLatencyBytes( if (HostVMMinPageSize < 2048) HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); else - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } else { HostVMDynamicLevels = 0; } @@ -7139,7 +7147,8 @@ static noinline_for_stack void UseMinimumDCFCLK( int ReorderingBytes) { struct vba_vars_st *v = &mode_lib->vba; - int dummy1, i, j, k; + int dummy1, j; + unsigned int i, k; double NormalEfficiency, dummy2, dummy3; double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2]; @@ -7166,7 +7175,7 @@ static noinline_for_stack void UseMinimumDCFCLK( + v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]); } - for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) + for (k = 0; k < v->NumberOfActivePlanes; ++k) NoOfDPPState[k] = v->NoOfDPP[i][j][k]; MinimumTWait = CalculateTWait(MaxPrefetchMode, v->FinalDRAMClockChangeLatency, v->UrgLatency[i], v->SREnterPlusExitTime); @@ -7269,7 +7278,7 @@ static noinline_for_stack void UseMinimumDCFCLK( } } DCFCLKRequiredForPeakBandwidth = 0; - for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) + for (k = 0; k < v->NumberOfActivePlanes; ++k) DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k]; MinimumTvmPlus2Tr0 = v->UrgLatency[i] @@ -7310,7 +7319,7 @@ static void CalculateUnboundedRequestAndCompressedBufferSize( double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64); *UnboundedRequestEnabled = UnboundedRequest(UseUnboundedRequestingFinal, TotalActiveDPP, NoChromaPlanes, Output[0]); - *CompressedBufferSizeInkByte = ( + *CompressedBufferSizeInkByte = (int)( *UnboundedRequestEnabled == true ? ConfigReturnBufferSizeInKByte - TotalActiveDPP * actDETBufferSizeInKByte : ConfigReturnBufferSizeInKByte - MaxNumDPP * actDETBufferSizeInKByte); @@ -7352,15 +7361,15 @@ static unsigned int CalculateMaxVStartup( unsigned int vblank_size = 0; double line_time_us = HTotal / PixelClock; unsigned int vblank_actual = VTotal - VActive; - unsigned int vblank_nom_default_in_line = dml_floor(VBlankNomDefaultUS / line_time_us, 1.0); + unsigned int vblank_nom_default_in_line = (unsigned int)dml_floor(VBlankNomDefaultUS / line_time_us, 1.0); unsigned int vblank_nom_input = VBlankNom; //dml_min(VBlankNom, vblank_nom_default_in_line); unsigned int vblank_avail = vblank_nom_input == 0 ? vblank_nom_default_in_line : vblank_nom_input; vblank_size = (unsigned int) dml_min(vblank_actual, vblank_avail); if (Interlace && !ProgressiveTointerlaceUnitinOPP) - MaxVStartup = dml_floor(vblank_size / 2.0, 1.0); + MaxVStartup = (unsigned int)dml_floor(vblank_size / 2.0, 1.0); else - MaxVStartup = vblank_size - dml_max(1.0, dml_ceil(WritebackDelayTime / line_time_us, 1.0)); + MaxVStartup = (unsigned int)(vblank_size - dml_max(1.0, dml_ceil(WritebackDelayTime / line_time_us, 1.0))); if (MaxVStartup > 1023) MaxVStartup = 1023; return MaxVStartup; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c index 40a916c2a9c6..ec745c2d6c81 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c @@ -205,11 +205,11 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_s extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 1) - 3; + rq_regs->rq_regs_l.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 1) - 3); if (rq_param->yuv420) { extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 1) - 3; + rq_regs->rq_regs_c.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 1) - 3); } rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); @@ -229,12 +229,12 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_s // Note: detile_buf_plane1_addr is in unit of 1KB if (rq_param->yuv420) { if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/2 to chroma)\n", __func__, detile_buf_plane1_addr); #endif } else { - detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0; // 2/3 to luma + detile_buf_plane1_addr = (unsigned int)(dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0); // 2/3 to luma #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/3 chroma)\n", __func__, detile_buf_plane1_addr); #endif @@ -277,8 +277,8 @@ static void handle_det_buf_split(struct display_mode_lib *mode_lib, display_rq_p #endif if (rq_param->yuv420_10bpc) { - full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256; - full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256; + full_swath_bytes_packed_l = (unsigned int)(dml_round_to_multiple((unsigned int)(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0), 256, 1) + 256); + full_swath_bytes_packed_c = (unsigned int)(dml_round_to_multiple((unsigned int)(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0), 256, 1) + 256); #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_l); dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_c); @@ -509,7 +509,7 @@ static void get_meta_and_pte_attr( // "/2" is like square root // blk is vertical biased if (tiling != dm_sw_linear) - log2_blk_height = log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); + log2_blk_height = (unsigned int)(log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1)); else log2_blk_height = 0; // blk height of 1 @@ -662,7 +662,7 @@ static void get_meta_and_pte_attr( if (surf_linear) { unsigned int dpte_row_height; - log2_dpte_row_height_linear = dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); + log2_dpte_row_height_linear = (unsigned int)dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); dml_print("DML_DLG: %s: is_chroma = %d\n", __func__, is_chroma); dml_print("DML_DLG: %s: dpte_buf_in_pte_reqs = %d\n", __func__, dpte_buf_in_pte_reqs); @@ -728,7 +728,7 @@ static void get_meta_and_pte_attr( // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, // the upper bound for the dpte groups per row is as follows. - rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); + rq_dlg_param->dpte_groups_per_row_ub = (unsigned int)dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); } static void get_surf_rq_param( @@ -753,7 +753,7 @@ static void get_surf_rq_param( vp_height = pipe_param->src.viewport_height_c; data_pitch = pipe_param->src.data_pitch_c; meta_pitch = pipe_param->src.meta_pitch_c; - surface_height = pipe_param->src.surface_height_y / 2.0; + surface_height = (unsigned int)(pipe_param->src.surface_height_y / 2.0); } else { vp_width = pipe_param->src.viewport_width / ppe; vp_height = pipe_param->src.viewport_height; @@ -771,18 +771,18 @@ static void get_surf_rq_param( access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed hactive_odm = pipe_param->dest.hactive / ((unsigned int) pipe_param->dest.odm_combine * 2); if (is_chroma) { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width; - src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width); + src_hactive_odm = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm); } else { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width; - src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width); + src_hactive_odm = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm); } if (access_dir == 0) { - vp_width = dml_min(full_src_vp_width, src_hactive_odm); + vp_width = (unsigned int)dml_min(full_src_vp_width, src_hactive_odm); dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width); } else { - vp_height = dml_min(full_src_vp_width, src_hactive_odm); + vp_height = (unsigned int)dml_min(full_src_vp_width, src_hactive_odm); dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height); } @@ -901,7 +901,7 @@ static void calculate_ttu_cursor( cur_req_size = 256; } - cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); + cur_req_width = (unsigned int)((double) cur_req_size / ((double) cur_bit_per_pixel / 8.0)); cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width; cur_req_per_width = cur_width_ub / (double) cur_req_width; hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor @@ -1042,7 +1042,7 @@ static void dml_rq_dlg_get_dlg_params( double refcyc_per_req_delivery_cur0; double refcyc_per_req_delivery_pre_cur1; double refcyc_per_req_delivery_cur1; - unsigned int vba__min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA + unsigned int vba__min_dst_y_next_start = (unsigned int)get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA unsigned int vba__vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA float vba__refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA @@ -1075,7 +1075,7 @@ static void dml_rq_dlg_get_dlg_params( dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; disp_dlg_regs->min_dst_y_next_start_us = (vba__min_dst_y_next_start * dst->hactive) / (unsigned int) dst->pixel_rate_mhz; - disp_dlg_regs->min_dst_y_next_start = vba__min_dst_y_next_start * dml_pow(2, 2); + disp_dlg_regs->min_dst_y_next_start = (unsigned int)(vba__min_dst_y_next_start * dml_pow(2, 2)); ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); @@ -1138,8 +1138,8 @@ static void dml_rq_dlg_get_dlg_params( if (interlaced) vstartup_start = vstartup_start / 2; - dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA - dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dst_x_after_scaler = (unsigned int)get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dst_y_after_scaler = (unsigned int)get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA // do some adjustment on the dst_after scaler to account for odm combine mode dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n", __func__, dst_x_after_scaler); @@ -1366,9 +1366,9 @@ static void dml_rq_dlg_get_dlg_params( } if (src->dynamic_metadata_enable && src->gpuvm) - disp_dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + disp_dlg_regs->refcyc_per_vm_dmdata = (unsigned int)(get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA - disp_dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + disp_dlg_regs->dmdata_dl_delta = (unsigned int)(get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA // TTU - Luma / Chroma if (access_dir) { // vertical access @@ -1474,8 +1474,8 @@ static void dml_rq_dlg_get_dlg_params( src->cur0_src_width, (enum cursor_bpp) (src->cur0_bpp)); - vba__refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - vba__refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + vba__refcyc_per_req_delivery_pre_cur0 = (float)(get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + vba__refcyc_per_req_delivery_cur0 = (float)(get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_pre_cur0); dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_cur0); @@ -1495,7 +1495,7 @@ static void dml_rq_dlg_get_dlg_params( // Assignment to register structures disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line ASSERT(disp_dlg_regs->dst_y_after_scaler < 8); - disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + disp_dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); // in terms of refclk ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); @@ -1532,23 +1532,23 @@ static void dml_rq_dlg_get_dlg_params( disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; } - disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA - disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA // Clamp to max for now if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2)); ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); @@ -1572,23 +1572,23 @@ static void dml_rq_dlg_get_dlg_params( disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (dual_plane) { disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c); if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1); // TODO: Is this the right calculation? Does htotal need to be halved? disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_c); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1); } disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1); @@ -1629,7 +1629,7 @@ static void dml_rq_dlg_get_dlg_params( disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs->qos_ramp_disable_cur0 = 0; - disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + disp_ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); print__ttu_regs_st(mode_lib, disp_ttu_regs); @@ -1660,7 +1660,7 @@ void dml314_rq_dlg_get_dlg_reg( dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes); - dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); + dlg_sys_param.total_flip_bytes = (unsigned int)get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); print__dlg_sys_params_st(mode_lib, &dlg_sys_param); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index eb199215d298..a97e38aa7fed 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -191,21 +191,24 @@ void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr) double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; /* For min clocks use as reported by PM FW and report those as min */ - uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; - uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; + uint16_t min_uclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; + uint16_t min_dcfclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; uint16_t setb_min_uclk_mhz = min_uclk_mhz; - uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; + uint16_t dcfclk_mhz_for_the_second_state = + (uint16_t)clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; dc_assert_fp_enabled(); /* For Set B ranges use min clocks state 2 when available, and report those to PM FW */ - if (dcfclk_mhz_for_the_second_state) - clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state; - else - clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; + if (dcfclk_mhz_for_the_second_state) { + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = + (uint16_t)dcfclk_mhz_for_the_second_state; + } else + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = + (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) - setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; + setb_min_uclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; /* Set A - Normal - default values */ clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; @@ -297,7 +300,7 @@ int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, dcn32_subvp_in_use(dc, context)) vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support; - if (vlevel < context->bw_ctx.dml.vba.soc.num_states && + if (vlevel < (int)context->bw_ctx.dml.vba.soc.num_states && vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) break; @@ -347,13 +350,13 @@ void dcn32_helper_populate_phantom_dlg_params(struct dc *dc, if (pipe->plane_state && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) { pipes[pipe_idx].pipe.dest.vstartup_start = - get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + (unsigned int)get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); pipes[pipe_idx].pipe.dest.vupdate_offset = - get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + (unsigned int)get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); pipes[pipe_idx].pipe.dest.vupdate_width = - get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + (unsigned int)get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); pipes[pipe_idx].pipe.dest.vready_offset = - get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + (unsigned int)get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest; } pipe_idx++; @@ -367,18 +370,18 @@ static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st * float sdp_bw_kbytes_sec; float limiting_bw_kbytes_sec; - memory_bw_kbytes_sec = entry->dram_speed_mts * + memory_bw_kbytes_sec = (float)(entry->dram_speed_mts * dcn3_2_soc.num_chans * dcn3_2_soc.dram_channel_width_bytes * - ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); + ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); - fabric_bw_kbytes_sec = entry->fabricclk_mhz * + fabric_bw_kbytes_sec = (float)(entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * - ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100); + ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); - sdp_bw_kbytes_sec = entry->dcfclk_mhz * + sdp_bw_kbytes_sec = (float)(entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * - ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100); + ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); limiting_bw_kbytes_sec = memory_bw_kbytes_sec; @@ -394,23 +397,23 @@ static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st * static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry) { if (entry->dcfclk_mhz > 0) { - float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100); + float bw_on_sdp = (float)(entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); - entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); - entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans * - dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); + entry->fabricclk_mhz = (float)(bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100))); + entry->dram_speed_mts = (float)(bw_on_sdp / (dcn3_2_soc.num_chans * + dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100))); } else if (entry->fabricclk_mhz > 0) { - float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100); + float bw_on_fabric = (float)(entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); - entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); - entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans * - dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); + entry->dcfclk_mhz = (float)(bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100))); + entry->dram_speed_mts = (float)(bw_on_fabric / (dcn3_2_soc.num_chans * + dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100))); } else if (entry->dram_speed_mts > 0) { - float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans * - dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); + float bw_on_dram = (float)(entry->dram_speed_mts * dcn3_2_soc.num_chans * + dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); - entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); - entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); + entry->fabricclk_mhz = (float)(bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100))); + entry->dcfclk_mhz = (float)(bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100))); } } @@ -418,8 +421,8 @@ static void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *t unsigned int *num_entries, struct _vcs_dpi_voltage_scaling_st *entry) { - int i = 0; - int index = 0; + unsigned int i = 0; + unsigned int index = 0; dc_assert_fp_enabled(); @@ -476,8 +479,8 @@ void dcn32_set_phantom_stream_timing(struct dc *dc, uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines; unsigned int num_dpp; unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; - unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; - unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; + unsigned int dcfclk = (unsigned int)context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; + unsigned int socclk = (unsigned int)context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; struct vba_vars_st *vba = &context->bw_ctx.dml.vba; struct dc_stream_state *main_stream = ref_pipe->stream; @@ -497,10 +500,10 @@ void dcn32_set_phantom_stream_timing(struct dc *dc, } // Calculate lines required for pstate allow width and FW processing delays - pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us + + pstate_width_fw_delay_lines = (uint32_t)(((double)(dc->caps.subvp_fw_processing_delay_us + dc->caps.subvp_pstate_allow_width_us) / 1000000) * (ref_pipe->stream->timing.pix_clk_100hz * 100) / - (double)ref_pipe->stream->timing.h_total; + (double)ref_pipe->stream->timing.h_total); // Update clks_cfg for calling into recalculate pipes[0].clks_cfg.voltage = vlevel; @@ -512,8 +515,8 @@ void dcn32_set_phantom_stream_timing(struct dc *dc, /* Add 16 lines margin to the MALL REGION because SUB_VP_START_LINE must be aligned * to 2 swaths (i.e. 16 lines) */ - phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) + - pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines; + phantom_vactive = (uint32_t)(get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) + + pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines); // W/A for DCC corruption with certain high resolution timings. // Determing if pipesplit is used. If so, add meta_row_height to the phantom vactive. @@ -524,7 +527,7 @@ void dcn32_set_phantom_stream_timing(struct dc *dc, phantom_vactive += dc->debug.subvp_extra_lines; // For backporch of phantom pipe, use vstartup of the main pipe - phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + phantom_bp = (uint32_t)get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); phantom_stream->dst.y = 0; phantom_stream->dst.height = phantom_vactive; @@ -534,7 +537,7 @@ void dcn32_set_phantom_stream_timing(struct dc *dc, * phantom for this case. */ phantom_stream->src.y = 0; - phantom_stream->src.height = (double)phantom_vactive * (double)main_stream->src.height / (double)main_stream->dst.height; + phantom_stream->src.height = (int)((double)phantom_vactive * (double)main_stream->src.height / (double)main_stream->dst.height); phantom_stream->timing.v_addressable = phantom_vactive; phantom_stream->timing.v_front_porch = 1; @@ -615,9 +618,9 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc, continue; // Round up - refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + + refresh_rate = (unsigned int)((pipe->stream->timing.pix_clk_100hz * 100 + pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) - / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); + / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total)); /* SubVP pipe candidate requirements: * - Refresh rate < 120hz * - Not able to switch in vactive naturally (switching in active means the @@ -644,8 +647,8 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc, pipe = &context->res_ctx.pipe_ctx[i]; if (num_pipes <= free_pipes) { struct dc_stream_state *stream = pipe->stream; - unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total / - (double)(stream->timing.pix_clk_100hz * 100)) * 1000000; + unsigned int frame_us = (unsigned int)((stream->timing.v_total * stream->timing.h_total / + (double)(stream->timing.pix_clk_100hz * 100)) * 1000000); if (frame_us > max_frame_time) { *index = i; max_frame_time = frame_us; @@ -747,10 +750,10 @@ static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context) phantom->timing.v_addressable; // Round up when calculating microschedule time (+ 1 at the end) - time_us = (microschedule_lines * phantom->timing.h_total) / + time_us = (uint32_t)((microschedule_lines * phantom->timing.h_total) / (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 + dc->caps.subvp_prefetch_end_to_mall_start_us + - dc->caps.subvp_fw_processing_delay_us + 1; + dc->caps.subvp_fw_processing_delay_us + 1); if (time_us > max_microschedule_us) max_microschedule_us = time_us; @@ -762,19 +765,19 @@ static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context) break; } } - vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / - (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; - vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / - (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; - vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) * + vactive1_us = (int32_t)(((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / + (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000); + vactive2_us = (int32_t)(((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / + (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000); + vblank1_us = (int32_t)((((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) * subvp_pipes[0]->stream->timing.h_total) / - (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; - vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) * + (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000); + vblank2_us = (int32_t)((((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) * subvp_pipes[1]->stream->timing.h_total) / - (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; + (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000); - if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us && - (vactive2_us - vblank1_us) / 2 > max_microschedule_us) + if ((vactive1_us - vblank2_us) / 2 > (int32_t)max_microschedule_us && + (vactive2_us - vblank1_us) / 2 > (int32_t)max_microschedule_us) return true; return false; @@ -852,19 +855,19 @@ static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context) main_timing = &pipe->stream->timing; phantom_timing = &phantom_stream->timing; drr_timing = &drr_pipe->stream->timing; - prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / + prefetch_us = (uint16_t)((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + - dc->caps.subvp_prefetch_end_to_mall_start_us; - subvp_active_us = main_timing->v_addressable * main_timing->h_total / - (double)(main_timing->pix_clk_100hz * 100) * 1000000; - drr_frame_us = drr_timing->v_total * drr_timing->h_total / - (double)(drr_timing->pix_clk_100hz * 100) * 1000000; + dc->caps.subvp_prefetch_end_to_mall_start_us); + subvp_active_us = (uint16_t)(main_timing->v_addressable * main_timing->h_total / + (double)(main_timing->pix_clk_100hz * 100) * 1000000); + drr_frame_us = (uint16_t)(drr_timing->v_total * drr_timing->h_total / + (double)(drr_timing->pix_clk_100hz * 100) * 1000000); // P-State allow width and FW delays already included phantom_timing->v_addressable - mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / - (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; + mall_region_us = (uint16_t)(phantom_timing->v_addressable * phantom_timing->h_total / + (double)(phantom_timing->pix_clk_100hz * 100) * 1000000); stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; - drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / - (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us); + drr_stretched_vblank_us = (uint16_t)((drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / + (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us)); max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us; } @@ -901,7 +904,7 @@ static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context) struct pipe_ctx *subvp_pipe = NULL; bool found = false; bool schedulable = false; - uint32_t i = 0; + uint8_t i = 0; uint8_t vblank_index = 0; uint16_t prefetch_us = 0; uint16_t mall_region_us = 0; @@ -947,18 +950,18 @@ static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context) vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing; // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe // Also include the prefetch end to mallstart delay time - prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / + prefetch_us = (uint16_t)((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + - dc->caps.subvp_prefetch_end_to_mall_start_us; + dc->caps.subvp_prefetch_end_to_mall_start_us); // P-State allow width and FW delays already included phantom_timing->v_addressable - mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / - (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; - vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total / - (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; - vblank_blank_us = (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total / - (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; - subvp_active_us = main_timing->v_addressable * main_timing->h_total / - (double)(main_timing->pix_clk_100hz * 100) * 1000000; + mall_region_us = (uint16_t)(phantom_timing->v_addressable * phantom_timing->h_total / + (double)(phantom_timing->pix_clk_100hz * 100) * 1000000); + vblank_frame_us = (uint16_t)(vblank_timing->v_total * vblank_timing->h_total / + (double)(vblank_timing->pix_clk_100hz * 100) * 1000000); + vblank_blank_us = (uint16_t)((vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total / + (double)(vblank_timing->pix_clk_100hz * 100) * 1000000); + subvp_active_us = (uint16_t)(main_timing->v_addressable * main_timing->h_total / + (double)(main_timing->pix_clk_100hz * 100) * 1000000); max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us; // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, @@ -986,7 +989,7 @@ static bool subvp_subvp_admissable(struct dc *dc, struct dc_state *context) { bool result = false; - uint32_t i; + uint8_t i; uint8_t subvp_count = 0; uint32_t min_refresh = subvp_high_refresh_list.min_refresh, max_refresh = 0; uint64_t refresh_rate = 0; @@ -1013,8 +1016,8 @@ static bool subvp_subvp_admissable(struct dc *dc, } if (subvp_count == 2 && ((min_refresh < 120 && max_refresh < 120) || - (min_refresh >= subvp_high_refresh_list.min_refresh && - max_refresh <= subvp_high_refresh_list.max_refresh))) + (min_refresh >= (uint32_t)subvp_high_refresh_list.min_refresh && + max_refresh <= (uint32_t)subvp_high_refresh_list.max_refresh))) result = true; return result; @@ -1092,7 +1095,7 @@ static bool subvp_validate_static_schedulability(struct dc *dc, static void assign_subvp_index(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; int index = 0; for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -1100,7 +1103,7 @@ static void assign_subvp_index(struct dc *dc, struct dc_state *context) if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) { - pipe_ctx->subvp_index = index++; + pipe_ctx->subvp_index = (uint8_t)index++; } else { pipe_ctx->subvp_index = 0; } @@ -1224,7 +1227,8 @@ static bool update_pipe_slice_table_with_split_flags( */ struct pipe_ctx *pipe; bool odm; - int dc_pipe_idx, dml_pipe_idx = 0; + unsigned int dc_pipe_idx; + int dml_pipe_idx = 0; bool updated = false; for (dc_pipe_idx = 0; @@ -1466,7 +1470,7 @@ static bool dcn32_full_validate_bw_helper(struct dc *dc, *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); /* This may adjust vlevel and maxMpcComb */ - if (*vlevel < context->bw_ctx.dml.soc.num_states) { + if (*vlevel < (int)context->bw_ctx.dml.soc.num_states) { *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); vba->VoltageLevel = *vlevel; } @@ -1527,14 +1531,14 @@ static bool dcn32_full_validate_bw_helper(struct dc *dc, /* Check that vlevel requested supports pstate or not * if not, select the lowest vlevel that supports it */ - for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { + for (i = *vlevel; i < (int)context->bw_ctx.dml.soc.num_states; i++) { if (vba->DRAMClockChangeSupport[i][vba->maxMpcComb] != dm_dram_clock_change_unsupported) { *vlevel = i; break; } } - if (*vlevel < context->bw_ctx.dml.soc.num_states + if (*vlevel < (int)context->bw_ctx.dml.soc.num_states && subvp_validate_static_schedulability(dc, context, *vlevel)) found_supported_config = true; if (found_supported_config) { @@ -1566,7 +1570,7 @@ static bool dcn32_full_validate_bw_helper(struct dc *dc, *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); /* This may adjust vlevel and maxMpcComb */ - if (*vlevel < context->bw_ctx.dml.soc.num_states) { + if (*vlevel < (int)context->bw_ctx.dml.soc.num_states) { *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); vba->VoltageLevel = *vlevel; } @@ -1599,7 +1603,7 @@ static bool dcn32_full_validate_bw_helper(struct dc *dc, static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { if (!context->res_ctx.pipe_ctx[i].stream) @@ -1614,7 +1618,8 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) { - int i, pipe_idx, active_hubp_count = 0; + int pipe_idx, active_hubp_count = 0; + unsigned int i; bool usr_retraining_support = false; bool unbounded_req_enabled = false; struct vba_vars_st *vba = &context->bw_ctx.dml.vba; @@ -1624,12 +1629,12 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, /* Writeback MCIF_WB arbitration parameters */ dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); - context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; - context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; - context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; - context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; - context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; - context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; + context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(context->bw_ctx.dml.vba.DISPCLK * 1000); + context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(context->bw_ctx.dml.vba.DCFCLK * 1000); + context->bw_ctx.bw.dcn.clk.socclk_khz = (int)(context->bw_ctx.dml.vba.SOCCLK * 1000); + context->bw_ctx.bw.dcn.clk.dramclk_khz = (int)(context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16); + context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000); + context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(context->bw_ctx.dml.vba.FabricClock * 1000); context->bw_ctx.bw.dcn.clk.p_state_change_support = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != dm_dram_clock_change_unsupported; @@ -1641,7 +1646,7 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); - context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000; + context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = (int)(context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000); if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported) context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false; else @@ -1650,8 +1655,8 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; ASSERT(usr_retraining_support); - if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) - context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; + if ((unsigned int)context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) + context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)dc->debug.min_disp_clk_khz; unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt); @@ -1670,13 +1675,13 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, continue; if (context->res_ctx.pipe_ctx[i].plane_state) active_hubp_count++; - pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, + pipes[pipe_idx].pipe.dest.vstartup_start = (unsigned int)get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); - pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, + pipes[pipe_idx].pipe.dest.vupdate_offset = (unsigned int)get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); - pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, + pipes[pipe_idx].pipe.dest.vupdate_width = (unsigned int)get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); - pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, + pipes[pipe_idx].pipe.dest.vready_offset = (unsigned int)get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) { @@ -1684,20 +1689,20 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0; context->res_ctx.pipe_ctx[i].unbounded_req = false; } else { - context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt, + context->res_ctx.pipe_ctx[i].det_buffer_size_kb = (int)get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled; } if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) - context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; + context->bw_ctx.bw.dcn.clk.dppclk_khz = (int)(pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000); if (context->res_ctx.pipe_ctx[i].plane_state) - context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; + context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = (int)(pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000); else context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0; context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; - context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = (unsigned int)get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0) context->res_ctx.pipe_ctx[i].has_vactive_margin = true; @@ -1740,10 +1745,10 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, /*save a original dppclock copy*/ context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; - context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz - * 1000; - context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz - * 1000; + context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = (int)(context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz + * 1000); + context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = (int)(context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz + * 1000); context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context); @@ -1779,7 +1784,7 @@ static struct pipe_ctx *dcn32_find_split_pipe( if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) { pipe = &context->res_ctx.pipe_ctx[old_index]; - pipe->pipe_idx = old_index; + pipe->pipe_idx = (uint8_t)old_index; } if (!pipe) @@ -1788,7 +1793,7 @@ static struct pipe_ctx *dcn32_find_split_pipe( && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) { if (context->res_ctx.pipe_ctx[i].stream == NULL) { pipe = &context->res_ctx.pipe_ctx[i]; - pipe->pipe_idx = i; + pipe->pipe_idx = (uint8_t)i; break; } } @@ -1803,7 +1808,7 @@ static struct pipe_ctx *dcn32_find_split_pipe( for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { if (context->res_ctx.pipe_ctx[i].stream == NULL) { pipe = &context->res_ctx.pipe_ctx[i]; - pipe->pipe_idx = i; + pipe->pipe_idx = (uint8_t)i; break; } } @@ -1846,13 +1851,13 @@ static bool dcn32_split_stream_for_mpc_or_odm( *sec_pipe = *pri_pipe; - sec_pipe->pipe_idx = pipe_idx; + sec_pipe->pipe_idx = (uint8_t)pipe_idx; sec_pipe->plane_res.mi = pool->mis[pipe_idx]; sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; - sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; + sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst; sec_pipe->stream_res.dsc = NULL; if (odm) { if (pri_pipe->next_odm_pipe) { @@ -1904,7 +1909,8 @@ static bool dcn32_apply_merge_split_flags_helper( int *split, bool *merge) { - int i, pipe_idx; + int pipe_idx; + unsigned int i; bool newly_split[MAX_PIPES] = { false }; struct vba_vars_st *vba = &context->bw_ctx.dml.vba; @@ -2165,7 +2171,7 @@ bool dcn32_internal_validate_bw(struct dc *dc, context->bw_ctx.dml.validate_max_state = false; - if (vlevel < context->bw_ctx.dml.soc.num_states) { + if (vlevel < (int)context->bw_ctx.dml.soc.num_states) { memset(split, 0, sizeof(split)); memset(merge, 0, sizeof(merge)); vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); @@ -2179,7 +2185,7 @@ bool dcn32_internal_validate_bw(struct dc *dc, if (vlevel == context->bw_ctx.dml.soc.num_states) goto validate_fail; - for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { + for (i = 0, pipe_idx = 0; i < (int)dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; @@ -2233,7 +2239,7 @@ bool dcn32_internal_validate_bw(struct dc *dc, flag_max_mpc_comb != context->bw_ctx.dml.vba.maxMpcComb) { /* check the context constructed with pipe split flags is still valid*/ bool flags_valid = false; - for (i = flag_vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { + for (i = flag_vlevel; i < (int)context->bw_ctx.dml.soc.num_states; i++) { if (vba->ModeSupport[i][flag_max_mpc_comb]) { vba->maxMpcComb = flag_max_mpc_comb; vba->VoltageLevel = i; @@ -2267,7 +2273,8 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, int pipe_cnt, int vlevel) { - int i, pipe_idx, vlevel_temp = 0; + int pipe_idx, vlevel_temp = 0; + unsigned int i; double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz; double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; double dram_speed_from_validation = context->bw_ctx.dml.vba.DRAMSpeed; @@ -2276,7 +2283,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, dm_dram_clock_change_unsupported; unsigned int dummy_latency_index = 0; int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; - unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; + unsigned int min_dram_speed_mts = (unsigned int)context->bw_ctx.dml.vba.DRAMSpeed; bool subvp_in_use = dcn32_subvp_in_use(dc, context); unsigned int min_dram_speed_mts_margin; bool need_fclk_lat_as_dummy = false; @@ -2405,16 +2412,16 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; } - context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = (uint32_t)(get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = (uint32_t)(get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); /* Set D: * All clocks min. @@ -2469,7 +2476,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, } if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { - min_dram_speed_mts = dram_speed_from_validation; + min_dram_speed_mts = (unsigned int)dram_speed_from_validation; min_dram_speed_mts_margin = 160; context->bw_ctx.dml.soc.dram_clock_change_latency_us = @@ -2501,20 +2508,20 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; } - context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); /* On DCN32/321, PMFW will set PSTATE_CHANGE_TYPE = 1 (FCLK) for UCLK dummy p-state. * In this case we must program FCLK WM Set C to use the UCLK dummy p-state WM * value. */ - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = (uint32_t)(get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) { /* The only difference between A and C is p-state latency, if p-state is not supported @@ -2526,7 +2533,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, /* Calculate FCLK p-state change watermark based on FCLK pstate change latency in case * UCLK p-state is not supported, to avoid underflow in case FCLK pstate is supported */ - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = (uint32_t)(get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); } else { /* Set A: * All clocks min. @@ -2540,16 +2547,16 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; - context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = (uint32_t)(get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = (uint32_t)(get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); } /* Make set D = set A since we do not optimized watermarks for MALL */ @@ -2574,7 +2581,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, pipe_idx++; } - context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; + context->perf_params.stutter_period_us = (unsigned int)context->bw_ctx.dml.vba.StutterPeriod; /* for proper prefetch calculations, if dummy lat > fclk lat, use fclk lat = dummy lat */ if (need_fclk_lat_as_dummy) @@ -2608,18 +2615,18 @@ static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; if (optimal_fclk) - *optimal_fclk = bw_from_dram / - (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); + *optimal_fclk = (unsigned int)(bw_from_dram / + (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100))); if (optimal_dcfclk) - *optimal_dcfclk = bw_from_dram / - (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); + *optimal_dcfclk = (unsigned int)(bw_from_dram / + (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100))); } static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, unsigned int index) { - int i; + unsigned int i; if (*num_entries == 0) return; @@ -2660,13 +2667,13 @@ void dcn32_patch_dpm_table(struct clk_bw_params *bw_params) * 0, will cause it to skip building the clock table. */ if (max_dcfclk_mhz == 0) - bw_params->clk_table.entries[0].dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; + bw_params->clk_table.entries[0].dcfclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].dcfclk_mhz; if (max_dispclk_mhz == 0) - bw_params->clk_table.entries[0].dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; + bw_params->clk_table.entries[0].dispclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].dispclk_mhz; if (max_dtbclk_mhz == 0) - bw_params->clk_table.entries[0].dtbclk_mhz = dcn3_2_soc.clock_limits[0].dtbclk_mhz; + bw_params->clk_table.entries[0].dtbclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].dtbclk_mhz; if (max_uclk_mhz == 0) - bw_params->clk_table.entries[0].memclk_mhz = dcn3_2_soc.clock_limits[0].dram_speed_mts / 16; + bw_params->clk_table.entries[0].memclk_mhz = (unsigned int)(dcn3_2_soc.clock_limits[0].dram_speed_mts / 16); } static void swap_table_entries(struct _vcs_dpi_voltage_scaling_st *first_entry, @@ -2686,9 +2693,9 @@ static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, unsigned int end_index = 0; unsigned int current_bw = 0; - for (int i = 0; i < (*num_entries - 1); i++) { + for (unsigned int i = 0; i < (*num_entries - 1); i++) { if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) { - current_bw = table[i].net_bw_in_kbytes_sec; + current_bw = (unsigned int)table[i].net_bw_in_kbytes_sec; start_index = i; end_index = ++i; @@ -2697,8 +2704,8 @@ static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, } if (start_index != end_index) { - for (int j = start_index; j < end_index; j++) { - for (int k = start_index; k < end_index; k++) { + for (unsigned int j = start_index; j < end_index; j++) { + for (unsigned int k = start_index; k < end_index; k++) { if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz) swap_table_entries(&table[k], &table[k+1]); } @@ -2717,7 +2724,7 @@ static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, */ static void remove_inconsistent_entries(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) { - for (int i = 0; i < (*num_entries - 1); i++) { + for (unsigned int i = 0; i < (*num_entries - 1); i++) { if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) { if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) || (table[i].fabricclk_mhz > table[i+1].fabricclk_mhz)) @@ -2765,7 +2772,8 @@ static int override_max_clk_values(struct clk_limit_table_entry *max_clk_limit, static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params, struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) { - int i, j; + int i; + unsigned int j; struct _vcs_dpi_voltage_scaling_st entry = {0}; struct clk_limit_table_entry max_clk_data = {0}; @@ -2835,12 +2843,12 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk max_clk_data.dppclk_mhz = max_clk_data.dispclk_mhz; if (max_clk_data.fclk_mhz == 0) - max_clk_data.fclk_mhz = max_clk_data.dcfclk_mhz * + max_clk_data.fclk_mhz = (unsigned int)(max_clk_data.dcfclk_mhz * dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / - dcn3_2_soc.pct_ideal_fabric_bw_after_urgent; + dcn3_2_soc.pct_ideal_fabric_bw_after_urgent); if (max_clk_data.phyclk_mhz == 0) - max_clk_data.phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; + max_clk_data.phyclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].phyclk_mhz; *num_entries = 0; entry.dispclk_mhz = max_clk_data.dispclk_mhz; @@ -2852,8 +2860,8 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; // Insert all the DCFCLK STAs - for (i = 0; i < num_dcfclk_stas; i++) { - entry.dcfclk_mhz = dcfclk_sta_targets[i]; + for (j = 0; j < num_dcfclk_stas; j++) { + entry.dcfclk_mhz = dcfclk_sta_targets[j]; entry.fabricclk_mhz = 0; entry.dram_speed_mts = 0; @@ -2872,10 +2880,10 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk insert_entry_into_table_sorted(table, num_entries, &entry); // Insert the UCLK DPMS - for (i = 0; i < num_uclk_dpms; i++) { + for (j = 0; j < num_uclk_dpms; j++) { entry.dcfclk_mhz = 0; entry.fabricclk_mhz = 0; - entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16; + entry.dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16; get_optimal_ntuple(&entry); entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry); @@ -2884,9 +2892,9 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk // If FCLK is coarse grained, insert individual DPMs. if (num_fclk_dpms > 2) { - for (i = 0; i < num_fclk_dpms; i++) { + for (j = 0; j < num_fclk_dpms; j++) { entry.dcfclk_mhz = 0; - entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; + entry.fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz; entry.dram_speed_mts = 0; get_optimal_ntuple(&entry); @@ -2976,7 +2984,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk // Remove duplicate states, note duplicate states are always neighbouring since table is sorted. i = 0; - while (i < *num_entries - 1) { + while (i < ((int)*num_entries - 1)) { if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz && table[i].dram_speed_mts == table[i + 1].dram_speed_mts) @@ -3093,9 +3101,12 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel); } - if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) - dc->dml2_options.bbox_overrides.dram_chanel_width_bytes = - dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; + if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) { + unsigned int dram_channel_width_bytes = (unsigned int)dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; + + dc->dml2_options.bbox_overrides.dram_chanel_width_bytes = dram_channel_width_bytes; + dcn3_2_soc.dram_channel_width_bytes = dram_channel_width_bytes; + } /* DML DSC delay factor workaround */ dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0; @@ -3142,13 +3153,13 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa if (min_dcfclk > dcfclk_sta_targets[0]) dcfclk_sta_targets[0] = min_dcfclk; if (!max_dcfclk_mhz) - max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; + max_dcfclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].dcfclk_mhz; if (!max_dispclk_mhz) - max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; + max_dispclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].dispclk_mhz; if (!max_dppclk_mhz) - max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz; + max_dppclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].dppclk_mhz; if (!max_phyclk_mhz) - max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; + max_phyclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].phyclk_mhz; if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array @@ -3365,8 +3376,8 @@ bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe) refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 + (uint64_t)pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1); - refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total); - refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total); + refresh_rate = (uint32_t)div_u64(refresh_rate, pipe->stream->timing.v_total); + refresh_rate = (uint32_t)div_u64(refresh_rate, pipe->stream->timing.h_total); if (refresh_rate >= min_refresh && refresh_rate <= max_refresh && dcn32_check_native_scaling_for_res(pipe, width, height)) { @@ -3411,9 +3422,9 @@ bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context if (!pipe_ctx->stream) continue; - refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100 + + refresh_rate = (unsigned int)((pipe_ctx->stream->timing.pix_clk_100hz * 100 + pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1) - / (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total); + / (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total)); if (refresh_rate < min_refresh) min_refresh = refresh_rate; @@ -3421,9 +3432,9 @@ bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context if (!dc->debug.disable_subvp_high_refresh && min_refresh >= subvp_min_refresh && pipe->stream && pipe->plane_state && !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) { - refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + + refresh_rate = (unsigned int)((pipe->stream->timing.pix_clk_100hz * 100 + pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) - / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); + / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total)); if (refresh_rate >= subvp_min_refresh && refresh_rate <= subvp_max_refresh) { for (i = 0; i < SUBVP_HIGH_REFRESH_LIST_LEN; i++) { uint32_t width = subvp_high_refresh_list.res[i].width; @@ -3543,8 +3554,8 @@ bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, stru /* Every plane (apart from the ones driven by the FPO pipes) needs to have active margin * in order for us to have found a valid "vactive" config for FPO + Vactive */ - blank_us = ((pipe->stream->timing.v_total - pipe->stream->timing.v_addressable) * pipe->stream->timing.h_total / - (double)(pipe->stream->timing.pix_clk_100hz * 100)) * 1000000; + blank_us = (unsigned int)(((pipe->stream->timing.v_total - pipe->stream->timing.v_addressable) * pipe->stream->timing.h_total / + (double)(pipe->stream->timing.pix_clk_100hz * 100)) * 1000000); if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] < vactive_margin_req_us || pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed || blank_us >= dc->debug.fpo_vactive_max_blank_us) { vactive_found = false; @@ -3572,7 +3583,7 @@ void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context) if (context->bw_ctx.dml.vba.DRAMSpeed <= dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16 && num_mclk_levels > 1) { context->bw_ctx.dml.vba.DRAMSpeed = dc->clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16; - context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; + context->bw_ctx.bw.dcn.clk.dramclk_khz = (int)(context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16); } } } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index 0782a34689a0..505b5a5f212e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -92,8 +92,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.WritebackHTaps[k], mode_lib->vba.WritebackVTaps[k], mode_lib->vba.WritebackSourceWidth[k], - mode_lib->vba.WritebackDestinationWidth[k], - mode_lib->vba.HTotal[k], mode_lib->vba.WritebackLineBufferSize, + (long)mode_lib->vba.WritebackDestinationWidth[k], + mode_lib->vba.HTotal[k], (unsigned int)mode_lib->vba.WritebackLineBufferSize, mode_lib->vba.DISPCLKDPPCLKVCOSpeed)); } } @@ -305,8 +305,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman .dummy_boolean); /* bool *ViewportSizeSupport */ } - v->CompBufReservedSpaceZs = v->CompBufReservedSpaceKBytes * 1024.0 / 256.0; - v->CompBufReservedSpace64B = v->CompBufReservedSpaceKBytes * 1024.0 / 64.0; + v->CompBufReservedSpaceZs = (unsigned int)(v->CompBufReservedSpaceKBytes * 1024.0 / 256.0); + v->CompBufReservedSpace64B = (unsigned int)(v->CompBufReservedSpaceKBytes * 1024.0 / 64.0); // DCFCLK Deep Sleep dml32_CalculateDCFCLKDeepSleep( @@ -326,7 +326,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.DPPCLK, v->ReadBandwidthSurfaceLuma, v->ReadBandwidthSurfaceChroma, - mode_lib->vba.ReturnBusWidth, + (int)mode_lib->vba.ReturnBusWidth, /* Output */ &v->DCFCLKDeepSleep); @@ -479,7 +479,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.HostVMMaxNonCachedPageTableLevels, mode_lib->vba.GPUVMMaxPageTableLevels, mode_lib->vba.GPUVMMinPageSizeKBytes, - mode_lib->vba.HostVMMinPageSize, + (unsigned int)mode_lib->vba.HostVMMinPageSize, /* Output */ v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_boolean_array2[0], // Boolean PTEBufferSizeNotExceeded[] @@ -528,12 +528,12 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman } - v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.ReorderBytes = mode_lib->vba.NumberOfChannels + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.ReorderBytes = (unsigned int)(mode_lib->vba.NumberOfChannels * dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly, mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly); + mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly)); - v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.VMDataOnlyReturnBW = dml32_get_return_bw_mbps_vm_only( + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.VMDataOnlyReturnBW = (unsigned int)dml32_get_return_bw_mbps_vm_only( &mode_lib->vba.soc, mode_lib->vba.VoltageLevel, mode_lib->vba.DCFCLK, @@ -577,7 +577,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman } v->UrgentExtraLatency = dml32_CalculateExtraLatency( - mode_lib->vba.RoundTripPingLatencyCycles, + (int)mode_lib->vba.RoundTripPingLatencyCycles, v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.ReorderBytes, mode_lib->vba.DCFCLK, mode_lib->vba.TotalActiveDPP, @@ -591,7 +591,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.DPPPerPlane, v->dpte_group_bytes, v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor, - mode_lib->vba.HostVMMinPageSize, + (unsigned int)mode_lib->vba.HostVMMinPageSize, mode_lib->vba.HostVMMaxNonCachedPageTableLevels); mode_lib->vba.TCalc = 24.0 / v->DCFCLKDeepSleep; @@ -605,9 +605,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.WritebackHRatio[k], mode_lib->vba.WritebackVRatio[k], mode_lib->vba.WritebackVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k], - mode_lib->vba.WritebackDestinationHeight[k], - mode_lib->vba.WritebackSourceHeight[k], + (long)mode_lib->vba.WritebackDestinationWidth[k], + (int)mode_lib->vba.WritebackDestinationHeight[k], + (int)mode_lib->vba.WritebackSourceHeight[k], mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK; } else v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0; @@ -622,9 +622,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.WritebackHRatio[j], mode_lib->vba.WritebackVRatio[j], mode_lib->vba.WritebackVTaps[j], - mode_lib->vba.WritebackDestinationWidth[j], - mode_lib->vba.WritebackDestinationHeight[j], - mode_lib->vba.WritebackSourceHeight[j], + (int)mode_lib->vba.WritebackDestinationWidth[j], + (int)mode_lib->vba.WritebackDestinationHeight[j], + (int)mode_lib->vba.WritebackSourceHeight[j], mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK); } } @@ -693,12 +693,12 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.UseUnboundedRequesting); for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { - v->MaxVStartupLines[k] = ((mode_lib->vba.Interlace[k] && + v->MaxVStartupLines[k] = (unsigned int)(((mode_lib->vba.Interlace[k] && !mode_lib->vba.ProgressiveToInterlaceUnitInOPP) ? dml_floor((mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) / 2.0, 1.0) : mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) - dml_max(1.0, dml_ceil((double) v->WritebackDelay[mode_lib->vba.VoltageLevel][k] - / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1)); + / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1))); // Clamp to max OTG vstartup register limit if (v->MaxVStartupLines[k] > 1023) @@ -714,7 +714,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->MaximumMaxVStartupLines = 0; for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) - v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); + v->MaximumMaxVStartupLines = (unsigned int)dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); ImmediateFlipRequirementFinal = false; @@ -789,21 +789,21 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman &v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe, v->DSCDelay[k], (unsigned int) (v->SwathWidthY[k] / v->HRatio[k]), - dml_min(v->VStartupLines, v->MaxVStartupLines[k]), + (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]), v->MaxVStartupLines[k], v->UrgentLatency, v->UrgentExtraLatency, v->TCalc, - v->PDEAndMetaPTEBytesFrame[k], - v->MetaRowByte[k], - v->PixelPTEBytesPerRow[k], + (unsigned int)v->PDEAndMetaPTEBytesFrame[k], + (unsigned int)v->MetaRowByte[k], + (unsigned int)v->PixelPTEBytesPerRow[k], v->PrefetchSourceLinesY[k], - v->SwathWidthY[k], - v->VInitPreFillY[k], + (unsigned int)v->SwathWidthY[k], + (unsigned int)v->VInitPreFillY[k], v->MaxNumSwathY[k], v->PrefetchSourceLinesC[k], - v->SwathWidthC[k], - v->VInitPreFillC[k], + (unsigned int)v->SwathWidthC[k], + (unsigned int)v->VInitPreFillC[k], v->MaxNumSwathC[k], v->swath_width_luma_ub[k], v->swath_width_chroma_ub[k], @@ -839,7 +839,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman dml_print("DML::%s: k=%0d Prefetch calculation errResult=%0d\n", __func__, k, mode_lib->vba.ErrorResult[k]); #endif - v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]); + v->VStartup[k] = (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]); } for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { @@ -1019,18 +1019,18 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.TotImmediateFlipBytes = 0; for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required) { - mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes + mode_lib->vba.TotImmediateFlipBytes = (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + mode_lib->vba.DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] - + v->MetaRowByte[k]); + + v->MetaRowByte[k])); if (v->use_one_row_for_frame_flip[k][0][0]) { mode_lib->vba.TotImmediateFlipBytes = - mode_lib->vba.TotImmediateFlipBytes - + 2 * v->PixelPTEBytesPerRow[k]; + (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + + 2 * v->PixelPTEBytesPerRow[k]); } else { mode_lib->vba.TotImmediateFlipBytes = - mode_lib->vba.TotImmediateFlipBytes - + v->PixelPTEBytesPerRow[k]; + (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + + v->PixelPTEBytesPerRow[k]); } } } @@ -1042,10 +1042,10 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.HostVMEnable, mode_lib->vba.HostVMMaxNonCachedPageTableLevels, mode_lib->vba.GPUVMEnable, - mode_lib->vba.HostVMMinPageSize, - v->PDEAndMetaPTEBytesFrame[k], - v->MetaRowByte[k], - v->PixelPTEBytesPerRow[k], + (unsigned int)mode_lib->vba.HostVMMinPageSize, + (unsigned int)v->PDEAndMetaPTEBytesFrame[k], + (unsigned int)v->MetaRowByte[k], + (unsigned int)v->PixelPTEBytesPerRow[k], mode_lib->vba.BandwidthAvailableForImmediateFlip, mode_lib->vba.TotImmediateFlipBytes, mode_lib->vba.SourcePixelFormat[k], @@ -1439,14 +1439,14 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman isInterlaceTiming = (mode_lib->vba.Interlace[k] && !mode_lib->vba.ProgressiveToInterlaceUnitInOPP); - v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((mode_lib->vba.VTotal[k] - + v->MIN_DST_Y_NEXT_START[k] = (unsigned int)(((isInterlaceTiming ? dml_floor((mode_lib->vba.VTotal[k] - mode_lib->vba.VFrontPorch[k]) / 2.0, 1.0) : mode_lib->vba.VTotal[k]) - mode_lib->vba.VFrontPorch[k]) + dml_max(1.0, dml_ceil(v->WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0)) + dml_floor(4.0 * v->TSetup[k] / (mode_lib->vba.HTotal[k] - / mode_lib->vba.PixelClock[k]), 1.0) / 4.0; + / mode_lib->vba.PixelClock[k]), 1.0) / 4.0); v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]); @@ -1724,7 +1724,8 @@ static void mode_support_configuration(struct vba_vars_st *v, void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) { struct vba_vars_st *v = &mode_lib->vba; - int i, j, start_state; + int i, start_state; + unsigned int j; unsigned int k, m; unsigned int MaximumMPCCombine; unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth; @@ -1931,7 +1932,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 || mode_lib->vba.SourcePixelFormat[k] == dm_420_10 || mode_lib->vba.SourcePixelFormat[k] == dm_420_12) { - v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma / 2.0; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma = (unsigned int)(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma / 2.0); } else { v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma; } @@ -2030,7 +2031,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.MPCCombineMethodIncompatible = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsNeededForPStateChangeAndVoltage && v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsPossible; - for (i = start_state; i < v->soc.num_states; i++) { + for (i = start_state; i < (int)v->soc.num_states; i++) { for (j = 0; j < 2; j++) { mode_lib->vba.TotalNumberOfActiveDPP[i][j] = 0; mode_lib->vba.TotalAvailablePipesSupport[i][j] = true; @@ -2103,7 +2104,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeNoDSC, v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeDSC, mode_lib->vba.DSCEnable[k], - mode_lib->vba.OutputLinkDPLanes[k], + (int)mode_lib->vba.OutputLinkDPLanes[k], mode_lib->vba.OutputLinkDPRate[k], /* Output */ @@ -2237,9 +2238,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.WritebackHTaps[k], mode_lib->vba.WritebackVTaps[k], mode_lib->vba.WritebackSourceWidth[k], - mode_lib->vba.WritebackDestinationWidth[k], + (long)mode_lib->vba.WritebackDestinationWidth[k], mode_lib->vba.HTotal[k], - mode_lib->vba.WritebackLineBufferSize, + (unsigned int)mode_lib->vba.WritebackLineBufferSize, mode_lib->vba.DISPCLKDPPCLKVCOSpeed)); } } @@ -2307,7 +2308,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } - for (i = start_state; i < v->soc.num_states; ++i) { + for (i = start_state; i < (int)v->soc.num_states; ++i) { mode_lib->vba.ExceededMultistreamSlots[i] = false; for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k) { @@ -2410,7 +2411,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } - for (i = start_state; i < v->soc.num_states; ++i) { + for (i = start_state; i < (int)v->soc.num_states; ++i) { mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = false; for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { if (mode_lib->vba.BlendingAndTiming[k] == k @@ -2427,7 +2428,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } - for (i = start_state; i < v->soc.num_states; ++i) { + for (i = start_state; i < (int)v->soc.num_states; ++i) { mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = true; mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = true; for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { @@ -2445,7 +2446,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } - for (i = start_state; i < v->soc.num_states; i++) { + for (i = start_state; i < (int)v->soc.num_states; i++) { mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = false; for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { if (mode_lib->vba.BlendingAndTiming[k] == k) { @@ -2482,7 +2483,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l /* Check DSC Unit and Slices Support */ v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0; - for (i = start_state; i < v->soc.num_states; ++i) { + for (i = start_state; i < (int)v->soc.num_states; ++i) { mode_lib->vba.NotEnoughDSCUnits[i] = false; mode_lib->vba.NotEnoughDSCSlices[i] = false; v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0; @@ -2517,7 +2518,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } /*DSC Delay per state*/ - for (i = start_state; i < v->soc.num_states; ++i) { + for (i = start_state; i < (int)v->soc.num_states; ++i) { for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { mode_lib->vba.DSCDelayPerState[i][k] = dml32_DSCDelayRequirement( mode_lib->vba.RequiresDSC[i][k], mode_lib->vba.ODMCombineEnablePerState[i][k], @@ -2531,7 +2532,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { for (m = 0; m <= mode_lib->vba.NumberOfActiveSurfaces - 1; m++) { - for (j = 0; j <= mode_lib->vba.NumberOfActiveSurfaces - 1; j++) { + for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; j++) { if (mode_lib->vba.BlendingAndTiming[k] == m && mode_lib->vba.RequiresDSC[i][m] == true) { mode_lib->vba.DSCDelayPerState[i][k] = @@ -2622,8 +2623,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.swath_width_luma_ub_this_state[k]; mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k] = mode_lib->vba.swath_width_chroma_ub_this_state[k]; - mode_lib->vba.SwathWidthYAllStates[i][j][k] = mode_lib->vba.SwathWidthYThisState[k]; - mode_lib->vba.SwathWidthCAllStates[i][j][k] = mode_lib->vba.SwathWidthCThisState[k]; + mode_lib->vba.SwathWidthYAllStates[i][j][k] = (unsigned int)mode_lib->vba.SwathWidthYThisState[k]; + mode_lib->vba.SwathWidthCAllStates[i][j][k] = (unsigned int)mode_lib->vba.SwathWidthCThisState[k]; mode_lib->vba.SwathHeightYAllStates[i][j][k] = mode_lib->vba.SwathHeightYThisState[k]; mode_lib->vba.SwathHeightCAllStates[i][j][k] = mode_lib->vba.SwathHeightCThisState[k]; mode_lib->vba.UnboundedRequestEnabledAllStates[i][j] = @@ -2682,7 +2683,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.SurfaceSizeInMALL, &mode_lib->vba.ExceededMALLSize); - for (i = start_state; i < v->soc.num_states; i++) { + for (i = start_state; i < (int)v->soc.num_states; i++) { for (j = 0; j < 2; j++) { for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { mode_lib->vba.swath_width_luma_ub_this_state[k] = @@ -2696,9 +2697,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DETBufferSizeInKByteThisState[k] = mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k]; mode_lib->vba.DETBufferSizeYThisState[k] = - mode_lib->vba.DETBufferSizeYAllStates[i][j][k]; + (unsigned int)mode_lib->vba.DETBufferSizeYAllStates[i][j][k]; mode_lib->vba.DETBufferSizeCThisState[k] = - mode_lib->vba.DETBufferSizeCAllStates[i][j][k]; + (unsigned int)mode_lib->vba.DETBufferSizeCAllStates[i][j][k]; mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k]; mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k]; } @@ -2772,7 +2773,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.HostVMMaxNonCachedPageTableLevels, mode_lib->vba.GPUVMMaxPageTableLevels, mode_lib->vba.GPUVMMinPageSizeKBytes, - mode_lib->vba.HostVMMinPageSize, + (unsigned int)mode_lib->vba.HostVMMinPageSize, /* Output */ mode_lib->vba.PTEBufferSizeNotExceededPerState, @@ -2901,7 +2902,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.RequiredDPPCLKThisState, mode_lib->vba.ReadBandwidthLuma, mode_lib->vba.ReadBandwidthChroma, - mode_lib->vba.ReturnBusWidth, + (int)mode_lib->vba.ReturnBusWidth, /* Output */ &mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j]); @@ -2921,9 +2922,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.WritebackHRatio[k], mode_lib->vba.WritebackVRatio[k], mode_lib->vba.WritebackVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k], - mode_lib->vba.WritebackDestinationHeight[k], - mode_lib->vba.WritebackSourceHeight[k], + (long)mode_lib->vba.WritebackDestinationWidth[k], + (int)mode_lib->vba.WritebackDestinationHeight[k], + (int)mode_lib->vba.WritebackSourceHeight[k], mode_lib->vba.HTotal[k]) / mode_lib->vba.RequiredDISPCLK[i][j]; } else { @@ -2940,9 +2941,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.WritebackHRatio[m], mode_lib->vba.WritebackVRatio[m], mode_lib->vba.WritebackVTaps[m], - mode_lib->vba.WritebackDestinationWidth[m], - mode_lib->vba.WritebackDestinationHeight[m], - mode_lib->vba.WritebackSourceHeight[m], + (int)mode_lib->vba.WritebackDestinationWidth[m], + (int)mode_lib->vba.WritebackDestinationHeight[m], + (int)mode_lib->vba.WritebackSourceHeight[m], mode_lib->vba.HTotal[m]) / mode_lib->vba.RequiredDISPCLK[i][j]); } @@ -2979,10 +2980,10 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } - v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ReorderingBytes = mode_lib->vba.NumberOfChannels + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ReorderingBytes = (unsigned int)(mode_lib->vba.NumberOfChannels * dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly, mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly); + mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly)); dml32_CalculateMinAndMaxPrefetchMode(mode_lib->vba.AllowForPStateChangeOrStutterInVBlankFinal, &mode_lib->vba.MinPrefetchMode, @@ -3060,8 +3061,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DRAMClockChangeLatency, mode_lib->vba.FCLKChangeLatency, mode_lib->vba.SREnterPlusExitTime, - mode_lib->vba.ReturnBusWidth, - mode_lib->vba.RoundTripPingLatencyCycles, + (int)mode_lib->vba.ReturnBusWidth, + (int)mode_lib->vba.RoundTripPingLatencyCycles, v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ReorderingBytes, mode_lib->vba.PixelChunkSizeInKByte, mode_lib->vba.MetaChunkSize, @@ -3069,7 +3070,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.GPUVMMaxPageTableLevels, mode_lib->vba.HostVMEnable, mode_lib->vba.NumberOfActiveSurfaces, - mode_lib->vba.HostVMMinPageSize, + (unsigned int)mode_lib->vba.HostVMMinPageSize, mode_lib->vba.HostVMMaxNonCachedPageTableLevels, mode_lib->vba.DynamicMetadataVMEnabled, mode_lib->vba.ImmediateFlipRequiredFinal, @@ -3187,9 +3188,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DETBufferSizeInKByteThisState[k] = mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k]; mode_lib->vba.DETBufferSizeYThisState[k] = - mode_lib->vba.DETBufferSizeYAllStates[i][j][k]; + (unsigned int)mode_lib->vba.DETBufferSizeYAllStates[i][j][k]; mode_lib->vba.DETBufferSizeCThisState[k] = - mode_lib->vba.DETBufferSizeCAllStates[i][j][k]; + (unsigned int)mode_lib->vba.DETBufferSizeCAllStates[i][j][k]; } mode_lib->vba.VActiveBandwithSupport[i][j] = dml32_CalculateVActiveBandwithSupport( @@ -3236,14 +3237,14 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l / v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.VMDataOnlyReturnBWPerState; mode_lib->vba.ExtraLatency = dml32_CalculateExtraLatency( - mode_lib->vba.RoundTripPingLatencyCycles, v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ReorderingBytes, + (int)mode_lib->vba.RoundTripPingLatencyCycles, v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ReorderingBytes, mode_lib->vba.DCFCLKState[i][j], mode_lib->vba.TotalNumberOfActiveDPP[i][j], mode_lib->vba.PixelChunkSizeInKByte, mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j], mode_lib->vba.MetaChunkSize, mode_lib->vba.ReturnBWPerState[i][j], mode_lib->vba.GPUVMEnable, mode_lib->vba.HostVMEnable, mode_lib->vba.NumberOfActiveSurfaces, mode_lib->vba.NoOfDPPThisState, mode_lib->vba.dpte_group_bytes, - v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.HostVMInefficiencyFactor, mode_lib->vba.HostVMMinPageSize, + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.HostVMInefficiencyFactor, (unsigned int)mode_lib->vba.HostVMMinPageSize, mode_lib->vba.HostVMMaxNonCachedPageTableLevels); v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NextPrefetchModeState = mode_lib->vba.MinPrefetchMode; @@ -3295,23 +3296,23 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l k, v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.HostVMInefficiencyFactor, &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe, - v->DSCDelayPerState[i][k], - v->SwathWidthYThisState[k] / v->HRatio[k], - dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), - v->MaximumVStartup[i][j][k], + (unsigned int)v->DSCDelayPerState[i][k], + (unsigned int)(v->SwathWidthYThisState[k] / v->HRatio[k]), + (unsigned int)dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), + (unsigned int)v->MaximumVStartup[i][j][k], v->UrgLatency[i], v->ExtraLatency, v->TimeCalc, - v->PDEAndMetaPTEBytesPerFrame[i][j][k], - v->MetaRowBytes[i][j][k], - v->DPTEBytesPerRow[i][j][k], + (unsigned int)v->PDEAndMetaPTEBytesPerFrame[i][j][k], + (unsigned int)v->MetaRowBytes[i][j][k], + (unsigned int)v->DPTEBytesPerRow[i][j][k], v->PrefetchLinesY[i][j][k], - v->SwathWidthYThisState[k], - v->PrefillY[k], + (unsigned int)v->SwathWidthYThisState[k], + (unsigned int)v->PrefillY[k], v->MaxNumSwY[k], v->PrefetchLinesC[i][j][k], - v->SwathWidthCThisState[k], - v->PrefillC[k], + (unsigned int)v->SwathWidthCThisState[k], + (unsigned int)v->PrefillC[k], v->MaxNumSwC[k], v->swath_width_luma_ub_this_state[k], v->swath_width_chroma_ub_this_state[k], @@ -3451,23 +3452,23 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.UrgentBurstFactorChromaPre, mode_lib->vba.UrgentBurstFactorCursorPre); - mode_lib->vba.TotImmediateFlipBytes = 0.0; + mode_lib->vba.TotImmediateFlipBytes = 0; for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { if (!(mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_not_required)) { mode_lib->vba.TotImmediateFlipBytes = - mode_lib->vba.TotImmediateFlipBytes + (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + mode_lib->vba.NoOfDPP[i][j][k] * mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k] - + mode_lib->vba.MetaRowBytes[i][j][k]; + + mode_lib->vba.MetaRowBytes[i][j][k]); if (mode_lib->vba.use_one_row_for_frame_flip[i][j][k]) { mode_lib->vba.TotImmediateFlipBytes = - mode_lib->vba.TotImmediateFlipBytes + 2 - * mode_lib->vba.DPTEBytesPerRow[i][j][k]; + (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + 2 + * mode_lib->vba.DPTEBytesPerRow[i][j][k]); } else { mode_lib->vba.TotImmediateFlipBytes = - mode_lib->vba.TotImmediateFlipBytes - + mode_lib->vba.DPTEBytesPerRow[i][j][k]; + (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + + mode_lib->vba.DPTEBytesPerRow[i][j][k]); } } } @@ -3480,7 +3481,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.HostVMEnable, mode_lib->vba.HostVMMaxNonCachedPageTableLevels, mode_lib->vba.GPUVMEnable, - mode_lib->vba.HostVMMinPageSize, + (unsigned int)mode_lib->vba.HostVMMinPageSize, mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k], mode_lib->vba.MetaRowBytes[i][j][k], mode_lib->vba.DPTEBytesPerRow[i][j][k], @@ -3722,9 +3723,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DETBufferSizeInKByte[k] = mode_lib->vba.DETBufferSizeInKByteAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; mode_lib->vba.DETBufferSizeY[k] = - mode_lib->vba.DETBufferSizeYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; + (unsigned int)mode_lib->vba.DETBufferSizeYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; mode_lib->vba.DETBufferSizeC[k] = - mode_lib->vba.DETBufferSizeCAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; + (unsigned int)mode_lib->vba.DETBufferSizeCAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; mode_lib->vba.OutputType[k] = mode_lib->vba.OutputTypePerState[mode_lib->vba.VoltageLevel][k]; mode_lib->vba.OutputRate[k] = mode_lib->vba.OutputRatePerState[mode_lib->vba.VoltageLevel][k]; } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c index 5e72966a8daf..8a2dbb4a2fbb 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c @@ -62,7 +62,7 @@ unsigned int dml32_dscceComputeDelay( pixelsPerClock = 1; //initial transmit delay as per PPS - initalXmitDelay = dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); + initalXmitDelay = (unsigned int)dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); //compute ssm delay if (bpc == 8) @@ -514,8 +514,8 @@ void dml32_CalculateSwathAndDETConfiguration( swath_width_chroma_ub); for (k = 0; k < NumberOfActiveSurfaces; ++k) { - RoundedUpMaxSwathSizeBytesY[k] = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k]; - RoundedUpMaxSwathSizeBytesC[k] = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k]; + RoundedUpMaxSwathSizeBytesY[k] = (unsigned int)(swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k]); + RoundedUpMaxSwathSizeBytesC[k] = (unsigned int)(swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k]); #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%0d DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]); dml_print("DML::%s: k=%0d swath_width_luma_ub = %d\n", __func__, k, swath_width_luma_ub[k]); @@ -531,8 +531,8 @@ void dml32_CalculateSwathAndDETConfiguration( #endif if (SourcePixelFormat[k] == dm_420_10) { - RoundedUpMaxSwathSizeBytesY[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesY[k], 256); - RoundedUpMaxSwathSizeBytesC[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesC[k], 256); + RoundedUpMaxSwathSizeBytesY[k] = (unsigned int)dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesY[k], 256); + RoundedUpMaxSwathSizeBytesC[k] = (unsigned int)dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesC[k], 256); } } @@ -656,7 +656,7 @@ void dml32_CalculateSwathAndDETConfiguration( #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%0d 2/3 DET for plane0, 1/3 for plane1\n", __func__, k); #endif - DETBufferSizeY[k] = dml_floor(DETBufferSizeInKByte[k] * 1024 * 2 / 3, 1024); + DETBufferSizeY[k] = (unsigned int)dml_floor(DETBufferSizeInKByte[k] * 1024 * 2 / 3, 1024); DETBufferSizeC[k] = DETBufferSizeInKByte[k] * 1024 - DETBufferSizeY[k]; } @@ -786,14 +786,14 @@ void dml32_CalculateSwathWidth( SwathWidthC[k] = SwathWidthdoubleDPPC[k]; } - surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); - surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); + surface_width_ub_l = (unsigned int)dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); + surface_height_ub_l = (unsigned int)dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); if (!IsVertical(SourceRotation[k])) { MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k]; MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k]; if (ViewportStationary[k] && DPPPerSurface[k] == 1) { - swath_width_luma_ub[k] = dml_min(surface_width_ub_l, + swath_width_luma_ub[k] = (unsigned int)dml_min(surface_width_ub_l, dml_floor(ViewportXStart[k] + SwathWidthY[k] + Read256BytesBlockWidthY[k] - 1, @@ -801,22 +801,22 @@ void dml32_CalculateSwathWidth( dml_floor(ViewportXStart[k], Read256BytesBlockWidthY[k])); } else { - swath_width_luma_ub[k] = dml_min(surface_width_ub_l, + swath_width_luma_ub[k] = (unsigned int)dml_min(surface_width_ub_l, dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]); } if (BytePerPixC[k] > 0) { - surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); + surface_width_ub_c = (unsigned int)dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); if (ViewportStationary[k] && DPPPerSurface[k] == 1) { - swath_width_chroma_ub[k] = dml_min(surface_width_ub_c, + swath_width_chroma_ub[k] = (unsigned int)dml_min(surface_width_ub_c, dml_floor(ViewportXStartC[k] + SwathWidthC[k] + Read256BytesBlockWidthC[k] - 1, Read256BytesBlockWidthC[k]) - dml_floor(ViewportXStartC[k], Read256BytesBlockWidthC[k])); } else { - swath_width_chroma_ub[k] = dml_min(surface_width_ub_c, + swath_width_chroma_ub[k] = (unsigned int)dml_min(surface_width_ub_c, dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]); @@ -829,25 +829,25 @@ void dml32_CalculateSwathWidth( MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k]; if (ViewportStationary[k] && DPPPerSurface[k] == 1) { - swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_floor(ViewportYStart[k] + + swath_width_luma_ub[k] = (unsigned int)dml_min(surface_height_ub_l, dml_floor(ViewportYStart[k] + SwathWidthY[k] + Read256BytesBlockHeightY[k] - 1, Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStart[k], Read256BytesBlockHeightY[k])); } else { - swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_ceil(SwathWidthY[k] - 1, + swath_width_luma_ub[k] = (unsigned int)dml_min(surface_height_ub_l, dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]); } if (BytePerPixC[k] > 0) { - surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); + surface_height_ub_c = (unsigned int)dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); if (ViewportStationary[k] && DPPPerSurface[k] == 1) { - swath_width_chroma_ub[k] = dml_min(surface_height_ub_c, + swath_width_chroma_ub[k] = (unsigned int)dml_min(surface_height_ub_c, dml_floor(ViewportYStartC[k] + SwathWidthC[k] + Read256BytesBlockHeightC[k] - 1, Read256BytesBlockHeightC[k]) - dml_floor(ViewportYStartC[k], Read256BytesBlockHeightC[k])); } else { - swath_width_chroma_ub[k] = dml_min(surface_height_ub_c, + swath_width_chroma_ub[k] = (unsigned int)dml_min(surface_height_ub_c, dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]); } @@ -956,7 +956,7 @@ void dml32_CalculateDETBufferSize( if (DETSizeOverride[0] > 0) { DETBufferSizeInKByte[0] = DETSizeOverride[0]; } else { - DETBufferSizeInKByte[0] = dml_max(nomDETInKByte, dml_ceil(2.0 * + DETBufferSizeInKByte[0] = (unsigned int)dml_max((unsigned int)nomDETInKByte, dml_ceil(2.0 * ((double) RoundedUpMaxSwathSizeBytesY[0] + (double) RoundedUpMaxSwathSizeBytesC[0]) / 1024.0, 64.0)); } @@ -993,7 +993,7 @@ void dml32_CalculateDETBufferSize( #endif if (minDET_pipe == 0) { - minDET_pipe = dml_max(128, dml_ceil(((double)RoundedUpMaxSwathSizeBytesY[k] + + minDET_pipe = (unsigned int)dml_max(128, dml_ceil(((double)RoundedUpMaxSwathSizeBytesY[k] + (double)RoundedUpMaxSwathSizeBytesC[k]) / 1024.0, 64)); #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%0d minDET_pipe = %d (assume each plane take half DET)\n", @@ -1106,7 +1106,7 @@ void dml32_CalculateDETBufferSize( //dml_print("DML::%s: j=%d, tmp1 = %f\n", __func__, j, tmp1); //dml_print("DML::%s: j=%d, tmp2 = %f\n", __func__, j, tmp2); - NextDETBufferPieceInKByte = dml_min( + NextDETBufferPieceInKByte = (unsigned int)dml_min( dml_round((double) DETBufferSizePoolInKByte * (ReadBandwidthLuma[NextSurfaceToAssignDETPiece] + ReadBandwidthChroma[NextSurfaceToAssignDETPiece]) / @@ -1379,7 +1379,7 @@ void dml32_CalculateOutputLink( *RequiresFEC = false; *OutBpp = dml32_TruncToValidBPP(dml_min(600, PHYCLKPerState) * 10, 3, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, false, Output, OutputFormat, - DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, &dummy); //OutputTypeAndRate = "HDMI"; *OutputType = dm_output_type_hdmi; @@ -1407,7 +1407,7 @@ void dml32_CalculateOutputLink( *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 10000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, - DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, + DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); if (*OutBpp == 0 && PHYCLKD32PerState < 13500.0 / 32 && DSCEnable == true && ForcedOutputLinkBPP == 0) { @@ -1417,7 +1417,7 @@ void dml32_CalculateOutputLink( OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, - NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); } //OutputTypeAndRate = Output & " UHBR10"; @@ -1429,7 +1429,7 @@ void dml32_CalculateOutputLink( *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, - DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, + DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); if (*OutBpp == 0 && PHYCLKD32PerState < 20000 / 32 && DSCEnable == true && @@ -1440,7 +1440,7 @@ void dml32_CalculateOutputLink( OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, - NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); } //OutputTypeAndRate = Output & " UHBR13p5"; @@ -1452,7 +1452,7 @@ void dml32_CalculateOutputLink( *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 20000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, - DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, + DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); if (*OutBpp == 0 && DSCEnable == true && ForcedOutputLinkBPP == 0) { *RequiresDSC = true; @@ -1461,7 +1461,7 @@ void dml32_CalculateOutputLink( OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, - NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); } //OutputTypeAndRate = Output & " UHBR20"; @@ -1475,7 +1475,7 @@ void dml32_CalculateOutputLink( *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 2700, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, - DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, + DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); if (*OutBpp == 0 && PHYCLKPerState < 540 && DSCEnable == true && ForcedOutputLinkBPP == 0) { @@ -1487,7 +1487,7 @@ void dml32_CalculateOutputLink( OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, - NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); } //OutputTypeAndRate = Output & " HBR"; @@ -1499,7 +1499,7 @@ void dml32_CalculateOutputLink( *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 5400, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, - DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, + DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); if (*OutBpp == 0 && PHYCLKPerState < 810 && DSCEnable == true && @@ -1513,7 +1513,7 @@ void dml32_CalculateOutputLink( OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, - NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); } //OutputTypeAndRate = Output & " HBR2"; @@ -1525,7 +1525,7 @@ void dml32_CalculateOutputLink( OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, - AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, + (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); if (*OutBpp == 0 && DSCEnable == true && ForcedOutputLinkBPP == 0) { @@ -1538,7 +1538,7 @@ void dml32_CalculateOutputLink( OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, - NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); } //OutputTypeAndRate = Output & " HBR3"; @@ -1654,7 +1654,7 @@ double dml32_TruncToValidBPP( MaxLinkBPP = 2 * MaxLinkBPP; } - *RequiredSlots = dml_ceil(DesiredBPP / MaxLinkBPP * 64, 1); + *RequiredSlots = (unsigned int)dml_ceil(DesiredBPP / MaxLinkBPP * 64, 1); if (DesiredBPP == 0) { if (DSCEnable) { @@ -1734,22 +1734,22 @@ unsigned int dml32_DSCDelayRequirement(bool DSCEnabled, if (DSCEnabled == true && OutputBpp != 0) { if (ODMMode == dm_odm_combine_mode_4to1) { DSCDelayRequirement_val = 4 * (dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, - dml_ceil(HActive / NumberOfDSCSlices, 1), NumberOfDSCSlices / 4, + (unsigned int)dml_ceil(HActive / NumberOfDSCSlices, 1), (unsigned int)(NumberOfDSCSlices / 4), OutputFormat, Output) + dml32_dscComputeDelay(OutputFormat, Output)); } else if (ODMMode == dm_odm_combine_mode_2to1) { DSCDelayRequirement_val = 2 * (dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, - dml_ceil(HActive / NumberOfDSCSlices, 1), NumberOfDSCSlices / 2, + (unsigned int)dml_ceil(HActive / NumberOfDSCSlices, 1), (unsigned int)(NumberOfDSCSlices / 2), OutputFormat, Output) + dml32_dscComputeDelay(OutputFormat, Output)); } else { DSCDelayRequirement_val = dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, - dml_ceil(HActive / NumberOfDSCSlices, 1), NumberOfDSCSlices, + (unsigned int)dml_ceil(HActive / NumberOfDSCSlices, 1), (unsigned int)NumberOfDSCSlices, OutputFormat, Output) + dml32_dscComputeDelay(OutputFormat, Output); } - DSCDelayRequirement_val = DSCDelayRequirement_val + (HTotal - HActive) * - dml_ceil((double)DSCDelayRequirement_val / HActive, 1); + DSCDelayRequirement_val = (unsigned int)(DSCDelayRequirement_val + (HTotal - HActive) * + dml_ceil((double)DSCDelayRequirement_val / HActive, 1)); - DSCDelayRequirement_val = DSCDelayRequirement_val * PixelClock / PixelClockBackEnd; + DSCDelayRequirement_val = (unsigned int)(DSCDelayRequirement_val * PixelClock / PixelClockBackEnd); } else { DSCDelayRequirement_val = 0; @@ -1765,7 +1765,7 @@ unsigned int dml32_DSCDelayRequirement(bool DSCEnabled, dml_print("DML::%s: DSCDelayRequirement_val = %d\n", __func__, DSCDelayRequirement_val); #endif - return dml_ceil(DSCDelayRequirement_val * dsc_delay_factor_wa, 1); + return (unsigned int)dml_ceil(DSCDelayRequirement_val * dsc_delay_factor_wa, 1); } void dml32_CalculateSurfaceSizeInMall( @@ -1811,16 +1811,16 @@ void dml32_CalculateSurfaceSizeInMall( for (k = 0; k < NumberOfActiveSurfaces; ++k) { if (ViewportStationary[k]) { - SurfaceSizeInMALL[k] = dml_min(dml_ceil(SurfaceWidthY[k], ReadBlockWidthY[k]), + SurfaceSizeInMALL[k] = (unsigned int)(dml_min(dml_ceil(SurfaceWidthY[k], ReadBlockWidthY[k]), dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + ReadBlockWidthY[k] - 1, ReadBlockWidthY[k]) - dml_floor(ViewportXStartY[k], ReadBlockWidthY[k])) * dml_min(dml_ceil(SurfaceHeightY[k], ReadBlockHeightY[k]), dml_floor(ViewportYStartY[k] + ViewportHeightY[k] + ReadBlockHeightY[k] - 1, ReadBlockHeightY[k]) - - dml_floor(ViewportYStartY[k], ReadBlockHeightY[k])) * BytesPerPixelY[k]; + dml_floor(ViewportYStartY[k], ReadBlockHeightY[k])) * BytesPerPixelY[k]); if (ReadBlockWidthC[k] > 0) { - SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] + dml_min(dml_ceil(SurfaceWidthC[k], ReadBlockWidthC[k]), dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + ReadBlockWidthC[k] - 1, ReadBlockWidthC[k]) - @@ -1829,10 +1829,10 @@ void dml32_CalculateSurfaceSizeInMall( dml_floor(ViewportYStartC[k] + ViewportHeightC[k] + ReadBlockHeightC[k] - 1, ReadBlockHeightC[k]) - dml_floor(ViewportYStartC[k], ReadBlockHeightC[k])) * - BytesPerPixelC[k]; + BytesPerPixelC[k]); } if (DCCEnable[k] == true) { - SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] + (dml_min(dml_ceil(DCCMetaPitchY[k], 8 * Read256BytesBlockWidthY[k]), dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + 8 * Read256BytesBlockWidthY[k] - 1, 8 * Read256BytesBlockWidthY[k]) @@ -1841,9 +1841,9 @@ void dml32_CalculateSurfaceSizeInMall( Read256BytesBlockHeightY[k]), dml_floor(ViewportYStartY[k] + ViewportHeightY[k] + 8 * Read256BytesBlockHeightY[k] - 1, 8 * Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStartY[k], 8 * - Read256BytesBlockHeightY[k])) * BytesPerPixelY[k] / 256) + (64 * 1024); + Read256BytesBlockHeightY[k])) *BytesPerPixelY[k] / 256) + (64 * 1024)); if (Read256BytesBlockWidthC[k] > 0) { - SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] + dml_min(dml_ceil(DCCMetaPitchC[k], 8 * Read256BytesBlockWidthC[k]), dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + 8 @@ -1858,41 +1858,41 @@ void dml32_CalculateSurfaceSizeInMall( Read256BytesBlockHeightC[k]) - dml_floor(ViewportYStartC[k], 8 * Read256BytesBlockHeightC[k])) * - BytesPerPixelC[k] / 256; + BytesPerPixelC[k] / 256); } } } else { - SurfaceSizeInMALL[k] = dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] + + SurfaceSizeInMALL[k] = (unsigned int)(dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] + ReadBlockWidthY[k] - 1), ReadBlockWidthY[k]) * dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + ReadBlockHeightY[k] - 1), ReadBlockHeightY[k]) * - BytesPerPixelY[k]; + BytesPerPixelY[k]); if (ReadBlockWidthC[k] > 0) { - SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] + dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] + ReadBlockWidthC[k] - 1), ReadBlockWidthC[k]) * dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + ReadBlockHeightC[k] - 1), ReadBlockHeightC[k]) * - BytesPerPixelC[k]; + BytesPerPixelC[k]); } if (DCCEnable[k] == true) { - SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] + (dml_ceil(dml_min(DCCMetaPitchY[k], ViewportWidthY[k] + 8 * Read256BytesBlockWidthY[k] - 1), 8 * Read256BytesBlockWidthY[k]) * dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + 8 * Read256BytesBlockHeightY[k] - 1), 8 * - Read256BytesBlockHeightY[k]) * BytesPerPixelY[k] / 256) + (64 * 1024); + Read256BytesBlockHeightY[k]) * BytesPerPixelY[k] / 256) + (64 * 1024)); if (Read256BytesBlockWidthC[k] > 0) { - SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] + dml_ceil(dml_min(DCCMetaPitchC[k], ViewportWidthC[k] + 8 * Read256BytesBlockWidthC[k] - 1), 8 * Read256BytesBlockWidthC[k]) * dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + 8 * Read256BytesBlockHeightC[k] - 1), 8 * Read256BytesBlockHeightC[k]) * - BytesPerPixelC[k] / 256; + BytesPerPixelC[k] / 256); } } } @@ -2321,51 +2321,51 @@ unsigned int dml32_CalculateVMAndRowBytes( if (HostVMMinPageSize < 2048) HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); else - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } *MetaRequestHeight = 8 * BlockHeight256Bytes; *MetaRequestWidth = 8 * BlockWidth256Bytes; if (SurfaceTiling == dm_sw_linear) { *meta_row_height = 32; - *meta_row_width = dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1, *MetaRequestWidth) - - dml_floor(ViewportXStart, *MetaRequestWidth); + *meta_row_width = (unsigned int)(dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1, *MetaRequestWidth) + - dml_floor(ViewportXStart, *MetaRequestWidth)); } else if (!IsVertical(SourceRotation)) { *meta_row_height = *MetaRequestHeight; if (ViewportStationary && NumberOfDPPs == 1) { - *meta_row_width = dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1, - *MetaRequestWidth) - dml_floor(ViewportXStart, *MetaRequestWidth); + *meta_row_width = (unsigned int)(dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1, + *MetaRequestWidth) - dml_floor(ViewportXStart, *MetaRequestWidth)); } else { - *meta_row_width = dml_ceil(SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth; + *meta_row_width = (unsigned int)(dml_ceil(SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth); } - *MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0; + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0); } else { *meta_row_height = *MetaRequestWidth; if (ViewportStationary && NumberOfDPPs == 1) { - *meta_row_width = dml_floor(ViewportYStart + ViewportHeight + *MetaRequestHeight - 1, - *MetaRequestHeight) - dml_floor(ViewportYStart, *MetaRequestHeight); + *meta_row_width = (unsigned int)(dml_floor(ViewportYStart + ViewportHeight + *MetaRequestHeight - 1, + *MetaRequestHeight) - dml_floor(ViewportYStart, *MetaRequestHeight)); } else { - *meta_row_width = dml_ceil(SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight; + *meta_row_width = (unsigned int)(dml_ceil(SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight); } - *MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0; + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0); } if (ViewportStationary && (NumberOfDPPs == 1 || !IsVertical(SourceRotation))) { - vp_height_meta_ub = dml_floor(ViewportYStart + ViewportHeight + 64 * BlockHeight256Bytes - 1, - 64 * BlockHeight256Bytes) - dml_floor(ViewportYStart, 64 * BlockHeight256Bytes); + vp_height_meta_ub = (unsigned int)(dml_floor(ViewportYStart + ViewportHeight + 64 * BlockHeight256Bytes - 1, + 64 * BlockHeight256Bytes) - dml_floor(ViewportYStart, 64 * BlockHeight256Bytes)); } else if (!IsVertical(SourceRotation)) { - vp_height_meta_ub = dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes; + vp_height_meta_ub = (unsigned int)(dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes); } else { - vp_height_meta_ub = dml_ceil(SwathWidth - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes; + vp_height_meta_ub = (unsigned int)(dml_ceil(SwathWidth - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes); } - DCCMetaSurfaceBytes = DCCMetaPitch * vp_height_meta_ub * BytePerPixel / 256.0; + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * vp_height_meta_ub * BytePerPixel / 256.0); if (GPUVMEnable == true) { - *MetaPTEBytesFrame = (dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / - (8 * 4.0 * 1024), 1) + 1) * 64; + *MetaPTEBytesFrame = (unsigned int)((dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / + (8 * 4.0 * 1024), 1) + 1) * 64); MPDEBytesFrame = 128 * (GPUVMMaxPageTableLevels - 1); } else { *MetaPTEBytesFrame = 0; @@ -2382,16 +2382,16 @@ unsigned int dml32_CalculateVMAndRowBytes( if (GPUVMEnable == true && GPUVMMaxPageTableLevels > 1) { if (ViewportStationary && (NumberOfDPPs == 1 || !IsVertical(SourceRotation))) { - vp_height_dpte_ub = dml_floor(ViewportYStart + ViewportHeight + + vp_height_dpte_ub = (unsigned int)(dml_floor(ViewportYStart + ViewportHeight + MacroTileHeight - 1, MacroTileHeight) - - dml_floor(ViewportYStart, MacroTileHeight); + dml_floor(ViewportYStart, MacroTileHeight)); } else if (!IsVertical(SourceRotation)) { - vp_height_dpte_ub = dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight; + vp_height_dpte_ub = (unsigned int)dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight; } else { - vp_height_dpte_ub = dml_ceil(SwathWidth - 1, MacroTileHeight) + MacroTileHeight; + vp_height_dpte_ub = (unsigned int)dml_ceil(SwathWidth - 1, MacroTileHeight) + MacroTileHeight; } - *DPDE0BytesFrame = 64 * (dml_ceil((Pitch * vp_height_dpte_ub * BytePerPixel - MacroTileSizeBytes) / - (8 * 2097152), 1) + 1); + *DPDE0BytesFrame = (unsigned int)(64 * (dml_ceil((Pitch * vp_height_dpte_ub * BytePerPixel - MacroTileSizeBytes) / + (8 * 2097152), 1) + 1)); ExtraDPDEBytesFrame = 128 * (GPUVMMaxPageTableLevels - 2); } else { *DPDE0BytesFrame = 0; @@ -2449,14 +2449,14 @@ unsigned int dml32_CalculateVMAndRowBytes( #endif *dpte_row_height_one_row_per_frame = vp_height_dpte_ub; - *dpte_row_width_ub_one_row_per_frame = (dml_ceil(((double)Pitch * (double)*dpte_row_height_one_row_per_frame / + *dpte_row_width_ub_one_row_per_frame = (unsigned int)((dml_ceil(((double)Pitch * (double)*dpte_row_height_one_row_per_frame / (double) *PixelPTEReqHeight - 1) / (double) *PixelPTEReqWidth, 1) + 1) * - (double) *PixelPTEReqWidth; + (double) *PixelPTEReqWidth); *PixelPTEBytesPerRow_one_row_per_frame = *dpte_row_width_ub_one_row_per_frame / *PixelPTEReqWidth * *PTERequestSize; if (SurfaceTiling == dm_sw_linear) { - *dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * + *dpte_row_height = (unsigned int)dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: dpte_row_height = %d (1)\n", __func__, @@ -2470,9 +2470,9 @@ unsigned int dml32_CalculateVMAndRowBytes( *PixelPTEReqWidth / Pitch), 1)); dml_print("DML::%s: dpte_row_height = %d\n", __func__, *dpte_row_height); #endif - *dpte_row_width_ub = dml_ceil(((double) Pitch * (double) *dpte_row_height - 1), + *dpte_row_width_ub = (unsigned int)dml_ceil(((double) Pitch * (double) *dpte_row_height - 1), (double) *PixelPTEReqWidth) + *PixelPTEReqWidth; - *PixelPTEBytesPerRow = *dpte_row_width_ub / (double)*PixelPTEReqWidth * (double)*PTERequestSize; + *PixelPTEBytesPerRow = (unsigned int)(*dpte_row_width_ub / (double)*PixelPTEReqWidth * (double)*PTERequestSize); // VBA_DELTA, VBA doesn't have programming value for pte row height linear. *dpte_row_height_linear = 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * @@ -2484,27 +2484,27 @@ unsigned int dml32_CalculateVMAndRowBytes( *dpte_row_height = *PixelPTEReqHeight; if (GPUVMMinPageSizeKBytes > 64) { - *dpte_row_width_ub = (dml_ceil((Pitch * *dpte_row_height / *PixelPTEReqHeight - 1) / - *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_width_ub = (unsigned int)((dml_ceil((Pitch * *dpte_row_height / *PixelPTEReqHeight - 1) / + *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); } else if (ViewportStationary && (NumberOfDPPs == 1)) { - *dpte_row_width_ub = dml_floor(ViewportXStart + SwathWidth + + *dpte_row_width_ub = (unsigned int)(dml_floor(ViewportXStart + SwathWidth + *PixelPTEReqWidth - 1, *PixelPTEReqWidth) - - dml_floor(ViewportXStart, *PixelPTEReqWidth); + dml_floor(ViewportXStart, *PixelPTEReqWidth)); } else { - *dpte_row_width_ub = (dml_ceil((SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * - *PixelPTEReqWidth; + *dpte_row_width_ub = (unsigned int)((dml_ceil((SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * + *PixelPTEReqWidth); } *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else { - *dpte_row_height = dml_min(*PixelPTEReqWidth, MacroTileWidth); + *dpte_row_height = (unsigned int)dml_min(*PixelPTEReqWidth, MacroTileWidth); if (ViewportStationary && (NumberOfDPPs == 1)) { - *dpte_row_width_ub = dml_floor(ViewportYStart + ViewportHeight + *PixelPTEReqHeight - 1, - *PixelPTEReqHeight) - dml_floor(ViewportYStart, *PixelPTEReqHeight); + *dpte_row_width_ub = (unsigned int)(dml_floor(ViewportYStart + ViewportHeight + *PixelPTEReqHeight - 1, + *PixelPTEReqHeight) - dml_floor(ViewportYStart, *PixelPTEReqHeight)); } else { - *dpte_row_width_ub = (dml_ceil((SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) - * *PixelPTEReqHeight; + *dpte_row_width_ub = (unsigned int)((dml_ceil((SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) + * *PixelPTEReqHeight); } *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize; @@ -2584,16 +2584,16 @@ double dml32_CalculatePrefetchSourceLines( } sw0_tmp = SwathHeight - (vp_start_rot % SwathHeight); if (sw0_tmp < *VInitPreFill) - *MaxNumSwath = dml_ceil((*VInitPreFill - sw0_tmp) / SwathHeight, 1) + 1; + *MaxNumSwath = (unsigned int)dml_ceil((*VInitPreFill - sw0_tmp) / SwathHeight, 1) + 1; else *MaxNumSwath = 1; - MaxPartialSwath = dml_max(1, (unsigned int) (vp_start_rot + *VInitPreFill - 1) % SwathHeight); + MaxPartialSwath = (unsigned int)dml_max(1, (unsigned int) (vp_start_rot + *VInitPreFill - 1) % SwathHeight); } else { - *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1; + *MaxNumSwath = (unsigned int)dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1; if (*VInitPreFill > 1) - MaxPartialSwath = dml_max(1, (unsigned int) (*VInitPreFill - 2) % SwathHeight); + MaxPartialSwath = (unsigned int)dml_max(1, (unsigned int) (*VInitPreFill - 2) % SwathHeight); else - MaxPartialSwath = dml_max(1, (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight); + MaxPartialSwath = (unsigned int)dml_max(1, (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight); } numLines = *MaxNumSwath * SwathHeight + MaxPartialSwath; @@ -3180,9 +3180,9 @@ unsigned int dml32_CalculateExtraLatencyBytes(unsigned int ReorderingBytes, if (HostVMMinPageSize < 2048) HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); else - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } else { HostVMDynamicLevels = 0; } @@ -3196,7 +3196,7 @@ unsigned int dml32_CalculateExtraLatencyBytes(unsigned int ReorderingBytes, (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor; } } - return ret; + return (unsigned int)ret; } void dml32_CalculateVUpdateAndDynamicMetadataParameters( @@ -3228,7 +3228,7 @@ void dml32_CalculateVUpdateAndDynamicMetadataParameters( dml_ceil((14.0 / DCFClkDeepSleep + 12.0 / Dppclk + TotalRepeaterDelayTime) * PixelClock, 1.0); *VReadyOffsetPix = dml_ceil(dml_max(150.0 / Dppclk, TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / Dppclk) * PixelClock, 1.0); - *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1.0); + *VUpdateOffsetPix = (unsigned int)dml_ceil(HTotal / 4.0, 1.0); *TSetup = (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock; *Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / Dispclk; *Tdmec = HTotal / PixelClock; @@ -3491,7 +3491,7 @@ bool dml32_CalculatePrefetchSchedule( double prefetch_sw_bytes; double bytes_pp; double dep_bytes; - unsigned int max_vratio_pre = v->MaxVRatioPre; + unsigned int max_vratio_pre = (unsigned int)v->MaxVRatioPre; double min_Lsw; double Tsw_est1 = 0; double Tsw_est3 = 0; @@ -3567,13 +3567,13 @@ bool dml32_CalculatePrefetchSchedule( v->GPUVMEnable == true ? TWait + Tvm_trips : 0); if (myPipe->ScalerEnabled) - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCL; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCL); else - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCLLBOnly; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCLLBOnly); - DPPCycles = DPPCycles + myPipe->NumberOfCursors * v->DPPCLKDelayCNVCCursor; + DPPCycles = (unsigned int)(DPPCycles + myPipe->NumberOfCursors * v->DPPCLKDelayCNVCCursor); - DISPCLKCycles = v->DISPCLKDelaySubtotal; + DISPCLKCycles = (unsigned int)v->DISPCLKDelaySubtotal; if (myPipe->Dppclk == 0.0 || myPipe->Dispclk == 0.0) return true; @@ -4416,8 +4416,8 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( for (k = 0; k < v->NumberOfActiveSurfaces; ++k) { - LBLatencyHidingSourceLinesY[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1); - LBLatencyHidingSourceLinesC[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1); + LBLatencyHidingSourceLinesY[k] = (unsigned int)(dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1)); + LBLatencyHidingSourceLinesC[k] = (unsigned int)(dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1)); #ifdef __DML_VBA_DEBUG__ @@ -4440,7 +4440,7 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( } LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; - LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); + LinesInDETYRoundedDownToSwath[k] = (unsigned int)dml_floor(LinesInDETY[k], SwathHeightY[k]); FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k]; ActiveClockChangeLatencyHidingY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY @@ -4454,7 +4454,7 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( if (BytePerPixelDETC[k] > 0) { LinesInDETC[k] = DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k]; - LinesInDETCRoundedDownToSwath[k] = dml_floor(LinesInDETC[k], SwathHeightC[k]); + LinesInDETCRoundedDownToSwath[k] = (unsigned int)dml_floor(LinesInDETC[k], SwathHeightC[k]); FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k]; ActiveClockChangeLatencyHidingC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC @@ -4614,9 +4614,9 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( unsigned int src_y_pstate_c; unsigned int src_y_ahead_l, src_y_ahead_c, sub_vp_lines_l, sub_vp_lines_c; - dst_y_pstate = dml_ceil((mmSOCParameters.DRAMClockChangeLatency + mmSOCParameters.UrgentLatency) / (v->HTotal[k] / v->PixelClock[k]), 1); - src_y_pstate_l = dml_ceil(dst_y_pstate * v->VRatio[k], SwathHeightY[k]); - src_y_ahead_l = dml_floor(DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k], SwathHeightY[k]) + LBLatencyHidingSourceLinesY[k]; + dst_y_pstate = (unsigned int)dml_ceil((mmSOCParameters.DRAMClockChangeLatency + mmSOCParameters.UrgentLatency) / (v->HTotal[k] / v->PixelClock[k]), 1); + src_y_pstate_l = (unsigned int)dml_ceil(dst_y_pstate * v->VRatio[k], SwathHeightY[k]); + src_y_ahead_l = (unsigned int)(dml_floor(DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k], SwathHeightY[k]) + LBLatencyHidingSourceLinesY[k]); sub_vp_lines_l = src_y_pstate_l + src_y_ahead_l + v->meta_row_height[k]; #ifdef __DML_VBA_DEBUG__ @@ -4634,10 +4634,10 @@ dml_print("DML::%s: k=%d, sub_vp_lines_l = %d\n", __func__, k, sub_vp_lines_l SubViewportLinesNeededInMALL[k] = sub_vp_lines_l; if (BytePerPixelDETC[k] > 0) { - src_y_pstate_c = dml_ceil(dst_y_pstate * v->VRatioChroma[k], SwathHeightC[k]); - src_y_ahead_c = dml_floor(DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k], SwathHeightC[k]) + LBLatencyHidingSourceLinesC[k]; + src_y_pstate_c = (unsigned int)dml_ceil(dst_y_pstate * v->VRatioChroma[k], SwathHeightC[k]); + src_y_ahead_c = (unsigned int)(dml_floor(DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k], SwathHeightC[k]) + LBLatencyHidingSourceLinesC[k]); sub_vp_lines_c = src_y_pstate_c + src_y_ahead_c + v->meta_row_height_chroma[k]; - SubViewportLinesNeededInMALL[k] = dml_max(sub_vp_lines_l, sub_vp_lines_c); + SubViewportLinesNeededInMALL[k] = (unsigned int)dml_max(sub_vp_lines_l, sub_vp_lines_c); #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%d, src_y_pstate_c = %d\n", __func__, k, src_y_pstate_c); @@ -4852,7 +4852,7 @@ void dml32_CalculatePixelDeliveryTimes( for (k = 0; k < NumberOfActiveSurfaces; ++k) { unsigned int cursor_req_per_width; - cursor_req_per_width = dml_ceil((double) CursorWidth[k][0] * (double) CursorBPP[k][0] / + cursor_req_per_width = (unsigned int)dml_ceil((double) CursorWidth[k][0] * (double) CursorBPP[k][0] / 256.0 / 8.0, 1.0); if (NumberOfCursors[k] > 0) { if (VRatio[k] <= 1) { @@ -5000,8 +5000,8 @@ void dml32_CalculateMetaAndPTETimes( meta_row_height_chroma[k]; min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; - meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / - meta_chunk_width_chroma; + meta_chunk_per_row_int_chroma = (unsigned int)((double) meta_row_width_chroma[k] / + meta_chunk_width_chroma); meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma; if (!IsVertical(SourceRotation[k])) { meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - @@ -5035,18 +5035,18 @@ void dml32_CalculateMetaAndPTETimes( for (k = 0; k < NumberOfActiveSurfaces; ++k) { if (GPUVMEnable == true) { if (!IsVertical(SourceRotation[k])) { - dpte_group_width_luma = (double) dpte_group_bytes[k] / - (double) PTERequestSizeY[k] * PixelPTEReqWidthY[k]; + dpte_group_width_luma = (unsigned int)((double) dpte_group_bytes[k] / + (double) PTERequestSizeY[k] * PixelPTEReqWidthY[k]); } else { - dpte_group_width_luma = (double) dpte_group_bytes[k] / - (double) PTERequestSizeY[k] * PixelPTEReqHeightY[k]; + dpte_group_width_luma = (unsigned int)((double) dpte_group_bytes[k] / + (double) PTERequestSizeY[k] * PixelPTEReqHeightY[k]); } if (use_one_row_for_frame[k]) { - dpte_groups_per_row_luma_ub = dml_ceil((double) dpte_row_width_luma_ub[k] / + dpte_groups_per_row_luma_ub = (unsigned int)dml_ceil((double) dpte_row_width_luma_ub[k] / (double) dpte_group_width_luma / 2.0, 1.0); } else { - dpte_groups_per_row_luma_ub = dml_ceil((double) dpte_row_width_luma_ub[k] / + dpte_groups_per_row_luma_ub = (unsigned int)dml_ceil((double) dpte_row_width_luma_ub[k] / (double) dpte_group_width_luma, 1.0); } #ifdef __DML_VBA_DEBUG__ @@ -5080,18 +5080,18 @@ void dml32_CalculateMetaAndPTETimes( time_per_pte_group_flip_chroma[k] = 0; } else { if (!IsVertical(SourceRotation[k])) { - dpte_group_width_chroma = (double) dpte_group_bytes[k] / - (double) PTERequestSizeC[k] * PixelPTEReqWidthC[k]; + dpte_group_width_chroma = (unsigned int)((double) dpte_group_bytes[k] / + (double) PTERequestSizeC[k] * PixelPTEReqWidthC[k]); } else { - dpte_group_width_chroma = (double) dpte_group_bytes[k] / - (double) PTERequestSizeC[k] * PixelPTEReqHeightC[k]; + dpte_group_width_chroma = (unsigned int)((double) dpte_group_bytes[k] / + (double) PTERequestSizeC[k] * PixelPTEReqHeightC[k]); } if (use_one_row_for_frame[k]) { - dpte_groups_per_row_chroma_ub = dml_ceil((double) dpte_row_width_chroma_ub[k] / + dpte_groups_per_row_chroma_ub = (unsigned int)dml_ceil((double) dpte_row_width_chroma_ub[k] / (double) dpte_group_width_chroma / 2.0, 1.0); } else { - dpte_groups_per_row_chroma_ub = dml_ceil((double) dpte_row_width_chroma_ub[k] / + dpte_groups_per_row_chroma_ub = (unsigned int)dml_ceil((double) dpte_row_width_chroma_ub[k] / (double) dpte_group_width_chroma, 1.0); } #ifdef __DML_VBA_DEBUG__ @@ -5210,32 +5210,32 @@ void dml32_CalculateVMGroupAndRequestTimes( if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) { if (DCCEnable[k] == false) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil( + num_group_per_lower_vm_stage = (unsigned int)(dml_ceil( (double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1.0) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / - (double) (vm_group_bytes[k]), 1.0); + (double) (vm_group_bytes[k]), 1.0)); } else { - num_group_per_lower_vm_stage = dml_ceil( + num_group_per_lower_vm_stage = (unsigned int)dml_ceil( (double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1.0); } } else { if (GPUVMMaxPageTableLevels == 1) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil( + num_group_per_lower_vm_stage = (unsigned int)(dml_ceil( (double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1.0) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / - (double) (vm_group_bytes[k]), 1.0); + (double) (vm_group_bytes[k]), 1.0)); } else { - num_group_per_lower_vm_stage = dml_ceil( + num_group_per_lower_vm_stage = (unsigned int)dml_ceil( (double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1.0); } } else { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = 2 + dml_ceil( + num_group_per_lower_vm_stage = (unsigned int)(2 + dml_ceil( (double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / @@ -5243,13 +5243,13 @@ void dml32_CalculateVMGroupAndRequestTimes( dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / - (double) (vm_group_bytes[k]), 1); + (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = 1 + dml_ceil( + num_group_per_lower_vm_stage = (unsigned int)(1 + dml_ceil( (double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil( (double) (meta_pte_bytes_per_frame_ub_l[k]) / - (double) (vm_group_bytes[k]), 1); + (double) (vm_group_bytes[k]), 1)); } } } @@ -5424,8 +5424,8 @@ void dml32_CalculateDCCConfiguration( MAS_vp_horz_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : 6144; MAS_vp_vert_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : (BytePerPixelY == 8 ? 3072 : 6144); - max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); - max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); + max_vp_horz_width = (unsigned int)dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); + max_vp_vert_height = (unsigned int)dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); eff_surf_width_l = (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma); eff_surf_width_c = eff_surf_width_l / (1 + yuv420); eff_surf_height_l = (SurfaceHeightLuma > max_vp_vert_height ? max_vp_vert_height : SurfaceHeightLuma); @@ -5442,10 +5442,10 @@ void dml32_CalculateDCCConfiguration( } if (SourcePixelFormat == dm_420_10) { - full_swath_bytes_horz_wc_l = dml_ceil((double) full_swath_bytes_horz_wc_l * 2.0 / 3.0, 256.0); - full_swath_bytes_horz_wc_c = dml_ceil((double) full_swath_bytes_horz_wc_c * 2.0 / 3.0, 256.0); - full_swath_bytes_vert_wc_l = dml_ceil((double) full_swath_bytes_vert_wc_l * 2.0 / 3.0, 256.0); - full_swath_bytes_vert_wc_c = dml_ceil((double) full_swath_bytes_vert_wc_c * 2.0 / 3.0, 256.0); + full_swath_bytes_horz_wc_l = (unsigned int)dml_ceil((double) full_swath_bytes_horz_wc_l * 2.0 / 3.0, 256.0); + full_swath_bytes_horz_wc_c = (unsigned int)dml_ceil((double) full_swath_bytes_horz_wc_c * 2.0 / 3.0, 256.0); + full_swath_bytes_vert_wc_l = (unsigned int)dml_ceil((double) full_swath_bytes_vert_wc_l * 2.0 / 3.0, 256.0); + full_swath_bytes_vert_wc_c = (unsigned int)dml_ceil((double) full_swath_bytes_vert_wc_c * 2.0 / 3.0, 256.0); } if (2 * full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSizeForDCC) { @@ -5994,10 +5994,10 @@ void dml32_CalculateStutterEfficiency( 1 - (SRExitTime + StutterBurstTime) / *StutterPeriod) * 100; *Z8StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitZ8Time + StutterBurstTime) / *StutterPeriod) * 100; - *NumberOfStutterBurstsPerFrame = ( + *NumberOfStutterBurstsPerFrame = (unsigned int)( *StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalSurface / *StutterPeriod, 1) : 0); - *Z8NumberOfStutterBurstsPerFrame = ( + *Z8NumberOfStutterBurstsPerFrame = (unsigned int)( *Z8StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalSurface / *StutterPeriod, 1) : 0); } else { @@ -6073,11 +6073,11 @@ void dml32_CalculateStutterEfficiency( dml_print("DML::%s: Z8NumberOfStutterBurstsPerFrame = %d\n", __func__, *Z8NumberOfStutterBurstsPerFrame); #endif - SwathSizeCriticalSurface = BytePerPixelYCriticalSurface * SwathHeightYCriticalSurface - * dml_ceil(SwathWidthYCriticalSurface, BlockWidth256BytesYCriticalSurface); + SwathSizeCriticalSurface = (unsigned int)(BytePerPixelYCriticalSurface * SwathHeightYCriticalSurface + * dml_ceil(SwathWidthYCriticalSurface, BlockWidth256BytesYCriticalSurface)); LastChunkOfSwathSize = SwathSizeCriticalSurface % (PixelChunkSizeInKByte * 1024); - MissingPartOfLastSwathOfDETSize = dml_ceil(DETBufferSizeYCriticalSurface, SwathSizeCriticalSurface) - - DETBufferSizeYCriticalSurface; + MissingPartOfLastSwathOfDETSize = (unsigned int)(dml_ceil(DETBufferSizeYCriticalSurface, SwathSizeCriticalSurface) + - DETBufferSizeYCriticalSurface); *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE = !(!UnboundedRequestEnabled && (NumberOfActiveSurfaces == 1) && doublePlaneCriticalSurface && doublePipeCriticalSurface && (LastChunkOfSwathSize > 0) @@ -6107,9 +6107,9 @@ void dml32_CalculateMaxDETAndMinCompressedBufferSize( bool det_buff_size_override_en = nomDETInKByteOverrideEnable; unsigned int det_buff_size_override_val = nomDETInKByteOverrideValue; - *MaxTotalDETInKByte = dml_ceil(((double)ConfigReturnBufferSizeInKByte + + *MaxTotalDETInKByte = (unsigned int)dml_ceil(((double)ConfigReturnBufferSizeInKByte + (double) ROBBufferSizeInKByte) * 4.0 / 5.0, 64); - *nomDETInKByte = dml_floor((double) *MaxTotalDETInKByte / (double) MaxNumDPP, 64); + *nomDETInKByte = (unsigned int)dml_floor((double) *MaxTotalDETInKByte / (double) MaxNumDPP, 64); *MinCompressedBufferSizeInKByte = ConfigReturnBufferSizeInKByte - *MaxTotalDETInKByte; #ifdef __DML_VBA_DEBUG__ @@ -6318,7 +6318,7 @@ bool dml32_CalculateDETSwathFillLatencyHiding(unsigned int NumberOfActiveSurface enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[], enum unbounded_requesting_policy UseUnboundedRequesting) { - int k; + unsigned int k; double SwathSizeAllSurfaces = 0; double SwathSizeAllSurfacesInFetchTimeUs; double DETSwathLatencyHidingUs; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c index 6c75aa82327a..bde043373d5d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c @@ -73,17 +73,17 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, dml_print("DML_DLG::%s: Calculation for pipe[%d] start, num_pipes=%d\n", __func__, pipe_idx, num_pipes); - pixel_chunk_bytes = get_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // From VBA - min_pixel_chunk_bytes = get_min_pixel_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA + pixel_chunk_bytes = (uint32_t)(get_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024); // From VBA + min_pixel_chunk_bytes = (uint32_t)get_min_pixel_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA if (pixel_chunk_bytes == 64 * 1024) min_pixel_chunk_bytes = 0; - meta_chunk_bytes = get_meta_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // From VBA - min_meta_chunk_bytes = get_min_meta_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA + meta_chunk_bytes = (uint32_t)(get_meta_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024); // From VBA + min_meta_chunk_bytes = (uint32_t)get_min_meta_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA - dpte_group_bytes = get_dpte_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA - mpte_group_bytes = get_vm_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dpte_group_bytes = (uint32_t)get_dpte_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + mpte_group_bytes = (uint32_t)get_vm_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA p1_pixel_chunk_bytes = pixel_chunk_bytes; p1_min_pixel_chunk_bytes = min_pixel_chunk_bytes; @@ -93,10 +93,10 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, p1_mpte_group_bytes = mpte_group_bytes; if ((enum source_format_class) src->source_format == dm_rgbe_alpha) - p1_pixel_chunk_bytes = get_alpha_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; + p1_pixel_chunk_bytes = (uint32_t)(get_alpha_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024); - rq_regs->rq_regs_l.chunk_size = dml_log2(pixel_chunk_bytes) - 10; - rq_regs->rq_regs_c.chunk_size = dml_log2(p1_pixel_chunk_bytes) - 10; + rq_regs->rq_regs_l.chunk_size = (uint32_t)(dml_log2(pixel_chunk_bytes) - 10); + rq_regs->rq_regs_c.chunk_size = (uint32_t)(dml_log2(p1_pixel_chunk_bytes) - 10); if (min_pixel_chunk_bytes == 0) rq_regs->rq_regs_l.min_chunk_size = 0; @@ -108,8 +108,8 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, else rq_regs->rq_regs_c.min_chunk_size = dml_log2(p1_min_pixel_chunk_bytes) - 8 + 1; - rq_regs->rq_regs_l.meta_chunk_size = dml_log2(meta_chunk_bytes) - 10; - rq_regs->rq_regs_c.meta_chunk_size = dml_log2(p1_meta_chunk_bytes) - 10; + rq_regs->rq_regs_l.meta_chunk_size = (uint32_t)(dml_log2(meta_chunk_bytes) - 10); + rq_regs->rq_regs_c.meta_chunk_size = (uint32_t)(dml_log2(p1_meta_chunk_bytes) - 10); if (min_meta_chunk_bytes == 0) rq_regs->rq_regs_l.min_meta_chunk_size = 0; @@ -121,32 +121,32 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, else rq_regs->rq_regs_c.min_meta_chunk_size = dml_log2(p1_min_meta_chunk_bytes) - 6 + 1; - rq_regs->rq_regs_l.dpte_group_size = dml_log2(dpte_group_bytes) - 6; + rq_regs->rq_regs_l.dpte_group_size = (uint32_t)(dml_log2(dpte_group_bytes) - 6); rq_regs->rq_regs_l.mpte_group_size = dml_log2(mpte_group_bytes) - 6; rq_regs->rq_regs_c.dpte_group_size = dml_log2(p1_dpte_group_bytes) - 6; rq_regs->rq_regs_c.mpte_group_size = dml_log2(p1_mpte_group_bytes) - 6; - detile_buf_size_in_bytes = get_det_buffer_size_kbytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * 1024; + detile_buf_size_in_bytes = (unsigned int)(get_det_buffer_size_kbytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * 1024); detile_buf_plane1_addr = 0; - pte_row_height_linear = get_dpte_row_height_linear_l(mode_lib, e2e_pipe_param, num_pipes, + pte_row_height_linear = (unsigned int)get_dpte_row_height_linear_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); if (src->sw_mode == dm_sw_linear) ASSERT(pte_row_height_linear >= 8); - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(pte_row_height_linear), 1) - 3; + rq_regs->rq_regs_l.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(pte_row_height_linear), 1) - 3); if (dual_plane) { - unsigned int p1_pte_row_height_linear = get_dpte_row_height_linear_c(mode_lib, e2e_pipe_param, + unsigned int p1_pte_row_height_linear = (unsigned int)get_dpte_row_height_linear_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); if (src->sw_mode == dm_sw_linear) ASSERT(p1_pte_row_height_linear >= 8); - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(p1_pte_row_height_linear), 1) - 3; + rq_regs->rq_regs_c.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(p1_pte_row_height_linear), 1) - 3); } - rq_regs->rq_regs_l.swath_height = dml_log2(get_swath_height_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); - rq_regs->rq_regs_c.swath_height = dml_log2(get_swath_height_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); + rq_regs->rq_regs_l.swath_height = (unsigned int)dml_log2(get_swath_height_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); + rq_regs->rq_regs_c.swath_height = (unsigned int)dml_log2(get_swath_height_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); // FIXME: take the max between luma, chroma chunk size? // okay for now, as we are setting pixel_chunk_bytes to 8kb anyways @@ -168,19 +168,19 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, // Note: detile_buf_plane1_addr is in unit of 1KB if (dual_plane) { if (is_phantom_pipe) { - detile_buf_plane1_addr = ((1024.0 * 1024.0) / 2.0 / 1024.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)((1024.0 * 1024.0) / 2.0 / 1024.0); // half to chroma } else { if (stored_swath_l_bytes / stored_swath_c_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/2 to chroma)\n", __func__, detile_buf_plane1_addr); #endif } else { - detile_buf_plane1_addr = + detile_buf_plane1_addr = (unsigned int)( dml_round_to_multiple( (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), - 1024, 0) / 1024.0; // 2/3 to luma + 1024, 0) / 1024.0); // 2/3 to luma #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/3 chroma)\n", __func__, detile_buf_plane1_addr); @@ -276,7 +276,7 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA - min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + min_dst_y_next_start = (unsigned int)get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank); dml_print("DML_DLG: %s: min_dst_y_next_start = %d\n", __func__, min_dst_y_next_start); @@ -284,14 +284,14 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, dual_plane = is_dual_plane((enum source_format_class) (src->source_format)); - vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, + vready_after_vcount0 = (unsigned int)get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA dlg_regs->vready_after_vcount0 = vready_after_vcount0; dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, dlg_regs->vready_after_vcount0); - dst_x_after_scaler = dml_ceil(get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx), 1); - dst_y_after_scaler = dml_ceil(get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx), 1); + dst_x_after_scaler = (unsigned int)dml_ceil(get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx), 1); + dst_y_after_scaler = (unsigned int)dml_ceil(get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx), 1); // do some adjustment on the dst_after scaler to account for odm combine mode dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n", __func__, dst_x_after_scaler); @@ -398,15 +398,15 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, } if (src->dynamic_metadata_enable && src->gpuvm) - dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, - pipe_idx) * refclk_freq_in_mhz; // From VBA + dlg_regs->refcyc_per_vm_dmdata = (unsigned int)(get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz); // From VBA - dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) - * refclk_freq_in_mhz; // From VBA + dlg_regs->dmdata_dl_delta = (unsigned int)(get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) + * refclk_freq_in_mhz); // From VBA - refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, - pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_req_delivery_pre_l = (unsigned int)(get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + refcyc_per_req_delivery_l = (unsigned int)(get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz); // From VBA dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, refcyc_per_req_delivery_pre_l); dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", __func__, refcyc_per_req_delivery_l); @@ -437,11 +437,11 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, } // Assign to register structures - dlg_regs->min_dst_y_next_start = min_dst_y_next_start * dml_pow(2, 2); + dlg_regs->min_dst_y_next_start = (unsigned int)(min_dst_y_next_start * dml_pow(2, 2)); ASSERT(dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line - dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); // in terms of refclk dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); @@ -456,14 +456,14 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, dml_print("DML_DLG: %s: dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, dlg_regs->dst_y_per_vm_flip); dml_print("DML_DLG: %s: dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, dlg_regs->dst_y_per_row_flip); - dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, - num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, - pipe_idx) * refclk_freq_in_mhz; // From VBA - dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, - pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA - dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, - pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA + dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, + num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz); // From VBA + dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA + dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA // From VBA dst_y_per_pte_row_nom_l = get_dst_y_per_pte_row_nom_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); @@ -500,22 +500,22 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, refcyc_per_meta_chunk_flip_c = get_refcyc_per_meta_chunk_flip_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - dlg_regs->dst_y_per_pte_row_nom_l = dst_y_per_pte_row_nom_l * dml_pow(2, 2); - dlg_regs->dst_y_per_pte_row_nom_c = dst_y_per_pte_row_nom_c * dml_pow(2, 2); - dlg_regs->dst_y_per_meta_row_nom_l = dst_y_per_meta_row_nom_l * dml_pow(2, 2); - dlg_regs->dst_y_per_meta_row_nom_c = dst_y_per_meta_row_nom_c * dml_pow(2, 2); - dlg_regs->refcyc_per_pte_group_nom_l = refcyc_per_pte_group_nom_l; - dlg_regs->refcyc_per_pte_group_nom_c = refcyc_per_pte_group_nom_c; - dlg_regs->refcyc_per_pte_group_vblank_l = refcyc_per_pte_group_vblank_l; - dlg_regs->refcyc_per_pte_group_vblank_c = refcyc_per_pte_group_vblank_c; - dlg_regs->refcyc_per_pte_group_flip_l = refcyc_per_pte_group_flip_l; - dlg_regs->refcyc_per_pte_group_flip_c = refcyc_per_pte_group_flip_c; - dlg_regs->refcyc_per_meta_chunk_nom_l = refcyc_per_meta_chunk_nom_l; - dlg_regs->refcyc_per_meta_chunk_nom_c = refcyc_per_meta_chunk_nom_c; - dlg_regs->refcyc_per_meta_chunk_vblank_l = refcyc_per_meta_chunk_vblank_l; - dlg_regs->refcyc_per_meta_chunk_vblank_c = refcyc_per_meta_chunk_vblank_c; - dlg_regs->refcyc_per_meta_chunk_flip_l = refcyc_per_meta_chunk_flip_l; - dlg_regs->refcyc_per_meta_chunk_flip_c = refcyc_per_meta_chunk_flip_c; + dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int)(dst_y_per_pte_row_nom_l * dml_pow(2, 2)); + dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int)(dst_y_per_pte_row_nom_c * dml_pow(2, 2)); + dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int)(dst_y_per_meta_row_nom_l * dml_pow(2, 2)); + dlg_regs->dst_y_per_meta_row_nom_c = (unsigned int)(dst_y_per_meta_row_nom_c * dml_pow(2, 2)); + dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)refcyc_per_pte_group_nom_l; + dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)refcyc_per_pte_group_nom_c; + dlg_regs->refcyc_per_pte_group_vblank_l = (unsigned int)refcyc_per_pte_group_vblank_l; + dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int)refcyc_per_pte_group_vblank_c; + dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int)refcyc_per_pte_group_flip_l; + dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int)refcyc_per_pte_group_flip_c; + dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)refcyc_per_meta_chunk_nom_l; + dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)refcyc_per_meta_chunk_nom_c; + dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int)refcyc_per_meta_chunk_vblank_l; + dlg_regs->refcyc_per_meta_chunk_vblank_c = (unsigned int)refcyc_per_meta_chunk_vblank_c; + dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int)refcyc_per_meta_chunk_flip_l; + dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int)refcyc_per_meta_chunk_flip_c; dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1); dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1); dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1); @@ -548,7 +548,7 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, ttu_regs->qos_ramp_disable_l = 0; ttu_regs->qos_ramp_disable_c = 0; ttu_regs->qos_ramp_disable_cur0 = 0; - ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); // CHECK for HW registers' range, assert or clamp ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); @@ -556,16 +556,16 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); if (dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(dml_pow(2, 23) - 1); if (dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(dml_pow(2, 23) - 1); ASSERT(dlg_regs->dst_y_after_scaler < (unsigned int) 8); ASSERT(dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); @@ -581,10 +581,10 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, ASSERT(dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17)); if (dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (dual_plane) { if (dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1); } ASSERT(dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13)); if (dual_plane) { @@ -592,10 +592,10 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, } if (dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (dual_plane) { if (dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1); } ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_c < (unsigned int)dml_pow(2, 13)); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c index e0a1dc89ce43..f4d826e0d13a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c @@ -162,20 +162,20 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = { static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry) { if (entry->dcfclk_mhz > 0) { - float bw_on_sdp = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100); + float bw_on_sdp = (float)(entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); entry->fabricclk_mhz = bw_on_sdp / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); entry->dram_speed_mts = bw_on_sdp / (dcn3_21_soc.num_chans * dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); } else if (entry->fabricclk_mhz > 0) { - float bw_on_fabric = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100); + float bw_on_fabric = (float)(entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); entry->dcfclk_mhz = bw_on_fabric / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); entry->dram_speed_mts = bw_on_fabric / (dcn3_21_soc.num_chans * dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); } else if (entry->dram_speed_mts > 0) { - float bw_on_dram = entry->dram_speed_mts * dcn3_21_soc.num_chans * - dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); + float bw_on_dram = (float)(entry->dram_speed_mts * dcn3_21_soc.num_chans * + dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); entry->fabricclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); entry->dcfclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); @@ -189,12 +189,12 @@ static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st * float sdp_bw_kbytes_sec; float limiting_bw_kbytes_sec; - memory_bw_kbytes_sec = entry->dram_speed_mts * dcn3_21_soc.num_chans * - dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); + memory_bw_kbytes_sec = (float)(entry->dram_speed_mts * dcn3_21_soc.num_chans * + dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); - fabric_bw_kbytes_sec = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100); + fabric_bw_kbytes_sec = (float)(entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); - sdp_bw_kbytes_sec = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100); + sdp_bw_kbytes_sec = (float)(entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); limiting_bw_kbytes_sec = memory_bw_kbytes_sec; @@ -211,8 +211,8 @@ static void dcn321_insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scalin unsigned int *num_entries, struct _vcs_dpi_voltage_scaling_st *entry) { - int i = 0; - int index = 0; + unsigned int i = 0; + unsigned int index = 0; dc_assert_fp_enabled(); @@ -237,7 +237,7 @@ static void dcn321_insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scalin static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, unsigned int index) { - int i; + unsigned int i; if (*num_entries == 0) return; @@ -265,19 +265,19 @@ static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, unsigned int end_index = 0; unsigned int current_bw = 0; - for (int i = 0; i < (*num_entries - 1); i++) { + for (unsigned int i = 0; i + 1 < *num_entries; i++) { if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) { - current_bw = table[i].net_bw_in_kbytes_sec; + current_bw = (unsigned int)table[i].net_bw_in_kbytes_sec; start_index = i; end_index = ++i; - while ((i < (*num_entries - 1)) && (table[i+1].net_bw_in_kbytes_sec == current_bw)) + while ((i + 1 < *num_entries) && (table[i+1].net_bw_in_kbytes_sec == current_bw)) end_index = ++i; } if (start_index != end_index) { - for (int j = start_index; j < end_index; j++) { - for (int k = start_index; k < end_index; k++) { + for (unsigned int j = start_index; j < end_index; j++) { + for (unsigned int k = start_index; k < end_index; k++) { if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz) swap_table_entries(&table[k], &table[k+1]); } @@ -296,7 +296,7 @@ static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, */ static void remove_inconsistent_entries(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) { - for (int i = 0; i < (*num_entries - 1); i++) { + for (unsigned int i = 0; i + 1 < *num_entries; i++) { if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) { if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) || (table[i].fabricclk_mhz > table[i+1].fabricclk_mhz)) @@ -344,7 +344,8 @@ static int override_max_clk_values(struct clk_limit_table_entry *max_clk_limit, static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params, struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) { - int i, j; + int i; + unsigned int j, k; struct _vcs_dpi_voltage_scaling_st entry = {0}; struct clk_limit_table_entry max_clk_data = {0}; @@ -414,12 +415,12 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk max_clk_data.dppclk_mhz = max_clk_data.dispclk_mhz; if (max_clk_data.fclk_mhz == 0) - max_clk_data.fclk_mhz = max_clk_data.dcfclk_mhz * + max_clk_data.fclk_mhz = (unsigned int)(max_clk_data.dcfclk_mhz * dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / - dcn3_21_soc.pct_ideal_fabric_bw_after_urgent; + dcn3_21_soc.pct_ideal_fabric_bw_after_urgent); if (max_clk_data.phyclk_mhz == 0) - max_clk_data.phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; + max_clk_data.phyclk_mhz = (unsigned int)dcn3_21_soc.clock_limits[0].phyclk_mhz; *num_entries = 0; entry.dispclk_mhz = max_clk_data.dispclk_mhz; @@ -431,8 +432,8 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk entry.phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; // Insert all the DCFCLK STAs - for (i = 0; i < num_dcfclk_stas; i++) { - entry.dcfclk_mhz = dcfclk_sta_targets[i]; + for (k = 0; k < num_dcfclk_stas; k++) { + entry.dcfclk_mhz = dcfclk_sta_targets[k]; entry.fabricclk_mhz = 0; entry.dram_speed_mts = 0; @@ -451,10 +452,10 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); // Insert the UCLK DPMS - for (i = 0; i < num_uclk_dpms; i++) { + for (k = 0; k < num_uclk_dpms; k++) { entry.dcfclk_mhz = 0; entry.fabricclk_mhz = 0; - entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16; + entry.dram_speed_mts = bw_params->clk_table.entries[k].memclk_mhz * 16; get_optimal_ntuple(&entry); entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry); @@ -463,9 +464,9 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk // If FCLK is coarse grained, insert individual DPMs. if (num_fclk_dpms > 2) { - for (i = 0; i < num_fclk_dpms; i++) { + for (k = 0; k < num_fclk_dpms; k++) { entry.dcfclk_mhz = 0; - entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; + entry.fabricclk_mhz = bw_params->clk_table.entries[k].fclk_mhz; entry.dram_speed_mts = 0; get_optimal_ntuple(&entry); @@ -489,7 +490,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk // ratios (by derate, are exact). // Remove states that require higher clocks than are supported - for (i = *num_entries - 1; i >= 0 ; i--) { + for (i = (int)*num_entries - 1; i >= 0 ; i--) { if (table[i].dcfclk_mhz > max_clk_data.dcfclk_mhz || table[i].fabricclk_mhz > max_clk_data.fclk_mhz || table[i].dram_speed_mts > max_clk_data.memclk_mhz * 16) @@ -519,7 +520,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk // coarse grained DPMs and remove duplicates. // Round up UCLKs - for (i = *num_entries - 1; i >= 0 ; i--) { + for (i = (int)*num_entries - 1; i >= 0 ; i--) { for (j = 0; j < num_uclk_dpms; j++) { if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) { table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16; @@ -530,7 +531,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk // If FCLK is coarse grained, round up to next DPMs if (num_fclk_dpms > 2) { - for (i = *num_entries - 1; i >= 0 ; i--) { + for (i = (int)*num_entries - 1; i >= 0 ; i--) { for (j = 0; j < num_fclk_dpms; j++) { if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) { table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz; @@ -541,7 +542,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk } // Otherwise, round up to minimum. else { - for (i = *num_entries - 1; i >= 0 ; i--) { + for (i = (int)*num_entries - 1; i >= 0 ; i--) { if (table[i].fabricclk_mhz < min_fclk_mhz) { table[i].fabricclk_mhz = min_fclk_mhz; } @@ -549,7 +550,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk } // Round DCFCLKs up to minimum - for (i = *num_entries - 1; i >= 0 ; i--) { + for (i = (int)*num_entries - 1; i >= 0 ; i--) { if (table[i].dcfclk_mhz < min_dcfclk_mhz) { table[i].dcfclk_mhz = min_dcfclk_mhz; } @@ -557,7 +558,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk // Remove duplicate states, note duplicate states are always neighbouring since table is sorted. i = 0; - while (i < *num_entries - 1) { + while (i < (int)*num_entries - 1) { if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz && table[i].dram_speed_mts == table[i + 1].dram_speed_mts) @@ -567,9 +568,8 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk } // Fix up the state indicies - for (i = *num_entries - 1; i >= 0 ; i--) { + for (i = (int)*num_entries - 1; i >= 0 ; i--) table[i].state = i; - } return 0; } @@ -588,12 +588,12 @@ static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; if (optimal_fclk) - *optimal_fclk = bw_from_dram / - (dcn3_21_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); + *optimal_fclk = (unsigned int)(bw_from_dram / + (dcn3_21_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100))); if (optimal_dcfclk) - *optimal_dcfclk = bw_from_dram / - (dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); + *optimal_dcfclk = (unsigned int)(bw_from_dram / + (dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100))); } /** dcn321_update_bw_bounding_box @@ -688,9 +688,12 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel); } - if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) - dc->dml2_options.bbox_overrides.dram_chanel_width_bytes = - dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; + if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) { + unsigned int dram_channel_width_bytes = (unsigned int)dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; + + dc->dml2_options.bbox_overrides.dram_chanel_width_bytes = dram_channel_width_bytes; + dcn3_21_soc.dram_channel_width_bytes = dram_channel_width_bytes; + } /* DML DSC delay factor workaround */ dcn3_21_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0; @@ -729,13 +732,13 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; } if (!max_dcfclk_mhz) - max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz; + max_dcfclk_mhz = (unsigned int)dcn3_21_soc.clock_limits[0].dcfclk_mhz; if (!max_dispclk_mhz) - max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz; + max_dispclk_mhz = (unsigned int)dcn3_21_soc.clock_limits[0].dispclk_mhz; if (!max_dppclk_mhz) - max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz; + max_dppclk_mhz = (unsigned int)dcn3_21_soc.clock_limits[0].dppclk_mhz; if (!max_phyclk_mhz) - max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; + max_phyclk_mhz = (unsigned int)dcn3_21_soc.clock_limits[0].phyclk_mhz; if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c index 7f40048dd67d..bef2b0bcfcf0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c @@ -233,7 +233,7 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc, struct clk_limit_table *clk_table = &bw_params->clk_table; struct _vcs_dpi_voltage_scaling_st *clock_limits = dc->scratch.update_bw_bounding_box.clock_limits; - int max_dispclk_mhz = 0, max_dppclk_mhz = 0; + unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0; dc_assert_fp_enabled(); @@ -357,21 +357,21 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc, dc->dml2_options.bbox_overrides.clks_table.num_states = clk_table->num_entries; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz = - clock_limits[i].dcfclk_mhz; + (unsigned int)clock_limits[i].dcfclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz = - clock_limits[i].fabricclk_mhz; + (unsigned int)clock_limits[i].fabricclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz = - clock_limits[i].dispclk_mhz; + (unsigned int)clock_limits[i].dispclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz = - clock_limits[i].dppclk_mhz; + (unsigned int)clock_limits[i].dppclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz = - clock_limits[i].socclk_mhz; + (unsigned int)clock_limits[i].socclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz = clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio; - dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_speed_mts; + dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = (unsigned int)clock_limits[i].dram_speed_mts; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz = - clock_limits[i].dtbclk_mhz; + (unsigned int)clock_limits[i].dtbclk_mhz; dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = clk_table->num_entries; dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = @@ -415,11 +415,11 @@ static bool is_dual_plane(enum surface_pixel_format format) static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing) { unsigned int num_lines = 0; - unsigned int lines_time_in_ns = 1000.0 * - (((float)timing->h_total * 1000.0) / - ((float)timing->pix_clk_100hz / 10.0)); + double lines_time_in_ns = 1000.0 * + (((double)timing->h_total * 1000.0) / + ((double)timing->pix_clk_100hz / 10.0)); - num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); + num_lines = (unsigned int)dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); return num_lines; } @@ -440,7 +440,8 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc, display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt; + unsigned int i; + int pipe_cnt; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = 0; bool upscaled = false; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c index 73c2aee57f28..9545d946215b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c @@ -266,7 +266,7 @@ void dcn351_update_bw_bounding_box_fpu(struct dc *dc, struct clk_limit_table *clk_table = &bw_params->clk_table; struct _vcs_dpi_voltage_scaling_st *clock_limits = dc->scratch.update_bw_bounding_box.clock_limits; - int max_dispclk_mhz = 0, max_dppclk_mhz = 0; + unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0; dc_assert_fp_enabled(); @@ -390,20 +390,20 @@ void dcn351_update_bw_bounding_box_fpu(struct dc *dc, dc->dml2_options.bbox_overrides.clks_table.num_states = clk_table->num_entries; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz = - clock_limits[i].dcfclk_mhz; + (unsigned int)clock_limits[i].dcfclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz = - clock_limits[i].fabricclk_mhz; + (unsigned int)clock_limits[i].fabricclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz = - clock_limits[i].dispclk_mhz; + (unsigned int)clock_limits[i].dispclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz = - clock_limits[i].dppclk_mhz; + (unsigned int)clock_limits[i].dppclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz = - clock_limits[i].socclk_mhz; + (unsigned int)clock_limits[i].socclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz = clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio; - dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_speed_mts; + dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = (unsigned int)clock_limits[i].dram_speed_mts; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz = - clock_limits[i].dtbclk_mhz; + (unsigned int)clock_limits[i].dtbclk_mhz; dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = clk_table->num_entries; dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = @@ -447,11 +447,11 @@ static bool is_dual_plane(enum surface_pixel_format format) static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing) { unsigned int num_lines = 0; - unsigned int lines_time_in_ns = 1000.0 * - (((float)timing->h_total * 1000.0) / - ((float)timing->pix_clk_100hz / 10.0)); + double lines_time_in_ns = 1000.0 * + (((double)timing->h_total * 1000.0) / + ((double)timing->pix_clk_100hz / 10.0)); - num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); + num_lines = (unsigned int)dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); return num_lines; } @@ -472,7 +472,8 @@ int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc, display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt; + int pipe_cnt; + unsigned int i; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = 0; bool upscaled = false; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c index 85453bbb4f9b..c42884dc16b2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -246,7 +246,7 @@ unsigned int get_total_surface_size_in_mall_bytes( unsigned int num_pipes) { unsigned int k; - unsigned int size = 0.0; + unsigned int size = 0; recalculate_params(mode_lib, pipes, num_pipes); for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) size += mode_lib->vba.SurfaceSizeInMALL[k]; @@ -304,7 +304,7 @@ bool get_is_phantom_pipe(struct display_mode_lib *mode_lib, const display_e2e_pi static void fetch_socbb_params(struct display_mode_lib *mode_lib) { soc_bounding_box_st *soc = &mode_lib->vba.soc; - int i; + unsigned int i; // SOC Bounding Box Parameters mode_lib->vba.ReturnBusWidth = soc->return_bus_width_bytes; @@ -343,7 +343,7 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib) mode_lib->vba.FCLKChangeLatency = soc->fclk_change_latency_us; mode_lib->vba.USRRetrainingLatency = soc->usr_retraining_latency_us; mode_lib->vba.SMNLatency = soc->smn_latency_us; - mode_lib->vba.MALLAllocatedForDCNFinal = soc->mall_allocated_for_dcn_mbytes; + mode_lib->vba.MALLAllocatedForDCNFinal = (unsigned int)soc->mall_allocated_for_dcn_mbytes; mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE = soc->pct_ideal_dram_bw_after_urgent_strobe; mode_lib->vba.MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation = @@ -946,7 +946,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) */ static void cache_debug_params(struct display_mode_lib *mode_lib) { - int k = 0; + unsigned int k = 0; for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++) mode_lib->vba.CachedActiveDRAMClockChangeLatencyMargin[k] = mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c index cf194bcba455..ff5cb04db9dd 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c @@ -261,12 +261,12 @@ void dml1_extract_rq_regs( if (rq_param->yuv420) { if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); /* half to chroma */ + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 64.0); /* half to chroma */ } else { - detile_buf_plane1_addr = dml_round_to_multiple( + detile_buf_plane1_addr = (unsigned int)(dml_round_to_multiple( (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 256, - 0) / 64.0; /* 2/3 to chroma */ + 0) / 64.0); /* 2/3 to chroma */ } } rq_regs->plane1_base_address = detile_buf_plane1_addr; @@ -447,7 +447,7 @@ static void dml1_rq_dlg_get_row_heights( */ if (tiling != dm_sw_linear) log2_blk_height = log2_blk256_height - + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); + + (unsigned int)dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); else log2_blk_height = 0; /* blk height of 1 */ @@ -522,7 +522,7 @@ static void dml1_rq_dlg_get_row_heights( * round the result down to a power of two. */ if (surf_linear) { - log2_dpte_row_height_linear = dml_floor( + log2_dpte_row_height_linear = (unsigned int)dml_floor( dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); @@ -686,7 +686,7 @@ static void get_surf_rq_param( */ if (pipe_src_param->sw_mode != dm_sw_linear) log2_blk_height = log2_blk256_height - + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); + + (unsigned int)dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); else log2_blk_height = 0; /* blk height of 1 */ @@ -848,7 +848,7 @@ static void get_surf_rq_param( * round the result down to a power of two. */ if (surf_linear) { - log2_dpte_row_height_linear = dml_floor( + log2_dpte_row_height_linear = (unsigned int)dml_floor( dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); @@ -922,7 +922,7 @@ static void get_surf_rq_param( /* since dpte groups are only aligned to dpte_req_width and not dpte_group_width, * the upper bound for the dpte groups per row is as follows. */ - rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( + rq_dlg_param->dpte_groups_per_row_ub = (unsigned int)dml_ceil( (double) dpte_row_width_ub / dpte_group_width, 1); @@ -1248,8 +1248,8 @@ void dml1_rq_dlg_get_dlg_params( dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; - pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz - + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; + pixel_rate_delay_subtotal = (unsigned int)(dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz + + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz); vstartup_start = e2e_pipe_param->pipe.dest.vstartup_start; @@ -1439,7 +1439,7 @@ void dml1_rq_dlg_get_dlg_params( } disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; /* in terms of line */ - disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; /* in terms of refclk */ + disp_dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); /* in terms of refclk */ ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); DTRACE( "DLG: %s: disp_dlg_regs->dst_y_after_scaler = 0x%0x", @@ -1576,19 +1576,19 @@ void dml1_rq_dlg_get_dlg_params( / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c); if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (mode_422) { swath_width_pixels_ub_l = swath_width_ub_l * 2; /* *2 for 2 pixel per element */ @@ -1844,7 +1844,7 @@ void dml1_rq_dlg_get_dlg_params( cur0_req_size = 256; } - cur0_req_width = (double) cur0_req_size / ((double) cur0_bit_per_pixel / 8.0); + cur0_req_width = (unsigned int)((double) cur0_req_size / ((double) cur0_bit_per_pixel / 8.0)); cur0_width_ub = dml_ceil((double) cur0_src_width / (double) cur0_req_width, 1) * (double) cur0_req_width; cur0_req_per_width = cur0_width_ub / (double) cur0_req_width; @@ -1917,7 +1917,7 @@ void dml1_rq_dlg_get_dlg_params( disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs->qos_ramp_disable_cur0 = 0; - disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + disp_ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); print__ttu_regs_st(mode_lib, disp_ttu_regs); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h index 6b2ab4ec2b5f..be6ebf53d9a2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h +++ b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h @@ -31,7 +31,7 @@ static inline double dml_min(double a, double b) { - return (double) dcn_bw_min2(a, b); + return (double)dcn_bw_min2((float)a, (float)b); } static inline double dml_min3(double a, double b, double c) @@ -46,7 +46,7 @@ static inline double dml_min4(double a, double b, double c, double d) static inline double dml_max(double a, double b) { - return (double) dcn_bw_max2(a, b); + return (double)dcn_bw_max2((float)a, (float)b); } static inline double dml_max3(double a, double b, double c) @@ -68,14 +68,14 @@ static inline double dml_ceil(double a, double granularity) { if (granularity == 0) return 0; - return (double) dcn_bw_ceil2(a, granularity); + return (double)dcn_bw_ceil2((float)a, (float)granularity); } static inline double dml_floor(double a, double granularity) { if (granularity == 0) return 0; - return (double) dcn_bw_floor2(a, granularity); + return (double)dcn_bw_floor2((float)a, (float)granularity); } static inline double dml_round(double a) @@ -103,31 +103,31 @@ static inline int dml_log2(double x) static inline double dml_pow(double a, int exp) { - return (double) dcn_bw_pow(a, exp); + return (double)dcn_bw_pow((float)a, (float)exp); } static inline double dml_fmod(double f, int val) { - return (double) dcn_bw_mod(f, val); + return (double)dcn_bw_mod((float)f, (float)val); } static inline double dml_ceil_2(double f) { - return (double) dcn_bw_ceil2(f, 2); + return (double)dcn_bw_ceil2((float)f, 2.0f); } static inline double dml_ceil_ex(double x, double granularity) { if (granularity == 0) return 0; - return (double) dcn_bw_ceil2(x, granularity); + return (double)dcn_bw_ceil2((float)x, (float)granularity); } static inline double dml_floor_ex(double x, double granularity) { if (granularity == 0) return 0; - return (double) dcn_bw_floor2(x, granularity); + return (double)dcn_bw_floor2((float)x, (float)granularity); } static inline unsigned int dml_round_to_multiple(unsigned int num, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c index ef75eb7d5adc..b8fc27a5361e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c @@ -96,7 +96,7 @@ static void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc, if (!table) return; - index = (bpp - table[0].bpp) * 2; + index = (int)((bpp - table[0].bpp) * 2); /* requested size is bigger than the table */ if (index >= table_size) { @@ -112,50 +112,50 @@ static void get_ofs_set(qp_set ofs, enum colour_mode mode, float bpp) int *p = ofs; if (mode == CM_444 || mode == CM_RGB) { - *p++ = (bpp <= 6) ? (0) : ((((bpp >= 8) && (bpp <= 12))) ? (2) : ((bpp >= 15) ? (10) : ((((bpp > 6) && (bpp < 8))) ? (0 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (2 + dsc_roundf((bpp - 12) * (8 / 3.0)))))); - *p++ = (bpp <= 6) ? (-2) : ((((bpp >= 8) && (bpp <= 12))) ? (0) : ((bpp >= 15) ? (8) : ((((bpp > 6) && (bpp < 8))) ? (-2 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (0 + dsc_roundf((bpp - 12) * (8 / 3.0)))))); - *p++ = (bpp <= 6) ? (-2) : ((((bpp >= 8) && (bpp <= 12))) ? (0) : ((bpp >= 15) ? (6) : ((((bpp > 6) && (bpp < 8))) ? (-2 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (0 + dsc_roundf((bpp - 12) * (6 / 3.0)))))); - *p++ = (bpp <= 6) ? (-4) : ((((bpp >= 8) && (bpp <= 12))) ? (-2) : ((bpp >= 15) ? (4) : ((((bpp > 6) && (bpp < 8))) ? (-4 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (-2 + dsc_roundf((bpp - 12) * (6 / 3.0)))))); - *p++ = (bpp <= 6) ? (-6) : ((((bpp >= 8) && (bpp <= 12))) ? (-4) : ((bpp >= 15) ? (2) : ((((bpp > 6) && (bpp < 8))) ? (-6 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (-4 + dsc_roundf((bpp - 12) * (6 / 3.0)))))); - *p++ = (bpp <= 12) ? (-6) : ((bpp >= 15) ? (0) : (-6 + dsc_roundf((bpp - 12) * (6 / 3.0)))); - *p++ = (bpp <= 12) ? (-8) : ((bpp >= 15) ? (-2) : (-8 + dsc_roundf((bpp - 12) * (6 / 3.0)))); - *p++ = (bpp <= 12) ? (-8) : ((bpp >= 15) ? (-4) : (-8 + dsc_roundf((bpp - 12) * (4 / 3.0)))); - *p++ = (bpp <= 12) ? (-8) : ((bpp >= 15) ? (-6) : (-8 + dsc_roundf((bpp - 12) * (2 / 3.0)))); - *p++ = (bpp <= 12) ? (-10) : ((bpp >= 15) ? (-8) : (-10 + dsc_roundf((bpp - 12) * (2 / 3.0)))); + *p++ = (int)((bpp <= 6) ? (0) : ((((bpp >= 8) && (bpp <= 12))) ? (2) : ((bpp >= 15) ? (10) : ((((bpp > 6) && (bpp < 8))) ? (0 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (2 + dsc_roundf((bpp - 12) * (8 / 3.0))))))); + *p++ = (int)((bpp <= 6) ? (-2) : ((((bpp >= 8) && (bpp <= 12))) ? (0) : ((bpp >= 15) ? (8) : ((((bpp > 6) && (bpp < 8))) ? (-2 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (0 + dsc_roundf((bpp - 12) * (8 / 3.0))))))); + *p++ = (int)((bpp <= 6) ? (-2) : ((((bpp >= 8) && (bpp <= 12))) ? (0) : ((bpp >= 15) ? (6) : ((((bpp > 6) && (bpp < 8))) ? (-2 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (0 + dsc_roundf((bpp - 12) * (6 / 3.0))))))); + *p++ = (int)((bpp <= 6) ? (-4) : ((((bpp >= 8) && (bpp <= 12))) ? (-2) : ((bpp >= 15) ? (4) : ((((bpp > 6) && (bpp < 8))) ? (-4 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (-2 + dsc_roundf((bpp - 12) * (6 / 3.0))))))); + *p++ = (int)((bpp <= 6) ? (-6) : ((((bpp >= 8) && (bpp <= 12))) ? (-4) : ((bpp >= 15) ? (2) : ((((bpp > 6) && (bpp < 8))) ? (-6 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (-4 + dsc_roundf((bpp - 12) * (6 / 3.0))))))); + *p++ = (int)((bpp <= 12) ? (-6) : ((bpp >= 15) ? (0) : (-6 + dsc_roundf((bpp - 12) * (6 / 3.0))))); + *p++ = (int)((bpp <= 12) ? (-8) : ((bpp >= 15) ? (-2) : (-8 + dsc_roundf((bpp - 12) * (6 / 3.0))))); + *p++ = (int)((bpp <= 12) ? (-8) : ((bpp >= 15) ? (-4) : (-8 + dsc_roundf((bpp - 12) * (4 / 3.0))))); + *p++ = (int)((bpp <= 12) ? (-8) : ((bpp >= 15) ? (-6) : (-8 + dsc_roundf((bpp - 12) * (2 / 3.0))))); + *p++ = (int)((bpp <= 12) ? (-10) : ((bpp >= 15) ? (-8) : (-10 + dsc_roundf((bpp - 12) * (2 / 3.0))))); *p++ = -10; - *p++ = (bpp <= 6) ? (-12) : ((bpp >= 8) ? (-10) : (-12 + dsc_roundf((bpp - 6) * (2 / 2.0)))); + *p++ = (int)((bpp <= 6) ? (-12) : ((bpp >= 8) ? (-10) : (-12 + dsc_roundf((bpp - 6) * (2 / 2.0))))); *p++ = -12; *p++ = -12; *p++ = -12; } else if (mode == CM_422) { - *p++ = (bpp <= 8) ? (2) : ((bpp >= 10) ? (10) : (2 + dsc_roundf((bpp - 8) * (8 / 2.0)))); - *p++ = (bpp <= 8) ? (0) : ((bpp >= 10) ? (8) : (0 + dsc_roundf((bpp - 8) * (8 / 2.0)))); - *p++ = (bpp <= 8) ? (0) : ((bpp >= 10) ? (6) : (0 + dsc_roundf((bpp - 8) * (6 / 2.0)))); - *p++ = (bpp <= 8) ? (-2) : ((bpp >= 10) ? (4) : (-2 + dsc_roundf((bpp - 8) * (6 / 2.0)))); - *p++ = (bpp <= 8) ? (-4) : ((bpp >= 10) ? (2) : (-4 + dsc_roundf((bpp - 8) * (6 / 2.0)))); - *p++ = (bpp <= 8) ? (-6) : ((bpp >= 10) ? (0) : (-6 + dsc_roundf((bpp - 8) * (6 / 2.0)))); - *p++ = (bpp <= 8) ? (-8) : ((bpp >= 10) ? (-2) : (-8 + dsc_roundf((bpp - 8) * (6 / 2.0)))); - *p++ = (bpp <= 8) ? (-8) : ((bpp >= 10) ? (-4) : (-8 + dsc_roundf((bpp - 8) * (4 / 2.0)))); - *p++ = (bpp <= 8) ? (-8) : ((bpp >= 10) ? (-6) : (-8 + dsc_roundf((bpp - 8) * (2 / 2.0)))); - *p++ = (bpp <= 8) ? (-10) : ((bpp >= 10) ? (-8) : (-10 + dsc_roundf((bpp - 8) * (2 / 2.0)))); + *p++ = (int)((bpp <= 8) ? (2) : ((bpp >= 10) ? (10) : (2 + dsc_roundf((bpp - 8) * (8 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (0) : ((bpp >= 10) ? (8) : (0 + dsc_roundf((bpp - 8) * (8 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (0) : ((bpp >= 10) ? (6) : (0 + dsc_roundf((bpp - 8) * (6 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (-2) : ((bpp >= 10) ? (4) : (-2 + dsc_roundf((bpp - 8) * (6 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (-4) : ((bpp >= 10) ? (2) : (-4 + dsc_roundf((bpp - 8) * (6 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (-6) : ((bpp >= 10) ? (0) : (-6 + dsc_roundf((bpp - 8) * (6 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (-8) : ((bpp >= 10) ? (-2) : (-8 + dsc_roundf((bpp - 8) * (6 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (-8) : ((bpp >= 10) ? (-4) : (-8 + dsc_roundf((bpp - 8) * (4 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (-8) : ((bpp >= 10) ? (-6) : (-8 + dsc_roundf((bpp - 8) * (2 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (-10) : ((bpp >= 10) ? (-8) : (-10 + dsc_roundf((bpp - 8) * (2 / 2.0))))); *p++ = -10; - *p++ = (bpp <= 6) ? (-12) : ((bpp >= 7) ? (-10) : (-12 + dsc_roundf((bpp - 6) * (2.0 / 1)))); + *p++ = (int)((bpp <= 6) ? (-12) : ((bpp >= 7) ? (-10) : (-12 + dsc_roundf((bpp - 6) * (2.0 / 1))))); *p++ = -12; *p++ = -12; *p++ = -12; } else { - *p++ = (bpp <= 6) ? (2) : ((bpp >= 8) ? (10) : (2 + dsc_roundf((bpp - 6) * (8 / 2.0)))); - *p++ = (bpp <= 6) ? (0) : ((bpp >= 8) ? (8) : (0 + dsc_roundf((bpp - 6) * (8 / 2.0)))); - *p++ = (bpp <= 6) ? (0) : ((bpp >= 8) ? (6) : (0 + dsc_roundf((bpp - 6) * (6 / 2.0)))); - *p++ = (bpp <= 6) ? (-2) : ((bpp >= 8) ? (4) : (-2 + dsc_roundf((bpp - 6) * (6 / 2.0)))); - *p++ = (bpp <= 6) ? (-4) : ((bpp >= 8) ? (2) : (-4 + dsc_roundf((bpp - 6) * (6 / 2.0)))); - *p++ = (bpp <= 6) ? (-6) : ((bpp >= 8) ? (0) : (-6 + dsc_roundf((bpp - 6) * (6 / 2.0)))); - *p++ = (bpp <= 6) ? (-8) : ((bpp >= 8) ? (-2) : (-8 + dsc_roundf((bpp - 6) * (6 / 2.0)))); - *p++ = (bpp <= 6) ? (-8) : ((bpp >= 8) ? (-4) : (-8 + dsc_roundf((bpp - 6) * (4 / 2.0)))); - *p++ = (bpp <= 6) ? (-8) : ((bpp >= 8) ? (-6) : (-8 + dsc_roundf((bpp - 6) * (2 / 2.0)))); - *p++ = (bpp <= 6) ? (-10) : ((bpp >= 8) ? (-8) : (-10 + dsc_roundf((bpp - 6) * (2 / 2.0)))); + *p++ = (int)((bpp <= 6) ? (2) : ((bpp >= 8) ? (10) : (2 + dsc_roundf((bpp - 6) * (8 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (0) : ((bpp >= 8) ? (8) : (0 + dsc_roundf((bpp - 6) * (8 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (0) : ((bpp >= 8) ? (6) : (0 + dsc_roundf((bpp - 6) * (6 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (-2) : ((bpp >= 8) ? (4) : (-2 + dsc_roundf((bpp - 6) * (6 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (-4) : ((bpp >= 8) ? (2) : (-4 + dsc_roundf((bpp - 6) * (6 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (-6) : ((bpp >= 8) ? (0) : (-6 + dsc_roundf((bpp - 6) * (6 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (-8) : ((bpp >= 8) ? (-2) : (-8 + dsc_roundf((bpp - 6) * (6 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (-8) : ((bpp >= 8) ? (-4) : (-8 + dsc_roundf((bpp - 6) * (4 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (-8) : ((bpp >= 8) ? (-6) : (-8 + dsc_roundf((bpp - 6) * (2 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (-10) : ((bpp >= 8) ? (-8) : (-10 + dsc_roundf((bpp - 6) * (2 / 2.0))))); *p++ = -10; - *p++ = (bpp <= 4) ? (-12) : ((bpp >= 5) ? (-10) : (-12 + dsc_roundf((bpp - 4) * (2 / 1.0)))); + *p++ = (int)((bpp <= 4) ? (-12) : ((bpp >= 5) ? (-10) : (-12 + dsc_roundf((bpp - 4) * (2 / 1.0))))); *p++ = -12; *p++ = -12; *p++ = -12; @@ -179,7 +179,7 @@ void _do_calc_rc_params(struct rc_params *rc, dc_assert_fp_enabled(); - bpp = ((float)drm_bpp / 16.0); + bpp = (float)((float)drm_bpp / 16.0); /* in native_422 or native_420 modes, the bits_per_pixel is double the * target bpp (the latter is what calc_rc_params expects) */ @@ -189,29 +189,29 @@ void _do_calc_rc_params(struct rc_params *rc, rc->rc_quant_incr_limit0 = ((bpc == BPC_8) ? 11 : (bpc == BPC_10 ? 15 : 19)) - ((minor_version == 1 && cm == CM_444) ? 1 : 0); rc->rc_quant_incr_limit1 = ((bpc == BPC_8) ? 11 : (bpc == BPC_10 ? 15 : 19)) - ((minor_version == 1 && cm == CM_444) ? 1 : 0); - bpp_group = MODE_SELECT(bpp, bpp * 2.0, bpp * 2.0); + bpp_group = MODE_SELECT(bpp, bpp * 2.0f, bpp * 2.0f); switch (cm) { case CM_420: - rc->initial_fullness_offset = (bpp >= 6) ? (2048) : ((bpp <= 4) ? (6144) : ((((bpp > 4) && (bpp <= 5))) ? (6144 - dsc_roundf((bpp - 4) * (512))) : (5632 - dsc_roundf((bpp - 5) * (3584))))); + rc->initial_fullness_offset = (int)((bpp >= 6) ? (2048) : ((bpp <= 4) ? (6144) : ((((bpp > 4) && (bpp <= 5))) ? (6144 - dsc_roundf((bpp - 4) * (512))) : (5632 - dsc_roundf((bpp - 5) * (3584)))))); rc->first_line_bpg_offset = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)((3 * bpc * 3) - (3 * bpp_group))); rc->second_line_bpg_offset = median3(0, 12, (int)((3 * bpc * 3) - (3 * bpp_group))); break; case CM_422: - rc->initial_fullness_offset = (bpp >= 8) ? (2048) : ((bpp <= 7) ? (5632) : (5632 - dsc_roundf((bpp - 7) * (3584)))); + rc->initial_fullness_offset = (int)((bpp >= 8) ? (2048) : ((bpp <= 7) ? (5632) : (5632 - dsc_roundf((bpp - 7) * (3584))))); rc->first_line_bpg_offset = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)((3 * bpc * 4) - (3 * bpp_group))); rc->second_line_bpg_offset = 0; break; case CM_444: case CM_RGB: - rc->initial_fullness_offset = (bpp >= 12) ? (2048) : ((bpp <= 8) ? (6144) : ((((bpp > 8) && (bpp <= 10))) ? (6144 - dsc_roundf((bpp - 8) * (512 / 2))) : (5632 - dsc_roundf((bpp - 10) * (3584 / 2))))); + rc->initial_fullness_offset = (int)((bpp >= 12) ? (2048) : ((bpp <= 8) ? (6144) : ((((bpp > 8) && (bpp <= 10))) ? (6144 - dsc_roundf((bpp - 8) * (512 / 2))) : (5632 - dsc_roundf((bpp - 10) * (3584 / 2)))))); rc->first_line_bpg_offset = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)(((3 * bpc + (cm == CM_444 ? 0 : 2)) * 3) - (3 * bpp_group))); rc->second_line_bpg_offset = 0; break; } - initial_xmit_delay_factor = (cm == CM_444 || cm == CM_RGB) ? 1.0 : 2.0; - rc->initial_xmit_delay = dsc_roundf(8192.0/2.0/bpp/initial_xmit_delay_factor); + initial_xmit_delay_factor = (float)((cm == CM_444 || cm == CM_RGB) ? 1.0 : 2.0); + rc->initial_xmit_delay = (int)dsc_roundf(8192.0/2.0/bpp/initial_xmit_delay_factor); if (cm == CM_422 || cm == CM_420) slice_width /= 2; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/README.md b/drivers/gpu/drm/amd/display/dc/dml2_0/README.md new file mode 100644 index 000000000000..9e8814fbe52f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/README.md @@ -0,0 +1,31 @@ +# DML2_0 (Display Mode Library 2.0) repository + +## Category to Directory Mapping + +```yaml +directory_categories: + app_tools: + - dml21/build/ + - dml21/src/dml2_unit_test/ + - utils/ + + driver_hw_dependent: + - dml21/inc/bounding_boxes/ + - dml21/src/dml2_cga/ + - dml21/src/dml2_core/ + - dml21/src/dml2_dpmm/ + - dml21/src/dml2_mcg/ + - dml21/src/dml2_pmo/ + - dml21/src/dml2_standalone_libraries/ + - dml21/src/dml2_utm_soc_bb/ + + driver_hw_independent: + - ./ + - dml21/ + - dml21/inc/ + - dml21/src/dml2_top/ + - dml21/src/inc/ + + undefined: + - .github/ +``` diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c index 698d62fb9cf7..16514f1e4ed9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c @@ -1119,10 +1119,10 @@ static dml_bool_t CalculatePrefetchSchedule(struct display_mode_lib_scratch_st * if (p->myPipe->Dppclk == 0.0 || p->myPipe->Dispclk == 0.0) return true; - *p->DSTXAfterScaler = (dml_uint_t) dml_round(s->DPPCycles * p->myPipe->PixelClock / p->myPipe->Dppclk + s->DISPCLKCycles * p->myPipe->PixelClock / p->myPipe->Dispclk + p->DSCDelay, 1.0); + *p->DSTXAfterScaler = (dml_uint_t) dml_round(s->DPPCycles * p->myPipe->PixelClock / p->myPipe->Dppclk + s->DISPCLKCycles * p->myPipe->PixelClock / p->myPipe->Dispclk + p->DSCDelay, true); *p->DSTXAfterScaler = (dml_uint_t) dml_round(*p->DSTXAfterScaler + (p->myPipe->ODMMode != dml_odm_mode_bypass ? 18 : 0) + (p->myPipe->DPPPerSurface - 1) * p->DPP_RECOUT_WIDTH + ((p->myPipe->ODMMode == dml_odm_mode_split_1to2 || p->myPipe->ODMMode == dml_odm_mode_mso_1to2) ? (dml_float_t)p->myPipe->HActive / 2.0 : 0) + - ((p->myPipe->ODMMode == dml_odm_mode_mso_1to4) ? (dml_float_t)p->myPipe->HActive * 3.0 / 4.0 : 0), 1.0); + ((p->myPipe->ODMMode == dml_odm_mode_mso_1to4) ? (dml_float_t)p->myPipe->HActive * 3.0 / 4.0 : 0), true); #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: DPPCycles = %u\n", __func__, s->DPPCycles); @@ -4301,7 +4301,7 @@ static void CalculateSwathAndDETConfiguration(struct display_mode_lib_scratch_st *p->compbuf_reserved_space_64b = 2 * p->PixelChunkSizeInKByte * 1024 / 64; if (*p->UnboundedRequestEnabled) { - *p->compbuf_reserved_space_64b = dml_max(*p->compbuf_reserved_space_64b, + *p->compbuf_reserved_space_64b = (dml_uint_t)dml_max(*p->compbuf_reserved_space_64b, (dml_float_t)(p->ROBBufferSizeInKByte * 1024/64) - (dml_float_t)(RoundedUpSwathSizeBytesY[SurfaceDoingUnboundedRequest] * TTUFIFODEPTH / MAXIMUMCOMPRESSION/64)); } @@ -6178,9 +6178,9 @@ static void CalculateImmediateFlipBandwithSupport( static dml_uint_t MicroSecToVertLines(dml_uint_t num_us, dml_uint_t h_total, dml_float_t pixel_clock) { - dml_uint_t lines_time_in_ns = 1000.0 * (h_total * 1000.0) / (pixel_clock * 1000.0); + dml_uint_t lines_time_in_ns = (dml_uint_t)(1000.0 * (h_total * 1000.0) / (pixel_clock * 1000.0)); - return dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); + return (dml_uint_t)dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); } /// @brief Calculate the maximum vstartup for mode support and mode programming consideration @@ -6207,9 +6207,9 @@ static dml_uint_t CalculateMaxVStartup( // + 2 is because // 1 -> VStartup_start should be 1 line before VSync // 1 -> always reserve 1 line between start of VBlank to VStartup signal - dml_uint_t vblank_nom_vsync_capped = dml_max(vblank_nom_input, + dml_uint_t vblank_nom_vsync_capped = (dml_uint_t)dml_max(vblank_nom_input, timing->VTotal[plane_idx] - timing->VActive[plane_idx] - timing->VFrontPorch[plane_idx] + 2); - dml_uint_t vblank_nom_max_allowed_capped = dml_min(vblank_nom_vsync_capped, max_allowed_vblank_nom); + dml_uint_t vblank_nom_max_allowed_capped = (dml_uint_t)dml_min(vblank_nom_vsync_capped, max_allowed_vblank_nom); dml_uint_t vblank_avail = (vblank_nom_max_allowed_capped == 0) ? vblank_nom_default_in_line : vblank_nom_max_allowed_capped; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c index b2fada6c44c3..3939a0d8b835 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c @@ -80,7 +80,7 @@ static inline float dcn_bw_pow(float a, float exp) /*ASSERT(exp == (int)exp);*/ if ((int)exp == 0) return 1; - temp = dcn_bw_pow(a, (int)(exp / 2)); + temp = dcn_bw_pow(a, (float)(exp / 2)); if (((int)exp % 2) == 0) { return temp * temp; } else { @@ -110,7 +110,7 @@ dml_float_t dml_ceil(dml_float_t x, dml_float_t granularity) if (granularity == 0) return 0; //return (dml_float_t) (ceil(x / granularity) * granularity); - return (dml_float_t)dcn_bw_ceil2(x, granularity); + return (dml_float_t)dcn_bw_ceil2((float)x, (float)granularity); } dml_float_t dml_floor(dml_float_t x, dml_float_t granularity) @@ -118,7 +118,7 @@ dml_float_t dml_floor(dml_float_t x, dml_float_t granularity) if (granularity == 0) return 0; //return (dml_float_t) (floor(x / granularity) * granularity); - return (dml_float_t)dcn_bw_floor2(x, granularity); + return (dml_float_t)dcn_bw_floor2((float)x, (float)granularity); } dml_float_t dml_min(dml_float_t x, dml_float_t y) @@ -168,12 +168,12 @@ dml_float_t dml_max5(dml_float_t a, dml_float_t b, dml_float_t c, dml_float_t d, } dml_float_t dml_log(dml_float_t x, dml_float_t base) { - return (dml_float_t) (_log(x) / _log(base)); + return (dml_float_t) (_log((float)x) / _log((float)base)); } dml_float_t dml_log2(dml_float_t x) { - return (dml_float_t) (_log(x) / _log(2)); + return (dml_float_t) (_log((float)x) / _log(2.0f)); } dml_float_t dml_round(dml_float_t val, dml_bool_t bankers_rounding) @@ -184,19 +184,19 @@ dml_float_t dml_round(dml_float_t val, dml_bool_t bankers_rounding) // else { // return round(val); double round_pt = 0.5; - double ceil = dml_ceil(val, 1); - double floor = dml_floor(val, 1); + double ceil = dml_ceil(val, 1.0); + double floor = dml_floor(val, 1.0); if (val - floor >= round_pt) - return ceil; + return (dml_float_t)ceil; else - return floor; + return (dml_float_t)floor; // } } dml_float_t dml_pow(dml_float_t base, int exp) { - return (dml_float_t) dcn_bw_pow(base, exp); + return (dml_float_t) dcn_bw_pow((float)base, (float)exp); } dml_uint_t dml_round_to_multiple(dml_uint_t num, dml_uint_t multiple, dml_bool_t up) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c index 476030193f14..d89fd876975e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c @@ -90,6 +90,8 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf struct pipe_ctx *pipe_ctx, struct dml2_context *dml_ctx) { + const unsigned int min_v_front_porch = (stream->timing.flags.INTERLACE != 0) ? 2 : 1; + unsigned int hblank_start, vblank_start; uint64_t min_hardware_refresh_in_uhz; uint32_t pix_clk_100hz; @@ -97,7 +99,8 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding; timing->v_active = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; timing->h_front_porch = stream->timing.h_front_porch; - timing->v_front_porch = stream->timing.v_front_porch; + timing->v_front_porch = stream->timing.v_front_porch > min_v_front_porch ? + stream->timing.v_front_porch : min_v_front_porch; timing->pixel_clock_khz = stream->timing.pix_clk_100hz / 10; if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0) timing->pixel_clock_khz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz / 10; @@ -116,7 +119,7 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf if (hblank_start < stream->timing.h_addressable) timing->h_blank_end = 0; - vblank_start = stream->timing.v_total - stream->timing.v_front_porch; + vblank_start = timing->v_total - timing->v_front_porch; timing->v_blank_end = vblank_start - stream->timing.v_addressable - stream->timing.v_border_top - stream->timing.v_border_bottom; @@ -848,10 +851,10 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state context->bw_ctx.bw.dcn.clk.socclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.socclk_khz; context->bw_ctx.bw.dcn.clk.subvp_prefetch_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.uclk_khz; context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz; - context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency; - context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency; - context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_efficiency; - context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_period; + context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency; + context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency; + context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_efficiency; + context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period = (int)in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_period; context->bw_ctx.bw.dcn.clk.zstate_support = in_ctx->v21.mode_programming.programming->z8_stutter.supported_in_blank; /*ignore meets_eco since it is not used*/ } diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c index 732de97335fa..835fece1d46a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c @@ -267,7 +267,7 @@ static struct dc_stream_state *dml21_add_phantom_stream(struct dml2_context *dml phantom_stream->dst.height = stream_programming->phantom_stream.descriptor.timing.v_active; phantom_stream->src.y = 0; - phantom_stream->src.height = (double)phantom_stream_descriptor->timing.v_active * (double)main_stream->src.height / (double)main_stream->dst.height; + phantom_stream->src.height = (int)((double)phantom_stream_descriptor->timing.v_active * (double)main_stream->src.height / (double)main_stream->dst.height); phantom_stream->use_dynamic_meta = false; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h index 98b26116cdc1..dff903a103db 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h @@ -19,7 +19,6 @@ enum dml2_project_id { dml2_project_dcn4x_stage1, dml2_project_dcn4x_stage2, dml2_project_dcn4x_stage2_auto_drr_svp, - dml2_project_dcn40, dml2_project_dcn42, }; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c index 6cad99c21139..67e307fa4310 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c @@ -21,7 +21,6 @@ bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance case dml2_project_dcn4x_stage1: result = false; break; - case dml2_project_dcn40: case dml2_project_dcn4x_stage2: case dml2_project_dcn4x_stage2_auto_drr_svp: out->initialize = &core_dcn4_initialize; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c index 39965ff2e111..be0517e10104 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c @@ -33,7 +33,6 @@ bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance out->map_watermarks = &dummy_map_watermarks; result = true; break; - case dml2_project_dcn40: case dml2_project_dcn4x_stage2: out->map_mode_to_soc_dpm = &dpmm_dcn3_map_mode_to_soc_dpm; out->map_watermarks = &dummy_map_watermarks; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.c index 3eaeff39ee79..ef8b75fed9a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.c @@ -22,7 +22,7 @@ static bool build_min_clk_table_coarse_grained(const struct dml2_soc_bb *soc_bb, min_table->dram_bw_table.entries[i].pre_derate_dram_bw_kbps = uclk_to_dram_bw_kbps(soc_bb->clk_table.uclk.clk_values_khz[i], &soc_bb->clk_table.dram_config, soc_bb->clk_table.wck_ratio.clk_values_khz[i]); min_table->dram_bw_table.entries[i].min_uclk_khz = soc_bb->clk_table.uclk.clk_values_khz[i]; - } else { + } else if (soc_bb->clk_table.uclk.num_clk_values > 0) { min_table->dram_bw_table.entries[i].pre_derate_dram_bw_kbps = min_table->dram_bw_table.entries[soc_bb->clk_table.uclk.num_clk_values - 1].pre_derate_dram_bw_kbps; min_table->dram_bw_table.entries[i].min_uclk_khz = soc_bb->clk_table.uclk.clk_values_khz[soc_bb->clk_table.uclk.num_clk_values - 1]; } diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c index fb0b0ac547c7..270283332cc1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c @@ -27,7 +27,6 @@ bool dml2_mcg_create(enum dml2_project_id project_id, struct dml2_mcg_instance * out->build_min_clock_table = &dummy_build_min_clock_table; result = true; break; - case dml2_project_dcn40: case dml2_project_dcn4x_stage2: case dml2_project_dcn4x_stage2_auto_drr_svp: out->build_min_clock_table = &mcg_dcn4_build_min_clock_table; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c index 83802aac11cd..af2ba7d08a61 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c @@ -3,8 +3,8 @@ // Copyright 2024 Advanced Micro Devices, Inc. #include "dml2_pmo_factory.h" -#include "dml2_pmo_dcn3.h" #include "dml2_pmo_dcn4_fams2.h" +#include "dml2_pmo_dcn3.h" #include "dml2_external_lib_deps.h" static bool dummy_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in_out) @@ -40,7 +40,6 @@ bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance * out->optimize_dcc_mcache = pmo_dcn4_fams2_optimize_dcc_mcache; result = true; break; - case dml2_project_dcn40: case dml2_project_dcn4x_stage2: out->initialize = pmo_dcn3_initialize; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c index a6c5031f69c1..04860b6790df 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c @@ -17,7 +17,6 @@ bool dml2_initialize_instance(struct dml2_initialize_instance_in_out *in_out) case dml2_project_dcn4x_stage1: case dml2_project_dcn4x_stage2: case dml2_project_dcn4x_stage2_auto_drr_svp: - case dml2_project_dcn40: case dml2_project_dcn42: return dml2_top_soc15_initialize_instance(in_out); case dml2_project_invalid: diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.h deleted file mode 100644 index 14d0ae03dce6..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.h +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: MIT -// -// Copyright 2024 Advanced Micro Devices, Inc. - -#ifndef __DML2_TOP_LEGACY_H__ -#define __DML2_TOP_LEGACY_H__ -#include "dml2_internal_shared_types.h" -bool dml2_top_legacy_initialize_instance(struct dml2_initialize_instance_in_out *in_out); -#endif /* __DML2_TOP_LEGACY_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c index 9bbe4e058be7..4543a60a0683 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c @@ -244,9 +244,9 @@ static bool assign_subvp_pipe(struct dml2_context *ctx, struct dc_state *context continue; // Round up - refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + + refresh_rate = (unsigned int)((pipe->stream->timing.pix_clk_100hz * 100 + pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) - / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); + / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total)); /* SubVP pipe candidate requirements: * - Refresh rate < 120hz * - Not able to switch in vactive naturally (switching in active means the @@ -264,8 +264,8 @@ static bool assign_subvp_pipe(struct dml2_context *ctx, struct dc_state *context pipe = &context->res_ctx.pipe_ctx[i]; if (num_pipes <= free_pipes) { struct dc_stream_state *stream = pipe->stream; - unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total / - (double)(stream->timing.pix_clk_100hz * 100)) * 1000000; + unsigned int frame_us = (unsigned int)((stream->timing.v_total * stream->timing.h_total / + (double)(stream->timing.pix_clk_100hz * 100)) * 1000000); if (frame_us > max_frame_time && !stream->ignore_msa_timing_param) { *index = i; max_frame_time = frame_us; @@ -382,8 +382,8 @@ static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *c phantom->timing.v_addressable; // Round up when calculating microschedule time (+ 1 at the end) - time_us = (microschedule_lines * phantom->timing.h_total) / - (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 + + time_us = (uint32_t)((microschedule_lines * phantom->timing.h_total) / + (double)(phantom->timing.pix_clk_100hz * 100) * 1000000) + ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us + ctx->config.svp_pstate.subvp_fw_processing_delay_us + 1; if (time_us > max_microschedule_us) @@ -402,16 +402,16 @@ static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *c if (index < 2 || !subvp_pipes[0] || !subvp_pipes[1]) return false; - vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / - (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; - vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / - (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; - vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) * + vactive1_us = (int32_t)(((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / + (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000); + vactive2_us = (int32_t)(((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / + (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000); + vblank1_us = (int32_t)(((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) * subvp_pipes[0]->stream->timing.h_total) / - (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; - vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) * + (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100) * 1000000); + vblank2_us = (int32_t)(((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) * subvp_pipes[1]->stream->timing.h_total) / - (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; + (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100) * 1000000); if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us && (vactive2_us - vblank1_us) / 2 > max_microschedule_us) @@ -445,13 +445,13 @@ bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context struct dc_crtc_timing *main_timing = NULL; struct dc_crtc_timing *phantom_timing = NULL; struct dc_stream_state *phantom_stream; - int16_t prefetch_us = 0; - int16_t mall_region_us = 0; - int16_t drr_frame_us = 0; // nominal frame time - int16_t subvp_active_us = 0; - int16_t stretched_drr_us = 0; - int16_t drr_stretched_vblank_us = 0; - int16_t max_vblank_mallregion = 0; + int32_t prefetch_us = 0; + int32_t mall_region_us = 0; + int32_t drr_frame_us = 0; // nominal frame time + int32_t subvp_active_us = 0; + int32_t stretched_drr_us = 0; + int32_t drr_stretched_vblank_us = 0; + int32_t max_vblank_mallregion = 0; // Find SubVP pipe for (i = 0; i < ctx->config.dcn_pipe_count; i++) { @@ -475,19 +475,19 @@ bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context phantom_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe->stream); main_timing = &pipe->stream->timing; phantom_timing = &phantom_stream->timing; - prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / + prefetch_us = (int32_t)((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + - ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us; - subvp_active_us = main_timing->v_addressable * main_timing->h_total / - (double)(main_timing->pix_clk_100hz * 100) * 1000000; - drr_frame_us = drr_timing->v_total * drr_timing->h_total / - (double)(drr_timing->pix_clk_100hz * 100) * 1000000; + ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us); + subvp_active_us = (int32_t)(main_timing->v_addressable * main_timing->h_total / + (double)(main_timing->pix_clk_100hz * 100) * 1000000); + drr_frame_us = (int32_t)(drr_timing->v_total * drr_timing->h_total / + (double)(drr_timing->pix_clk_100hz * 100) * 1000000); // P-State allow width and FW delays already included phantom_timing->v_addressable - mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / - (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; + mall_region_us = (int32_t)(phantom_timing->v_addressable * phantom_timing->h_total / + (double)(phantom_timing->pix_clk_100hz * 100) * 1000000); stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; - drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / - (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us); + drr_stretched_vblank_us = (int32_t)((drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / + (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us)); max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us; /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the @@ -526,12 +526,12 @@ static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state * bool schedulable = false; uint32_t i = 0; uint8_t vblank_index = 0; - uint16_t prefetch_us = 0; - uint16_t mall_region_us = 0; - uint16_t vblank_frame_us = 0; - uint16_t subvp_active_us = 0; - uint16_t vblank_blank_us = 0; - uint16_t max_vblank_mallregion = 0; + uint32_t prefetch_us = 0; + uint32_t mall_region_us = 0; + uint32_t vblank_frame_us = 0; + uint32_t subvp_active_us = 0; + uint32_t vblank_blank_us = 0; + uint32_t max_vblank_mallregion = 0; struct dc_crtc_timing *main_timing = NULL; struct dc_crtc_timing *phantom_timing = NULL; struct dc_crtc_timing *vblank_timing = NULL; @@ -581,24 +581,27 @@ static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state * vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing; // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe // Also include the prefetch end to mallstart delay time - prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / + prefetch_us = (uint32_t)((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + - ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us; + ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us); // P-State allow width and FW delays already included phantom_timing->v_addressable - mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / - (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; - vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total / - (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; - vblank_blank_us = (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total / - (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; - subvp_active_us = main_timing->v_addressable * main_timing->h_total / - (double)(main_timing->pix_clk_100hz * 100) * 1000000; + mall_region_us = (uint32_t)(phantom_timing->v_addressable * phantom_timing->h_total / + (double)(phantom_timing->pix_clk_100hz * 100) * 1000000); + vblank_frame_us = (uint32_t)(vblank_timing->v_total * vblank_timing->h_total / + (double)(vblank_timing->pix_clk_100hz * 100) * 1000000); + vblank_blank_us = (uint32_t)((vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total / + (double)(vblank_timing->pix_clk_100hz * 100) * 1000000); + subvp_active_us = (uint32_t)(main_timing->v_addressable * main_timing->h_total / + (double)(main_timing->pix_clk_100hz * 100) * 1000000); max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us; + const uint64_t required_us = (uint64_t)prefetch_us + + (uint64_t)vblank_frame_us + + (uint64_t)max_vblank_mallregion; // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, // and the max of (VBLANK blanking time, MALL region) // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0) - if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0) + if ((uint64_t)subvp_active_us > required_us) schedulable = true; } return schedulable; @@ -694,10 +697,10 @@ static void set_phantom_stream_timing(struct dml2_context *ctx, struct dc_state } // Calculate lines required for pstate allow width and FW processing delays - pstate_width_fw_delay_lines = ((double)(ctx->config.svp_pstate.subvp_fw_processing_delay_us + + pstate_width_fw_delay_lines = (uint32_t)(((double)(ctx->config.svp_pstate.subvp_fw_processing_delay_us + ctx->config.svp_pstate.subvp_pstate_allow_width_us) / 1000000) * (ref_pipe->stream->timing.pix_clk_100hz * 100) / - (double)ref_pipe->stream->timing.h_total; + (double)ref_pipe->stream->timing.h_total); // DML calculation for MALL region doesn't take into account FW delay // and required pstate allow width for multi-display cases @@ -712,7 +715,7 @@ static void set_phantom_stream_timing(struct dml2_context *ctx, struct dc_state fp_and_sync_width_time = (phantom_stream->timing.v_front_porch + phantom_stream->timing.v_sync_width) * line_time; if ((svp_vstartup * line_time) + fp_and_sync_width_time > cvt_rb_vblank_max) { - svp_vstartup = (cvt_rb_vblank_max - fp_and_sync_width_time) / line_time; + svp_vstartup = (unsigned int)((cvt_rb_vblank_max - fp_and_sync_width_time) / line_time); } // For backporch of phantom pipe, use vstartup of the main pipe diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c index ef693f608d59..ab2964811c5b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c @@ -123,9 +123,9 @@ int dml2_policy_build_synthetic_soc_states(struct dml2_policy_build_synthetic_so struct dml2_policy_build_synthetic_soc_states_params *p) { int i, j; - unsigned int min_fclk_mhz = p->in_states->state_array[0].fabricclk_mhz; - unsigned int min_dcfclk_mhz = p->in_states->state_array[0].dcfclk_mhz; - unsigned int min_socclk_mhz = p->in_states->state_array[0].socclk_mhz; + unsigned int min_fclk_mhz = (unsigned int)p->in_states->state_array[0].fabricclk_mhz; + unsigned int min_dcfclk_mhz = (unsigned int)p->in_states->state_array[0].dcfclk_mhz; + unsigned int min_socclk_mhz = (unsigned int)p->in_states->state_array[0].socclk_mhz; int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c index 8e0997441ee0..0d8ff236c6d0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c @@ -508,11 +508,11 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc, /* DCFCLK stas values are project specific */ if ((dml2->v20.dml_core_ctx.project == dml_project_dcn32) || (dml2->v20.dml_core_ctx.project == dml_project_dcn321)) { - p->dcfclk_stas_mhz[0] = p->in_states->state_array[0].dcfclk_mhz; + p->dcfclk_stas_mhz[0] = (int)p->in_states->state_array[0].dcfclk_mhz; p->dcfclk_stas_mhz[1] = 615; p->dcfclk_stas_mhz[2] = 906; p->dcfclk_stas_mhz[3] = 1324; - p->dcfclk_stas_mhz[4] = p->in_states->state_array[1].dcfclk_mhz; + p->dcfclk_stas_mhz[4] = (int)p->in_states->state_array[1].dcfclk_mhz; } else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 && dml2->v20.dml_core_ctx.project != dml_project_dcn36 && dml2->v20.dml_core_ctx.project != dml_project_dcn351) { diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c index 86567e232415..1bc81e26a11f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c @@ -333,7 +333,7 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont } context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb; - context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000; + context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = (int)(dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000); if (context->bw_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz) context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz; @@ -362,10 +362,10 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; - context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz - * 1000; - context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz - * 1000; + context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = (int)(in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz + * 1000); + context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = (int)(in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz + * 1000); if (dc->config.forced_clocks || dc->debug.max_disp_clk) { context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; @@ -375,18 +375,18 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont void dml2_extract_watermark_set(struct dcn_watermarks *watermark, struct display_mode_lib_st *dml_core_ctx) { - watermark->urgent_ns = dml_get_wm_urgent(dml_core_ctx) * 1000; - watermark->cstate_pstate.cstate_enter_plus_exit_ns = dml_get_wm_stutter_enter_exit(dml_core_ctx) * 1000; - watermark->cstate_pstate.cstate_exit_ns = dml_get_wm_stutter_exit(dml_core_ctx) * 1000; - watermark->cstate_pstate.pstate_change_ns = dml_get_wm_dram_clock_change(dml_core_ctx) * 1000; - watermark->pte_meta_urgent_ns = dml_get_wm_memory_trip(dml_core_ctx) * 1000; - watermark->frac_urg_bw_nom = dml_get_fraction_of_urgent_bandwidth(dml_core_ctx) * 1000; - watermark->frac_urg_bw_flip = dml_get_fraction_of_urgent_bandwidth_imm_flip(dml_core_ctx) * 1000; - watermark->urgent_latency_ns = dml_get_urgent_latency(dml_core_ctx) * 1000; - watermark->cstate_pstate.fclk_pstate_change_ns = dml_get_wm_fclk_change(dml_core_ctx) * 1000; - watermark->usr_retraining_ns = dml_get_wm_usr_retraining(dml_core_ctx) * 1000; - watermark->cstate_pstate.cstate_enter_plus_exit_z8_ns = dml_get_wm_z8_stutter_enter_exit(dml_core_ctx) * 1000; - watermark->cstate_pstate.cstate_exit_z8_ns = dml_get_wm_z8_stutter(dml_core_ctx) * 1000; + watermark->urgent_ns = (uint32_t)(dml_get_wm_urgent(dml_core_ctx) * 1000); + watermark->cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(dml_get_wm_stutter_enter_exit(dml_core_ctx) * 1000); + watermark->cstate_pstate.cstate_exit_ns = (uint32_t)(dml_get_wm_stutter_exit(dml_core_ctx) * 1000); + watermark->cstate_pstate.pstate_change_ns = (uint32_t)(dml_get_wm_dram_clock_change(dml_core_ctx) * 1000); + watermark->pte_meta_urgent_ns = (uint32_t)(dml_get_wm_memory_trip(dml_core_ctx) * 1000); + watermark->frac_urg_bw_nom = (uint32_t)(dml_get_fraction_of_urgent_bandwidth(dml_core_ctx) * 1000); + watermark->frac_urg_bw_flip = (uint32_t)(dml_get_fraction_of_urgent_bandwidth_imm_flip(dml_core_ctx) * 1000); + watermark->urgent_latency_ns = (uint32_t)(dml_get_urgent_latency(dml_core_ctx) * 1000); + watermark->cstate_pstate.fclk_pstate_change_ns = (uint32_t)(dml_get_wm_fclk_change(dml_core_ctx) * 1000); + watermark->usr_retraining_ns = (uint32_t)(dml_get_wm_usr_retraining(dml_core_ctx) * 1000); + watermark->cstate_pstate.cstate_enter_plus_exit_z8_ns = (uint32_t)(dml_get_wm_z8_stutter_enter_exit(dml_core_ctx) * 1000); + watermark->cstate_pstate.cstate_exit_z8_ns = (uint32_t)(dml_get_wm_z8_stutter(dml_core_ctx) * 1000); } unsigned int dml2_calc_max_scaled_time( @@ -434,9 +434,9 @@ void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib for (j = 0 ; j < 4; j++) { /*current dml only has one set of watermark, need to follow up*/ bw_writeback->mcif_wb_arb[i].cli_watermark[j] = - dml_get_wm_writeback_urgent(dml_core_ctx) * 1000; + (unsigned int)(dml_get_wm_writeback_urgent(dml_core_ctx) * 1000); bw_writeback->mcif_wb_arb[i].pstate_watermark[j] = - dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000; + (unsigned int)(dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000); } if (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk != 0) { /* time_per_pixel should be in u6.6 format */ @@ -450,7 +450,7 @@ void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib wbif_mode, wb_arb_params->cli_watermark[0]); /*not required any more*/ bw_writeback->mcif_wb_arb[i].dram_speed_change_duration = - dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000; + (unsigned int)(dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000); } } diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c index 2bdd063cc1e1..2b8afe46ff1c 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c @@ -824,7 +824,7 @@ void dpp1_program_input_lut( struct dpp *dpp_base, const struct dc_gamma *gamma) { - int i; + unsigned int i; struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); bool rama_occupied = false; uint32_t ram_num; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c index 0d2c9fcd3362..b9adf8433b36 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c @@ -256,7 +256,7 @@ static void dpp1_dscl_set_scaler_filter( for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) { for (pair = 0; pair < tap_pairs; pair++) { even_coef = filter[phase * taps + 2 * pair]; - if ((pair * 2 + 1) < taps) + if ((uint32_t)(pair * 2 + 1) < taps) odd_coef = filter[phase * taps + 2 * pair + 1]; else odd_coef = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c index e7880fc61b4a..d24f02d201f4 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c @@ -517,11 +517,16 @@ bool dpp3_get_optimal_number_of_taps( else if (max_taps_c < min_taps_c) return false; - if (scl_data->taps.v_taps > max_taps_y) - scl_data->taps.v_taps = max_taps_y; + { + uint32_t max_supported_taps_y = (uint32_t)max_taps_y; + uint32_t max_supported_taps_c = (uint32_t)max_taps_c; - if (scl_data->taps.v_taps_c > max_taps_c) - scl_data->taps.v_taps_c = max_taps_c; + if (scl_data->taps.v_taps > max_supported_taps_y) + scl_data->taps.v_taps = max_supported_taps_y; + + if (scl_data->taps.v_taps_c > max_supported_taps_c) + scl_data->taps.v_taps_c = max_supported_taps_c; + } if (!dpp->ctx->dc->debug.always_scale) { if (IDENTITY_RATIO(scl_data->ratios.horz)) { diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c index 4f3b48ed8679..340111e3deac 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c @@ -176,7 +176,7 @@ static void dpp401_program_cursor_csc( struct color_matrices_reg cur_matrix_regs; unsigned int i; const uint16_t *regval = NULL; - int arr_size = sizeof(dpp_input_csc_matrix) / sizeof(struct dpp_input_csc_matrix); + unsigned int arr_size = sizeof(dpp_input_csc_matrix) / sizeof(struct dpp_input_csc_matrix); if (color_space < COLOR_SPACE_YCBCR601) { REG_SET(CUR0_MATRIX_MODE, 0, CUR0_MATRIX_MODE, CUR_MATRIX_BYPASS); diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c index 8b7e55e337d3..df3c21ef57a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c @@ -253,7 +253,7 @@ static void dpp401_dscl_set_scaler_filter( for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) { for (pair = 0; pair < tap_pairs; pair++) { even_coef = filter[phase * taps + 2 * pair]; - if ((pair * 2 + 1) < taps) + if ((uint32_t)(pair * 2 + 1) < taps) odd_coef = filter[phase * taps + 2 * pair + 1]; else odd_coef = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c index c126fb9d5bfa..f60e084068c8 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c @@ -269,10 +269,10 @@ static void dpp42_dpp_setup( tbl_entry.color_space = input_color_space; - if (color_space >= COLOR_SPACE_YCBCR601) - select = INPUT_CSC_SELECT_ICSC; - else + if (dpp3_should_bypass_post_csc_for_colorspace(color_space)) select = INPUT_CSC_SELECT_BYPASS; + else + select = INPUT_CSC_SELECT_ICSC; dpp3_program_post_csc(dpp_base, color_space, select, &tbl_entry); @@ -280,6 +280,14 @@ static void dpp42_dpp_setup( dpp3_program_post_csc(dpp_base, color_space, select, NULL); } } +static void dcn42_dpp_force_disable_cursor(struct dpp *dpp_base) +{ + struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); + + /* Force disable cursor */ + REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, 0); + dpp_base->pos.cur0_ctl.bits.cur0_enable = 0; +} static struct dpp_funcs dcn42_dpp_funcs = { .dpp_program_gamcor_lut = dpp3_program_gamcor_lut, @@ -302,6 +310,7 @@ static struct dpp_funcs dcn42_dpp_funcs = { .dpp_cm_hist_control = dpp42_dpp_cm_hist_control, .dpp_cm_hist_read = dpp42_dpp_cm_hist_read, .dpp_read_reg_state = dpp30_read_reg_state, + .dpp_force_disable_cursor = dcn42_dpp_force_disable_cursor, }; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 8dfb6dd14eb2..8dcdda46ee1e 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -858,19 +858,20 @@ static bool decide_dsc_target_bpp_x16( int *target_bpp_x16) { struct dc_dsc_bw_range range; + uint32_t target_bandwidth_kbps_u = (uint32_t)target_bandwidth_kbps; *target_bpp_x16 = 0; if (decide_dsc_bandwidth_range(policy->min_target_bpp * 16, policy->max_target_bpp * 16, num_slices_h, dsc_common_caps, timing, link_encoding, &range)) { - if (target_bandwidth_kbps >= range.stream_kbps) { + if (target_bandwidth_kbps_u >= range.stream_kbps) { if (policy->enable_dsc_when_not_needed || options->force_dsc_when_not_needed) /* enable max bpp even dsc is not needed */ *target_bpp_x16 = range.max_target_bpp_x16; - } else if (target_bandwidth_kbps >= range.max_kbps) { + } else if (target_bandwidth_kbps_u >= range.max_kbps) { /* use max target bpp allowed */ *target_bpp_x16 = range.max_target_bpp_x16; - } else if (target_bandwidth_kbps >= range.min_kbps) { + } else if (target_bandwidth_kbps_u >= range.min_kbps) { /* use target bpp that can take entire target bandwidth */ *target_bpp_x16 = compute_bpp_x16_from_target_bandwidth( target_bandwidth_kbps, timing, num_slices_h, @@ -1053,10 +1054,11 @@ static bool setup_dsc_config( int max_slices_h = 0; int num_slices_h = 0; int pic_width; + uint32_t pic_width_u; int slice_width; int target_bpp; int sink_per_slice_throughput_mps; - int branch_max_throughput_mps = 0; + uint32_t branch_max_throughput_mps = 0; bool is_dsc_possible = false; int pic_height; int slice_height; @@ -1066,12 +1068,13 @@ static bool setup_dsc_config( dc_dsc_get_policy_for_timing(timing, options->max_target_bpp_limit_override_x16, &policy, link_encoding); pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right; + pic_width_u = (uint32_t)pic_width; pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; if (!dsc_sink_caps->is_dsc_supported) goto done; - if (dsc_sink_caps->branch_max_line_width && dsc_sink_caps->branch_max_line_width < pic_width) + if (dsc_sink_caps->branch_max_line_width && dsc_sink_caps->branch_max_line_width < pic_width_u) goto done; // Intersect decoder with encoder DSC caps and validate DSC settings diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index 6e1e759462bf..7ee31cae5959 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -168,8 +168,9 @@ bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct ds { struct dsc_optc_config dsc_optc_cfg; struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); + uint32_t max_image_width = (uint32_t)dsc20->max_image_width; - if (dsc_cfg->pic_width > dsc20->max_image_width) + if (dsc_cfg->pic_width > max_image_width) return false; return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); @@ -405,20 +406,20 @@ bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple); dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v; - dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor; - dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width; - dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height; + dsc_reg_vals->pps.dsc_version_minor = (u8)dsc_cfg->dc_dsc_cfg.version_minor; + dsc_reg_vals->pps.pic_width = (u16)dsc_cfg->pic_width; + dsc_reg_vals->pps.pic_height = (u16)dsc_cfg->pic_height; dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth); dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable; - dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth; + dsc_reg_vals->pps.line_buf_depth = (u8)dsc_cfg->dc_dsc_cfg.linebuf_depth; dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1; dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0; // Need to find the ceiling value for the slice width - dsc_reg_vals->pps.slice_width = (dsc_cfg->pic_width + dsc_cfg->dsc_padding + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slices_h; + dsc_reg_vals->pps.slice_width = (u16)((dsc_cfg->pic_width + dsc_cfg->dsc_padding + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slices_h); // TODO: in addition to validating slice height (pic height must be divisible by slice height), // see what happens when the same condition doesn't apply for slice_width/pic_width. - dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; + dsc_reg_vals->pps.slice_height = (u16)(dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v); ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { @@ -428,9 +429,9 @@ bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1; if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) - dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32; + dsc_reg_vals->pps.bits_per_pixel = (u16)dsc_reg_vals->bpp_x32; else - dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1; + dsc_reg_vals->pps.bits_per_pixel = (u16)(dsc_reg_vals->bpp_x32 >> 1); dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c index 41c3b814b6bd..363e83ad21db 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c @@ -119,8 +119,9 @@ bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct { struct dsc_optc_config dsc_optc_cfg; struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); + uint32_t max_image_width = (uint32_t)dsc401->max_image_width; - if (dsc_cfg->pic_width > dsc401->max_image_width) + if (dsc_cfg->pic_width > max_image_width) return false; return dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, &dsc_optc_cfg); diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c index 59864130cf83..6c07d9a87bfe 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c @@ -72,27 +72,27 @@ static void copy_rc_to_cfg(struct drm_dsc_config *dsc_cfg, const struct rc_param { int i; - dsc_cfg->rc_quant_incr_limit0 = rc->rc_quant_incr_limit0; - dsc_cfg->rc_quant_incr_limit1 = rc->rc_quant_incr_limit1; - dsc_cfg->initial_offset = rc->initial_fullness_offset; - dsc_cfg->initial_xmit_delay = rc->initial_xmit_delay; - dsc_cfg->first_line_bpg_offset = rc->first_line_bpg_offset; - dsc_cfg->second_line_bpg_offset = rc->second_line_bpg_offset; - dsc_cfg->flatness_min_qp = rc->flatness_min_qp; - dsc_cfg->flatness_max_qp = rc->flatness_max_qp; + dsc_cfg->rc_quant_incr_limit0 = (u8)rc->rc_quant_incr_limit0; + dsc_cfg->rc_quant_incr_limit1 = (u8)rc->rc_quant_incr_limit1; + dsc_cfg->initial_offset = (u16)rc->initial_fullness_offset; + dsc_cfg->initial_xmit_delay = (u16)rc->initial_xmit_delay; + dsc_cfg->first_line_bpg_offset = (u8)rc->first_line_bpg_offset; + dsc_cfg->second_line_bpg_offset = (u8)rc->second_line_bpg_offset; + dsc_cfg->flatness_min_qp = (u8)rc->flatness_min_qp; + dsc_cfg->flatness_max_qp = (u8)rc->flatness_max_qp; for (i = 0; i < QP_SET_SIZE; ++i) { - dsc_cfg->rc_range_params[i].range_min_qp = rc->qp_min[i]; - dsc_cfg->rc_range_params[i].range_max_qp = rc->qp_max[i]; + dsc_cfg->rc_range_params[i].range_min_qp = (u8)rc->qp_min[i]; + dsc_cfg->rc_range_params[i].range_max_qp = (u8)rc->qp_max[i]; /* Truncate 8-bit signed value to 6-bit signed value */ dsc_cfg->rc_range_params[i].range_bpg_offset = 0x3f & rc->ofs[i]; } - dsc_cfg->rc_model_size = rc->rc_model_size; - dsc_cfg->rc_edge_factor = rc->rc_edge_factor; - dsc_cfg->rc_tgt_offset_high = rc->rc_tgt_offset_hi; - dsc_cfg->rc_tgt_offset_low = rc->rc_tgt_offset_lo; + dsc_cfg->rc_model_size = (u16)rc->rc_model_size; + dsc_cfg->rc_edge_factor = (u8)rc->rc_edge_factor; + dsc_cfg->rc_tgt_offset_high = (u8)rc->rc_tgt_offset_hi; + dsc_cfg->rc_tgt_offset_low = (u8)rc->rc_tgt_offset_lo; for (i = 0; i < QP_SET_SIZE - 1; ++i) - dsc_cfg->rc_buf_thresh[i] = rc->rc_buf_thresh[i]; + dsc_cfg->rc_buf_thresh[i] = (u16)rc->rc_buf_thresh[i]; } int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, @@ -103,7 +103,8 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct drm_dsc_config dsc_cfg; dsc_params->pps = *pps; - dsc_params->pps.initial_scale_value = 8 * rc->rc_model_size / (rc->rc_model_size - rc->initial_fullness_offset); + dsc_params->pps.initial_scale_value = (u8)(8 * rc->rc_model_size / + (rc->rc_model_size - rc->initial_fullness_offset)); copy_pps_fields(&dsc_cfg, &dsc_params->pps); copy_rc_to_cfg(&dsc_cfg, rc); diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c index a2c46350e44e..95f8b7c7d657 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c @@ -646,6 +646,9 @@ enum gpio_result dal_ddc_change_mode( enum gpio_ddc_line dal_ddc_get_line( const struct ddc *ddc) { + if (!ddc) + return GPIO_DDC_LINE_UNKNOWN; + return (enum gpio_ddc_line)dal_gpio_get_enum(ddc->pin_data); } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c index 86d60986d669..a76884a069e8 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c @@ -36,7 +36,7 @@ #undef FN #define FN(reg_name, field_name) \ - ddc->shifts->field_name, ddc->masks->field_name + gpio_reg_shift(ddc->shifts->field_name), ddc->masks->field_name #define CTX \ ddc->base.base.ctx diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c index 7f137cb96895..5db83920e367 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c @@ -37,7 +37,7 @@ #undef FN #define FN(reg_name, field_name) \ - generic->shifts->field_name, generic->masks->field_name + gpio_reg_shift(generic->shifts->field_name), generic->masks->field_name #define CTX \ generic->base.base.ctx diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c index f0d400972897..07651dc7e205 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c @@ -32,7 +32,7 @@ #undef FN #define FN(reg_name, field_name) \ - gpio->regs->field_name ## _shift, gpio->regs->field_name ## _mask + gpio_reg_shift(gpio->regs->field_name ## _shift), gpio->regs->field_name ## _mask #define CTX \ gpio->base.ctx diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h index bca0cef18ff9..5b551068cdd6 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h @@ -141,4 +141,13 @@ enum gpio_result dal_hw_gpio_change_mode( void dal_hw_gpio_close( struct hw_gpio_pin *ptr); +/* + * Shared helper used by all GPIO register helpers that pass a field shift + * (stored as uint32_t) into register functions that expect uint8_t. + */ +static inline uint8_t gpio_reg_shift(uint32_t shift) +{ + return (uint8_t)shift; +} + #endif diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c index 79e107904e21..2cb960e517ae 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c @@ -35,7 +35,7 @@ #undef FN #define FN(reg_name, field_name) \ - hpd->shifts->field_name, hpd->masks->field_name + gpio_reg_shift(hpd->shifts->field_name), hpd->masks->field_name #define CTX \ hpd->base.base.ctx diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c index 92ed130aeaec..79d6ab8ed71c 100644 --- a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c @@ -468,7 +468,7 @@ static void dcn31_hpo_dp_stream_enc_update_dp_info_packets( &info_frame->spd, true); - if (info_frame->hdrsmd.valid) + if (info_frame->hdrsmd.valid && !info_frame->firmware_controlled_hdr_info_packet) enc->vpg->funcs->update_generic_info_packet( enc->vpg, 3, /* packetIndex */ diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c index 97ef8281a476..d683d0740c13 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c @@ -638,27 +638,27 @@ void hubbub1_update_dchub( SDPIF_FB_BASE, 0x0FFFF); REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + SDPIF_AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22)); REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + SDPIF_AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22)); REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 22); + SDPIF_AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr + + dh_data->zfb_size_in_byte - 1) >> 22)); break; case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + SDPIF_AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22)); REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + SDPIF_AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22)); REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 22); + SDPIF_AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr + + dh_data->zfb_size_in_byte - 1) >> 22)); break; case FRAME_BUFFER_MODE_LOCAL_ONLY: /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c index 5c6f7ddafd6b..053a08b6d3a3 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c @@ -398,17 +398,17 @@ int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub, struct dcn_vmid_page_table_config phys_config; REG_SET(DCN_VM_FB_LOCATION_BASE, 0, - FB_BASE, pa_config->system_aperture.fb_base >> 24); + FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base)); REG_SET(DCN_VM_FB_LOCATION_TOP, 0, - FB_TOP, pa_config->system_aperture.fb_top >> 24); + FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top)); REG_SET(DCN_VM_FB_OFFSET, 0, - FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); + FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset)); REG_SET(DCN_VM_AGP_BOT, 0, - AGP_BOT, pa_config->system_aperture.agp_bot >> 24); + AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot)); REG_SET(DCN_VM_AGP_TOP, 0, - AGP_TOP, pa_config->system_aperture.agp_top >> 24); + AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top)); REG_SET(DCN_VM_AGP_BASE, 0, - AGP_BASE, pa_config->system_aperture.agp_base >> 24); + AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base)); REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, (pa_config->page_table_default_page_addr >> 44) & 0xF); @@ -447,36 +447,36 @@ void hubbub2_update_dchub(struct hubbub *hubbub, /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ REG_UPDATE(DCN_VM_AGP_BASE, - AGP_BASE, dh_data->zfb_phys_addr_base >> 24); + AGP_BASE, ADDR_HI24(dh_data->zfb_phys_addr_base)); /*This field defines the bottom range of the AGP aperture and represents the 24*/ /*MSBs, bits [47:24] of the 48 address bits*/ REG_UPDATE(DCN_VM_AGP_BOT, - AGP_BOT, dh_data->zfb_mc_base_addr >> 24); + AGP_BOT, ADDR_HI24(dh_data->zfb_mc_base_addr)); /*This field defines the top range of the AGP aperture and represents the 24*/ /*MSBs, bits [47:24] of the 48 address bits*/ REG_UPDATE(DCN_VM_AGP_TOP, - AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 24); + AGP_TOP, ADDR_HI24(dh_data->zfb_mc_base_addr + + dh_data->zfb_size_in_byte - 1)); break; case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ REG_UPDATE(DCN_VM_AGP_BASE, - AGP_BASE, dh_data->zfb_phys_addr_base >> 24); + AGP_BASE, ADDR_HI24(dh_data->zfb_phys_addr_base)); /*This field defines the bottom range of the AGP aperture and represents the 24*/ /*MSBs, bits [47:24] of the 48 address bits*/ REG_UPDATE(DCN_VM_AGP_BOT, - AGP_BOT, dh_data->zfb_mc_base_addr >> 24); + AGP_BOT, ADDR_HI24(dh_data->zfb_mc_base_addr)); /*This field defines the top range of the AGP aperture and represents the 24*/ /*MSBs, bits [47:24] of the 48 address bits*/ REG_UPDATE(DCN_VM_AGP_TOP, - AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 24); + AGP_TOP, ADDR_HI24(dh_data->zfb_mc_base_addr + + dh_data->zfb_size_in_byte - 1)); break; case FRAME_BUFFER_MODE_LOCAL_ONLY: /*Should not touch FB LOCATION (should be done by VBIOS)*/ diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h index 46d8f5c70750..6223dfaee270 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h @@ -141,4 +141,7 @@ void hubbub2_wm_read_state(struct hubbub *hubbub, void hubbub2_read_state(struct hubbub *hubbub, struct dcn_hubbub_state *hubbub_state); +/* Extract bits [47:24] of a physical address for hardware register fields */ +#define ADDR_HI24(a) ((uint32_t)((uint64_t)(a) >> 24)) + #endif diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c index e4496ad203b2..d790d6ee359a 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c @@ -111,17 +111,17 @@ int hubbub21_init_dchub(struct hubbub *hubbub, struct dcn_vmid_page_table_config phys_config; REG_SET(DCN_VM_FB_LOCATION_BASE, 0, - FB_BASE, pa_config->system_aperture.fb_base >> 24); + FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base)); REG_SET(DCN_VM_FB_LOCATION_TOP, 0, - FB_TOP, pa_config->system_aperture.fb_top >> 24); + FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top)); REG_SET(DCN_VM_FB_OFFSET, 0, - FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); + FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset)); REG_SET(DCN_VM_AGP_BOT, 0, - AGP_BOT, pa_config->system_aperture.agp_bot >> 24); + AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot)); REG_SET(DCN_VM_AGP_TOP, 0, - AGP_TOP, pa_config->system_aperture.agp_top >> 24); + AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top)); REG_SET(DCN_VM_AGP_BASE, 0, - AGP_BASE, pa_config->system_aperture.agp_base >> 24); + AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base)); if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) { phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12; diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c index 181a93dc46e6..6a7c1bee5747 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c @@ -68,17 +68,17 @@ int hubbub3_init_dchub_sys_ctx(struct hubbub *hubbub, struct dcn_vmid_page_table_config phys_config; REG_SET(DCN_VM_FB_LOCATION_BASE, 0, - FB_BASE, pa_config->system_aperture.fb_base >> 24); + FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base)); REG_SET(DCN_VM_FB_LOCATION_TOP, 0, - FB_TOP, pa_config->system_aperture.fb_top >> 24); + FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top)); REG_SET(DCN_VM_FB_OFFSET, 0, - FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); + FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset)); REG_SET(DCN_VM_AGP_BOT, 0, - AGP_BOT, pa_config->system_aperture.agp_bot >> 24); + AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot)); REG_SET(DCN_VM_AGP_TOP, 0, - AGP_TOP, pa_config->system_aperture.agp_top >> 24); + AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top)); REG_SET(DCN_VM_AGP_BASE, 0, - AGP_BASE, pa_config->system_aperture.agp_base >> 24); + AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base)); if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) { phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12; diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c index 3c298192f359..79cb506be5cb 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c @@ -910,17 +910,17 @@ int hubbub31_init_dchub_sys_ctx(struct hubbub *hubbub, struct dcn_vmid_page_table_config phys_config; REG_SET(DCN_VM_FB_LOCATION_BASE, 0, - FB_BASE, pa_config->system_aperture.fb_base >> 24); + FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base)); REG_SET(DCN_VM_FB_LOCATION_TOP, 0, - FB_TOP, pa_config->system_aperture.fb_top >> 24); + FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top)); REG_SET(DCN_VM_FB_OFFSET, 0, - FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); + FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset)); REG_SET(DCN_VM_AGP_BOT, 0, - AGP_BOT, pa_config->system_aperture.agp_bot >> 24); + AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot)); REG_SET(DCN_VM_AGP_TOP, 0, - AGP_TOP, pa_config->system_aperture.agp_top >> 24); + AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top)); REG_SET(DCN_VM_AGP_BASE, 0, - AGP_BASE, pa_config->system_aperture.agp_base >> 24); + AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base)); if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) { phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12; diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c index 3b9542c08f3d..e12ed7591848 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c @@ -833,7 +833,7 @@ bool hubbub401_get_dcc_compression_cap(struct hubbub *hubbub, struct dc_surface_dcc_cap *output) { struct dc *dc = hubbub->ctx->dc; - const unsigned int max_dcc_plane_width = dc->caps.dcc_plane_width_limit; + const int max_dcc_plane_width = (int)dc->caps.dcc_plane_width_limit; /* DCN4_Programming_Guide_DCHUB.docx, Section 5.11.2.2 */ enum dcc_control dcc_control; unsigned int plane0_bpe, plane1_bpe; @@ -1198,6 +1198,7 @@ bool dcn401_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs bool wm_pending = false; uint32_t temp; + bool allow_sdpif_rate_limit_when_cstate_req = arb_regs->allow_sdpif_rate_limit_when_cstate_req != 0; /* request backpressure and outstanding return threshold (unused)*/ //REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, arb_regs->req_stall_threshold); @@ -1205,8 +1206,8 @@ bool dcn401_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs /* P-State stall threshold */ REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, arb_regs->pstate_stall_threshold); - if (safe_to_lower || arb_regs->allow_sdpif_rate_limit_when_cstate_req > hubbub2->allow_sdpif_rate_limit_when_cstate_req) { - hubbub2->allow_sdpif_rate_limit_when_cstate_req = arb_regs->allow_sdpif_rate_limit_when_cstate_req; + if (safe_to_lower || allow_sdpif_rate_limit_when_cstate_req > hubbub2->allow_sdpif_rate_limit_when_cstate_req) { + hubbub2->allow_sdpif_rate_limit_when_cstate_req = allow_sdpif_rate_limit_when_cstate_req; /* only update the required bits */ REG_GET(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, &temp); diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c index 73b6b0ffcb74..ddfc60e845a4 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c @@ -503,6 +503,7 @@ static bool dcn42_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb bool wm_pending = false; uint32_t temp; + bool allow_sdpif_rate_limit_when_cstate_req = arb_regs->allow_sdpif_rate_limit_when_cstate_req != 0; /* request backpressure and outstanding return threshold (unused)*/ //REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, arb_regs->req_stall_threshold); @@ -510,8 +511,8 @@ static bool dcn42_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb /* 401 delta: do not update P-State stall threshold (handled by fw) */ // REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, arb_regs->pstate_stall_threshold); - if (safe_to_lower || arb_regs->allow_sdpif_rate_limit_when_cstate_req > hubbub2->allow_sdpif_rate_limit_when_cstate_req) { - hubbub2->allow_sdpif_rate_limit_when_cstate_req = arb_regs->allow_sdpif_rate_limit_when_cstate_req; + if (safe_to_lower || allow_sdpif_rate_limit_when_cstate_req > hubbub2->allow_sdpif_rate_limit_when_cstate_req) { + hubbub2->allow_sdpif_rate_limit_when_cstate_req = allow_sdpif_rate_limit_when_cstate_req; /* only update the required bits */ REG_GET(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, &temp); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c index ceee5165fd6a..cf2c9f80056e 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c @@ -68,10 +68,10 @@ void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, - MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); + MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.low_part); REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, - MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); + MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.low_part); REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, ENABLE_L1_TLB, 1, @@ -710,7 +710,7 @@ void hubp2_dmdata_load( uint32_t dmdata_sw_size, const uint32_t *dmdata_sw_data) { - int i; + unsigned int i; struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); /* load dmdata into HUBP buffer in SW mode */ diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c index 08ea0a1b9e7f..67828505939a 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c @@ -238,10 +238,10 @@ static void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, - MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); + MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.low_part); REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, - MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); + MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.low_part); REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, ENABLE_L1_TLB, 1, diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c index e2708e30eb1b..3e5ae0eae39f 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c @@ -55,10 +55,10 @@ void hubp3_set_vm_system_aperture_settings(struct hubp *hubp, mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, - MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); + MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.low_part); REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, - MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); + MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.low_part); REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, ENABLE_L1_TLB, 1, diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c index 5a816442deee..3c7a6569b692 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c @@ -41,12 +41,12 @@ hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name void hubp401_program_3dlut_fl_addr(struct hubp *hubp, - const struct dc_plane_address *address) + const struct dc_plane_address address) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, address->lut3d.addr.high_part); - REG_WRITE(HUBP_3DLUT_ADDRESS_LOW, address->lut3d.addr.low_part); + REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, address.lut3d.addr.high_part); + REG_WRITE(HUBP_3DLUT_ADDRESS_LOW, address.lut3d.addr.low_part); } void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group) @@ -72,46 +72,33 @@ int hubp401_get_3dlut_fl_done(struct hubp *hubp) return ret; } -static void hubp401_get_3dlut_fl_xbar_map( - const enum dc_cm_lut_pixel_format format, - enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_y_g, - enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cb_b, - enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cr_r) -{ - switch (format) { - case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB: - case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB: - case CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10: - /* BGRA */ - *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; - *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; - *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; - break; - case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB: - case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB: - case CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10: - default: - /* RGBA */ - *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; - *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; - *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; - break; - } -} - -void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, - const enum dc_cm_lut_pixel_format format) +void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g = 0; - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b = 0; - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r = 0; + REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ADDRESSING_MODE, addr_mode); +} - hubp401_get_3dlut_fl_xbar_map(format, - &bit_slice_y_g, - &bit_slice_cb_b, - &bit_slice_cr_r); +void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_WIDTH, width); +} + +void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_TMZ, protection_bits); +} + +void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); REG_UPDATE_3(HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SELECT_Y_G, bit_slice_y_g, @@ -119,122 +106,62 @@ void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, HUBP_3DLUT_CROSSBAR_SELECT_CR_R, bit_slice_cr_r); } -static enum hubp_3dlut_fl_width hubp401_get_3dlut_fl_width( - const enum dc_cm_lut_size size, - const enum dc_cm_lut_swizzle swizzle) -{ - enum hubp_3dlut_fl_width width = 0; - - switch (size) { - case CM_LUT_SIZE_333333: - ASSERT(swizzle != CM_LUT_1D_PACKED_LINEAR); - width = hubp_3dlut_fl_width_33; - break; - case CM_LUT_SIZE_171717: - if (swizzle != CM_LUT_1D_PACKED_LINEAR) { - width = hubp_3dlut_fl_width_17; - } else { - width = hubp_3dlut_fl_width_17_transformed; - } - break; - default: - width = 0; - break; - } - - return width; -} - -static enum hubp_3dlut_fl_format hubp401_get_3dlut_fl_format( - const enum dc_cm_lut_pixel_format dc_format) -{ - enum hubp_3dlut_fl_format hubp_format = hubp_3dlut_fl_format_unorm_12msb_bitslice; - - switch (dc_format) { - case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB: - case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB: - hubp_format = hubp_3dlut_fl_format_unorm_12msb_bitslice; - break; - case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB: - case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB: - hubp_format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; - break; - case CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10: - case CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10: - hubp_format = hubp_3dlut_fl_format_float_fp1_5_10; - break; - default: - BREAK_TO_DEBUGGER(); - break; - } - - return hubp_format; -} - -static enum hubp_3dlut_fl_addressing_mode hubp401_get_3dlut_fl_addr_mode( - const enum dc_cm_lut_swizzle swizzle) -{ - enum hubp_3dlut_fl_addressing_mode addr_mode; - - switch (swizzle) { - case CM_LUT_1D_PACKED_LINEAR: - addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; - break; - case CM_LUT_3D_SWIZZLE_LINEAR_RGB: - case CM_LUT_3D_SWIZZLE_LINEAR_BGR: - default: - addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; - break; - } - - return addr_mode; -} - -static enum hubp_3dlut_fl_mode hubp401_get_3dlut_fl_mode( - const enum dc_cm_lut_swizzle swizzle) -{ - enum hubp_3dlut_fl_mode mode; - - switch (swizzle) { - case CM_LUT_3D_SWIZZLE_LINEAR_RGB: - mode = hubp_3dlut_fl_mode_native_1; - break; - case CM_LUT_3D_SWIZZLE_LINEAR_BGR: - mode = hubp_3dlut_fl_mode_native_2; - break; - case CM_LUT_1D_PACKED_LINEAR: - mode = hubp_3dlut_fl_mode_transform; - break; - default: - mode = hubp_3dlut_fl_mode_disable; - break; - } - - return mode; -} - -void hubp401_program_3dlut_fl_config(struct hubp *hubp, - const struct dc_3dlut_dma *config) +void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - enum hubp_3dlut_fl_width width = hubp401_get_3dlut_fl_width(config->size, config->swizzle); - enum hubp_3dlut_fl_format format = hubp401_get_3dlut_fl_format(config->format); - enum hubp_3dlut_fl_addressing_mode addr_mode = hubp401_get_3dlut_fl_addr_mode(config->swizzle); - enum hubp_3dlut_fl_mode mode = hubp401_get_3dlut_fl_mode(config->swizzle); + REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_BIAS, bias, HUBP0_3DLUT_FL_SCALE, scale); +} + +void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_MODE, mode); +} + +void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, format); +} + +void hubp401_program_3dlut_fl_config( + struct hubp *hubp, + struct hubp_fl_3dlut_config *cfg) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + uint32_t mpc_width = {(cfg->width == 17) ? 0 : 1}; + uint32_t width = {cfg->width}; + + if (cfg->layout == DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR) + width = (cfg->width == 17) ? 4916 : 35940; REG_UPDATE_2(_3DLUT_FL_CONFIG, - HUBP0_3DLUT_FL_MODE, mode, - HUBP0_3DLUT_FL_FORMAT, format); + HUBP0_3DLUT_FL_MODE, cfg->mode, + HUBP0_3DLUT_FL_FORMAT, cfg->format); REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE, - HUBP0_3DLUT_FL_BIAS, config->bias, - HUBP0_3DLUT_FL_SCALE, config->scale); + HUBP0_3DLUT_FL_BIAS, cfg->bias, + HUBP0_3DLUT_FL_SCALE, cfg->scale); - REG_UPDATE_3(HUBP_3DLUT_CONTROL, - HUBP_3DLUT_WIDTH, width, - HUBP_3DLUT_ADDRESSING_MODE, addr_mode, - HUBP_3DLUT_TMZ, config->addr.tmz_surface); + REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, + HUBP_3DLUT_ADDRESS_HIGH, cfg->address.lut3d.addr.high_part); + REG_UPDATE(HUBP_3DLUT_ADDRESS_LOW, + HUBP_3DLUT_ADDRESS_LOW, cfg->address.lut3d.addr.low_part); + + //cross bar + REG_UPDATE_8(HUBP_3DLUT_CONTROL, + HUBP_3DLUT_MPC_WIDTH, mpc_width, + HUBP_3DLUT_WIDTH, width, + HUBP_3DLUT_CROSSBAR_SELECT_CR_R, cfg->crossbar_bit_slice_cr_r, + HUBP_3DLUT_CROSSBAR_SELECT_Y_G, cfg->crossbar_bit_slice_y_g, + HUBP_3DLUT_CROSSBAR_SELECT_CB_B, cfg->crossbar_bit_slice_cb_b, + HUBP_3DLUT_ADDRESSING_MODE, cfg->addr_mode, + HUBP_3DLUT_TMZ, cfg->protection_bits, + HUBP_3DLUT_ENABLE, cfg->enabled ? 1 : 0); } void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor) @@ -1135,13 +1062,19 @@ static struct hubp_funcs dcn401_hubp_funcs = { .hubp_update_mall_sel = hubp401_update_mall_sel, .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering, .hubp_program_mcache_id_and_split_coordinate = hubp401_program_mcache_id_and_split_coordinate, + .hubp_update_3dlut_fl_bias_scale = hubp401_update_3dlut_fl_bias_scale, + .hubp_program_3dlut_fl_mode = hubp401_program_3dlut_fl_mode, + .hubp_program_3dlut_fl_format = hubp401_program_3dlut_fl_format, .hubp_program_3dlut_fl_addr = hubp401_program_3dlut_fl_addr, - .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config, .hubp_program_3dlut_fl_dlg_param = hubp401_program_3dlut_fl_dlg_param, .hubp_enable_3dlut_fl = hubp401_enable_3dlut_fl, + .hubp_program_3dlut_fl_addressing_mode = hubp401_program_3dlut_fl_addressing_mode, + .hubp_program_3dlut_fl_width = hubp401_program_3dlut_fl_width, + .hubp_program_3dlut_fl_tmz_protected = hubp401_program_3dlut_fl_tmz_protected, .hubp_program_3dlut_fl_crossbar = hubp401_program_3dlut_fl_crossbar, .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, .hubp_clear_tiling = hubp401_clear_tiling, + .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config, .hubp_read_reg_state = hubp3_read_reg_state }; diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h index 043948f64b86..4570b8016de5 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h @@ -328,17 +328,32 @@ int hubp401_get_3dlut_fl_done(struct hubp *hubp); void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable); +void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale); + void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, - const enum dc_cm_lut_pixel_format format); + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r); + +void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits); + +void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width); + +void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode); void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable); void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group); -void hubp401_program_3dlut_fl_addr(struct hubp *hubp, const struct dc_plane_address *address); +void hubp401_program_3dlut_fl_addr(struct hubp *hubp, const struct dc_plane_address address); -void hubp401_program_3dlut_fl_config(struct hubp *hubp, - const struct dc_3dlut_dma *config); +void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format); + +void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode); + +void hubp401_program_3dlut_fl_config( + struct hubp *hubp, + struct hubp_fl_3dlut_config *cfg); void hubp401_clear_tiling(struct hubp *hubp); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c index ad6badcceb12..e4602c3ddc66 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c @@ -311,84 +311,19 @@ static void hubp42_program_surface_config( hubp42_program_pixel_format(hubp, format); } -static void hubp42_get_3dlut_fl_xbar_map( - const enum dc_cm_lut_pixel_format format, - enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_y_g, - enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cb_b, - enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cr_r) -{ - switch (format) { - case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB: - case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB: - case CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10: - /* BGRA */ - *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; - *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; - *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; - break; - case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB: - case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB: - case CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10: - default: - /* RGBA */ - *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; - *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; - *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; - break; - } -} - void hubp42_program_3dlut_fl_crossbar(struct hubp *hubp, - const enum dc_cm_lut_pixel_format format) + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_r, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_g, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_b) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_g = 0; - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_b = 0; - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_r = 0; - - hubp42_get_3dlut_fl_xbar_map(format, - &bit_slice_g, - &bit_slice_b, - &bit_slice_r); - REG_UPDATE_3(HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SEL_R, bit_slice_r, HUBP_3DLUT_CROSSBAR_SEL_G, bit_slice_g, HUBP_3DLUT_CROSSBAR_SEL_B, bit_slice_b); } -static uint32_t hubp42_get_3dlut_fl_mpc_width( - const enum dc_cm_lut_size size) -{ - uint32_t width = 0; - - switch (size) { - case CM_LUT_SIZE_333333: - width = 1; - break; - case CM_LUT_SIZE_171717: - default: - width = 0; - break; - } - - return width; -} - -void hubp42_program_3dlut_fl_config(struct hubp *hubp, - const struct dc_3dlut_dma *config) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - uint32_t mpc_width = hubp42_get_3dlut_fl_mpc_width(config->size); - - REG_UPDATE(HUBP_3DLUT_CONTROL, - HUBP_3DLUT_MPC_WIDTH, mpc_width); - - hubp401_program_3dlut_fl_config(hubp, config); -} - static bool hubp42_program_surface_flip_and_addr( struct hubp *hubp, const struct dc_plane_address *address, @@ -670,10 +605,15 @@ struct hubp_funcs dcn42_hubp_funcs = { .hubp_set_flip_int = hubp1_set_flip_int, .hubp_in_blank = hubp1_in_blank, .program_extended_blank = hubp31_program_extended_blank_value, + .hubp_update_3dlut_fl_bias_scale = hubp401_update_3dlut_fl_bias_scale, + .hubp_program_3dlut_fl_mode = hubp401_program_3dlut_fl_mode, + .hubp_program_3dlut_fl_format = hubp401_program_3dlut_fl_format, .hubp_program_3dlut_fl_addr = hubp401_program_3dlut_fl_addr, - .hubp_program_3dlut_fl_config = hubp42_program_3dlut_fl_config, .hubp_program_3dlut_fl_dlg_param = hubp401_program_3dlut_fl_dlg_param, .hubp_enable_3dlut_fl = hubp401_enable_3dlut_fl, + .hubp_program_3dlut_fl_addressing_mode = hubp401_program_3dlut_fl_addressing_mode, + .hubp_program_3dlut_fl_width = hubp401_program_3dlut_fl_width, + .hubp_program_3dlut_fl_tmz_protected = hubp401_program_3dlut_fl_tmz_protected, .hubp_program_3dlut_fl_crossbar = hubp42_program_3dlut_fl_crossbar, .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, .hubp_clear_tiling = hubp3_clear_tiling, diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h index 88bb1337ab9d..f0e614136228 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h @@ -58,11 +58,11 @@ bool hubp42_construct( const struct dcn_hubp2_shift *hubp_shift, const struct dcn_hubp2_mask *hubp_mask); -void hubp42_program_3dlut_fl_crossbar(struct hubp *hubp, - const enum dc_cm_lut_pixel_format format); - -void hubp42_program_3dlut_fl_config(struct hubp *hubp, - const struct dc_3dlut_dma *config); +void hubp42_program_3dlut_fl_crossbar( + struct hubp *hubp, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_r, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_g, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_b); void hubp42_read_state(struct hubp *hubp); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 5273ca09fe12..d81271b870bb 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -504,7 +504,7 @@ dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, } j = 0; - for (k = 0; k < (region_end - region_start); k++) { + for (k = 0; k < (uint32_t)(region_end - region_start); k++) { increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); start_index = (region_start + k + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; @@ -665,16 +665,45 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) } static void -dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable) +dce110_external_encoder_control(enum bp_external_encoder_control_action action, + struct dc_link *link, + struct dc_crtc_timing *timing) { - struct dc_link *link = pipe_ctx->stream->link; + struct dc *dc = link->ctx->dc; struct dc_bios *bios = link->ctx->dc_bios; - struct bp_encoder_control encoder_control = {0}; + const struct dc_link_settings *link_settings = &link->cur_link_settings; + enum bp_result bp_result = BP_RESULT_OK; + struct bp_external_encoder_control ext_cntl = { + .action = action, + .connector_obj_id = link->link_enc->connector, + .encoder_id = link->ext_enc_id, + .lanes_number = link_settings->lane_count, + .link_rate = link_settings->link_rate, - encoder_control.action = enable ? ENCODER_CONTROL_ENABLE : ENCODER_CONTROL_DISABLE; - encoder_control.engine_id = link->link_enc->analog_engine; - encoder_control.pixel_clock = pipe_ctx->stream->timing.pix_clk_100hz / 10; - bios->funcs->encoder_control(bios, &encoder_control); + /* Use signal type of the real link encoder, ie. DP */ + .signal = link->connector_signal, + + /* We don't know the timing yet when executing the SETUP action, + * so use a reasonably high default value. It seems that ENABLE + * can change the actual pixel clock but doesn't work with higher + * pixel clocks than what SETUP was called with. + */ + .pixel_clock = timing ? timing->pix_clk_100hz / 10 : 300000, + .color_depth = timing ? timing->display_color_depth : COLOR_DEPTH_888, + }; + DC_LOGGER_INIT(dc->ctx); + + bp_result = bios->funcs->external_encoder_control(bios, &ext_cntl); + + if (bp_result != BP_RESULT_OK) + DC_LOG_ERROR("Failed to execute external encoder action: 0x%x\n", action); +} + +static void +dce110_prepare_ddc(struct dc_link *link) +{ + if (link->ext_enc_id.id) + dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DDC_SETUP, link, NULL); } static bool @@ -684,7 +713,8 @@ dce110_dac_load_detect(struct dc_link *link) struct link_encoder *link_enc = link->link_enc; enum bp_result bp_result; - bp_result = bios->funcs->dac_load_detection(bios, link_enc->analog_engine); + bp_result = bios->funcs->dac_load_detection( + bios, link_enc->analog_engine, link->ext_enc_id); return bp_result == BP_RESULT_OK; } @@ -700,7 +730,6 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) uint32_t early_control = 0; struct timing_generator *tg = pipe_ctx->stream_res.tg; - link_hwss->setup_stream_attribute(pipe_ctx); link_hwss->setup_stream_encoder(pipe_ctx); dc->hwss.update_info_frame(pipe_ctx); @@ -719,8 +748,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) tg->funcs->set_early_control(tg, early_control); - if (dc_is_rgb_signal(pipe_ctx->stream->signal)) - dce110_dac_encoder_control(pipe_ctx, true); + if (link->ext_enc_id.id) + dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_ENABLE, link, timing); } static enum bp_result link_transmitter_control( @@ -858,7 +887,7 @@ void dce110_edp_power_control( DC_LOG_HW_RESUME_S3( "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n", __func__, remaining_min_edp_poweroff_time_ms); - msleep(remaining_min_edp_poweroff_time_ms); + msleep((unsigned int)remaining_min_edp_poweroff_time_ms); DC_LOG_HW_RESUME_S3( "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n", __func__, remaining_min_edp_poweroff_time_ms); @@ -883,7 +912,7 @@ void dce110_edp_power_control( cntl.coherent = false; cntl.lanes_number = LANE_COUNT_FOUR; cntl.hpd_sel = link->link_enc->hpd_source; - pwrseq_instance = link->panel_cntl->pwrseq_inst; + pwrseq_instance = (uint8_t)link->panel_cntl->pwrseq_inst; if (ctx->dc->ctx->dmub_srv && ctx->dc->debug.dmub_command_table) { @@ -952,7 +981,7 @@ void dce110_edp_wait_for_T12( t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12 if (time_since_edp_poweroff_ms < t12_duration) - msleep(t12_duration - time_since_edp_poweroff_ms); + msleep((unsigned int)(t12_duration - time_since_edp_poweroff_ms)); } } /*todo: cloned in stream enc, fix*/ @@ -1021,8 +1050,9 @@ void dce110_edp_backlight_control( */ /* dc_service_sleep_in_milliseconds(50); */ /*edp 1.2*/ - if (link->panel_cntl) - pwrseq_instance = link->panel_cntl->pwrseq_inst; + if (link->panel_cntl) { + pwrseq_instance = (uint8_t)link->panel_cntl->pwrseq_inst; + } if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) { if (!link->dc->config.edp_no_power_sequencing) @@ -1219,8 +1249,8 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) link_enc->transmitter - TRANSMITTER_UNIPHY_A); } - if (dc_is_rgb_signal(pipe_ctx->stream->signal)) - dce110_dac_encoder_control(pipe_ctx, false); + if (link->ext_enc_id.id) + dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DISABLE, link, NULL); } void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, @@ -1439,11 +1469,11 @@ void build_audio_output( audio_output->crtc_info.pixel_repetition = 1; audio_output->crtc_info.interlaced = - stream->timing.flags.INTERLACE; + (stream->timing.flags.INTERLACE != 0); audio_output->crtc_info.refresh_rate = - (stream->timing.pix_clk_100hz*100)/ - (stream->timing.h_total*stream->timing.v_total); + (uint16_t)((stream->timing.pix_clk_100hz*100)/ + (stream->timing.h_total*stream->timing.v_total)); audio_output->crtc_info.color_depth = stream->timing.display_color_depth; @@ -1603,22 +1633,6 @@ static enum dc_status dce110_enable_stream_timing( return DC_OK; } -static void -dce110_select_crtc_source(struct pipe_ctx *pipe_ctx) -{ - struct dc_link *link = pipe_ctx->stream->link; - struct dc_bios *bios = link->ctx->dc_bios; - struct bp_crtc_source_select crtc_source_select = {0}; - enum engine_id engine_id = link->link_enc->preferred_engine; - - if (dc_is_rgb_signal(pipe_ctx->stream->signal)) - engine_id = link->link_enc->analog_engine; - crtc_source_select.controller_id = CONTROLLER_ID_D0 + pipe_ctx->stream_res.tg->inst; - crtc_source_select.color_depth = pipe_ctx->stream->timing.display_color_depth; - crtc_source_select.engine_id = engine_id; - crtc_source_select.sink_signal = pipe_ctx->stream->signal; - bios->funcs->select_crtc_source(bios, &crtc_source_select); -} enum dc_status dce110_apply_single_controller_ctx_to_hw( struct pipe_ctx *pipe_ctx, @@ -1639,10 +1653,6 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw( hws->funcs.disable_stream_gating(dc, pipe_ctx); } - if (pipe_ctx->stream->signal == SIGNAL_TYPE_RGB) { - dce110_select_crtc_source(pipe_ctx); - } - if (pipe_ctx->stream_res.audio != NULL) { struct audio_output audio_output = {0}; @@ -1722,8 +1732,7 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw( pipe_ctx->stream_res.tg->funcs->set_static_screen_control( pipe_ctx->stream_res.tg, event_triggers, 2); - if (!dc_is_virtual_signal(pipe_ctx->stream->signal) && - !dc_is_rgb_signal(pipe_ctx->stream->signal)) + if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( pipe_ctx->stream_res.stream_enc, pipe_ctx->stream_res.tg->inst); @@ -1778,20 +1787,22 @@ static void power_down_encoders(struct dc *dc) for (i = 0; i < dc->link_count; i++) { struct dc_link *link = dc->links[i]; - struct link_encoder *link_enc = link->link_enc; + struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link); enum signal_type signal = link->connector_signal; dc->link_srv->blank_dp_stream(link, false); if (signal != SIGNAL_TYPE_EDP) signal = SIGNAL_TYPE_NONE; - if (link->ep_type == DISPLAY_ENDPOINT_PHY) + if (link->ep_type == DISPLAY_ENDPOINT_PHY && link_enc) link_enc->funcs->disable_output(link_enc, signal); if (link->fec_state == dc_link_fec_enabled) { - link_enc->funcs->fec_set_enable(link_enc, false); - link_enc->funcs->fec_set_ready(link_enc, false); - link->fec_state = dc_link_fec_not_ready; + if (link_enc && link_enc->funcs->fec_set_enable && link_enc->funcs->fec_set_ready) { + link_enc->funcs->fec_set_enable(link_enc, false); + link_enc->funcs->fec_set_ready(link_enc, false); + link->fec_state = dc_link_fec_not_ready; + } } link->link_status.link_active = false; @@ -1801,7 +1812,7 @@ static void power_down_encoders(struct dc *dc) static void power_down_controllers(struct dc *dc) { - int i; + unsigned int i; for (i = 0; i < dc->res_pool->timing_generator_count; i++) { dc->res_pool->timing_generators[i]->funcs->disable_crtc( @@ -1811,7 +1822,7 @@ static void power_down_controllers(struct dc *dc) static void power_down_clock_sources(struct dc *dc) { - int i; + unsigned int i; if (dc->res_pool->dp_clock_source->funcs->cs_power_down( dc->res_pool->dp_clock_source) == false) @@ -1820,7 +1831,7 @@ static void power_down_clock_sources(struct dc *dc) for (i = 0; i < dc->res_pool->clk_src_count; i++) { if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( dc->res_pool->clock_sources[i]) == false) - dm_error("Failed to power down pll! (clk src index=%d)\n", i); + dm_error("Failed to power down pll! (clk src index=%u)\n", i); } } @@ -1839,7 +1850,7 @@ static void power_down_all_hw_blocks(struct dc *dc) static void disable_vga_and_power_gate_all_controllers( struct dc *dc) { - int i; + uint8_t i; struct timing_generator *tg; struct dc_context *ctx = dc->ctx; @@ -1869,7 +1880,7 @@ static void get_edp_streams(struct dc_state *context, struct dc_stream_state **edp_streams, int *edp_stream_num) { - int i; + uint8_t i; *edp_stream_num = 0; for (i = 0; i < context->stream_count; i++) { @@ -1907,13 +1918,13 @@ static void clean_up_dsc_blocks(struct dc *dc) struct stream_encoder *se = NULL; struct dccg *dccg = dc->res_pool->dccg; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; - int i; + unsigned int i; if (!dc->caps.is_apu || dc->ctx->dce_version < DCN_VERSION_3_15) return; /*VBIOS supports dsc starts from dcn315*/ - for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) { struct dcn_dsc_state s = {0}; dsc = dc->res_pool->dscs[i]; @@ -1991,7 +2002,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) struct pipe_ctx *pipe_ctx = NULL; struct dce_hwseq *hws = dc->hwseq; int edp_with_sink_num; - unsigned int edp_num; + unsigned int j, edp_num; int edp_stream_num; int i; bool can_apply_edp_fast_boot = false; @@ -2011,8 +2022,8 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) /* Check fastboot support, disable on DCE 6-8-10 because of blank screens */ if (edp_num && edp_stream_num && dc->ctx->dce_version > DCE_VERSION_10_0) { - for (i = 0; i < edp_num; i++) { - edp_link = edp_links[i]; + for (j = 0; j < edp_num; j++) { + edp_link = edp_links[j]; if (edp_link != edp_streams[0]->link) continue; // enable fastboot if backend is enabled on eDP @@ -2115,9 +2126,11 @@ static uint32_t compute_pstate_blackout_duration( const struct dc_stream_state *stream) { uint32_t total_dest_line_time_ns; + int64_t pstate_blackout_duration_ns64; uint32_t pstate_blackout_duration_ns; - pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; + pstate_blackout_duration_ns64 = (1000 * blackout_duration.value) >> 24; + pstate_blackout_duration_ns = (uint32_t)pstate_blackout_duration_ns64; total_dest_line_time_ns = 1000000UL * (stream->timing.h_total * 10) / @@ -2251,7 +2264,7 @@ static void get_position(struct pipe_ctx **pipe_ctx, static void set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_params *params) { - unsigned int i; + int i; unsigned int triggers = 0; if (params->triggers.overlay_update) @@ -2538,7 +2551,7 @@ enum dc_status dce110_apply_ctx_to_hw( struct dce_hwseq *hws = dc->hwseq; struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status status; - int i; + unsigned int i; bool was_hpo_acquired = resource_is_hpo_acquired(dc->current_state); bool is_hpo_acquired = resource_is_hpo_acquired(context); @@ -2574,7 +2587,7 @@ enum dc_status dce110_apply_ctx_to_hw( } hws->funcs.enable_display_power_gating( - dc, i, dc->ctx->dc_bios, + dc, (uint8_t)i, dc->ctx->dc_bios, PIPE_GATING_CONTROL_DISABLE); } @@ -2904,7 +2917,7 @@ static void dce110_init_pipes(struct dc *dc, struct dc_state *context) static void dce110_init_hw(struct dc *dc) { - int i; + unsigned int i; struct dc_bios *bp; struct transform *xfm; struct abm *abm; @@ -2919,10 +2932,10 @@ static void dce110_init_hw(struct dc *dc) xfm->funcs->transform_reset(xfm); hws->funcs.enable_display_power_gating( - dc, i, bp, + dc, (uint8_t)i, bp, PIPE_GATING_CONTROL_INIT); hws->funcs.enable_display_power_gating( - dc, i, bp, + dc, (uint8_t)i, bp, PIPE_GATING_CONTROL_DISABLE); hws->funcs.enable_display_pipe_clock_gating( dc->ctx, @@ -3126,7 +3139,7 @@ static void dce110_apply_ctx_for_surface( int num_planes, struct dc_state *context) { - int i; + unsigned int i; if (num_planes == 0) return; @@ -3180,7 +3193,7 @@ static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct p return; hws->funcs.enable_display_power_gating( - dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); + dc, (uint8_t)fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); dc->res_pool->transforms[fe_idx]->funcs->transform_reset( dc->res_pool->transforms[fe_idx]); @@ -3376,6 +3389,15 @@ void dce110_enable_tmds_link_output(struct dc_link *link, link->phy_state.symclk_state = SYMCLK_ON_TX_ON; } +static void dce110_enable_analog_link_output( + struct dc_link *link, + uint32_t pix_clk_100hz) +{ + link->link_enc->funcs->enable_analog_output( + link->link_enc, + pix_clk_100hz); +} + void dce110_enable_dp_link_output( struct dc_link *link, const struct link_resource *link_res, @@ -3423,6 +3445,11 @@ void dce110_enable_dp_link_output( } } + if (link->ext_enc_id.id) { + dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_INIT, link, NULL); + dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_SETUP, link, NULL); + } + if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) { if (dc->clk_mgr->funcs->notify_link_rate_change) dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link); @@ -3513,8 +3540,10 @@ static const struct hw_sequencer_funcs dce110_funcs = { .enable_lvds_link_output = dce110_enable_lvds_link_output, .enable_tmds_link_output = dce110_enable_tmds_link_output, .enable_dp_link_output = dce110_enable_dp_link_output, + .enable_analog_link_output = dce110_enable_analog_link_output, .disable_link_output = dce110_disable_link_output, .dac_load_detect = dce110_dac_load_detect, + .prepare_ddc = dce110_prepare_ddc, }; static const struct hwseq_private_funcs dce110_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c index 0689bbf12ad8..fbe34d1bb39a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c @@ -208,24 +208,24 @@ static void dce120_update_dchub( FB_BASE, 0x0FFFF); REG_UPDATE(DCHUB_AGP_BASE, - AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22)); REG_UPDATE(DCHUB_AGP_BOT, - AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22)); REG_UPDATE(DCHUB_AGP_TOP, - AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22); + AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22)); break; case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ REG_UPDATE(DCHUB_AGP_BASE, - AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22)); REG_UPDATE(DCHUB_AGP_BOT, - AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22)); REG_UPDATE(DCHUB_AGP_TOP, - AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22); + AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22)); break; case FRAME_BUFFER_MODE_LOCAL_ONLY: /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 756ce8379538..13e0e9ceeae3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -225,7 +225,7 @@ void dcn10_lock_all_pipes(struct dc *dc, struct pipe_ctx *pipe_ctx; struct pipe_ctx *old_pipe_ctx; struct timing_generator *tg; - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; @@ -298,7 +298,7 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx) { struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; DTN_INFO( "HUBP: format addr_hi width height rot mir sw_mode dcc_en blank_en clock_en ttu_dis underflow min_ttu_vblank qos_low_wm qos_high_wm\n"); @@ -456,7 +456,7 @@ static void dcn10_log_color_state(struct dc *dc, struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; bool is_gamut_remap_available = false; - int i; + unsigned int i; DTN_INFO("DPP: IGAM format IGAM mode DGAM mode RGAM mode" " GAMUT adjust " @@ -616,7 +616,8 @@ void dcn10_log_hw_state(struct dc *dc, { struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; - int i; + int j; + unsigned int i; DTN_INFO_BEGIN(); @@ -686,8 +687,8 @@ void dcn10_log_hw_state(struct dc *dc, // dcn_dsc_state struct field bytes_per_pixel was renamed to bits_per_pixel // TODO: Update golden log header to reflect this name change DTN_INFO("DSC: CLOCK_EN SLICE_WIDTH Bytes_pp\n"); - for (i = 0; i < pool->res_cap->num_dsc; i++) { - struct display_stream_compressor *dsc = pool->dscs[i]; + for (j = 0; j < pool->res_cap->num_dsc; j++) { + struct display_stream_compressor *dsc = pool->dscs[j]; struct dcn_dsc_state s = {0}; dsc->funcs->dsc_read_state(dsc, &s); @@ -1059,7 +1060,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; struct hubp *hubp = dc->res_pool->hubps[0]; - int i; + unsigned int i; if (dc->debug.disable_stutter) return; @@ -1089,7 +1090,7 @@ void dcn10_bios_golden_init(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; struct dc_bios *bp = dc->ctx->dc_bios; - int i; + unsigned int i; bool allow_self_fresh_force_enable = true; if (hws->funcs.s0i3_golden_init_wa && hws->funcs.s0i3_golden_init_wa(dc)) @@ -1130,7 +1131,7 @@ static void false_optc_underflow_wa( const struct dc_stream_state *stream, struct timing_generator *tg) { - int i; + unsigned int i; bool underflow; if (!dc->hwseq->wa.false_optc_underflow) @@ -1157,7 +1158,7 @@ static void false_optc_underflow_wa( static int calculate_vready_offset_for_group(struct pipe_ctx *pipe) { struct pipe_ctx *other_pipe; - int vready_offset = pipe->pipe_dlg_param.vready_offset; + unsigned int vready_offset = pipe->pipe_dlg_param.vready_offset; /* Always use the largest vready_offset of all connected pipes */ for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) { @@ -1290,7 +1291,7 @@ static void dcn10_reset_back_end_for_pipe( struct dc_state *context) { (void)context; - int i; + unsigned int i; struct dc_link *link; DC_LOGGER_INIT(dc->ctx); if (pipe_ctx->stream_res.stream_enc == NULL) { @@ -1574,7 +1575,7 @@ void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx void dcn10_init_pipes(struct dc *dc, struct dc_state *context) { - int i; + uint8_t i; struct dce_hwseq *hws = dc->hwseq; struct hubbub *hubbub = dc->res_pool->hubbub; bool can_apply_seamless_boot = false; @@ -1677,7 +1678,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context) pipe_ctx->plane_res.hubp = hubp; pipe_ctx->plane_res.dpp = dpp; - pipe_ctx->plane_res.mpcc_inst = dpp->inst; + pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst; hubp->mpcc_id = dpp->inst; hubp->opp_id = OPP_ID_INVALID; hubp->power_gated = false; @@ -1764,7 +1765,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context) void dcn10_init_hw(struct dc *dc) { - int i; + unsigned int i; struct abm *abm = dc->res_pool->abm; struct dmcu *dmcu = dc->res_pool->dmcu; struct dce_hwseq *hws = dc->hwseq; @@ -2095,22 +2096,22 @@ static void log_tf(struct dc_context *ctx, // DC_LOG_GAMMA is default logging of all hw points // DC_LOG_ALL_GAMMA logs all points, not only hw points // DC_LOG_ALL_TF_POINTS logs all channels of the tf - int i = 0; + unsigned int i = 0; DC_LOG_GAMMA("Gamma Correction TF"); DC_LOG_ALL_GAMMA("Logging all tf points..."); DC_LOG_ALL_TF_CHANNELS("Logging all channels..."); for (i = 0; i < hw_points_num; i++) { - DC_LOG_GAMMA("R\t%d\t%llu", i, tf->tf_pts.red[i].value); - DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu", i, tf->tf_pts.green[i].value); - DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu", i, tf->tf_pts.blue[i].value); + DC_LOG_GAMMA("R\t%u\t%llu", i, tf->tf_pts.red[i].value); + DC_LOG_ALL_TF_CHANNELS("G\t%u\t%llu", i, tf->tf_pts.green[i].value); + DC_LOG_ALL_TF_CHANNELS("B\t%u\t%llu", i, tf->tf_pts.blue[i].value); } for (i = hw_points_num; i < MAX_NUM_HW_POINTS; i++) { - DC_LOG_ALL_GAMMA("R\t%d\t%llu", i, tf->tf_pts.red[i].value); - DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu", i, tf->tf_pts.green[i].value); - DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu", i, tf->tf_pts.blue[i].value); + DC_LOG_ALL_GAMMA("R\t%u\t%llu", i, tf->tf_pts.red[i].value); + DC_LOG_ALL_TF_CHANNELS("G\t%u\t%llu", i, tf->tf_pts.green[i].value); + DC_LOG_ALL_TF_CHANNELS("B\t%u\t%llu", i, tf->tf_pts.blue[i].value); } } @@ -2258,7 +2259,7 @@ void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock) struct dmub_hw_lock_inst_flags inst_flags = { 0 }; hw_locks.bits.lock_cursor = 1; - inst_flags.opp_inst = pipe->stream_res.opp->inst; + inst_flags.opp_inst = (uint8_t)pipe->stream_res.opp->inst; dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, lock, @@ -2278,7 +2279,7 @@ static bool wait_for_reset_trigger_to_occur( /* To avoid endless loop we wait at most * frames_to_wait_on_triggered_reset frames for the reset to occur. */ const uint32_t frames_to_wait_on_triggered_reset = 10; - int i; + unsigned int i; for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { @@ -2290,7 +2291,7 @@ static bool wait_for_reset_trigger_to_occur( if (tg->funcs->did_triggered_reset_occur(tg)) { rc = true; /* usually occurs at i=1 */ - DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", + DC_SYNC_INFO("GSL: reset occurred at wait count: %u\n", i); break; } @@ -2383,7 +2384,7 @@ static uint8_t get_clock_divider(struct pipe_ctx *pipe, } clock_divider *= numpipes; - return clock_divider; + return (uint8_t)clock_divider; } static int dcn10_align_pixel_clocks(struct dc *dc, int group_size, @@ -2458,7 +2459,7 @@ static int dcn10_align_pixel_clocks(struct dc *dc, int group_size, dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk( dc->res_pool->dp_clock_source, grouped_pipes[i]->stream_res.tg->inst, - phase[i], modulo[i]); + (unsigned int)phase[i], (unsigned int)modulo[i]); dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz( dc->res_pool->dp_clock_source, grouped_pipes[i]->stream_res.tg->inst, &pclk); @@ -3263,7 +3264,7 @@ void dcn10_wait_for_pending_cleared(struct dc *dc, { struct pipe_ctx *pipe_ctx; struct timing_generator *tg; - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { pipe_ctx = &context->res_ctx.pipe_ctx[i]; @@ -3294,7 +3295,7 @@ void dcn10_post_unlock_program_front_end( struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; @@ -3466,7 +3467,7 @@ void dcn10_get_position(struct pipe_ctx **pipe_ctx, void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_params *params) { - unsigned int i; + int i; unsigned int triggers = 0; if (params->triggers.surface_update) @@ -3516,7 +3517,7 @@ void dcn10_config_stereo_parameters( } } flags->RIGHT_EYE_POLARITY =\ - stream->timing.flags.RIGHT_EYE_3D_POLARITY; + (stream->timing.flags.RIGHT_EYE_3D_POLARITY != 0); if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) flags->FRAME_PACKED = 1; } @@ -3553,7 +3554,7 @@ void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc) static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) { - int i; + unsigned int i; for (i = 0; i < res_pool->pipe_count; i++) { if (res_pool->hubps[i]->inst == mpcc_inst) @@ -3794,7 +3795,7 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) // Swap axis and mirror vertically else if (param.rotation == ROTATION_ANGLE_270) { uint32_t temp_y = pos_cpy.y; - int viewport_height = + uint32_t viewport_height = pipe_ctx->plane_res.scl_data.viewport.height; int viewport_y = pipe_ctx->plane_res.scl_data.viewport.y; @@ -4121,7 +4122,7 @@ void dcn10_get_clock(struct dc *dc, void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { struct hubp *hubp = pool->hubps[i]; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 288e4edaa9a2..07c53a8e73b5 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -79,7 +79,7 @@ void dcn20_log_color_state(struct dc *dc, struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; bool is_gamut_remap_available = false; - int i; + unsigned int i; DTN_INFO("DPP: DGAM mode SHAPER mode 3DLUT mode 3DLUT bit depth" " 3DLUT size RGAM mode GAMUT adjust " @@ -235,7 +235,7 @@ void dcn20_setup_gsl_group_as_lock( group_idx = find_free_gsl_group(dc); ASSERT(group_idx != 0); - pipe_ctx->stream_res.gsl_group = group_idx; + pipe_ctx->stream_res.gsl_group = (uint8_t)group_idx; /* set gsl group reg field and mark resource used */ switch (group_idx) { @@ -400,6 +400,7 @@ void dcn20_init_blank( struct output_pixel_processor *bottom_opp = NULL; uint32_t num_opps, opp_id_src0, opp_id_src1; uint32_t otg_active_width = 0, otg_active_height = 0; + unsigned int num_opp_cap = (unsigned int)dc->res_pool->res_cap->num_opp; /* program opp dpg blank color */ color_space = COLOR_SPACE_SRGB; @@ -413,7 +414,7 @@ void dcn20_init_blank( /* get the OPTC source */ tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); - if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { + if (opp_id_src0 >= num_opp_cap) { ASSERT(false); return; } @@ -426,7 +427,7 @@ void dcn20_init_blank( if (num_opps == 2) { otg_active_width = otg_active_width / 2; - if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { + if (opp_id_src1 >= num_opp_cap) { ASSERT(false); return; } @@ -826,7 +827,7 @@ enum dc_status dcn20_enable_stream_timing( unsigned int event_triggers = 0; int opp_cnt = 1; int opp_inst[MAX_PIPES] = {0}; - bool interlace = stream->timing.flags.INTERLACE; + bool interlace = (stream->timing.flags.INTERLACE != 0); int i; struct mpc_dwb_flow_control flow_control; struct mpc *mpc = dc->res_pool->mpc; @@ -1405,9 +1406,9 @@ void dcn20_pipe_control_lock( } if (flip_immediate && lock) { - const int TIMEOUT_FOR_FLIP_PENDING_US = 100000; + const unsigned int TIMEOUT_FOR_FLIP_PENDING_US = 100000U; unsigned int polling_interval_us = 1; - int i; + unsigned int i; temp_pipe = pipe; while (temp_pipe) { @@ -1452,7 +1453,7 @@ void dcn20_pipe_control_lock( struct dmub_hw_lock_inst_flags inst_flags = { 0 }; hw_locks.bits.lock_pipe = 1; - inst_flags.otg_inst = pipe->stream_res.tg->inst; + inst_flags.otg_inst = (uint8_t)pipe->stream_res.tg->inst; if (pipe->plane_state != NULL) hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; @@ -1870,7 +1871,7 @@ void dcn20_update_dchubp_dpp( static int dcn20_calculate_vready_offset_for_group(struct pipe_ctx *pipe) { struct pipe_ctx *other_pipe; - int vready_offset = pipe->pipe_dlg_param.vready_offset; + unsigned int vready_offset = pipe->pipe_dlg_param.vready_offset; /* Always use the largest vready_offset of all connected pipes */ for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) { @@ -2038,7 +2039,7 @@ void dcn20_program_front_end_for_ctx( struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; unsigned int prev_hubp_count = 0; unsigned int hubp_count = 0; struct dce_hwseq *hws = dc->hwseq; @@ -2242,7 +2243,7 @@ void dcn20_post_unlock_program_front_end( unsigned int timeout_us = 100000; unsigned int polling_interval_us = 1; struct dce_hwseq *hwseq = dc->hwseq; - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) && @@ -2266,7 +2267,7 @@ void dcn20_post_unlock_program_front_end( if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable && dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) { struct hubp *hubp = pipe->plane_res.hubp; - int j = 0; + unsigned int j = 0; for (j = 0; j < timeout_us / polling_interval_us && hubp->funcs->hubp_is_flip_pending(hubp); j++) @@ -2285,7 +2286,7 @@ void dcn20_post_unlock_program_front_end( if (resource_is_pipe_type(old_pipe, OTG_MASTER) && resource_is_pipe_type(pipe, OTG_MASTER) && resource_get_odm_slice_count(old_pipe) < resource_get_odm_slice_count(pipe) && dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) { - int j = 0; + unsigned int j = 0; struct timing_generator *tg = pipe->stream_res.tg; if (tg->funcs->get_optc_double_buffer_pending) { @@ -2420,7 +2421,7 @@ void dcn20_optimize_bandwidth( struct dc_state *context) { struct hubbub *hubbub = dc->res_pool->hubbub; - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; @@ -2438,10 +2439,13 @@ void dcn20_optimize_bandwidth( dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, true); - if (dc->clk_mgr->dc_mode_softmax_enabled) - if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && - context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) + if (dc->clk_mgr->dc_mode_softmax_enabled) { + int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000; + + if (dc->clk_mgr->clks.dramclk_khz > softmax_memclk_khz && + context->bw_ctx.bw.dcn.clk.dramclk_khz <= softmax_memclk_khz) dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk); + } /* increase compbuf size */ if (hubbub->funcs->program_compbuf_size) @@ -2478,7 +2482,7 @@ bool dcn20_update_bandwidth( struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; struct dce_hwseq *hws = dc->hwseq; /* recalculate DML parameters */ @@ -2733,7 +2737,8 @@ void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); // Call Helper to track VMID use - vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); + vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, + (uint8_t)pipe_ctx->plane_res.hubp->inst); pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( pipe_ctx->plane_res.hubp, @@ -3126,7 +3131,7 @@ void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) void dcn20_fpga_init_hw(struct dc *dc) { - int i, j; + uint8_t i, j; struct dce_hwseq *hws = dc->hwseq; struct resource_pool *res_pool = dc->res_pool; struct dc_state *context = dc->current_state; @@ -3199,7 +3204,7 @@ void dcn20_fpga_init_hw(struct dc *dc) pipe_ctx->plane_res.hubp = hubp; pipe_ctx->plane_res.dpp = dpp; - pipe_ctx->plane_res.mpcc_inst = dpp->inst; + pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst; hubp->mpcc_id = dpp->inst; hubp->opp_id = OPP_ID_INVALID; hubp->power_gated = false; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c index 062745389d9a..476c2112afec 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c @@ -146,10 +146,10 @@ bool dcn21_dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, memset(&cmd, 0, sizeof(cmd)); cmd.abm_set_pipe.header.type = DMUB_CMD__ABM; cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE; - cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst; - cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = pwrseq_inst; - cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = option; - cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = panel_inst; + cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = (uint8_t)otg_inst; + cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = (uint8_t)pwrseq_inst; + cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = (uint8_t)option; + cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = (uint8_t)panel_inst; cmd.abm_set_pipe.abm_set_pipe_data.ramping_boundary = ramping_boundary; cmd.abm_set_pipe.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pipe_data); @@ -287,7 +287,7 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx, bool dcn21_is_abm_supported(struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) { - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index 2aa0f1de8103..a2c8d4b21ac3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -79,7 +79,7 @@ void dcn30_log_color_state(struct dc *dc, struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; bool is_gamut_remap_available = false; - int i; + unsigned int i; DTN_INFO("DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode" " 3DLUT mode 3DLUT bit depth 3DLUT size RGAM mode" @@ -581,7 +581,7 @@ void dcn30_program_all_writeback_pipes_in_tree( struct dc_writeback_info wb_info; struct dwbc *dwb; struct dc_stream_status *stream_status = NULL; - int i_wb, i_pipe, i_stream; + unsigned int i_wb, i_pipe, i_stream; DC_LOG_DWB("%s", __func__); ASSERT(stream); @@ -645,7 +645,7 @@ void dcn30_init_hw(struct dc *dc) struct dce_hwseq *hws = dc->hwseq; struct dc_bios *dcb = dc->ctx->dc_bios; struct resource_pool *res_pool = dc->res_pool; - int i; + unsigned int i; unsigned int edp_num; uint32_t backlight = MAX_BACKLIGHT_LEVEL; uint32_t user_level = MAX_BACKLIGHT_LEVEL; @@ -978,7 +978,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) cursor_cache_enable ? &cursor_attr : NULL)) { unsigned int v_total = stream->adjust.v_total_max ? stream->adjust.v_total_max : stream->timing.v_total; - unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz * + unsigned int refresh_hz = (unsigned int)div_u64((unsigned long long)stream->timing.pix_clk_100hz * 100LL, (v_total * stream->timing.h_total)); /* @@ -1006,9 +1006,9 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) unsigned int denom = refresh_hz * 6528; unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us; - tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * + tmr_delay = (uint32_t)(div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), - denom) - 64LL; + denom) - 64LL); /* In some cases the stutter period is really big (tiny modes) in these * cases MALL cant be enabled, So skip these cases to avoid a ASSERT() @@ -1030,9 +1030,9 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) } denom *= 2; - tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * + tmr_delay = (uint32_t)(div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), - denom) - 64LL; + denom) - 64LL); } /* Copy HW cursor */ @@ -1062,9 +1062,9 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part; cmd.mall.cursor_copy_dst.quad_part = (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047; - cmd.mall.cursor_width = cursor_attr.width; - cmd.mall.cursor_height = cursor_attr.height; - cmd.mall.cursor_pitch = cursor_attr.pitch; + cmd.mall.cursor_width = (uint16_t)cursor_attr.width; + cmd.mall.cursor_height = (uint16_t)cursor_attr.height; + cmd.mall.cursor_pitch = (uint16_t)cursor_attr.pitch; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); @@ -1197,10 +1197,13 @@ void dcn30_prepare_bandwidth(struct dc *dc, context->bw_ctx.bw.dcn.clk.p_state_change_support = false; } - if (dc->clk_mgr->dc_mode_softmax_enabled) - if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && - context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) + if (dc->clk_mgr->dc_mode_softmax_enabled) { + int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000; + + if (dc->clk_mgr->clks.dramclk_khz <= softmax_memclk_khz && + context->bw_ctx.bw.dcn.clk.dramclk_khz > softmax_memclk_khz) dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); + } dcn20_prepare_bandwidth(dc, context); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index b4afb2bc4493..71643ccf23d9 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -72,7 +72,7 @@ static void enable_memory_low_power(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; - int i; + unsigned int i; if (dc->debug.enable_mem_low_power.bits.dmcu) { // Force ERAM to shutdown if DMCU is not enabled @@ -116,7 +116,7 @@ void dcn31_init_hw(struct dc *dc) struct resource_pool *res_pool = dc->res_pool; uint32_t backlight = MAX_BACKLIGHT_LEVEL; uint32_t user_level = MAX_BACKLIGHT_LEVEL; - int i; + unsigned int i; if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); @@ -399,6 +399,9 @@ void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) pipe_ctx->stream_res.hpo_dp_stream_enc, &pipe_ctx->stream_res.encoder_info_frame); + pipe_ctx->stream_res.encoder_info_frame.firmware_controlled_hdr_info_packet + = pipe_ctx->stream->firmware_controlled_hdr_info_packet; + pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets( pipe_ctx->stream_res.hpo_dp_stream_enc, &pipe_ctx->stream_res.encoder_info_frame); @@ -409,6 +412,9 @@ void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) pipe_ctx->stream_res.stream_enc, &pipe_ctx->stream_res.encoder_info_frame); + pipe_ctx->stream_res.encoder_info_frame.firmware_controlled_hdr_info_packet + = pipe_ctx->stream->firmware_controlled_hdr_info_packet; + pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( pipe_ctx->stream_res.stream_enc, &pipe_ctx->stream_res.encoder_info_frame); @@ -665,7 +671,7 @@ void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable) void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_params *params) { - unsigned int i; + int i; unsigned int triggers = 0; if (params->triggers.surface_update) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index 858a06b03b57..408d417318c2 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -211,7 +211,7 @@ void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx if (pipe_ctx->stream_res.dsc) { struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; - update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); + update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0); /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && @@ -232,60 +232,60 @@ void dcn314_dsc_pg_control( uint32_t pwr_status = power_on ? 0 : 2; uint32_t org_ip_request_cntl = 0; - if (hws->ctx->dc->debug.disable_dsc_power_gate) - return; - if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc && hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on) hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( hws->ctx->dc->res_pool->dccg, dsc_inst); - REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); - if (org_ip_request_cntl == 0) - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + if (!hws->ctx->dc->debug.disable_dsc_power_gate) { - switch (dsc_inst) { - case 0: /* DSC0 */ - REG_UPDATE(DOMAIN16_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); - REG_WAIT(DOMAIN16_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - case 1: /* DSC1 */ - REG_UPDATE(DOMAIN17_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); + switch (dsc_inst) { + case 0: /* DSC0 */ + REG_UPDATE(DOMAIN16_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN17_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - case 2: /* DSC2 */ - REG_UPDATE(DOMAIN18_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN16_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 1: /* DSC1 */ + REG_UPDATE(DOMAIN17_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN18_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - case 3: /* DSC3 */ - REG_UPDATE(DOMAIN19_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN17_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 2: /* DSC2 */ + REG_UPDATE(DOMAIN18_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN19_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - default: - BREAK_TO_DEBUGGER(); - break; + REG_WAIT(DOMAIN18_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 3: /* DSC3 */ + REG_UPDATE(DOMAIN19_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN19_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } - if (org_ip_request_cntl == 0) - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); - if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) { if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( @@ -419,7 +419,7 @@ void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc if (dcn314_is_pipe_dig_fifo_on(pipe)) continue; pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg); - reset_sync_context_for_pipe(dc, context, i); + reset_sync_context_for_pipe(dc, context, (uint8_t)i); otg_disabled[i] = true; } } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index b45ceb570a5c..fd42f0afc3a9 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -226,7 +226,7 @@ static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) */ static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) { - int i; + unsigned int i; uint32_t num_ways = 0; uint32_t mall_ss_size_bytes = 0; @@ -351,7 +351,7 @@ bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) */ void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; bool enable_subvp = false; if (!dc->ctx || !dc->ctx->dmub_srv) @@ -607,7 +607,7 @@ bool dcn32_set_output_transfer_func(struct dc *dc, */ void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; /* Unforce p-state for each pipe if it is not FPO or SubVP. * For FPO and SubVP, if it's already forced disallow, leave @@ -674,7 +674,7 @@ void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context) */ void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context); bool cache_cursor = false; @@ -728,7 +728,7 @@ void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) */ void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; struct dce_hwseq *hws = dc->hwseq; // Don't force p-state disallow -- can't block dummy p-state @@ -793,7 +793,7 @@ void dcn32_init_hw(struct dc *dc) struct dce_hwseq *hws = dc->hwseq; struct dc_bios *dcb = dc->ctx->dc_bios; struct resource_pool *res_pool = dc->res_pool; - int i; + unsigned int i; unsigned int edp_num; uint32_t backlight = MAX_BACKLIGHT_LEVEL; uint32_t user_level = MAX_BACKLIGHT_LEVEL; @@ -1175,7 +1175,7 @@ void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx * if (pipe_ctx->stream_res.dsc) { struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; - dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); + dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0); /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && @@ -1277,7 +1277,7 @@ void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_ if ((pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal)) && dc_state_get_pipe_subvp_type(dc_state, pipe) != SUBVP_PHANTOM) { pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg); - reset_sync_context_for_pipe(dc, context, i); + reset_sync_context_for_pipe(dc, context, (uint8_t)i); otg_disabled[i] = true; } } @@ -1655,6 +1655,7 @@ void dcn32_init_blank( uint32_t num_opps, opp_id_src0, opp_id_src1; uint32_t otg_active_width = 0, otg_active_height = 0; uint32_t i; + unsigned int num_opp_cap = (unsigned int)dc->res_pool->res_cap->num_opp; /* program opp dpg blank color */ color_space = COLOR_SPACE_SRGB; @@ -1668,12 +1669,12 @@ void dcn32_init_blank( /* get the OPTC source */ tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); - if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { + if (opp_id_src0 >= num_opp_cap) { ASSERT(false); return; } - for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { + for (i = 0; i < num_opp_cap; i++) { if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) { opp = dc->res_pool->opps[i]; break; @@ -1683,11 +1684,11 @@ void dcn32_init_blank( if (num_opps == 2) { otg_active_width = otg_active_width / 2; - if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { + if (opp_id_src1 >= num_opp_cap) { ASSERT(false); return; } - for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { + for (i = 0; i < num_opp_cap; i++) { if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) { bottom_opp = dc->res_pool->opps[i]; break; @@ -1751,7 +1752,7 @@ bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc, const struct dc_state *cur_ctx, const struct dc_state *new_ctx) { - int i; + unsigned int i; const struct pipe_ctx *cur_pipe, *new_pipe; bool is_seamless = true; @@ -1812,10 +1813,13 @@ void dcn32_prepare_bandwidth(struct dc *dc, context->bw_ctx.bw.dcn.clk.p_state_change_support = false; } - if (dc->clk_mgr->dc_mode_softmax_enabled) - if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && - context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) + if (dc->clk_mgr->dc_mode_softmax_enabled) { + int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000; + + if (dc->clk_mgr->clks.dramclk_khz <= softmax_memclk_khz && + context->bw_ctx.bw.dcn.clk.dramclk_khz > softmax_memclk_khz) dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); + } dcn20_prepare_bandwidth(dc, context); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index f133b52ea958..a094c8b40a85 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -145,7 +145,7 @@ void dcn35_init_hw(struct dc *dc) struct resource_pool *res_pool = dc->res_pool; uint32_t backlight = MAX_BACKLIGHT_LEVEL; uint32_t user_level = MAX_BACKLIGHT_LEVEL; - int i; + unsigned int i; print_pg_status(dc, __func__, ": start"); @@ -467,7 +467,7 @@ void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx * if (pipe_ctx->stream_res.dsc) { struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; - update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); + update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0); /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && @@ -621,7 +621,7 @@ void dcn35_z10_restore(const struct dc *dc) void dcn35_init_pipes(struct dc *dc, struct dc_state *context) { - int i; + uint8_t i; struct dce_hwseq *hws = dc->hwseq; struct hubbub *hubbub = dc->res_pool->hubbub; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; @@ -725,7 +725,7 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context) pipe_ctx->plane_res.hubp = hubp; pipe_ctx->plane_res.dpp = dpp; - pipe_ctx->plane_res.mpcc_inst = dpp->inst; + pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst; hubp->mpcc_id = dpp->inst; hubp->opp_id = OPP_ID_INVALID; hubp->power_gated = false; @@ -904,6 +904,13 @@ void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) return; + if (dc->debug.disable_dpp_power_gate) { + /* Workaround for use case when disabled power gating set to 1 */ + /* Force disable cursor if power gating is disabled */ + struct dpp *dpp = pipe_ctx->plane_res.dpp; + if (dpp && dpp->funcs->dpp_force_disable_cursor) + dpp->funcs->dpp_force_disable_cursor(dpp); + } if (hws->funcs.plane_atomic_disable) hws->funcs.plane_atomic_disable(dc, pipe_ctx); @@ -923,14 +930,15 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, bool hpo_frl_stream_enc_acquired = false; bool hpo_dp_stream_enc_acquired = false; int i = 0, j = 0; + unsigned int ui = 0, uj = 0; unsigned int edp_num = 0; struct dc_link *edp_links[MAX_NUM_EDP] = { NULL }; memset(update_state, 0, sizeof(struct pg_block_update)); - for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) { - if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i] && - dc->res_pool->hpo_dp_stream_enc[i]) { + for (ui = 0; ui < dc->res_pool->hpo_dp_stream_enc_count; ui++) { + if (context->res_ctx.is_hpo_dp_stream_enc_acquired[ui] && + dc->res_pool->hpo_dp_stream_enc[ui]) { hpo_dp_stream_enc_acquired = true; break; } @@ -941,11 +949,11 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, update_state->pg_res_update[PG_DWB] = true; - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + for (ui = 0; ui < dc->res_pool->pipe_count; ui++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[ui]; for (j = 0; j < PG_HW_PIPE_RESOURCES_NUM_ELEMENT; j++) - update_state->pg_pipe_res_update[j][i] = true; + update_state->pg_pipe_res_update[j][ui] = true; if (!pipe_ctx) continue; @@ -968,9 +976,9 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, /* All HUBP/DPP instances must be powered if the DSC inst != HUBP inst */ if (!pipe_ctx->top_pipe && pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->inst != pipe_ctx->stream_res.dsc->inst) { - for (j = 0; j < dc->res_pool->pipe_count; ++j) { - update_state->pg_pipe_res_update[PG_HUBP][j] = false; - update_state->pg_pipe_res_update[PG_DPP][j] = false; + for (uj = 0; uj < dc->res_pool->pipe_count; ++uj) { + update_state->pg_pipe_res_update[PG_HUBP][uj] = false; + update_state->pg_pipe_res_update[PG_DPP][uj] = false; } } } @@ -990,10 +998,10 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, } /*domain24 controls all the otg, mpc, opp, as long as one otg is still up, avoid enabling OTG PG*/ - for (i = 0; i < dc->res_pool->timing_generator_count; i++) { - struct timing_generator *tg = dc->res_pool->timing_generators[i]; + for (ui = 0; ui < dc->res_pool->timing_generator_count; ui++) { + struct timing_generator *tg = dc->res_pool->timing_generators[ui]; if (tg && tg->funcs->is_tg_enabled(tg)) { - update_state->pg_pipe_res_update[PG_OPTC][i] = false; + update_state->pg_pipe_res_update[PG_OPTC][ui] = false; break; } } @@ -1027,10 +1035,11 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, bool hpo_frl_stream_enc_acquired = false; bool hpo_dp_stream_enc_acquired = false; int i = 0, j = 0; + unsigned int ui = 0, uj = 0; memset(update_state, 0, sizeof(struct pg_block_update)); - for (i = 0; i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < (int)dc->res_pool->pipe_count; i++) { struct pipe_ctx *cur_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; @@ -1104,9 +1113,9 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, if (dc->links[i]->type != dc_connection_none) update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true; - for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) { - if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i] && - dc->res_pool->hpo_dp_stream_enc[i]) { + for (ui = 0; ui < dc->res_pool->hpo_dp_stream_enc_count; ui++) { + if (context->res_ctx.is_hpo_dp_stream_enc_acquired[ui] && + dc->res_pool->hpo_dp_stream_enc[ui]) { hpo_dp_stream_enc_acquired = true; break; } @@ -1119,8 +1128,8 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true; if (dc->caps.sequential_ono) { - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; + for (ui = 0; ui < dc->res_pool->pipe_count; ui++) { + struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[ui]; if (new_pipe->stream_res.dsc && !new_pipe->top_pipe && update_state->pg_pipe_res_update[PG_DSC][new_pipe->stream_res.dsc->inst]) { @@ -1130,9 +1139,9 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, /* All HUBP/DPP instances must be powered if the DSC inst != HUBP inst */ if (new_pipe->plane_res.hubp && new_pipe->plane_res.hubp->inst != new_pipe->stream_res.dsc->inst) { - for (j = 0; j < dc->res_pool->pipe_count; ++j) { - update_state->pg_pipe_res_update[PG_HUBP][j] = true; - update_state->pg_pipe_res_update[PG_DPP][j] = true; + for (uj = 0; uj < dc->res_pool->pipe_count; ++uj) { + update_state->pg_pipe_res_update[PG_HUBP][uj] = true; + update_state->pg_pipe_res_update[PG_DPP][uj] = true; } } } @@ -1179,6 +1188,7 @@ void dcn35_hw_block_power_down(struct dc *dc, struct pg_block_update *update_state) { int i = 0; + unsigned int pipe_idx = 0; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; if (!pg_cntl) @@ -1192,11 +1202,11 @@ void dcn35_hw_block_power_down(struct dc *dc, } if (!dc->caps.sequential_ono) { - for (i = 0; i < dc->res_pool->pipe_count; i++) { - if (update_state->pg_pipe_res_update[PG_HUBP][i] && - update_state->pg_pipe_res_update[PG_DPP][i]) { + for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { + if (update_state->pg_pipe_res_update[PG_HUBP][pipe_idx] && + update_state->pg_pipe_res_update[PG_DPP][pipe_idx]) { if (pg_cntl->funcs->hubp_dpp_pg_control) - pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false); + pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, pipe_idx, false); } } @@ -1255,7 +1265,7 @@ void dcn35_hw_block_power_down(struct dc *dc, void dcn35_hw_block_power_up(struct dc *dc, struct pg_block_update *update_state) { - int i = 0; + unsigned int i = 0; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; if (!pg_cntl) @@ -1268,7 +1278,7 @@ void dcn35_hw_block_power_up(struct dc *dc, pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true); if (!dc->caps.sequential_ono) { - for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) + for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) if (update_state->pg_pipe_res_update[PG_DSC][i]) { if (pg_cntl->funcs->dsc_pg_control) pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true); @@ -1297,7 +1307,7 @@ void dcn35_hw_block_power_up(struct dc *dc, void dcn35_root_clock_control(struct dc *dc, struct pg_block_update *update_state, bool power_on) { - int i = 0; + unsigned int i = 0; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; if (!pg_cntl) @@ -1321,7 +1331,7 @@ void dcn35_root_clock_control(struct dc *dc, dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on); } - for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) { if (update_state->pg_pipe_res_update[PG_DSC][i]) { if (power_on) { if (dc->res_pool->dccg->funcs->enable_dsc) @@ -1442,7 +1452,7 @@ void dcn35_set_drr(struct pipe_ctx **pipe_ctx, void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_params *params) { - unsigned int i; + int i; unsigned int triggers = 0; if (params->triggers.surface_update) @@ -1562,7 +1572,8 @@ bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx) */ static void dcn35_calc_blocks_to_ungate_for_hw_release(struct dc *dc, struct pg_block_update *update_state) { - int i = 0, j = 0; + unsigned int i = 0; + int j = 0; memset(update_state, 0, sizeof(struct pg_block_update)); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c index 93fe5b262a3d..8720e47fb33a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c @@ -152,7 +152,7 @@ void dcn351_hw_block_power_down(struct dc *dc, void dcn351_hw_block_power_up(struct dc *dc, struct pg_block_update *update_state) { - int i = 0; + unsigned int i = 0; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; if (!pg_cntl || dc->debug.ignore_pg) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 9768b8f6b6fb..d4a118e047b7 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -95,6 +95,10 @@ void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx) unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst; struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; + //For now assert if location is not pre-blend + if (pipe_ctx->plane_state) + ASSERT(pipe_ctx->plane_state->mcm_location == MPCC_MOVABLE_CM_LOCATION_BEFORE); + // program MPCC_MCM_FIRST_GAMUT_REMAP memset(&mpc_adjust, 0, sizeof(mpc_adjust)); mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; @@ -139,7 +143,7 @@ void dcn401_init_hw(struct dc *dc) struct dce_hwseq *hws = dc->hwseq; struct dc_bios *dcb = dc->ctx->dc_bios; struct resource_pool *res_pool = dc->res_pool; - int i; + unsigned int i; unsigned int edp_num; uint32_t backlight = MAX_BACKLIGHT_LEVEL; uint32_t user_level = MAX_BACKLIGHT_LEVEL; @@ -374,6 +378,242 @@ void dcn401_init_hw(struct dc *dc) } } +static void dcn401_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx, + enum MCM_LUT_XABLE *shaper_xable, + enum MCM_LUT_XABLE *lut3d_xable, + enum MCM_LUT_XABLE *lut1d_xable) +{ + enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting = DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL; + bool lut1d_enable = false; + struct mpc *mpc = dc->res_pool->mpc; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + + if (!pipe_ctx->plane_state) + return; + shaper_3dlut_setting = pipe_ctx->plane_state->mcm_shaper_3dlut_setting; + lut1d_enable = pipe_ctx->plane_state->mcm_lut1d_enable; + mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); + pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; + + *lut1d_xable = lut1d_enable ? MCM_LUT_ENABLE : MCM_LUT_DISABLE; + + switch (shaper_3dlut_setting) { + case DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL: + *lut3d_xable = *shaper_xable = MCM_LUT_DISABLE; + break; + case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER: + *lut3d_xable = MCM_LUT_DISABLE; + *shaper_xable = MCM_LUT_ENABLE; + break; + case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT: + *lut3d_xable = *shaper_xable = MCM_LUT_ENABLE; + break; + } +} + +void dcn401_populate_mcm_luts(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_cm2_func_luts mcm_luts, + bool lut_bank_a) +{ + struct dpp *dpp_base = pipe_ctx->plane_res.dpp; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + int mpcc_id = hubp->inst; + struct mpc *mpc = dc->res_pool->mpc; + union mcm_lut_params m_lut_params; + enum dc_cm2_transfer_func_source lut3d_src = mcm_luts.lut3d_data.lut3d_src; + enum hubp_3dlut_fl_format format = 0; + enum hubp_3dlut_fl_mode mode; + enum hubp_3dlut_fl_width width = 0; + enum hubp_3dlut_fl_addressing_mode addr_mode; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g = 0; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b = 0; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r = 0; + enum MCM_LUT_XABLE shaper_xable = MCM_LUT_DISABLE; + enum MCM_LUT_XABLE lut3d_xable = MCM_LUT_DISABLE; + enum MCM_LUT_XABLE lut1d_xable = MCM_LUT_DISABLE; + bool rval; + + dcn401_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable); + + /* 1D LUT */ + if (mcm_luts.lut1d_func) { + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (mcm_luts.lut1d_func->type == TF_TYPE_HWPWL) + m_lut_params.pwl = &mcm_luts.lut1d_func->pwl; + else if (mcm_luts.lut1d_func->type == TF_TYPE_DISTRIBUTED_POINTS) { + rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, + mcm_luts.lut1d_func, + &dpp_base->regamma_params, false); + m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; + } + if (m_lut_params.pwl) { + if (mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, m_lut_params, lut_bank_a, mpcc_id); + } + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut1d_xable && m_lut_params.pwl, lut_bank_a, mpcc_id); + } + + /* Shaper */ + if (mcm_luts.shaper && mcm_luts.lut3d_data.mpc_3dlut_enable) { + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (mcm_luts.shaper->type == TF_TYPE_HWPWL) + m_lut_params.pwl = &mcm_luts.shaper->pwl; + else if (mcm_luts.shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { + ASSERT(false); + rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, + mcm_luts.shaper, + &dpp_base->regamma_params, true); + m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; + } + if (m_lut_params.pwl) { + if (mpc->funcs->mcm.populate_lut) + mpc->funcs->mcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id); + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_ENABLE, lut_bank_a, mpcc_id); + } + } + + /* 3DLUT */ + switch (lut3d_src) { + case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, false); + + if (mcm_luts.lut3d_data.lut3d_func && mcm_luts.lut3d_data.lut3d_func->state.bits.initialized) { + m_lut_params.lut3d = &mcm_luts.lut3d_data.lut3d_func->lut_3d; + if (mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, m_lut_params, lut_bank_a, mpcc_id); + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, + mpcc_id); + } + break; + case DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM: + switch (mcm_luts.lut3d_data.gpu_mem_params.size) { +#if defined(CONFIG_DRM_AMD_DC_DCN4_2) + case DC_CM2_GPU_MEM_SIZE_333333: + if (dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33) + width = hubp_3dlut_fl_width_33; + break; +#endif + case DC_CM2_GPU_MEM_SIZE_171717: + width = hubp_3dlut_fl_width_17; + break; + case DC_CM2_GPU_MEM_SIZE_TRANSFORMED: + width = hubp_3dlut_fl_width_transformed; + break; + default: + //TODO: handle default case + break; + } + + //check for support + if (mpc->funcs->mcm.is_config_supported && + !mpc->funcs->mcm.is_config_supported(width)) + break; + + if (mpc->funcs->program_lut_read_write_control) + mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, mpcc_id); + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, mpcc_id); + + if (hubp->funcs->hubp_program_3dlut_fl_addr) + hubp->funcs->hubp_program_3dlut_fl_addr(hubp, mcm_luts.lut3d_data.gpu_mem_params.addr); + + if (mpc->funcs->mcm.program_bit_depth) + mpc->funcs->mcm.program_bit_depth(mpc, mcm_luts.lut3d_data.gpu_mem_params.bit_depth, mpcc_id); + + switch (mcm_luts.lut3d_data.gpu_mem_params.layout) { + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB: + mode = hubp_3dlut_fl_mode_native_1; + addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR: + mode = hubp_3dlut_fl_mode_native_2; + addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR: + mode = hubp_3dlut_fl_mode_transform; + addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; + break; + default: + mode = hubp_3dlut_fl_mode_disable; + addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + } + if (hubp->funcs->hubp_program_3dlut_fl_mode) + hubp->funcs->hubp_program_3dlut_fl_mode(hubp, mode); + + if (hubp->funcs->hubp_program_3dlut_fl_addressing_mode) + hubp->funcs->hubp_program_3dlut_fl_addressing_mode(hubp, addr_mode); + + switch (mcm_luts.lut3d_data.gpu_mem_params.format_params.format) { + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB: + format = hubp_3dlut_fl_format_unorm_12msb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB: + format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10: + format = hubp_3dlut_fl_format_float_fp1_5_10; + break; + } + if (hubp->funcs->hubp_program_3dlut_fl_format) + hubp->funcs->hubp_program_3dlut_fl_format(hubp, format); + if (hubp->funcs->hubp_update_3dlut_fl_bias_scale && + mpc->funcs->mcm.program_bias_scale) { + mpc->funcs->mcm.program_bias_scale(mpc, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale, + mpcc_id); + hubp->funcs->hubp_update_3dlut_fl_bias_scale(hubp, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale); + } + + //navi 4x has a bug and r and blue are swapped and need to be worked around here in + //TODO: need to make a method for get_xbar per asic OR do the workaround in program_crossbar for 4x + switch (mcm_luts.lut3d_data.gpu_mem_params.component_order) { + case DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA: + default: + crossbar_bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; + crossbar_bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + crossbar_bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; + break; + } + + if (hubp->funcs->hubp_program_3dlut_fl_crossbar) + hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, + crossbar_bit_slice_cr_r, + crossbar_bit_slice_y_g, + crossbar_bit_slice_cb_b); + + if (mpc->funcs->mcm.program_lut_read_write_control) + mpc->funcs->mcm.program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, true, mpcc_id); + + if (mpc->funcs->mcm.program_3dlut_size) + mpc->funcs->mcm.program_3dlut_size(mpc, width, mpcc_id); + + if (mpc->funcs->update_3dlut_fast_load_select) + mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst); + + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, true); + else { + if (mpc->funcs->program_lut_mode) { + mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); + mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); + } + } + break; + + } +} + void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx) { (void)dc; @@ -387,167 +627,51 @@ void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx) bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) { - struct dc *dc = pipe_ctx->plane_res.hubp->ctx->dc; struct dpp *dpp_base = pipe_ctx->plane_res.dpp; - struct hubp *hubp = pipe_ctx->plane_res.hubp; - const struct dc_plane_cm *cm = &plane_state->cm; - int mpcc_id = hubp->inst; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc; struct mpc *mpc = dc->res_pool->mpc; - union mcm_lut_params m_lut_params; - struct dc_3dlut_dma lut3d_dma; - bool lut_enable; - bool lut_bank_a; + bool result; + const struct pwl_params *lut_params = NULL; bool rval; - bool result = true; - /* decide LUT bank based on current in use */ - mpc->funcs->get_lut_mode(mpc, MCM_LUT_1DLUT, mpcc_id, &lut_enable, &lut_bank_a); - if (!lut_enable) { - mpc->funcs->get_lut_mode(mpc, MCM_LUT_SHAPER, mpcc_id, &lut_enable, &lut_bank_a); - } - if (!lut_enable) { - mpc->funcs->get_lut_mode(mpc, MCM_LUT_3DLUT, mpcc_id, &lut_enable, &lut_bank_a); + if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { + dcn401_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a); + return true; } - /* switch to the next bank */ - if (lut_enable) { - lut_bank_a = !lut_bank_a; - } - - /* MCM location fixed to pre-blend */ mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); - - /* 1D LUT */ - lut_enable = cm->flags.bits.blend_enable; - memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (lut_enable) { - if (cm->blend_func.type == TF_TYPE_HWPWL) - m_lut_params.pwl = &cm->blend_func.pwl; - else if (cm->blend_func.type == TF_TYPE_DISTRIBUTED_POINTS) { - rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, - &cm->blend_func, - &dpp_base->regamma_params, - false); - m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; - } - - if (!m_lut_params.pwl) { - lut_enable = false; - } - } else { - lut_enable = false; + pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; + // 1D LUT + if (plane_state->blend_tf.type == TF_TYPE_HWPWL) + lut_params = &plane_state->blend_tf.pwl; + else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) { + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->blend_tf, + &dpp_base->regamma_params, false); + lut_params = rval ? &dpp_base->regamma_params : NULL; } + result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); + lut_params = NULL; - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut_enable, lut_bank_a, CM_LUT_SIZE_NONE, mpcc_id); - if (lut_enable && mpc->funcs->populate_lut) - mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, &m_lut_params, lut_bank_a, mpcc_id); - - /* Shaper */ - lut_enable = cm->flags.bits.shaper_enable; - if (lut_enable) { - memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (cm->shaper_func.type == TF_TYPE_HWPWL) - m_lut_params.pwl = &cm->shaper_func.pwl; - else if (cm->shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { - ASSERT(false); - rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, - &cm->shaper_func, - &dpp_base->shaper_params, - true); - m_lut_params.pwl = rval ? &dpp_base->shaper_params : NULL; - } - if (!m_lut_params.pwl) { - lut_enable = false; - } - } else { - lut_enable = false; + // Shaper + if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL) + lut_params = &plane_state->in_shaper_func.pwl; + else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { + // TODO: dpp_base replace + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->in_shaper_func, + &dpp_base->shaper_params, true); + lut_params = rval ? &dpp_base->shaper_params : NULL; } + result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, lut_enable, lut_bank_a, CM_LUT_SIZE_NONE, mpcc_id); - if (lut_enable && mpc->funcs->populate_lut) - mpc->funcs->populate_lut(mpc, MCM_LUT_SHAPER, &m_lut_params, lut_bank_a, mpcc_id); - - /* NOTE: Toggling from DMA->Host is not supported atomically as hardware - * blocks writes until 3DLUT FL mode is cleared from HUBP on VUpdate. - * Expectation is either option is used consistently. - */ - - /* 3DLUT */ - lut_enable = cm->flags.bits.lut3d_enable; - if (lut_enable && cm->flags.bits.lut3d_dma_enable) { - /* Fast (DMA) Load Mode */ - /* MPC */ - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut_enable, lut_bank_a, cm->lut3d_dma.size, mpcc_id); - - /* only supports 12 bit */ - if (mpc->funcs->program_lut_read_write_control) - mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, 12, mpcc_id); - - if (mpc->funcs->update_3dlut_fast_load_select) - mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst); - - /* HUBP */ - if (hubp->funcs->hubp_program_3dlut_fl_config) - hubp->funcs->hubp_program_3dlut_fl_config(hubp, &cm->lut3d_dma); - - if (hubp->funcs->hubp_program_3dlut_fl_crossbar) - hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, cm->lut3d_dma.format); - - if (hubp->funcs->hubp_program_3dlut_fl_addr) - hubp->funcs->hubp_program_3dlut_fl_addr(hubp, &cm->lut3d_dma.addr); - - if (hubp->funcs->hubp_enable_3dlut_fl) { - hubp->funcs->hubp_enable_3dlut_fl(hubp, true); - } else { - /* GPU memory only supports fast load path */ - BREAK_TO_DEBUGGER(); - lut_enable = false; - result = false; - } - } else { - /* Legacy (Host) Load Mode */ - memset(&m_lut_params, 0, sizeof(m_lut_params)); - - if (cm->flags.bits.lut3d_enable && cm->lut3d_func.state.bits.initialized) { - m_lut_params.lut3d = &cm->lut3d_func.lut_3d; - } else { - lut_enable = false; - } - - /* MPC */ - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, - MCM_LUT_3DLUT, - lut_enable, - lut_bank_a, - cm->lut3d_func.lut_3d.use_tetrahedral_9 ? CM_LUT_SIZE_999 : CM_LUT_SIZE_171717, - mpcc_id); - - if (lut_enable) { - if (mpc->funcs->program_lut_read_write_control) - mpc->funcs->program_lut_read_write_control(mpc, - MCM_LUT_3DLUT, - lut_bank_a, - cm->lut3d_func.lut_3d.use_12bits ? 12 : 10, - mpcc_id); - - if (mpc->funcs->update_3dlut_fast_load_select) - mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, 0xf); - - if (mpc->funcs->populate_lut) - mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, &m_lut_params, lut_bank_a, mpcc_id); - } - - /* HUBP */ - memset(&lut3d_dma, 0, sizeof(lut3d_dma)); - if (hubp->funcs->hubp_program_3dlut_fl_config) - hubp->funcs->hubp_program_3dlut_fl_config(hubp, &lut3d_dma); - - if (hubp->funcs->hubp_enable_3dlut_fl) - hubp->funcs->hubp_enable_3dlut_fl(hubp, false); + // 3D + if (mpc->funcs->program_3dlut) { + if (plane_state->lut3d_func.state.bits.initialized == 1) + result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id); + else + result &= mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); } return result; @@ -1157,8 +1281,8 @@ static bool dcn401_check_no_memory_request_for_cab(struct dc *dc) static uint32_t dcn401_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) { - int i; - uint8_t num_ways = 0; + unsigned int i; + uint32_t num_ways = 0; uint32_t mall_ss_size_bytes = 0; mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes; @@ -1189,7 +1313,8 @@ static uint32_t dcn401_calculate_cab_allocation(struct dc *dc, struct dc_state * bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable) { union dmub_rb_cmd cmd; - uint8_t ways, i; + uint32_t ways; + uint8_t i; int j; bool mall_ss_unsupported = false; struct dc_plane_state *plane = NULL; @@ -1242,7 +1367,7 @@ bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable) } if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) { cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB; - cmd.cab.cab_alloc_ways = ways; + cmd.cab.cab_alloc_ways = (uint8_t)ways; DC_LOG_MALL("cab allocation: %d ways. CAB action: DCN_SS_FIT_IN_CAB\n", ways); } else { cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB; @@ -1298,10 +1423,13 @@ void dcn401_prepare_bandwidth(struct dc *dc, context->bw_ctx.bw.dcn.clk.p_state_change_support = false; } - if (dc->clk_mgr->dc_mode_softmax_enabled) - if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && - context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) + if (dc->clk_mgr->dc_mode_softmax_enabled) { + int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000; + + if (dc->clk_mgr->clks.dramclk_khz <= softmax_memclk_khz && + context->bw_ctx.bw.dcn.clk.dramclk_khz > softmax_memclk_khz) dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); + } /* Increase clocks */ dc->clk_mgr->funcs->update_clocks( @@ -1347,7 +1475,7 @@ void dcn401_optimize_bandwidth( struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; struct hubbub *hubbub = dc->res_pool->hubbub; /* enable fams2 if needed */ @@ -1367,10 +1495,13 @@ void dcn401_optimize_bandwidth( hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs, true); } - if (dc->clk_mgr->dc_mode_softmax_enabled) - if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && - context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) + if (dc->clk_mgr->dc_mode_softmax_enabled) { + int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000; + + if (dc->clk_mgr->clks.dramclk_khz > softmax_memclk_khz && + context->bw_ctx.bw.dcn.clk.dramclk_khz <= softmax_memclk_khz) dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk); + } /* increase compbuf size */ if (hubbub->funcs->program_compbuf_segments) @@ -1433,12 +1564,15 @@ void dcn401_dmub_hw_control_lock_fast(union block_sequence_params *params) void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable) { bool fams2_info_required; + bool fams2_enabled; + bool fams2_legacy_no_fams2; if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable) return; - fams2_info_required = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable; - fams2_info_required |= context->bw_ctx.bw.dcn.fams2_global_config.features.bits.legacy_method_no_fams2; + fams2_enabled = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable != 0u; + fams2_legacy_no_fams2 = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.legacy_method_no_fams2 != 0u; + fams2_info_required = fams2_enabled || fams2_legacy_no_fams2; dc_dmub_srv_fams2_update_config(dc, context, enable && fams2_info_required); } @@ -1470,7 +1604,7 @@ static void update_dsc_for_odm_change(struct dc *dc, struct dc_state *context, if (otg_master->stream_res.dsc) dcn32_update_dsc_on_stream(otg_master, - otg_master->stream->timing.flags.DSC); + otg_master->stream->timing.flags.DSC != 0u); if (old_otg_master && old_otg_master->stream_res.dsc) { for (i = 0; i < old_opp_head_count; i++) { old_pipe = old_opp_heads[i]; @@ -1824,9 +1958,10 @@ void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx) for (odm_pipe = pipe_ctx; odm_pipe != NULL; odm_pipe = odm_pipe->next_odm_pipe) { for (mpc_pipe = odm_pipe; mpc_pipe != NULL; mpc_pipe = mpc_pipe->bottom_pipe) { - if (mpc_pipe->plane_state && - mpc_pipe->plane_state->cm.flags.bits.lut3d_enable && - mpc_pipe->plane_state->cm.flags.bits.lut3d_dma_enable) { + if (mpc_pipe->plane_state && mpc_pipe->plane_state->mcm_luts.lut3d_data.lut3d_src + == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM + && mpc_pipe->plane_state->mcm_shaper_3dlut_setting + == DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT) { wa_pipes[wa_pipe_ct++] = mpc_pipe; } } @@ -2337,7 +2472,7 @@ void dcn401_program_front_end_for_ctx( struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; unsigned int prev_hubp_count = 0; unsigned int hubp_count = 0; struct dce_hwseq *hws = dc->hwseq; @@ -2504,7 +2639,7 @@ void dcn401_post_unlock_program_front_end( unsigned int timeout_us = 100000; unsigned int polling_interval_us = 1; struct dce_hwseq *hwseq = dc->hwseq; - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) && @@ -2528,7 +2663,7 @@ void dcn401_post_unlock_program_front_end( if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable && dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) { struct hubp *hubp = pipe->plane_res.hubp; - int j = 0; + unsigned int j = 0; for (j = 0; j < timeout_us / polling_interval_us && hubp->funcs->hubp_is_flip_pending(hubp); j++) @@ -2547,7 +2682,7 @@ void dcn401_post_unlock_program_front_end( if (resource_is_pipe_type(old_pipe, OTG_MASTER) && resource_is_pipe_type(pipe, OTG_MASTER) && resource_get_odm_slice_count(old_pipe) < resource_get_odm_slice_count(pipe) && dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) { - int j = 0; + unsigned int j = 0; struct timing_generator *tg = pipe->stream_res.tg; if (tg->funcs->get_optc_double_buffer_pending) { @@ -2632,7 +2767,7 @@ bool dcn401_update_bandwidth( struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; struct dce_hwseq *hws = dc->hwseq; /* recalculate DML parameters */ @@ -3133,9 +3268,10 @@ void dcn401_program_all_writeback_pipes_in_tree_sequence( struct block_sequence_state *seq_state) { struct dwbc *dwb; - int i_wb, i_pipe; + unsigned int i_wb, i_pipe; + unsigned int num_dwb_cap = (unsigned int)dc->res_pool->res_cap->num_dwb; - if (!stream || stream->num_wb_info > dc->res_pool->res_cap->num_dwb) + if (!stream || (unsigned int)stream->num_wb_info > num_dwb_cap) return; /* For each writeback pipe */ @@ -3297,7 +3433,7 @@ void dcn401_setup_gsl_group_as_lock_sequence( group_idx = find_free_gsl_group(dc); ASSERT(group_idx != 0); - pipe_ctx->stream_res.gsl_group = group_idx; + pipe_ctx->stream_res.gsl_group = (uint8_t)group_idx; /* set gsl group reg field and mark resource used */ switch (group_idx) { @@ -3783,7 +3919,7 @@ void dcn401_update_mpcc_sequence(struct dc *dc, static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) { - int i; + unsigned int i; for (i = 0; i < res_pool->pipe_count; i++) { if (res_pool->hubps[i]->inst == mpcc_inst) @@ -3858,7 +3994,7 @@ void dcn401_set_hdr_multiplier_sequence(struct pipe_ctx *pipe_ctx, void dcn401_program_mall_pipe_config_sequence(struct dc *dc, struct dc_state *context, struct block_sequence_state *seq_state) { - int i; + unsigned int i; unsigned int num_ways = dcn401_calculate_cab_allocation(dc, context); bool cache_cursor = false; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c index 46f2f9833d9e..cbc20f214f9e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c @@ -35,7 +35,6 @@ #include "dc_stream_priv.h" #include "dcn35/dcn35_hwseq.h" #include "dcn42/dcn42_hwseq.h" -#include "dce/dmub_hw_lock_mgr.h" #include "dio/dcn10/dcn10_dio.h" #define DC_LOGGER \ @@ -65,7 +64,7 @@ void dcn42_init_hw(struct dc *dc) struct dce_hwseq *hws = dc->hwseq; struct dc_bios *dcb = dc->ctx->dc_bios; struct resource_pool *res_pool = dc->res_pool; - int i; + unsigned int i; unsigned int edp_num; uint32_t backlight = MAX_BACKLIGHT_LEVEL; uint32_t user_level = MAX_BACKLIGHT_LEVEL; @@ -394,6 +393,68 @@ void dcn42_program_cm_hist( plane_state->cm_hist_control, plane_state->color_space); } +static void dc_get_lut_xbar( + enum dc_cm2_gpu_mem_pixel_component_order order, + enum hubp_3dlut_fl_crossbar_bit_slice *cr_r, + enum hubp_3dlut_fl_crossbar_bit_slice *y_g, + enum hubp_3dlut_fl_crossbar_bit_slice *cb_b) +{ + switch (order) { + case DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA: + *cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; + *y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + *cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; + break; + case DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_BGRA: + *cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; + *y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + *cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; + break; + } +} + +static void dc_get_lut_mode( + enum dc_cm2_gpu_mem_layout layout, + enum hubp_3dlut_fl_mode *mode, + enum hubp_3dlut_fl_addressing_mode *addr_mode) +{ + switch (layout) { + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB: + *mode = hubp_3dlut_fl_mode_native_1; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR: + *mode = hubp_3dlut_fl_mode_native_2; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR: + *mode = hubp_3dlut_fl_mode_transform; + *addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; + break; + default: + *mode = hubp_3dlut_fl_mode_disable; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + } +} + +static void dc_get_lut_format( + enum dc_cm2_gpu_mem_format dc_format, + enum hubp_3dlut_fl_format *format) +{ + switch (dc_format) { + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB: + *format = hubp_3dlut_fl_format_unorm_12msb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB: + *format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10: + *format = hubp_3dlut_fl_format_float_fp1_5_10; + break; + } +} + static bool dc_is_rmcm_3dlut_supported(struct hubp *hubp, struct mpc *mpc) { if (mpc->funcs->rmcm.power_on_shaper_3dlut && @@ -404,17 +465,119 @@ static bool dc_is_rmcm_3dlut_supported(struct hubp *hubp, struct mpc *mpc) return false; } +static bool is_rmcm_3dlut_fl_supported(struct dc *dc, enum dc_cm2_gpu_mem_size size) +{ + if (!dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut) + return false; + if (size == DC_CM2_GPU_MEM_SIZE_171717) + return (dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17); + else if (size == DC_CM2_GPU_MEM_SIZE_333333) + return (dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33); + return false; +} + +static void dcn42_set_mcm_location_post_blend(struct dc *dc, struct pipe_ctx *pipe_ctx, bool bPostBlend) +{ + struct mpc *mpc = dc->res_pool->mpc; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + + if (!pipe_ctx->plane_state) + return; + + mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); + pipe_ctx->plane_state->mcm_location = (bPostBlend) ? + MPCC_MOVABLE_CM_LOCATION_AFTER : + MPCC_MOVABLE_CM_LOCATION_BEFORE; +} + +static void dcn42_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx, + enum MCM_LUT_XABLE *shaper_xable, + enum MCM_LUT_XABLE *lut3d_xable, + enum MCM_LUT_XABLE *lut1d_xable) +{ + enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting = DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL; + bool lut1d_enable = false; + struct mpc *mpc = dc->res_pool->mpc; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + + if (!pipe_ctx->plane_state) + return; + shaper_3dlut_setting = pipe_ctx->plane_state->mcm_shaper_3dlut_setting; + lut1d_enable = pipe_ctx->plane_state->mcm_lut1d_enable; + mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); + pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; + + *lut1d_xable = lut1d_enable ? MCM_LUT_ENABLE : MCM_LUT_DISABLE; + + switch (shaper_3dlut_setting) { + case DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL: + *lut3d_xable = *shaper_xable = MCM_LUT_DISABLE; + break; + case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER: + *lut3d_xable = MCM_LUT_DISABLE; + *shaper_xable = MCM_LUT_ENABLE; + break; + case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT: + *lut3d_xable = *shaper_xable = MCM_LUT_ENABLE; + break; + } +} + +static void fl_get_lut_mode( + enum dc_cm2_gpu_mem_layout layout, + enum dc_cm2_gpu_mem_size size, + enum hubp_3dlut_fl_mode *mode, + enum hubp_3dlut_fl_addressing_mode *addr_mode, + enum hubp_3dlut_fl_width *width) +{ + *width = hubp_3dlut_fl_width_17; + + if (size == DC_CM2_GPU_MEM_SIZE_333333) + *width = hubp_3dlut_fl_width_33; + + switch (layout) { + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB: + *mode = hubp_3dlut_fl_mode_native_1; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR: + *mode = hubp_3dlut_fl_mode_native_2; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR: + *mode = hubp_3dlut_fl_mode_transform; + *addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; + break; + default: + *mode = hubp_3dlut_fl_mode_disable; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + } +} + bool dcn42_program_rmcm_luts( struct hubp *hubp, struct pipe_ctx *pipe_ctx, - const struct dc_plane_cm *cm, + enum dc_cm2_transfer_func_source lut3d_src, + struct dc_cm2_func_luts *mcm_luts, struct mpc *mpc, + bool lut_bank_a, int mpcc_id) { struct dpp *dpp_base = pipe_ctx->plane_res.dpp; union mcm_lut_params m_lut_params = {0}; + enum MCM_LUT_XABLE shaper_xable, lut3d_xable = MCM_LUT_DISABLE, lut1d_xable; + enum hubp_3dlut_fl_mode mode; + enum hubp_3dlut_fl_addressing_mode addr_mode; + enum hubp_3dlut_fl_format format = hubp_3dlut_fl_format_unorm_12msb_bitslice; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; + enum hubp_3dlut_fl_width width = hubp_3dlut_fl_width_17; + struct dc *dc = hubp->ctx->dc; + struct hubp_fl_3dlut_config fl_config; struct mpc_fl_3dlut_config mpc_fl_config; struct dc_stream_state *stream = pipe_ctx->stream; @@ -422,23 +585,25 @@ bool dcn42_program_rmcm_luts( // true->false when it can be allocated at DI time struct dc_rmcm_3dlut *rmcm_3dlut = dc_stream_get_3dlut_for_stream(dc, stream, false); - bool lut_bank_a = true; // TODO get from HW - //check to see current pipe is part of a stream with allocated rmcm 3dlut if (!rmcm_3dlut) return false; + rmcm_3dlut->protection_bits = mcm_luts->lut3d_data.rmcm_tmz; + + dcn42_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable); + /* Shaper */ - if (cm->flags.bits.shaper_enable) { + if (mcm_luts->shaper) { memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (cm->shaper_func.type == TF_TYPE_HWPWL) { - m_lut_params.pwl = &cm->shaper_func.pwl; - } else if (cm->shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { + if (mcm_luts->shaper->type == TF_TYPE_HWPWL) { + m_lut_params.pwl = &mcm_luts->shaper->pwl; + } else if (mcm_luts->shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { ASSERT(false); cm_helper_translate_curve_to_hw_format( dc->ctx, - &cm->shaper_func, + mcm_luts->shaper, &dpp_base->shaper_params, true); m_lut_params.pwl = &dpp_base->shaper_params; } @@ -454,21 +619,58 @@ bool dcn42_program_rmcm_luts( } /* 3DLUT */ - if (!cm->flags.bits.lut3d_dma_enable) { + switch (lut3d_src) { + case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: memset(&m_lut_params, 0, sizeof(m_lut_params)); // Don't know what to do in this case. - } else { - if (!dc_is_rmcm_3dlut_supported(hubp, mpc)) + //case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: + break; + case DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM: + fl_get_lut_mode(mcm_luts->lut3d_data.gpu_mem_params.layout, + mcm_luts->lut3d_data.gpu_mem_params.size, + &mode, + &addr_mode, + &width); + + if (!dc_is_rmcm_3dlut_supported(hubp, mpc) || + !mpc->funcs->rmcm.is_config_supported( + (width == hubp_3dlut_fl_width_17 || + width == hubp_3dlut_fl_width_transformed) ? 17 : 33)) return false; + // setting native or transformed mode, + dc_get_lut_mode(mcm_luts->lut3d_data.gpu_mem_params.layout, &mode, &addr_mode); + //seems to be only for the MCM - mpc_fl_config.enabled = cm->flags.bits.lut3d_enable; - mpc_fl_config.size = cm->lut3d_dma.size; + dc_get_lut_format(mcm_luts->lut3d_data.gpu_mem_params.format_params.format, &format); + + dc_get_lut_xbar( + mcm_luts->lut3d_data.gpu_mem_params.component_order, + &crossbar_bit_slice_cr_r, + &crossbar_bit_slice_y_g, + &crossbar_bit_slice_cb_b); + + fl_config.mode = mode; + fl_config.enabled = lut3d_xable != MCM_LUT_DISABLE; + fl_config.address = mcm_luts->lut3d_data.gpu_mem_params.addr; + fl_config.format = format; + fl_config.crossbar_bit_slice_y_g = crossbar_bit_slice_y_g; + fl_config.crossbar_bit_slice_cb_b = crossbar_bit_slice_cb_b; + fl_config.crossbar_bit_slice_cr_r = crossbar_bit_slice_cr_r; + fl_config.width = width; + fl_config.protection_bits = rmcm_3dlut->protection_bits; + fl_config.addr_mode = addr_mode; + fl_config.layout = mcm_luts->lut3d_data.gpu_mem_params.layout; + fl_config.bias = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.bias; + fl_config.scale = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.scale; + + mpc_fl_config.enabled = fl_config.enabled; + mpc_fl_config.width = width; mpc_fl_config.select_lut_bank_a = lut_bank_a; - mpc_fl_config.bit_depth = 0; + mpc_fl_config.bit_depth = mcm_luts->lut3d_data.gpu_mem_params.bit_depth; mpc_fl_config.hubp_index = hubp->inst; - mpc_fl_config.bias = cm->lut3d_dma.bias; - mpc_fl_config.scale = cm->lut3d_dma.scale; + mpc_fl_config.bias = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.bias; + mpc_fl_config.scale = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.scale; //1. power down the block mpc->funcs->rmcm.power_on_shaper_3dlut(mpc, mpcc_id, false); @@ -476,44 +678,268 @@ bool dcn42_program_rmcm_luts( //2. program RMCM - 3dlut reg programming mpc->funcs->rmcm.fl_3dlut_configure(mpc, &mpc_fl_config, mpcc_id); - /* HUBP */ - if (hubp->funcs->hubp_program_3dlut_fl_config) - hubp->funcs->hubp_program_3dlut_fl_config(hubp, &cm->lut3d_dma); - - if (hubp->funcs->hubp_program_3dlut_fl_addr) - hubp->funcs->hubp_program_3dlut_fl_addr(hubp, &cm->lut3d_dma.addr); + hubp->funcs->hubp_program_3dlut_fl_config(hubp, &fl_config); //3. power on the block mpc->funcs->rmcm.power_on_shaper_3dlut(mpc, mpcc_id, true); + + break; + default: + return false; } return true; } -bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *plane_state) +void dcn42_populate_mcm_luts(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_cm2_func_luts mcm_luts, + bool lut_bank_a) { - struct dc *dc = pipe_ctx->plane_res.hubp->ctx->dc; + struct dpp *dpp_base = pipe_ctx->plane_res.dpp; struct hubp *hubp = pipe_ctx->plane_res.hubp; - const struct dc_plane_cm *cm = &plane_state->cm; - struct mpc *mpc = dc->res_pool->mpc; int mpcc_id = hubp->inst; - bool result; + struct mpc *mpc = dc->res_pool->mpc; + union mcm_lut_params m_lut_params; + enum dc_cm2_transfer_func_source lut3d_src = mcm_luts.lut3d_data.lut3d_src; + enum hubp_3dlut_fl_format format = 0; + enum hubp_3dlut_fl_mode mode; + enum hubp_3dlut_fl_width width = 0; + enum hubp_3dlut_fl_addressing_mode addr_mode; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g = 0; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b = 0; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r = 0; + enum MCM_LUT_XABLE shaper_xable = MCM_LUT_DISABLE; + enum MCM_LUT_XABLE lut3d_xable = MCM_LUT_DISABLE; + enum MCM_LUT_XABLE lut1d_xable = MCM_LUT_DISABLE; + bool rval; - /* MCM */ - result = dcn401_set_mcm_luts(pipe_ctx, plane_state); + dcn42_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable); - /* RMCM */ - if (cm->flags.bits.rmcm_enable && cm->flags.bits.lut3d_dma_enable) { - /* TODO - move RMCM to its own block */ + //MCM - setting its location (Before/After) blender + //set to post blend (true) + dcn42_set_mcm_location_post_blend( + dc, + pipe_ctx, + mcm_luts.lut3d_data.mpc_mcm_post_blend); + + //RMCM - 3dLUT+Shaper + if (mcm_luts.lut3d_data.rmcm_3dlut_enable && + is_rmcm_3dlut_fl_supported(dc, mcm_luts.lut3d_data.gpu_mem_params.size)) { dcn42_program_rmcm_luts( hubp, pipe_ctx, - cm, + lut3d_src, + &mcm_luts, mpc, + lut_bank_a, mpcc_id); } + /* 1D LUT */ + if (mcm_luts.lut1d_func) { + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (mcm_luts.lut1d_func->type == TF_TYPE_HWPWL) + m_lut_params.pwl = &mcm_luts.lut1d_func->pwl; + else if (mcm_luts.lut1d_func->type == TF_TYPE_DISTRIBUTED_POINTS) { + rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, + mcm_luts.lut1d_func, + &dpp_base->regamma_params, false); + m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; + } + if (m_lut_params.pwl) { + if (mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, m_lut_params, lut_bank_a, mpcc_id); + } + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut1d_xable && m_lut_params.pwl, lut_bank_a, mpcc_id); + } + + /* Shaper */ + if (mcm_luts.shaper && mcm_luts.lut3d_data.mpc_3dlut_enable) { + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (mcm_luts.shaper->type == TF_TYPE_HWPWL) + m_lut_params.pwl = &mcm_luts.shaper->pwl; + else if (mcm_luts.shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { + ASSERT(false); + rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, + mcm_luts.shaper, + &dpp_base->regamma_params, true); + m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; + } + if (m_lut_params.pwl) { + if (mpc->funcs->mcm.populate_lut) + mpc->funcs->mcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id); + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_ENABLE, lut_bank_a, mpcc_id); + } + } + + /* 3DLUT */ + switch (lut3d_src) { + case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, false); + + if (mcm_luts.lut3d_data.lut3d_func && mcm_luts.lut3d_data.lut3d_func->state.bits.initialized) { + m_lut_params.lut3d = &mcm_luts.lut3d_data.lut3d_func->lut_3d; + if (mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, m_lut_params, lut_bank_a, mpcc_id); + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, + mpcc_id); + } + break; + case DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM: + switch (mcm_luts.lut3d_data.gpu_mem_params.size) { + case DC_CM2_GPU_MEM_SIZE_333333: + width = hubp_3dlut_fl_width_33; + break; + case DC_CM2_GPU_MEM_SIZE_171717: + width = hubp_3dlut_fl_width_17; + break; + case DC_CM2_GPU_MEM_SIZE_TRANSFORMED: + width = hubp_3dlut_fl_width_transformed; + break; + default: + //TODO: Handle default case + break; + } + + //check for support + if (mpc->funcs->mcm.is_config_supported && + !mpc->funcs->mcm.is_config_supported(width)) + break; + + if (mpc->funcs->program_lut_read_write_control) + mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, mpcc_id); + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, mpcc_id); + + if (hubp->funcs->hubp_program_3dlut_fl_addr) + hubp->funcs->hubp_program_3dlut_fl_addr(hubp, mcm_luts.lut3d_data.gpu_mem_params.addr); + + if (mpc->funcs->mcm.program_bit_depth) + mpc->funcs->mcm.program_bit_depth(mpc, mcm_luts.lut3d_data.gpu_mem_params.bit_depth, mpcc_id); + + dc_get_lut_mode(mcm_luts.lut3d_data.gpu_mem_params.layout, &mode, &addr_mode); + if (hubp->funcs->hubp_program_3dlut_fl_mode) + hubp->funcs->hubp_program_3dlut_fl_mode(hubp, mode); + + if (hubp->funcs->hubp_program_3dlut_fl_addressing_mode) + hubp->funcs->hubp_program_3dlut_fl_addressing_mode(hubp, addr_mode); + + switch (mcm_luts.lut3d_data.gpu_mem_params.format_params.format) { + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB: + format = hubp_3dlut_fl_format_unorm_12msb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB: + format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10: + format = hubp_3dlut_fl_format_float_fp1_5_10; + break; + } + if (hubp->funcs->hubp_program_3dlut_fl_format) + hubp->funcs->hubp_program_3dlut_fl_format(hubp, format); + if (hubp->funcs->hubp_update_3dlut_fl_bias_scale && + mpc->funcs->mcm.program_bias_scale) { + mpc->funcs->mcm.program_bias_scale(mpc, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale, + mpcc_id); + hubp->funcs->hubp_update_3dlut_fl_bias_scale(hubp, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale); + } + + //navi 4x has a bug and r and blue are swapped and need to be worked around here in + //TODO: need to make a method for get_xbar per asic OR do the workaround in program_crossbar for 4x + dc_get_lut_xbar( + mcm_luts.lut3d_data.gpu_mem_params.component_order, + &crossbar_bit_slice_cr_r, + &crossbar_bit_slice_y_g, + &crossbar_bit_slice_cb_b); + + if (hubp->funcs->hubp_program_3dlut_fl_crossbar) + hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, + crossbar_bit_slice_cr_r, + crossbar_bit_slice_y_g, + crossbar_bit_slice_cb_b); + + if (mpc->funcs->mcm.program_lut_read_write_control) + mpc->funcs->mcm.program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, true, mpcc_id); + + if (mpc->funcs->mcm.program_3dlut_size) + mpc->funcs->mcm.program_3dlut_size(mpc, width, mpcc_id); + + if (mpc->funcs->update_3dlut_fast_load_select) + mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst); + + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, true); + else { + if (mpc->funcs->program_lut_mode) { + mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); + mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); + } + } + break; + } +} + +bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) +{ + struct dpp *dpp_base = pipe_ctx->plane_res.dpp; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc; + struct mpc *mpc = dc->res_pool->mpc; + bool result; + const struct pwl_params *lut_params = NULL; + bool rval; + + if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { + dcn42_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a); + return true; + } + + mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); + pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; + // 1D LUT + if (plane_state->blend_tf.type == TF_TYPE_HWPWL) + lut_params = &plane_state->blend_tf.pwl; + else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) { + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->blend_tf, + &dpp_base->regamma_params, false); + lut_params = rval ? &dpp_base->regamma_params : NULL; + } + result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); + lut_params = NULL; + + // Shaper + if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL) + lut_params = &plane_state->in_shaper_func.pwl; + else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { + // TODO: dpp_base replace + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->in_shaper_func, + &dpp_base->shaper_params, true); + lut_params = rval ? &dpp_base->shaper_params : NULL; + } + result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); + + // 3D + if (mpc->funcs->program_3dlut) { + if (plane_state->lut3d_func.state.bits.initialized == 1) + result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id); + else + result &= mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); + } + return result; } void dcn42_hardware_release(struct dc *dc) @@ -540,7 +966,8 @@ void dcn42_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, { bool hpo_frl_stream_enc_acquired = false; bool hpo_dp_stream_enc_acquired = false; - int i = 0, j = 0; + unsigned int i = 0; + int j = 0; memset(update_state, 0, sizeof(struct pg_block_update)); @@ -663,7 +1090,8 @@ void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, struct pg_block_update *update_state) { bool hpo_dp_stream_enc_acquired = false; - int i = 0, j = 0; + unsigned int i = 0; + int j = 0; memset(update_state, 0, sizeof(struct pg_block_update)); @@ -795,6 +1223,7 @@ void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, struct pg_block_update *update_state) { int i = 0; + int pipe_count = dc->res_pool->pipe_count; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; bool block_disabled = true; @@ -808,7 +1237,7 @@ void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, pg_cntl->funcs->hpo_pg_control(pg_cntl, false); } - for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { + for (i = pipe_count - 1; i >= 0; i--) { if (update_state->pg_pipe_res_update[PG_HUBP][i] && update_state->pg_pipe_res_update[PG_DPP][i]) { if (pg_cntl->funcs->hubp_dpp_pg_control) @@ -828,7 +1257,7 @@ void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, } } - for (i = 0; i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < pipe_count; i++) { if (!update_state->pg_pipe_res_update[PG_MPCC][i] || !update_state->pg_pipe_res_update[PG_OPP][i] || !update_state->pg_pipe_res_update[PG_OPTC][i]) { @@ -883,7 +1312,7 @@ void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, void dcn42_hw_block_power_up(struct dc *dc, struct pg_block_update *update_state) { - int i = 0; + unsigned int i = 0; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; bool block_enabled = false; @@ -917,7 +1346,7 @@ void dcn42_hw_block_power_up(struct dc *dc, pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true); } - for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) { if (update_state->pg_pipe_res_update[PG_DSC][i]) { if (pg_cntl->funcs->dsc_pg_control) pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true); @@ -944,7 +1373,7 @@ void dcn42_hw_block_power_up(struct dc *dc, void dcn42_root_clock_control(struct dc *dc, struct pg_block_update *update_state, bool power_on) { - int i = 0; + unsigned int i = 0; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; if (!pg_cntl) @@ -968,7 +1397,7 @@ void dcn42_root_clock_control(struct dc *dc, dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on); } - for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) { if (update_state->pg_pipe_res_update[PG_DSC][i]) { if (power_on) { if (dc->res_pool->dccg->funcs->enable_dsc) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h index c4cfeed45b19..0539ee0ffaee 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h @@ -18,11 +18,18 @@ void dcn42_program_cm_hist( bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); +void dcn42_populate_mcm_luts(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_cm2_func_luts mcm_luts, + bool lut_bank_a); + bool dcn42_program_rmcm_luts( struct hubp *hubp, struct pipe_ctx *pipe_ctx, - const struct dc_plane_cm *cm, + enum dc_cm2_transfer_func_source lut3d_src, + struct dc_cm2_func_luts *mcm_luts, struct mpc *mpc, + bool lut_bank_a, int mpcc_id); void dcn42_hardware_release(struct dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index d1dba7ffcd9b..4b9fcb87e60d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -33,6 +33,7 @@ #include "inc/core_status.h" #include "inc/hw/hw_shared.h" #include "dsc/dsc.h" +#include "link_service_types.h" struct pipe_ctx; struct dc_state; @@ -52,7 +53,13 @@ struct drr_params; struct dc_underflow_debug_data; struct dsc_optc_config; struct vm_system_aperture_param; -struct memory_qos; +struct dc_measured_memory_qos; +struct stream_encoder; +struct hpo_dp_stream_encoder; +struct hpo_frl_stream_encoder; +struct link_training_settings; +struct dc_link; +struct dc_crtc_timing; struct subvp_pipe_control_lock_fast_params { struct dc *dc; bool lock; @@ -91,6 +98,21 @@ struct program_gamut_remap_params { struct pipe_ctx *pipe_ctx; }; +struct hubp_enable_3dlut_fl_params { + struct hubp *hubp; +}; + +struct tg_setup_vertical_interrupt0_params { + struct timing_generator *tg; + uint32_t start_line; + uint32_t end_line; +}; + +struct update_info_frame_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + struct program_manual_trigger_params { struct pipe_ctx *pipe_ctx; }; @@ -707,11 +729,37 @@ struct abort_cursor_offload_update_params { struct pipe_ctx *pipe_ctx; }; +struct cursor_lock_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; + bool lock; +}; + +struct setup_periodic_interrupt_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + +struct send_cursor_info_to_dmu_params { + struct pipe_ctx *pipe_ctx; + int pipe_idx; +}; + struct set_cursor_attribute_params { struct dc *dc; struct pipe_ctx *pipe_ctx; }; +struct hubp_set_cursor_attributes_params { + struct hubp *hubp; + const struct dc_cursor_attributes *attributes; +}; + +struct dpp_set_cursor_attributes_params { + struct dpp *dpp; + struct dc_cursor_attributes *attributes; +}; + struct set_cursor_position_params { struct dc *dc; struct pipe_ctx *pipe_ctx; @@ -739,6 +787,113 @@ struct phantom_hubp_post_enable_params { struct hubp *hubp; }; +struct begin_cursor_offload_update_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + +struct update_cursor_offload_pipe_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + +struct commit_cursor_offload_update_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + +struct stream_enc_update_hdmi_info_packets_params { + struct pipe_ctx *pipe_ctx; +}; + +struct hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params { + struct pipe_ctx *pipe_ctx; +}; + +struct hpo_dp_stream_enc_update_dp_info_packets_params { + struct pipe_ctx *pipe_ctx; +}; + +struct stream_enc_update_dp_info_packets_sdp_line_num_params { + struct pipe_ctx *pipe_ctx; +}; + +struct stream_enc_update_dp_info_packets_params { + struct pipe_ctx *pipe_ctx; +}; + +struct dsc_set_config_simple_params { + struct display_stream_compressor *dsc; + struct dsc_config dsc_cfg; + struct dsc_optc_config dsc_optc_cfg; +}; + +struct stream_enc_dp_set_dsc_config_params { + struct stream_encoder *stream_enc; + const struct dsc_optc_config *dsc_optc_cfg; +}; + +struct hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params { + struct hpo_dp_stream_encoder *hpo_dp_stream_enc; + bool immediate_update; + uint8_t *dsc_packed_pps; + bool pps_sdp_stream; +}; + +struct stream_enc_dp_set_dsc_pps_info_packet_params { + struct stream_encoder *stream_enc; + bool immediate_update; + uint8_t *dsc_packed_pps; + bool pps_sdp_stream; +}; + +struct dp_trace_source_sequence_params { + struct dc_link *link; + enum dpcd_source_sequence source; +}; + +struct set_dmdata_attributes_params { + struct hubp *hubp; + struct dc_dmdata_attributes attr; +}; + +struct link_increase_mst_payload_params { + struct pipe_ctx *pipe_ctx; + uint32_t mst_stream_bw; +}; + +struct link_reduce_mst_payload_params { + struct pipe_ctx *pipe_ctx; + uint32_t mst_stream_bw; +}; + +struct dp_set_test_pattern_params { + struct dc_link *link; + enum dp_test_pattern test_pattern; + enum dp_test_pattern_color_space test_pattern_color_space; + const struct link_training_settings *p_link_settings; + const unsigned char *p_custom_pattern; + unsigned int cust_pattern_size; +}; + +struct link_set_dpms_off_params { + struct pipe_ctx *pipe_ctx; +}; + +struct disable_audio_stream_params { + struct pipe_ctx *pipe_ctx; +}; + +struct prepare_bandwidth_params { + struct dc *dc; + struct dc_state *context; +}; + +struct link_set_dpms_on_params { + struct dc_state *state; + struct pipe_ctx *pipe_ctx; +}; + union block_sequence_params { struct update_plane_addr_params update_plane_addr_params; struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; @@ -747,6 +902,9 @@ union block_sequence_params { struct program_triplebuffer_params program_triplebuffer_params; struct set_input_transfer_func_params set_input_transfer_func_params; struct program_gamut_remap_params program_gamut_remap_params; + struct hubp_enable_3dlut_fl_params hubp_enable_3dlut_fl_params; + struct tg_setup_vertical_interrupt0_params tg_setup_vertical_interrupt0_params; + struct update_info_frame_params update_info_frame_params; struct program_manual_trigger_params program_manual_trigger_params; struct send_dmcub_cmd_params send_dmcub_cmd_params; struct setup_dpp_params setup_dpp_params; @@ -855,12 +1013,38 @@ union block_sequence_params { struct dpp_set_scaler_params dpp_set_scaler_params; struct hubp_mem_program_viewport_params hubp_mem_program_viewport_params; struct abort_cursor_offload_update_params abort_cursor_offload_update_params; + struct cursor_lock_params cursor_lock_params; + struct setup_periodic_interrupt_params setup_periodic_interrupt_params; + struct send_cursor_info_to_dmu_params send_cursor_info_to_dmu_params; struct set_cursor_attribute_params set_cursor_attribute_params; + struct hubp_set_cursor_attributes_params hubp_set_cursor_attributes_params; + struct dpp_set_cursor_attributes_params dpp_set_cursor_attributes_params; struct set_cursor_position_params set_cursor_position_params; struct set_cursor_sdr_white_level_params set_cursor_sdr_white_level_params; struct program_output_csc_params program_output_csc_params; struct hubp_set_blank_params hubp_set_blank_params; struct phantom_hubp_post_enable_params phantom_hubp_post_enable_params; + struct begin_cursor_offload_update_params begin_cursor_offload_update_params; + struct update_cursor_offload_pipe_params update_cursor_offload_pipe_params; + struct commit_cursor_offload_update_params commit_cursor_offload_update_params; + struct stream_enc_update_hdmi_info_packets_params stream_enc_update_hdmi_info_packets_params; + struct hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params; + struct hpo_dp_stream_enc_update_dp_info_packets_params hpo_dp_stream_enc_update_dp_info_packets_params; + struct stream_enc_update_dp_info_packets_sdp_line_num_params stream_enc_update_dp_info_packets_sdp_line_num_params; + struct stream_enc_update_dp_info_packets_params stream_enc_update_dp_info_packets_params; + struct dsc_set_config_simple_params dsc_set_config_simple_params; + struct stream_enc_dp_set_dsc_config_params stream_enc_dp_set_dsc_config_params; + struct hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params; + struct stream_enc_dp_set_dsc_pps_info_packet_params stream_enc_dp_set_dsc_pps_info_packet_params; + struct dp_trace_source_sequence_params dp_trace_source_sequence_params; + struct set_dmdata_attributes_params set_dmdata_attributes_params; + struct link_increase_mst_payload_params link_increase_mst_payload_params; + struct link_reduce_mst_payload_params link_reduce_mst_payload_params; + struct dp_set_test_pattern_params dp_set_test_pattern_params; + struct link_set_dpms_off_params link_set_dpms_off_params; + struct disable_audio_stream_params disable_audio_stream_params; + struct prepare_bandwidth_params prepare_bandwidth_params; + struct link_set_dpms_on_params link_set_dpms_on_params; }; enum block_sequence_func { @@ -871,6 +1055,11 @@ enum block_sequence_func { HUBP_UPDATE_PLANE_ADDR, DPP_SET_INPUT_TRANSFER_FUNC, DPP_PROGRAM_GAMUT_REMAP, + HUBP_ENABLE_3DLUT_FL, + OTG_SETUP_VERTICAL_INTERRUPT, + HWSS_SETUP_PERIODIC_INTERRUPT, + HWSS_UPDATE_INFO_FRAME, + HUBP_SET_DMDATA_ATTRIBUTES, OPTC_PROGRAM_MANUAL_TRIGGER, DMUB_SEND_DMCUB_CMD, DPP_SETUP_DPP, @@ -975,13 +1164,37 @@ enum block_sequence_func { DPP_SET_SCALER, HUBP_MEM_PROGRAM_VIEWPORT, ABORT_CURSOR_OFFLOAD_UPDATE, + HWSS_CURSOR_LOCK, + HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE, + HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE, + HWSS_UPDATE_CURSOR_OFFLOAD_PIPE, + DC_SEND_CURSOR_INFO_TO_DMU, SET_CURSOR_ATTRIBUTE, + HUBP_SET_CURSOR_ATTRIBUTES, + DPP_SET_CURSOR_ATTRIBUTES, SET_CURSOR_POSITION, SET_CURSOR_SDR_WHITE_LEVEL, PROGRAM_OUTPUT_CSC, HUBP_SET_LEGACY_TILING_COMPAT_LEVEL, HUBP_SET_BLANK, PHANTOM_HUBP_POST_ENABLE, + STREAM_ENC_UPDATE_HDMI_INFO_PACKETS, + HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM, + HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS, + STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM, + STREAM_ENC_UPDATE_DP_INFO_PACKETS, + DSC_SET_CONFIG_SIMPLE, + STREAM_ENC_DP_SET_DSC_CONFIG, + HPO_DP_STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET, + STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET, + LINK_INCREASE_MST_PAYLOAD, + LINK_REDUCE_MST_PAYLOAD, + DP_TRACE_SOURCE_SEQUENCE, + DP_SET_TEST_PATTERN, + LINK_SET_DPMS_OFF, + DISABLE_AUDIO_STREAM, + PREPARE_BANDWIDTH, + LINK_SET_DPMS_ON, /* This must be the last value in this enum, add new ones above */ HWSS_BLOCK_SEQUENCE_FUNC_COUNT }; @@ -1303,12 +1516,12 @@ struct hw_sequencer_funcs { /** * measure_memory_qos - Measure memory QoS metrics * @dc: DC structure - * @qos: Pointer to memory_qos struct to populate with measured values + * @qos: Pointer to dc_measured_memory_qos struct to populate with measured values * - * Populates the provided memory_qos struct with peak bandwidth, average bandwidth, + * Populates the provided dc_measured_memory_qos struct with peak bandwidth, average bandwidth, * max latency, min latency, and average latency from hardware performance counters. */ - void (*measure_memory_qos)(struct dc *dc, struct memory_qos *qos); + void (*measure_memory_qos)(struct dc *dc, struct dc_measured_memory_qos *qos); }; @@ -1455,6 +1668,40 @@ void hwss_dsc_calculate_and_set_config(union block_sequence_params *params); void hwss_dsc_enable_with_opp(union block_sequence_params *params); +void hwss_dsc_set_config_simple(union block_sequence_params *params); + +void hwss_stream_enc_update_hdmi_info_packets(union block_sequence_params *params); + +void hwss_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(union block_sequence_params *params); + +void hwss_hpo_dp_stream_enc_update_dp_info_packets(union block_sequence_params *params); + +void hwss_stream_enc_update_dp_info_packets_sdp_line_num(union block_sequence_params *params); + +void hwss_stream_enc_update_dp_info_packets(union block_sequence_params *params); + +void hwss_stream_enc_dp_set_dsc_config(union block_sequence_params *params); + +void hwss_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(union block_sequence_params *params); + +void hwss_stream_enc_dp_set_dsc_pps_info_packet(union block_sequence_params *params); + +void hwss_set_dmdata_attributes(union block_sequence_params *params); + +void hwss_dp_trace_source_sequence(union block_sequence_params *params); + +void hwss_link_increase_mst_payload(union block_sequence_params *params); + +void hwss_link_reduce_mst_payload(union block_sequence_params *params); + +void hwss_dp_set_test_pattern(union block_sequence_params *params); + +void hwss_link_set_dpms_off(union block_sequence_params *params); + +void hwss_prepare_bandwidth(struct dc *dc, union block_sequence_params *params); + +void hwss_link_set_dpms_on(union block_sequence_params *params); + void hwss_program_tg(union block_sequence_params *params); void hwss_tg_program_global_sync(union block_sequence_params *params); @@ -1463,6 +1710,12 @@ void hwss_tg_wait_for_state(union block_sequence_params *params); void hwss_tg_set_vtg_params(union block_sequence_params *params); +void hwss_hubp_enable_3dlut_fl(union block_sequence_params *params); + +void hwss_update_info_frame(struct dc *dc, union block_sequence_params *params); + +void hwss_tg_setup_vertical_interrupt0(union block_sequence_params *params); + void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params); void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params); @@ -1603,12 +1856,20 @@ void hwss_hubp_mem_program_viewport(union block_sequence_params *params); void hwss_abort_cursor_offload_update(union block_sequence_params *params); +void hwss_send_cursor_info_to_dmu(union block_sequence_params *params); + void hwss_set_cursor_attribute(union block_sequence_params *params); +void hwss_hubp_set_cursor_attributes(union block_sequence_params *params); + +void hwss_dpp_set_cursor_attributes(union block_sequence_params *params); + void hwss_set_cursor_position(union block_sequence_params *params); void hwss_set_cursor_sdr_white_level(union block_sequence_params *params); +void hwss_program_gamut_remap(union block_sequence_params *params); + void hwss_program_output_csc(union block_sequence_params *params); void hwss_hubp_set_legacy_tiling_compat_level(union block_sequence_params *params); @@ -1617,6 +1878,18 @@ void hwss_hubp_set_blank(union block_sequence_params *params); void hwss_phantom_hubp_post_enable(union block_sequence_params *params); +void hwss_cursor_lock(union block_sequence_params *params); + +void hwss_begin_cursor_offload_update(union block_sequence_params *params); + +void hwss_commit_cursor_offload_update(union block_sequence_params *params); + +void hwss_update_cursor_offload_pipe(union block_sequence_params *params); + +void hwss_setup_periodic_interrupt(struct dc *dc, union block_sequence_params *params); + +void hwss_disable_audio_stream(struct dc *dc, union block_sequence_params *params); + void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state, struct dc *dc, struct pipe_ctx *pipe_ctx, bool lock); @@ -1695,6 +1968,9 @@ void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state, void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state, struct timing_generator *tg, struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); +void hwss_add_vertical_interrupt_setup(struct block_sequence_state *seq_state, + struct timing_generator *tg, uint32_t start_line, uint32_t end_line); + void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state, struct timing_generator *tg, int start_line); @@ -2012,6 +2288,14 @@ void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state, struct dc *dc, struct pipe_ctx *pipe_ctx); +void hwss_add_hubp_set_cursor_attributes(struct block_sequence_state *seq_state, + struct hubp *hubp, + const struct dc_cursor_attributes *attributes); + +void hwss_add_dpp_set_cursor_attributes(struct block_sequence_state *seq_state, + struct dpp *dpp, + struct dc_cursor_attributes *attributes); + void hwss_add_set_cursor_position(struct block_sequence_state *seq_state, struct dc *dc, struct pipe_ctx *pipe_ctx); @@ -2056,4 +2340,105 @@ void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq enum dc_pixel_encoding pixel_encoding, bool is_otg_master); +void hwss_add_hubp_enable_3dlut_fl(struct block_sequence_state *seq_state, + struct hubp *hubp); + +void hwss_add_begin_cursor_offload_update(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx); + +void hwss_add_cursor_lock(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx, + bool lock); + +void hwss_add_send_update_cursor_info_to_dmu(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, + int index); + +void hwss_add_update_cursor_offload_pipe(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx); + +void hwss_add_commit_cursor_offload_update(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx); + +void hwss_add_stream_enc_update_hdmi_info_packets(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_hpo_dp_stream_enc_update_dp_info_packets(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_stream_enc_update_dp_info_packets_sdp_line_num(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_stream_enc_update_dp_info_packets(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_dsc_set_config(struct block_sequence_state *seq_state, + struct display_stream_compressor *dsc, + const struct dsc_config *dsc_cfg, + const struct dsc_optc_config *dsc_optc_cfg); + +void hwss_add_stream_enc_dp_set_dsc_config(struct block_sequence_state *seq_state, + struct stream_encoder *stream_enc, + const struct dsc_optc_config *dsc_optc_cfg); + +void hwss_add_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(struct block_sequence_state *seq_state, + struct hpo_dp_stream_encoder *hpo_dp_stream_enc, + bool immediate_update, + uint8_t *dsc_packed_pps, + bool pps_sdp_stream); + +void hwss_add_stream_enc_dp_set_dsc_pps_info_packet(struct block_sequence_state *seq_state, + struct stream_encoder *stream_enc, + bool immediate_update, + uint8_t *dsc_packed_pps, + bool pps_sdp_stream); + +void hwss_add_setup_periodic_interrupt(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx); + +void hwss_add_dp_trace_source_sequence(struct block_sequence_state *seq_state, + struct dc_link *link, + enum dpcd_source_sequence source); + +void hwss_add_set_dmdata_attributes(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_link_increase_mst_payload(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, + uint32_t mst_stream_bw); + +void hwss_add_link_reduce_mst_payload(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, + uint32_t mst_stream_bw); + +void hwss_add_dp_set_test_pattern(struct block_sequence_state *seq_state, + struct dc_link *link, + enum dp_test_pattern test_pattern, + enum dp_test_pattern_color_space test_pattern_color_space, + const struct link_training_settings *p_link_settings, + const unsigned char *p_custom_pattern, + unsigned int cust_pattern_size); + +void hwss_add_link_set_dpms_off(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_disable_audio_stream(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_prepare_bandwidth(struct block_sequence_state *seq_state, + struct dc *dc, + struct dc_state *context); + +void hwss_add_link_set_dpms_on(struct block_sequence_state *seq_state, + struct dc_state *state, + struct pipe_ctx *pipe_ctx); + #endif /* __DC_HW_SEQUENCER_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h index d1656c9d50df..d567d4bd585d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h +++ b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h @@ -79,7 +79,7 @@ static inline struct bw_fixed bw_int_to_fixed(int64_t value) static inline int32_t bw_fixed_to_int(struct bw_fixed value) { - return BW_FIXED_GET_INTEGER_PART(value.value); + return (int32_t)BW_FIXED_GET_INTEGER_PART(value.value); } struct bw_fixed bw_frc_to_fixed(int64_t num, int64_t denum); diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index e960ca9062ad..a99e1937f8ce 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -707,7 +707,7 @@ struct dc_bounding_box_max_clk { int max_phyclk_mhz; }; -struct memory_qos { +struct dc_measured_memory_qos { uint32_t peak_bw_mbps; uint32_t avg_bw_mbps; uint32_t max_latency_ns; @@ -715,4 +715,12 @@ struct memory_qos { uint32_t avg_latency_ns; }; +struct dc_requested_memory_qos { + uint32_t bandwidth_lb_in_mbps; + uint32_t calculated_avg_bw_in_mbps; + uint32_t max_latency_ub_in_ns; + uint32_t avg_latency_ub_in_ns; + uint32_t max_bw_budget_in_mbps; +}; + #endif /* _CORE_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 21224fd6b36d..dcce81e3d97c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -28,6 +28,7 @@ #define __DAL_CLK_MGR_H__ #include "dc.h" +#include "core_types.h" #include "dm_pp_smu.h" /* Constants */ @@ -362,6 +363,27 @@ struct clk_mgr_funcs { uint32_t (*set_smartmux_switch)(struct clk_mgr *clk_mgr, uint32_t pins_to_set); unsigned int (*get_max_clock_khz)(struct clk_mgr *clk_mgr_base, enum clk_type clk_type); + /** + * override_memory_bandwidth_request - Override the DCN nominal memory + * bandwidth request sent to PMFW, independent of the current display + * mode. For debug use only. + * @clk_mgr: clock manager instance + * @bw_kbps: requested bandwidth in kbps; 0 clears the override + * + * Return: capped bandwidth value actually applied (kbps) + */ + unsigned int (*override_memory_bandwidth_request)( + struct clk_mgr *clk_mgr, + unsigned int bw_kbps); + /** + * get_requested_memory_qos - Retrieve current QoS request from the clock manager's + * current clock state, reflecting any active bandwidth overrides. + * @clk_mgr: clock manager instance + * @qos: pointer to dc_requested_memory_qos structure to populate + */ + void (*get_requested_memory_qos)( + struct clk_mgr *clk_mgr, + struct dc_requested_memory_qos *qos); }; struct clk_mgr { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index 2a5a81d15950..0530b214c4b6 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -89,7 +89,7 @@ enum hubp_3dlut_fl_addressing_mode { enum hubp_3dlut_fl_width { hubp_3dlut_fl_width_17 = 17, hubp_3dlut_fl_width_33 = 33, - hubp_3dlut_fl_width_17_transformed = 4916, //mpc default + hubp_3dlut_fl_width_transformed = 4916, //mpc default }; enum hubp_3dlut_fl_crossbar_bit_slice { @@ -99,6 +99,22 @@ enum hubp_3dlut_fl_crossbar_bit_slice { hubp_3dlut_fl_crossbar_bit_slice_48_63 = 3 }; +struct hubp_fl_3dlut_config { + bool enabled; + enum hubp_3dlut_fl_width width; + enum hubp_3dlut_fl_mode mode; + enum hubp_3dlut_fl_format format; + uint16_t bias; + uint16_t scale; + struct dc_plane_address address; + enum hubp_3dlut_fl_addressing_mode addr_mode; + enum dc_cm2_gpu_mem_layout layout; + uint8_t protection_bits; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r; +}; + struct hubp { const struct hubp_funcs *funcs; struct dc_context *ctx; @@ -133,7 +149,7 @@ struct surface_flip_registers { uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; - bool tmz_surface; + uint8_t tmz_surface; bool immediate; uint8_t vmid; bool grph_stereo; @@ -273,15 +289,24 @@ struct hubp_funcs { void (*hubp_wait_pipe_read_start)(struct hubp *hubp); void (*hubp_program_mcache_id_and_split_coordinate)(struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs); + void (*hubp_update_3dlut_fl_bias_scale)(struct hubp *hubp, uint16_t bias, uint16_t scale); + void (*hubp_program_3dlut_fl_mode)(struct hubp *hubp, + enum hubp_3dlut_fl_mode mode); + void (*hubp_program_3dlut_fl_format)(struct hubp *hubp, + enum hubp_3dlut_fl_format format); void (*hubp_program_3dlut_fl_addr)(struct hubp *hubp, - const struct dc_plane_address *address); - void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, - const struct dc_3dlut_dma *config); + const struct dc_plane_address address); void (*hubp_program_3dlut_fl_dlg_param)(struct hubp *hubp, int refcyc_per_3dlut_group); void (*hubp_enable_3dlut_fl)(struct hubp *hubp, bool enable); + void (*hubp_program_3dlut_fl_addressing_mode)(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode); + void (*hubp_program_3dlut_fl_width)(struct hubp *hubp, enum hubp_3dlut_fl_width width); + void (*hubp_program_3dlut_fl_tmz_protected)(struct hubp *hubp, uint8_t protection_bits); void (*hubp_program_3dlut_fl_crossbar)(struct hubp *hubp, - enum dc_cm_lut_pixel_format format); + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r); int (*hubp_get_3dlut_fl_done)(struct hubp *hubp); + void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg); void (*hubp_clear_tiling)(struct hubp *hubp); uint32_t (*hubp_get_current_read_line)(struct hubp *hubp); uint32_t (*hubp_get_det_config_error)(struct hubp *hubp); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index f5617674bea8..54eb2eba68bf 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -54,7 +54,6 @@ #include "dc_hw_types.h" #include "hw_shared.h" #include "transform.h" -#include "dc_types.h" #define MAX_MPCC 6 #define MAX_OPP 6 @@ -102,6 +101,13 @@ enum mpcc_movable_cm_location { MPCC_MOVABLE_CM_LOCATION_AFTER, }; +enum MCM_LUT_XABLE { + MCM_LUT_DISABLE, + MCM_LUT_DISABLED = MCM_LUT_DISABLE, + MCM_LUT_ENABLE, + MCM_LUT_ENABLED = MCM_LUT_ENABLE, +}; + enum MCM_LUT_ID { MCM_LUT_3DLUT, MCM_LUT_1DLUT, @@ -110,7 +116,7 @@ enum MCM_LUT_ID { struct mpc_fl_3dlut_config { bool enabled; - enum dc_cm_lut_size size; + uint16_t width; bool select_lut_bank_a; uint16_t bit_depth; int hubp_index; @@ -1069,11 +1075,8 @@ struct mpc_funcs { * * void */ - void (*populate_lut)(struct mpc *mpc, - const enum MCM_LUT_ID id, - const union mcm_lut_params *params, - const bool lut_bank_a, - const int mpcc_id); + void (*populate_lut)(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, + bool lut_bank_a, int mpcc_id); /** * @program_lut_read_write_control: @@ -1084,18 +1087,13 @@ struct mpc_funcs { * - [in/out] mpc - MPC context. * - [in] id * - [in] lut_bank_a - * - [in] bit_depth * - [in] mpcc_id * * Return: * * void */ - void (*program_lut_read_write_control)(struct mpc *mpc, - const enum MCM_LUT_ID id, - const bool lut_bank_a, - const unsigned int bit_depth, - const int mpcc_id); + void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id); /** * @program_lut_mode: @@ -1105,44 +1103,33 @@ struct mpc_funcs { * Parameters: * - [in/out] mpc - MPC context. * - [in] id - * - [in] enable + * - [in] xable * - [in] lut_bank_a - * - [in] size * - [in] mpcc_id * * Return: * * void */ - void (*program_lut_mode)(struct mpc *mpc, - const enum MCM_LUT_ID id, - const bool enable, - const bool lut_bank_a, - const enum dc_cm_lut_size size, - const int mpcc_id); - + void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const enum MCM_LUT_XABLE xable, + bool lut_bank_a, int mpcc_id); /** - * @get_lut_mode: - * - * Obtains enablement and ram bank status. - * - * Parameters: - * - [in/out] mpc - MPC context. - * - [in] id - * - [in] mpcc_id - * - [out] enable - * - [out] lut_bank_a - * - * Return: - * - * void - */ - void (*get_lut_mode)(struct mpc *mpc, - const enum MCM_LUT_ID id, - const int mpcc_id, - bool *enable, - bool *lut_bank_a); + * @mcm: + * + * MPC MCM new HW sequential programming functions + */ + struct { + void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id); + void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id); + void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id); + bool (*is_config_supported)(uint32_t width); + void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, + bool lut_bank_a, bool enabled, int mpcc_id); + + void (*populate_lut)(struct mpc *mpc, const union mcm_lut_params params, + bool lut_bank_a, int mpcc_id); + } mcm; /** * @rmcm: @@ -1155,11 +1142,9 @@ struct mpc_funcs { void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, bool enabled, int mpcc_id); - void (*program_lut_mode)(struct mpc *mpc, - bool enable, - bool lut_bank_a, - int mpcc_id); - void (*program_3dlut_size)(struct mpc *mpc, const enum dc_cm_lut_size size, int mpcc_id); + void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_XABLE xable, + bool lut_bank_a, int mpcc_id); + void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id); void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id); void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id); bool (*is_config_supported)(uint32_t width); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index 27f950ae45ee..a9bf960dacbc 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -93,6 +93,7 @@ struct encoder_info_frame { /* Adaptive Sync SDP*/ struct dc_info_packet adaptive_sync; struct enc_sdp_line_num sdp_line_num; + bool firmware_controlled_hdr_info_packet; }; struct encoder_unblank_param { diff --git a/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h b/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h index 23daf98b8aa8..6a97a3e28bd2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h @@ -8,9 +8,26 @@ #include "dc.h" #include "dml_top_soc_parameter_types.h" +/* Forward declarations — callers that dereference these structs must include + * the full UTM model headers themselves. */ +struct utm_qos_model; +struct utm_qos_model_dchub_v2; + struct soc_and_ip_translator_funcs { - void (*get_soc_bb)(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config); + void (*get_soc_bb)( + struct dml2_soc_bb *soc_bb, + const struct dc *dc, + const struct dml2_configuration_options *config); void (*get_ip_caps)(struct dml2_ip_capabilities *dml_ip_caps); + /** + * get_utm_qos_model - Return the static UTM QoS model for this DCN + * generation. Caller provides storage for @qos_model and @dchub. + * @qos_model: output — populated with SoC bounding box and SOP table + * @dchub: output — populated with DCHUB client extension data + */ + void (*get_utm_qos_model)( + struct utm_qos_model *qos_model, + struct utm_qos_model_dchub_v2 *dchub); }; struct soc_and_ip_translator { diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c index 015f3659cf77..8958d286dde1 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c @@ -210,7 +210,7 @@ bool dce110_vblank_set(struct irq_service *irq_service, dc_interrupt_to_irq_source(irq_service->ctx->dc, info->src_id, info->ext_id); - uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; + unsigned int pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; struct timing_generator *tg; diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c index 060460abc377..ae6ed3a52d53 100644 --- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c +++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c @@ -199,7 +199,6 @@ static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video unsigned int channel_count; unsigned int channel = 0; unsigned int modes = 0; - unsigned int sampling_rate_in_hz = 0; // get audio test mode and test pattern parameters core_link_read_dpcd( @@ -232,38 +231,10 @@ static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video } } - // translate sampling rate - switch (dpcd_test_mode.bits.sampling_rate) { - case AUDIO_SAMPLING_RATE_32KHZ: - sampling_rate_in_hz = 32000; - break; - case AUDIO_SAMPLING_RATE_44_1KHZ: - sampling_rate_in_hz = 44100; - break; - case AUDIO_SAMPLING_RATE_48KHZ: - sampling_rate_in_hz = 48000; - break; - case AUDIO_SAMPLING_RATE_88_2KHZ: - sampling_rate_in_hz = 88200; - break; - case AUDIO_SAMPLING_RATE_96KHZ: - sampling_rate_in_hz = 96000; - break; - case AUDIO_SAMPLING_RATE_176_4KHZ: - sampling_rate_in_hz = 176400; - break; - case AUDIO_SAMPLING_RATE_192KHZ: - sampling_rate_in_hz = 192000; - break; - default: - sampling_rate_in_hz = 0; - break; - } - link->audio_test_data.flags.test_requested = 1; link->audio_test_data.flags.disable_video = disable_video; - link->audio_test_data.sampling_rate = sampling_rate_in_hz; - link->audio_test_data.channel_count = channel_count; + link->audio_test_data.sampling_rate = (uint8_t)dpcd_test_mode.bits.sampling_rate; + link->audio_test_data.channel_count = (uint8_t)channel_count; link->audio_test_data.pattern_type = test_pattern; if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) { @@ -885,7 +856,7 @@ bool dp_set_test_pattern( struct dmub_hw_lock_inst_flags inst_flags = { 0 }; hw_locks.bits.lock_dig = 1; - inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst; + inst_flags.dig_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv, true, @@ -933,7 +904,7 @@ bool dp_set_test_pattern( struct dmub_hw_lock_inst_flags inst_flags = { 0 }; hw_locks.bits.lock_dig = 1; - inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst; + inst_flags.dig_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv, false, diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c index dbbedeeed298..04df75114dd5 100644 --- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c +++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c @@ -63,7 +63,7 @@ void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx, time_slot_in_ms = dc_fixpt_from_fraction(32 * 4, link_bw_in_kbps); mtp_cnt_per_h_blank = dc_fixpt_div(h_blank_in_ms, dc_fixpt_mul_int(time_slot_in_ms, 64)); - hblank_min_symbol_width = dc_fixpt_floor( + hblank_min_symbol_width = (uint16_t)dc_fixpt_floor( dc_fixpt_mul(mtp_cnt_per_h_blank, throttled_vcp_size)); } @@ -98,7 +98,7 @@ void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx) &stream->timing, stream->output_color_space, stream->use_vsc_sdp_for_colorimetry, - stream->timing.flags.DSC, + (stream->timing.flags.DSC != 0), false); link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 794dd6a95918..026c55ca0196 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -290,12 +290,12 @@ static bool i2c_read( struct i2c_payload payloads[2] = { { .write = true, - .address = address, + .address = (uint8_t)address, .length = 1, .data = &offs_data }, { .write = false, - .address = address, + .address = (uint8_t)address, .length = len, .data = buffer } }; @@ -524,7 +524,7 @@ static void read_current_link_settings_on_detect(struct dc_link *link) uint8_t link_rate_set = 0; uint32_t read_dpcd_retry_cnt = 10; enum dc_status status = DC_ERROR_UNEXPECTED; - int i; + unsigned int i; union max_down_spread max_down_spread = {0}; // Read DPCD 00101h to find out the number of lanes currently set @@ -655,7 +655,7 @@ static bool wait_for_entering_dp_alt_mode(struct dc_link *link) unsigned long long enter_timestamp; unsigned long long finish_timestamp; unsigned long long time_taken_in_ns; - int tries_taken; + unsigned int tries_taken; /** * this function will only exist if we are on dcn21 (is_in_alt_mode is a @@ -1619,7 +1619,7 @@ struct dc_sink *link_add_remote_sink( void link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) { - int i; + unsigned int i; if (!link->sink_count) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index e12c25896364..d52155e86f0f 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -546,24 +546,24 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; /* stream encoder index */ - config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; + config.stream_enc_idx = (uint8_t)(pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA); if (dp_is_128b_132b_signal(pipe_ctx)) config.stream_enc_idx = - pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; + (uint8_t)(pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0); /* dig back end */ config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; /* link encoder index */ - config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; + config.link_enc_idx = (uint8_t)(link_enc->transmitter - TRANSMITTER_UNIPHY_A); if (dp_is_128b_132b_signal(pipe_ctx)) - config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; + config.link_enc_idx = (uint8_t)pipe_ctx->link_res.hpo_dp_link_enc->inst; /* dio output index is dpia index for DPIA endpoint & dcio index by default */ if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) - config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; + config.dio_output_idx = (uint8_t)(pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1); else - config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; + config.dio_output_idx = (uint8_t)(link_enc->transmitter - TRANSMITTER_UNIPHY_A); /* phy index */ @@ -1411,7 +1411,7 @@ static bool write_128b_132b_sst_payload_allocation_table( if (allocate) { avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); - req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); + req_slot_count = (uint8_t)dc_fixpt_ceil(avg_time_slots_per_mtp); /// Validation should filter out modes that exceed link BW ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); if (req_slot_count > MAX_MTP_SLOT_COUNT) @@ -1811,7 +1811,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) write_scdc_data( stream->link->ddc, stream->phy_pix_clk, - stream->timing.flags.LTE_340MCSC_SCRAMBLE); + (stream->timing.flags.LTE_340MCSC_SCRAMBLE != 0)); memset(&stream->link->cur_link_settings, 0, sizeof(struct dc_link_settings)); @@ -2016,9 +2016,7 @@ static enum dc_status enable_link_dp_mst( return enable_link_dp(state, pipe_ctx); } -static enum dc_status enable_link_analog( - struct dc_state *state, - struct pipe_ctx *pipe_ctx) +static enum dc_status enable_link_analog(struct pipe_ctx *pipe_ctx) { struct dc_link *link = pipe_ctx->stream->link; @@ -2083,7 +2081,7 @@ static enum dc_status enable_link( status = DC_OK; break; case SIGNAL_TYPE_RGB: - status = enable_link_analog(state, pipe_ctx); + status = enable_link_analog(pipe_ctx); break; case SIGNAL_TYPE_VIRTUAL: status = enable_link_virtual(pipe_ctx); @@ -2111,7 +2109,7 @@ static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, i if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { int sink_index = 0; - int i = 0; + unsigned int i = 0; for (i = 0; i < link->sink_count; i++) { if (link->remote_sinks[i] == NULL) @@ -2132,7 +2130,7 @@ static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, i link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw); if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { - int i = 0; + unsigned int i = 0; for (i = 0; i < link->sink_count; i++) { if (link->remote_sinks[i] == NULL) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index 7e7682d7dfc8..032c97660658 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -381,7 +381,7 @@ static bool encoder_is_external_dp( static void link_destruct(struct dc_link *link) { - int i; + unsigned int i; if (link->ddc) link_destroy_ddc_service(&link->ddc); @@ -516,7 +516,7 @@ static bool construct_phy(struct dc_link *link, sizeof(struct dc_link_settings)); link->link_id = - bios->funcs->get_connector_id(bios, init_params->connector_index); + bios->funcs->get_connector_id(bios, (uint8_t)init_params->connector_index); link->ep_type = DISPLAY_ENDPOINT_PHY; @@ -544,7 +544,7 @@ static bool construct_phy(struct dc_link *link, if (bios->funcs->get_disp_connector_caps_info) { bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info); - link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY; + link->is_internal_display = (disp_connect_caps_info.INTERNAL_DISPLAY != 0); DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display); } @@ -568,7 +568,9 @@ static bool construct_phy(struct dc_link *link, goto ddc_create_fail; } - if (!link->ddc->ddc_pin) { + /* Embedded display connectors such as LVDS may not have DDC. */ + if (!link->ddc->ddc_pin && + !dc_is_embedded_signal(link->connector_signal)) { DC_ERROR("Failed to get I2C info for connector!\n"); goto ddc_create_fail; } @@ -895,7 +897,7 @@ static bool construct_dpia(struct dc_link *link, } /* Set dpia port index : 0 to number of dpia ports */ - link->ddc_hw_inst = init_params->connector_index; + link->ddc_hw_inst = (uint8_t)init_params->connector_index; // Assign Dpia preferred eng_id if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c index eb791285ed06..ec083e8b75b4 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c @@ -302,9 +302,11 @@ static bool dp_validate_mode_timing( req_bw = dc_bandwidth_in_kbps_from_timing(timing, dc_link_get_highest_encoding_format(link)); max_bw = dp_link_bandwidth_kbps(link, link_setting); + uint32_t max_uncompressed_pixel_rate_100hz = + link->dpcd_caps.max_uncompressed_pixel_rate_cap.bits.max_uncompressed_pixel_rate_cap * 10000U; bool is_max_uncompressed_pixel_rate_exceeded = link->dpcd_caps.max_uncompressed_pixel_rate_cap.bits.valid && - timing->pix_clk_100hz > link->dpcd_caps.max_uncompressed_pixel_rate_cap.bits.max_uncompressed_pixel_rate_cap * 10000; + timing->pix_clk_100hz > max_uncompressed_pixel_rate_100hz; if (is_max_uncompressed_pixel_rate_exceeded && !timing->flags.DSC) { return false; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c index a66217e54a09..1bf0903a3cf8 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c @@ -96,7 +96,7 @@ static void i2c_payloads_add( for (pos = 0; pos < len; pos += payload_size) { struct i2c_payload payload = { .write = write, - .address = address, + .address = (uint8_t)address, .length = DDC_MIN(payload_size, len - pos), .data = data + pos }; dal_vector_append(&payloads->payloads, &payload); @@ -384,8 +384,7 @@ bool link_query_ddc_data( i2c_payloads_add( &payloads, address, read_size, read_buf, false); - command.number_of_payloads = - i2c_payloads_get_count(&payloads); + command.number_of_payloads = (uint8_t)i2c_payloads_get_count(&payloads); success = dm_helpers_submit_i2c( ddc->ctx, diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 782a45caa13d..817b4010edcb 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -1353,7 +1353,7 @@ bool dp_overwrite_extended_receiver_cap(struct dc_link *link) union down_stream_port_count down_strm_port_count; union edp_configuration_cap edp_config_cap; - int i; + unsigned int i; for (i = 0; i < read_dpcd_retry_cnt; i++) { status = core_link_read_dpcd( @@ -1713,7 +1713,7 @@ enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link) CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: "); // Identify closest LTTPR to determine if workarounds required for known embedded LTTPR - closest_lttpr_offset = dp_get_closest_lttpr_offset(lttpr_count); + closest_lttpr_offset = dp_get_closest_lttpr_offset((uint8_t)lttpr_count); core_link_read_dpcd(link, (DP_LTTPR_IEEE_OUI + closest_lttpr_offset), link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui)); @@ -1752,7 +1752,7 @@ static bool retrieve_link_cap(struct dc_link *link) union dp_downstream_port_present ds_port = { 0 }; enum dc_status status = DC_ERROR_UNEXPECTED; uint32_t read_dpcd_retry_cnt = 20; - int i; + unsigned int i; struct dp_sink_hw_fw_revision dp_hw_fw_revision; const uint32_t post_oui_delay = 30; // 30ms bool is_fec_supported = false; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c index 766b54631c79..da227889e007 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c @@ -119,7 +119,7 @@ bool dpia_query_hpd_status(struct dc_link *link) /* prepare QUERY_HPD command */ cmd.query_hpd.header.type = DMUB_CMD__QUERY_HPD_STATE; cmd.query_hpd.header.payload_bytes = sizeof(cmd.query_hpd.data); - cmd.query_hpd.data.instance = link->link_id.enum_id - ENUM_ID_1; + cmd.query_hpd.data.instance = (uint8_t)(link->link_id.enum_id - ENUM_ID_1); cmd.query_hpd.data.ch_type = AUX_CHANNEL_DPIA; /* Query dpia hpd status from dmub */ diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c index c958d3f600c8..dd854d992692 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c @@ -112,7 +112,7 @@ static int get_estimated_bw(struct dc_link *link) return bw_estimated_bw * (Kbps_TO_Gbps / link->dpia_bw_alloc_config.bw_granularity); } -static int get_non_reduced_max_link_rate(struct dc_link *link) +static uint8_t get_non_reduced_max_link_rate(struct dc_link *link) { uint8_t nrd_max_link_rate = 0; @@ -125,7 +125,7 @@ static int get_non_reduced_max_link_rate(struct dc_link *link) return nrd_max_link_rate; } -static int get_non_reduced_max_lane_count(struct dc_link *link) +static uint8_t get_non_reduced_max_lane_count(struct dc_link *link) { uint8_t nrd_max_lane_count = 0; @@ -180,7 +180,7 @@ static void dpia_bw_alloc_unplug(struct dc_link *link) static void link_dpia_send_bw_alloc_request(struct dc_link *link, int req_bw) { - uint8_t request_reg_val; + uint32_t request_reg_val; uint32_t temp, request_bw; if (link->dpia_bw_alloc_config.bw_granularity == 0) { @@ -197,7 +197,7 @@ static void link_dpia_send_bw_alloc_request(struct dc_link *link, int req_bw) request_bw = request_reg_val * (Kbps_TO_Gbps / link->dpia_bw_alloc_config.bw_granularity); - if (request_bw > link->dpia_bw_alloc_config.estimated_bw) { + if (request_bw > (uint32_t)link->dpia_bw_alloc_config.estimated_bw) { DC_LOG_ERROR("%s: Link[%d]: Request BW (%d --> %d) > Estimated BW (%d)... Set to Estimated BW!", __func__, link->link_index, req_bw, request_bw, link->dpia_bw_alloc_config.estimated_bw); @@ -212,8 +212,8 @@ static void link_dpia_send_bw_alloc_request(struct dc_link *link, int req_bw) link->dpia_bw_alloc_config.allocated_bw = request_bw; DC_LOG_DC("%s: Link[%d]: Request BW: %d", __func__, link->link_index, request_bw); - core_link_write_dpcd(link, REQUESTED_BW, - &request_reg_val, + uint8_t requested_bw_dpcd = (uint8_t)request_reg_val; + core_link_write_dpcd(link, REQUESTED_BW, &requested_bw_dpcd, sizeof(uint8_t)); } diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c index 1860d44f63c1..f9e0ba24d401 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c @@ -65,7 +65,7 @@ bool dp_parse_link_loss_status( /*1. Check that Link Status changed, before re-training.*/ /*parse lane status*/ - for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { + for (lane = 0; lane < (uint32_t)link->cur_link_settings.lane_count; lane++) { /* check status of lanes 0,1 * changed DpcdAddress_Lane01Status (0x202) */ @@ -223,7 +223,7 @@ static void handle_hpd_irq_vesa_replay_sink(struct dc_link *link) } } -static void handle_hpd_irq_replay_sink(struct dc_link *link, bool *need_re_enable) +static void handle_hpd_irq_replay_sink(struct dc_link *link, bool *need_re_enable, bool *replay_esd_detection_needed) { union dpcd_replay_configuration replay_configuration = {0}; union dpcd_replay_configuration replay_sink_status = {0}; @@ -311,6 +311,14 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link, bool *need_re_enabl *need_re_enable = true; } } + + if (!link->replay_settings.replay_allow_active && + replay_sink_status.bits.SINK_DEVICE_REPLAY_STATUS == 0x7) { + /* If sink device replay status is 0x7 and replay is disabled, + * it means sink is in a bad state and link retraining is needed to recover + */ + *replay_esd_detection_needed = true; + } } void dp_handle_link_loss(struct dc_link *link) @@ -469,6 +477,7 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, enum dc_status result; bool status = false; bool replay_re_enable_needed = false; + bool replay_esd_detection_needed = false; if (out_link_loss) *out_link_loss = false; @@ -482,6 +491,7 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n", __func__, link->link_index); + handle_hpd_irq_replay_sink(link, &replay_re_enable_needed, &replay_esd_detection_needed); /* All the "handle_hpd_irq_xxx()" methods * should be called only after @@ -528,8 +538,6 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, /* PSR-related error was detected and handled */ return true; - handle_hpd_irq_replay_sink(link, &replay_re_enable_needed); - /* If PSR-related error handled, Main link may be off, * so do not handle as a normal sink status change interrupt. */ @@ -552,27 +560,30 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, * Downstream port status changed, * then DM should call DC to do the detection. * NOTE: Now includes eDP link loss detection and retraining + * Link will be retrained if panel is not EDP or + * Replay ESD recovery is needed. */ + if (link->connector_signal != SIGNAL_TYPE_EDP || replay_esd_detection_needed) { + if (dp_parse_link_loss_status( + link, + &hpd_irq_dpcd_data)) { + /* Connectivity log: link loss */ + CONN_DATA_LINK_LOSS(link, + hpd_irq_dpcd_data.raw, + sizeof(hpd_irq_dpcd_data), + "Status: "); - if (dp_parse_link_loss_status( - link, - &hpd_irq_dpcd_data)) { - /* Connectivity log: link loss */ - CONN_DATA_LINK_LOSS(link, - hpd_irq_dpcd_data.raw, - sizeof(hpd_irq_dpcd_data), - "Status: "); + if (defer_handling && has_left_work) + *has_left_work = true; + else + dp_handle_link_loss(link); - if (defer_handling && has_left_work) - *has_left_work = true; - else - dp_handle_link_loss(link); + status = false; + if (out_link_loss) + *out_link_loss = true; - status = false; - if (out_link_loss) - *out_link_loss = true; - - dp_trace_link_loss_increment(link); + dp_trace_link_loss_increment(link); + } } if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling) { diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c index 96afce4ffbfa..72d6e6011a09 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c @@ -60,11 +60,10 @@ static void dp_pr_set_static_screen_param(struct dc_link *link) if (dc->current_state->res_ctx.pipe_ctx[i].stream && dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) { struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; - unsigned int vsync_rate_hz = div64_u64(div64_u64( - (stream->timing.pix_clk_100hz * (u64)100), - stream->timing.v_total), - stream->timing.h_total); - + unsigned int vsync_rate_hz = (unsigned int)div64_u64(div64_u64( + (stream->timing.pix_clk_100hz * (u64)100), + stream->timing.v_total), + stream->timing.h_total); params.triggers.cursor_update = true; params.triggers.overlay_update = true; params.triggers.surface_update = true; @@ -264,7 +263,7 @@ bool dp_pr_enable(struct dc_link *link, bool enable) cmd.pr_enable.header.type = DMUB_CMD__PR; cmd.pr_enable.header.sub_type = DMUB_CMD__PR_ENABLE; cmd.pr_enable.header.payload_bytes = sizeof(struct dmub_cmd_pr_enable_data); - cmd.pr_enable.data.panel_inst = panel_inst; + cmd.pr_enable.data.panel_inst = (uint8_t)panel_inst; cmd.pr_enable.data.enable = enable ? 1 : 0; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); @@ -301,17 +300,17 @@ bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_con cmd.pr_copy_settings.header.type = DMUB_CMD__PR; cmd.pr_copy_settings.header.sub_type = DMUB_CMD__PR_COPY_SETTINGS; cmd.pr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_pr_copy_settings_data); - cmd.pr_copy_settings.data.panel_inst = panel_inst; + cmd.pr_copy_settings.data.panel_inst = (uint8_t)panel_inst; // HW inst cmd.pr_copy_settings.data.aux_inst = replay_context->aux_inst; cmd.pr_copy_settings.data.digbe_inst = replay_context->digbe_inst; cmd.pr_copy_settings.data.digfe_inst = replay_context->digfe_inst; if (pipe_ctx->plane_res.dpp) - cmd.pr_copy_settings.data.dpp_inst = pipe_ctx->plane_res.dpp->inst; + cmd.pr_copy_settings.data.dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst; else cmd.pr_copy_settings.data.dpp_inst = 0; if (pipe_ctx->stream_res.tg) - cmd.pr_copy_settings.data.otg_inst = pipe_ctx->stream_res.tg->inst; + cmd.pr_copy_settings.data.otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; else cmd.pr_copy_settings.data.otg_inst = 0; @@ -329,9 +328,9 @@ bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_con link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps; if (pipe_ctx->stream->timing.dsc_cfg.num_slices_v > 0) - cmd.pr_copy_settings.data.dsc_slice_height = (pipe_ctx->stream->timing.v_addressable + + cmd.pr_copy_settings.data.dsc_slice_height = (uint16_t)((pipe_ctx->stream->timing.v_addressable + pipe_ctx->stream->timing.v_border_top + pipe_ctx->stream->timing.v_border_bottom) / - pipe_ctx->stream->timing.dsc_cfg.num_slices_v; + pipe_ctx->stream->timing.dsc_cfg.num_slices_v); if (dc_is_embedded_signal(link->connector_signal)) cmd.pr_copy_settings.data.main_link_activity_option = OPTION_1C; @@ -358,7 +357,7 @@ bool dp_pr_update_state(struct dc_link *link, struct dmub_cmd_pr_update_state_da cmd.pr_update_state.header.type = DMUB_CMD__PR; cmd.pr_update_state.header.sub_type = DMUB_CMD__PR_UPDATE_STATE; cmd.pr_update_state.header.payload_bytes = sizeof(struct dmub_cmd_pr_update_state_data); - cmd.pr_update_state.data.panel_inst = panel_inst; + cmd.pr_update_state.data.panel_inst = (uint8_t)panel_inst; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); return true; @@ -379,7 +378,7 @@ bool dp_pr_set_general_cmd(struct dc_link *link, struct dmub_cmd_pr_general_cmd_ cmd.pr_general_cmd.header.type = DMUB_CMD__PR; cmd.pr_general_cmd.header.sub_type = DMUB_CMD__PR_GENERAL_CMD; cmd.pr_general_cmd.header.payload_bytes = sizeof(struct dmub_cmd_pr_general_cmd_data); - cmd.pr_general_cmd.data.panel_inst = panel_inst; + cmd.pr_general_cmd.data.panel_inst = (uint8_t)panel_inst; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); return true; @@ -397,7 +396,7 @@ bool dp_pr_get_state(const struct dc_link *link, uint64_t *state) do { // Send gpint command and wait for ack - if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__GET_REPLAY_STATE, panel_inst, + if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__GET_REPLAY_STATE, (uint16_t)panel_inst, &replay_state, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) { // Return invalid state when GPINT times out replay_state = PR_STATE_INVALID; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c index ddff0db4ce70..605bf19dc4f2 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c @@ -310,7 +310,7 @@ static void maximize_lane_settings(const struct link_training_settings *lt_setti max_requested.FFE_PRESET = lane_settings[0].FFE_PRESET; /* Determine what the maximum of the requested settings are*/ - for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) { + for (lane = 1; lane < (uint32_t)lt_settings->link_settings.lane_count; lane++) { if (lane_settings[lane].VOLTAGE_SWING > max_requested.VOLTAGE_SWING) max_requested.VOLTAGE_SWING = lane_settings[lane].VOLTAGE_SWING; @@ -568,7 +568,7 @@ enum link_training_result dp_check_link_loss_status( sizeof(dpcd_buf)); /*parse lane status*/ - for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { + for (lane = 0; lane < (uint32_t)link->cur_link_settings.lane_count; lane++) { /* * check lanes status */ diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c index 66d0fb1b9b9d..4331e032416f 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c @@ -132,7 +132,7 @@ void decide_8b_10b_training_settings( */ lt_settings->link_settings.link_spread = link->dp_ss_off ? LINK_SPREAD_DISABLED : LINK_SPREAD_05_DOWNSPREAD_30KHZ; - lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting); + lt_settings->eq_pattern_time = (uint16_t)get_eq_training_aux_rd_interval(link, link_setting); lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting); lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_res, link_setting); lt_settings->enhanced_framing = 1; @@ -140,7 +140,7 @@ void decide_8b_10b_training_settings( lt_settings->disallow_per_lane_settings = true; lt_settings->always_match_dpcd_with_hw_lane_settings = true; lt_settings->lttpr_mode = dp_decide_8b_10b_lttpr_mode(link); - lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting, lt_settings->lttpr_mode); + lt_settings->cr_pattern_time = (uint16_t)get_cr_training_aux_rd_interval(link, link_setting, lt_settings->lttpr_mode); dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); /* Some embedded LTTPRs rely on receiving TPS2 before LT to interop reliably with sensitive VGA dongles @@ -195,7 +195,7 @@ static void set_link_settings_and_perform_early_tps2_retimer_pre_lt_sequence(str * 6. Begin link training as usual * */ - uint32_t closest_lttpr_address_offset = dp_get_closest_lttpr_offset(lttpr_count); + uint32_t closest_lttpr_address_offset = dp_get_closest_lttpr_offset((uint8_t)lttpr_count); union dpcd_training_pattern dpcd_pattern = {0}; @@ -379,7 +379,7 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence( dpcd_set_lane_settings(link, lt_settings, offset); /* 3. wait for receiver to lock-on*/ - wait_time_microsec = dp_get_eq_aux_rd_interval(link, lt_settings, offset, retries_ch_eq); + wait_time_microsec = dp_get_eq_aux_rd_interval(link, lt_settings, offset, (uint8_t)retries_ch_eq); dp_wait_for_training_aux_rd_interval( link, @@ -408,7 +408,7 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence( /* 6. check CHEQ done*/ if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && dp_is_symbol_locked(lane_count, dpcd_lane_status) && - dp_check_interlane_aligned(dpcd_lane_status_updated, link, retries_ch_eq)) + dp_check_interlane_aligned(dpcd_lane_status_updated, link, (uint8_t)retries_ch_eq)) return LINK_TRAINING_SUCCESS; /* 7. update VS/PE/PC2 in lt_settings*/ diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 4a2699a374b7..6aa65815af22 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -601,12 +601,12 @@ bool edp_set_psr_allow_active(struct dc_link *link, const bool *allow_active, link->psr_settings.psr_power_opt = *power_opts; if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt) - psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst); + psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, (uint8_t)panel_inst); } if (psr != NULL && link->psr_settings.psr_feature_enabled && force_static && psr->funcs->psr_force_static) - psr->funcs->psr_force_static(psr, panel_inst); + psr->funcs->psr_force_static(psr, (uint8_t)panel_inst); /* Enable or Disable PSR */ if (allow_active && link->psr_settings.psr_allow_active != *allow_active) { @@ -615,9 +615,9 @@ bool edp_set_psr_allow_active(struct dc_link *link, const bool *allow_active, if (!link->psr_settings.psr_allow_active) dc_z10_restore(dc); - if (psr != NULL && link->psr_settings.psr_feature_enabled) { - psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst); - } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && + if (psr != NULL && link->psr_settings.psr_feature_enabled) + psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, (uint8_t)panel_inst); + else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled) dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait); else @@ -637,7 +637,7 @@ bool edp_get_psr_state(const struct dc_link *link, enum dc_psr_state *state) return false; if (psr != NULL && link->psr_settings.psr_feature_enabled) - psr->funcs->psr_get_state(psr, state, panel_inst); + psr->funcs->psr_get_state(psr, state, (uint8_t)panel_inst); else if (dmcu != NULL && link->psr_settings.psr_feature_enabled) dmcu->funcs->get_psr_state(dmcu, state); @@ -811,7 +811,7 @@ bool edp_setup_psr(struct dc_link *link, psr_context->smuPhyId = transmitter_to_phy_id(link); psr_context->crtcTimingVerticalTotal = stream->timing.v_total; - psr_context->vsync_rate_hz = div64_u64(div64_u64((stream-> + psr_context->vsync_rate_hz = (unsigned int)div64_u64(div64_u64((stream-> timing.pix_clk_100hz * (u64)100), stream->timing.v_total), stream->timing.h_total); @@ -885,7 +885,7 @@ bool edp_setup_psr(struct dc_link *link, if (psr) { link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr, - link, psr_context, panel_inst); + link, psr_context, (uint8_t)panel_inst); link->psr_settings.psr_power_opt = 0; link->psr_settings.psr_allow_active = 0; } else { @@ -913,7 +913,7 @@ void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency, enum // PSR residency measurements only supported on DMCUB if (psr != NULL && link->psr_settings.psr_feature_enabled) - psr->funcs->psr_get_residency(psr, residency, panel_inst, mode); + psr->funcs->psr_get_residency(psr, residency, (uint8_t)panel_inst, mode); else *residency = 0; } @@ -947,7 +947,7 @@ bool edp_set_replay_allow_active(struct dc_link *link, const bool *allow_active, if (power_opts && link->replay_settings.replay_power_opt_active != *power_opts) { if (replay != NULL && link->replay_settings.replay_feature_enabled && replay->funcs->replay_set_power_opt) { - replay->funcs->replay_set_power_opt(replay, *power_opts, panel_inst); + replay->funcs->replay_set_power_opt(replay, *power_opts, (uint8_t)panel_inst); link->replay_settings.replay_power_opt_active = *power_opts; } } @@ -957,7 +957,7 @@ bool edp_set_replay_allow_active(struct dc_link *link, const bool *allow_active, // TODO: Handle mux change case if force_static is set // If force_static is set, just change the replay_allow_active state directly if (replay != NULL && link->replay_settings.replay_feature_enabled) - replay->funcs->replay_enable(replay, *allow_active, wait, panel_inst); + replay->funcs->replay_enable(replay, *allow_active, wait, (uint8_t)panel_inst); link->replay_settings.replay_allow_active = *allow_active; } @@ -975,7 +975,7 @@ bool edp_get_replay_state(const struct dc_link *link, uint64_t *state) return false; if (replay != NULL && link->replay_settings.replay_feature_enabled) - replay->funcs->replay_get_state(replay, &pr_state, panel_inst); + replay->funcs->replay_get_state(replay, &pr_state, (uint8_t)panel_inst); *state = pr_state; return true; @@ -1046,12 +1046,11 @@ bool edp_setup_freesync_replay(struct dc_link *link, const struct dc_stream_stat replay_context.os_request_force_ffu = link->replay_settings.config.os_request_force_ffu; link->replay_settings.replay_feature_enabled = - replay->funcs->replay_copy_settings(replay, link, &replay_context, panel_inst); + replay->funcs->replay_copy_settings(replay, link, &replay_context, (uint8_t)panel_inst); if (link->replay_settings.replay_feature_enabled) { replay_config.bits.FREESYNC_PANEL_REPLAY_MODE = 1; - replay_config.bits.TIMING_DESYNC_ERROR_VERIFICATION = - link->replay_settings.config.replay_timing_sync_supported; + replay_config.bits.TIMING_DESYNC_ERROR_VERIFICATION = 0; replay_config.bits.STATE_TRANSITION_ERROR_DETECTION = 1; dm_helpers_dp_write_dpcd(link->ctx, link, DP_SINK_PR_ENABLE_AND_CONFIGURATION, @@ -1096,7 +1095,7 @@ bool edp_send_replay_cmd(struct dc_link *link, return false; if (dp_pr_get_panel_inst(dc, link, &panel_inst)) - cmd_data->panel_inst = panel_inst; + cmd_data->panel_inst = (uint8_t)panel_inst; else { DC_LOG_DC("%s(): get edp panel inst fail ", __func__); return false; @@ -1121,7 +1120,7 @@ bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal, uin if (coasting_vtotal && (link->replay_settings.coasting_vtotal != coasting_vtotal || link->replay_settings.frame_skip_number != frame_skip_number)) { - replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, panel_inst, frame_skip_number); + replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, (uint8_t)panel_inst, frame_skip_number); link->replay_settings.coasting_vtotal = coasting_vtotal; link->replay_settings.frame_skip_number = frame_skip_number; } @@ -1143,7 +1142,7 @@ bool edp_replay_residency(const struct dc_link *link, return false; if (replay != NULL && link->replay_settings.replay_feature_enabled) - replay->funcs->replay_residency(replay, panel_inst, residency, is_start, mode); + replay->funcs->replay_residency(replay, (uint8_t)panel_inst, residency, is_start, mode); else *residency = 0; @@ -1168,7 +1167,7 @@ bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link, if (link->replay_settings.replay_feature_enabled && replay->funcs->replay_set_power_opt_and_coasting_vtotal) { replay->funcs->replay_set_power_opt_and_coasting_vtotal(replay, - *power_opts, panel_inst, coasting_vtotal, frame_skip_number); + *power_opts, (uint8_t)panel_inst, coasting_vtotal, frame_skip_number); link->replay_settings.replay_power_opt_active = *power_opts; link->replay_settings.coasting_vtotal = coasting_vtotal; link->replay_settings.frame_skip_number = frame_skip_number; @@ -1252,10 +1251,10 @@ static void edp_set_assr_enable(const struct dc *pDC, struct dc_link *link, memset(&cmd, 0, sizeof(cmd)); - link_enc_index = link->link_enc->transmitter - TRANSMITTER_UNIPHY_A; + link_enc_index = (uint8_t)(link->link_enc->transmitter - TRANSMITTER_UNIPHY_A); if (link_res->hpo_dp_link_enc) { - link_enc_index = link_res->hpo_dp_link_enc->inst; + link_enc_index = (uint8_t)link_res->hpo_dp_link_enc->inst; use_hpo_dp_link_enc = true; } diff --git a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c index 2a422e223bf2..2e0f07ec04e4 100644 --- a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c +++ b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c @@ -40,8 +40,8 @@ #define FN(reg_name, field_name) \ mcif_wb20->mcif_wb_shift->field_name, mcif_wb20->mcif_wb_mask->field_name -#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8 -#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40 +#define MCIF_ADDR(addr) ((uint32_t)((((unsigned long long)(addr) & 0xffffffffffULL) + 0xFEULL) >> 8)) +#define MCIF_ADDR_HIGH(addr) ((uint32_t)(((unsigned long long)(addr)) >> 40)) /* wbif programming guide: * 1. set up wbif parameter: diff --git a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c index c3b089ba511a..6b6f80a3bfd5 100644 --- a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c +++ b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c @@ -40,8 +40,8 @@ #define FN(reg_name, field_name) \ mcif_wb30->mcif_wb_shift->field_name, mcif_wb30->mcif_wb_mask->field_name -#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8 -#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40 +#define MCIF_ADDR(addr) ((uint32_t)((((unsigned long long)(addr) & 0xffffffffffULL) + 0xFEULL) >> 8)) +#define MCIF_ADDR_HIGH(addr) ((uint32_t)(((unsigned long long)(addr)) >> 40)) /* wbif programming guide: * 1. set up wbif parameter: diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c index 27e653234850..0779db249765 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c @@ -422,7 +422,7 @@ void mpc1_init_mpcc_list_from_hw( if (out_mux == mpcc_id) tree->opp_list = mpcc; - if (bot_sel != 0xf && bot_sel < mpc10->num_mpcc) { + if (bot_sel != 0xf && bot_sel < (unsigned int)mpc10->num_mpcc) { bot_mpcc_id = bot_sel; REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id); REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel); diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c index e0617db2d0c1..ce1ee2062e41 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c @@ -73,15 +73,56 @@ void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_locati } } -void mpc401_populate_lut(struct mpc *mpc, - const enum MCM_LUT_ID id, - const union mcm_lut_params *params, - const bool lut_bank_a, - const int mpcc_id) +static enum dc_lut_mode get3dlut_config( + struct mpc *mpc, + bool *is_17x17x17, + bool *is_12bits_color_channel, + int mpcc_id) +{ + uint32_t i_mode, i_enable_10bits, lut_size; + enum dc_lut_mode mode; + struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); + + REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], + MPCC_MCM_3DLUT_MODE_CURRENT, &i_mode); + + REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPCC_MCM_3DLUT_30BIT_EN, &i_enable_10bits); + + switch (i_mode) { + case 0: + mode = LUT_BYPASS; + break; + case 1: + mode = LUT_RAM_A; + break; + case 2: + mode = LUT_RAM_B; + break; + default: + mode = LUT_BYPASS; + break; + } + if (i_enable_10bits > 0) + *is_12bits_color_channel = false; + else + *is_12bits_color_channel = true; + + REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size); + + if (lut_size == 0) + *is_17x17x17 = true; + else + *is_17x17x17 = false; + + return mode; +} + +void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, bool lut_bank_a, int mpcc_id) { const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B; - const struct pwl_params *lut1d = params->pwl; - const struct pwl_params *lut_shaper = params->pwl; + const struct pwl_params *lut1d = params.pwl; + const struct pwl_params *lut_shaper = params.pwl; bool is_17x17x17; bool is_12bits_color_channel; const struct dc_rgb *lut0; @@ -90,7 +131,7 @@ void mpc401_populate_lut(struct mpc *mpc, const struct dc_rgb *lut3; int lut_size0; int lut_size; - const struct tetrahedral_params *lut3d = params->lut3d; + const struct tetrahedral_params *lut3d = params.lut3d; switch (id) { case MCM_LUT_1DLUT: @@ -133,6 +174,8 @@ void mpc401_populate_lut(struct mpc *mpc, mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true); + get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id); + is_17x17x17 = !lut3d->use_tetrahedral_9; is_12bits_color_channel = lut3d->use_12bits; if (is_17x17x17) { @@ -155,6 +198,8 @@ void mpc401_populate_lut(struct mpc *mpc, sizeof(lut3d->tetrahedral_9.lut1[0]); } + mpc32_select_3dlut_ram(mpc, next_mode, + is_12bits_color_channel, mpcc_id); mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id); if (is_12bits_color_channel) mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id); @@ -187,69 +232,46 @@ void mpc401_populate_lut(struct mpc *mpc, } -static uint32_t mpc401_cm_lut_size_to_3dlut_size(const enum dc_cm_lut_size cm_size) -{ - uint32_t size = 0; - - switch (cm_size) { - case CM_LUT_SIZE_999: - size = 1; - break; - case CM_LUT_SIZE_171717: - size = 0; - break; - default: - /* invalid LUT size */ - ASSERT(false); - size = 0; - break; - } - - return size; -} - void mpc401_program_lut_mode( struct mpc *mpc, const enum MCM_LUT_ID id, - const bool enable, - const bool lut_bank_a, - const enum dc_cm_lut_size size, - const int mpcc_id) + const enum MCM_LUT_XABLE xable, + bool lut_bank_a, + int mpcc_id) { - uint32_t lut_size; struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); switch (id) { case MCM_LUT_3DLUT: - if (enable) { - lut_size = mpc401_cm_lut_size_to_3dlut_size(size); - REG_UPDATE_2(MPCC_MCM_3DLUT_MODE[mpcc_id], - MPCC_MCM_3DLUT_MODE, lut_bank_a ? 1 : 2, - MPCC_MCM_3DLUT_SIZE, lut_size); - } else { - if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) - mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false); + switch (xable) { + case MCM_LUT_DISABLE: REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, 0); + break; + case MCM_LUT_ENABLE: + REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, lut_bank_a ? 1 : 2); + break; } break; case MCM_LUT_SHAPER: - if (enable) { - REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); - } else { - if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) - mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false); + switch (xable) { + case MCM_LUT_DISABLE: REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, 0); + break; + case MCM_LUT_ENABLE: + REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); + break; } break; case MCM_LUT_1DLUT: - if (enable) { - REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], - MPCC_MCM_1DLUT_MODE, 2); - } else { - if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) - mpc32_power_on_blnd_lut(mpc, mpcc_id, false); + switch (xable) { + case MCM_LUT_DISABLE: REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_MODE, 0); + break; + case MCM_LUT_ENABLE: + REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], + MPCC_MCM_1DLUT_MODE, 2); + break; } REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_SELECT, lut_bank_a ? 0 : 1); @@ -257,20 +279,14 @@ void mpc401_program_lut_mode( } } -void mpc401_program_lut_read_write_control(struct mpc *mpc, - const enum MCM_LUT_ID id, - const bool lut_bank_a, - const unsigned int bit_depth, - const int mpcc_id) +void mpc401_program_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id) { struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); switch (id) { case MCM_LUT_3DLUT: mpc32_select_3dlut_ram_mask(mpc, 0xf, mpcc_id); - REG_UPDATE_2(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], - MPCC_MCM_3DLUT_30BIT_EN, (bit_depth == 10) ? 1 : 0, - MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1); + REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1); break; case MCM_LUT_SHAPER: mpc32_configure_shaper_lut(mpc, lut_bank_a, mpcc_id); @@ -562,44 +578,6 @@ void mpc401_get_gamut_remap(struct mpc *mpc, arr_reg_val, ARRAY_SIZE(arr_reg_val)); } -void mpc401_get_lut_mode(struct mpc *mpc, - const enum MCM_LUT_ID id, - const int mpcc_id, - bool *enable, - bool *lut_bank_a) -{ - struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); - - uint32_t lut_mode = 0; - uint32_t lut_select = 0; - - *enable = false; - *lut_bank_a = true; - - switch (id) { - case MCM_LUT_SHAPER: - REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], - MPCC_MCM_SHAPER_MODE_CURRENT, &lut_mode); - *enable = lut_mode != 0; - *lut_bank_a = lut_mode != 2; - break; - case MCM_LUT_1DLUT: - REG_GET_2(MPCC_MCM_1DLUT_CONTROL[mpcc_id], - MPCC_MCM_1DLUT_MODE_CURRENT, &lut_mode, - MPCC_MCM_1DLUT_SELECT_CURRENT, &lut_select); - *enable = lut_mode != 0; - *lut_bank_a = lut_mode == 0 || lut_select == 0; - break; - case MCM_LUT_3DLUT: - default: - REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], - MPCC_MCM_3DLUT_MODE_CURRENT, &lut_mode); - *enable = lut_mode != 0; - *lut_bank_a = lut_mode != 2; - break; - } -} - static const struct mpc_funcs dcn401_mpc_funcs = { .read_mpcc_state = mpc1_read_mpcc_state, .insert_plane = mpc1_insert_plane, @@ -638,7 +616,6 @@ static const struct mpc_funcs dcn401_mpc_funcs = { .populate_lut = mpc401_populate_lut, .program_lut_read_write_control = mpc401_program_lut_read_write_control, .program_lut_mode = mpc401_program_lut_mode, - .get_lut_mode = mpc401_get_lut_mode, }; diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h index c16560c84453..6d842d7b95c7 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h @@ -206,32 +206,21 @@ void dcn401_mpc_construct(struct dcn401_mpc *mpc401, int num_rmu); void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id); -void mpc401_populate_lut(struct mpc *mpc, - const enum MCM_LUT_ID id, - const union mcm_lut_params *params, - bool lut_bank_a, - int mpcc_id); +void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, + bool lut_bank_a, int mpcc_id); void mpc401_program_lut_mode( struct mpc *mpc, const enum MCM_LUT_ID id, - const bool enable, - const bool lut_bank_a, - const enum dc_cm_lut_size size, - const int mpcc_id); - -void mpc401_get_lut_mode(struct mpc *mpc, - const enum MCM_LUT_ID id, - const int mpcc_id, - bool *enable, - bool *lut_bank_a); + const enum MCM_LUT_XABLE xable, + bool lut_bank_a, + int mpcc_id); void mpc401_program_lut_read_write_control( struct mpc *mpc, const enum MCM_LUT_ID id, - const bool lut_bank_a, - const unsigned int bit_depth, - const int mpcc_id); + bool lut_bank_a, + int mpcc_id); void mpc401_set_gamut_remap( struct mpc *mpc, diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c index 507dbdbea600..38c0e8f96d40 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c @@ -63,6 +63,154 @@ void mpc42_update_blending( mpcc->blnd_cfg = *blnd_cfg; } +/* Shaper functions */ +void mpc42_power_on_shaper_3dlut( + struct mpc *mpc, + uint32_t mpcc_id, + bool power_on) +{ + uint32_t power_status_shaper = 2; + uint32_t power_status_3dlut = 2; + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + int max_retries = 10; + + REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, + MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0); + REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, + MPCC_MCM_SHAPER_MEM_PWR_DIS, power_on == true ? 1:0); + /* wait for memory to fully power up */ + if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { + REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries); + REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries); + } + + /*read status is not mandatory, it is just for debugging*/ + REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper); + REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut); + + if (power_status_shaper != 0 && power_on == true) + BREAK_TO_DEBUGGER(); + + if (power_status_3dlut != 0 && power_on == true) + BREAK_TO_DEBUGGER(); +} + +void mpc42_configure_shaper_lut( + struct mpc *mpc, + bool is_ram_a, + uint32_t mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_UPDATE(MPCC_MCM_SHAPER_SCALE_G_B[mpcc_id], + MPCC_MCM_SHAPER_SCALE_B, 0x7000); + REG_UPDATE(MPCC_MCM_SHAPER_SCALE_G_B[mpcc_id], + MPCC_MCM_SHAPER_SCALE_G, 0x7000); + REG_UPDATE(MPCC_MCM_SHAPER_SCALE_R[mpcc_id], + MPCC_MCM_SHAPER_SCALE_R, 0x7000); + REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 7); + REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); + REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0); +} + + +void mpc42_program_3dlut_size(struct mpc *mpc, uint32_t width, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + uint32_t size = 0xff; + + REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &size); + + REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, + (width == 33) ? 2 : + (width == 17) ? 0 : 2); + + REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &size); +} + +void mpc42_program_3dlut_fl_bias_scale(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_UPDATE_2(MPCC_MCM_3DLUT_OUT_OFFSET_R[mpcc_id], + MPCC_MCM_3DLUT_OUT_OFFSET_R, bias, + MPCC_MCM_3DLUT_OUT_SCALE_R, scale); + + REG_UPDATE_2(MPCC_MCM_3DLUT_OUT_OFFSET_G[mpcc_id], + MPCC_MCM_3DLUT_OUT_OFFSET_G, bias, + MPCC_MCM_3DLUT_OUT_SCALE_G, scale); + + REG_UPDATE_2(MPCC_MCM_3DLUT_OUT_OFFSET_B[mpcc_id], + MPCC_MCM_3DLUT_OUT_OFFSET_B, bias, + MPCC_MCM_3DLUT_OUT_SCALE_B, scale); +} + +void mpc42_program_bit_depth(struct mpc *mpc, uint16_t bit_depth, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_WRITE_EN_MASK, 0xF); + + //program bit_depth + REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPCC_MCM_3DLUT_30BIT_EN, + (bit_depth == 10) ? 1 : 0); +} + +bool mpc42_is_config_supported(uint32_t width) +{ + if (width == 17) + return true; + + return false; +} + +void mpc42_populate_lut(struct mpc *mpc, const union mcm_lut_params params, + bool lut_bank_a, int mpcc_id) +{ + const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B; + const struct pwl_params *lut_shaper = params.pwl; + + if (lut_shaper == NULL) + return; + if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) + mpc42_power_on_shaper_3dlut(mpc, mpcc_id, true); + + mpc42_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id); + + if (next_mode == LUT_RAM_A) + mpc32_program_shaper_luta_settings(mpc, lut_shaper, mpcc_id); + else + mpc32_program_shaper_lutb_settings(mpc, lut_shaper, mpcc_id); + + mpc32_program_shaper_lut( + mpc, lut_shaper->rgb_resulted, lut_shaper->hw_points_num, mpcc_id); + + mpc42_power_on_shaper_3dlut(mpc, mpcc_id, false); +} + +void mpc42_program_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, + bool lut_bank_a, bool enabled, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + switch (id) { + case MCM_LUT_3DLUT: + REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, + (!enabled) ? 0 : + (lut_bank_a) ? 1 : 2); + REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1); + break; + case MCM_LUT_SHAPER: + mpc32_configure_shaper_lut(mpc, lut_bank_a, mpcc_id); + break; + default: + break; + } +} + /* RMCM Shaper functions */ void mpc42_power_on_rmcm_shaper_3dlut( struct mpc *mpc, @@ -526,47 +674,32 @@ void mpc42_program_rmcm_lut_read_write_control(struct mpc *mpc, const enum MCM_L } } -void mpc42_program_lut_mode(struct mpc *mpc, - bool enable, - bool lut_bank_a, - int mpcc_id) +void mpc42_program_lut_mode(struct mpc *mpc, const enum MCM_LUT_XABLE xable, + bool lut_bank_a, int mpcc_id) { struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); - if (enable) { - REG_UPDATE(MPC_RMCM_SHAPER_CONTROL[mpcc_id], MPC_RMCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); - } else { + switch (xable) { + case MCM_LUT_DISABLE: REG_UPDATE(MPC_RMCM_SHAPER_CONTROL[mpcc_id], MPC_RMCM_SHAPER_LUT_MODE, 0); + break; + case MCM_LUT_ENABLE: + REG_UPDATE(MPC_RMCM_SHAPER_CONTROL[mpcc_id], MPC_RMCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); + break; } } -static uint32_t mpc42_get_rmcm_3dlut_width( - const enum dc_cm_lut_size size) -{ - uint32_t width = 0; - - switch (size) { - case CM_LUT_SIZE_333333: - width = 2; - break; - case CM_LUT_SIZE_171717: - default: - width = 0; - break; - } - - return width; -} - -void mpc42_program_rmcm_3dlut_size(struct mpc *mpc, - const enum dc_cm_lut_size size, - int mpcc_id) +void mpc42_program_rmcm_3dlut_size(struct mpc *mpc, uint32_t width, int mpcc_id) { struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); - uint32_t width = mpc42_get_rmcm_3dlut_width(size); + uint32_t size = 0xff; - REG_UPDATE(MPC_RMCM_3DLUT_MODE[mpcc_id], - MPC_RMCM_3DLUT_SIZE, width); + REG_GET(MPC_RMCM_3DLUT_MODE[mpcc_id], MPC_RMCM_3DLUT_SIZE, &size); + + REG_UPDATE(MPC_RMCM_3DLUT_MODE[mpcc_id], MPC_RMCM_3DLUT_SIZE, + (width == 33) ? 2 : 0); + + REG_GET(MPC_RMCM_3DLUT_MODE[mpcc_id], MPC_RMCM_3DLUT_SIZE, &size); } void mpc42_program_rmcm_3dlut_fast_load_bias_scale(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id) @@ -598,6 +731,14 @@ void mpc42_program_rmcm_bit_depth(struct mpc *mpc, uint16_t bit_depth, int mpcc_ (bit_depth == 10) ? 1 : 0); } +bool mpc42_is_rmcm_config_supported(uint32_t width) +{ + if (width == 17 || width == 33) + return true; + + return false; +} + void mpc42_set_fl_config( struct mpc *mpc, struct mpc_fl_3dlut_config *cfg, @@ -605,7 +746,6 @@ void mpc42_set_fl_config( { struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); - uint32_t width = mpc42_get_rmcm_3dlut_width(cfg->size); /* From: Jie Zhou @@ -646,7 +786,7 @@ void mpc42_set_fl_config( //width REG_UPDATE_2(MPC_RMCM_3DLUT_MODE[mpcc_id], - MPC_RMCM_3DLUT_SIZE, width, + MPC_RMCM_3DLUT_SIZE, (cfg->width == 33) ? 2 : 0, MPC_RMCM_3DLUT_MODE, (!cfg->enabled) ? 0 : (cfg->select_lut_bank_a) ? 1 : 2); //connect to hubp @@ -659,6 +799,182 @@ void mpc42_set_fl_config( REG_UPDATE(MPC_RMCM_CNTL[mpcc_id], MPC_RMCM_CNTL, cfg->enabled ? 0 : 0xF); } +//static void rmcm_program_gamut_remap( +// struct mpc *mpc, +// unsigned int mpcc_id, +// const uint16_t *regval, +// enum mpcc_gamut_remap_id gamut_remap_block_id, +// enum mpcc_gamut_remap_mode_select mode_select) +//{ +// struct color_matrices_reg gamut_regs; +// struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); +// +// if (gamut_remap_block_id == MPCC_OGAM_GAMUT_REMAP || +// gamut_remap_block_id == MPCC_MCM_FIRST_GAMUT_REMAP || +// gamut_remap_block_id == MPCC_MCM_SECOND_GAMUT_REMAP) { +// mpc_program_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); +// return; +// } +// if (gamut_remap_block_id == MPCC_OGAM_GAMUT_REMAP) { +// +// if (regval == NULL || mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) { +// REG_SET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], 0, +// MPC_RMCM_GAMUT_REMAP_MODE, mode_select); +// return; +// } +// +// gamut_regs.shifts.csc_c11 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C11_A; +// gamut_regs.masks.csc_c11 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C11_A; +// gamut_regs.shifts.csc_c12 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C12_A; +// gamut_regs.masks.csc_c12 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C12_A; +// +// switch (mode_select) { +// case MPCC_GAMUT_REMAP_MODE_SELECT_1: +// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_A[mpcc_id]); +// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_A[mpcc_id]); +// break; +// case MPCC_GAMUT_REMAP_MODE_SELECT_2: +// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_B[mpcc_id]); +// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_B[mpcc_id]); +// break; +// default: +// break; +// } +// +// cm_helper_program_color_matrices( +// mpc->ctx, +// regval, +// &gamut_regs); +// +// //select coefficient set to use, set A (MODE_1) or set B (MODE_2) +// REG_SET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], 0, MPC_RMCM_GAMUT_REMAP_MODE, mode_select); +// } +//} + +//static bool is_mpc_legacy_gamut_id(enum mpcc_gamut_remap_id gamut_remap_block_id) +//{ +// if (gamut_remap_block_id == MPCC_OGAM_GAMUT_REMAP || +// gamut_remap_block_id == MPCC_MCM_FIRST_GAMUT_REMAP || +// gamut_remap_block_id == MPCC_MCM_SECOND_GAMUT_REMAP) { +// return true; +// } +// return false; +//} +//static void program_gamut_remap( +// struct mpc *mpc, +// unsigned int mpcc_id, +// const uint16_t *regval, +// enum mpcc_gamut_remap_id gamut_remap_block_id, +// enum mpcc_gamut_remap_mode_select mode_select) +//{ +// if (is_mpc_legacy_gamut_id(gamut_remap_block_id)) +// mpc_program_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); +// else +// rmcm_program_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); +//} + +//void mpc42_set_gamut_remap( +// struct mpc *mpc, +// int mpcc_id, +// const struct mpc_grph_gamut_adjustment *adjust) +//{ +// struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); +// unsigned int i = 0; +// uint32_t mode_select = 0; +// +// if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) { +// /* Bypass / Disable if type is bypass or hw */ +// program_gamut_remap(mpc, mpcc_id, NULL, +// adjust->mpcc_gamut_remap_block_id, MPCC_GAMUT_REMAP_MODE_SELECT_0); +// } else { +// struct fixed31_32 arr_matrix[12]; +// uint16_t arr_reg_val[12]; +// +// for (i = 0; i < 12; i++) +// arr_matrix[i] = adjust->temperature_matrix[i]; +// +// convert_float_matrix(arr_reg_val, arr_matrix, 12); +// +// if (is_mpc_legacy_gamut_id(adjust->mpcc_gamut_remap_block_id)) +// REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id], +// MPCC_GAMUT_REMAP_MODE_CURRENT, &mode_select); +// else +// REG_GET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], +// MPC_RMCM_GAMUT_REMAP_MODE_CURRENT, &mode_select); +// +// //If current set in use not set A (MODE_1), then use set A, otherwise use set B +// if (mode_select != MPCC_GAMUT_REMAP_MODE_SELECT_1) +// mode_select = MPCC_GAMUT_REMAP_MODE_SELECT_1; +// else +// mode_select = MPCC_GAMUT_REMAP_MODE_SELECT_2; +// +// program_gamut_remap(mpc, mpcc_id, arr_reg_val, +// adjust->mpcc_gamut_remap_block_id, mode_select); +// } +//} + +//static void read_gamut_remap(struct mpc *mpc, +// int mpcc_id, +// uint16_t *regval, +// enum mpcc_gamut_remap_id gamut_remap_block_id, +// uint32_t *mode_select) +//{ +// struct color_matrices_reg gamut_regs = {0}; +// struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); +// +// if (is_mpc_legacy_gamut_id(gamut_remap_block_id)) { +// mpc_read_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); +// } +// if (gamut_remap_block_id == MPCC_RMCM_GAMUT_REMAP) { +// //current coefficient set in use +// REG_GET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], MPC_RMCM_GAMUT_REMAP_MODE, mode_select); +// +// gamut_regs.shifts.csc_c11 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C11_A; +// gamut_regs.masks.csc_c11 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C11_A; +// gamut_regs.shifts.csc_c12 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C12_A; +// gamut_regs.masks.csc_c12 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C12_A; +// +// switch (*mode_select) { +// case MPCC_GAMUT_REMAP_MODE_SELECT_1: +// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_A[mpcc_id]); +// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_A[mpcc_id]); +// break; +// case MPCC_GAMUT_REMAP_MODE_SELECT_2: +// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_B[mpcc_id]); +// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_B[mpcc_id]); +// break; +// default: +// break; +// } +// } +// +// if (*mode_select != MPCC_GAMUT_REMAP_MODE_SELECT_0) { +// cm_helper_read_color_matrices( +// mpc42->base.ctx, +// regval, +// &gamut_regs); +// } +//} + +//void mpc42_get_gamut_remap(struct mpc *mpc, +// int mpcc_id, +// struct mpc_grph_gamut_adjustment *adjust) +//{ +// uint16_t arr_reg_val[12] = {0}; +// uint32_t mode_select; +// +// read_gamut_remap(mpc, mpcc_id, arr_reg_val, adjust->mpcc_gamut_remap_block_id, &mode_select); +// +// if (mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) { +// adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; +// return; +// } +// +// adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; +// convert_hw_matrix(adjust->temperature_matrix, +// arr_reg_val, ARRAY_SIZE(arr_reg_val)); +//} + void mpc42_read_mpcc_state( struct mpc *mpc, int mpcc_inst, @@ -755,7 +1071,14 @@ static const struct mpc_funcs dcn42_mpc_funcs = { .populate_lut = mpc401_populate_lut, .program_lut_read_write_control = mpc401_program_lut_read_write_control, .program_lut_mode = mpc401_program_lut_mode, - .get_lut_mode = mpc401_get_lut_mode, + .mcm = { + .program_lut_read_write_control = mpc42_program_lut_read_write_control, + .program_3dlut_size = mpc42_program_3dlut_size, + .program_bias_scale = mpc42_program_3dlut_fl_bias_scale, + .program_bit_depth = mpc42_program_bit_depth, + .is_config_supported = mpc42_is_config_supported, + .populate_lut = mpc42_populate_lut, + }, .rmcm = { .enable_3dlut_fl = mpc42_enable_3dlut_fl, .update_3dlut_fast_load_select = mpc42_update_3dlut_fast_load_select, @@ -764,6 +1087,7 @@ static const struct mpc_funcs dcn42_mpc_funcs = { .program_3dlut_size = mpc42_program_rmcm_3dlut_size, .program_bias_scale = mpc42_program_rmcm_3dlut_fast_load_bias_scale, .program_bit_depth = mpc42_program_rmcm_bit_depth, + .is_config_supported = mpc42_is_rmcm_config_supported, .power_on_shaper_3dlut = mpc42_power_on_rmcm_shaper_3dlut, .populate_lut = mpc42_populate_rmcm_lut, .fl_3dlut_configure = mpc42_set_fl_config, diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h index a5f7f4f2bb3b..12a12c28e553 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h @@ -884,6 +884,49 @@ void dcn42_mpc_construct(struct dcn42_mpc *mpc401, void mpc42_init_mpcc(struct mpcc *mpcc, int mpcc_inst); +void mpc42_program_shaper_lutb_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id); +void mpc42_program_shaper_luta_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id); +void mpc42_configure_shaper_lut( + struct mpc *mpc, + bool is_ram_a, + uint32_t mpcc_id); +void mpc42_power_on_shaper_3dlut( + struct mpc *mpc, + uint32_t mpcc_id, + bool power_on); +void mpc42_program_3dlut_size( + struct mpc *mpc, + uint32_t width, + int mpcc_id); +void mpc42_program_3dlut_fl_bias_scale( + struct mpc *mpc, + uint16_t bias, + uint16_t scale, + int mpcc_id); +void mpc42_program_bit_depth( + struct mpc *mpc, + uint16_t bit_depth, + int mpcc_id); +void mpc42_populate_lut( + struct mpc *mpc, + const union mcm_lut_params params, + bool lut_bank_a, + int mpcc_id); +void mpc42_program_lut_read_write_control( + struct mpc *mpc, + const enum MCM_LUT_ID id, + bool lut_bank_a, + bool enabled, + int mpcc_id); + +bool mpc42_is_config_supported(uint32_t width); + /* RMCM */ void mpc42_program_rmcm_shaper_lut( struct mpc *mpc, @@ -927,12 +970,12 @@ void mpc42_program_rmcm_lut_read_write_control( int mpcc_id); void mpc42_program_lut_mode( struct mpc *mpc, - bool enable, + const enum MCM_LUT_XABLE xable, bool lut_bank_a, int mpcc_id); void mpc42_program_rmcm_3dlut_size( struct mpc *mpc, - const enum dc_cm_lut_size size, + uint32_t width, int mpcc_id); void mpc42_program_rmcm_3dlut_fast_load_bias_scale( struct mpc *mpc, @@ -944,6 +987,8 @@ void mpc42_program_rmcm_bit_depth( uint16_t bit_depth, int mpcc_id); +bool mpc42_is_rmcm_config_supported(uint32_t width); + void mpc42_set_fl_config( struct mpc *mpc, struct mpc_fl_3dlut_config *cfg, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c index 9e66b9b97c63..e6426ccee2d8 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c @@ -375,7 +375,7 @@ void optc1_set_vtg_params(struct timing_generator *optc, if (REG(OTG_INTERLACE_CONTROL)) { if (patched_crtc_timing.flags.INTERLACE == 1) { v_init = v_init / 2; - if ((optc1->vstartup_start/2)*2 > asic_blank_end) + if ((uint32_t)((optc1->vstartup_start/2)*2) > asic_blank_end) v_fp2 = v_fp2 / 2; } } diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c index 39ce4d4a61a1..c558b1d633f3 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c @@ -305,8 +305,8 @@ static void optc2_align_vblanks( L = div_u64(L, master_h_total); L = div_u64(L, slave_pixel_clock_100Hz); XY = div_u64(L, p); - Y = master_v_active - XY - 1; - X = div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider); + Y = (uint32_t)(master_v_active - XY - 1); + X = (uint32_t)div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider); /* * set master OTG to unlock when V/H diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h index fc7192f01b33..8e7d65317e7c 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h @@ -164,7 +164,6 @@ SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ - SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\ SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\ SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\ SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \ diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c index f5bf5940e748..1d0181534a67 100644 --- a/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c +++ b/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c @@ -380,7 +380,7 @@ void pg_cntl35_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on) uint32_t power_gate = power_on ? 0 : 1; uint32_t pwr_status = power_on ? 0 : 2; uint32_t org_ip_request_cntl; - int i; + unsigned int i; bool block_enabled; bool all_mpcc_disabled = true, all_opp_disabled = true; bool all_optc_disabled = true, all_stream_disabled = true; @@ -460,7 +460,7 @@ static bool pg_cntl35_mem_status(struct pg_cntl *pg_cntl) void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl) { - int i = 0; + unsigned int i = 0; bool block_enabled; pg_cntl->pg_res_enable[PG_HPO] = pg_cntl35_hpo_pg_status(pg_cntl); @@ -494,7 +494,7 @@ void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl) static void pg_cntl35_print_pg_status(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log) { - int i = 0; + unsigned int i = 0; bool block_enabled = false; DC_LOG_DEBUG("%s: %s", debug_func, debug_log); diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c index 96290538a889..4a096fa3fc10 100644 --- a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c +++ b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c @@ -503,7 +503,7 @@ void pg_cntl42_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on) uint32_t power_gate = power_on ? 0 : 1; uint32_t pwr_status = power_on ? 0 : 2; uint32_t org_ip_request_cntl; - int i; + unsigned int i; bool block_enabled; bool all_mpcc_disabled = true, all_opp_disabled = true; bool all_optc_disabled = true, all_stream_disabled = true; @@ -564,7 +564,7 @@ void pg_cntl42_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on) void pg_cntl42_init_pg_status(struct pg_cntl *pg_cntl) { - int i = 0; + unsigned int i = 0; bool block_enabled; pg_cntl->pg_res_enable[PG_HPO] = pg_cntl42_hpo_pg_status(pg_cntl); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c index f83acfe7a15e..8a0b4ef2977d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c @@ -1150,7 +1150,7 @@ static struct pipe_ctx *dce110_acquire_underlay( /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; - pipe_ctx->pipe_idx = underlay_idx; + pipe_ctx->pipe_idx = (uint8_t)underlay_idx; pipe_ctx->stream = stream; @@ -1160,7 +1160,7 @@ static struct pipe_ctx *dce110_acquire_underlay( hws->funcs.enable_display_power_gating( dc, - pipe_ctx->stream_res.tg->inst, + (uint8_t)pipe_ctx->stream_res.tg->inst, dcb, PIPE_GATING_CONTROL_DISABLE); /* diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index 6a25dcfcdf17..d2d56a1c4b8b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -753,7 +753,8 @@ static struct link_encoder *dce60_link_encoder_create( enc_init_data, &link_enc_feature, &link_enc_regs[link_regs_id], - &link_enc_aux_regs[enc_init_data->channel - 1], + enc_init_data->channel == CHANNEL_ID_UNKNOWN ? + NULL : &link_enc_aux_regs[enc_init_data->channel - 1], enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index 33be49b3c1b1..6c00497e9a01 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -760,7 +760,8 @@ static struct link_encoder *dce80_link_encoder_create( enc_init_data, &link_enc_feature, &link_enc_regs[link_regs_id], - &link_enc_aux_regs[enc_init_data->channel - 1], + enc_init_data->channel == CHANNEL_ID_UNKNOWN ? + NULL : &link_enc_aux_regs[enc_init_data->channel - 1], enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c index 0fdebe63d355..943635c4fbb8 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c @@ -1139,7 +1139,7 @@ static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer( idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; - idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; + idle_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[idle_pipe->pipe_idx]->inst; return idle_pipe; } @@ -1735,7 +1735,7 @@ struct resource_pool *dcn10_create_resource_pool( if (!pool) return NULL; - if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn10_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; kfree(pool); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index a99829f23965..4bc7777be60e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -1523,13 +1523,13 @@ bool dcn20_split_stream_for_odm( *next_odm_pipe = *prev_odm_pipe; - next_odm_pipe->pipe_idx = pipe_idx; + next_odm_pipe->pipe_idx = (uint8_t)pipe_idx; next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; - next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; + next_odm_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[next_odm_pipe->pipe_idx]->inst; next_odm_pipe->stream_res.dsc = NULL; if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; @@ -1580,13 +1580,13 @@ void dcn20_split_stream_for_mpc( *secondary_pipe = *primary_pipe; secondary_pipe->bottom_pipe = sec_bot_pipe; - secondary_pipe->pipe_idx = pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)pipe_idx; secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; - secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; + secondary_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[secondary_pipe->pipe_idx]->inst; secondary_pipe->stream_res.dsc = NULL; if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { ASSERT(!secondary_pipe->bottom_pipe); @@ -1736,7 +1736,7 @@ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx; if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; - secondary_pipe->pipe_idx = preferred_pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx; } } if (secondary_pipe == NULL && @@ -1744,7 +1744,7 @@ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx; if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; - secondary_pipe->pipe_idx = preferred_pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx; } } @@ -1762,7 +1762,7 @@ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; - secondary_pipe->pipe_idx = preferred_pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx; break; } } @@ -1783,7 +1783,7 @@ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; - secondary_pipe->pipe_idx = preferred_pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx; break; } } @@ -2216,7 +2216,7 @@ struct pipe_ctx *dcn20_acquire_free_pipe_for_layer( sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx]; sec_dpp_pipe->plane_res.ipp = pool->ipps[sec_dpp_pipe->pipe_idx]; sec_dpp_pipe->plane_res.dpp = pool->dpps[sec_dpp_pipe->pipe_idx]; - sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst; + sec_dpp_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[sec_dpp_pipe->pipe_idx]->inst; return sec_dpp_pipe; } @@ -2622,7 +2622,7 @@ static bool dcn20_resource_construct( ranges.num_reader_wm_sets = 0; if (loaded_bb->num_states == 1) { - ranges.reader_wm_sets[0].wm_inst = i; + ranges.reader_wm_sets[0].wm_inst = (uint8_t)i; ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; @@ -2631,7 +2631,7 @@ static bool dcn20_resource_construct( ranges.num_reader_wm_sets = 1; } else if (loaded_bb->num_states > 1) { for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { - ranges.reader_wm_sets[i].wm_inst = i; + ranges.reader_wm_sets[i].wm_inst = (uint8_t)i; ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; DC_FP_START(); @@ -2829,7 +2829,7 @@ struct resource_pool *dcn20_create_resource_pool( if (!pool) return NULL; - if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn20_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 84f6d9dc443f..9001423da4f8 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -1757,7 +1757,7 @@ struct resource_pool *dcn21_create_resource_pool( if (!pool) return NULL; - if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn21_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index 4a864689c44f..7ba02a453f2e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -1563,13 +1563,13 @@ static bool dcn30_split_stream_for_mpc_or_odm( *sec_pipe = *pri_pipe; - sec_pipe->pipe_idx = pipe_idx; + sec_pipe->pipe_idx = (uint8_t)pipe_idx; sec_pipe->plane_res.mi = pool->mis[pipe_idx]; sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; - sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; + sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst; sec_pipe->stream_res.dsc = NULL; if (odm) { if (pri_pipe->next_odm_pipe) { @@ -1623,7 +1623,7 @@ static struct pipe_ctx *dcn30_find_split_pipe( if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) { pipe = &context->res_ctx.pipe_ctx[old_index]; - pipe->pipe_idx = old_index; + pipe->pipe_idx = (uint8_t)old_index; } if (!pipe) @@ -1632,7 +1632,7 @@ static struct pipe_ctx *dcn30_find_split_pipe( && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) { if (context->res_ctx.pipe_ctx[i].stream == NULL) { pipe = &context->res_ctx.pipe_ctx[i]; - pipe->pipe_idx = i; + pipe->pipe_idx = (uint8_t)i; break; } } @@ -1647,7 +1647,7 @@ static struct pipe_ctx *dcn30_find_split_pipe( for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { if (context->res_ctx.pipe_ctx[i].stream == NULL) { pipe = &context->res_ctx.pipe_ctx[i]; - pipe->pipe_idx = i; + pipe->pipe_idx = (uint8_t)i; break; } } @@ -2379,7 +2379,7 @@ static bool dcn30_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2669,7 +2669,7 @@ struct resource_pool *dcn30_create_resource_pool( if (!pool) return NULL; - if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn30_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index a74b150cbe9c..05e59b6255f7 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -1358,7 +1358,7 @@ static void set_wm_ranges( struct _vcs_dpi_soc_bounding_box_st *loaded_bb) { struct pp_smu_wm_range_sets ranges = {0}; - int i; + unsigned int i; ranges.num_reader_wm_sets = 0; @@ -1372,7 +1372,7 @@ static void set_wm_ranges( ranges.num_reader_wm_sets = 1; } else if (loaded_bb->num_states > 1) { for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { - ranges.reader_wm_sets[i].wm_inst = i; + ranges.reader_wm_sets[i].wm_inst = (uint8_t)i; ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; DC_FP_START(); @@ -1506,7 +1506,7 @@ static bool dcn301_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -1773,7 +1773,7 @@ struct resource_pool *dcn301_create_resource_pool( if (!pool) return NULL; - if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn301_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c index 539c5aa6bffa..652b98aaa196 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c @@ -1300,7 +1300,7 @@ static bool dcn302_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->res_cap->num_mpc_3dlut; dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -1560,7 +1560,7 @@ struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *ini if (!pool) return NULL; - if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn302_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return pool; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c index 529eccb4ed3b..b22e72a61393 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c @@ -1244,7 +1244,7 @@ static bool dcn303_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->res_cap->num_mpc_3dlut; dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -1492,7 +1492,7 @@ struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *ini if (!pool) return NULL; - if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn303_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return pool; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index 39944d90ea98..573d2a680115 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -1987,7 +1987,7 @@ static bool dcn31_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2 dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2279,7 +2279,7 @@ struct resource_pool *dcn31_create_resource_pool( if (!pool) return NULL; - if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn31_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c index 5acc545bbe7f..7585151ffcde 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c @@ -1914,7 +1914,7 @@ static bool dcn314_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2 dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2191,7 +2191,7 @@ struct resource_pool *dcn314_create_resource_pool( if (!pool) return NULL; - if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn314_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 975e14f3f5fa..7f8e3304af31 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -1957,7 +1957,7 @@ static bool dcn315_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2220,7 +2220,7 @@ struct resource_pool *dcn315_create_resource_pool( if (!pool) return NULL; - if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn315_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c index 914d91df174c..a6dd1bb9da64 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c @@ -1833,7 +1833,7 @@ static bool dcn316_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2 dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2086,7 +2086,7 @@ struct resource_pool *dcn316_create_resource_pool( if (!pool) return NULL; - if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn316_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index 82f81b586986..bf34fdf781dc 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -2302,7 +2302,7 @@ static bool dcn32_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2619,7 +2619,7 @@ struct resource_pool *dcn32_create_resource_pool( if (!pool) return NULL; - if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn32_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); @@ -2747,7 +2747,7 @@ static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) && !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; - secondary_pipe->pipe_idx = preferred_pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx; } } @@ -2760,7 +2760,7 @@ static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( if ((res_ctx->pipe_ctx[i].stream == NULL) && !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { secondary_pipe = &res_ctx->pipe_ctx[i]; - secondary_pipe->pipe_idx = i; + secondary_pipe->pipe_idx = (uint8_t)i; break; } } @@ -2794,7 +2794,7 @@ static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( pipe = &old_ctx->pipe_ctx[head_index]; if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; - idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; + idle_pipe->pipe_idx = (uint8_t)pipe->bottom_pipe->pipe_idx; } else { idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe); if (!idle_pipe) @@ -2808,7 +2808,7 @@ static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; - idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; + idle_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[idle_pipe->pipe_idx]->inst; return idle_pipe; } @@ -2859,7 +2859,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe( pool, opp_head_pipe); if (free_pipe_idx >= 0) { free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx]; - free_pipe->pipe_idx = free_pipe_idx; + free_pipe->pipe_idx = (uint8_t)free_pipe_idx; free_pipe->stream = opp_head_pipe->stream; free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg; free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp; @@ -2868,7 +2868,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe( free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx]; free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx]; free_pipe->plane_res.mpcc_inst = - pool->dpps[free_pipe->pipe_idx]->inst; + (uint8_t)pool->dpps[free_pipe->pipe_idx]->inst; } else { ASSERT(opp_head_pipe); free_pipe = NULL; @@ -2890,7 +2890,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head( if (free_pipe_idx >= 0) { free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx]; - free_pipe->pipe_idx = free_pipe_idx; + free_pipe->pipe_idx = (uint8_t)free_pipe_idx; free_pipe->stream = otg_master->stream; free_pipe->stream_res.tg = otg_master->stream_res.tg; free_pipe->stream_res.dsc = NULL; @@ -2900,7 +2900,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head( free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx]; free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx]; free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx]; - free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst; + free_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[free_pipe_idx]->inst; free_pipe->dsc_padding_params = otg_master->dsc_padding_params; if (free_pipe->stream->timing.flags.DSC == 1) { dcn20_acquire_dsc(free_pipe->stream->ctx->dc, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c index 4808c793590f..b2eac83ef02c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c @@ -333,7 +333,7 @@ void dcn32_determine_det_override(struct dc *dc, continue; if (context->stream_status[i].plane_count > 0) - plane_segments = stream_segments / context->stream_status[i].plane_count; + plane_segments = (uint8_t)(stream_segments / context->stream_status[i].plane_count); else plane_segments = stream_segments; for (j = 0; j < dc->res_pool->pipe_count; j++) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c index c8c81870d50e..5f5720a3953a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c @@ -1801,7 +1801,7 @@ static bool dcn321_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2109,7 +2109,7 @@ struct resource_pool *dcn321_create_resource_pool( if (!pool) return NULL; - if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn321_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index 2a1b0b152501..82a5bdf38e8a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -1948,7 +1948,7 @@ static bool dcn35_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2 dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2266,7 +2266,7 @@ struct resource_pool *dcn35_create_resource_pool( if (!pool) return NULL; - if (dcn35_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn35_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index bfd1016aa780..a4922df2f8d6 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -1921,7 +1921,7 @@ static bool dcn351_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2 dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2239,7 +2239,7 @@ struct resource_pool *dcn351_create_resource_pool( if (!pool) return NULL; - if (dcn351_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn351_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c index 07a6675a7329..5cc52914e32b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c @@ -1918,7 +1918,7 @@ static bool dcn36_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2 dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2236,7 +2236,7 @@ struct resource_pool *dcn36_create_resource_pool( if (!pool) return NULL; - if (dcn36_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn36_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index cb93bfbe9e9e..22ce58250db3 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -2002,7 +2002,7 @@ static bool dcn401_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2336,7 +2336,7 @@ struct resource_pool *dcn401_create_resource_pool( if (!pool) return NULL; - if (dcn401_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn401_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c index c0d37f00fed9..c013a6483f5d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -666,7 +666,6 @@ static const struct resource_caps res_cap_dcn42 = { .num_vmid = 16, .num_mpc_3dlut = 2, .num_dsc = 4, - .num_rmcm = 2, }; static const struct dc_plane_cap plane_cap = { @@ -694,9 +693,13 @@ static const struct dc_debug_options debug_defaults_drv = { .force_abm_enable = false, .clock_trace = true, .disable_pplib_clock_request = false, - .disable_dpp_power_gate = true, - .disable_hubp_power_gate = true, - .disable_optc_power_gate = true, + .ignore_pg = false, + .disable_dpp_power_gate = false, + .disable_hubp_power_gate = false, + .disable_optc_power_gate = false, + .disable_dsc_power_gate = false, + .disable_dio_power_gate = true, + .disable_hpo_power_gate = true, .pipe_split_policy = MPC_SPLIT_AVOID, .force_single_disp_pipe_split = false, .disable_dcc = DCC_ENABLE, @@ -758,7 +761,6 @@ static const struct dc_debug_options debug_defaults_drv = { .min_disp_clk_khz = 50000, .static_screen_wait_frames = 2, .disable_z10 = false, - .ignore_pg = true, .disable_stutter_for_wm_program = true, .min_deep_sleep_dcfclk_khz = 8000, .replay_skip_crtc_disabled = true, @@ -1805,8 +1807,6 @@ static struct resource_funcs dcn42_res_pool_funcs = { .get_panel_config_defaults = dcn42_get_panel_config_defaults, .get_preferred_eng_id_dpia = dcn42_get_preferred_eng_id_dpia, .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, - .add_phantom_pipes = dcn32_add_phantom_pipes, - .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, .prepare_mcache_programming = dcn42_prepare_mcache_programming, .build_pipe_pix_clk_params = dcn42_build_pipe_pix_clk_params, .get_power_profile = dcn401_get_power_profile, @@ -1896,27 +1896,7 @@ static bool dcn42_resource_construct( dc->caps.cursor_not_scaled = true; dc->caps.min_horizontal_blanking_period = 80; dc->caps.dmdata_alloc_size = 2048; - dc->caps.mall_size_per_mem_channel = 4; - /* total size = mall per channel * num channels * 1024 * 1024 */ - dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * - dc->ctx->dc_bios->vram_info.num_chans * 1048576; dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; - dc->caps.cache_line_size = 64; - dc->caps.cache_num_ways = 16; - - /* Calculate the available MALL space */ - dc->caps.max_cab_allocation_bytes = - dcn32_calc_num_avail_chans_for_mall(dc, dc->ctx->dc_bios->vram_info.num_chans) * - dc->caps.mall_size_per_mem_channel * 1024 * 1024; - dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; - - dc->caps.subvp_fw_processing_delay_us = 15; - dc->caps.subvp_drr_max_vblank_margin_us = 40; - dc->caps.subvp_prefetch_end_to_mall_start_us = 15; - dc->caps.subvp_swath_height_margin_lines = 16; - dc->caps.subvp_pstate_allow_width_us = 20; - dc->caps.subvp_vertical_int_margin_us = 30; - dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin dc->caps.max_slave_planes = 2; dc->caps.max_slave_yuv_planes = 2; @@ -1969,7 +1949,7 @@ static bool dcn42_resource_construct( dc->caps.color.mpc.gamut_remap = 1; //configurable to be before or after BLND in MPCC - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; dc->caps.color.mpc.num_rmcm_3dluts = 2; dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; @@ -2302,26 +2282,6 @@ static bool dcn42_resource_construct( resource_init_common_dml2_callbacks(dc, &dc->dml2_options); dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch; - dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc; - dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = - pool->base.funcs->calculate_mall_ways_from_bytes; - - dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us; - dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us; - dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; - dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines; - - dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp; - dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch; - - dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size; - dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways; - dc->dml2_options.mall_cfg.max_cab_allocation_bytes = - dc->caps.max_cab_allocation_bytes; - dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE; - dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE; - dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES; - dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH; dc->dml2_options.max_segments_per_hubp = 24; dc->dml2_options.det_segment_size = DCN42_CRB_SEGMENT_SIZE_KB; @@ -2349,7 +2309,7 @@ struct resource_pool *dcn42_create_resource_pool( if (!pool) return NULL; - if (dcn42_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn42_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c index 1b397fa7e05c..89f7ccd7f81f 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c @@ -42,17 +42,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( /* dcfclk */ if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { - dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; + dml_clk_table->dcfclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dcfclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->dcfclk.num_clk_values) { if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dcfclk_mhz && dc_clk_table->entries[i].dcfclk_mhz > dc_bw_params->dc_mode_limit.dcfclk_mhz) { if (i == 0 || dc_clk_table->entries[i-1].dcfclk_mhz < dc_bw_params->dc_mode_limit.dcfclk_mhz) { dml_clk_table->dcfclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dcfclk_mhz * 1000; - dml_clk_table->dcfclk.num_clk_values = i + 1; + dml_clk_table->dcfclk.num_clk_values = (uint8_t)(i + 1); } else { dml_clk_table->dcfclk.clk_values_khz[i] = 0; - dml_clk_table->dcfclk.num_clk_values = i; + dml_clk_table->dcfclk.num_clk_values = (uint8_t)i; } } else { dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000; @@ -65,17 +65,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( /* fclk */ if (dc_clk_table->num_entries_per_clk.num_fclk_levels) { - dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_fclk_levels; + dml_clk_table->fclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_fclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->fclk.num_clk_values) { if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.fclk_mhz && dc_clk_table->entries[i].fclk_mhz > dc_bw_params->dc_mode_limit.fclk_mhz) { if (i == 0 || dc_clk_table->entries[i-1].fclk_mhz < dc_bw_params->dc_mode_limit.fclk_mhz) { dml_clk_table->fclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.fclk_mhz * 1000; - dml_clk_table->fclk.num_clk_values = i + 1; + dml_clk_table->fclk.num_clk_values = (uint8_t)(i + 1); } else { dml_clk_table->fclk.clk_values_khz[i] = 0; - dml_clk_table->fclk.num_clk_values = i; + dml_clk_table->fclk.num_clk_values = (uint8_t)i; } } else { dml_clk_table->fclk.clk_values_khz[i] = dc_clk_table->entries[i].fclk_mhz * 1000; @@ -88,17 +88,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( /* uclk */ if (dc_clk_table->num_entries_per_clk.num_memclk_levels) { - dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; + dml_clk_table->uclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_memclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->uclk.num_clk_values) { if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.memclk_mhz && dc_clk_table->entries[i].memclk_mhz > dc_bw_params->dc_mode_limit.memclk_mhz) { if (i == 0 || dc_clk_table->entries[i-1].memclk_mhz < dc_bw_params->dc_mode_limit.memclk_mhz) { dml_clk_table->uclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.memclk_mhz * 1000; - dml_clk_table->uclk.num_clk_values = i + 1; + dml_clk_table->uclk.num_clk_values = (uint8_t)(i + 1); } else { dml_clk_table->uclk.clk_values_khz[i] = 0; - dml_clk_table->uclk.num_clk_values = i; + dml_clk_table->uclk.num_clk_values = (uint8_t)i; } } else { dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000; @@ -114,17 +114,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( /* dispclk */ if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) { - dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels; + dml_clk_table->dispclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dispclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->dispclk.num_clk_values) { if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dispclk_mhz && dc_clk_table->entries[i].dispclk_mhz > dc_bw_params->dc_mode_limit.dispclk_mhz) { if (i == 0 || dc_clk_table->entries[i-1].dispclk_mhz < dc_bw_params->dc_mode_limit.dispclk_mhz) { dml_clk_table->dispclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dispclk_mhz * 1000; - dml_clk_table->dispclk.num_clk_values = i + 1; + dml_clk_table->dispclk.num_clk_values = (uint8_t)(i + 1); } else { dml_clk_table->dispclk.clk_values_khz[i] = 0; - dml_clk_table->dispclk.num_clk_values = i; + dml_clk_table->dispclk.num_clk_values = (uint8_t)i; } } else { dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000; @@ -137,17 +137,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( /* dppclk */ if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) { - dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels; + dml_clk_table->dppclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dppclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->dppclk.num_clk_values) { if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dppclk_mhz && dc_clk_table->entries[i].dppclk_mhz > dc_bw_params->dc_mode_limit.dppclk_mhz) { if (i == 0 || dc_clk_table->entries[i-1].dppclk_mhz < dc_bw_params->dc_mode_limit.dppclk_mhz) { dml_clk_table->dppclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dppclk_mhz * 1000; - dml_clk_table->dppclk.num_clk_values = i + 1; + dml_clk_table->dppclk.num_clk_values = (uint8_t)(i + 1); } else { dml_clk_table->dppclk.clk_values_khz[i] = 0; - dml_clk_table->dppclk.num_clk_values = i; + dml_clk_table->dppclk.num_clk_values = (uint8_t)i; } } else { dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000; @@ -160,17 +160,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( /* dtbclk */ if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) { - dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels; + dml_clk_table->dtbclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dtbclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->dtbclk.num_clk_values) { if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dtbclk_mhz && dc_clk_table->entries[i].dtbclk_mhz > dc_bw_params->dc_mode_limit.dtbclk_mhz) { if (i == 0 || dc_clk_table->entries[i-1].dtbclk_mhz < dc_bw_params->dc_mode_limit.dtbclk_mhz) { dml_clk_table->dtbclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dtbclk_mhz * 1000; - dml_clk_table->dtbclk.num_clk_values = i + 1; + dml_clk_table->dtbclk.num_clk_values = (uint8_t)(i + 1); } else { dml_clk_table->dtbclk.clk_values_khz[i] = 0; - dml_clk_table->dtbclk.num_clk_values = i; + dml_clk_table->dtbclk.num_clk_values = (uint8_t)i; } } else { dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000; @@ -183,17 +183,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( /* socclk */ if (dc_clk_table->num_entries_per_clk.num_socclk_levels) { - dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels; + dml_clk_table->socclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_socclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->socclk.num_clk_values) { if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.socclk_mhz && dc_clk_table->entries[i].socclk_mhz > dc_bw_params->dc_mode_limit.socclk_mhz) { if (i == 0 || dc_clk_table->entries[i-1].socclk_mhz < dc_bw_params->dc_mode_limit.socclk_mhz) { dml_clk_table->socclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.socclk_mhz * 1000; - dml_clk_table->socclk.num_clk_values = i + 1; + dml_clk_table->socclk.num_clk_values = (uint8_t)(i + 1); } else { dml_clk_table->socclk.clk_values_khz[i] = 0; - dml_clk_table->socclk.num_clk_values = i; + dml_clk_table->socclk.num_clk_values = (uint8_t)i; } } else { dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000; diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c index e723b4d0aff3..e0802359829e 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c @@ -47,18 +47,18 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( * for use with dml we need to fill in using an active value aiming for >= 2x DCFCLK */ if (dc_clk_table->num_entries_per_clk.num_fclk_levels && dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { - dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; - dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; + dml_clk_table->fclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dcfclk_levels; + dml_clk_table->dcfclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dcfclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { - if (i < dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { + if (i < (int)dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { int j, max_fclk = 0; dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000; for (j = 0; j < MAX_NUM_DPM_LVL; j++) { - if (dc_clk_table->entries[j].fclk_mhz * 1000 > max_fclk) + if ((uint32_t)(dc_clk_table->entries[j].fclk_mhz * 1000) > (uint32_t)max_fclk) max_fclk = dc_clk_table->entries[j].fclk_mhz * 1000; dml_clk_table->fclk.clk_values_khz[i] = max_fclk; - if (max_fclk >= 2 * dml_clk_table->dcfclk.clk_values_khz[i]) + if ((uint32_t)max_fclk >= 2 * dml_clk_table->dcfclk.clk_values_khz[i]) break; } } else { @@ -70,7 +70,7 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( /* uclk */ if (dc_clk_table->num_entries_per_clk.num_memclk_levels) { - dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; + dml_clk_table->uclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_memclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->uclk.num_clk_values) { dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000; @@ -84,7 +84,7 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( /* dispclk */ if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) { - dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels; + dml_clk_table->dispclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dispclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->dispclk.num_clk_values) { dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000; @@ -101,7 +101,7 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( /* dppclk */ if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) { - dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels; + dml_clk_table->dppclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dppclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->dppclk.num_clk_values) { dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000; @@ -117,7 +117,7 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( /* dtbclk */ if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) { - dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels; + dml_clk_table->dtbclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dtbclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->dtbclk.num_clk_values) { dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000; @@ -129,7 +129,7 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( /* socclk */ if (dc_clk_table->num_entries_per_clk.num_socclk_levels) { - dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels; + dml_clk_table->socclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_socclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->socclk.num_clk_values) { dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000; diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index fe9431cea3e5..300bbfe3c98d 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -329,7 +329,7 @@ union dmub_addr { /* Flattened structure containing SOC BB parameters stored in the VBIOS * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. - * This also prevents alighment issues when new parameters are added to the SoC BB. + * This also prevents alignment issues when new parameters are added to the SoC BB. * The following parameters should be added since these values can't be obtained elsewhere: * -dml2_soc_power_management_parameters * -dml2_soc_vmin_clock_limits @@ -958,7 +958,7 @@ union dmub_fw_meta { //============================================================================== #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) /** - * dmub_trace_code_t - firmware trace code, 32-bits + * typedef dmub_trace_code_t - firmware trace code, 32-bits */ typedef uint32_t dmub_trace_code_t; @@ -1008,15 +1008,30 @@ union dmub_fw_boot_status { * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. */ enum dmub_fw_boot_status_bit { - DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ - DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ - DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ - DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ - DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ - DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ - DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ - DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ - DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ + /** @DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE: 1 if DAL FW */ + DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), + /** @DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY: 1 if mailbox ready */ + DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), + /** @DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE: 1 if init done */ + DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), + /** @DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED: 1 if driver should call restore */ + DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), + /** + * @DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED: 1 if VBIOS data is + * deferred programmed + */ + DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), + /** @DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED: 1 if FAMS is enabled */ + DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), + /** + * @DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED: 1 if detection needs + * to be triggered by driver + */ + DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), + /** @DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE: 1 if hw power init is completed */ + DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), + /** @DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED: if ONO regions are enabled */ + DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), }; /* Register bit definition for SCRATCH5 */ @@ -1080,18 +1095,22 @@ enum dmub_ips_comand_type { */ enum dmub_cursor_offload_comand_type { /** + * @DMUB_CMD__CURSOR_OFFLOAD_INIT: * Initializes the cursor offload feature. */ DMUB_CMD__CURSOR_OFFLOAD_INIT = 0, /** - * Enables cursor offloading for a stream and updates the timing parameters. + * @DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE: Enables cursor offloading + * for a stream and updates the timing parameters. */ DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE = 1, /** + * @DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE: * Disables cursor offloading for a given stream. */ DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE = 2, /** + * @DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM: * Programs the latest data for a given stream. */ DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM = 3, @@ -1157,7 +1176,7 @@ enum dmub_fw_boot_options_bit { * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... */ -/** +/* * enum dmub_shared_state_feature_id - List of shared state features. */ enum dmub_shared_state_feature_id { @@ -1170,7 +1189,7 @@ enum dmub_shared_state_feature_id { }; /** - * struct dmub_shared_state_ips_fw - Firmware signals for IPS. + * struct dmub_shared_state_ips_fw_signals - Firmware signals for IPS. */ union dmub_shared_state_ips_fw_signals { struct { @@ -1185,7 +1204,7 @@ union dmub_shared_state_ips_fw_signals { }; /** - * struct dmub_shared_state_ips_signals - Firmware signals for IPS. + * struct dmub_shared_state_ips_driver_signals - Firmware signals for IPS. */ union dmub_shared_state_ips_driver_signals { struct { @@ -1247,7 +1266,7 @@ struct dmub_shared_state_ips_driver { }; /* 248-bytes, fixed */ /** - * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. + * struct dmub_shared_state_cursor_offload_stream_v1 - Header metadata for cursor offload. */ struct dmub_shared_state_cursor_offload_stream_v1 { uint32_t last_write_idx; /**< Last write index */ @@ -1263,14 +1282,14 @@ struct dmub_shared_state_cursor_offload_v1 { }; /* 248-bytes, fixed */ /** - * enum dmub_shared_state_feature_common - Generic payload. + * struct dmub_shared_state_feature_common - Generic payload. */ struct dmub_shared_state_feature_common { uint32_t padding[62]; }; /* 248-bytes, fixed */ /** - * enum dmub_shared_state_feature_header - Feature description. + * struct dmub_shared_state_feature_header - Feature description. */ struct dmub_shared_state_feature_header { uint16_t id; /**< Feature ID */ @@ -1546,8 +1565,9 @@ enum dmub_gpint_command { * DESC: Gets IPS residency in microseconds * ARGS: 0 - Return IPS1 residency * 1 - Return IPS2 residency - * 2 - Return IPS1_RCG residency + * 2 - Return IPS0_RCG residency * 3 - Return IPS1_ONO2_ON residency + * 4 - Return IPS1_Z8_RETENTION residency * RETURN: Total residency in microseconds - lower 32 bits */ DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, @@ -1567,17 +1587,18 @@ enum dmub_gpint_command { * DESC: Gets IPS residency * ARGS: 0 - Return IPS1 residency * 1 - Return IPS2 residency - * 2 - Return IPS1_RCG residency + * 2 - Return IPS0_RCG residency * 3 - Return IPS1_ONO2_ON residency + * 4 - Return IPS1_Z8_RETENTION residency * RETURN: Total residency in milli-percent. */ DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, /** - * DESC: Gets IPS1_RCG histogram counts + * DESC: Gets IPS0_RCG histogram counts * ARGS: Bucket index * RETURN: Total count for the bucket */ - DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, + DMUB_GPINT__GET_IPS0_RCG_HISTOGRAM_COUNTER = 128, /** * DESC: Gets IPS1_ONO2_ON histogram counts * ARGS: Bucket index @@ -1588,8 +1609,9 @@ enum dmub_gpint_command { * DESC: Gets IPS entry counter during residency measurement * ARGS: 0 - Return IPS1 entry counts * 1 - Return IPS2 entry counts - * 2 - Return IPS1_RCG entry counts - * 3 - Return IPS2_ONO2_ON entry counts + * 2 - Return IPS0_RCG entry counts + * 3 - Return IPS1_ONO2_ON entry counts + * 4 - Return IPS1_Z8_RETENTION entry counts * RETURN: Entry counter for selected IPS mode */ DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, @@ -1597,8 +1619,9 @@ enum dmub_gpint_command { * DESC: Gets IPS inactive residency in microseconds * ARGS: 0 - Return IPS1_MAX residency * 1 - Return IPS2 residency - * 2 - Return IPS1_RCG residency + * 2 - Return IPS0_RCG residency * 3 - Return IPS1_ONO2_ON residency + * 4 - Return IPS1_Z8_RETENTION residency * RETURN: Total inactive residency in microseconds - lower 32 bits */ DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, @@ -1606,8 +1629,9 @@ enum dmub_gpint_command { * DESC: Gets IPS inactive residency in microseconds * ARGS: 0 - Return IPS1_MAX residency * 1 - Return IPS2 residency - * 2 - Return IPS1_RCG residency + * 2 - Return IPS0_RCG residency * 3 - Return IPS1_ONO2_ON residency + * 4 - Return IPS1_Z8_RETENTION residency * RETURN: Total inactive residency in microseconds - upper 32 bits */ DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, @@ -1615,8 +1639,9 @@ enum dmub_gpint_command { * DESC: Gets IPS residency in microseconds * ARGS: 0 - Return IPS1 residency * 1 - Return IPS2 residency - * 2 - Return IPS1_RCG residency + * 2 - Return IPS0_RCG residency * 3 - Return IPS1_ONO2_ON residency + * 4 - Return IPS1_Z8_RETENTION residency * RETURN: Total residency in microseconds - upper 32 bits */ DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, @@ -1908,30 +1933,36 @@ enum dmub_cmd_type { */ enum dmub_out_cmd_type { /** - * Invalid outbox command, ignored. + * @DMUB_OUT_CMD__NULL: Invalid outbox command, ignored. */ DMUB_OUT_CMD__NULL = 0, /** + * @DMUB_OUT_CMD__DP_AUX_REPLY: * Command type used for DP AUX Reply data notification */ DMUB_OUT_CMD__DP_AUX_REPLY = 1, /** + * @DMUB_OUT_CMD__DP_HPD_NOTIFY: * Command type used for DP HPD event notification */ DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, /** + * @DMUB_OUT_CMD__SET_CONFIG_REPLY: * Command type used for SET_CONFIG Reply notification */ DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, /** + * @DMUB_OUT_CMD__DPIA_NOTIFICATION: * Command type used for USB4 DPIA notification */ DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, /** + * @DMUB_OUT_CMD__HPD_SENSE_NOTIFY: * Command type used for HPD redetect notification */ DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, /** + * @DMUB_OUT_CMD__FUSED_IO: * Command type used for Fused IO notification */ DMUB_OUT_CMD__FUSED_IO = 7, @@ -1990,7 +2021,7 @@ struct dmub_cmd_read_modify_write_sequence { #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 /** - * struct dmub_cmd_read_modify_write_sequence - Read modify write command. + * struct dmub_rb_cmd_read_modify_write - Read modify write command. */ struct dmub_rb_cmd_read_modify_write { struct dmub_cmd_header header; /**< command header */ @@ -2001,7 +2032,7 @@ struct dmub_rb_cmd_read_modify_write { }; /* - * Update a register with specified masks and values sequeunce + * Update a register with specified masks and values sequence * * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword * @@ -2123,19 +2154,19 @@ struct dmub_rb_cmd_PLAT_54186_wa { */ enum dmub_cmd_mall_type { /** - * Allows display refresh from MALL. + * @DMUB_CMD__MALL_ACTION_ALLOW: Allows display refresh from MALL. */ DMUB_CMD__MALL_ACTION_ALLOW = 0, /** - * Disallows display refresh from MALL. + * @DMUB_CMD__MALL_ACTION_DISALLOW: Disallows display refresh from MALL. */ DMUB_CMD__MALL_ACTION_DISALLOW = 1, /** - * Cursor copy for MALL. + * @DMUB_CMD__MALL_ACTION_COPY_CURSOR: Cursor copy for MALL. */ DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, /** - * Controls DF requests. + * @DMUB_CMD__MALL_ACTION_NO_DF_REQ: Controls DF requests. */ DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, }; @@ -2164,25 +2195,28 @@ struct dmub_rb_cmd_mall { */ enum dmub_cmd_cab_type { /** + * @DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION: * No idle optimizations (i.e. no CAB) */ DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, /** - * No DCN requests for memory + * @DMUB_CMD__CAB_NO_DCN_REQ: No DCN requests for memory */ DMUB_CMD__CAB_NO_DCN_REQ = 1, /** + * @DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB: * Fit surfaces in CAB (i.e. CAB enable) */ DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, /** + * @DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB: * Do not fit surfaces in CAB (i.e. no CAB) */ DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, }; /** - * struct dmub_rb_cmd_cab - CAB command data. + * struct dmub_rb_cmd_cab_for_ss - CAB command data. */ struct dmub_rb_cmd_cab_for_ss { struct dmub_cmd_header header; @@ -2190,7 +2224,7 @@ struct dmub_rb_cmd_cab_for_ss { uint8_t debug_bits; /* debug bits */ }; -/** +/* * Enum for indicating which MCLK switch mode per pipe */ enum mclk_switch_mode { @@ -2664,11 +2698,18 @@ struct dmub_fams2_stream_static_state_v1 { * p-state request to allow latency */ enum dmub_fams2_allow_delay_check_mode { - /* No check for request to allow delay */ + /** + * @FAMS2_ALLOW_DELAY_CHECK_NONE: No check for request to allow delay + */ FAMS2_ALLOW_DELAY_CHECK_NONE = 0, - /* Check for request to allow delay */ + /** + * @FAMS2_ALLOW_DELAY_CHECK_FROM_START: Check for request to allow delay + */ FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, - /* Check for prepare to allow delay */ + /** + * @FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE: + * Check for prepare to allow delay + */ FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, }; @@ -2740,27 +2781,28 @@ struct dmub_rb_cmd_ib { */ enum dmub_cmd_idle_opt_type { /** - * DCN hardware restore. + * @DMUB_CMD__IDLE_OPT_DCN_RESTORE: DCN hardware restore. */ DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, /** - * DCN hardware save. + * @DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT: DCN hardware save. */ DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, /** - * DCN hardware notify idle. + * @DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE: DCN hardware notify idle. */ DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, /** + * @DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE: * DCN hardware notify power state. */ DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, /** - * DCN notify to release HW. + * @DMUB_CMD__IDLE_OPT_RELEASE_HW: DCN notify to release HW. */ DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, }; @@ -2789,7 +2831,7 @@ struct dmub_rb_cmd_idle_opt_dcn_notify_idle { struct dmub_dcn_notify_idle_cntl_data cntl_data; }; -/** +/* * enum dmub_idle_opt_dc_power_state - DC power states. */ enum dmub_idle_opt_dc_power_state { @@ -2831,7 +2873,7 @@ struct dmub_clocks { */ enum dmub_cmd_clk_mgr_type { /** - * Notify DMCUB of clock update. + * @DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS: Notify DMCUB of clock update. */ DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, }; @@ -2867,7 +2909,7 @@ struct dmub_cmd_set_pixel_clock_data { }; /** - * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. + * struct dmub_rb_cmd_set_pixel_clock - Set pixel clock command. */ struct dmub_rb_cmd_set_pixel_clock { struct dmub_cmd_header header; /**< header */ @@ -3076,21 +3118,40 @@ struct dmub_rb_cmd_dpphy_init { * 4 AUX request command bits are shifted to high nibble. */ enum dp_aux_request_action { - /** I2C-over-AUX write request */ + /** + * @DP_AUX_REQ_ACTION_I2C_WRITE: I2C-over-AUX write request + */ DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, - /** I2C-over-AUX read request */ + /** + * @DP_AUX_REQ_ACTION_I2C_READ: I2C-over-AUX read request + */ DP_AUX_REQ_ACTION_I2C_READ = 0x10, - /** I2C-over-AUX write status request */ + /** + * @DP_AUX_REQ_ACTION_I2C_STATUS_REQ: I2C-over-AUX write status request + */ DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, - /** I2C-over-AUX write request with MOT=1 */ + /** + * @DP_AUX_REQ_ACTION_I2C_WRITE_MOT: + * I2C-over-AUX write request with MOT=1 + */ DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, - /** I2C-over-AUX read request with MOT=1 */ + /** + * @DP_AUX_REQ_ACTION_I2C_READ_MOT: + * I2C-over-AUX read request with MOT=1 + */ DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, - /** I2C-over-AUX write status request with MOT=1 */ + /** + * @DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT: + * I2C-over-AUX write status request with MOT=1 + */ DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, - /** Native AUX write request */ + /** + * @DP_AUX_REQ_ACTION_DPCD_WRITE: Native AUX write request + */ DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, - /** Native AUX read request */ + /** + * @DP_AUX_REQ_ACTION_DPCD_READ: Native AUX read request + */ DP_AUX_REQ_ACTION_DPCD_READ = 0x90 }; @@ -3098,21 +3159,21 @@ enum dp_aux_request_action { * enum aux_return_code_type - DP AUX process return code listing. */ enum aux_return_code_type { - /** AUX process succeeded */ + /** @AUX_RET_SUCCESS: AUX process succeeded */ AUX_RET_SUCCESS = 0, - /** AUX process failed with unknown reason */ + /** @AUX_RET_ERROR_UNKNOWN: AUX process failed with unknown reason */ AUX_RET_ERROR_UNKNOWN, - /** AUX process completed with invalid reply */ + /** @AUX_RET_ERROR_INVALID_REPLY: AUX process completed with invalid reply */ AUX_RET_ERROR_INVALID_REPLY, - /** AUX process timed out */ + /** @AUX_RET_ERROR_TIMEOUT: AUX process timed out */ AUX_RET_ERROR_TIMEOUT, - /** HPD was low during AUX process */ + /** @AUX_RET_ERROR_HPD_DISCON: HPD was low during AUX process */ AUX_RET_ERROR_HPD_DISCON, - /** Failed to acquire AUX engine */ + /** @AUX_RET_ERROR_ENGINE_ACQUIRE: Failed to acquire AUX engine */ AUX_RET_ERROR_ENGINE_ACQUIRE, - /** AUX request not supported */ + /** @AUX_RET_ERROR_INVALID_OPERATION: AUX request not supported */ AUX_RET_ERROR_INVALID_OPERATION, - /** AUX process not available */ + /** @AUX_RET_ERROR_PROTOCOL_ERROR: AUX process not available */ AUX_RET_ERROR_PROTOCOL_ERROR, }; @@ -3120,9 +3181,9 @@ enum aux_return_code_type { * enum aux_channel_type - DP AUX channel type listing. */ enum aux_channel_type { - /** AUX thru Legacy DP AUX */ + /** @AUX_CHANNEL_LEGACY_DDC: AUX thru Legacy DP AUX */ AUX_CHANNEL_LEGACY_DDC, - /** AUX thru DPIA DP tunneling */ + /** @AUX_CHANNEL_DPIA: AUX thru DPIA DP tunneling */ AUX_CHANNEL_DPIA }; @@ -3383,7 +3444,7 @@ struct dpia_bw_allocation_notify_data { }; /** - * union dpia_notify_data_type - DPIA Notification in Outbox command + * union dpia_notification_data - DPIA Notification in Outbox command */ union dpia_notification_data { /** @@ -3439,7 +3500,7 @@ struct dmub_rb_cmd_query_hpd_state { }; /** - * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. + * struct dmub_rb_cmd_hpd_sense_notify_data - HPD sense notification data. */ struct dmub_rb_cmd_hpd_sense_notify_data { uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ @@ -3483,7 +3544,7 @@ enum dmub_cmd_psr_type { /** * Set PSR level. - * PSR level is a 16-bit value dicated by driver that + * PSR level is a 16-bit value dictated by driver that * will enable/disable different functionality. */ DMUB_CMD__PSR_SET_LEVEL = 4, @@ -3607,7 +3668,7 @@ enum phy_link_rate { */ }; -/** +/* * enum dmub_phy_fsm_state - PHY FSM states. * PHY FSM state to transit to during PSR enable/disable. */ @@ -3640,7 +3701,7 @@ struct dmub_cmd_psr_copy_settings_data { */ union dmub_psr_debug_flags debug; /** - * 16-bit value dicated by driver that will enable/disable different functionality. + * 16-bit value dictated by driver that will enable/disable different functionality. */ uint16_t psr_level; /** @@ -3680,7 +3741,7 @@ struct dmub_cmd_psr_copy_settings_data { */ uint8_t aux_inst; /** - * Determines if SMU optimzations are enabled/disabled. + * Determines if SMU optimizations are enabled/disabled. */ uint8_t smu_optimizations_en; /** @@ -3797,7 +3858,7 @@ struct dmub_rb_cmd_psr_copy_settings { */ struct dmub_cmd_psr_set_level_data { /** - * 16-bit value dicated by driver that will enable/disable different functionality. + * 16-bit value dictated by driver that will enable/disable different functionality. */ uint16_t psr_level; /** @@ -4175,7 +4236,7 @@ struct dmub_rb_cmd_update_cursor_info { */ struct dmub_cmd_psr_set_vtotal_data { /** - * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. + * 16-bit value dictated by driver that indicates the vtotal in PSR active requirement when screen idle.. */ uint16_t psr_vtotal_idle; /** @@ -4189,7 +4250,7 @@ struct dmub_cmd_psr_set_vtotal_data { */ uint8_t panel_inst; /* - * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. + * 16-bit value dictated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. */ uint16_t psr_vtotal_su; /** @@ -4489,7 +4550,7 @@ struct dmub_cmd_replay_copy_settings_data { uint8_t aux_inst; /** * Panel Instance. - * Panel isntance to identify which psr_state to use + * Panel instance to identify which psr_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4512,7 +4573,7 @@ struct dmub_cmd_replay_copy_settings_data { */ uint8_t dpphy_inst; /** - * Determines if SMU optimzations are enabled/disabled. + * Determines if SMU optimizations are enabled/disabled. */ uint8_t smu_optimizations_en; /** @@ -4602,7 +4663,7 @@ struct dmub_rb_cmd_smart_power_oled_enable_data { uint8_t enable; /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4641,7 +4702,7 @@ struct dmub_rb_cmd_replay_enable_data { uint8_t enable; /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4689,7 +4750,7 @@ struct dmub_rb_cmd_replay_enable { struct dmub_cmd_replay_set_power_opt_data { /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4709,7 +4770,7 @@ struct dmub_cmd_replay_set_power_opt_data { struct dmub_cmd_replay_set_timing_sync_data { /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4729,7 +4790,7 @@ struct dmub_cmd_replay_set_timing_sync_data { struct dmub_cmd_replay_set_pseudo_vtotal { /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4745,7 +4806,7 @@ struct dmub_cmd_replay_set_pseudo_vtotal { struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4759,7 +4820,7 @@ struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { struct dmub_cmd_replay_set_general_cmd_data { /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4796,7 +4857,7 @@ struct dmub_rb_cmd_replay_set_power_opt { */ struct dmub_cmd_replay_set_coasting_vtotal_data { /** - * 16-bit value dicated by driver that indicates the coasting vtotal. + * 16-bit value dictated by driver that indicates the coasting vtotal. */ uint16_t coasting_vtotal; /** @@ -4805,12 +4866,12 @@ struct dmub_cmd_replay_set_coasting_vtotal_data { uint8_t cmd_version; /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; /** - * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. + * 16-bit value dictated by driver that indicates the coasting vtotal high byte part. */ uint16_t coasting_vtotal_high; /** @@ -4913,7 +4974,7 @@ struct dmub_rb_cmd_replay_set_general_cmd { struct dmub_cmd_replay_frameupdate_timer_data { /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4946,7 +5007,7 @@ struct dmub_rb_cmd_replay_set_frameupdate_timer { union dmub_replay_cmd_set { /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -5122,7 +5183,7 @@ struct dmub_hw_lock_inst_flags { uint8_t opp_inst; /** * OTG HW instance for global update lock. - * TODO: Remove, and re-use otg_inst. + * TODO: Remove, and reuse otg_inst. */ uint8_t dig_inst; /** @@ -5884,10 +5945,11 @@ struct dmub_rb_cmd_abm_query_caps { */ enum dmub_abm_ace_curve_type { /** - * ACE curve as defined by the SW layer. + * @ABM_ACE_CURVE_TYPE__SW: ACE curve as defined by the SW layer. */ ABM_ACE_CURVE_TYPE__SW = 0, /** + * @ABM_ACE_CURVE_TYPE__SW_IF: * ACE curve as defined by the SW to HW translation interface layer. */ ABM_ACE_CURVE_TYPE__SW_IF = 1, @@ -5898,10 +5960,11 @@ enum dmub_abm_ace_curve_type { */ enum dmub_abm_histogram_type { /** - * ACE curve as defined by the SW layer. + * @ABM_HISTOGRAM_TYPE__SW: ACE curve as defined by the SW layer. */ ABM_HISTOGRAM_TYPE__SW = 0, /** + * @ABM_HISTOGRAM_TYPE__SW_IF: * ACE curve as defined by the SW to HW translation interface layer. */ ABM_HISTOGRAM_TYPE__SW_IF = 1, @@ -6107,14 +6170,17 @@ struct dmub_rb_cmd_get_visual_confirm_color { */ enum dmub_cmd_panel_cntl_type { /** + * @DMUB_CMD__PANEL_CNTL_HW_INIT: * Initializes embedded panel hardware blocks. */ DMUB_CMD__PANEL_CNTL_HW_INIT = 0, /** + * @DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO: * Queries backlight info for the embedded panel. */ DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, /** + * @DMUB_CMD__PANEL_DEBUG_PWM_FREQ: * Sets the PWM Freq as per user's requirement. */ DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, @@ -6318,7 +6384,7 @@ struct dmub_cmd_cable_id_input { }; /** - * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. + * struct dmub_cmd_cable_id_output - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. */ struct dmub_cmd_cable_id_output { uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ @@ -6513,7 +6579,7 @@ struct dmub_rb_cmd_assr_enable { enum ips_residency_mode { IPS_RESIDENCY__IPS1_MAX, IPS_RESIDENCY__IPS2, - IPS_RESIDENCY__IPS1_RCG, + IPS_RESIDENCY__IPS1_RCG, // refers to IPS0 + RCG IPS_RESIDENCY__IPS1_ONO2_ON, IPS_RESIDENCY__IPS1_Z8_RETENTION, IPS_RESIDENCY__PG_ONO_LAST_SEEN_IN_IPS, @@ -6609,7 +6675,7 @@ struct dmub_cmd_pr_enable_data { uint8_t enable; /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -6687,7 +6753,7 @@ struct dmub_cmd_pr_copy_settings_data { uint8_t aux_inst; /** * Panel Instance. - * Panel isntance to identify which psr_state to use + * Panel instance to identify which psr_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -6696,7 +6762,7 @@ struct dmub_cmd_pr_copy_settings_data { */ uint8_t dpphy_inst; /** - * Determines if SMU optimzations are enabled/disabled. + * Determines if SMU optimizations are enabled/disabled. */ uint8_t smu_optimizations_en; /** @@ -6704,7 +6770,7 @@ struct dmub_cmd_pr_copy_settings_data { */ uint32_t line_time_in_ns; /* - * Use FSFT afftet pixel clk + * Use FSFT after pixel clk */ uint32_t pix_clk_100hz; /* @@ -6777,7 +6843,7 @@ union dmub_pr_runtime_flags { struct dmub_cmd_pr_update_state_data { /** * Panel Instance. - * Panel isntance to identify which psr_state to use + * Panel instance to identify which psr_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -6799,7 +6865,7 @@ struct dmub_cmd_pr_update_state_data { struct dmub_cmd_pr_general_cmd_data { /** * Panel Instance. - * Panel isntance to identify which psr_state to use + * Panel instance to identify which psr_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c index e5a78df80d72..3444eb7d7d81 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c @@ -535,7 +535,7 @@ void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, union dmub_rb_cmd *cmd) { uint32_t *dwords = (uint32_t *)cmd; - int32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes; + uint32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes; uint32_t msg_index; static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch"); diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c index a09aa19ad379..e86fcfc74985 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c @@ -429,7 +429,7 @@ void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, union dmub_rb_cmd *cmd) { uint32_t *dwords = (uint32_t *)cmd; - int32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes; + uint32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes; uint32_t msg_index; static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch"); diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h index 38a77fa9b4af..a0f03fb67605 100644 --- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h @@ -153,6 +153,10 @@ struct embedded_panel_info { uint32_t drr_enabled; uint32_t min_drr_refresh_rate; bool realtek_eDPToLVDS; + uint16_t panel_width_mm; + uint16_t panel_height_mm; + uint16_t fake_edid_size; + const uint8_t *fake_edid; }; struct dc_firmware_info { diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c index 1f225d0d6c44..beb97cbdad6e 100644 --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c @@ -364,7 +364,7 @@ void precompute_pq(void) /* one-time pre-compute dePQ values - only for max pixel value 125 FP16 */ void precompute_de_pq(void) { - int i; + uint32_t i; struct fixed31_32 y; uint32_t begin_index, end_index; @@ -783,7 +783,7 @@ static struct fixed31_32 calculate_mapped_value( struct pwl_float_data *rgb, const struct pixel_gamma_point *coeff, enum channel_name channel, - uint32_t max_index) + int32_t max_index) { const struct gamma_point *point; @@ -1425,7 +1425,7 @@ static void apply_lut_1d( uint32_t num_hw_points, struct dc_transfer_func_distributed_points *tf_pts) { - int i = 0; + uint32_t i = 0; int color = 0; struct fixed31_32 *regamma_y; struct fixed31_32 norm_y; @@ -1569,7 +1569,7 @@ static bool calculate_interpolated_hardware_curve( { const struct pixel_gamma_point *coeff = coeff128; - uint32_t max_entries = 3 - 1; + int32_t max_entries = 3 - 1; uint32_t i = 0; @@ -1581,7 +1581,7 @@ static bool calculate_interpolated_hardware_curve( } i = 0; - max_entries += ramp->num_entries; + max_entries += (int32_t)ramp->num_entries; /* TODO: float point case */ @@ -1635,7 +1635,7 @@ static bool map_regamma_hw_to_x_user( { /* setup to spare calculated ideal regamma values */ - int i = 0; + uint32_t i = 0; struct hw_x_point *coords = coords_x; const struct pwl_float_data_ex *regamma = rgb_regamma; diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_power.h b/drivers/gpu/drm/amd/display/modules/inc/mod_power.h new file mode 100644 index 000000000000..89037f7b7961 --- /dev/null +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_power.h @@ -0,0 +1,415 @@ +/* Copyright (c) 2019 Advanced Micro Devices, Inc. All rights reserved. */ + +#ifndef MODULES_INC_MOD_POWER_H_ +#define MODULES_INC_MOD_POWER_H_ + +#include "dm_services.h" + +struct mod_power_init_params { + + bool disable_fractional_pwm; + + /* Use nits based brightness instead of brightness percentage + */ + bool use_nits_based_brightness; + unsigned int panel_min_millinits; + unsigned int panel_max_millinits; + + unsigned int min_backlight_pwm; + unsigned int max_backlight_pwm; + + unsigned int min_abm_backlight; + unsigned int num_backlight_levels; + bool backlight_ramping_override; + unsigned int backlight_ramping_reduction; + unsigned int backlight_ramping_start; + bool def_varibright_enable; + unsigned int def_varibright_level; + unsigned int varibright_level; + unsigned int abm_config_setting; + + bool allow_psr_smu_optimizations; + + bool allow_psr_multi_disp_optimizations; + + bool use_custom_backlight_caps; + unsigned int custom_backlight_caps_config_no; + bool use_linear_backlight_curve; +}; + +struct mod_power { + int dummy; +}; + +/* VariBright settings structure */ +struct varibright_info { + unsigned int level; + bool enable; + bool activate; +}; + +struct mod_power_psr_context { + /* ddc line */ + unsigned int channel; + /* Transmitter id */ + unsigned int transmitter_id; + /* Engine Id is used for Dig Be source select */ + unsigned int engine_id; + /* Controller Id used for Dig Fe source select */ + unsigned int controller_id; + /* Pcie or Uniphy */ + unsigned int phy_type; + /* Physical PHY Id used by SMU interpretation */ + unsigned int smu_phy_id; + /* Vertical total pixels from crtc timing. + * This is used for static screen detection. + * ie. If we want to detect half a frame, + * we use this to determine the hyst lines. + */ + unsigned int crtc_timing_vertical_total; + /* PSR supported from panel capabilities and + * current display configuration + */ + bool psr_supported_display_config; + /* Whether fast link training is supported by the panel */ + bool psr_exit_link_training_required; + /* If RFB setup time is greater than the total VBLANK time, + * it is not possible for the sink to capture the video frame + * in the same frame the SDP is sent. In this case, + * the frame capture indication bit should be set and an extra + * static frame should be transmitted to the sink. + */ + bool psr_frame_capture_indication_req; + /* Set the last possible line SDP may be transmitted without violating + * the RFB setup time or entering the active video frame. + */ + unsigned int sdp_transmit_line_num_deadline; + /* The VSync rate in Hz used to calculate the + * step size for smooth brightness feature + */ + unsigned int vsync_rate_hz; + unsigned int skip_psr_wait_for_pll_lock; + unsigned int number_of_controllers; + /* Unused, for future use. To indicate that first changed frame from + * state3 shouldn't result in psr_inactive, but rather to perform + * an automatic single frame rfb_update. + */ + bool rfb_update_auto_en; + /* Number of frame before entering static screen */ + unsigned int timehyst_frames; + /* Partial frames before entering static screen */ + unsigned int hyst_lines; + /* # of repeated AUX transaction attempts to make before + * indicating failure to the driver + */ + unsigned int aux_repeats; + /* Controls hw blocks to power down during PSR active state */ + unsigned int psr_level; + /* Controls additional delay after remote frame capture before + * continuing powerd own + */ + unsigned int frame_delay; + bool allow_smu_optimizations; + bool allow_multi_disp_optimizations; + unsigned int line_time_in_us; + /* Panel self refresh 2 selective update granularity required */ + bool su_granularity_required; + /* psr2 selective update y granularity capability */ + uint8_t su_y_granularity; + uint8_t rate_control_caps; + bool os_request_force_ffu; +}; + +enum psr_event { + psr_event_invalid = 0x0, + psr_event_vsync = 0x1, + psr_event_full_screen = 0x2, + psr_event_defer_enable = 0x4, + psr_event_hw_programming = 0x8, + psr_event_test_harness_enable_psr = 0x10, + psr_event_test_harness_disable_psr = 0x20, + psr_event_mpo_video_selective_update = 0x40, + psr_event_edp_panel_off_disable_psr = 0x80, + psr_event_dynamic_display_switch = 0x100, + psr_event_big_screen_video = 0x200, + psr_event_dds_defer_stream_enable = 0x800, + psr_event_dynamic_link_rate_control = 0x1000, + psr_event_vrr_transition = 0x2000, + psr_event_pause = 0x4000, + psr_event_immediate_flip = 0x8000, + psr_event_os_request_disable = 0x10000, + psr_event_os_request_force_ffu = 0x20000, + psr_event_os_override_hold = 0x40000, + psr_event_crc_window_active = 0x80000, +}; + +enum replay_event { + replay_event_invalid = 0x0, + replay_event_vsync = 0x1, + replay_event_full_screen = 0x2, + replay_event_mpo_video_selective_update = 0x4, + replay_event_big_screen_video = 0x8, + replay_event_hw_programming = 0x10, + replay_event_edp_panel_off_disable_psr = 0x20, + replay_event_general_ui = 0x40, + replay_event_vrr = 0x80, + replay_event_prepare_vtotal = 0x100, + replay_event_test_harness_enable_replay = 0x200, + replay_event_test_harness_disable_replay = 0x400, + replay_event_test_harness_ultra_sleep = 0x800, + replay_event_immediate_flip = 0x1000, + replay_event_vrr_transition = 0x2000, + replay_event_pause = 0x4000, + replay_event_disable_replay_while_DPMS = 0x8000, + replay_event_test_harness_mode = 0x10000, + replay_event_cursor_updating = 0x20000, + replay_event_sleep_resume = 0x40000, + replay_event_disable_in_AC = 0x80000, + replay_event_disable_replay_while_detect_display = 0x100000, + replay_event_disable_replay_while_switching_mux = 0x400000, + replay_event_infopacket = 0x800000, + replay_event_os_request_disable = 0x1000000, + replay_event_os_request_force_ffu = 0x2000000, + replay_event_os_override_hold = 0x4000000, + replay_event_crc_window_active = 0x8000000, +}; + +enum replay_enable_option { + pr_enable_option_static_screen = 0x1, + pr_enable_option_mpo_video = 0x2, + pr_enable_option_full_screen_video = 0x4, + pr_enable_option_general_ui = 0x8, + pr_enable_option_full_screen = 0x10, + pr_enable_option_static_screen_coasting = 0x10000, + pr_enable_option_mpo_video_coasting = 0x20000, + pr_enable_option_full_screen_video_coasting = 0x40000, + pr_enable_option_full_screen_coasting = 0x100000, +}; + +struct mod_power *mod_power_create(struct dc *dc, + struct mod_power_init_params *init_params, + unsigned int edp_num); + +void mod_power_destroy(struct mod_power *mod_power); + +bool mod_power_hw_init(struct mod_power *mod_power); + +bool mod_power_add_stream(struct mod_power *mod_power, + struct dc_stream_state *stream, struct psr_caps *caps); + +bool mod_power_remove_stream(struct mod_power *mod_power, + const struct dc_stream_state *stream); + +bool mod_power_replace_stream(struct mod_power *mod_power, + const struct dc_stream_state *current_stream, + struct dc_stream_state *new_stream, + struct psr_caps *new_caps); + +bool mod_power_set_backlight_nits(struct mod_power *mod_power, + struct dc_stream_state *streams, + unsigned int backlight_millinit, + unsigned int transition_time_millisec, + bool skip_aux, + bool is_hdr); + +bool mod_power_set_backlight_percent(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millipercent, + unsigned int transition_time_millisec, + bool is_hdr); + +void mod_power_update_backlight(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millipercent); + +void mod_power_update_backlight_nits(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millinit); + +bool mod_power_get_backlight_pwm(struct mod_power *mod_power, + unsigned int *backlight_pwm, + unsigned int inst); + +bool mod_power_get_backlight_nits(struct mod_power *mod_power, + unsigned int *backlight_millinit, + unsigned int inst); + +bool mod_power_get_backlight_percent(struct mod_power *mod_power, + unsigned int *backlight_millipercent, + unsigned int inst); + +bool mod_power_get_hw_target_backlight_pwm_nits( + struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millinit, + unsigned int inst); + +bool mod_power_get_hw_target_backlight_pwm_percent( + struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millipercent, + unsigned int inst); + +bool mod_power_get_hw_target_backlight_pwm( + struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_u16_16); + +bool mod_power_get_hw_backlight_pwm( + struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight); + +bool mod_power_get_hw_backlight_pwm_nits( + struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millinit, + unsigned int inst); + +bool mod_power_get_hw_backlight_aux_nits( + struct mod_power *mod_power, + struct dc_stream_state **streams, int num_streams, + unsigned int *backlight_millinit_avg, + unsigned int *backlight_millinit_peak); + +bool mod_power_get_hw_backlight_pwm_percent( + struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millipercent, + unsigned int inst); + +void mod_power_initialize_backlight_caps + (struct mod_power *mod_power); + +bool mod_power_get_panel_backlight_boundaries + (struct mod_power *mod_power, + unsigned int *out_min_backlight, + unsigned int *out_max_backlight, + unsigned int *out_ac_backlight_percent, + unsigned int *out_dc_backlight_percent, + unsigned int inst); + +bool mod_power_set_smooth_brightness(struct mod_power *mod_power, + bool enable_brightness, + unsigned int inst); + +bool mod_power_notify_mode_change(struct mod_power *mod_power, + const struct dc_stream_state *stream, + bool is_hdr); + +bool mod_power_get_varibright_level(struct mod_power *mod_power, + unsigned int *varibright_level); + +bool mod_power_get_varibright_hw_level(struct mod_power *mod_power, + unsigned int *varibright_level); + +bool mod_power_get_varibright_default_level(struct mod_power *mod_power, + unsigned int *varibright_level); + +bool mod_power_get_varibright_enable(struct mod_power *mod_power, + bool *varibright_enable); + +bool mod_power_varibright_activate(struct mod_power *mod_power, + bool activate, struct dc_stream_update *stream_update); + +bool mod_power_varibright_feature_enable(struct mod_power *mod_power, + bool enable, struct dc_stream_update *stream_update); + + +bool mod_power_varibright_set_level(struct mod_power *mod_power, + unsigned int level, struct dc_stream_update *stream_update); + +bool mod_power_varibright_set_hw_level(struct mod_power *mod_power, + unsigned int level, struct dc_stream_update *stream_update); + +bool mod_power_is_abm_active(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int inst); + + +bool mod_power_set_psr_event(struct mod_power *mod_power, + struct dc_stream_state *stream, bool set_event, + enum psr_event event, bool wait); + +bool mod_power_get_psr_event(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int *active_psr_events); + +bool mod_power_get_psr_state(struct mod_power *mod_power, + const struct dc_stream_state *stream, + enum dc_psr_state *state); + +bool mod_power_get_psr_enabled_status(struct mod_power *mod_power, + const struct dc_stream_state *stream, + bool *psr_enabled); + +bool mod_power_set_replay_event(struct mod_power *mod_power, + struct dc_stream_state *stream, bool set_event, + enum replay_event event, bool wait_for_disable); + +bool mod_power_get_replay_event(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int *active_replay_events); + +bool mod_power_get_replay_active_status(const struct dc_stream_state *stream, + bool *replay_active); + +bool mod_power_replay_set_coasting_vtotal(struct mod_power *mod_power, + const struct dc_stream_state *stream, + uint32_t coasting_vtotal, uint16_t frame_skip_number); + +void mod_power_replay_residency(const struct dc_stream_state *stream, + unsigned int *residency, const bool is_start, const bool is_alpm); + +bool mod_power_replay_set_power_opt_and_coasting_vtotal(struct mod_power *mod_power, + const struct dc_stream_state *stream, unsigned int active_replay_events, uint32_t coasting_vtotal, + bool is_ultra_sleep_mode, uint16_t frame_skip_number); + +void mod_power_replay_set_timing_sync_supported(struct mod_power *mod_power, + const struct dc_stream_state *stream); + +void mod_power_replay_disabled_adaptive_sync_sdp(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool force_disabled); + +void mod_power_replay_disabled_desync_error_detection(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool force_disabled); +void mod_power_set_low_rr_activate(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool low_rr_supported); + +void mod_power_set_video_conferencing_activate(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool video_conferencing_activate); + +void mod_power_set_live_capture_with_cvt_activate(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool live_capture_with_cvt_activate); + +void mod_power_set_replay_continuously_resync(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool enable); + +void mod_power_set_coasting_vtotal_without_frame_update(struct mod_power *mod_power, + const struct dc_stream_state *stream, uint32_t coasting_vtotal); + + + +void mod_power_psr_residency(struct mod_power *mod_power, + const struct dc_stream_state *stream, + unsigned int *residency, + const uint8_t mode); +bool mod_power_psr_get_active_psr_events(struct mod_power *mod_power, + const struct dc_stream_state *stream, unsigned int *active_psr_events); +bool mod_power_psr_set_sink_vtotal_in_psr_active(struct mod_power *mod_power, + const struct dc_stream_state *stream, + uint16_t psr_vtotal_idle, + uint16_t psr_vtotal_su); + + + +bool mod_power_backlight_percent_to_nits(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millipercent, + unsigned int *backlight_millinit); +bool mod_power_backlight_nits_to_percent(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millinit, + unsigned int *backlight_millipercent); + +#endif /* MODULES_INC_MOD_POWER_H_ */ diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c index 00473c6284d5..55c7250f18d8 100644 --- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c +++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c @@ -246,7 +246,7 @@ void set_vsc_packet_colorimetry_data( break; } - info_packet->sb[16] = (pixelEncoding << 4) | colorimetryFormat; + info_packet->sb[16] = (uint8_t)((pixelEncoding << 4) | colorimetryFormat); /* Set color depth */ switch (stream->timing.display_color_depth) { diff --git a/drivers/gpu/drm/amd/display/modules/power/Makefile b/drivers/gpu/drm/amd/display/modules/power/Makefile index 9d1b22d35ece..b27a1ff3d86b 100644 --- a/drivers/gpu/drm/amd/display/modules/power/Makefile +++ b/drivers/gpu/drm/amd/display/modules/power/Makefile @@ -23,7 +23,7 @@ # Makefile for the 'power' sub-module of DAL. # -MOD_POWER = power_helpers.o +MOD_POWER = power_helpers.o power.o AMD_DAL_MOD_POWER = $(addprefix $(AMDDALPATH)/modules/power/,$(MOD_POWER)) #$(info ************ DAL POWER MODULE MAKEFILE ************) diff --git a/drivers/gpu/drm/amd/display/modules/power/power.c b/drivers/gpu/drm/amd/display/modules/power/power.c new file mode 100644 index 000000000000..1ee671119ddd --- /dev/null +++ b/drivers/gpu/drm/amd/display/modules/power/power.c @@ -0,0 +1,3024 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "dc.h" +#include "mod_power.h" +#include "core_types.h" +#include "dmcu.h" +#include "abm.h" +#include "power_helpers.h" +#include "dce/dmub_psr.h" +#include "dal_asic_id.h" +#include "link_service.h" +#include + +#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ +#define DC_TRACE_LEVEL_MESSAGEP(...) /* do nothing */ + +#define MOD_POWER_MAX_CONCURRENT_STREAMS 32 +#define SMOOTH_BRIGHTNESS_ADJUSTMENT_TIME_IN_MS 500 +#define LOW_REFRESH_RATE_DURATION_US_UPPER_BOUND 25000 + + +struct backlight_state { + /* HW uses u16.16 format for backlight PWM */ + unsigned int backlight_pwm; + /* DM may call power module to set backlight + * targeting percent brightness + */ + unsigned int backlight_millipercent; + /* DM may call power module to set backlight based on an explicit + * nits value. + */ + unsigned int backlight_millinit; + unsigned int frame_ramp; + bool smooth_brightness_enabled; + bool isHDR; +}; +struct power_entity { + struct dc_stream_state *stream; + struct psr_caps *caps; + struct mod_power_psr_context *psr_context; + + /*PSR cached properties*/ + bool psr_enabled; + unsigned int psr_events; + unsigned int psr_power_opt; + unsigned int replay_events; +}; + +struct pwr_backlight_properties { + bool use_nits_based_brightness; + bool disable_fractional_pwm; + + unsigned int min_abm_backlight; + unsigned int num_backlight_levels; + + bool backlight_ramping_override; + unsigned int backlight_ramping_reduction; + unsigned int backlight_ramping_start; + + /* Backlight cached properties */ + unsigned int ac_backlight_percent; + unsigned int dc_backlight_percent; + + /* backlight LUT stored in HW u16.16 format*/ + unsigned int *backlight_lut; + unsigned int min_backlight_pwm; + unsigned int max_backlight_pwm; + unsigned int backlight_range; + + /* Describes the panel's min and max luminance in millinits measured + * on full white screen, in min and max backlight settings. + */ + unsigned int min_brightness_millinits; + unsigned int max_brightness_millinits; + unsigned int nits_range; + + bool backlight_caps_valid; + bool use_custom_backlight_caps; + unsigned int custom_backlight_caps_config_no; + bool use_linear_backlight_curve; +}; + +struct dmcu_varibright_cached_properties { + unsigned int varibright_config_setting; + unsigned int varibright_level; + unsigned int varibright_hw_level; + unsigned int def_varibright_level; + bool varibright_user_enable; + bool varibright_active; +}; + +struct core_power { + struct mod_power public; + struct dc *dc; + struct power_entity *map; + struct dmcu_varibright_cached_properties varibright_prop; + struct pwr_backlight_properties bl_prop[MAX_NUM_EDP]; + struct backlight_state bl_state[MAX_NUM_EDP]; + unsigned int edp_num; + + bool psr_smu_optimizations_support; + bool multi_disp_optimizations_support; + + unsigned int num_entities; +}; + +union dmcu_abm_set_bl_params { + struct { + unsigned int gradual_change : 1; /* [0:0] */ + unsigned int reserved : 15; /* [15:1] */ + unsigned int frame_ramp : 16; /* [31:16] */ + } bits; + unsigned int u32All; +}; + +/* If system or panel does not report some sort of brightness percent to nits + * mapping, we will use following default values so backlight control using + * nits based interfaces will still work, but might not describe panel + * correctly. In this case percentage based backlight control should ideally + * be used. + * Min = 5 nits + * Max = 300 nits + */ + +static const unsigned int pwr_default_min_brightness_millinits = 1000; +static const unsigned int pwr_default_sdr_brightness_millinits = 270000; + +static const unsigned int default_ac_backlight_percent = 100; +static const unsigned int default_dc_backlight_percent = 70; + +#define MOD_POWER_TO_CORE(mod_power)\ + container_of(mod_power, struct core_power, public) + +static unsigned int calc_psr_num_static_frames(unsigned int vsync_rate_hz) +{ + /* Initialize fail-safe to 2 static frames. */ + unsigned int num_frames_static = 2; + + /* Calculate number of frames such that at least 30 ms has passed. + * Round up to ensure the static period is not shorter than 30 ms. + */ + if (vsync_rate_hz != 0) + num_frames_static = DIV_ROUND_UP(30000 * vsync_rate_hz, 1000000); + + return num_frames_static; +} + +/* Given a specific dc_stream* this function finds its equivalent + * on the core_freesync->map and returns the corresponding index + */ +static unsigned int map_index_from_stream(struct core_power *core_power, + const struct dc_stream_state *stream) +{ + unsigned int index = 0; + + for (index = 0; index < core_power->num_entities; index++) { + if (core_power->map[index].stream == stream) + return index; + } + /* Could not find stream requested, this is not trivial, fix when hit*/ + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "map index from stream: ERROR: core_power=%p stream=%p", + core_power, + stream); + ASSERT(false); + /* We come here only when we can't map stream index. + * In good cases, this would happen when we attempt to change + * brightness before stream creation, in which case we create a + * dummy stream with index 0. + * With external monitor connected, the index passed from this return + * is 1. Passing anything greater than 0 from here would always point + * to bad memory. + */ + return 0; +} + +static uint16_t backlight_8_to_16(unsigned int backlight_8bit) +{ + return (uint16_t)(backlight_8bit * 0x101); +} + + +static unsigned int backlight_millipercent_to_millinit( + struct core_power *core_power, unsigned int millipercent, unsigned int inst) +{ + unsigned int millinit = 0; + unsigned long long numerator = 0; + + if (core_power == NULL) + return 0; + + numerator = ((unsigned long long)millipercent) * + core_power->bl_prop[inst].nits_range; + millinit = ((unsigned int)div_u64(numerator, 100000)) + + core_power->bl_prop[inst].min_brightness_millinits; + + return millinit; +} + +static unsigned int backlight_millinit_to_millipercent( + struct core_power *core_power, unsigned int millinit, unsigned int inst) +{ + unsigned int millipercent = 0; + unsigned long long numerator = 0; + + if (core_power == NULL) + return 0; + + if (millinit <= core_power->bl_prop[inst].min_brightness_millinits) + return 0; + + if (millinit >= core_power->bl_prop[inst].max_brightness_millinits) + return (100 * 1000); + + numerator = (((unsigned long long)millinit) - + core_power->bl_prop[inst].min_brightness_millinits) * 100000; + millipercent = ((unsigned int)div_u64(numerator, + core_power->bl_prop[inst].nits_range)); + + return millipercent; +} + +static unsigned int backlight_pwm_to_millipercent( + struct core_power *core_power, unsigned int pwm, unsigned int inst) +{ + unsigned int millipercent = 0; + unsigned int max_index = 0; + + if (core_power == NULL) + return 0; + + if (!core_power->bl_prop[inst].backlight_caps_valid) + return 0; + + /* Doesn't really make sense to have one single backlight level + * possible... + */ + if (core_power->bl_prop[inst].num_backlight_levels < 2) + return 0; + + max_index = core_power->bl_prop[inst].num_backlight_levels - 1; + + if (pwm <= core_power->bl_prop[inst].backlight_lut[0]) + return 0; + + if (pwm > core_power->bl_prop[inst].backlight_lut[max_index]) + return (100 * 1000); + + /* We need to do a binary search over the array for where the pwm level + * is in the lut. Based on the index we can determine percentage. + */ + unsigned int min = 0; + unsigned int max = max_index; + unsigned int mid = 0; + + while (max >= min) { + mid = (min + max) / 2; /* floor of half range */ + + if (core_power->bl_prop[inst].backlight_lut[mid] < pwm) + min = mid + 1; + else if (core_power->bl_prop[inst].backlight_lut[mid] > pwm) + max = mid - 1; + else + break; + } + + /* In this case, exact match is not found. Check if mid/min/max + * value is actually closer. + */ + if (max < min) { + unsigned int min_delta; + unsigned int mid_delta; + unsigned int max_delta; + + min_delta = (core_power->bl_prop[inst].backlight_lut[min] > pwm) ? + core_power->bl_prop[inst].backlight_lut[min] - pwm : + pwm - core_power->bl_prop[inst].backlight_lut[min]; + + mid_delta = (core_power->bl_prop[inst].backlight_lut[mid] > pwm) ? + core_power->bl_prop[inst].backlight_lut[mid] - pwm : + pwm - core_power->bl_prop[inst].backlight_lut[mid]; + + max_delta = (core_power->bl_prop[inst].backlight_lut[max] > pwm) ? + core_power->bl_prop[inst].backlight_lut[max] - pwm : + pwm - core_power->bl_prop[inst].backlight_lut[max]; + + if ((min_delta < mid_delta) && (min_delta < max_delta)) + mid = min; + + if ((max_delta < mid_delta) && (max_delta < min_delta)) + mid = max; + } + + /* No interpolation, just take closest index */ + millipercent = 1000 * 100 * mid / max_index; + + return millipercent; +} + +static unsigned int backlight_pwm_to_millinit( + struct core_power *core_power, unsigned int pwm, unsigned int inst) +{ + unsigned int millinit = 0; + + if (core_power == NULL) + return 0; + + if (pwm <= core_power->bl_prop[inst].min_backlight_pwm) + return core_power->bl_prop[inst].min_brightness_millinits; + + if (pwm >= core_power->bl_prop[inst].max_backlight_pwm) + return core_power->bl_prop[inst].max_brightness_millinits; + + millinit = ((unsigned int)div_u64(((unsigned long long)pwm - + core_power->bl_prop[inst].min_backlight_pwm) * + core_power->bl_prop[inst].nits_range, + core_power->bl_prop[inst].backlight_range)); + + millinit += core_power->bl_prop[inst].min_brightness_millinits; + + if (millinit > core_power->bl_prop[inst].max_brightness_millinits) + millinit = core_power->bl_prop[inst].max_brightness_millinits; + + return millinit; +} + +static unsigned int backlight_millipercent_to_pwm( + struct core_power *core_power, unsigned int millipercent, unsigned int inst) +{ + unsigned int pwm = (unsigned int)-1; + unsigned int index = 0; + + if (core_power == NULL) + return 0; + + // Bypass the brightness mapping LUT + if (core_power->bl_prop->use_linear_backlight_curve) { + pwm = core_power->bl_prop[inst].min_backlight_pwm + + (unsigned int) div_u64((unsigned long long) millipercent * + core_power->bl_prop[inst].backlight_range, + 100000); + + if (pwm > core_power->bl_prop[inst].max_backlight_pwm) + pwm = core_power->bl_prop[inst].max_backlight_pwm; + + return pwm; + } + + if (millipercent >= (100 * 1000)) + return core_power->bl_prop[inst].backlight_lut[core_power->bl_prop[inst].num_backlight_levels - 1]; + + /* This will give the floor index. */ + index = ((core_power->bl_prop[inst].num_backlight_levels - 1) * + millipercent) / 100000; + /* Null check otherwise eDP doesn't lightup when connected to DP1 */ + if (core_power->bl_prop[inst].backlight_lut == NULL) + return pwm; + + pwm = core_power->bl_prop[inst].backlight_lut[index]; + + return pwm; +} + +static unsigned int backlight_millinit_to_pwm( + struct core_power *core_power, unsigned int millinit, unsigned int inst) +{ + unsigned int pwm = 0; + + if (core_power == NULL) + return 0; + + /* For nits based brightness, the signal will be a value + * between the minimum and maximum value. + */ + if (millinit >= core_power->bl_prop[inst].max_brightness_millinits) + return core_power->bl_prop[inst].max_backlight_pwm; + else if (millinit <= core_power->bl_prop[inst].min_brightness_millinits) + return core_power->bl_prop[inst].min_backlight_pwm; + + pwm = ((unsigned int)div_u64(((unsigned long long)millinit - + core_power->bl_prop[inst].min_brightness_millinits) * + core_power->bl_prop[inst].backlight_range, + core_power->bl_prop[inst].nits_range)); + + pwm += core_power->bl_prop[inst].min_backlight_pwm; + + if (pwm > core_power->bl_prop[inst].max_backlight_pwm) + pwm = core_power->bl_prop[inst].max_backlight_pwm; + + return pwm; +} + +static bool validate_ext_backlight_caps( + struct dm_acpi_atif_backlight_caps *ext_backlight_caps) +{ + unsigned int i; + unsigned int num_of_data_points = 0; + unsigned int last_signal_level = 0; + unsigned int last_luminance = 0; + + num_of_data_points = ext_backlight_caps->num_data_points; + + /* Validation rules: + * 1. BIOS should carry customized data points and + * the number of data points should not be larger than 99. + * 2. The max_input_signal should be larger than min_input_signal. + * 3. For each data point: + * a. luminance should be in ascending order and + * should not be 0 or 100 since the corresponding signal_level + * are assigned by min_input_signal and max_input_signal. + * b. signal_level should be in ascending order and + * be within the range of min/max_input_signal. + */ + if (num_of_data_points > BL_DATA_POINTS) + return false; + + if (ext_backlight_caps->min_input_signal >= ext_backlight_caps->max_input_signal) + return false; + + last_signal_level = ext_backlight_caps->min_input_signal; + for (i = 0; i < num_of_data_points; i++) { + unsigned int luminance = ext_backlight_caps->data_points[i].luminance; + unsigned int signal_level = ext_backlight_caps->data_points[i].signal_level; + + if ((luminance <= last_luminance) || (luminance > BL_DATA_POINTS)) + return false; + + if ((signal_level <= last_signal_level) || (signal_level >= ext_backlight_caps->max_input_signal)) + return false; + + last_signal_level = signal_level; + last_luminance = luminance; + } + + return true; +} + +/* hard coded to default backlight curve. */ +static void initialize_backlight_caps(struct core_power *core_power, unsigned int inst) +{ + unsigned int i; + struct dm_acpi_atif_backlight_caps *ext_backlight_caps = NULL; + bool custom_curve_present = false; + unsigned int num_levels = 0; + struct dc *dc = NULL; + enum dm_acpi_display_type acpi_display_type = + (inst == 0) ? AcpiDisplayType_LCD1 : AcpiDisplayType_LCD2; + + if (core_power == NULL) + return; + dc = core_power->dc; + + num_levels = core_power->bl_prop[inst].num_backlight_levels; + + /* Allocate memory for ATIF output + * (do not want to use 256 bytes on the stack) + */ + ext_backlight_caps = (struct dm_acpi_atif_backlight_caps *) + (kzalloc(sizeof(struct dm_acpi_atif_backlight_caps), + GFP_KERNEL)); + + if (ext_backlight_caps == NULL) + return; + + /* Retrieve ACPI extended brightness caps */ + if (dm_query_extended_brightness_caps + (dc->ctx, acpi_display_type, ext_backlight_caps)) { + custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps); + } + + if (core_power->bl_prop[inst].use_custom_backlight_caps && + fill_custom_backlight_caps( + core_power->bl_prop[inst].custom_backlight_caps_config_no, + ext_backlight_caps)) { + custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps); + } + + if (custom_curve_present) { + unsigned int index = 1; + unsigned int num_of_data_points = ext_backlight_caps->num_data_points; + + core_power->bl_prop[inst].ac_backlight_percent = + ext_backlight_caps->ac_level_percentage; + core_power->bl_prop[inst].dc_backlight_percent = + ext_backlight_caps->dc_level_percentage; + core_power->bl_prop[inst].backlight_lut[0] = + backlight_8_to_16( + ext_backlight_caps->min_input_signal); + core_power->bl_prop[inst].backlight_lut[num_levels - 1] = + backlight_8_to_16( + ext_backlight_caps->max_input_signal); + + /* Filling translation table from data points - + * between every two provided data points we + * lineary interpolate missing values + */ + for (i = 0; i < num_of_data_points; i++) { + unsigned int luminance = + ext_backlight_caps->data_points[i].luminance; + unsigned int signal_level = + backlight_8_to_16( + ext_backlight_caps->data_points[i].signal_level); + + /* Since luminance is a percentage, scale it by num_levels*/ + luminance = (luminance * num_levels) / 101; + + /* Lineary interpolate missing values */ + if (index < luminance) { + unsigned int base_value = + core_power->bl_prop[inst].backlight_lut[index-1]; + unsigned int delta_signal = + signal_level - base_value; + unsigned int delta_luma = + luminance - index + 1; + unsigned int step = delta_signal; + + for (; index < luminance; index++) { + core_power->bl_prop[inst].backlight_lut[index] = + base_value + (step / delta_luma); + step += delta_signal; + } + } + + /* Now [index == luminance], + * so we can add data point to the translation table + */ + core_power->bl_prop[inst].backlight_lut[index++] = signal_level; + } + + /* Complete the final segment of interpolation - + * between last datapoint and maximum value + */ + if (index < num_levels - 1) { + unsigned int base_value = + core_power->bl_prop[inst].backlight_lut[index-1]; + unsigned int delta_signal = + core_power->bl_prop[inst].backlight_lut[num_levels - 1] - + base_value; + unsigned int delta_luma = num_levels - index; + unsigned int step = delta_signal; + + for (; index < num_levels - 1; index++) { + core_power->bl_prop[inst].backlight_lut[index] = + base_value + (step / delta_luma); + step += delta_signal; + } + } + /* Build backlight translation table based on default curve */ + } else { + /* Defines default backlight curve F(x) = A(x*x) + Bx + C. + * + * Backlight curve should always satisfy: + * F(0) = min, F(100) = max, + * So polynom coefficients are: + * A is 0.0255 - B/100 - min/10000 - (255-max)/10000 = + * (max - min)/10000 - B/100 + * B is adjustable factor to modify the curve. + * Bigger B results in less concave curve. + * B range is [0..(max-min)/100] + * C is backlight minimum + */ + unsigned int backlight_curve_coeff_a_factor = + num_levels * num_levels; + unsigned int backlight_curve_coeff_b = num_levels; + unsigned int delta = + core_power->bl_prop[inst].backlight_lut[num_levels - 1] - + core_power->bl_prop[inst].backlight_lut[0]; + unsigned int coeffC = core_power->bl_prop[inst].backlight_lut[0]; + unsigned int coeffB = + (backlight_curve_coeff_b < delta ? + backlight_curve_coeff_b : delta); + unsigned long long coeffA = delta - coeffB; /* coeffB is B*100 */ + + for (i = 1; i < num_levels - 1; i++) { + uint64_t lut_val = div_u64(coeffA * i * i, backlight_curve_coeff_a_factor) + + div_u64((uint64_t)coeffB * i, backlight_curve_coeff_b) + coeffC; + + ASSERT(lut_val <= 0xFFFFFFFF); + core_power->bl_prop[inst].backlight_lut[i] = (unsigned int)lut_val; + } + } + + if (ext_backlight_caps != NULL) + kfree(ext_backlight_caps); + + /* Successfully initialized */ + core_power->bl_prop[inst].backlight_caps_valid = true; +} + +static void varibright_set_level(struct core_power *core_power) +{ + if (!core_power->varibright_prop.varibright_active || + !core_power->varibright_prop.varibright_user_enable) + core_power->varibright_prop.varibright_hw_level = 0; + else + core_power->varibright_prop.varibright_hw_level = + core_power->varibright_prop.varibright_level; +} + +bool mod_power_hw_init(struct mod_power *mod_power) +{ + struct core_power *core_power = NULL; + struct dc *dc = NULL; + struct dmcu *dmcu = NULL; + struct dmcu_iram_parameters params; + unsigned int i; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + dc = core_power->dc; + + for (i = 0; i < core_power->edp_num; i++) { + params.set = core_power->varibright_prop.varibright_config_setting; + params.backlight_ramping_override = core_power->bl_prop[i].backlight_ramping_override; + params.backlight_ramping_reduction = core_power->bl_prop[i].backlight_ramping_reduction; + params.backlight_ramping_start = core_power->bl_prop[i].backlight_ramping_start; + params.backlight_lut_array = core_power->bl_prop[i].backlight_lut; + params.backlight_lut_array_size = core_power->bl_prop[i].num_backlight_levels; + params.min_abm_backlight = core_power->bl_prop[i].min_abm_backlight; + + dmcu = dc->res_pool->dmcu; + + // In the case where abm is implemented on dmcub, + // dmcu object will be null. + // ABM 2.4 and up are implemented on dmcub. + if (dmcu) { + //DMCU does not support multiple eDP + return dmcu_load_iram(dmcu, params); + } else if (dc->ctx->dmub_srv) { + if (!dmub_init_abm_config(dc->res_pool, params, i)) + return false; + } else + return false; + } + return true; +} + +struct mod_power *mod_power_create(struct dc *dc, + struct mod_power_init_params *init_params, + unsigned int edp_num) +{ + struct core_power *core_power = NULL; + int i = 0; + unsigned int abm_max_config = 0; + unsigned int inst = 0; + bool is_brightness_range_valid = false; + + if (dc == NULL) + goto fail_dc_null; + + core_power = kzalloc(sizeof(struct core_power), GFP_KERNEL); + + if (core_power == NULL) + goto fail_alloc_context; + + core_power->edp_num = edp_num; + core_power->map = kzalloc(sizeof(struct power_entity) * MOD_POWER_MAX_CONCURRENT_STREAMS, + GFP_KERNEL); + + if (core_power->map == NULL) + goto fail_alloc_map; + + for (i = 0; i < MOD_POWER_MAX_CONCURRENT_STREAMS; i++) { + core_power->map[i].stream = NULL; + } + + for (i = 0; i < MOD_POWER_MAX_CONCURRENT_STREAMS; i++) { + core_power->map[i].psr_context = + kzalloc(sizeof(struct mod_power_psr_context), + GFP_KERNEL); + if (core_power->map[i].psr_context == NULL) + goto fail_construct; + } + + core_power->psr_smu_optimizations_support = init_params->allow_psr_smu_optimizations; + core_power->multi_disp_optimizations_support = init_params->allow_psr_multi_disp_optimizations; + + for (inst = 0; inst < edp_num; inst++) { + core_power->bl_prop[inst].min_abm_backlight = + init_params[inst].min_abm_backlight; + core_power->bl_prop[inst].disable_fractional_pwm = + init_params[inst].disable_fractional_pwm; + core_power->bl_prop[inst].use_linear_backlight_curve = + init_params[inst].use_linear_backlight_curve; + core_power->bl_prop[inst].use_nits_based_brightness = + init_params[inst].use_nits_based_brightness; + core_power->bl_prop[inst].backlight_ramping_override = + init_params[inst].backlight_ramping_override; + core_power->bl_prop[inst].backlight_ramping_reduction = + init_params[inst].backlight_ramping_reduction; + core_power->bl_prop[inst].backlight_ramping_start = + init_params[inst].backlight_ramping_start; + core_power->bl_prop[inst].use_custom_backlight_caps = + init_params[inst].use_custom_backlight_caps; + core_power->bl_prop[inst].custom_backlight_caps_config_no = + init_params[inst].custom_backlight_caps_config_no; + + // Do not allow less than 101 backlight levels + if (init_params[inst].num_backlight_levels < 101) + core_power->bl_prop[inst].num_backlight_levels = 101; + else + core_power->bl_prop[inst].num_backlight_levels = + init_params[inst].num_backlight_levels; + + core_power->bl_prop[inst].backlight_lut = (unsigned int *) + (kzalloc(sizeof(unsigned int) * + core_power->bl_prop[inst].num_backlight_levels, GFP_KERNEL)); + if (core_power->bl_prop[inst].backlight_lut == NULL) + goto fail_alloc_backlight_array; + } + + core_power->varibright_prop.varibright_active = false; + + core_power->varibright_prop.varibright_user_enable = + init_params->def_varibright_enable; + + // Table of ABM levels here is 1-4, but level 0 also exists as 'off' + if (init_params->varibright_level <= abm_defines_max_level) { + core_power->varibright_prop.varibright_level = + init_params->varibright_level; + + } else { + core_power->varibright_prop.varibright_level = 3; + } + if (init_params->def_varibright_level <= abm_defines_max_level) { + core_power->varibright_prop.def_varibright_level = + init_params->def_varibright_level; + } else { + core_power->varibright_prop.def_varibright_level = 3; + } + + // ABM used to contain 4 different configs. There is only 3 since ABM 2.3. + if ((dc->res_pool->dmcu != NULL) && (dc->res_pool->dmcu->dmcu_version.abm_version < 0x23)) + abm_max_config = 4; + else + abm_max_config = 3; + + if (init_params->abm_config_setting < abm_max_config) + core_power->varibright_prop.varibright_config_setting = + init_params->abm_config_setting; + else + core_power->varibright_prop.varibright_config_setting = 0; + + for (inst = 0; inst < edp_num; inst++) { + core_power->bl_prop[inst].backlight_lut[0] = init_params[inst].min_backlight_pwm; + core_power->bl_prop[inst].backlight_lut[ + core_power->bl_prop[inst].num_backlight_levels-1] = + init_params[inst].max_backlight_pwm; + core_power->bl_prop[inst].min_backlight_pwm = init_params[inst].min_backlight_pwm; + core_power->bl_prop[inst].max_backlight_pwm = init_params[inst].max_backlight_pwm; + core_power->bl_prop[inst].ac_backlight_percent = + default_ac_backlight_percent; + core_power->bl_prop[inst].dc_backlight_percent = + default_dc_backlight_percent; + core_power->bl_prop[inst].backlight_caps_valid = false; + + if (core_power->bl_prop[inst].use_nits_based_brightness) { + core_power->bl_prop[inst].min_brightness_millinits = + init_params[inst].panel_min_millinits; + core_power->bl_prop[inst].max_brightness_millinits = + init_params[inst].panel_max_millinits; + } else { + + core_power->bl_prop[inst].min_brightness_millinits = + pwr_default_min_brightness_millinits; + core_power->bl_prop[inst].max_brightness_millinits = + pwr_default_sdr_brightness_millinits; + } + + core_power->bl_prop[inst].backlight_range = + core_power->bl_prop[inst].max_backlight_pwm- + core_power->bl_prop[inst].min_backlight_pwm; + + core_power->bl_prop[inst].nits_range = + core_power->bl_prop[inst].max_brightness_millinits - + core_power->bl_prop[inst].min_brightness_millinits; + + core_power->bl_state[inst].smooth_brightness_enabled = true; + } + + /* Check if at least 1 instance in core_power is populated before failing */ + for (inst = 0; inst < edp_num; inst++) { + if (core_power->bl_prop[inst].nits_range != 0 && core_power->bl_prop[inst].backlight_range != 0) { + is_brightness_range_valid = true; + break; + } + + } + if (!is_brightness_range_valid) + goto fail_bad_brightness_range; + + core_power->num_entities = 0; + + core_power->dc = dc; + for (inst = 0; inst < edp_num; inst++) { + initialize_backlight_caps(core_power, inst); + core_power->bl_state[inst].backlight_millipercent = + core_power->bl_prop[inst].dc_backlight_percent * 1000; + core_power->bl_state[inst].backlight_pwm = backlight_millipercent_to_pwm(core_power, + core_power->bl_state[inst].backlight_millipercent, inst); + core_power->bl_state[inst].backlight_millinit = backlight_millipercent_to_millinit(core_power, + core_power->bl_state[inst].backlight_millipercent, inst); + } + + return &core_power->public; + +fail_bad_brightness_range: +fail_alloc_backlight_array: + for (inst = 0; inst < edp_num; inst++) + if (core_power->bl_prop[inst].backlight_lut) + kfree(core_power->bl_prop[inst].backlight_lut); +fail_construct: + for (i = 0; i < MOD_POWER_MAX_CONCURRENT_STREAMS; i++) { + if (core_power->map[i].psr_context) + kfree(core_power->map[i].psr_context); + } + kfree(core_power->map); + +fail_alloc_map: + kfree(core_power); + +fail_alloc_context: +fail_dc_null: + return NULL; +} + +void mod_power_destroy(struct mod_power *mod_power) +{ + if (mod_power != NULL) { + unsigned int i; + struct core_power *core_power = + MOD_POWER_TO_CORE(mod_power); + + for (i = 0; i < MOD_POWER_MAX_CONCURRENT_STREAMS; i++) + if (core_power->map[i].psr_context) + kfree(core_power->map[i].psr_context); + + for (i = 0; i < core_power->num_entities; i++) + if (core_power->map[i].stream) + dc_stream_release(core_power->map[i].stream); + + kfree(core_power->map); + + for (i = 0; i < MAX_NUM_EDP; i++) + if (core_power->bl_prop[i].backlight_lut) + kfree(core_power->bl_prop[i].backlight_lut); + + kfree(core_power); + } +} + +bool mod_power_add_stream(struct mod_power *mod_power, + struct dc_stream_state *stream, struct psr_caps *caps) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities < MOD_POWER_MAX_CONCURRENT_STREAMS) { + dc_stream_retain(stream); + + core_power->map[core_power->num_entities].stream = stream; + core_power->map[core_power->num_entities].caps = caps; + + // initialize cached PSR params to something "safe" (something that is + // consistent with disabled PSR state) + core_power->map[core_power->num_entities].psr_enabled = 0; + core_power->map[core_power->num_entities].psr_events = psr_event_vsync; + core_power->map[core_power->num_entities].psr_power_opt = 0; + core_power->num_entities++; + return true; + } + + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power: add_stream: ERROR: stream=%p num_entities=%u >= MOD_POWER_MAX_CONCURRENT_STREAMS", + stream, + core_power->num_entities); + + return false; +} + +bool mod_power_remove_stream(struct mod_power *mod_power, + const struct dc_stream_state *stream) +{ + unsigned int i = 0; + struct core_power *core_power = NULL; + unsigned int index = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + if (core_power->num_entities == 0) { + /* trying to remove a stream a second time or have not added yet */ + BREAK_TO_DEBUGGER(); + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power: remove_stream: ERROR: num_entities=0 stream=%p", + stream); + return false; + } + + index = map_index_from_stream(core_power, stream); + + if (index >= core_power->num_entities) { + /* trying to remove a stream a second time or have not added yet */ + BREAK_TO_DEBUGGER(); + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power: remove_stream: ERROR: index=%u >= num_entities=%u stream=%p", + index, + core_power->num_entities, + stream); + return false; + } + + dc_stream_release(core_power->map[index].stream); + core_power->map[index].stream = NULL; + /* To remove this entity, shift everything after down */ + for (i = index; i < core_power->num_entities - 1; i++) { + core_power->map[i].stream = core_power->map[i + 1].stream; + core_power->map[i].caps = core_power->map[i + 1].caps; + + // copy over cached parameters in case they map to PSR capable display + core_power->map[i].psr_enabled = core_power->map[i + 1].psr_enabled; + core_power->map[i].psr_events = core_power->map[i + 1].psr_events; + core_power->map[i].psr_power_opt = core_power->map[i + 1].psr_power_opt; + + memcpy(core_power->map[i].psr_context, core_power->map[i + 1].psr_context, sizeof(struct mod_power_psr_context)); + memset(core_power->map[i + 1].psr_context, 0, sizeof(struct mod_power_psr_context)); + } + core_power->num_entities--; + + return true; +} + +/* + * Replace_stream should be used when there is a mode set for existing + * display target with a valid stream. In this case might need to retain + * cached PSR state (events, power opt, en/dis) if we are dealing with PSR + * capable display. If mod_power_remove and mod_power_add are used instead, + * then stream may be assigned to a different slot and may end up with + * wrong cached PSR state. It is hard to tell which PSR events should + * persist through mode set or what psr_events should be initialized to, so + * it might be better just to retain them all. + */ +bool mod_power_replace_stream(struct mod_power *mod_power, + const struct dc_stream_state *current_stream, + struct dc_stream_state *new_stream, + struct psr_caps *new_caps) +{ + struct core_power *core_power = NULL; + unsigned int index = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + if (core_power->num_entities == 0) { + /* no streams exist in the table yet */ + BREAK_TO_DEBUGGER(); + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power: replace_stream: ERROR: num_entities=0 stream=%p", + current_stream); + return false; + } + + index = map_index_from_stream(core_power, current_stream); + + if (index >= core_power->num_entities) { + /* trying to replace a non-existent stream */ + BREAK_TO_DEBUGGER(); + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power: replace_stream: ERROR: index=%u >= num_entities=%u stream=%p", + index, + core_power->num_entities, + current_stream); + return false; + } + + dc_stream_release(core_power->map[index].stream); + dc_stream_retain(new_stream); + core_power->map[index].stream = new_stream; + core_power->map[index].caps = new_caps; + memset(core_power->map[index].psr_context, 0, sizeof(struct mod_power_psr_context)); + + return true; +} + +static bool set_backlight_millinits_aux(struct core_power *core_power, + struct dc_stream_state *stream, + unsigned int backlight_millinits, + unsigned int transition_time_millisec, + unsigned int inst) +{ + struct dc_link *link = NULL; + + if (core_power == NULL) + return false; + + if (stream == NULL) + return true; + + link = dc_stream_get_link(stream); + + return dc_link_set_backlight_level_nits(link, core_power->bl_state[inst].isHDR, + backlight_millinits, transition_time_millisec); +} + +static bool set_backlight(struct core_power *core_power, + struct dc_stream_state *stream, + struct set_backlight_level_params *backlight_level_params, + unsigned int inst) +{ + bool retv = false; + unsigned int frame_ramp = 0; + unsigned int vsync_rate_hz; + union dmcu_abm_set_bl_params params; + const struct dc_link *link = NULL; + unsigned int backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16; + unsigned int transition_time_millisec = backlight_level_params->transition_time_in_ms; + + if (core_power == NULL) + return false; + + core_power->bl_state[inst].backlight_pwm = backlight_pwm_u16_16; + + if (stream == NULL) + return true; + + if (stream->link->connector_signal != SIGNAL_TYPE_EDP) + return false; + + if (transition_time_millisec != 0) { + unsigned int v_total = + (stream->adjust.v_total_max == 0) ? stream->timing.v_total : stream->adjust.v_total_max; + + vsync_rate_hz = (unsigned int)div_u64(div_u64((stream-> + timing.pix_clk_100hz * 100), + v_total), + stream->timing.h_total); + + if (core_power->bl_state[inst].smooth_brightness_enabled) + frame_ramp = ((vsync_rate_hz * + transition_time_millisec) + 500) / 1000; + } + + core_power->bl_state[inst].frame_ramp = frame_ramp; + params.u32All = 0; + params.bits.gradual_change = (frame_ramp > 0); + params.bits.frame_ramp = frame_ramp; + link = dc_stream_get_link(stream); + + mod_power_set_psr_event(&core_power->public, stream, true, psr_event_hw_programming, true); + mod_power_set_replay_event(&core_power->public, stream, true, replay_event_hw_programming, true); + + backlight_level_params->frame_ramp = params.u32All; + retv = dc_link_set_backlight_level(link, backlight_level_params); + + mod_power_set_psr_event(&core_power->public, stream, false, psr_event_hw_programming, false); + mod_power_set_replay_event(&core_power->public, stream, false, replay_event_hw_programming, false); + + return retv; +} + +static void fill_backlight_level_params(struct core_power *core_power, + struct set_backlight_level_params *backlight_level_params, + int panel_inst, uint8_t aux_inst, unsigned int backlight_pwm, + enum backlight_control_type backlight_control_type, + unsigned int backlight_millinit, unsigned int transition_time_millisec, + bool is_hdr) +{ + struct pwr_backlight_properties *bl_prop = &core_power->bl_prop[panel_inst]; + + backlight_level_params->aux_inst = aux_inst; + backlight_level_params->backlight_pwm_u16_16 = backlight_pwm; + backlight_level_params->control_type = backlight_control_type; + backlight_level_params->backlight_millinits = backlight_millinit; + backlight_level_params->transition_time_in_ms = transition_time_millisec; + backlight_level_params->min_luminance = bl_prop->min_brightness_millinits; + backlight_level_params->max_luminance = bl_prop->max_brightness_millinits; + backlight_level_params->min_backlight_pwm = bl_prop->min_backlight_pwm; + backlight_level_params->max_backlight_pwm = bl_prop->max_backlight_pwm; + + if (backlight_control_type == BACKLIGHT_CONTROL_AMD_AUX && !is_hdr) + backlight_level_params->control_type = BACKLIGHT_CONTROL_PWM; +} + +bool mod_power_set_backlight_nits(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millinit, + unsigned int transition_time_millisec, + bool skip_aux, + bool is_hdr) +{ + struct core_power *core_power = NULL; + unsigned int backlight_pwm; + unsigned int panel_inst = 0; + struct set_backlight_level_params backlight_level_params = { 0 }; + const struct dc_link *link = NULL; + uint8_t aux_inst = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + link = dc_stream_get_link(stream); + + ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF); + aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel; + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst)) + return false; + + if (!skip_aux) { + if (!set_backlight_millinits_aux(core_power, stream, + backlight_millinit, transition_time_millisec, panel_inst)) + return false; + } +// always send both AUX (above) and PWM (below) + core_power->bl_state[panel_inst].backlight_millinit = backlight_millinit; + + core_power->bl_state[panel_inst].backlight_millipercent = + backlight_millinit_to_millipercent( + core_power, backlight_millinit, panel_inst); + + backlight_pwm = backlight_millinit_to_pwm( + core_power, backlight_millinit, panel_inst); + + fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, aux_inst, backlight_pwm, + link->backlight_control_type, backlight_millinit, transition_time_millisec, is_hdr); + + return set_backlight(core_power, stream, + &backlight_level_params, panel_inst); +} + + +bool mod_power_backlight_percent_to_nits(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millipercent, + unsigned int *backlight_millinit) +{ + struct core_power *core_power = NULL; + unsigned int inst = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) + return false; + + *backlight_millinit = backlight_millipercent_to_millinit( + core_power, backlight_millipercent, inst); + return true; +} + +bool mod_power_backlight_nits_to_percent(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millinit, + unsigned int *backlight_millipercent) +{ + struct core_power *core_power = NULL; + unsigned int inst = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) + return false; + + *backlight_millipercent = backlight_millinit_to_millipercent( + core_power, backlight_millinit, inst); + return true; +} + +bool mod_power_set_backlight_percent(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millipercent, + unsigned int transition_time_millisec, + bool is_hdr) +{ + struct core_power *core_power = NULL; + struct set_backlight_level_params backlight_level_params = { 0 }; + const struct dc_link *link = NULL; + unsigned int backlight_pwm; + unsigned int panel_inst = 0; + uint8_t aux_inst = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + link = dc_stream_get_link(stream); + ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF); + aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel; + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst)) + return false; + core_power->bl_state[panel_inst].backlight_millipercent = backlight_millipercent; + + core_power->bl_state[panel_inst].backlight_millinit = + backlight_millipercent_to_millinit( + core_power, backlight_millipercent, panel_inst); + + backlight_pwm = backlight_millipercent_to_pwm( + core_power, backlight_millipercent, panel_inst); + + fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, + aux_inst, backlight_pwm, link->backlight_control_type, + core_power->bl_state[panel_inst].backlight_millinit, transition_time_millisec, is_hdr); + + return set_backlight(core_power, stream, + &backlight_level_params, panel_inst); +} + +void mod_power_update_backlight(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millipercent) +{ + struct core_power *core_power = NULL; + unsigned int inst = 0; + + if (mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) + return; + core_power->bl_state[inst].backlight_millipercent = backlight_millipercent; + + core_power->bl_state[inst].backlight_millinit = + backlight_millipercent_to_millinit( + core_power, backlight_millipercent, inst); + + core_power->bl_state[inst].backlight_pwm = backlight_millipercent_to_pwm( + core_power, backlight_millipercent, inst); +} + +void mod_power_update_backlight_nits(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millinit) +{ + struct core_power *core_power = NULL; + unsigned int inst = 0; + + if (mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) + return; + + core_power->bl_state[inst].backlight_millinit = backlight_millinit; + + core_power->bl_state[inst].backlight_millipercent = backlight_millinit_to_millipercent( + core_power, backlight_millinit, inst); + core_power->bl_state[inst].backlight_pwm = backlight_millinit_to_pwm( + core_power, backlight_millinit, inst); +} + +bool mod_power_get_backlight_pwm(struct mod_power *mod_power, + unsigned int *backlight_pwm, + unsigned int inst) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *backlight_pwm = core_power->bl_state[inst].backlight_pwm; + + return true; +} + +bool mod_power_get_backlight_nits(struct mod_power *mod_power, + unsigned int *backlight_millinit, + unsigned int inst) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *backlight_millinit = core_power->bl_state[inst].backlight_millinit; + + return true; +} + +bool mod_power_get_backlight_percent(struct mod_power *mod_power, + unsigned int *backlight_millipercent, + unsigned int inst) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *backlight_millipercent = core_power->bl_state[inst].backlight_millipercent; + + return true; +} + +bool mod_power_get_hw_target_backlight_pwm_nits(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millinit, + unsigned int inst) +{ + struct core_power *core_power = NULL; + unsigned int backlight_u16_16 = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (mod_power_get_hw_target_backlight_pwm(mod_power, link, + &backlight_u16_16)) { + *backlight_millinit = + backlight_pwm_to_millinit(core_power, + backlight_u16_16, inst); + return true; + } + return false; +} + +bool mod_power_get_hw_target_backlight_pwm_percent(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millipercent, + unsigned int inst) +{ + struct core_power *core_power = NULL; + unsigned int backlight_u16_16 = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (mod_power_get_hw_target_backlight_pwm(mod_power, link, + &backlight_u16_16)) { + *backlight_millipercent = + backlight_pwm_to_millipercent(core_power, + backlight_u16_16, inst); + return true; + } + return false; +} + +bool mod_power_get_hw_target_backlight_pwm(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_u16_16) +{ + if (mod_power == NULL) + return false; + + *backlight_u16_16 = dc_link_get_target_backlight_pwm(link); + + return true; +} + +bool mod_power_get_hw_backlight_pwm_nits(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millinit, + unsigned int inst) +{ + struct core_power *core_power = NULL; + unsigned int backlight_u16_16 = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (mod_power_get_hw_backlight_pwm(mod_power, link, &backlight_u16_16)) { + *backlight_millinit = + backlight_pwm_to_millinit(core_power, + backlight_u16_16, inst); + return true; + } + return false; +} + +bool mod_power_get_hw_backlight_aux_nits(struct mod_power *mod_power, + struct dc_stream_state **streams, int num_streams, + unsigned int *backlight_millinit_avg, + unsigned int *backlight_millinit_peak) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + int stream_index; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power == NULL) + return false; + + if (num_streams < 1) + return true; + + for (stream_index = 0; stream_index < num_streams; stream_index++) + if (streams[stream_index]->link->connector_signal == SIGNAL_TYPE_EDP || + streams[stream_index]->link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) + break; + + if (stream_index == num_streams) + return false; + + link = dc_stream_get_link(streams[stream_index]); + if (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 0) + return false; + + return dc_link_get_backlight_level_nits(link, backlight_millinit_avg, + backlight_millinit_peak); +} + +bool mod_power_get_hw_backlight_pwm_percent(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millipercent, + unsigned int inst) +{ + struct core_power *core_power = NULL; + unsigned int backlight_u16_16 = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (mod_power_get_hw_backlight_pwm(mod_power, link, &backlight_u16_16)) { + *backlight_millipercent = + backlight_pwm_to_millipercent(core_power, + backlight_u16_16, inst); + return true; + } + return false; +} + +bool mod_power_get_hw_backlight_pwm(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_u16_16) +{ + if (mod_power == NULL) + return false; + + *backlight_u16_16 = dc_link_get_backlight_level(link); + + return true; +} + +bool mod_power_get_panel_backlight_boundaries( + struct mod_power *mod_power, + unsigned int *out_min_backlight, + unsigned int *out_max_backlight, + unsigned int *out_ac_backlight_percent, + unsigned int *out_dc_backlight_percent, + unsigned int inst) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + /* If cache was successfully updated, + * copy the values to output structure and return success + */ + if (core_power->bl_prop[inst].backlight_caps_valid) { + *out_min_backlight = core_power->bl_prop[inst].backlight_lut[0]; + *out_max_backlight = + core_power->bl_prop[inst].backlight_lut[ + core_power->bl_prop[inst].num_backlight_levels - 1]; + *out_ac_backlight_percent = + core_power->bl_prop[inst].ac_backlight_percent; + *out_dc_backlight_percent = + core_power->bl_prop[inst].dc_backlight_percent; + + return true; + } + + return false; +} + +bool mod_power_set_smooth_brightness(struct mod_power *mod_power, + bool enable_brightness, + unsigned int inst) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + core_power->bl_state[inst].smooth_brightness_enabled = enable_brightness; + + return true; +} + +bool mod_power_notify_mode_change(struct mod_power *mod_power, + const struct dc_stream_state *stream, + bool is_hdr) +{ + unsigned int stream_index = 0; + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + struct psr_config psr_config = {0}; + struct psr_context psr_context = {0}; + struct dc *dc = NULL; + unsigned int panel_inst = 0; + int active_psr_events = 0; + int active_replay_events = 0; + + if ((mod_power == NULL) || (stream == NULL)) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + stream_index = map_index_from_stream(core_power, stream); + + if (stream_index >= core_power->num_entities) + return false; + + dc = core_power->dc; + link = dc_stream_get_link(stream); + active_psr_events = core_power->map[stream_index].psr_events; + active_replay_events = core_power->map[stream_index].replay_events; + if (link != NULL && dc_get_edp_link_panel_inst(dc, link, &panel_inst)) { + struct set_backlight_level_params backlight_level_params = { 0 }; + + ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF); + uint8_t aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel; + + if (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || + link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) + dc_link_set_backlight_level_nits(link, core_power->bl_state[panel_inst].isHDR, + core_power->bl_state[panel_inst].backlight_millinit, 0); + + backlight_level_params.frame_ramp = 0; + + fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, aux_inst, + core_power->bl_state[panel_inst].backlight_pwm, link->backlight_control_type, + core_power->bl_state[panel_inst].backlight_millinit, 0, is_hdr); + + dc_link_set_backlight_level(link, &backlight_level_params); + + mod_power_calc_psr_configs(&psr_config, link, stream); + + psr_config.psr_exit_link_training_required = core_power->map[stream_index].caps->psr_exit_link_training_required; + + if (dc->ctx->asic_id.chip_family >= AMDGPU_FAMILY_GC_11_0_1) + psr_config.allow_smu_optimizations = + core_power->psr_smu_optimizations_support && dc_is_embedded_signal(stream->signal); + else + psr_config.allow_smu_optimizations = + core_power->psr_smu_optimizations_support && mod_power_only_edp(dc->current_state, stream); + + psr_config.allow_multi_disp_optimizations = core_power->multi_disp_optimizations_support; + + psr_config.rate_control_caps = core_power->map[stream_index].caps->rate_control_caps; + + if (active_psr_events & psr_event_os_request_force_ffu) { + psr_config.os_request_force_ffu = true; + } + /* + * DSC support: + * DSC slice height value must be 'mod' by su_y_granularity. + * According to Panel Vendor, there might be varied conditions to fulfill. + * Right now, DSC slice height value must be multiple of su_y_granularity. + * + * The value of DSC slice height is determined in DSC Driver but it does not + * propagated out here, so we need to calculate it as below 'slice_height'. + */ + psr_su_set_dsc_slice_height(dc, link, + (struct dc_stream_state *) stream, + &psr_config); + + dc_link_setup_psr(link, stream, &psr_config, &psr_context); + + link->replay_settings.replay_smu_opt_enable = + (link->replay_settings.config.replay_smu_opt_supported && + mod_power_only_edp(dc->current_state, stream)); + + if (active_replay_events & replay_event_os_request_force_ffu) { + link->replay_settings.config.os_request_force_ffu = true; + } + + if (dc_is_embedded_signal(stream->signal)) + dc->link_srv->dp_setup_replay(link, stream); + } + + return true; +} + +bool mod_power_varibright_feature_enable(struct mod_power *mod_power, bool enable, + struct dc_stream_update *stream_update) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + core_power->varibright_prop.varibright_user_enable = enable; + + /* find abm hw level to program, and save in stream update */ + varibright_set_level(core_power); + *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; + + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">ABM feature enable: enable=%u su->varibright_level=%u varibright_hw_level=%u", + (unsigned int) enable, + *stream_update->abm_level, + core_power->varibright_prop.varibright_hw_level); + return true; +} + +bool mod_power_varibright_activate(struct mod_power *mod_power, + bool activate, + struct dc_stream_update *stream_update) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + core_power->varibright_prop.varibright_active = activate; + + /* find abm hw level to program, and save in stream update */ + varibright_set_level(core_power); + *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; + + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">ABM activate: activate=%u su->varibright_level=%u", + (unsigned int) activate, + *stream_update->abm_level); + return true; +} +bool mod_power_varibright_set_level(struct mod_power *mod_power, unsigned int level, + struct dc_stream_update *stream_update) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + core_power->varibright_prop.varibright_level = level; + core_power->varibright_prop.varibright_hw_level = level; + + /* find abm hw level to program, and save in stream update */ + varibright_set_level(core_power); + *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; + + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">ABM set level: level=%u -> (varibright_level=%u varibright_hw_level=%u) -> su->varibright_level=%u", + level, + core_power->varibright_prop.varibright_level, + core_power->varibright_prop.varibright_hw_level, + *stream_update->abm_level); + return true; +} + +bool mod_power_varibright_set_hw_level(struct mod_power *mod_power, unsigned int level, + struct dc_stream_update *stream_update) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (level == 0 || level == ABM_LEVEL_IMMEDIATE_DISABLE) + core_power->varibright_prop.varibright_active = 0; + else + core_power->varibright_prop.varibright_active = 1; + core_power->varibright_prop.varibright_hw_level = level; + *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; + + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">ABM set level: level=%u -> (varibright_level=%u varibright_hw_level=%u) -> su->varibright_level=%u", + level, + core_power->varibright_prop.varibright_level, + core_power->varibright_prop.varibright_hw_level, + *stream_update->abm_level); + return true; +} + +bool mod_power_get_varibright_level(struct mod_power *mod_power, + unsigned int *varibright_level) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *varibright_level = core_power->varibright_prop.varibright_level; + + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">get varibright level: cp->varibright_level=%u", + *varibright_level); + return true; + +} + +bool mod_power_get_varibright_hw_level(struct mod_power *mod_power, + unsigned int *varibright_level) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *varibright_level = core_power->varibright_prop.varibright_hw_level; + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">get varibright HW level: hw_level=%u", + *varibright_level); + return true; +} + +bool mod_power_get_varibright_default_level(struct mod_power *mod_power, + unsigned int *varibright_level) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *varibright_level = core_power->varibright_prop.def_varibright_level; + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">get varibright default level: def_varibright_level=%u", + *varibright_level); + return true; +} + +bool mod_power_get_varibright_enable(struct mod_power *mod_power, + bool *varibright_enable) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *varibright_enable = core_power->varibright_prop.varibright_user_enable; + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">get varibright enable state: varibright_user_enable=%u", + (unsigned int) (*varibright_enable)); + return true; +} + +bool mod_power_is_abm_active(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int inst) +{ + unsigned int user_backlight = 0; + unsigned int current_backlight = 0; + bool is_active = false; + + if (mod_power == NULL) + return false; + + mod_power_get_backlight_pwm(mod_power, &user_backlight, inst); + mod_power_get_hw_backlight_pwm(mod_power, link, ¤t_backlight); + + if (user_backlight != current_backlight) + is_active = true; + else + is_active = false; + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">get ABM active state: is_active=%u (user_backlight_pwm=%u, current_backlight_pwm=%u)", + (unsigned int)is_active, + user_backlight, + current_backlight); + return is_active; +} + + +static void mod_power_psr_set_power_opt(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int active_psr_events, + bool psr_enable_request) +{ + (void)psr_enable_request; + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + unsigned int stream_index = 0; + unsigned int power_opt = 0; + + if (!stream) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + stream_index = map_index_from_stream(core_power, stream); + if (!core_power->map[stream_index].caps->psr_version) + return; + + link = dc_stream_get_link(stream); + + if (active_psr_events == 0) { + /* Static Screen */ + power_opt |= (psr_power_opt_smu_opt_static_screen | psr_power_opt_z10_static_screen | + psr_power_opt_ds_disable_allow); + } + + /* psr_power_opt_flag is a configuration parameter into the module that determines + * which optimizations to enable during psr + */ + power_opt &= core_power->map[stream_index].caps->psr_power_opt_flag; + if (core_power->map[stream_index].psr_power_opt != power_opt) { + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power set_power_opt: psr_power_opt=0x%04x, power_opt=0x%04x" + "active_psr_events=0x%04x, psr_power_opt_flag=0x%04x", + core_power->map[stream_index].psr_power_opt, + power_opt, + active_psr_events, + core_power->map[stream_index].caps->psr_power_opt_flag); + dc_link_set_psr_allow_active(link, NULL, false, false, &power_opt); + core_power->map[stream_index].psr_power_opt = power_opt; + } +} + +static bool set_psr_enable(struct mod_power *mod_power, + struct dc_stream_state *stream, + bool psr_enable, + bool wait, + bool force_static) +{ + struct core_power *core_power = NULL; + enum dc_psr_state state = PSR_STATE0; + unsigned int retry_count; + const unsigned int max_retry = 1000; + struct dc_link *link = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) { + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "set psr enable: ERROR: stream=%p num_entities=%u", + stream, + core_power->num_entities); + return false; + } + + if (psr_enable) { + unsigned int vsync_rate_hz; + struct dc_static_screen_params params = {0}; + + vsync_rate_hz = (unsigned int)div_u64(div_u64(( + stream->timing.pix_clk_100hz * 100), + stream->timing.v_total), + stream->timing.h_total); + + params.triggers.cursor_update = true; + params.triggers.overlay_update = true; + params.triggers.surface_update = true; + params.num_frames = calc_psr_num_static_frames(vsync_rate_hz); + + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Firmware_PsrState, + "set psr enable: CALCS: pix_clk_100hz=%u v_total=%u h_total=%u vsync_rate_hz=%u num_frames=%u", + stream->timing.pix_clk_100hz, + stream->timing.v_total, + stream->timing.h_total, + vsync_rate_hz, + params.num_frames); + + dc_stream_set_static_screen_params(core_power->dc, + &stream, 1, + ¶ms); + } + + link = dc_stream_get_link(stream); + + if (!dc_link_set_psr_allow_active(link, &psr_enable, false, force_static, NULL)) { + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "set psr enable: ERROR: stream=%p link=%p psr_enable=%d", + stream, + link, + psr_enable); + return false; + } + + if (wait == true) { + + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Firmware_PsrState, + "set psr enable: BEGIN WAIT: psr_enable=%d", + (int)psr_enable); + + for (retry_count = 0; retry_count <= max_retry; retry_count++) { + dc_link_get_psr_state(link, &state); + if (psr_enable) { + if (state != PSR_STATE0 && + (!force_static || state == PSR_STATE3)) + break; + } else { + if (state == PSR_STATE0) + break; + } + udelay(500); + } + + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Firmware_PsrState, + "set psr enable: END WAIT: psr_enable=%d", + (int)psr_enable); + + /* assert if max retry hit */ + if (retry_count >= max_retry) { + ASSERT(0); + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "set psr enable: ERROR: retry_count=%u: Unexpectedly long wait for PSR state change.", + retry_count); + } + } else { + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Firmware_PsrState, + "set psr enable: PSR state change initiated (wait=false): psr_enable=%d", + (int)psr_enable); + } + + return true; +} + +bool mod_power_get_psr_event(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int *active_psr_events) +{ + struct core_power *core_power = NULL; + unsigned int stream_index = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + stream_index = map_index_from_stream(core_power, stream); + + if (!core_power->map[stream_index].caps->psr_version) + return false; + + *active_psr_events = core_power->map[stream_index].psr_events; + + return true; +} + +bool mod_power_set_psr_event(struct mod_power *mod_power, + struct dc_stream_state *stream, bool set_event, + enum psr_event event, bool wait) +{ + struct core_power *core_power = NULL; + unsigned int stream_index = 0; + unsigned int active_psr_events = 0; + bool psr_enable_request = false; + bool force_static = false; + + if (mod_power == NULL || stream == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + stream_index = map_index_from_stream(core_power, stream); + + if (core_power->num_entities == 0) { + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power set_psr_event: ERROR: stream=%p event=%d num_entities=%u", + stream, + (int)event, + core_power->num_entities); + return false; + } + + if (!core_power->map[stream_index].caps->psr_version) + return false; + + if (set_event) + core_power->map[stream_index].psr_events |= event; + else + core_power->map[stream_index].psr_events &= ~event; + + active_psr_events = core_power->map[stream_index].psr_events; + + // ignore other events when we're in forced psr enabled state + if (active_psr_events & psr_event_dynamic_display_switch && + event != psr_event_dynamic_display_switch) + return false; + + // ignore other events when we're in forced psr enabled state + if (active_psr_events & psr_event_os_override_hold && + event != psr_event_os_override_hold) + return false; + + // ignore other events when we're in forced psr enabled state + // dds events need to be processed while in dynamic_link_rate_control + if (active_psr_events & psr_event_dynamic_link_rate_control && + event != psr_event_dynamic_link_rate_control && + event != psr_event_dds_defer_stream_enable && + event != psr_event_dynamic_display_switch) + return false; + + if (active_psr_events & (psr_event_test_harness_disable_psr | psr_event_os_request_disable)) + psr_enable_request = false; + else if (active_psr_events & psr_event_pause) + psr_enable_request = false; + else if (active_psr_events & psr_event_test_harness_enable_psr) + psr_enable_request = true; + else if (active_psr_events & psr_event_dynamic_display_switch) { + psr_enable_request = true; + force_static = true; + } else if (active_psr_events & psr_event_dynamic_link_rate_control) { + psr_enable_request = true; + force_static = true; + } else if (active_psr_events & psr_event_edp_panel_off_disable_psr) + psr_enable_request = false; + else if (active_psr_events & (psr_event_hw_programming | + psr_event_defer_enable | + psr_event_dds_defer_stream_enable | + psr_event_vrr_transition | + psr_event_immediate_flip)) + psr_enable_request = false; + else if (active_psr_events & psr_event_big_screen_video) + psr_enable_request = true; + else if (active_psr_events & psr_event_full_screen) + psr_enable_request = false; + else if (active_psr_events & psr_event_mpo_video_selective_update) + psr_enable_request = true; + else if (active_psr_events & psr_event_vsync) + psr_enable_request = false; + else if (active_psr_events & psr_event_crc_window_active) + psr_enable_request = false; + else + psr_enable_request = true; + + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power set_psr_event: before: psr_enabled=%d -> request: set_event=%d event=0x%04x -> result: psr_events=0x%04x psr_enable_request=%d", + (int)core_power->map[stream_index].psr_enabled, + (int)set_event, + (unsigned int)event, + (unsigned int)core_power->map[stream_index].psr_events, + (int)psr_enable_request); + mod_power_psr_set_power_opt(mod_power, stream, active_psr_events, psr_enable_request); + + if (core_power->map[stream_index].psr_enabled != psr_enable_request || force_static) { + if (set_psr_enable(mod_power, stream, psr_enable_request, wait, force_static)) { + core_power->map[stream_index].psr_enabled = psr_enable_request; + } + } + + return true; +} + +bool mod_power_get_psr_state(struct mod_power *mod_power, + const struct dc_stream_state *stream, + enum dc_psr_state *state) +{ + struct core_power *core_power = NULL; + const struct dc_link *link = NULL; + + if (!stream) + return false; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + link = dc_stream_get_link(stream); + return dc_link_get_psr_state(link, state); +} + +bool mod_power_get_psr_enabled_status(struct mod_power *mod_power, + const struct dc_stream_state *stream, + bool *psr_enabled) +{ + struct core_power *core_power = NULL; + unsigned int stream_index = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + stream_index = map_index_from_stream(core_power, stream); + + if (!core_power->map[stream_index].caps->psr_version) + return false; + + *psr_enabled = core_power->map[stream_index].psr_enabled; + + return true; +} + +void mod_power_psr_residency(struct mod_power *mod_power, + const struct dc_stream_state *stream, + unsigned int *residency, + const uint8_t mode) +{ + struct core_power *core_power = NULL; + const struct dc_link *link = NULL; + + if (!stream) + return; + + if (mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return; + + link = dc_stream_get_link(stream); + + if (link != NULL) + link->dc->link_srv->edp_get_psr_residency(link, residency, mode); +} +bool mod_power_psr_get_active_psr_events(struct mod_power *mod_power, + const struct dc_stream_state *stream, unsigned int *active_psr_events) +{ + struct core_power *core_power = NULL; + unsigned int stream_index = 0; + + if (!stream) + return false; + + if (mod_power == NULL) + return false; + + if (active_psr_events == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + stream_index = map_index_from_stream(core_power, stream); + + *active_psr_events = core_power->map[stream_index].psr_events; + return true; +} + +bool mod_power_psr_set_sink_vtotal_in_psr_active(struct mod_power *mod_power, + const struct dc_stream_state *stream, + uint16_t psr_vtotal_idle, + uint16_t psr_vtotal_su) +{ + struct core_power *core_power = NULL; + unsigned int stream_index = 0; + const struct dc_link *link = NULL; + + if (!stream) + return false; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + stream_index = map_index_from_stream(core_power, stream); + + if (!core_power->map[stream_index].caps->psr_version) + return false; + + link = dc_stream_get_link(stream); + + return link->dc->link_srv->edp_set_sink_vtotal_in_psr_active( + link, psr_vtotal_idle, psr_vtotal_su); +} + +static bool mod_power_set_replay_active(struct dc_stream_state *stream, + bool replay_active, + bool wait, + bool force_static) +{ + uint64_t state; + unsigned int retry_count; + const unsigned int max_retry = 1000; + struct dc_link *link = NULL; + + if (!stream) + return false; + + link = dc_stream_get_link(stream); + + if (!link) + return false; + + if (!dc_link_set_replay_allow_active(link, &replay_active, false, force_static, NULL)) + return false; + + if (wait == true) { + + for (retry_count = 0; retry_count <= max_retry; retry_count++) { + dc_link_get_replay_state(link, &state); + if (replay_active) { + if (state != REPLAY_STATE_0 && + (!force_static || state == REPLAY_STATE_3)) + break; + } else { + if (state == REPLAY_STATE_0) + break; + } + udelay(500); + } + + /* assert if max retry hit */ + if (retry_count >= max_retry) + ASSERT(0); + } else { + /* To-do: Add trace log */ + } + + return true; +} + +static unsigned int mod_power_replay_setup_power_opt(struct dc_link *link, + unsigned int active_replay_events, bool is_ultra_sleep_mode) +{ + unsigned int power_opt = 0; + + if (is_ultra_sleep_mode) { + /* Static Screen */ + power_opt |= (replay_power_opt_smu_opt_static_screen | replay_power_opt_z10_static_screen); + } else if (active_replay_events & replay_event_test_harness_ultra_sleep) { + power_opt |= replay_power_opt_z10_static_screen; + } + + /* replay_power_opt_flag is a configuration parameter into the module that determines + * which optimizations to enable during replay + */ + power_opt &= link->replay_settings.config.replay_power_opt_supported; + + return power_opt; +} + +static bool mod_power_replay_set_power_opt(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int active_replay_events, + bool is_ultra_sleep_mode) +{ + (void)mod_power; + struct dc_link *link = NULL; + unsigned int power_opt = 0; + + if (!stream) + return false; + + link = dc_stream_get_link(stream); + + if (!link || !link->replay_settings.replay_feature_enabled) + return false; + + power_opt = mod_power_replay_setup_power_opt(link, active_replay_events, is_ultra_sleep_mode); + + if (!dc_link_set_replay_allow_active(link, NULL, false, false, &power_opt)) + return false; + + return true; +} + +bool mod_power_get_replay_event(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int *active_replay_events) +{ + struct core_power *core_power = NULL; + unsigned int stream_index = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + stream_index = map_index_from_stream(core_power, stream); + + *active_replay_events = core_power->map[stream_index].replay_events; + + return true; +} + +static bool mod_power_update_replay_active_status(unsigned int active_replay_events, + struct dc_link *link, uint32_t *coasting_vtotal, bool *is_full_screen_video, bool *is_ultra_sleep_mode, uint16_t *frame_skip_number, bool *is_video_playback) +{ + if (!link || !coasting_vtotal || !is_full_screen_video || !is_video_playback) + return false; + + // Check coasting_vtotal_table has been updated. + if (!link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_STATIC] + || !link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_NOM]) + return false; + + unsigned int replay_enable_option = + link->replay_settings.config.replay_enable_option; + + /* TODO: To support test harness and DDS event */ + + *coasting_vtotal = link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_NOM]; + ASSERT(link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_NOM] <= 0xFFFF); + *frame_skip_number = (uint16_t)link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_NOM]; + + link->replay_settings.config.replay_timing_sync_supported = false; + + *is_full_screen_video = false; + + *is_ultra_sleep_mode = false; + + *is_video_playback = false; + + /* DSAT test scenario */ + if (active_replay_events & replay_event_test_harness_mode) { + if (link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS]) + *coasting_vtotal = + link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS]; + if (link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS]) { + ASSERT(link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS] <= 0xFFFF); + *frame_skip_number = + (uint16_t)link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS]; + } + + /* During the ultra sleep mode testing, disable the timing sync in short vblank mode */ + if (active_replay_events & (replay_event_test_harness_enable_replay)) { + if ((active_replay_events & replay_event_test_harness_ultra_sleep) && + !link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode) + link->replay_settings.config.replay_timing_sync_supported = false; + return true; + } else + return false; + } else if (active_replay_events & (replay_event_test_harness_enable_replay)) { + if (link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS]) + *coasting_vtotal = link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS]; + if (link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS]) { + uint32_t frame_skip_val = + link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS]; + + ASSERT(frame_skip_val <= 0xFFFF); + *frame_skip_number = (uint16_t)frame_skip_val; + } + + /* During the ultra sleep mode testing, disable the timing sync in short vblank mode */ + if ((active_replay_events & replay_event_test_harness_ultra_sleep) && + !link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode) + link->replay_settings.config.replay_timing_sync_supported = false; + return true; + } else if (active_replay_events & (replay_event_test_harness_disable_replay | replay_event_os_request_disable)) { + // set last set coasting vtotal + if (link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS]) + *coasting_vtotal = link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS]; + if (link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS]) { + uint32_t frame_skip_val = + link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS]; + + ASSERT(frame_skip_val <= 0xFFFF); + *frame_skip_number = (uint16_t)frame_skip_val; + } + return false; + } + + /* Inactive conditions */ + if (active_replay_events & (replay_event_edp_panel_off_disable_psr | + replay_event_hw_programming | + replay_event_vrr | + replay_event_immediate_flip | + replay_event_prepare_vtotal | + replay_event_vrr_transition | + replay_event_pause | + replay_event_disable_replay_while_DPMS | + replay_event_sleep_resume | + replay_event_disable_in_AC | + replay_event_disable_replay_while_detect_display | + replay_event_infopacket | + replay_event_crc_window_active)) + return false; + + // Full screen scenario + if (active_replay_events & replay_event_full_screen) { + if (!(replay_enable_option & pr_enable_option_full_screen)) + return false; + } + + /* Full screen video scenario */ + if (active_replay_events & replay_event_big_screen_video) { + + link->replay_settings.config.replay_timing_sync_supported = false; + + if (replay_enable_option & pr_enable_option_full_screen_video_coasting) { + unsigned int fsn_vid = + link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_FULL_SCREEN_VIDEO]; + + *coasting_vtotal = + link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_FULL_SCREEN_VIDEO]; + ASSERT(fsn_vid <= 0xFFFF); + *frame_skip_number = (uint16_t)fsn_vid; + } + + *is_video_playback = true; + + if ((replay_enable_option & pr_enable_option_full_screen_video) && + (replay_enable_option & pr_enable_option_full_screen_video_coasting)) { + *is_full_screen_video = true; + return true; + } else + return false; + } + + /* MPO video scenario + * Some of the cases may contain a full screen UI layer in MPO video scenario which is + * not the expected case to enable Replay. + */ + if ((active_replay_events & replay_event_mpo_video_selective_update) && + !(active_replay_events & replay_event_full_screen)) { + + link->replay_settings.config.replay_timing_sync_supported = false; + + if (replay_enable_option & pr_enable_option_mpo_video_coasting) { + *coasting_vtotal = link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_NOM]; + { + uint32_t frame_skip_val = + link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_NOM]; + + ASSERT(frame_skip_val <= 0xFFFF); + *frame_skip_number = (uint16_t)frame_skip_val; + } + } + + *is_video_playback = true; + + if (replay_enable_option & pr_enable_option_mpo_video) + return true; + else + return false; + } + + /* Static screen scenario */ + if (!(active_replay_events & replay_event_vsync)) { + + if (replay_enable_option & pr_enable_option_static_screen_coasting) { + // Do not adjust eDP refresh rate if static screen + normal sleep mode + if ((!(link->replay_settings.config.replay_power_opt_supported & + replay_power_opt_z10_static_screen)) || + (active_replay_events & replay_event_cursor_updating)) { + // normal sleep mode + *coasting_vtotal = + link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_NOM]; + { + uint32_t frame_skip_val = + link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_NOM]; + + ASSERT(frame_skip_val <= 0xFFFF); + *frame_skip_number = (uint16_t)frame_skip_val; + } + } else { + // ultra sleep mode + *coasting_vtotal = + link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_STATIC]; + { + uint32_t frame_skip_val = + link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_STATIC]; + + ASSERT(frame_skip_val <= 0xFFFF); + *frame_skip_number = (uint16_t)frame_skip_val; + } + *is_ultra_sleep_mode = true; + } + } + + if (replay_enable_option & pr_enable_option_static_screen) { + if (!link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode) + link->replay_settings.config.replay_timing_sync_supported = false; + return true; + } else + return false; + } + + /* General UI scenario */ + if (active_replay_events & replay_event_general_ui) { + if (replay_enable_option & pr_enable_option_general_ui) + return true; + else + return false; + } + + return false; +} + +bool mod_power_replay_set_coasting_vtotal(struct mod_power *mod_power, + const struct dc_stream_state *stream, + uint32_t coasting_vtotal, + uint16_t frame_skip_number) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + + if (!stream) + return false; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return false; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + return link->dc->link_srv->edp_set_coasting_vtotal(link, coasting_vtotal, frame_skip_number); +} + +void mod_power_replay_set_timing_sync_supported(struct mod_power *mod_power, + const struct dc_stream_state *stream) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + unsigned int stream_index = 0; + union dmub_replay_cmd_set cmd_data = { 0 }; + + if (!stream || mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + if (core_power->num_entities == 0) + return; + + stream_index = map_index_from_stream(core_power, stream); + if (stream_index > core_power->num_entities) //invalid index + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + cmd_data.sync_data.timing_sync_supported = link->replay_settings.config.replay_timing_sync_supported; + + link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_Timing_Sync_Supported, + &cmd_data); +} + +void mod_power_replay_disabled_adaptive_sync_sdp(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool force_disabled) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + unsigned int stream_index = 0; + union dmub_replay_cmd_set cmd_data = { 0 }; + + if (!stream || mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + if (core_power->num_entities == 0) + return; + + stream_index = map_index_from_stream(core_power, stream); + if (stream_index > core_power->num_entities) //invalid index + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + cmd_data.disabled_adaptive_sync_sdp_data.force_disabled = force_disabled; + + link->dc->link_srv->edp_send_replay_cmd(link, Replay_Disabled_Adaptive_Sync_SDP, + &cmd_data); +} + +static void mod_power_replay_set_general_cmd(struct mod_power *mod_power, + const struct dc_stream_state *stream, + const enum dmub_cmd_replay_general_subtype general_cmd_type, + const uint32_t param1, const uint32_t param2) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + unsigned int stream_index = 0; + union dmub_replay_cmd_set cmd_data = { 0 }; + + if (!stream || mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + if (core_power->num_entities == 0) + return; + + stream_index = map_index_from_stream(core_power, stream); + if (stream_index > core_power->num_entities) //invalid index + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + cmd_data.set_general_cmd_data.subtype = general_cmd_type; + cmd_data.set_general_cmd_data.param1 = param1; + cmd_data.set_general_cmd_data.param2 = param2; + link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_General_Cmd, + &cmd_data); +} + +void mod_power_replay_disabled_desync_error_detection(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool force_disabled) +{ + mod_power_replay_set_general_cmd(mod_power, stream, + REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, + force_disabled, 0); +} + +static void mod_power_replay_set_pseudo_vtotal(struct mod_power *mod_power, + const struct dc_stream_state *stream, uint16_t vtotal) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + unsigned int stream_index = 0; + union dmub_replay_cmd_set cmd_data = { 0 }; + + if (!stream || mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + if (core_power->num_entities == 0) + return; + + stream_index = map_index_from_stream(core_power, stream); + if (stream_index > core_power->num_entities) //invalid index + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + cmd_data.pseudo_vtotal_data.vtotal = vtotal; + + if (link->replay_settings.last_pseudo_vtotal != vtotal) { + link->replay_settings.last_pseudo_vtotal = vtotal; + link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_Pseudo_VTotal, &cmd_data); + } +} + +static void mod_power_update_error_status(struct mod_power *mod_power, + const struct dc_stream_state *stream) +{ + struct dc_link *link = NULL; + union replay_debug_flags *pDebug = NULL; + + if (mod_power == NULL || stream == NULL) + return; + + link = dc_stream_get_link(stream); + + if (!link) + return; + + pDebug = (union replay_debug_flags *)&link->replay_settings.config.debug_flags; + + if (0 == pDebug->bitfields.enable_visual_confirm_debug) + return; + + mod_power_replay_set_general_cmd(mod_power, stream, + REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, + link->replay_settings.config.replay_error_status.raw, 0); +} + +void mod_power_set_low_rr_activate(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool low_rr_supported) +{ + struct dc_link *link = NULL; + + if (mod_power == NULL || stream == NULL) + return; + + link = dc_stream_get_link(stream); + + if (!link) + return; + + mod_power_replay_set_general_cmd(mod_power, stream, + REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, + low_rr_supported, 0); +} + +void mod_power_set_video_conferencing_activate(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool video_conferencing_activate) +{ + struct dc_link *link = NULL; + + if (mod_power == NULL || stream == NULL) + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + mod_power_replay_set_general_cmd(mod_power, stream, + REPLAY_GENERAL_CMD_VIDEO_CONFERENCING, + video_conferencing_activate, 0); +} + +void mod_power_set_coasting_vtotal_without_frame_update(struct mod_power *mod_power, + const struct dc_stream_state *stream, uint32_t coasting_vtotal) +{ + struct dc_link *link = NULL; + + if (mod_power == NULL || stream == NULL) + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + mod_power_replay_set_general_cmd(mod_power, stream, + REPLAY_GENERAL_CMD_SET_COASTING_VTOTAL_WITHOUT_FRAME_UPDATE, + coasting_vtotal, 0); +} + +void mod_power_set_replay_continuously_resync(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool enable) +{ + struct dc_link *link = NULL; + + if (mod_power == NULL || stream == NULL) + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + mod_power_replay_set_general_cmd(mod_power, stream, + REPLAY_GENERAL_CMD_SET_CONTINUOUSLY_RESYNC, + enable, 0); +} + +void mod_power_set_live_capture_with_cvt_activate(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool live_capture_with_cvt_activate) +{ + struct dc_link *link = NULL; + + if (mod_power == NULL || stream == NULL) + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + // Check if LIVE_CAPTURE_WITH_CVT bit is enabled in DalRegKey_ReplayOptimization + if (!link->replay_settings.config.replay_optimization.bits.LIVE_CAPTURE_WITH_CVT) + return; + + if (link->replay_settings.config.live_capture_with_cvt_activated != live_capture_with_cvt_activate) { + link->replay_settings.config.live_capture_with_cvt_activated = live_capture_with_cvt_activate; + mod_power_replay_set_general_cmd(mod_power, stream, + REPLAY_GENERAL_CMD_LIVE_CAPTURE_WITH_CVT, + live_capture_with_cvt_activate, 0); + } +} + +bool mod_power_set_replay_event(struct mod_power *mod_power, + struct dc_stream_state *stream, bool set_event, + enum replay_event event, bool wait_for_disable) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + unsigned int stream_index = 0; + unsigned int active_replay_events = 0; + bool replay_active_request = false; + bool force_static = false; + uint32_t coasting_vtotal = 0; + bool current_timing_sync_status = false; + bool is_full_screen_video = false; + bool is_ultra_sleep_mode = false; + unsigned int sink_duration_us = 0; + bool low_rr_active = false; + uint16_t frame_skip_number = 0; + bool is_video_playback = false; + + if (!stream) + return false; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + stream_index = map_index_from_stream(core_power, stream); + + if (set_event) + core_power->map[stream_index].replay_events |= event; + else + core_power->map[stream_index].replay_events &= ~event; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return false; + + if ((core_power->map[stream_index].replay_events & replay_event_disable_replay_while_switching_mux) != 0) + return false; + + if ((core_power->map[stream_index].replay_events & replay_event_os_override_hold) != 0) + return false; + + active_replay_events = core_power->map[stream_index].replay_events; + + current_timing_sync_status = + link->replay_settings.config.replay_timing_sync_supported; + + replay_active_request = mod_power_update_replay_active_status(active_replay_events, + link, &coasting_vtotal, &is_full_screen_video, &is_ultra_sleep_mode, &frame_skip_number, &is_video_playback); + + if (is_full_screen_video) + mod_power_replay_set_pseudo_vtotal(mod_power, stream, + link->replay_settings.low_rr_full_screen_video_pseudo_vtotal); + else + mod_power_replay_set_pseudo_vtotal(mod_power, stream, 0); + + //If timing_sync_status change, then re-enabled set timing_sync_supported value and re-enabled replay + if (current_timing_sync_status != link->replay_settings.config.replay_timing_sync_supported) + mod_power_replay_set_timing_sync_supported(mod_power, stream); + + if (link->replay_settings.config.low_rr_supported) { + sink_duration_us = + (unsigned int)(div_u64(((unsigned long long)(coasting_vtotal) + * 10000) * stream->timing.h_total, + stream->timing.pix_clk_100hz)); + low_rr_active = sink_duration_us < LOW_REFRESH_RATE_DURATION_US_UPPER_BOUND ? false : true; + if (low_rr_active != link->replay_settings.config.low_rr_activated) { + mod_power_set_low_rr_activate(mod_power, stream, low_rr_active); + link->replay_settings.config.low_rr_activated = low_rr_active; + } + } + + // The function return fail when + // 1. DMUB function is not support (for backward compatible). + // 2. active_replay_events or coasting_vtotal is not updated in the same time + if (!mod_power_replay_set_power_opt_and_coasting_vtotal(mod_power, + stream, active_replay_events, coasting_vtotal, is_ultra_sleep_mode, frame_skip_number)) { + if (!mod_power_replay_set_power_opt(mod_power, stream, active_replay_events, is_ultra_sleep_mode)) + return false; + + if (!mod_power_replay_set_coasting_vtotal(mod_power, stream, coasting_vtotal, frame_skip_number)) + return false; + } + + mod_power_set_live_capture_with_cvt_activate(mod_power, stream, is_video_playback); + + mod_power_update_error_status(mod_power, stream); + + // If Replay is going to be enable (No matter is disable -> enable or enable -> enable), we don't need to wait. + // If Replay is going to be disable + // if disable -> disable + // -> Replay DMUB state should be state 0. + // So no matter wait_for_disable is true or not, it should makes no difference. + // if enable -> disable -> We should wait if wait_for_disable is true. + if (replay_active_request) + wait_for_disable = false; + + if (!mod_power_set_replay_active(stream, replay_active_request, wait_for_disable, force_static)) + return false; + + return true; +} + +bool mod_power_get_replay_active_status(const struct dc_stream_state *stream, + bool *replay_active) +{ + const struct dc_link *link = NULL; + + if (!stream) + return false; + + link = dc_stream_get_link(stream); + *replay_active = link->replay_settings.replay_allow_active; + + return true; +} + +void mod_power_replay_residency(const struct dc_stream_state *stream, + unsigned int *residency, const bool is_start, const bool is_alpm) +{ + const struct dc_link *link = NULL; + enum pr_residency_mode mode; + + if (!stream) + return; + + link = dc_stream_get_link(stream); + + if (is_alpm) + mode = PR_RESIDENCY_MODE_ALPM; + else + mode = PR_RESIDENCY_MODE_PHY; + + if (link && link->dc && link->dc->link_srv) + link->dc->link_srv->edp_replay_residency(link, residency, is_start, mode); +} + +bool mod_power_replay_set_power_opt_and_coasting_vtotal(struct mod_power *mod_power, + const struct dc_stream_state *stream, unsigned int active_replay_events, uint32_t coasting_vtotal, + bool is_ultra_sleep_mode, uint16_t frame_skip_number) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + unsigned int power_opt = 0; + + if (!stream) + return false; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + link = dc_stream_get_link(stream); + + if (!link || !link->replay_settings.replay_feature_enabled) + return false; + + power_opt = mod_power_replay_setup_power_opt(link, active_replay_events, is_ultra_sleep_mode); + + return link->dc->link_srv->edp_set_replay_power_opt_and_coasting_vtotal(link, &power_opt, coasting_vtotal, frame_skip_number); +} + + + + + diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c index 5d444e9eb38f..f8b763db9b8c 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c @@ -647,12 +647,12 @@ static void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram unsigned int set = params.set; ram_table->flags = 0x0; - ram_table->min_abm_backlight = (big_endian) ? + ram_table->min_abm_backlight = (uint16_t)((big_endian) ? cpu_to_be16(params.min_abm_backlight) : - cpu_to_le16(params.min_abm_backlight); + cpu_to_le16(params.min_abm_backlight)); for (i = 0; i < NUM_AGGR_LEVEL; i++) { - ram_table->hybrid_factor[i] = abm_settings[set][i].brightness_gain; + ram_table->hybrid_factor[i] = (uint8_t)abm_settings[set][i].brightness_gain; ram_table->contrast_factor[i] = abm_settings[set][i].contrast_factor; ram_table->deviation_gain[i] = abm_settings[set][i].deviation_gain; ram_table->min_knee[i] = abm_settings[set][i].min_knee; @@ -960,8 +960,8 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link, struct dc_stream_state *stream, struct psr_config *config) { - uint16_t pic_height; - uint16_t slice_height; + uint32_t pic_height; + uint32_t slice_height; config->dsc_slice_height = 0; if (!(link->connector_signal & SIGNAL_TYPE_EDP) || @@ -978,7 +978,7 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link, return false; slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v; - config->dsc_slice_height = slice_height; + config->dsc_slice_height = (uint16_t)slice_height; if (slice_height) { if (config->su_y_granularity && @@ -1056,7 +1056,7 @@ void set_replay_low_rr_full_screen_video_src_vtotal(struct dc_link *link, uint16 void calculate_replay_link_off_frame_count(struct dc_link *link, uint16_t vtotal, uint16_t htotal) { - uint8_t max_link_off_frame_count = 0; + uint32_t max_link_off_frame_count = 0; uint16_t max_deviation_line = 0, pixel_deviation_per_line = 0; if (!link || link->replay_settings.config.replay_version != DC_FREESYNC_REPLAY) @@ -1093,7 +1093,7 @@ bool fill_custom_backlight_caps(unsigned int config_no, struct dm_acpi_atif_back caps->dc_level_percentage = custom_backlight_profiles[config_no].dc_level_percentage; caps->min_input_signal = custom_backlight_profiles[config_no].min_input_signal; caps->max_input_signal = custom_backlight_profiles[config_no].max_input_signal; - caps->num_data_points = custom_backlight_profiles[config_no].num_data_points; + caps->num_data_points = (uint8_t)custom_backlight_profiles[config_no].num_data_points; memcpy(caps->data_points, custom_backlight_profiles[config_no].data_points, data_points_size); return true; } diff --git a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c b/drivers/gpu/drm/amd/display/modules/vmid/vmid.c index 179b505f7777..32617893ffb2 100644 --- a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c +++ b/drivers/gpu/drm/amd/display/modules/vmid/vmid.c @@ -56,7 +56,7 @@ static void clear_entry_from_vmid_table(struct core_vmid *core_vmid, unsigned in static void evict_vmids(struct core_vmid *core_vmid) { - int i; + unsigned int i; int ord_int = dc_get_vmid_use_vector(core_vmid->dc); ASSERT(ord_int >= 0 && ord_int <= 0xFFFF); @@ -72,7 +72,7 @@ static void evict_vmids(struct core_vmid *core_vmid) // Return value of -1 indicates vmid table uninitialized or ptb dne in the table static int get_existing_vmid_for_ptb(struct core_vmid *core_vmid, uint64_t ptb) { - int i; + unsigned int i; for (i = 0; i < core_vmid->num_vmid; i++) { if (core_vmid->ptb_assigned_to_vmid[i] == ptb) @@ -85,7 +85,7 @@ static int get_existing_vmid_for_ptb(struct core_vmid *core_vmid, uint64_t ptb) // Expected to be called only when there's an available vmid static int get_next_available_vmid(struct core_vmid *core_vmid) { - int i; + unsigned int i; for (i = 1; i < core_vmid->num_vmid; i++) { if (core_vmid->ptb_assigned_to_vmid[i] == 0) diff --git a/drivers/gpu/drm/amd/include/amd_cper.h b/drivers/gpu/drm/amd/include/amd_cper.h index a252ee4c7874..baa0f30b9c4d 100644 --- a/drivers/gpu/drm/amd/include/amd_cper.h +++ b/drivers/gpu/drm/amd/include/amd_cper.h @@ -58,7 +58,7 @@ enum cper_error_severity { CPER_SEV_NON_FATAL_UNCORRECTED = 0, - CPER_SEV_FATAL = 1, + CPER_SEV_FATAL_UNCORRECTED = 1, CPER_SEV_NON_FATAL_CORRECTED = 2, CPER_SEV_NUM = 3, diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h index d6a2839b4682..025e5490e6f1 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h @@ -5475,6 +5475,14 @@ #define regCHA_PERFCOUNTER3_HI_BASE_IDX 1 +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_perfddec +// base address: 0x34000 +#define regGC_CANE_PERFCOUNTER0_LO 0x36c0 +#define regGC_CANE_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGC_CANE_PERFCOUNTER0_HI 0x36c1 +#define regGC_CANE_PERFCOUNTER0_HI_BASE_IDX 1 + + // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_perfsdec // base address: 0x36000 #define regCPG_PERFCOUNTER1_SELECT 0x3800 @@ -5761,6 +5769,16 @@ #define regCHA_PERFCOUNTER3_SELECT1_BASE_IDX 1 +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_perfsdec +// base address: 0x36000 +#define regGC_CANE_PERFCOUNTER0_SELECT 0x3e80 +#define regGC_CANE_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGC_CANE_PERFCOUNTER0_SELECT1 0x3e81 +#define regGC_CANE_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGC_CANE_PERFCOUNTER0_MODE 0x3e82 +#define regGC_CANE_PERFCOUNTER0_MODE_BASE_IDX 1 + + // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gdfll_xvmin_xvmin_xvmin_reg_blk // base address: 0x3a014 #define regXVMIN_XVMIN_WR_DATA 0x4806 @@ -12080,6 +12098,22 @@ #define regGC_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2ffbmprdec +// base address: 0x353d0 +#define regGCUTCL2_FFBM_PERFCOUNTER_LO 0x34f4 +#define regGCUTCL2_FFBM_PERFCOUNTER_LO_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER_HI 0x34f5 +#define regGCUTCL2_FFBM_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2nhttlbprdec +// base address: 0x353e0 +#define regGCUTCL2_NHTTLB_PERFCOUNTER_LO 0x34f8 +#define regGCUTCL2_NHTTLB_PERFCOUNTER_LO_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER_HI 0x34f9 +#define regGCUTCL2_NHTTLB_PERFCOUNTER_HI_BASE_IDX 1 + + // addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbprdec // base address: 0x353f0 #define regGC_L2TLB_PERFCOUNTER_LO 0x34fc @@ -12176,6 +12210,82 @@ #define regGC_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2ffbmpldec +// base address: 0x37bb0 +#define regGCUTCL2_FFBM_PERFCOUNTER0_CFG 0x3eec +#define regGCUTCL2_FFBM_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER1_CFG 0x3eed +#define regGCUTCL2_FFBM_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER2_CFG 0x3eee +#define regGCUTCL2_FFBM_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER3_CFG 0x3eef +#define regGCUTCL2_FFBM_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER4_CFG 0x3ef0 +#define regGCUTCL2_FFBM_PERFCOUNTER4_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER5_CFG 0x3ef1 +#define regGCUTCL2_FFBM_PERFCOUNTER5_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER6_CFG 0x3ef2 +#define regGCUTCL2_FFBM_PERFCOUNTER6_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER7_CFG 0x3ef3 +#define regGCUTCL2_FFBM_PERFCOUNTER7_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER8_CFG 0x3ef4 +#define regGCUTCL2_FFBM_PERFCOUNTER8_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER9_CFG 0x3ef5 +#define regGCUTCL2_FFBM_PERFCOUNTER9_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER10_CFG 0x3ef6 +#define regGCUTCL2_FFBM_PERFCOUNTER10_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER11_CFG 0x3ef7 +#define regGCUTCL2_FFBM_PERFCOUNTER11_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER12_CFG 0x3ef8 +#define regGCUTCL2_FFBM_PERFCOUNTER12_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER13_CFG 0x3ef9 +#define regGCUTCL2_FFBM_PERFCOUNTER13_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER14_CFG 0x3efa +#define regGCUTCL2_FFBM_PERFCOUNTER14_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER15_CFG 0x3efb +#define regGCUTCL2_FFBM_PERFCOUNTER15_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL 0x3efc +#define regGCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2nhttlbpldec +// base address: 0x37c00 +#define regGCUTCL2_NHTTLB_PERFCOUNTER0_CFG 0x3f00 +#define regGCUTCL2_NHTTLB_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER1_CFG 0x3f01 +#define regGCUTCL2_NHTTLB_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER2_CFG 0x3f02 +#define regGCUTCL2_NHTTLB_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER3_CFG 0x3f03 +#define regGCUTCL2_NHTTLB_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER4_CFG 0x3f04 +#define regGCUTCL2_NHTTLB_PERFCOUNTER4_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER5_CFG 0x3f05 +#define regGCUTCL2_NHTTLB_PERFCOUNTER5_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER6_CFG 0x3f06 +#define regGCUTCL2_NHTTLB_PERFCOUNTER6_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER7_CFG 0x3f07 +#define regGCUTCL2_NHTTLB_PERFCOUNTER7_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER8_CFG 0x3f08 +#define regGCUTCL2_NHTTLB_PERFCOUNTER8_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER9_CFG 0x3f09 +#define regGCUTCL2_NHTTLB_PERFCOUNTER9_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER10_CFG 0x3f0a +#define regGCUTCL2_NHTTLB_PERFCOUNTER10_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER11_CFG 0x3f0b +#define regGCUTCL2_NHTTLB_PERFCOUNTER11_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER12_CFG 0x3f0c +#define regGCUTCL2_NHTTLB_PERFCOUNTER12_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER13_CFG 0x3f0d +#define regGCUTCL2_NHTTLB_PERFCOUNTER13_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER14_CFG 0x3f0e +#define regGCUTCL2_NHTTLB_PERFCOUNTER14_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER15_CFG 0x3f0f +#define regGCUTCL2_NHTTLB_PERFCOUNTER15_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL 0x3f10 +#define regGCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + // addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpldec // base address: 0x37c50 #define regGC_L2TLB_PERFCOUNTER0_CFG 0x3f14 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h index f606c5cd03c5..1cf890de35cb 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h @@ -16951,6 +16951,15 @@ #define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_perfddec +//GC_CANE_PERFCOUNTER0_LO +#define GC_CANE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GC_CANE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GC_CANE_PERFCOUNTER0_HI +#define GC_CANE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GC_CANE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_perfsdec //CPG_PERFCOUNTER1_SELECT #define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 @@ -18123,6 +18132,46 @@ #define CHA_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_perfsdec +//GC_CANE_PERFCOUNTER0_SELECT +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GC_CANE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GC_CANE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GC_CANE_PERFCOUNTER0_SELECT1 +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GC_CANE_PERFCOUNTER0_MODE +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE0__SHIFT 0x0 +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE1__SHIFT 0x2 +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE2__SHIFT 0x4 +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE3__SHIFT 0x6 +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE0__SHIFT 0x8 +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE1__SHIFT 0xc +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE2__SHIFT 0x10 +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE3__SHIFT 0x14 +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE0_MASK 0x00000003L +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE1_MASK 0x0000000CL +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE2_MASK 0x00000030L +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE3_MASK 0x000000C0L +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE0_MASK 0x00000F00L +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE1_MASK 0x0000F000L +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE2_MASK 0x000F0000L +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE3_MASK 0x00F00000L + + // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gdfll_xvmin_xvmin_xvmin_reg_blk //XVMIN_XVMIN_WR_DATA #define XVMIN_XVMIN_WR_DATA__XVMINDATA__SHIFT 0x0 @@ -43203,6 +43252,28 @@ #define GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2ffbmprdec +//GCUTCL2_FFBM_PERFCOUNTER_LO +#define GCUTCL2_FFBM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GCUTCL2_FFBM_PERFCOUNTER_HI +#define GCUTCL2_FFBM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GCUTCL2_FFBM_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GCUTCL2_FFBM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2nhttlbprdec +//GCUTCL2_NHTTLB_PERFCOUNTER_LO +#define GCUTCL2_NHTTLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GCUTCL2_NHTTLB_PERFCOUNTER_HI +#define GCUTCL2_NHTTLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GCUTCL2_NHTTLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GCUTCL2_NHTTLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + // addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbprdec //GC_L2TLB_PERFCOUNTER_LO #define GC_L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 @@ -43660,6 +43731,390 @@ #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2ffbmpldec +//GCUTCL2_FFBM_PERFCOUNTER0_CFG +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER1_CFG +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER2_CFG +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER3_CFG +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER4_CFG +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER5_CFG +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER6_CFG +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER7_CFG +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER8_CFG +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER9_CFG +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER10_CFG +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER11_CFG +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER12_CFG +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER13_CFG +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER14_CFG +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER15_CFG +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2nhttlbpldec +//GCUTCL2_NHTTLB_PERFCOUNTER0_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER1_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER2_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER3_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER4_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER5_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER6_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER7_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER8_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER9_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER10_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER11_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER12_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER13_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER14_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER15_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + // addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpldec //GC_L2TLB_PERFCOUNTER0_CFG #define GC_L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_offset.h new file mode 100755 index 000000000000..f10e6168ad54 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_offset.h @@ -0,0 +1,149 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_12_1_1_OFFSET_HEADER +#define _gc_12_1_1_OFFSET_HEADER + + + +// addressBlock: aigc_grbma_grbma_grbmadec +// base address: 0x18000 +#define regGRBMA_GFX_INDEX 0x0011 +#define regGRBMA_GFX_INDEX_BASE_IDX 1 + + +// addressBlock: aigc_grbma_grbma_perfddec +// base address: 0x19200 +#define regGRBMA_PERFCOUNTER0_LO 0x0480 +#define regGRBMA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGRBMA_PERFCOUNTER0_HI 0x0481 +#define regGRBMA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGRBMA_PERFCOUNTER1_LO 0x0482 +#define regGRBMA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGRBMA_PERFCOUNTER1_HI 0x0483 +#define regGRBMA_PERFCOUNTER1_HI_BASE_IDX 1 + + +// addressBlock: aigc_grbma_grbma_perfsdec +// base address: 0x19300 +#define regGRBMA_PERFCOUNTER0_SELECT 0x04c0 +#define regGRBMA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGRBMA_PERFCOUNTER1_SELECT 0x04c1 +#define regGRBMA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regAID_PERFMON_CNTL 0x04c2 +#define regAID_PERFMON_CNTL_BASE_IDX 1 + + +// addressBlock: aigc_gl2x_gfx_se_perfsdec +// base address: 0x19300 +#define regGL2C_PERFCOUNTER0_SELECT 0x04e8 +#define regGL2C_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER0_SELECT1 0x04e9 +#define regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_SELECT 0x04ea +#define regGL2C_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_SELECT1 0x04eb +#define regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL2C_PERFCOUNTER2_SELECT 0x04ec +#define regGL2C_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER2_SELECT1 0x04ed +#define regGL2C_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGL2C_PERFCOUNTER3_SELECT 0x04ee +#define regGL2C_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER3_SELECT1 0x04ef +#define regGL2C_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_SELECT 0x04f0 +#define regGL2A_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_SELECT1 0x04f1 +#define regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_SELECT 0x04f2 +#define regGL2A_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_SELECT1 0x04f3 +#define regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL2A_PERFCOUNTER2_SELECT 0x04f4 +#define regGL2A_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER2_SELECT1 0x04f5 +#define regGL2A_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGL2A_PERFCOUNTER3_SELECT 0x04f6 +#define regGL2A_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER3_SELECT1 0x04f7 +#define regGL2A_PERFCOUNTER3_SELECT1_BASE_IDX 1 + + +// addressBlock: aigc_gl2x_gfx_se_perfddec +// base address: 0x19200 +#define regGL2C_PERFCOUNTER0_LO 0x04a0 +#define regGL2C_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER0_HI 0x04a1 +#define regGL2C_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_LO 0x04a2 +#define regGL2C_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_HI 0x04a3 +#define regGL2C_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL2C_PERFCOUNTER2_LO 0x04a4 +#define regGL2C_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER2_HI 0x04a5 +#define regGL2C_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL2C_PERFCOUNTER3_LO 0x04a6 +#define regGL2C_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER3_HI 0x04a7 +#define regGL2C_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_LO 0x04a8 +#define regGL2A_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_HI 0x04a9 +#define regGL2A_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_LO 0x04aa +#define regGL2A_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_HI 0x04ab +#define regGL2A_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER2_LO 0x04ac +#define regGL2A_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER2_HI 0x04ad +#define regGL2A_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER3_LO 0x04ae +#define regGL2A_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER3_HI 0x04af +#define regGL2A_PERFCOUNTER3_HI_BASE_IDX 1 + + +// addressBlock: aigc_gfx_gcea_se_gfx_se_perfsdec +// base address: 0x19320 +#define regGC_EA_SE_PERFCOUNTER0_SELECT 0x04c8 +#define regGC_EA_SE_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGC_EA_SE_PERFCOUNTER0_SELECT1 0x04c9 +#define regGC_EA_SE_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGC_EA_SE_PERFCOUNTER1_SELECT 0x04ca +#define regGC_EA_SE_PERFCOUNTER1_SELECT_BASE_IDX 1 + + +// addressBlock: aigc_gfx_gcea_se_gfx_se_perfddec +// base address: 0x19240 +#define regGC_EA_SE_PERFCOUNTER0_LO 0x0490 +#define regGC_EA_SE_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGC_EA_SE_PERFCOUNTER0_HI 0x0491 +#define regGC_EA_SE_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGC_EA_SE_PERFCOUNTER1_LO 0x0492 +#define regGC_EA_SE_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGC_EA_SE_PERFCOUNTER1_HI 0x0493 +#define regGC_EA_SE_PERFCOUNTER1_HI_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_sh_mask.h new file mode 100755 index 000000000000..8d09c8150a53 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_sh_mask.h @@ -0,0 +1,377 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_12_1_1_SH_MASK_HEADER +#define _gc_12_1_1_SH_MASK_HEADER + + +// addressBlock: aigc_grbma_grbma_grbmadec +//GRBMA_GFX_INDEX +#define GRBMA_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 +#define GRBMA_GFX_INDEX__SA_INDEX__SHIFT 0x8 +#define GRBMA_GFX_INDEX__SE_INDEX__SHIFT 0x10 +#define GRBMA_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT 0x1d +#define GRBMA_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBMA_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBMA_GFX_INDEX__INSTANCE_INDEX_MASK 0x0000007FL +#define GRBMA_GFX_INDEX__SA_INDEX_MASK 0x00000300L +#define GRBMA_GFX_INDEX__SE_INDEX_MASK 0x000F0000L +#define GRBMA_GFX_INDEX__SA_BROADCAST_WRITES_MASK 0x20000000L +#define GRBMA_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBMA_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L + + +// addressBlock: aigc_grbma_grbma_perfddec +//GRBMA_PERFCOUNTER0_LO +#define GRBMA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBMA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBMA_PERFCOUNTER0_HI +#define GRBMA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBMA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBMA_PERFCOUNTER1_LO +#define GRBMA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBMA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBMA_PERFCOUNTER1_HI +#define GRBMA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBMA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aigc_grbma_grbma_perfsdec +//GRBMA_PERFCOUNTER0_SELECT +#define GRBMA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBMA_PERFCOUNTER0_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x6 +#define GRBMA_PERFCOUNTER0_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT 0x7 +#define GRBMA_PERFCOUNTER0_SELECT__PMR_BUSY_USER_DEFINED_MASK__SHIFT 0x8 +#define GRBMA_PERFCOUNTER0_SELECT__SC_CLEAN_USER_DEFINED_MASK__SHIFT 0x9 +#define GRBMA_PERFCOUNTER0_SELECT__WGS_BUSY_USER_DEFINED_MASK__SHIFT 0xa +#define GRBMA_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBMA_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xc +#define GRBMA_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBMA_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBMA_PERFCOUNTER0_SELECT__GL2C_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBMA_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBMA_PERFCOUNTER0_SELECT__XCAC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBMA_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBMA_PERFCOUNTER0_SELECT__GL2A_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBMA_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBMA_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBMA_PERFCOUNTER0_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBMA_PERFCOUNTER0_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBMA_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBMA_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBMA_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBMA_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBMA_PERFCOUNTER0_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBMA_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBMA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBMA_PERFCOUNTER0_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000040L +#define GRBMA_PERFCOUNTER0_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK_MASK 0x00000080L +#define GRBMA_PERFCOUNTER0_SELECT__PMR_BUSY_USER_DEFINED_MASK_MASK 0x00000100L +#define GRBMA_PERFCOUNTER0_SELECT__SC_CLEAN_USER_DEFINED_MASK_MASK 0x00000200L +#define GRBMA_PERFCOUNTER0_SELECT__WGS_BUSY_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBMA_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBMA_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBMA_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBMA_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBMA_PERFCOUNTER0_SELECT__GL2C_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBMA_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBMA_PERFCOUNTER0_SELECT__XCAC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBMA_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBMA_PERFCOUNTER0_SELECT__GL2A_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBMA_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBMA_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBMA_PERFCOUNTER0_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBMA_PERFCOUNTER0_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBMA_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBMA_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBMA_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBMA_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBMA_PERFCOUNTER0_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBMA_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +//GRBMA_PERFCOUNTER1_SELECT +#define GRBMA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBMA_PERFCOUNTER1_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x6 +#define GRBMA_PERFCOUNTER1_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT 0x7 +#define GRBMA_PERFCOUNTER1_SELECT__PMR_BUSY_USER_DEFINED_MASK__SHIFT 0x8 +#define GRBMA_PERFCOUNTER1_SELECT__SC_CLEAN_USER_DEFINED_MASK__SHIFT 0x9 +#define GRBMA_PERFCOUNTER1_SELECT__WGS_BUSY_USER_DEFINED_MASK__SHIFT 0xa +#define GRBMA_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBMA_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xc +#define GRBMA_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBMA_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBMA_PERFCOUNTER1_SELECT__GL2C_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBMA_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBMA_PERFCOUNTER1_SELECT__XCAC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBMA_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBMA_PERFCOUNTER1_SELECT__GL2A_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBMA_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBMA_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBMA_PERFCOUNTER1_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBMA_PERFCOUNTER1_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBMA_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBMA_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBMA_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBMA_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBMA_PERFCOUNTER1_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBMA_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBMA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBMA_PERFCOUNTER1_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000040L +#define GRBMA_PERFCOUNTER1_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK_MASK 0x00000080L +#define GRBMA_PERFCOUNTER1_SELECT__PMR_BUSY_USER_DEFINED_MASK_MASK 0x00000100L +#define GRBMA_PERFCOUNTER1_SELECT__SC_CLEAN_USER_DEFINED_MASK_MASK 0x00000200L +#define GRBMA_PERFCOUNTER1_SELECT__WGS_BUSY_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBMA_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBMA_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBMA_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBMA_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBMA_PERFCOUNTER1_SELECT__GL2C_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBMA_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBMA_PERFCOUNTER1_SELECT__XCAC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBMA_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBMA_PERFCOUNTER1_SELECT__GL2A_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBMA_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBMA_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBMA_PERFCOUNTER1_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBMA_PERFCOUNTER1_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBMA_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBMA_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBMA_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBMA_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBMA_PERFCOUNTER1_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBMA_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +//AID_PERFMON_CNTL +#define AID_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define AID_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 +#define AID_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define AID_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define AID_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL +#define AID_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L +#define AID_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L +#define AID_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L + + +// addressBlock: aigc_gl2x_gfx_se_perfsdec +//GL2C_PERFCOUNTER0_SELECT +#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2C_PERFCOUNTER0_SELECT1 +#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL2C_PERFCOUNTER1_SELECT +#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2C_PERFCOUNTER1_SELECT1 +#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL2C_PERFCOUNTER2_SELECT +#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2C_PERFCOUNTER2_SELECT1 +#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL2C_PERFCOUNTER3_SELECT +#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2C_PERFCOUNTER3_SELECT1 +#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL2A_PERFCOUNTER0_SELECT +#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2A_PERFCOUNTER0_SELECT1 +#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL2A_PERFCOUNTER1_SELECT +#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2A_PERFCOUNTER1_SELECT1 +#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL2A_PERFCOUNTER2_SELECT +#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2A_PERFCOUNTER2_SELECT1 +#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL2A_PERFCOUNTER3_SELECT +#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2A_PERFCOUNTER3_SELECT1 +#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L + + +// addressBlock: aigc_gfx_gcea_se_gfx_se_perfsdec +//GC_EA_SE_PERFCOUNTER0_SELECT +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GC_EA_SE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GC_EA_SE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GC_EA_SE_PERFCOUNTER0_SELECT1 +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GC_EA_SE_PERFCOUNTER1_SELECT +#define GC_EA_SE_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GC_EA_SE_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT 0x1c +#define GC_EA_SE_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GC_EA_SE_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK 0xF0000000L + + +// addressBlock: aigc_gfx_gcea_se_gfx_se_perfddec +//GC_EA_SE_PERFCOUNTER0_LO +#define GC_EA_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GC_EA_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GC_EA_SE_PERFCOUNTER0_HI +#define GC_EA_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GC_EA_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GC_EA_SE_PERFCOUNTER1_LO +#define GC_EA_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GC_EA_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GC_EA_SE_PERFCOUNTER1_HI +#define GC_EA_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GC_EA_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_offset.h new file mode 100644 index 000000000000..0b42c1c9c848 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_offset.h @@ -0,0 +1,13149 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _nbio_6_3_2_OFFSET_HEADER +#define _nbio_6_3_2_OFFSET_HEADER + + + +// addressBlock: nbif0_nbif0_bif_bx_SYSDEC +// base address: 0x0 +#define regBIF_BX0_SYSHUB_INDEX_OVLP 0x0008 +#define regBIF_BX0_SYSHUB_INDEX_OVLP_BASE_IDX 0 +#define regBIF_BX0_SYSHUB_DATA_OVLP 0x0009 +#define regBIF_BX0_SYSHUB_DATA_OVLP_BASE_IDX 0 +#define regBIF_BX0_SYSHUB_INDEX_HI_OVLP 0x000a +#define regBIF_BX0_SYSHUB_INDEX_HI_OVLP_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX 0x000c +#define regBIF_BX0_PCIE_INDEX_BASE_IDX 0 +#define regBIF_BX0_PCIE_DATA 0x000d +#define regBIF_BX0_PCIE_DATA_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX2 0x000e +#define regBIF_BX0_PCIE_INDEX2_BASE_IDX 0 +#define regBIF_BX0_PCIE_DATA2 0x000f +#define regBIF_BX0_PCIE_DATA2_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX_HI 0x0010 +#define regBIF_BX0_PCIE_INDEX_HI_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX2_HI 0x0011 +#define regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX 0 +#define regBIF_BX0_SBIOS_SCRATCH_0 0x0034 +#define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_1 0x0035 +#define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_2 0x0036 +#define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_3 0x0037 +#define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_0 0x0038 +#define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_1 0x0039 +#define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_2 0x003a +#define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_3 0x003b +#define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_4 0x003c +#define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_5 0x003d +#define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_6 0x003e +#define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_7 0x003f +#define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_8 0x0040 +#define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_9 0x0041 +#define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_10 0x0042 +#define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_11 0x0043 +#define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_12 0x0044 +#define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_13 0x0045 +#define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_14 0x0046 +#define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_15 0x0047 +#define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_BIF_RLC_INTR_CNTL 0x004c +#define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_BIF_VCE_INTR_CNTL 0x004d +#define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_BIF_UVD_INTR_CNTL 0x004e +#define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_BIF_Engine_INTR_CNTL 0x004f +#define regBIF_BX0_BIF_Engine_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 0x006c +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 0x006d +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 0x006e +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 0x006f +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 0x0070 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 0x0072 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 0x0074 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 0x0076 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 0x0078 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 0x007a +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 0x007b +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL 0x007c +#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL 0x007d +#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL 0x007e +#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f +#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_0 0x0080 +#define regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_1 0x0081 +#define regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_2 0x0082 +#define regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_3 0x0083 +#define regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_4 0x0084 +#define regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_5 0x0085 +#define regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_6 0x0086 +#define regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_7 0x0087 +#define regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_8 0x0088 +#define regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_9 0x0089 +#define regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_10 0x008a +#define regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_11 0x008b +#define regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_12 0x008c +#define regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_13 0x008d +#define regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_14 0x008e +#define regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_15 0x008f +#define regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_0 0x0090 +#define regBIF_BX0_FW_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_1 0x0091 +#define regBIF_BX0_FW_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_2 0x0092 +#define regBIF_BX0_FW_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_3 0x0093 +#define regBIF_BX0_FW_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_4 0x0094 +#define regBIF_BX0_FW_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_5 0x0095 +#define regBIF_BX0_FW_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_6 0x0096 +#define regBIF_BX0_FW_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_7 0x0097 +#define regBIF_BX0_FW_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_8 0x0098 +#define regBIF_BX0_FW_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_9 0x0099 +#define regBIF_BX0_FW_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_10 0x009a +#define regBIF_BX0_FW_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_11 0x009b +#define regBIF_BX0_FW_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_12 0x009c +#define regBIF_BX0_FW_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_13 0x009d +#define regBIF_BX0_FW_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_14 0x009e +#define regBIF_BX0_FW_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_15 0x009f +#define regBIF_BX0_FW_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_4 0x00a0 +#define regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_5 0x00a1 +#define regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_6 0x00a2 +#define regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_7 0x00a3 +#define regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_8 0x00a4 +#define regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_9 0x00a5 +#define regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_10 0x00a6 +#define regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_11 0x00a7 +#define regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_12 0x00a8 +#define regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_13 0x00a9 +#define regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_14 0x00aa +#define regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_15 0x00ab +#define regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX 1 + + +// addressBlock: nbif0_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED 0x0068 +#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH 0x0069 +#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL 0x006b +#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL 0x006c +#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 0x006d +#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL 0x006e +#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL 0x006f +#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 0x0070 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC 0x0071 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 0x0072 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL 0x0074 +#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL 0x0075 +#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL 0x0076 +#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 0x0077 +#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC 0x0078 +#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP 0x0079 +#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH 0x004b +#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_CNTL 0x004d +#define regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL 0x004e +#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS 0x004f +#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 0x0050 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL 0x0051 +#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL 0x0052 +#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x0054 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x0055 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x0055 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x0055 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x0055 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x0056 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x0056 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x0056 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x0056 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC 0x0057 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 0x0058 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP 0x005a +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x005b +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL 0x005b +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x005b +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x005c +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x005c +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x005c +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x005c +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x005d +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x005d +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x005d +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL 0x005d +#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED 0x005e +#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL 0x0060 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID 0x0061 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL 0x0062 +#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL 0x0063 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL 0x0064 +#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3 0x0065 +#define regRCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_PF0_MM_INDEX 0x0000 +#define regBIF_BX_PF0_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_PF0_MM_DATA 0x0001 +#define regBIF_BX_PF0_MM_DATA_BASE_IDX 0 +#define regBIF_BX_PF0_MM_INDEX_HI 0x0006 +#define regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX 0 +#define regBIF_BX_PF0_RSMU_INDEX 0x0000 +#define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX 1 +#define regBIF_BX_PF0_RSMU_DATA 0x0001 +#define regBIF_BX_PF0_RSMU_DATA_BASE_IDX 1 +#define regBIF_BX_PF0_RSMU_INDEX_HI 0x0002 +#define regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX 1 + + +// addressBlock: nbif0_nbif0_bif_bx_BIFDEC1 +// base address: 0x0 +#define regBIF_BX0_CC_BIF_BX_STRAP0 0x00e2 +#define regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX 2 +#define regBIF_BX0_CC_BIF_BX_PINSTRAP0 0x00e4 +#define regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX 2 +#define regBIF_BX0_BIF_MM_INDACCESS_CNTL 0x00e6 +#define regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BUS_CNTL 0x00e7 +#define regBIF_BX0_BUS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_SCRATCH0 0x00e8 +#define regBIF_BX0_BIF_SCRATCH0_BASE_IDX 2 +#define regBIF_BX0_BIF_SCRATCH1 0x00e9 +#define regBIF_BX0_BIF_SCRATCH1_BASE_IDX 2 +#define regBIF_BX0_BX_RESET_EN 0x00ed +#define regBIF_BX0_BX_RESET_EN_BASE_IDX 2 +#define regBIF_BX0_MM_CFGREGS_CNTL 0x00ee +#define regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BX_RESET_CNTL 0x00f0 +#define regBIF_BX0_BX_RESET_CNTL_BASE_IDX 2 +#define regBIF_BX0_INTERRUPT_CNTL 0x00f1 +#define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX 2 +#define regBIF_BX0_INTERRUPT_CNTL2 0x00f2 +#define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX 2 +#define regBIF_BX0_CLKREQB_PAD_CNTL 0x00f8 +#define regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC 0x00fb +#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC 0x00fc +#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 2 +#define regBIF_BX0_BIF_DOORBELL_CNTL 0x00fd +#define regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_DOORBELL_INT_CNTL 0x00fe +#define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_FB_EN 0x0100 +#define regBIF_BX0_BIF_FB_EN_BASE_IDX 2 +#define regBIF_BX0_BIF_INTR_CNTL 0x0101 +#define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF 0x0109 +#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX 2 +#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF 0x010a +#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 +#define regBIF_BX0_BACO_CNTL 0x010b +#define regBIF_BX0_BACO_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIME0 0x010c +#define regBIF_BX0_BIF_BACO_EXIT_TIME0_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER1 0x010d +#define regBIF_BX0_BIF_BACO_EXIT_TIMER1_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER2 0x010e +#define regBIF_BX0_BIF_BACO_EXIT_TIMER2_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER3 0x010f +#define regBIF_BX0_BIF_BACO_EXIT_TIMER3_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER4 0x0110 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER4_BASE_IDX 2 +#define regBIF_BX0_MEM_TYPE_CNTL 0x0111 +#define regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL 0x0113 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0 0x0114 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1 0x0115 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2 0x0116 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3 0x0117 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4 0x0118 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5 0x0119 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6 0x011a +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7 0x011b +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8 0x011c +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9 0x011d +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10 0x011e +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11 0x011f +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12 0x0120 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13 0x0121 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14 0x0122 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15 0x0123 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX 2 +#define regBIF_BX0_VF_REGWR_EN 0x0124 +#define regBIF_BX0_VF_REGWR_EN_BASE_IDX 2 +#define regBIF_BX0_VF_DOORBELL_EN 0x0125 +#define regBIF_BX0_VF_DOORBELL_EN_BASE_IDX 2 +#define regBIF_BX0_VF_FB_EN 0x0126 +#define regBIF_BX0_VF_FB_EN_BASE_IDX 2 +#define regBIF_BX0_VF_REGWR_STATUS 0x0127 +#define regBIF_BX0_VF_REGWR_STATUS_BASE_IDX 2 +#define regBIF_BX0_VF_DOORBELL_STATUS 0x0128 +#define regBIF_BX0_VF_DOORBELL_STATUS_BASE_IDX 2 +#define regBIF_BX0_VF_FB_STATUS 0x0129 +#define regBIF_BX0_VF_FB_STATUS_BASE_IDX 2 +#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL 0x012d +#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL 0x012e +#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_CNTL 0x012f +#define regBIF_BX0_BIF_RB_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_BASE 0x0130 +#define regBIF_BX0_BIF_RB_BASE_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_RPTR 0x0131 +#define regBIF_BX0_BIF_RB_RPTR_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR 0x0132 +#define regBIF_BX0_BIF_RB_WPTR_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI 0x0133 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO 0x0134 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX 2 +#define regBIF_BX0_MAILBOX_INDEX 0x0135 +#define regBIF_BX0_MAILBOX_INDEX_BASE_IDX 2 +#define regBIF_BX0_BACO_AZ_ENHANCE_CTRL 0x0141 +#define regBIF_BX0_BACO_AZ_ENHANCE_CTRL_BASE_IDX 2 +#define regBIF_BX0_BIF_MP1_INTR_CTRL 0x0142 +#define regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX 2 +#define regBIF_BX0_BIF_PERSTB_PAD_CNTL 0x0145 +#define regBIF_BX0_BIF_PERSTB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_PX_EN_PAD_CNTL 0x0146 +#define regBIF_BX0_BIF_PX_EN_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL 0x0147 +#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL 0x0148 +#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL 0x0149 +#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE 0x0165 +#define regBIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DEV0_0_RCC_ERR_INT_CNTL 0x0086 +#define regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC 0x0087 +#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_RESET_EN 0x0088 +#define regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_VDM_SUPPORT 0x0089 +#define regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 0x008a +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 0x008b +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_GPUIOV_REGION 0x008c +#define regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN 0x008d +#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL 0x008e +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x008f +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE 0x008f +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0 0x00be +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1 0x00bf +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUS_CNTL 0x00c1 +#define regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_CNTL 0x00c2 +#define regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE 0x00c6 +#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE 0x00c7 +#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE 0x00c8 +#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_XDMA_LO 0x00c9 +#define regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_XDMA_HI 0x00ca +#define regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC 0x00cb +#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1 0x00cc +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_LIST0 0x00cd +#define regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_LIST1 0x00ce +#define regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2 0x00cf +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM 0x00d0 +#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_HOST_BUSNUM 0x00d1 +#define regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI 0x00d2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO 0x00d3 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI 0x00d4 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO 0x00d5 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI 0x00d6 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO 0x00d7 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI 0x00d8 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO 0x00d9 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 0x00da +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 0x00db +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL 0x00dd +#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL 0x00de +#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE 0x00df +#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL 0x00e0 +#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MH_ARB_CNTL 0x00e1 +#define regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_rcc_strap_BIFDEC1 +// base address: 0x0 +#define regRCC_STRAP0_RCC_BIF_STRAP0 0x0000 +#define regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP1 0x0001 +#define regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP10 0x0002 +#define regRCC_STRAP0_RCC_BIF_STRAP10_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP11 0x0003 +#define regRCC_STRAP0_RCC_BIF_STRAP11_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP12 0x0004 +#define regRCC_STRAP0_RCC_BIF_STRAP12_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP13 0x0005 +#define regRCC_STRAP0_RCC_BIF_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP2 0x0006 +#define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP3 0x0007 +#define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP4 0x0008 +#define regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP5 0x0009 +#define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP6 0x000a +#define regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP7 0x000b +#define regRCC_STRAP0_RCC_BIF_STRAP7_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP8 0x000c +#define regRCC_STRAP0_RCC_BIF_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP9 0x000d +#define regRCC_STRAP0_RCC_BIF_STRAP9_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 0x000e +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 0x000f +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10 0x0010 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11 0x0011 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12 0x0012 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13 0x0013 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14 0x0014 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP15 0x0015 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP15_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP16 0x0016 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP16_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP17 0x0017 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP17_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP18 0x0018 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP18_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 0x0019 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 0x001a +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 0x001b +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 0x001c +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 0x001d +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 0x001e +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 0x001f +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 0x0020 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0x0021 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 0x0022 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 0x0023 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 0x0024 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15 0x0025 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16 0x0026 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17 0x0027 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18 0x0028 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP19 0x0029 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP19_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 0x002a +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP22 0x002b +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP22_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP23 0x002c +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP23_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP24 0x002d +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP24_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 0x002e +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 0x002f +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 0x0030 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 0x0031 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 0x0032 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 0x0033 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP1 0x0034 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP10 0x0035 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP10_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP11 0x0036 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP11_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP12 0x0037 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP12_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP13 0x0038 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP14 0x0039 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP14_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP15 0x003a +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP15_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP16 0x003b +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP16_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP17 0x003c +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP17_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP18 0x003d +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP18_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP19 0x003e +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP19_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 0x003f +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20 0x0040 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21 0x0041 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23 0x0042 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24 0x0043 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 0x0044 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 0x0045 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 0x0046 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 0x0047 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 0x0048 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP8 0x0049 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP9 0x004a +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP9_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_PF0_BIF_BME_STATUS 0x00eb +#define regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_CONTROL 0x013e +#define regBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_PF0_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_PF0_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_PF0_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_gdc_GDCDEC +// base address: 0x0 +#define regGDC0_NGDC_SDP_PORT_CTRL 0x0180 +#define regGDC0_NGDC_SDP_PORT_CTRL_BASE_IDX 2 +#define regGDC0_SHUB_REGS_IF_CTL 0x0181 +#define regGDC0_SHUB_REGS_IF_CTL_BASE_IDX 2 +#define regGDC0_NGDC_MGCG_CTRL 0x0187 +#define regGDC0_NGDC_MGCG_CTRL_BASE_IDX 2 +#define regGDC0_S2A_MISC_CNTL 0x0188 +#define regGDC0_S2A_MISC_CNTL_BASE_IDX 2 +#define regGDC0_NGDC_MCA_SMN_CTRL0 0x018b +#define regGDC0_NGDC_MCA_SMN_CTRL0_BASE_IDX 2 +#define regGDC0_NGDC_EARLY_WAKEUP_CTRL 0x018c +#define regGDC0_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 2 +#define regGDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL 0x0198 +#define regGDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL_BASE_IDX 2 +#define regGDC0_GDC_DMA_SION_PCTRL 0x0199 +#define regGDC0_GDC_DMA_SION_PCTRL_BASE_IDX 2 +#define regGDC0_NGDC_MP4SDP_CNTL 0x019b +#define regGDC0_NGDC_MP4SDP_CNTL_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF0 0x01f3 +#define regGDC0_DOORBELL_VCN_TARGET_VF0_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF1 0x01f3 +#define regGDC0_DOORBELL_VCN_TARGET_VF1_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF2 0x01f4 +#define regGDC0_DOORBELL_VCN_TARGET_VF2_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF3 0x01f4 +#define regGDC0_DOORBELL_VCN_TARGET_VF3_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF4 0x01f5 +#define regGDC0_DOORBELL_VCN_TARGET_VF4_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF5 0x01f5 +#define regGDC0_DOORBELL_VCN_TARGET_VF5_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF6 0x01f6 +#define regGDC0_DOORBELL_VCN_TARGET_VF6_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF7 0x01f6 +#define regGDC0_DOORBELL_VCN_TARGET_VF7_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_PF 0x01f7 +#define regGDC0_DOORBELL_ACCESS_EN_PF_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF0 0x01f7 +#define regGDC0_DOORBELL_ACCESS_EN_VF0_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF1 0x01f8 +#define regGDC0_DOORBELL_ACCESS_EN_VF1_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF2 0x01f8 +#define regGDC0_DOORBELL_ACCESS_EN_VF2_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF3 0x01f9 +#define regGDC0_DOORBELL_ACCESS_EN_VF3_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF4 0x01f9 +#define regGDC0_DOORBELL_ACCESS_EN_VF4_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF5 0x01fa +#define regGDC0_DOORBELL_ACCESS_EN_VF5_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF6 0x01fa +#define regGDC0_DOORBELL_ACCESS_EN_VF6_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF7 0x01fb +#define regGDC0_DOORBELL_ACCESS_EN_VF7_BASE_IDX 2 +#define regGDC0_NGDC_CNDI_BUS_PORT_CTRL 0x01fc +#define regGDC0_NGDC_CNDI_BUS_PORT_CTRL_BASE_IDX 2 +#define regGDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL 0x01fd +#define regGDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_gdc_s2a_GDCS2A_DEC +// base address: 0x0 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL 0x01cb +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1 0x01cc +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL 0x01cd +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1 0x01ce +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL 0x01cf +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1 0x01d0 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL 0x01d1 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1 0x01d2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL 0x01d3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1 0x01d4 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL 0x01d5 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1 0x01d6 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL 0x01d7 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1 0x01d8 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL 0x01d9 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1 0x01da +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL 0x01db +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1 0x01dc +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL 0x01dd +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1 0x01de +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL 0x01df +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1 0x01e0 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL 0x01e1 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1 0x01e2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL 0x01e3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1 0x01e4 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL 0x01e5 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1 0x01e6 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL 0x01e7 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1 0x01e8 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL 0x01e9 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1 0x01ea +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG 0x01eb +#define regGDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 2 +#define regGDC_S2A0_NBIF_GFX_DOORBELL_STATUS 0x01ec +#define regGDC_S2A0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x003f +#define cfgVENDOR_CAP_LIST 0x0048 +#define cfgADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0664 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x0668 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x066c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x06dc +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x06e0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x06e2 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_RTR_DATA2 0x0724 +#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST 0x0728 +#define cfgPCIE_PWR_BUDGET_DATA_SELECT 0x072c +#define cfgPCIE_PWR_BUDGET_DATA 0x0730 +#define cfgPCIE_PWR_BUDGET_CAP 0x0734 +#define cfgPCIE_DPA_ENH_CAP_LIST 0x0738 +#define cfgPCIE_DPA_CAP 0x073c +#define cfgPCIE_DPA_LATENCY_INDICATOR 0x0740 +#define cfgPCIE_DPA_STATUS 0x0744 +#define cfgPCIE_DPA_CNTL 0x0746 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0748 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0749 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x074a +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x074b +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x074c +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x074d +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x074e +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x074f +#define cfgPCIE_LTR_ENH_CAP_LIST 0x0768 +#define cfgPCIE_LTR_CAP 0x076c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x0776 +#define cfgPCIE_BAR_ENH_CAP_LIST 0x0778 +#define cfgPCIE_BAR1_CAP 0x077c +#define cfgPCIE_BAR1_CNTL 0x0780 +#define cfgPCIE_BAR2_CAP 0x0784 +#define cfgPCIE_BAR2_CNTL 0x0788 +#define cfgPCIE_BAR3_CAP 0x078c +#define cfgPCIE_BAR3_CNTL 0x0790 +#define cfgPCIE_BAR4_CAP 0x0794 +#define cfgPCIE_BAR4_CNTL 0x0798 +#define cfgPCIE_BAR5_CAP 0x079c +#define cfgPCIE_BAR5_CNTL 0x07a0 +#define cfgPCIE_BAR6_CAP 0x07a4 +#define cfgPCIE_BAR6_CNTL 0x07a8 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL 0x07b2 +#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x07b4 +#define cfgPCIE_PAGE_REQ_CNTL 0x07b8 +#define cfgPCIE_PAGE_REQ_STATUS 0x07ba +#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x07bc +#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x07c0 +#define cfgPCIE_PASID_ENH_CAP_LIST 0x07c4 +#define cfgPCIE_PASID_CAP 0x07c8 +#define cfgPCIE_PASID_CNTL 0x07ca +#define cfgPCIE_SRIOV_ENH_CAP_LIST 0x07cc +#define cfgPCIE_SRIOV_CAP 0x07d0 +#define cfgPCIE_SRIOV_CONTROL 0x07d4 +#define cfgPCIE_SRIOV_STATUS 0x07d6 +#define cfgPCIE_SRIOV_INITIAL_VFS 0x07d8 +#define cfgPCIE_SRIOV_TOTAL_VFS 0x07da +#define cfgPCIE_SRIOV_NUM_VFS 0x07dc +#define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x07de +#define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x07e0 +#define cfgPCIE_SRIOV_VF_STRIDE 0x07e2 +#define cfgPCIE_SRIOV_VF_DEVICE_ID 0x07e6 +#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x07e8 +#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x07ec +#define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x07f0 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x07f4 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x07f8 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x07fc +#define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0800 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0804 +#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x0808 +#define cfgPCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x08e0 +#define cfgPCIE_VF_RESIZE_BAR1_CAP 0x08e4 +#define cfgPCIE_VF_RESIZE_BAR1_CNTL 0x08e8 +#define cfgPCIE_VF_RESIZE_BAR2_CAP 0x08ec +#define cfgPCIE_VF_RESIZE_BAR2_CNTL 0x08f0 +#define cfgPCIE_VF_RESIZE_BAR3_CAP 0x08f4 +#define cfgPCIE_VF_RESIZE_BAR3_CNTL 0x08f8 +#define cfgPCIE_VF_RESIZE_BAR4_CAP 0x08fc +#define cfgPCIE_VF_RESIZE_BAR4_CNTL 0x0900 +#define cfgPCIE_VF_RESIZE_BAR5_CAP 0x0904 +#define cfgPCIE_VF_RESIZE_BAR5_CNTL 0x0908 +#define cfgPCIE_VF_RESIZE_BAR6_CAP 0x090c +#define cfgPCIE_VF_RESIZE_BAR6_CNTL 0x0910 +#define cfgPCIE_DOE_ENH_CAP_LIST 0x0914 +#define cfgPCIE_DOE_CAP 0x0918 +#define cfgPCIE_DOE_CNTL 0x091c +#define cfgPCIE_DOE_STS 0x0920 +#define cfgPCIE_DOE_WMBOX 0x0924 +#define cfgPCIE_DOE_RMBOX 0x0928 +#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x09ac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x09b0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x09b4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x09b8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x09bc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x09c0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x09c4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x09c8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x09cc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x09d4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x09dc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x09e0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0 0x0a04 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 0x0a08 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 0x0a0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 0x0a10 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 0x0a14 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0 0x0a1c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1 0x0a20 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2 0x0a24 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3 0x0a28 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4 0x0a2c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5 0x0a30 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6 0x0a34 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7 0x0a38 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8 0x0a3c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0 0x0a4c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1 0x0a50 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2 0x0a54 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3 0x0a58 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4 0x0a5c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5 0x0a60 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6 0x0a64 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7 0x0a68 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8 0x0a6c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0 0x0a7c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1 0x0a80 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2 0x0a84 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3 0x0a88 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4 0x0a8c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5 0x0a90 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6 0x0a94 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7 0x0a98 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8 0x0a9c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0 0x0aac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1 0x0ab0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2 0x0ab4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3 0x0ab8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4 0x0abc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5 0x0ac0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6 0x0ac4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7 0x0ac8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8 0x0acc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0 0x0adc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1 0x0ae0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2 0x0ae4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3 0x0ae8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4 0x0aec +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5 0x0af0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6 0x0af4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7 0x0af8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8 0x0afc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0 0x0b0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1 0x0b10 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2 0x0b14 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3 0x0b18 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4 0x0b1c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5 0x0b20 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6 0x0b24 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7 0x0b28 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8 0x0b2c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0 0x0b3c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1 0x0b40 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2 0x0b44 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3 0x0b48 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4 0x0b4c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5 0x0b50 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6 0x0b54 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7 0x0b58 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8 0x0b5c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0 0x0b6c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1 0x0b70 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2 0x0b74 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3 0x0b78 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4 0x0b7c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5 0x0b80 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6 0x0b84 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7 0x0b88 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8 0x0b8c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0 0x0b9c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1 0x0ba0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2 0x0ba4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3 0x0ba8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4 0x0bac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5 0x0bb0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6 0x0bb4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7 0x0bb8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8 0x0bbc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0 0x0bcc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1 0x0bd0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2 0x0bd4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3 0x0bd8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4 0x0bdc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5 0x0be0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6 0x0be4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7 0x0be8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8 0x0bec +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0 0x0bfc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1 0x0c00 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2 0x0c04 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3 0x0c08 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4 0x0c0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5 0x0c10 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6 0x0c14 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7 0x0c18 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8 0x0c1c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0 0x0c2c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1 0x0c30 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2 0x0c34 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3 0x0c38 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4 0x0c3c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5 0x0c40 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6 0x0c44 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7 0x0c48 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8 0x0c4c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0 0x0c5c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1 0x0c60 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2 0x0c64 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3 0x0c68 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4 0x0c6c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5 0x0c70 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6 0x0c74 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7 0x0c78 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8 0x0c7c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0 0x0c8c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1 0x0c90 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2 0x0c94 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3 0x0c98 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4 0x0c9c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5 0x0ca0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6 0x0ca4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7 0x0ca8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8 0x0cac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0 0x0cbc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1 0x0cc0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2 0x0cc4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3 0x0cc8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4 0x0ccc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5 0x0cd0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6 0x0cd4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7 0x0cd8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8 0x0cdc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0 0x0cec +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1 0x0cf0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2 0x0cf4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3 0x0cf8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4 0x0cfc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5 0x0d00 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6 0x0d04 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7 0x0d08 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8 0x0d0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0 0x0d1c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1 0x0d20 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2 0x0d24 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3 0x0d28 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4 0x0d2c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5 0x0d30 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6 0x0d34 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7 0x0d38 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8 0x0d3c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0 0x0d4c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1 0x0d50 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2 0x0d54 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3 0x0d58 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4 0x0d5c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5 0x0d60 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6 0x0d64 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7 0x0d68 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8 0x0d6c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0 0x0d7c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1 0x0d80 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2 0x0d84 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3 0x0d88 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4 0x0d8c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5 0x0d90 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6 0x0d94 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7 0x0d98 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8 0x0d9c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0 0x0dac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1 0x0db0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2 0x0db4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3 0x0db8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4 0x0dbc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5 0x0dc0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6 0x0dc4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7 0x0dc8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8 0x0dcc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE 0x0ddc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE 0x0de0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE 0x0de4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE 0x0de8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS 0x0dec +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS 0x0df0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS 0x0df4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS 0x0df8 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgpciedecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x0114 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x0118 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x011c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x011e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0120 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0122 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0126 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0128 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x012a +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x012c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x012e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0132 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0134 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0136 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0138 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x013a +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 0x01b8 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 0x01bc +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 0x01c0 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 0x01c4 +#define cfgBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x01c8 +#define cfgBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x01cc +#define cfgBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x01d0 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 0x01d8 +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 0x01d9 +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 0x01da +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 0x01db +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 0x01dc +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 0x01dd +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 0x01de +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 0x01df +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 0x01e0 +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 0x01e1 +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 0x01e2 +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 0x01e3 +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 0x01e4 +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 0x01e5 +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 0x01e6 +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 0x01e7 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST 0x01f8 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_32GT 0x01fc +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT 0x0200 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT 0x0204 +#define cfgBIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1 0x0208 +#define cfgBIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2 0x020c +#define cfgBIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1 0x0210 +#define cfgBIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2 0x0214 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT 0x0218 +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT 0x0219 +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT 0x021a +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT 0x021b +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT 0x021c +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT 0x021d +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT 0x021e +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT 0x021f +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT 0x0220 +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT 0x0221 +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT 0x0222 +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT 0x0223 +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT 0x0224 +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT 0x0225 +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT 0x0226 +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT 0x0227 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST 0x0238 +#define cfgBIF_CFG_DEV0_EPF0_AP_CAP 0x023c +#define cfgBIF_CFG_DEV0_EPF0_AP_CNTL 0x0240 +#define cfgBIF_CFG_DEV0_EPF0_AP_DATA1 0x0244 +#define cfgBIF_CFG_DEV0_EPF0_AP_DATA2 0x0248 +#define cfgBIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK 0x024c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 0x0256 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 0x0258 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 0x025a +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 0x025c +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 0x025e +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 0x0260 +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 0x0262 +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 0x0264 +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 0x0266 +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 0x0268 +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 0x026a +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 0x026c +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 0x026e +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 0x0270 +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 0x0272 +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 0x0274 +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 0x0276 +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 0x0278 +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 0x027a +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 0x027c +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 0x027e +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 0x0282 +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 0x0286 +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 0x028a +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 0x028c +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 0x028e +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 0x0292 +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 0x0296 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x0404 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x0408 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x040c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x0410 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x0412 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x0414 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x0418 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x041e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x0420 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x0424 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x042a +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 0x0430 +#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 0x0434 +#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 0x0438 +#define cfgBIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST 0x0e00 +#define cfgBIF_CFG_DEV0_EPF0_IDE_CAP 0x0e04 +#define cfgBIF_CFG_DEV0_EPF0_IDE_CNTL 0x0e08 +#define cfgBIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL 0x0e0c +#define cfgBIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS 0x0e10 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CAP 0x0e14 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL 0x0e18 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS 0x0e1c +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG1 0x0e20 +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2 0x0e24 +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1 0x0e28 +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG2 0x0e2c +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG3 0x0e30 +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1 0x0e34 +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG2 0x0e38 +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG3 0x0e3c +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CAP 0x0e40 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL 0x0e44 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS 0x0e48 +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG1 0x0e4c +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2 0x0e50 +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1 0x0e54 +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG2 0x0e58 +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG3 0x0e5c +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1 0x0e60 +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG2 0x0e64 +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG3 0x0e68 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CAP 0x0e6c +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL 0x0e70 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS 0x0e74 +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG1 0x0e78 +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2 0x0e7c +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1 0x0e80 +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG2 0x0e84 +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG3 0x0e88 +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1 0x0e8c +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG2 0x0e90 +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG3 0x0e94 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CAP 0x0e98 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL 0x0e9c +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS 0x0ea0 +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG1 0x0ea4 +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2 0x0ea8 +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1 0x0eac +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG2 0x0eb0 +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG3 0x0eb4 +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1 0x0eb8 +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG2 0x0ebc +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG3 0x0ec0 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CAP 0x0ec4 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL 0x0ec8 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS 0x0ecc +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG1 0x0ed0 +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2 0x0ed4 +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1 0x0ed8 +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG2 0x0edc +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG3 0x0ee0 +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1 0x0ee4 +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG2 0x0ee8 +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG3 0x0eec +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CAP 0x0ef0 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL 0x0ef4 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS 0x0ef8 +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG1 0x0efc +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2 0x0f00 +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1 0x0f04 +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG2 0x0f08 +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG3 0x0f0c +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1 0x0f10 +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG2 0x0f14 +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG3 0x0f18 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CAP 0x0f1c +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL 0x0f20 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS 0x0f24 +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG1 0x0f28 +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2 0x0f2c +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1 0x0f30 +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG2 0x0f34 +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG3 0x0f38 +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1 0x0f3c +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG2 0x0f40 +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG3 0x0f44 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CAP 0x0f48 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL 0x0f4c +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS 0x0f50 +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG1 0x0f54 +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2 0x0f58 +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1 0x0f5c +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG2 0x0f60 +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG3 0x0f64 +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1 0x0f68 +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG2 0x0f6c +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG3 0x0f70 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CAP 0x0f74 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL 0x0f78 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS 0x0f7c +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG1 0x0f80 +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2 0x0f84 +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1 0x0f88 +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG2 0x0f8c +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG3 0x0f90 +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1 0x0f94 +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG2 0x0f98 +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG3 0x0f9c + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_rc_bifcfgdecp +// base address: 0x10100000 +#define regBIF_CFG_DEV0_RC0_VENDOR_ID 0x0000 +#define regBIF_CFG_DEV0_RC0_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DEVICE_ID 0x0000 +#define regBIF_CFG_DEV0_RC0_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_COMMAND 0x0001 +#define regBIF_CFG_DEV0_RC0_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_STATUS 0x0001 +#define regBIF_CFG_DEV0_RC0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_REVISION_ID 0x0002 +#define regBIF_CFG_DEV0_RC0_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE 0x0002 +#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SUB_CLASS 0x0002 +#define regBIF_CFG_DEV0_RC0_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_BASE_CLASS 0x0002 +#define regBIF_CFG_DEV0_RC0_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_CACHE_LINE 0x0003 +#define regBIF_CFG_DEV0_RC0_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LATENCY 0x0003 +#define regBIF_CFG_DEV0_RC0_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_HEADER 0x0003 +#define regBIF_CFG_DEV0_RC0_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_BIST 0x0003 +#define regBIF_CFG_DEV0_RC0_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1 0x0004 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2 0x0005 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY 0x0006 +#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT 0x0007 +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS 0x0007 +#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT 0x0008 +#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT 0x0009 +#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER 0x000a +#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER 0x000b +#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI 0x000c +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_CAP_PTR 0x000d +#define regBIF_CFG_DEV0_RC0_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR 0x000e +#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE 0x000f +#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN 0x000f +#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL 0x000f +#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL 0x0010 +#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST 0x0014 +#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PMI_CAP 0x0014 +#define regBIF_CFG_DEV0_RC0_PMI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL 0x0015 +#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST 0x0016 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP 0x0016 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP 0x0017 +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL 0x0018 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS 0x0018 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CAP 0x0019 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL 0x001a +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS 0x001a +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SLOT_CAP 0x001b +#define regBIF_CFG_DEV0_RC0_SLOT_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL 0x001c +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS 0x001c +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_ROOT_CNTL 0x001d +#define regBIF_CFG_DEV0_RC0_ROOT_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_ROOT_CAP 0x001d +#define regBIF_CFG_DEV0_RC0_ROOT_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_ROOT_STATUS 0x001e +#define regBIF_CFG_DEV0_RC0_ROOT_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2 0x001f +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2 0x0020 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2 0x0020 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CAP2 0x0021 +#define regBIF_CFG_DEV0_RC0_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL2 0x0022 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS2 0x0022 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SLOT_CAP2 0x0023 +#define regBIF_CFG_DEV0_RC0_SLOT_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2 0x0024 +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2 0x0024 +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST 0x0028 +#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL 0x0028 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO 0x0029 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI 0x002a +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA 0x002a +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA 0x002a +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 0x002b +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 0x002b +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST 0x0030 +#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SSID_CAP 0x0031 +#define regBIF_CFG_DEV0_RC0_SSID_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0040 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0041 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 0x0042 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 0x0043 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x0044 +#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 0x0045 +#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS 0x0046 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x0047 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x0047 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0048 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0048 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0049 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0049 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x004a +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x004a +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x004b +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x004b +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x004c +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x004c +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x004d +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x004d +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x004e +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x004e +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0x006e +#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT 0x006f +#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT 0x0070 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT 0x0071 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0072 +#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0073 +#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0074 +#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0x0076 +#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0x0076 +#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0x0076 +#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0x0076 +#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0x0077 +#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0x0077 +#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0x0077 +#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0x0077 +#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0x0078 +#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0x0078 +#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0x0078 +#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0x0078 +#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0x0079 +#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0x0079 +#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0x0079 +#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0x0079 +#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST 0x007e +#define regBIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT 0x007f +#define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT 0x0080 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT 0x0081 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1 0x0082 +#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2 0x0083 +#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1 0x0084 +#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2 0x0085 +#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT 0x0086 +#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT 0x0086 +#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT 0x0086 +#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT 0x0086 +#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT 0x0087 +#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT 0x0087 +#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT 0x0087 +#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT 0x0087 +#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT 0x0088 +#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT 0x0088 +#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT 0x0088 +#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT 0x0088 +#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT 0x0089 +#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT 0x0089 +#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT 0x0089 +#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT 0x0089 +#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST 0x008e +#define regBIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_AP_CAP 0x008f +#define regBIF_CFG_DEV0_RC0_AP_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_AP_CNTL 0x0090 +#define regBIF_CFG_DEV0_RC0_AP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_AP_DATA1 0x0091 +#define regBIF_CFG_DEV0_RC0_AP_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_AP_DATA2 0x0092 +#define regBIF_CFG_DEV0_RC0_AP_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_AP_SEL_EN_MASK 0x0093 +#define regBIF_CFG_DEV0_RC0_AP_SEL_EN_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST 0x0094 +#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP 0x0095 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS 0x0095 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL 0x0096 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS 0x0096 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL 0x0097 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS 0x0097 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL 0x0098 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS 0x0098 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL 0x0099 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS 0x0099 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL 0x009a +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS 0x009a +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL 0x009b +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS 0x009b +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL 0x009c +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS 0x009c +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL 0x009d +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS 0x009d +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL 0x009e +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS 0x009e +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL 0x009f +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS 0x009f +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL 0x00a0 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS 0x00a0 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL 0x00a1 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS 0x00a1 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL 0x00a2 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS 0x00a2 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL 0x00a3 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS 0x00a3 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL 0x00a4 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS 0x00a4 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL 0x00a5 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS 0x00a5 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST 0x0100 +#define regBIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST 0x0101 +#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 0x0102 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 0x0103 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL 0x0104 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS 0x0104 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP 0x0105 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL 0x0106 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS 0x0107 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP 0x0108 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL 0x0109 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS 0x010a +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST 0x010c +#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP 0x010d +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS 0x010e +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST 0x0180 +#define regBIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0181 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS 0x0182 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK 0x0183 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY 0x0184 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS 0x0185 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK 0x0186 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL 0x0187 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 0x0188 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 0x0189 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 0x018a +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 0x018b +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD 0x018c +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS 0x018d +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID 0x018e +#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG4 0x018f +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 0x018f +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG5 0x0190 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 0x0190 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG6 0x0191 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 0x0191 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG7 0x0192 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 0x0192 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG8 0x0193 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG9 0x0194 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG10 0x0195 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG11 0x0196 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG12 0x0197 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG13 0x0198 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0199 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x019a +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x019b +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST 0x01b7 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP 0x01b8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL 0x01b8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST 0x01c7 +#define regBIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_RTR_DATA1 0x01c8 +#define regBIF_CFG_DEV0_RC0_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_RTR_DATA2 0x01c9 +#define regBIF_CFG_DEV0_RC0_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST 0x0380 +#define regBIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_CAP 0x0381 +#define regBIF_CFG_DEV0_RC0_IDE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_CNTL 0x0382 +#define regBIF_CFG_DEV0_RC0_IDE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL 0x0383 +#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS 0x0384 +#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP 0x0385 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL 0x0386 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS 0x0387 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1 0x0388 +#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2 0x0389 +#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1 0x038a +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2 0x038b +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3 0x038c +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1 0x038d +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2 0x038e +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3 0x038f +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP 0x0390 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL 0x0391 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS 0x0392 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1 0x0393 +#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2 0x0394 +#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1 0x0395 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2 0x0396 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3 0x0397 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1 0x0398 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2 0x0399 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3 0x039a +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP 0x039b +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL 0x039c +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS 0x039d +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1 0x039e +#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2 0x039f +#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1 0x03a0 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2 0x03a1 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3 0x03a2 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1 0x03a3 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2 0x03a4 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3 0x03a5 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP 0x03a6 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL 0x03a7 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS 0x03a8 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1 0x03a9 +#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2 0x03aa +#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1 0x03ab +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2 0x03ac +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3 0x03ad +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1 0x03ae +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2 0x03af +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3 0x03b0 +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP 0x03b1 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL 0x03b2 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS 0x03b3 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1 0x03b4 +#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2 0x03b5 +#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1 0x03b6 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2 0x03b7 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3 0x03b8 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1 0x03b9 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2 0x03ba +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3 0x03bb +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP 0x03bc +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL 0x03bd +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS 0x03be +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1 0x03bf +#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2 0x03c0 +#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1 0x03c1 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2 0x03c2 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3 0x03c3 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1 0x03c4 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2 0x03c5 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3 0x03c6 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP 0x03c7 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL 0x03c8 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS 0x03c9 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1 0x03ca +#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2 0x03cb +#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1 0x03cc +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2 0x03cd +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3 0x03ce +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1 0x03cf +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2 0x03d0 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3 0x03d1 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP 0x03d2 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL 0x03d3 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS 0x03d4 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1 0x03d5 +#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2 0x03d6 +#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1 0x03d7 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2 0x03d8 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3 0x03d9 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1 0x03da +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2 0x03db +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3 0x03dc +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP 0x03dd +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL 0x03de +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS 0x03df +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1 0x03e0 +#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2 0x03e1 +#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1 0x03e2 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2 0x03e3 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3 0x03e4 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1 0x03e5 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2 0x03e6 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3 0x03e7 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_0_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x10012 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x10013 +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x10014 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x10014 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x10015 +#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10199 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x1019a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x1019b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x101b7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x101b8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x101b8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x101ca +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x101cb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x101cc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x101cd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x101ce +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x101cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x101d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x101d1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x101d1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x101d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x101d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x101d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x101d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x101d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x101d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x101d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x101d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x101da +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x101db +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x101de +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x101df +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x101e0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x101e1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x101e2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x101e3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x101e4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x101e5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x101e6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x101e7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x101e8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x101e9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x101ea +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x101ed +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x101ee +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x101ee +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x101ef +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x101f0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x101f1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x101f2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x101f2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x101f3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x101f4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x101f5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x101f5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x101f6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x101f6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x101f7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x101f7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x101f8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x101f8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x101f9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x101fa +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x101fb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x101fc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x101fd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x101fe +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x101ff +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x10200 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x10201 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x10202 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10238 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP 0x10239 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL 0x1023a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP 0x1023b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL 0x1023c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP 0x1023d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL 0x1023e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP 0x1023f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL 0x10240 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP 0x10241 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL 0x10242 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP 0x10243 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL 0x10244 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST 0x10245 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP 0x10246 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL 0x10247 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS 0x10248 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX 0x10249 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX 0x1024a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x1026b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x1026c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x1026d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x1026e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x1026f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x10270 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x10271 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x10272 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x10273 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x10275 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x10277 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x10278 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0 0x10281 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 0x10282 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 0x10283 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 0x10284 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 0x10285 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0 0x10287 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1 0x10288 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2 0x10289 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3 0x1028a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4 0x1028b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5 0x1028c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6 0x1028d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7 0x1028e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8 0x1028f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0 0x10293 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1 0x10294 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2 0x10295 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3 0x10296 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4 0x10297 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5 0x10298 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6 0x10299 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7 0x1029a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8 0x1029b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0 0x1029f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1 0x102a0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2 0x102a1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3 0x102a2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4 0x102a3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5 0x102a4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6 0x102a5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7 0x102a6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8 0x102a7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0 0x102ab +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1 0x102ac +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2 0x102ad +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3 0x102ae +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4 0x102af +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5 0x102b0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6 0x102b1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7 0x102b2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8 0x102b3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0 0x102b7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1 0x102b8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2 0x102b9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3 0x102ba +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4 0x102bb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5 0x102bc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6 0x102bd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7 0x102be +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8 0x102bf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0 0x102c3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1 0x102c4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2 0x102c5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3 0x102c6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4 0x102c7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5 0x102c8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6 0x102c9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7 0x102ca +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8 0x102cb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0 0x102cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1 0x102d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2 0x102d1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3 0x102d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4 0x102d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5 0x102d4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6 0x102d5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7 0x102d6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8 0x102d7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0 0x102db +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1 0x102dc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2 0x102dd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3 0x102de +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4 0x102df +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5 0x102e0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6 0x102e1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7 0x102e2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8 0x102e3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0 0x102e7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1 0x102e8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2 0x102e9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3 0x102ea +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4 0x102eb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5 0x102ec +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6 0x102ed +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7 0x102ee +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8 0x102ef +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0 0x102f3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1 0x102f4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2 0x102f5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3 0x102f6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4 0x102f7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5 0x102f8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6 0x102f9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7 0x102fa +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8 0x102fb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0 0x102ff +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1 0x10300 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2 0x10301 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3 0x10302 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4 0x10303 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5 0x10304 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6 0x10305 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7 0x10306 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8 0x10307 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0 0x1030b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1 0x1030c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2 0x1030d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3 0x1030e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4 0x1030f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5 0x10310 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6 0x10311 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7 0x10312 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8 0x10313 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0 0x10317 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1 0x10318 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2 0x10319 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3 0x1031a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4 0x1031b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5 0x1031c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6 0x1031d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7 0x1031e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8 0x1031f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0 0x10323 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1 0x10324 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2 0x10325 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3 0x10326 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4 0x10327 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5 0x10328 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6 0x10329 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7 0x1032a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8 0x1032b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0 0x1032f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1 0x10330 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2 0x10331 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3 0x10332 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4 0x10333 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5 0x10334 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6 0x10335 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7 0x10336 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8 0x10337 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0 0x1033b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1 0x1033c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2 0x1033d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3 0x1033e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4 0x1033f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5 0x10340 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6 0x10341 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7 0x10342 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8 0x10343 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0 0x10347 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1 0x10348 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2 0x10349 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3 0x1034a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4 0x1034b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5 0x1034c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6 0x1034d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7 0x1034e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8 0x1034f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0 0x10353 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1 0x10354 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2 0x10355 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3 0x10356 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4 0x10357 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5 0x10358 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6 0x10359 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7 0x1035a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8 0x1035b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0 0x1035f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1 0x10360 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2 0x10361 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3 0x10362 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4 0x10363 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5 0x10364 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6 0x10365 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7 0x10366 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8 0x10367 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0 0x1036b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1 0x1036c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2 0x1036d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3 0x1036e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4 0x1036f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5 0x10370 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6 0x10371 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7 0x10372 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8 0x10373 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE 0x10377 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE 0x10378 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE 0x10379 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE 0x1037a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS 0x1037b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS 0x1037c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS 0x1037d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS 0x1037e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgpciedecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x10044 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x10045 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x10046 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x10047 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x10047 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x10048 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x10048 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x10049 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x10049 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x1004a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x1004a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x1004b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x1004b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x1004c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x1004c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x1004d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x1004d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x1004e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x1004e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x1006e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0x1006f +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0x10070 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0x10071 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x10072 +#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x10073 +#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x10074 +#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x10076 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x10076 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x10076 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x10076 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x10077 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x10077 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x10077 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x10077 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x10078 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x10078 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x10078 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x10078 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x10079 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x10079 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x10079 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x10079 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST 0x1007e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT 0x1007f +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT 0x10080 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT 0x10081 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1 0x10082 +#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2 0x10083 +#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1 0x10084 +#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2 0x10085 +#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT 0x10086 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT 0x10086 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT 0x10086 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT 0x10086 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT 0x10087 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT 0x10087 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT 0x10087 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT 0x10087 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT 0x10088 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT 0x10088 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT 0x10088 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT 0x10088 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT 0x10089 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT 0x10089 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT 0x10089 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT 0x10089 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST 0x1008e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_AP_CAP 0x1008f +#define regBIF_CFG_DEV0_EPF0_0_AP_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_AP_CNTL 0x10090 +#define regBIF_CFG_DEV0_EPF0_0_AP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_AP_DATA1 0x10091 +#define regBIF_CFG_DEV0_EPF0_0_AP_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_AP_DATA2 0x10092 +#define regBIF_CFG_DEV0_EPF0_0_AP_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK 0x10093 +#define regBIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0x10094 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0x10095 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0x10095 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x10096 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x10096 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x10097 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x10097 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x1009a +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x1009a +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x1009b +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x1009b +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x1009c +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x1009c +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x1009d +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x1009d +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x1009e +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x1009e +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x1009f +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x1009f +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x100a0 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x100a0 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x100a1 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x100a1 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x100a2 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x100a2 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x100a3 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x100a3 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x100a4 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x100a4 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x100a5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x100a5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x10101 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x10102 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x10103 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x10104 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x10104 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x10105 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x10106 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x10107 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x10108 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x10109 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x1010a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x1010c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0x1010d +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0x1010e +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST 0x10380 +#define regBIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_CAP 0x10381 +#define regBIF_CFG_DEV0_EPF0_0_IDE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_CNTL 0x10382 +#define regBIF_CFG_DEV0_EPF0_0_IDE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL 0x10383 +#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS 0x10384 +#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP 0x10385 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL 0x10386 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS 0x10387 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1 0x10388 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2 0x10389 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1 0x1038a +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2 0x1038b +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3 0x1038c +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1 0x1038d +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2 0x1038e +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3 0x1038f +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP 0x10390 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL 0x10391 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS 0x10392 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1 0x10393 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2 0x10394 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1 0x10395 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2 0x10396 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3 0x10397 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1 0x10398 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2 0x10399 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3 0x1039a +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP 0x1039b +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL 0x1039c +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS 0x1039d +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1 0x1039e +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2 0x1039f +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1 0x103a0 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2 0x103a1 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3 0x103a2 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1 0x103a3 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2 0x103a4 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3 0x103a5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP 0x103a6 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL 0x103a7 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS 0x103a8 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1 0x103a9 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2 0x103aa +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1 0x103ab +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2 0x103ac +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3 0x103ad +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1 0x103ae +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2 0x103af +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3 0x103b0 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP 0x103b1 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL 0x103b2 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS 0x103b3 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1 0x103b4 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2 0x103b5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1 0x103b6 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2 0x103b7 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3 0x103b8 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1 0x103b9 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2 0x103ba +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3 0x103bb +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP 0x103bc +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL 0x103bd +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS 0x103be +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1 0x103bf +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2 0x103c0 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1 0x103c1 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2 0x103c2 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3 0x103c3 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1 0x103c4 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2 0x103c5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3 0x103c6 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP 0x103c7 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL 0x103c8 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS 0x103c9 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1 0x103ca +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2 0x103cb +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1 0x103cc +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2 0x103cd +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3 0x103ce +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1 0x103cf +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2 0x103d0 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3 0x103d1 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP 0x103d2 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL 0x103d3 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS 0x103d4 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1 0x103d5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2 0x103d6 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1 0x103d7 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2 0x103d8 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3 0x103d9 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1 0x103da +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2 0x103db +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3 0x103dc +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP 0x103dd +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL 0x103de +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS 0x103df +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1 0x103e0 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2 0x103e1 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1 0x103e2 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2 0x103e3 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3 0x103e4 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1 0x103e5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2 0x103e6 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3 0x103e7 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF0_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF0_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF0_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF0_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF1_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF1_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF1_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF1_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF1_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF2_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF2_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF2_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF2_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF2_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF3_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF3_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF3_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF3_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF3_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF4_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF4_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF4_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF4_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF4_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF5_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF5_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF5_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF5_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF5_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF6_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF6_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF6_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF6_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF6_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF7_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF7_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF7_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF7_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF7_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF0_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF0_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF0_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF1_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF1_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF1_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF2_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF2_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF2_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF3_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF3_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF3_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF4_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF4_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF4_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF5_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF5_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF5_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF6_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF6_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF6_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF7_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF7_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF7_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +// base address: 0x10141000 +#define regBIF_CFG_DEV0_EPF1_VENDOR_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_COMMAND 0x10401 +#define regBIF_CFG_DEV0_EPF1_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_STATUS 0x10401 +#define regBIF_CFG_DEV0_EPF1_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_REVISION_ID 0x10402 +#define regBIF_CFG_DEV0_EPF1_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE 0x10402 +#define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_SUB_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_CACHE_LINE 0x10403 +#define regBIF_CFG_DEV0_EPF1_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LATENCY 0x10403 +#define regBIF_CFG_DEV0_EPF1_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_HEADER 0x10403 +#define regBIF_CFG_DEV0_EPF1_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BIST 0x10403 +#define regBIF_CFG_DEV0_EPF1_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1 0x10404 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2 0x10405 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3 0x10406 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4 0x10407 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5 0x10408 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6 0x10409 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 0x1040a +#define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID 0x1040b +#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 0x1040c +#define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_CAP_PTR 0x1040d +#define regBIF_CFG_DEV0_EPF1_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 0x1040f +#define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 0x1040f +#define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MIN_GRANT 0x1040f +#define regBIF_CFG_DEV0_EPF1_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MAX_LATENCY 0x1040f +#define regBIF_CFG_DEV0_EPF1_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 0x10412 +#define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 0x10413 +#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 0x10414 +#define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PMI_CAP 0x10414 +#define regBIF_CFG_DEV0_EPF1_PMI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 0x10415 +#define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL_BASE_IDX 5 +#define regSBRN 0x10418 +#define regSBRN_BASE_IDX 5 +#define regFLADJ 0x10418 +#define regFLADJ_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 0x10419 +#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_CAP 0x10419 +#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP 0x1041a +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL 0x1041b +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS 0x1041b +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_CAP 0x1041c +#define regBIF_CFG_DEV0_EPF1_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_CNTL 0x1041d +#define regBIF_CFG_DEV0_EPF1_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_STATUS 0x1041d +#define regBIF_CFG_DEV0_EPF1_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2 0x10422 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 0x10423 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 0x10423 +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_CAP2 0x10424 +#define regBIF_CFG_DEV0_EPF1_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_CNTL2 0x10425 +#define regBIF_CFG_DEV0_EPF1_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_STATUS2 0x10425 +#define regBIF_CFG_DEV0_EPF1_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 0x10428 +#define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 0x10428 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 0x10429 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 0x1042a +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MASK 0x1042b +#define regBIF_CFG_DEV0_EPF1_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MASK_64 0x1042c +#define regBIF_CFG_DEV0_EPF1_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_PENDING 0x1042c +#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64 0x1042d +#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 0x10430 +#define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 0x10430 +#define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSIX_TABLE 0x10431 +#define regBIF_CFG_DEV0_EPF1_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSIX_PBA 0x10432 +#define regBIF_CFG_DEV0_EPF1_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 0x10441 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 0x10442 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 0x10443 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST 0x104b6 +#define regBIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP3 0x104b7 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL3 0x104b8 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS3 0x104b9 +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST 0x10500 +#define regBIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST 0x10580 +#define regBIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10581 +#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 0x10582 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 0x10583 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 0x10584 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 0x10585 +#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 0x10586 +#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 0x10587 +#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 0x10588 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 0x10589 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 0x1058a +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 0x1058b +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4 0x1058f +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 0x1058f +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5 0x10590 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 0x10590 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6 0x10591 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 0x10591 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7 0x10592 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 0x10592 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8 0x10593 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9 0x10594 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10 0x10595 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11 0x10596 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12 0x10597 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13 0x10598 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 0x105b7 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 0x105b8 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 0x105b8 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST 0x105c7 +#define regBIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_RTR_DATA1 0x105c8 +#define regBIF_CFG_DEV0_EPF1_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_RTR_DATA2 0x105c9 +#define regBIF_CFG_DEV0_EPF1_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x105ca +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 0x105cb +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 0x105cc +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 0x105cd +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 0x105ce +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 0x105cf +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 0x105d0 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 0x105d1 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 0x105d1 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x105d2 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x105d2 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x105d2 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x105d2 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x105d3 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x105d3 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x105d3 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x105d3 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 0x105dc +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 0x105dd +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 0x105dd +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 0x105de +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 0x105df +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 0x105e0 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 0x105e1 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 0x105e2 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 0x105e3 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 0x105e4 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 0x105e5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 0x105e6 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 0x105e7 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 0x105e8 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 0x105e9 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 0x105ea +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 0x105f1 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 0x105f2 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 0x105f2 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST 0x105f3 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP 0x105f4 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL 0x105f5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS 0x105f5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS 0x105f6 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS 0x105f6 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS 0x105f7 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK 0x105f7 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET 0x105f8 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE 0x105f8 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID 0x105f9 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x105fa +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x105fb +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 0x105fc +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 0x105fd +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 0x105fe +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 0x105ff +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 0x10600 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 0x10601 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x10602 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10638 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP 0x10639 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL 0x1063a +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP 0x1063b +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL 0x1063c +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP 0x1063d +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL 0x1063e +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP 0x1063f +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL 0x10640 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP 0x10641 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL 0x10642 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP 0x10643 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL 0x10644 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf1_vf0_bifcfgdecp +// base address: 0x10141000 +#define regBIF_CFG_DEV0_EPF1_VF0_VENDOR_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_VF0_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_COMMAND 0x10401 +#define regBIF_CFG_DEV0_EPF1_VF0_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_STATUS 0x10401 +#define regBIF_CFG_DEV0_EPF1_VF0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_REVISION_ID 0x10402 +#define regBIF_CFG_DEV0_EPF1_VF0_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE 0x10402 +#define regBIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_SUB_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_VF0_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_CACHE_LINE 0x10403 +#define regBIF_CFG_DEV0_EPF1_VF0_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_LATENCY 0x10403 +#define regBIF_CFG_DEV0_EPF1_VF0_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_HEADER 0x10403 +#define regBIF_CFG_DEV0_EPF1_VF0_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BIST 0x10403 +#define regBIF_CFG_DEV0_EPF1_VF0_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1 0x10404 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2 0x10405 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3 0x10406 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4 0x10407 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5 0x10408 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6 0x10409 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR 0x1040a +#define regBIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID 0x1040b +#define regBIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR 0x1040c +#define regBIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_CAP_PTR 0x1040d +#define regBIF_CFG_DEV0_EPF1_VF0_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE 0x1040f +#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN 0x1040f +#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MIN_GRANT 0x1040f +#define regBIF_CFG_DEV0_EPF1_VF0_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY 0x1040f +#define regBIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST 0x10419 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP 0x10419 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP 0x1041a +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL 0x1041b +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS 0x1041b +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP 0x1041c +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL 0x1041d +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS 0x1041d +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2 0x10422 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2 0x10423 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2 0x10423 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP2 0x10424 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2 0x10425 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2 0x10425 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST 0x10428 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL 0x10428 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO 0x10429 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI 0x1042a +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK 0x1042b +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64 0x1042c +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING 0x1042c +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64 0x1042d +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST 0x10430 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL 0x10430 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE 0x10431 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_PBA 0x10432 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x10441 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1 0x10442 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2 0x10443 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST 0x104b6 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3 0x104b7 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3 0x104b8 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3 0x104b9 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST 0x10500 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST 0x10580 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10581 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS 0x10582 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK 0x10583 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY 0x10584 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS 0x10585 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK 0x10586 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL 0x10587 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0 0x10588 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1 0x10589 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2 0x1058a +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3 0x1058b +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4 0x1058f +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0 0x1058f +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5 0x10590 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1 0x10590 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6 0x10591 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2 0x10591 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7 0x10592 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3 0x10592 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8 0x10593 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9 0x10594 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10 0x10595 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11 0x10596 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12 0x10597 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13 0x10598 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST 0x105c7 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA1 0x105c8 +#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA2 0x105c9 +#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST 0x105dc +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP 0x105dd +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL 0x105dd +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DEV0_1_RCC_VDM_SUPPORT 0xc440 +#define regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BUS_CNTL 0xc441 +#define regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC 0xc442 +#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL 0xc443 +#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL 0xc444 +#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE 0xc445 +#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL 0xc446 +#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_MH_ARB_CNTL 0xc447 +#define regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 0xc448 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 0xc449 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_ep_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH 0xc44c +#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_CNTL 0xc44e +#define regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL 0xc44f +#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS 0xc450 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 0xc451 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL 0xc452 +#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL 0xc453 +#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL 0xc454 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC 0xc455 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 0xc456 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP 0xc457 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0xc458 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL 0xc458 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0xc458 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL 0xc45c +#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED 0xc45d +#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL 0xc45f +#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID 0xc460 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL 0xc461 +#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL 0xc462 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL 0xc463 +#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3 0xc464 +#define regRCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_dwn_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED 0xc468 +#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH 0xc469 +#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL 0xc46b +#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL 0xc46c +#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 0xc46d +#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL 0xc46e +#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL 0xc46f +#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 0xc470 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC 0xc471 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 0xc472 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL 0xc475 +#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL 0xc476 +#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL 0xc477 +#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 0xc478 +#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX 5 +#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC 0xc479 +#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX 5 +#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP 0xc47a +#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_pfc_amdgfx_RCCPFCDEC +// base address: 0x10134000 +#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL 0xd040 +#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE 0xd041 +#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 0xd042 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 0xd043 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 0xd044 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 0xd045 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 0xd046 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 0xd047 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL 0xd048 +#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL 0xd049 +#define regRCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_NFC 0xd04a +#define regRCC_PFC_AMDGFX_RCC_NFC_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_shadow_reg_shadowdec +// base address: 0x10130000 +#define regSHADOW_COMMAND 0xc001 +#define regSHADOW_COMMAND_BASE_IDX 5 +#define regSHADOW_BASE_ADDR_1 0xc004 +#define regSHADOW_BASE_ADDR_1_BASE_IDX 5 +#define regSHADOW_BASE_ADDR_2 0xc005 +#define regSHADOW_BASE_ADDR_2_BASE_IDX 5 +#define regSHADOW_SUB_BUS_NUMBER_LATENCY 0xc006 +#define regSHADOW_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 +#define regSHADOW_IO_BASE_LIMIT 0xc007 +#define regSHADOW_IO_BASE_LIMIT_BASE_IDX 5 +#define regSHADOW_MEM_BASE_LIMIT 0xc008 +#define regSHADOW_MEM_BASE_LIMIT_BASE_IDX 5 +#define regSHADOW_PREF_BASE_LIMIT 0xc009 +#define regSHADOW_PREF_BASE_LIMIT_BASE_IDX 5 +#define regSHADOW_PREF_BASE_UPPER 0xc00a +#define regSHADOW_PREF_BASE_UPPER_BASE_IDX 5 +#define regSHADOW_PREF_LIMIT_UPPER 0xc00b +#define regSHADOW_PREF_LIMIT_UPPER_BASE_IDX 5 +#define regSHADOW_IO_BASE_LIMIT_HI 0xc00c +#define regSHADOW_IO_BASE_LIMIT_HI_BASE_IDX 5 +#define regSHADOW_IRQ_BRIDGE_CNTL 0xc00f +#define regSHADOW_IRQ_BRIDGE_CNTL_BASE_IDX 5 +#define regSUC_INDEX 0xc038 +#define regSUC_INDEX_BASE_IDX 5 +#define regSUC_DATA 0xc039 +#define regSUC_DATA_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_swus_SUMDEC +// base address: 0x1013b000 +#define regSUM_INDEX 0xec38 +#define regSUM_INDEX_BASE_IDX 5 +#define regSUM_DATA 0xec39 +#define regSUM_DATA_BASE_IDX 5 +#define regSUM_INDEX_HI 0xec3b +#define regSUM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_strap_rcc_strap_internal +// base address: 0x10100000 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 0xc400 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 0xc401 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 0xc402 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 0xc403 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 0xc404 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 0xc405 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 0xc406 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 0xc407 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 0xc408 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 0xc409 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10 0xc40a +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11 0xc40b +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12 0xc40c +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13 0xc40d +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14 0xc40e +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP15 0xc40f +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP15_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP16 0xc410 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP16_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP17 0xc411 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP17_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP18 0xc412 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP18_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP0 0xc480 +#define regRCC_DEV1_PORT_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP1 0xc481 +#define regRCC_DEV1_PORT_STRAP1_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP2 0xc482 +#define regRCC_DEV1_PORT_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP3 0xc483 +#define regRCC_DEV1_PORT_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP4 0xc484 +#define regRCC_DEV1_PORT_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP5 0xc485 +#define regRCC_DEV1_PORT_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP6 0xc486 +#define regRCC_DEV1_PORT_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP7 0xc487 +#define regRCC_DEV1_PORT_STRAP7_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP8 0xc488 +#define regRCC_DEV1_PORT_STRAP8_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP9 0xc489 +#define regRCC_DEV1_PORT_STRAP9_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP10 0xc48a +#define regRCC_DEV1_PORT_STRAP10_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP11 0xc48b +#define regRCC_DEV1_PORT_STRAP11_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP12 0xc48c +#define regRCC_DEV1_PORT_STRAP12_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP13 0xc48d +#define regRCC_DEV1_PORT_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP14 0xc48e +#define regRCC_DEV1_PORT_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP15 0xc48f +#define regRCC_DEV1_PORT_STRAP15_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP16 0xc490 +#define regRCC_DEV1_PORT_STRAP16_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP0 0xc500 +#define regRCC_DEV2_PORT_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP1 0xc501 +#define regRCC_DEV2_PORT_STRAP1_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP2 0xc502 +#define regRCC_DEV2_PORT_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP3 0xc503 +#define regRCC_DEV2_PORT_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP4 0xc504 +#define regRCC_DEV2_PORT_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP5 0xc505 +#define regRCC_DEV2_PORT_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP6 0xc506 +#define regRCC_DEV2_PORT_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP7 0xc507 +#define regRCC_DEV2_PORT_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP8 0xc508 +#define regRCC_DEV2_PORT_STRAP8_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP9 0xc509 +#define regRCC_DEV2_PORT_STRAP9_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP10 0xc50a +#define regRCC_DEV2_PORT_STRAP10_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP11 0xc50b +#define regRCC_DEV2_PORT_STRAP11_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP12 0xc50c +#define regRCC_DEV2_PORT_STRAP12_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP13 0xc50d +#define regRCC_DEV2_PORT_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP14 0xc50e +#define regRCC_DEV2_PORT_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP15 0xc50f +#define regRCC_DEV2_PORT_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP16 0xc510 +#define regRCC_DEV2_PORT_STRAP16_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP0 0xc600 +#define regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP1 0xc601 +#define regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP2 0xc602 +#define regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP3 0xc603 +#define regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP4 0xc604 +#define regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP5 0xc605 +#define regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP6 0xc606 +#define regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP7 0xc607 +#define regRCC_STRAP1_RCC_BIF_STRAP7_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP8 0xc608 +#define regRCC_STRAP1_RCC_BIF_STRAP8_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP9 0xc609 +#define regRCC_STRAP1_RCC_BIF_STRAP9_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP10 0xc60a +#define regRCC_STRAP1_RCC_BIF_STRAP10_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP11 0xc60b +#define regRCC_STRAP1_RCC_BIF_STRAP11_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP12 0xc60c +#define regRCC_STRAP1_RCC_BIF_STRAP12_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP13 0xc60d +#define regRCC_STRAP1_RCC_BIF_STRAP13_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 0xd000 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 0xd001 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 0xd002 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 0xd003 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 0xd004 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 0xd005 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 0xd008 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 0xd009 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 0xd00d +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 0xd00e +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15 0xd00f +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16 0xd010 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17 0xd011 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18 0xd012 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP19 0xd013 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP19_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP22 0xd016 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP22_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP23 0xd017 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP23_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP24 0xd018 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP24_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 0xd080 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP1 0xd081 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP1_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 0xd082 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 0xd083 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 0xd084 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 0xd085 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 0xd086 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 0xd087 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP8 0xd088 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP8_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP9 0xd089 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP9_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP10 0xd08a +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP10_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP11 0xd08b +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP11_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP12 0xd08c +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP12_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP13 0xd08d +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP13_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP14 0xd08e +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP14_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP15 0xd08f +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP15_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP16 0xd090 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP16_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP17 0xd091 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP17_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP18 0xd092 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP18_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP19 0xd093 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP19_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20 0xd094 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21 0xd095 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23 0xd097 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24 0xd098 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP0 0xd100 +#define regRCC_DEV0_EPF2_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP2 0xd102 +#define regRCC_DEV0_EPF2_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP3 0xd103 +#define regRCC_DEV0_EPF2_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP4 0xd104 +#define regRCC_DEV0_EPF2_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP5 0xd105 +#define regRCC_DEV0_EPF2_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP6 0xd106 +#define regRCC_DEV0_EPF2_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP7 0xd107 +#define regRCC_DEV0_EPF2_STRAP7_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP9 0xd109 +#define regRCC_DEV0_EPF2_STRAP9_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP10 0xd10a +#define regRCC_DEV0_EPF2_STRAP10_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP11 0xd10b +#define regRCC_DEV0_EPF2_STRAP11_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP12 0xd10c +#define regRCC_DEV0_EPF2_STRAP12_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP13 0xd10d +#define regRCC_DEV0_EPF2_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP14 0xd10e +#define regRCC_DEV0_EPF2_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP15 0xd10f +#define regRCC_DEV0_EPF2_STRAP15_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP16 0xd110 +#define regRCC_DEV0_EPF2_STRAP16_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP20 0xd114 +#define regRCC_DEV0_EPF2_STRAP20_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP0 0xd180 +#define regRCC_DEV0_EPF3_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP2 0xd182 +#define regRCC_DEV0_EPF3_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP3 0xd183 +#define regRCC_DEV0_EPF3_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP4 0xd184 +#define regRCC_DEV0_EPF3_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP5 0xd185 +#define regRCC_DEV0_EPF3_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP6 0xd186 +#define regRCC_DEV0_EPF3_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP7 0xd187 +#define regRCC_DEV0_EPF3_STRAP7_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP9 0xd189 +#define regRCC_DEV0_EPF3_STRAP9_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP10 0xd18a +#define regRCC_DEV0_EPF3_STRAP10_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP11 0xd18b +#define regRCC_DEV0_EPF3_STRAP11_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP12 0xd18c +#define regRCC_DEV0_EPF3_STRAP12_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP13 0xd18d +#define regRCC_DEV0_EPF3_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP14 0xd18e +#define regRCC_DEV0_EPF3_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP15 0xd18f +#define regRCC_DEV0_EPF3_STRAP15_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP16 0xd190 +#define regRCC_DEV0_EPF3_STRAP16_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP20 0xd194 +#define regRCC_DEV0_EPF3_STRAP20_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP0 0xd200 +#define regRCC_DEV0_EPF4_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP2 0xd202 +#define regRCC_DEV0_EPF4_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP3 0xd203 +#define regRCC_DEV0_EPF4_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP4 0xd204 +#define regRCC_DEV0_EPF4_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP5 0xd205 +#define regRCC_DEV0_EPF4_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP6 0xd206 +#define regRCC_DEV0_EPF4_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP7 0xd207 +#define regRCC_DEV0_EPF4_STRAP7_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP9 0xd209 +#define regRCC_DEV0_EPF4_STRAP9_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP13 0xd20d +#define regRCC_DEV0_EPF4_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP14 0xd20e +#define regRCC_DEV0_EPF4_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP15 0xd20f +#define regRCC_DEV0_EPF4_STRAP15_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP16 0xd210 +#define regRCC_DEV0_EPF4_STRAP16_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP0 0xd280 +#define regRCC_DEV0_EPF5_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP2 0xd282 +#define regRCC_DEV0_EPF5_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP3 0xd283 +#define regRCC_DEV0_EPF5_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP4 0xd284 +#define regRCC_DEV0_EPF5_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP5 0xd285 +#define regRCC_DEV0_EPF5_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP6 0xd286 +#define regRCC_DEV0_EPF5_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP7 0xd287 +#define regRCC_DEV0_EPF5_STRAP7_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP9 0xd289 +#define regRCC_DEV0_EPF5_STRAP9_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP13 0xd28d +#define regRCC_DEV0_EPF5_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP14 0xd28e +#define regRCC_DEV0_EPF5_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP15 0xd28f +#define regRCC_DEV0_EPF5_STRAP15_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP16 0xd290 +#define regRCC_DEV0_EPF5_STRAP16_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP0 0xd300 +#define regRCC_DEV0_EPF6_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP2 0xd302 +#define regRCC_DEV0_EPF6_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP3 0xd303 +#define regRCC_DEV0_EPF6_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP4 0xd304 +#define regRCC_DEV0_EPF6_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP5 0xd305 +#define regRCC_DEV0_EPF6_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP6 0xd306 +#define regRCC_DEV0_EPF6_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP7 0xd307 +#define regRCC_DEV0_EPF6_STRAP7_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP9 0xd309 +#define regRCC_DEV0_EPF6_STRAP9_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP13 0xd30d +#define regRCC_DEV0_EPF6_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP14 0xd30e +#define regRCC_DEV0_EPF6_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP15 0xd30f +#define regRCC_DEV0_EPF6_STRAP15_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP16 0xd310 +#define regRCC_DEV0_EPF6_STRAP16_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP0 0xd380 +#define regRCC_DEV0_EPF7_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP2 0xd382 +#define regRCC_DEV0_EPF7_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP3 0xd383 +#define regRCC_DEV0_EPF7_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP4 0xd384 +#define regRCC_DEV0_EPF7_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP5 0xd385 +#define regRCC_DEV0_EPF7_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP6 0xd386 +#define regRCC_DEV0_EPF7_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP9 0xd389 +#define regRCC_DEV0_EPF7_STRAP9_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP13 0xd38d +#define regRCC_DEV0_EPF7_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP14 0xd38e +#define regRCC_DEV0_EPF7_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP15 0xd38f +#define regRCC_DEV0_EPF7_STRAP15_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP16 0xd390 +#define regRCC_DEV0_EPF7_STRAP16_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP0 0xd400 +#define regRCC_DEV1_EPF0_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP2 0xd402 +#define regRCC_DEV1_EPF0_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP3 0xd403 +#define regRCC_DEV1_EPF0_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP4 0xd404 +#define regRCC_DEV1_EPF0_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP5 0xd405 +#define regRCC_DEV1_EPF0_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP6 0xd406 +#define regRCC_DEV1_EPF0_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP9 0xd409 +#define regRCC_DEV1_EPF0_STRAP9_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP13 0xd40d +#define regRCC_DEV1_EPF0_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP14 0xd40e +#define regRCC_DEV1_EPF0_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP15 0xd40f +#define regRCC_DEV1_EPF0_STRAP15_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP16 0xd410 +#define regRCC_DEV1_EPF0_STRAP16_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP0 0xd480 +#define regRCC_DEV1_EPF1_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP1 0xd481 +#define regRCC_DEV1_EPF1_STRAP1_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP2 0xd482 +#define regRCC_DEV1_EPF1_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP3 0xd483 +#define regRCC_DEV1_EPF1_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP4 0xd484 +#define regRCC_DEV1_EPF1_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP5 0xd485 +#define regRCC_DEV1_EPF1_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP6 0xd486 +#define regRCC_DEV1_EPF1_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP7 0xd487 +#define regRCC_DEV1_EPF1_STRAP7_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP8 0xd488 +#define regRCC_DEV1_EPF1_STRAP8_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP9 0xd489 +#define regRCC_DEV1_EPF1_STRAP9_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP13 0xd48d +#define regRCC_DEV1_EPF1_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP14 0xd48e +#define regRCC_DEV1_EPF1_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP15 0xd48f +#define regRCC_DEV1_EPF1_STRAP15_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP16 0xd490 +#define regRCC_DEV1_EPF1_STRAP16_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP17 0xd491 +#define regRCC_DEV1_EPF1_STRAP17_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP18 0xd492 +#define regRCC_DEV1_EPF1_STRAP18_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP19 0xd493 +#define regRCC_DEV1_EPF1_STRAP19_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP20 0xd494 +#define regRCC_DEV1_EPF1_STRAP20_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP21 0xd495 +#define regRCC_DEV1_EPF1_STRAP21_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP0 0xd500 +#define regRCC_DEV1_EPF2_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP1 0xd501 +#define regRCC_DEV1_EPF2_STRAP1_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP2 0xd502 +#define regRCC_DEV1_EPF2_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP3 0xd503 +#define regRCC_DEV1_EPF2_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP4 0xd504 +#define regRCC_DEV1_EPF2_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP5 0xd505 +#define regRCC_DEV1_EPF2_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP6 0xd506 +#define regRCC_DEV1_EPF2_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP7 0xd507 +#define regRCC_DEV1_EPF2_STRAP7_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP8 0xd508 +#define regRCC_DEV1_EPF2_STRAP8_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP9 0xd509 +#define regRCC_DEV1_EPF2_STRAP9_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP13 0xd50d +#define regRCC_DEV1_EPF2_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP14 0xd50e +#define regRCC_DEV1_EPF2_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP15 0xd50f +#define regRCC_DEV1_EPF2_STRAP15_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP16 0xd510 +#define regRCC_DEV1_EPF2_STRAP16_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP17 0xd511 +#define regRCC_DEV1_EPF2_STRAP17_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP18 0xd512 +#define regRCC_DEV1_EPF2_STRAP18_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP19 0xd513 +#define regRCC_DEV1_EPF2_STRAP19_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP20 0xd514 +#define regRCC_DEV1_EPF2_STRAP20_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP21 0xd515 +#define regRCC_DEV1_EPF2_STRAP21_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP0 0xd580 +#define regRCC_DEV1_EPF3_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP2 0xd582 +#define regRCC_DEV1_EPF3_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP3 0xd583 +#define regRCC_DEV1_EPF3_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP4 0xd584 +#define regRCC_DEV1_EPF3_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP5 0xd585 +#define regRCC_DEV1_EPF3_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP6 0xd586 +#define regRCC_DEV1_EPF3_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP7 0xd587 +#define regRCC_DEV1_EPF3_STRAP7_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP13 0xd58d +#define regRCC_DEV1_EPF3_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP14 0xd58e +#define regRCC_DEV1_EPF3_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP15 0xd58f +#define regRCC_DEV1_EPF3_STRAP15_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP16 0xd590 +#define regRCC_DEV1_EPF3_STRAP16_BASE_IDX 5 +#define regRCC_DEV1_EPF4_STRAP6 0xd606 +#define regRCC_DEV1_EPF4_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF5_STRAP6 0xd686 +#define regRCC_DEV1_EPF5_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF6_STRAP6 0xd706 +#define regRCC_DEV1_EPF6_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP0 0xd800 +#define regRCC_DEV2_EPF0_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP2 0xd802 +#define regRCC_DEV2_EPF0_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP3 0xd803 +#define regRCC_DEV2_EPF0_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP4 0xd804 +#define regRCC_DEV2_EPF0_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP5 0xd805 +#define regRCC_DEV2_EPF0_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP6 0xd806 +#define regRCC_DEV2_EPF0_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP7 0xd807 +#define regRCC_DEV2_EPF0_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP13 0xd80d +#define regRCC_DEV2_EPF0_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP14 0xd80e +#define regRCC_DEV2_EPF0_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP15 0xd80f +#define regRCC_DEV2_EPF0_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP16 0xd810 +#define regRCC_DEV2_EPF0_STRAP16_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP18 0xd812 +#define regRCC_DEV2_EPF0_STRAP18_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP25 0xd819 +#define regRCC_DEV2_EPF0_STRAP25_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP26 0xd81a +#define regRCC_DEV2_EPF0_STRAP26_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP0 0xd880 +#define regRCC_DEV2_EPF1_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP2 0xd882 +#define regRCC_DEV2_EPF1_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP3 0xd883 +#define regRCC_DEV2_EPF1_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP4 0xd884 +#define regRCC_DEV2_EPF1_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP5 0xd885 +#define regRCC_DEV2_EPF1_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP6 0xd886 +#define regRCC_DEV2_EPF1_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP7 0xd887 +#define regRCC_DEV2_EPF1_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP13 0xd88d +#define regRCC_DEV2_EPF1_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP14 0xd88e +#define regRCC_DEV2_EPF1_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP15 0xd88f +#define regRCC_DEV2_EPF1_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP16 0xd890 +#define regRCC_DEV2_EPF1_STRAP16_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP0 0xd900 +#define regRCC_DEV2_EPF2_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP2 0xd902 +#define regRCC_DEV2_EPF2_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP3 0xd903 +#define regRCC_DEV2_EPF2_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP4 0xd904 +#define regRCC_DEV2_EPF2_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP5 0xd905 +#define regRCC_DEV2_EPF2_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP6 0xd906 +#define regRCC_DEV2_EPF2_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP7 0xd907 +#define regRCC_DEV2_EPF2_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP13 0xd90d +#define regRCC_DEV2_EPF2_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP14 0xd90e +#define regRCC_DEV2_EPF2_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP15 0xd90f +#define regRCC_DEV2_EPF2_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP16 0xd910 +#define regRCC_DEV2_EPF2_STRAP16_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP0 0xd980 +#define regRCC_DEV2_EPF3_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP2 0xd982 +#define regRCC_DEV2_EPF3_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP3 0xd983 +#define regRCC_DEV2_EPF3_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP4 0xd984 +#define regRCC_DEV2_EPF3_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP5 0xd985 +#define regRCC_DEV2_EPF3_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP6 0xd986 +#define regRCC_DEV2_EPF3_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP7 0xd987 +#define regRCC_DEV2_EPF3_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP13 0xd98d +#define regRCC_DEV2_EPF3_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP14 0xd98e +#define regRCC_DEV2_EPF3_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP15 0xd98f +#define regRCC_DEV2_EPF3_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP16 0xd990 +#define regRCC_DEV2_EPF3_STRAP16_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP0 0xda00 +#define regRCC_DEV2_EPF4_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP2 0xda02 +#define regRCC_DEV2_EPF4_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP3 0xda03 +#define regRCC_DEV2_EPF4_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP4 0xda04 +#define regRCC_DEV2_EPF4_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP5 0xda05 +#define regRCC_DEV2_EPF4_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP6 0xda06 +#define regRCC_DEV2_EPF4_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP7 0xda07 +#define regRCC_DEV2_EPF4_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP13 0xda0d +#define regRCC_DEV2_EPF4_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP14 0xda0e +#define regRCC_DEV2_EPF4_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP15 0xda0f +#define regRCC_DEV2_EPF4_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP16 0xda10 +#define regRCC_DEV2_EPF4_STRAP16_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP0 0xda80 +#define regRCC_DEV2_EPF5_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP2 0xda82 +#define regRCC_DEV2_EPF5_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP3 0xda83 +#define regRCC_DEV2_EPF5_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP4 0xda84 +#define regRCC_DEV2_EPF5_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP5 0xda85 +#define regRCC_DEV2_EPF5_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP6 0xda86 +#define regRCC_DEV2_EPF5_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP7 0xda87 +#define regRCC_DEV2_EPF5_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP13 0xda8d +#define regRCC_DEV2_EPF5_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP14 0xda8e +#define regRCC_DEV2_EPF5_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP15 0xda8f +#define regRCC_DEV2_EPF5_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP16 0xda90 +#define regRCC_DEV2_EPF5_STRAP16_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP0 0xdb00 +#define regRCC_DEV2_EPF6_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP2 0xdb02 +#define regRCC_DEV2_EPF6_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP3 0xdb03 +#define regRCC_DEV2_EPF6_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP4 0xdb04 +#define regRCC_DEV2_EPF6_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP5 0xdb05 +#define regRCC_DEV2_EPF6_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP6 0xdb06 +#define regRCC_DEV2_EPF6_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP7 0xdb07 +#define regRCC_DEV2_EPF6_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP13 0xdb0d +#define regRCC_DEV2_EPF6_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP14 0xdb0e +#define regRCC_DEV2_EPF6_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP15 0xdb0f +#define regRCC_DEV2_EPF6_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP16 0xdb10 +#define regRCC_DEV2_EPF6_STRAP16_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_rst_bif_rst_regblk +// base address: 0x10100000 +#define regHARD_RST_CTRL 0xe000 +#define regHARD_RST_CTRL_BASE_IDX 5 +#define regSELF_SOFT_RST 0xe002 +#define regSELF_SOFT_RST_BASE_IDX 5 +#define regBIF_GFX_DRV_VPU_RST 0xe003 +#define regBIF_GFX_DRV_VPU_RST_BASE_IDX 5 +#define regBIF_RST_MISC_CTRL 0xe004 +#define regBIF_RST_MISC_CTRL_BASE_IDX 5 +#define regBIF_RST_MISC_CTRL2 0xe005 +#define regBIF_RST_MISC_CTRL2_BASE_IDX 5 +#define regBIF_RST_MISC_CTRL3 0xe006 +#define regBIF_RST_MISC_CTRL3_BASE_IDX 5 +#define regDEV0_PF0_FLR_RST_CTRL 0xe008 +#define regDEV0_PF0_FLR_RST_CTRL_BASE_IDX 5 +#define regDEV0_PF1_FLR_RST_CTRL 0xe009 +#define regDEV0_PF1_FLR_RST_CTRL_BASE_IDX 5 +#define regBIF_INST_RESET_INTR_STS 0xe010 +#define regBIF_INST_RESET_INTR_STS_BASE_IDX 5 +#define regBIF_PF_FLR_INTR_STS 0xe011 +#define regBIF_PF_FLR_INTR_STS_BASE_IDX 5 +#define regBIF_D3HOTD0_INTR_STS 0xe012 +#define regBIF_D3HOTD0_INTR_STS_BASE_IDX 5 +#define regBIF_POWER_INTR_STS 0xe014 +#define regBIF_POWER_INTR_STS_BASE_IDX 5 +#define regBIF_PF_DSTATE_INTR_STS 0xe015 +#define regBIF_PF_DSTATE_INTR_STS_BASE_IDX 5 +#define regSELF_SOFT_RST_2 0xe016 +#define regSELF_SOFT_RST_2_BASE_IDX 5 +#define regSION_SDP_PORT_RST 0xe017 +#define regSION_SDP_PORT_RST_BASE_IDX 5 +#define regBIF_INST_RESET_INTR_MASK 0xe020 +#define regBIF_INST_RESET_INTR_MASK_BASE_IDX 5 +#define regBIF_PF_FLR_INTR_MASK 0xe021 +#define regBIF_PF_FLR_INTR_MASK_BASE_IDX 5 +#define regBIF_D3HOTD0_INTR_MASK 0xe022 +#define regBIF_D3HOTD0_INTR_MASK_BASE_IDX 5 +#define regBIF_POWER_INTR_MASK 0xe024 +#define regBIF_POWER_INTR_MASK_BASE_IDX 5 +#define regBIF_PF_DSTATE_INTR_MASK 0xe025 +#define regBIF_PF_DSTATE_INTR_MASK_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF_FLR_INTR_MASK 0xe028 +#define regBIF_DEV0_PF0_VF_FLR_INTR_MASK_BASE_IDX 5 +#define regBIF_DEV0_PF1_VF_FLR_INTR_MASK 0xe029 +#define regBIF_DEV0_PF1_VF_FLR_INTR_MASK_BASE_IDX 5 +#define regBIF_PF_FLR_RST 0xe040 +#define regBIF_PF_FLR_RST_BASE_IDX 5 +#define regBIF_PF_FLR_PROTECT 0xe042 +#define regBIF_PF_FLR_PROTECT_BASE_IDX 5 +#define regBIF_PF_FLR_PROTECT3 0xe044 +#define regBIF_PF_FLR_PROTECT3_BASE_IDX 5 +#define regBIF_DEV0_PF0_DSTATE_VALUE 0xe050 +#define regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX 5 +#define regBIF_DEV0_PF1_DSTATE_VALUE 0xe051 +#define regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX 5 +#define regGFX_RST_CNTL_IND0 0xe05d +#define regGFX_RST_CNTL_IND0_BASE_IDX 5 +#define regGFX_RST_CNTL_SOFT_PF 0xe05e +#define regGFX_RST_CNTL_SOFT_PF_BASE_IDX 5 +#define regGFX_RST_CNTL_IND1 0xe05f +#define regGFX_RST_CNTL_IND1_BASE_IDX 5 +#define regGFX_RST_CNTL_IND2 0xe060 +#define regGFX_RST_CNTL_IND2_BASE_IDX 5 +#define regGFX_RST_CNTL_IND3 0xe061 +#define regGFX_RST_CNTL_IND3_BASE_IDX 5 +#define regGFX_RST_CNTL_IND4 0xe062 +#define regGFX_RST_CNTL_IND4_BASE_IDX 5 +#define regGFX_RST_CNTL_IND5 0xe063 +#define regGFX_RST_CNTL_IND5_BASE_IDX 5 +#define regGFX_RST_CNTL_IND6 0xe064 +#define regGFX_RST_CNTL_IND6_BASE_IDX 5 +#define regGFX_RST_CNTL_IND7 0xe065 +#define regGFX_RST_CNTL_IND7_BASE_IDX 5 +#define regGFX_RST_CNTL_IND8 0xe066 +#define regGFX_RST_CNTL_IND8_BASE_IDX 5 +#define regDEV0_PF0_D3HOTD0_RST_CTRL 0xe07e +#define regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX 5 +#define regDEV0_PF1_D3HOTD0_RST_CTRL 0xe07f +#define regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF_FLR_PROTECT 0xe086 +#define regBIF_DEV0_PF0_VF_FLR_PROTECT_BASE_IDX 5 +#define regBIF_DEV0_PF1_VF_FLR_PROTECT 0xe087 +#define regBIF_DEV0_PF1_VF_FLR_PROTECT_BASE_IDX 5 +#define regBIF_SRIOVEN_SET_INTR_STS 0xe088 +#define regBIF_SRIOVEN_SET_INTR_STS_BASE_IDX 5 +#define regBIF_SRIOVEN_CLR_INTR_STS 0xe089 +#define regBIF_SRIOVEN_CLR_INTR_STS_BASE_IDX 5 +#define regBIF_SRIOVEN_SET_INTR_MASK 0xe08a +#define regBIF_SRIOVEN_SET_INTR_MASK_BASE_IDX 5 +#define regBIF_SRIOVEN_CLR_INTR_MASK 0xe08b +#define regBIF_SRIOVEN_CLR_INTR_MASK_BASE_IDX 5 +#define regBIF_PORT0_DSTATE_VALUE 0xe230 +#define regBIF_PORT0_DSTATE_VALUE_BASE_IDX 5 +#define regBIF_DEV0_PF0_RST_VF_FLR_IDLE 0xe2c4 +#define regBIF_DEV0_PF0_RST_VF_FLR_IDLE_BASE_IDX 5 +#define regBIF_DEV0_PF1_RST_VF_FLR_IDLE 0xe2c5 +#define regBIF_DEV0_PF1_RST_VF_FLR_IDLE_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF_FLR_INTR_STS 0xe2c8 +#define regBIF_DEV0_PF0_VF_FLR_INTR_STS_BASE_IDX 5 +#define regBIF_DEV0_PF1_VF_FLR_INTR_STS 0xe2c9 +#define regBIF_DEV0_PF1_VF_FLR_INTR_STS_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF_FLR_RST 0xe2cc +#define regBIF_DEV0_PF0_VF_FLR_RST_BASE_IDX 5 +#define regBIF_DEV0_PF1_VF_FLR_RST 0xe2cd +#define regBIF_DEV0_PF1_VF_FLR_RST_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_misc_bif_misc_regblk +// base address: 0x10100000 +#define regDOE_PRV_CTRL0_DEV0F0 0xc806 +#define regDOE_PRV_CTRL0_DEV0F0_BASE_IDX 5 +#define regDOE_PRV_CMD_DEV0F0 0xc807 +#define regDOE_PRV_CMD_DEV0F0_BASE_IDX 5 +#define regDOE_PRV_WDATA_DEV0F0 0xc808 +#define regDOE_PRV_WDATA_DEV0F0_BASE_IDX 5 +#define regDOE_PRV_STS_DEV0F0 0xc809 +#define regDOE_PRV_STS_DEV0F0_BASE_IDX 5 +#define regDOE_PRV_RDATA_DEV0F0 0xc80a +#define regDOE_PRV_RDATA_DEV0F0_BASE_IDX 5 +#define regNBIF_RC_INTR_CNTL 0xc81b +#define regNBIF_RC_INTR_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_TDISP_CNTL 0xc8c0 +#define regBIF_DEV0_PF0_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF1_TDISP_CNTL 0xc8c1 +#define regBIF_DEV0_PF1_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF0_TDISP_CNTL 0xc8d0 +#define regBIF_DEV0_PF0_VF0_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF1_TDISP_CNTL 0xc8d1 +#define regBIF_DEV0_PF0_VF1_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF2_TDISP_CNTL 0xc8d2 +#define regBIF_DEV0_PF0_VF2_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF3_TDISP_CNTL 0xc8d3 +#define regBIF_DEV0_PF0_VF3_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF4_TDISP_CNTL 0xc8d4 +#define regBIF_DEV0_PF0_VF4_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF5_TDISP_CNTL 0xc8d5 +#define regBIF_DEV0_PF0_VF5_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF6_TDISP_CNTL 0xc8d6 +#define regBIF_DEV0_PF0_VF6_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF7_TDISP_CNTL 0xc8d7 +#define regBIF_DEV0_PF0_VF7_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF1_VF0_TDISP_CNTL 0xc8d8 +#define regBIF_DEV0_PF1_VF0_TDISP_CNTL_BASE_IDX 5 +#define regBIF_TDISP_ERROR_DEV0_PF0_INST0 0xc9d0 +#define regBIF_TDISP_ERROR_DEV0_PF0_INST0_BASE_IDX 5 +#define regBIF_TDISP_ERROR_DEV0_PF1_INST0 0xc9d1 +#define regBIF_TDISP_ERROR_DEV0_PF1_INST0_BASE_IDX 5 +#define regBIF_TDISP_UNLOCKED_DEV0_PF0_INST0 0xc9d8 +#define regBIF_TDISP_UNLOCKED_DEV0_PF0_INST0_BASE_IDX 5 +#define regBIF_TDISP_UNLOCKED_DEV0_PF1_INST0 0xc9d9 +#define regBIF_TDISP_UNLOCKED_DEV0_PF1_INST0_BASE_IDX 5 +#define regBIF_TDISP_MISC_CNTL_DEV0 0xc9e0 +#define regBIF_TDISP_MISC_CNTL_DEV0_BASE_IDX 5 +#define regBIF_TDISP_MISC_CNTL 0xc9e4 +#define regBIF_TDISP_MISC_CNTL_BASE_IDX 5 +#define regBIF_RCC_IDE_TDISP_CNTL 0xc9e5 +#define regBIF_RCC_IDE_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31 0xca00 +#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31 0xca01 +#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31 0xca02 +#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31 0xca03 +#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31 0xca04 +#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31 0xca05 +#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31 0xca06 +#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31 0xca07 +#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31 0xca08 +#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31 0xca09 +#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31 0xca0a +#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31 0xca0b +#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31 0xca0c +#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31 0xca0d +#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31 0xca0e +#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31 0xca0f +#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31 0xca10 +#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31 0xca11 +#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31 0xca12 +#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31 0xca13 +#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31 0xca14 +#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31 0xca15 +#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31 0xca16 +#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31 0xca17 +#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31 0xca18 +#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31 0xca19 +#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31 0xca1a +#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_SYSTEM_EN 0xca1b +#define regBIF_SYSTEM_EN_BASE_IDX 5 +#define regBIF_MASK_SYSTEM_EN 0xca1c +#define regBIF_MASK_SYSTEM_EN_BASE_IDX 5 +#define regGPUIOV_SCH0 0xcb40 +#define regGPUIOV_SCH0_BASE_IDX 5 +#define regGPUIOV_SCH1 0xcb41 +#define regGPUIOV_SCH1_BASE_IDX 5 +#define regGPUIOV_SCH2 0xcb42 +#define regGPUIOV_SCH2_BASE_IDX 5 +#define regGPUIOV_SCH3 0xcb43 +#define regGPUIOV_SCH3_BASE_IDX 5 +#define regGPUIOV_SCH4 0xcb44 +#define regGPUIOV_SCH4_BASE_IDX 5 +#define regGPUIOV_SCH5 0xcb45 +#define regGPUIOV_SCH5_BASE_IDX 5 +#define regGPUIOV_SCH6 0xcb46 +#define regGPUIOV_SCH6_BASE_IDX 5 +#define regGPUIOV_SCH7 0xcb47 +#define regGPUIOV_SCH7_BASE_IDX 5 +#define regGPUIOV_SCH8 0xcb48 +#define regGPUIOV_SCH8_BASE_IDX 5 +#define regGPUIOV_SCH9 0xcb49 +#define regGPUIOV_SCH9_BASE_IDX 5 +#define regGPUIOV_SCH10 0xcb4a +#define regGPUIOV_SCH10_BASE_IDX 5 +#define regGPUIOV_SCH11 0xcb4b +#define regGPUIOV_SCH11_BASE_IDX 5 +#define regGPUIOV_SCH12 0xcb4c +#define regGPUIOV_SCH12_BASE_IDX 5 +#define regGPUIOV_SCH13 0xcb4d +#define regGPUIOV_SCH13_BASE_IDX 5 +#define regGPUIOV_SCH14 0xcb4e +#define regGPUIOV_SCH14_BASE_IDX 5 +#define regGPUIOV_SCH15 0xcb4f +#define regGPUIOV_SCH15_BASE_IDX 5 +#define regGPUIOV_SCH16 0xcb50 +#define regGPUIOV_SCH16_BASE_IDX 5 +#define regGPUIOV_SCH17 0xcb51 +#define regGPUIOV_SCH17_BASE_IDX 5 +#define regGPUIOV_SCH18 0xcb52 +#define regGPUIOV_SCH18_BASE_IDX 5 +#define regGPUIOV_SCH19 0xcb53 +#define regGPUIOV_SCH19_BASE_IDX 5 +#define regGPUIOV_MMHUB_P2P_CNTL 0xcb54 +#define regGPUIOV_MMHUB_P2P_CNTL_BASE_IDX 5 +#define regBIF_AER_INTR_CTRL 0xcb55 +#define regBIF_AER_INTR_CTRL_BASE_IDX 5 +#define regBIF_AER_INTR_STS 0xcb56 +#define regBIF_AER_INTR_STS_BASE_IDX 5 +#define regBIF_PCIE_MSG_CTRL 0xcb57 +#define regBIF_PCIE_MSG_CTRL_BASE_IDX 5 +#define regBIF_PCIE_MSG_HEADER_DW0 0xcb58 +#define regBIF_PCIE_MSG_HEADER_DW0_BASE_IDX 5 +#define regBIF_PCIE_MSG_HEADER_DW1 0xcb59 +#define regBIF_PCIE_MSG_HEADER_DW1_BASE_IDX 5 +#define regBIF_PCIE_MSG_HEADER_DW2 0xcb5a +#define regBIF_PCIE_MSG_HEADER_DW2_BASE_IDX 5 +#define regBIF_PCIE_MSG_HEADER_DW3 0xcb5b +#define regBIF_PCIE_MSG_HEADER_DW3_BASE_IDX 5 +#define regBIF_PCIE_MSG_DATA_DW0 0xcb5c +#define regBIF_PCIE_MSG_DATA_DW0_BASE_IDX 5 +#define regBIF_PCIE_MSG_DATA_DW1 0xcb5d +#define regBIF_PCIE_MSG_DATA_DW1_BASE_IDX 5 +#define regBIF_PCIE_MSG_DATA_DW2 0xcb5e +#define regBIF_PCIE_MSG_DATA_DW2_BASE_IDX 5 +#define regBIF_PCIE_MSG_DATA_DW3 0xcb5f +#define regBIF_PCIE_MSG_DATA_DW3_BASE_IDX 5 +#define regBIFC_SEC_AER_SMN_CTRL0 0xcb60 +#define regBIFC_SEC_AER_SMN_CTRL0_BASE_IDX 5 +#define regBIFC_SEC_AER_SMN_CTRL1 0xcb61 +#define regBIFC_SEC_AER_SMN_CTRL1_BASE_IDX 5 +#define regBIFC_SEC_AER_SMN_CTRL2 0xcb62 +#define regBIFC_SEC_AER_SMN_CTRL2_BASE_IDX 5 +#define regBIF_PCIE_ERR_CTRL0 0xcb63 +#define regBIF_PCIE_ERR_CTRL0_BASE_IDX 5 +#define regBIF_PCIE_ERR_CTRL1 0xcb64 +#define regBIF_PCIE_ERR_CTRL1_BASE_IDX 5 +#define regBIF_PCIE_ERR_CTRL2 0xcb65 +#define regBIF_PCIE_ERR_CTRL2_BASE_IDX 5 +#define regBIF_AER_UNCORR_ERR_STATUS 0xcb66 +#define regBIF_AER_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_AER_UNCORR_ERR_MASK 0xcb67 +#define regBIF_AER_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_AER_UNCORR_ERR_SEVERITY 0xcb68 +#define regBIF_AER_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_AER_CORR_ERR_STATUS 0xcb69 +#define regBIF_AER_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_AER_CORR_ERR_MASK 0xcb6a +#define regBIF_AER_CORR_ERR_MASK_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_0 0xcb6b +#define regRCC_EP_STICKY_RESTORE_0_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_1 0xcb6c +#define regRCC_EP_STICKY_RESTORE_1_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_2 0xcb6d +#define regRCC_EP_STICKY_RESTORE_2_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_3 0xcb6e +#define regRCC_EP_STICKY_RESTORE_3_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_4 0xcb6f +#define regRCC_EP_STICKY_RESTORE_4_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_5 0xcb70 +#define regRCC_EP_STICKY_RESTORE_5_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_6 0xcb71 +#define regRCC_EP_STICKY_RESTORE_6_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_7 0xcb72 +#define regRCC_EP_STICKY_RESTORE_7_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_8 0xcb73 +#define regRCC_EP_STICKY_RESTORE_8_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_9 0xcb74 +#define regRCC_EP_STICKY_RESTORE_9_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_10 0xcb75 +#define regRCC_EP_STICKY_RESTORE_10_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_11 0xcb76 +#define regRCC_EP_STICKY_RESTORE_11_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_12 0xcb77 +#define regRCC_EP_STICKY_RESTORE_12_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_13 0xcb78 +#define regRCC_EP_STICKY_RESTORE_13_BASE_IDX 5 +#define regBIF_DEVICE3_STATUS 0xcb79 +#define regBIF_DEVICE3_STATUS_BASE_IDX 5 +#define regBIFC_SEC_MCTP_SMN_CTRL0 0xcb81 +#define regBIFC_SEC_MCTP_SMN_CTRL0_BASE_IDX 5 +#define regBIFC_SEC_MCTP_SMN_CTRL1 0xcb82 +#define regBIFC_SEC_MCTP_SMN_CTRL1_BASE_IDX 5 +#define regNBIF_MCTP_GENERIC_CNTL 0xcc08 +#define regNBIF_MCTP_GENERIC_CNTL_BASE_IDX 5 +#define regNBIF_MCTP_GENERIC_STATUS 0xcc09 +#define regNBIF_MCTP_GENERIC_STATUS_BASE_IDX 5 +#define regSDPVW_UPDATE_EN 0xcc22 +#define regSDPVW_UPDATE_EN_BASE_IDX 5 +#define regREGS_ROM_OFFSET_CTRL 0xcc23 +#define regREGS_ROM_OFFSET_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_POISON_DATA_DROP_CTRL 0xcc24 +#define regBIFL_SEC_RAS_POISON_DATA_DROP_CTRL_BASE_IDX 5 +#define regREGS_INDEX_DATA_PAIR_CTRL 0xcc25 +#define regREGS_INDEX_DATA_PAIR_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_RESPONSE_DROP_CTRL 0xcc26 +#define regBIFL_SEC_RAS_RESPONSE_DROP_CTRL_BASE_IDX 5 +#define regBIFC_SEC_MCA_SMN_CTRL0 0xcc44 +#define regBIFC_SEC_MCA_SMN_CTRL0_BASE_IDX 5 +#define regBIFC_SEC_MCA_SMN_CTRL1 0xcc45 +#define regBIFC_SEC_MCA_SMN_CTRL1_BASE_IDX 5 +#define regBIFL_SEC_RAS_POISON_DBUG_CTRL 0xcc46 +#define regBIFL_SEC_RAS_POISON_DBUG_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_PARITY_DBUG_CTRL 0xcc47 +#define regBIFL_SEC_RAS_PARITY_DBUG_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_NTB_DBUG_CTRL 0xcc48 +#define regBIFL_SEC_RAS_NTB_DBUG_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL 0xcc4a +#define regBIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_TIMEOUT_DBUG_CTRL 0xcc4c +#define regBIFL_SEC_RAS_TIMEOUT_DBUG_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL 0xcc5b +#define regBIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL 0xcc5c +#define regBIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL 0xcc5d +#define regBIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL 0xcc5e +#define regBIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL 0xcc5f +#define regBIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL 0xcc60 +#define regBIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL 0xcc61 +#define regBIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL 0xcc62 +#define regBIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL 0xcc63 +#define regBIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL 0xcc64 +#define regBIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL 0xcc65 +#define regBIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL 0xcc66 +#define regBIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL 0xcc67 +#define regBIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL 0xcc68 +#define regBIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL 0xcc69 +#define regBIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL 0xcc6a +#define regBIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL 0xcc6b +#define regBIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL 0xcc6c +#define regBIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL 0xcc6d +#define regBIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL 0xcc6e +#define regBIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL 0xcc6f +#define regBIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL 0xcc70 +#define regBIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL 0xcc71 +#define regBIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL 0xcc72 +#define regBIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL 0xcc73 +#define regBIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL 0xcc74 +#define regBIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL 0xcc75 +#define regBIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL 0xcc76 +#define regBIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL 0xcc77 +#define regBIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL 0xcc78 +#define regBIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL 0xcc79 +#define regBIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL 0xcc7a +#define regBIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL 0xcc7b +#define regBIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL 0xcc7c +#define regBIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL 0xcc7d +#define regBIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL 0xcc7e +#define regBIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL 0xcc7f +#define regBIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL 0xcc80 +#define regBIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL 0xcc81 +#define regBIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL 0xcc82 +#define regBIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL_BASE_IDX 5 +#define regNBIF_STRAP_BIOS_CNTL 0xcc89 +#define regNBIF_STRAP_BIOS_CNTL_BASE_IDX 5 +#define regSMN_MST_NORMAL_SECURITY 0xcdea +#define regSMN_MST_NORMAL_SECURITY_BASE_IDX 5 +#define regOVERRIDE_TYPE_FOR_CHAIN_CTRL 0xcdec +#define regOVERRIDE_TYPE_FOR_CHAIN_CTRL_BASE_IDX 5 +#define regPROCESSING_HINT_SUPPORT_CNTL 0xcded +#define regPROCESSING_HINT_SUPPORT_CNTL_BASE_IDX 5 +#define regDEV0_PF0_VF0_MMIO0_FENCE 0xce40 +#define regDEV0_PF0_VF0_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF1_MMIO0_FENCE 0xce41 +#define regDEV0_PF0_VF1_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF2_MMIO0_FENCE 0xce42 +#define regDEV0_PF0_VF2_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF3_MMIO0_FENCE 0xce43 +#define regDEV0_PF0_VF3_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF4_MMIO0_FENCE 0xce44 +#define regDEV0_PF0_VF4_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF5_MMIO0_FENCE 0xce45 +#define regDEV0_PF0_VF5_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF6_MMIO0_FENCE 0xce46 +#define regDEV0_PF0_VF6_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF7_MMIO0_FENCE 0xce47 +#define regDEV0_PF0_VF7_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_START 0xce48 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_END 0xce49 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_END_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_START 0xce4a +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_END 0xce4b +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_END_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_START 0xce4c +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_END 0xce4d +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_END_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_START 0xce4e +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_END 0xce4f +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_END_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_START 0xce50 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_END 0xce51 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_END_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_START 0xce52 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_END 0xce53 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_END_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_START 0xce54 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_END 0xce55 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_END_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_START 0xce56 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_END 0xce57 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_END_BASE_IDX 5 +#define regDEV0_PF1_VF0_MMIO0_FENCE 0xce58 +#define regDEV0_PF1_VF0_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_START 0xce59 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_START_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_END 0xce5a +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_END_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_START 0xce5b +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_START_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_END 0xce5c +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_END_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_START 0xce5d +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_START_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_END 0xce5e +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_END_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_START 0xce5f +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_START_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_END 0xce60 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_WR 0xce61 +#define regDEV0_PF0_PF_MMIO0_FENCE_WR_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RD 0xce62 +#define regDEV0_PF0_PF_MMIO0_FENCE_RD_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_START 0xce63 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_END 0xce64 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_START 0xce65 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_END 0xce66 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_START 0xce67 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_END 0xce68 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_START 0xce69 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_END 0xce6a +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_START 0xce6b +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_END 0xce6c +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_START 0xce6d +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_END 0xce6e +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_START 0xce6f +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_END 0xce70 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_START 0xce71 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_END 0xce72 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_START 0xce73 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_END 0xce74 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_START 0xce75 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_END 0xce76 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_START 0xce77 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_END 0xce78 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_START 0xce79 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_END 0xce7a +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_START 0xce7b +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_END 0xce7c +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_START 0xce7d +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_END 0xce7e +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_START 0xce7f +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_END 0xce80 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_START 0xce81 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_END 0xce82 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_START 0xce83 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_END 0xce84 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_START 0xce85 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_END 0xce86 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_START 0xce87 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_END 0xce88 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_START 0xce89 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_END 0xce8a +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_START 0xce8b +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_END 0xce8c +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_START 0xce8d +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_END 0xce8e +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_START 0xce8f +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_END 0xce90 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_START 0xce91 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_END 0xce92 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_START 0xce93 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_END 0xce94 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_START 0xce95 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_END 0xce96 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_START 0xce97 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_END 0xce98 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_START 0xce99 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_END 0xce9a +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_START 0xce9b +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_END 0xce9c +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_START 0xce9d +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_END 0xce9e +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_START 0xce9f +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_END 0xcea0 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_START 0xcea1 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_END 0xcea2 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_END_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_WR 0xcea3 +#define regDEV0_PF1_PF_MMIO0_FENCE_WR_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RD 0xcea4 +#define regDEV0_PF1_PF_MMIO0_FENCE_RD_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_START 0xcea5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_START_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_END 0xcea6 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_END_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_START 0xcea7 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_START_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_END 0xcea8 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_END_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_START 0xcea9 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_START_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_END 0xceaa +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_END_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_START 0xceab +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_START_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_END 0xceac +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_END_BASE_IDX 5 +#define regMISC_SCRATCH 0xe800 +#define regMISC_SCRATCH_BASE_IDX 5 +#define regINTR_LINE_POLARITY 0xe801 +#define regINTR_LINE_POLARITY_BASE_IDX 5 +#define regINTR_LINE_ENABLE 0xe802 +#define regINTR_LINE_ENABLE_BASE_IDX 5 +#define regOUTSTANDING_VC_ALLOC 0xe803 +#define regOUTSTANDING_VC_ALLOC_BASE_IDX 5 +#define regBIFC_MISC_CTRL0 0xe804 +#define regBIFC_MISC_CTRL0_BASE_IDX 5 +#define regBIFC_MISC_CTRL1 0xe805 +#define regBIFC_MISC_CTRL1_BASE_IDX 5 +#define regBIFC_BME_ERR_LOG_LB 0xe806 +#define regBIFC_BME_ERR_LOG_LB_BASE_IDX 5 +#define regBIFC_LC_TIMER_CTRL 0xe807 +#define regBIFC_LC_TIMER_CTRL_BASE_IDX 5 +#define regBIFC_RCCBIH_BME_ERR_LOG0 0xe808 +#define regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX 5 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0xe80a +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX 5 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0xe80b +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX 5 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0xe80c +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX 5 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0xe80d +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX 5 +#define regBIFC_DMA_ATTR_CNTL2_DEV0 0xe81a +#define regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX 5 +#define regBIFC_MISC_CTRL2 0xe822 +#define regBIFC_MISC_CTRL2_BASE_IDX 5 +#define regBME_DUMMY_CNTL_0 0xe825 +#define regBME_DUMMY_CNTL_0_BASE_IDX 5 +#define regBIFC_THT_CNTL 0xe827 +#define regBIFC_THT_CNTL_BASE_IDX 5 +#define regBIFC_HSTARB_CNTL 0xe828 +#define regBIFC_HSTARB_CNTL_BASE_IDX 5 +#define regBIFC_GSI_CNTL 0xe829 +#define regBIFC_GSI_CNTL_BASE_IDX 5 +#define regBIFC_PCIEFUNC_CNTL 0xe82a +#define regBIFC_PCIEFUNC_CNTL_BASE_IDX 5 +#define regBIFC_PASID_CHECK_DIS 0xe82b +#define regBIFC_PASID_CHECK_DIS_BASE_IDX 5 +#define regBIFC_SDP_CNTL_0 0xe82c +#define regBIFC_SDP_CNTL_0_BASE_IDX 5 +#define regBIFC_SDP_CNTL_1 0xe82d +#define regBIFC_SDP_CNTL_1_BASE_IDX 5 +#define regBIFC_PASID_STS 0xe82e +#define regBIFC_PASID_STS_BASE_IDX 5 +#define regBIFC_ATHUB_ACT_CNTL 0xe82f +#define regBIFC_ATHUB_ACT_CNTL_BASE_IDX 5 +#define regBIFC_PERF_CNTL_0 0xe830 +#define regBIFC_PERF_CNTL_0_BASE_IDX 5 +#define regBIF_MISC_BIFC_PERF_CNTL_1 0xe831 +#define regBIF_MISC_BIFC_PERF_CNTL_1_BASE_IDX 5 +#define regBIFC_PERF_CNT_MMIO_RD_L32BIT 0xe832 +#define regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX 5 +#define regBIFC_PERF_CNT_MMIO_WR_L32BIT 0xe833 +#define regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX 5 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT 0xe834 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX 5 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT 0xe835 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX 5 +#define regNBIF_REGIF_ERRSET_CTRL 0xe836 +#define regNBIF_REGIF_ERRSET_CTRL_BASE_IDX 5 +#define regBIFC_SDP_CNTL_2 0xe837 +#define regBIFC_SDP_CNTL_2_BASE_IDX 5 +#define regNBIF_PGMST_CTRL 0xe838 +#define regNBIF_PGMST_CTRL_BASE_IDX 5 +#define regNBIF_PGSLV_CTRL 0xe839 +#define regNBIF_PGSLV_CTRL_BASE_IDX 5 +#define regNBIF_PG_MISC_CTRL 0xe83a +#define regNBIF_PG_MISC_CTRL_BASE_IDX 5 +#define regSMN_MST_EP_CNTL3 0xe83c +#define regSMN_MST_EP_CNTL3_BASE_IDX 5 +#define regSMN_MST_EP_CNTL4 0xe83d +#define regSMN_MST_EP_CNTL4_BASE_IDX 5 +#define regSMN_MST_CNTL1 0xe83e +#define regSMN_MST_CNTL1_BASE_IDX 5 +#define regSMN_MST_EP_CNTL5 0xe83f +#define regSMN_MST_EP_CNTL5_BASE_IDX 5 +#define regBIF_SELFRING_BUFFER_VID 0xe840 +#define regBIF_SELFRING_BUFFER_VID_BASE_IDX 5 +#define regBIF_SELFRING_VECTOR_CNTL 0xe841 +#define regBIF_SELFRING_VECTOR_CNTL_BASE_IDX 5 +#define regHDP_ERR_STATUS_EXT 0xe842 +#define regHDP_ERR_STATUS_EXT_BASE_IDX 5 +#define regNBIF_STRAP_WRITE_CTRL 0xe845 +#define regNBIF_STRAP_WRITE_CTRL_BASE_IDX 5 +#define regNBIF_INTX_DSTATE_MISC_CNTL 0xe846 +#define regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX 5 +#define regNBIF_PENDING_MISC_CNTL 0xe847 +#define regNBIF_PENDING_MISC_CNTL_BASE_IDX 5 +#define regBIF_GMI_WRR_WEIGHT 0xe848 +#define regBIF_GMI_WRR_WEIGHT_BASE_IDX 5 +#define regBIF_GMI_WRR_WEIGHT2 0xe849 +#define regBIF_GMI_WRR_WEIGHT2_BASE_IDX 5 +#define regBIF_GMI_WRR_WEIGHT3 0xe84a +#define regBIF_GMI_WRR_WEIGHT3_BASE_IDX 5 +#define regBIF_GMI_WRR_WEIGHT4 0xe84b +#define regBIF_GMI_WRR_WEIGHT4_BASE_IDX 5 +#define regNBIF_PWRBRK_REQUEST 0xe84c +#define regNBIF_PWRBRK_REQUEST_BASE_IDX 5 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F0 0xe850 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX 5 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F1 0xe851 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX 5 +#define regBIF_DMA_MP4_ERR_LOG 0xe870 +#define regBIF_DMA_MP4_ERR_LOG_BASE_IDX 5 +#define regBIF_PASID_ERR_LOG 0xe871 +#define regBIF_PASID_ERR_LOG_BASE_IDX 5 +#define regBIF_PASID_ERR_CLR 0xe872 +#define regBIF_PASID_ERR_CLR_BASE_IDX 5 +#define regNBIF_VWIRE_CTRL 0xe880 +#define regNBIF_VWIRE_CTRL_BASE_IDX 5 +#define regNBIF_MGCG_CTRL_LCLK 0xe887 +#define regNBIF_MGCG_CTRL_LCLK_BASE_IDX 5 +#define regNBIF_DS_CTRL_LCLK 0xe888 +#define regNBIF_DS_CTRL_LCLK_BASE_IDX 5 +#define regSMN_MST_CNTL0 0xe889 +#define regSMN_MST_CNTL0_BASE_IDX 5 +#define regSMN_MST_EP_CNTL1 0xe88a +#define regSMN_MST_EP_CNTL1_BASE_IDX 5 +#define regSMN_MST_EP_CNTL2 0xe88b +#define regSMN_MST_EP_CNTL2_BASE_IDX 5 +#define regNBIF_SDP_VWR_VCHG_DIS_CTRL 0xe88c +#define regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX 5 +#define regNBIF_SDP_VWR_VCHG_RST_CTRL0 0xe88d +#define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX 5 +#define regNBIF_SDP_VWR_VCHG_RST_CTRL1 0xe88e +#define regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX 5 +#define regNBIF_SDP_VWR_VCHG_TRIG 0xe88f +#define regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX 5 +#define regNBIO_LCLK_DEEPSLEEP_MASK 0xe890 +#define regNBIO_LCLK_DEEPSLEEP_MASK_BASE_IDX 5 +#define regNBIF_DS_CTRL_USBCLK 0xe891 +#define regNBIF_DS_CTRL_USBCLK_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_MISC3 0xe897 +#define regNBIF_SHUB_TODET_CLIENT_MISC3_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CTRL 0xe898 +#define regNBIF_SHUB_TODET_CTRL_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_CTRL 0xe899 +#define regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_STATUS 0xe89a +#define regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX 5 +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL 0xe89b +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_CTRL2 0xe89c +#define regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_STATUS2 0xe89d +#define regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX 5 +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2 0xe89e +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX 5 +#define regDMA_SDP_PORT_DEBUG 0xe8a0 +#define regDMA_SDP_PORT_DEBUG_BASE_IDX 5 +#define regSDP_PORT_MONITOR_CONTROL 0xe8a2 +#define regSDP_PORT_MONITOR_CONTROL_BASE_IDX 5 +#define regSDP_PORT_MONITOR_ADDRESS0 0xe8a3 +#define regSDP_PORT_MONITOR_ADDRESS0_BASE_IDX 5 +#define regSDP_PORT_MONITOR_ADDRESS1 0xe8a4 +#define regSDP_PORT_MONITOR_ADDRESS1_BASE_IDX 5 +#define regSDP_PORT_MONITOR_UNITID 0xe8a5 +#define regSDP_PORT_MONITOR_UNITID_BASE_IDX 5 +#define regSDP_PORT_MONITOR_INFO0 0xe8a6 +#define regSDP_PORT_MONITOR_INFO0_BASE_IDX 5 +#define regSDP_PORT_MONITOR_INFO1 0xe8a7 +#define regSDP_PORT_MONITOR_INFO1_BASE_IDX 5 +#define regSDP_PORT_MONITOR_INFO2 0xe8a8 +#define regSDP_PORT_MONITOR_INFO2_BASE_IDX 5 +#define regSDP_PORT_MONITOR_INFO3 0xe8a9 +#define regSDP_PORT_MONITOR_INFO3_BASE_IDX 5 +#define regSDP_PORT_MONITOR_INFO4 0xe8aa +#define regSDP_PORT_MONITOR_INFO4_BASE_IDX 5 +#define regBIFC_BME_ERR_LOG_HB 0xe8ab +#define regBIFC_BME_ERR_LOG_HB_BASE_IDX 5 +#define regBIFC_GFX_INT_MONITOR_MASK 0xe8ad +#define regBIFC_GFX_INT_MONITOR_MASK_BASE_IDX 5 +#define regBIFC_GFX_INT_MONITOR_STS 0xe8ae +#define regBIFC_GFX_INT_MONITOR_STS_BASE_IDX 5 +#define regBIFC_GFX_INT_MONITOR_CTRL 0xe8af +#define regBIFC_GFX_INT_MONITOR_CTRL_BASE_IDX 5 +#define regNBIF_FLUSH_CTRL 0xe8b1 +#define regNBIF_FLUSH_CTRL_BASE_IDX 5 +#define regNBIF_GUI_FLUSH_CNTL 0xe8b3 +#define regNBIF_GUI_FLUSH_CNTL_BASE_IDX 5 +#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC 0xe8c0 +#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC 0xe8c1 +#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC 0xe8c2 +#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC 0xe8c3 +#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC 0xe8c4 +#define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC 0xe8c5 +#define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC_BASE_IDX 5 +#define regDISCON_HYSTERESIS_HEAD_CTRL 0xe8c6 +#define regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX 5 +#define regBIFC_GSI_SDP_REQ_POOLCRED_ALLOC 0xe8c7 +#define regBIFC_GSI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_GSI_SDP_DAT_POOLCRED_ALLOC 0xe8c8 +#define regBIFC_GSI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_MCA_SMN_CTRL0 0xe8cb +#define regBIFC_MCA_SMN_CTRL0_BASE_IDX 5 +#define regBIFC_MCTP_SMN_CTRL0 0xe8ce +#define regBIFC_MCTP_SMN_CTRL0_BASE_IDX 5 +#define regNBIF_REGIF_DEBUG_COUNTER_CTRL 0xe8cf +#define regNBIF_REGIF_DEBUG_COUNTER_CTRL_BASE_IDX 5 +#define regBIFC_EARLY_WAKEUP_CNTL 0xe8d2 +#define regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX 5 +#define regBIFC_PERF_CNT_MMIO_RD_H16BIT 0xe8f0 +#define regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX 5 +#define regBIFC_PERF_CNT_MMIO_WR_H16BIT 0xe8f1 +#define regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX 5 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT 0xe8f2 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX 5 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT 0xe8f3 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_PERF_COM_COUNT_ENABLE 0xe8f4 +#define regBIF_MISC_NBIF_PERF_COM_COUNT_ENABLE_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_FSM 0xe8f5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_FSM_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_COUNTER 0xe8f6 +#define regBIF_MISC_NBIF_SDP_PERF_COUNTER_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT 0xe8f7 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT 0xe8f8 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT 0xe8f9 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT 0xe8fa +#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT 0xe8fb +#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT 0xe8fc +#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT 0xe8fd +#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT 0xe8fe +#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_BX_PERF_CNT_FSM 0xe8ff +#define regBIF_MISC_NBIF_BX_PERF_CNT_FSM_BASE_IDX 5 +#define regNBIF_TDISP_ENTER_ERR_CNTL 0xe905 +#define regNBIF_TDISP_ENTER_ERR_CNTL_BASE_IDX 5 +#define regBIF_UNITID_ERR_LOG 0xe906 +#define regBIF_UNITID_ERR_LOG_BASE_IDX 5 +#define regNBIF_COM_COUNT_VALUE 0xe908 +#define regNBIF_COM_COUNT_VALUE_BASE_IDX 5 +#define regNBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL 0xe909 +#define regNBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL_BASE_IDX 5 +#define regNBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL 0xe90a +#define regNBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL_BASE_IDX 5 +#define regBIF_AER_CNTL 0xe92c +#define regBIF_AER_CNTL_BASE_IDX 5 +#define regNBIF_IDE_INFO_CNTL 0xe92d +#define regNBIF_IDE_INFO_CNTL_BASE_IDX 5 +#define regBIFC_EXP_MISC_CTRL0 0xe9c0 +#define regBIFC_EXP_MISC_CTRL0_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_PF 0xea80 +#define regSECOND_HDP_MEM_FLUSH_CNTL_PF_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF0 0xea81 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF0_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF1 0xea82 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF1_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF2 0xea83 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF2_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF3 0xea84 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF3_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF4 0xea85 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF4_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF5 0xea86 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF5_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF6 0xea87 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF6_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF7 0xea88 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF7_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_PF 0xea89 +#define regSECOND_HDP_REG_FLUSH_CNTL_PF_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF0 0xea8a +#define regSECOND_HDP_REG_FLUSH_CNTL_VF0_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF1 0xea8b +#define regSECOND_HDP_REG_FLUSH_CNTL_VF1_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF2 0xea8c +#define regSECOND_HDP_REG_FLUSH_CNTL_VF2_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF3 0xea8d +#define regSECOND_HDP_REG_FLUSH_CNTL_VF3_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF4 0xea8e +#define regSECOND_HDP_REG_FLUSH_CNTL_VF4_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF5 0xea8f +#define regSECOND_HDP_REG_FLUSH_CNTL_VF5_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF6 0xea90 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF6_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF7 0xea91 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF7_BASE_IDX 5 +#define regGPU_HDP_FLUSH_GFX_FW 0xf4c0 +#define regGPU_HDP_FLUSH_GFX_FW_BASE_IDX 5 +#define regNBIF_RRMT_CNTL 0xf500 +#define regNBIF_RRMT_CNTL_BASE_IDX 5 +#define regRRMT_NBIF_MISC_REG1 0xf501 +#define regRRMT_NBIF_MISC_REG1_BASE_IDX 5 +#define regRRMT_LUT_INDEX 0xf502 +#define regRRMT_LUT_INDEX_BASE_IDX 5 +#define regRRMT_LUT_DATA 0xf503 +#define regRRMT_LUT_DATA_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_misc_pfvf_dev0_epf0_bif_misc_pfvf_regblk +// base address: 0x10100000 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0 0xf600 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1 0xf601 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2 0xf602 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3 0xf603 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0 0xf604 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1 0xf605 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2 0xf606 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3 0xf607 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0 0xf608 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1 0xf609 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2 0xf60a +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3 0xf60b +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0 0xf60c +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1 0xf60d +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2 0xf60e +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3 0xf60f +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0 0xf610 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1 0xf611 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2 0xf612 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3 0xf613 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_misc_pfvf_dev0_epf1_bif_misc_pfvf_regblk +// base address: 0x10100000 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0 0xf619 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1 0xf61a +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2 0xf61b +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3 0xf61c +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0 0xf61d +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1 0xf61e +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2 0xf61f +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3 0xf620 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0 0xf621 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1 0xf622 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2 0xf623 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3 0xf624 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0 0xf625 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1 0xf626 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2 0xf627 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3 0xf628 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0 0xf629 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1 0xf62a +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2 0xf62b +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3 0xf62c +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_trap_bif_trap_regblk +// base address: 0x10100000 +#define regNBIF_TRAP_NP_STATUS 0x4000 +#define regNBIF_TRAP_NP_STATUS_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST0 0x4001 +#define regNBIF_TRAP_NP_REQUEST0_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST1 0x4002 +#define regNBIF_TRAP_NP_REQUEST1_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST2 0x4003 +#define regNBIF_TRAP_NP_REQUEST2_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST3 0x4004 +#define regNBIF_TRAP_NP_REQUEST3_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST4 0x4005 +#define regNBIF_TRAP_NP_REQUEST4_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST5 0x4006 +#define regNBIF_TRAP_NP_REQUEST5_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST6 0x4007 +#define regNBIF_TRAP_NP_REQUEST6_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB0 0x4008 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB0_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB1 0x4009 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB1_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB2 0x400a +#define regNBIF_TRAP_NP_REQUEST_DATASTRB2_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB3 0x400b +#define regNBIF_TRAP_NP_REQUEST_DATASTRB3_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB4 0x400c +#define regNBIF_TRAP_NP_REQUEST_DATASTRB4_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB5 0x400d +#define regNBIF_TRAP_NP_REQUEST_DATASTRB5_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB6 0x400e +#define regNBIF_TRAP_NP_REQUEST_DATASTRB6_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB7 0x400f +#define regNBIF_TRAP_NP_REQUEST_DATASTRB7_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA0 0x4010 +#define regNBIF_TRAP_NP_REQUEST_DATA0_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA1 0x4011 +#define regNBIF_TRAP_NP_REQUEST_DATA1_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA2 0x4012 +#define regNBIF_TRAP_NP_REQUEST_DATA2_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA3 0x4013 +#define regNBIF_TRAP_NP_REQUEST_DATA3_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA4 0x4014 +#define regNBIF_TRAP_NP_REQUEST_DATA4_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA5 0x4015 +#define regNBIF_TRAP_NP_REQUEST_DATA5_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA6 0x4016 +#define regNBIF_TRAP_NP_REQUEST_DATA6_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA7 0x4017 +#define regNBIF_TRAP_NP_REQUEST_DATA7_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA8 0x4018 +#define regNBIF_TRAP_NP_REQUEST_DATA8_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA9 0x4019 +#define regNBIF_TRAP_NP_REQUEST_DATA9_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA10 0x401a +#define regNBIF_TRAP_NP_REQUEST_DATA10_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA11 0x401b +#define regNBIF_TRAP_NP_REQUEST_DATA11_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA12 0x401c +#define regNBIF_TRAP_NP_REQUEST_DATA12_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA13 0x401d +#define regNBIF_TRAP_NP_REQUEST_DATA13_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA14 0x401e +#define regNBIF_TRAP_NP_REQUEST_DATA14_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA15 0x401f +#define regNBIF_TRAP_NP_REQUEST_DATA15_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA16 0x4020 +#define regNBIF_TRAP_NP_REQUEST_DATA16_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA17 0x4021 +#define regNBIF_TRAP_NP_REQUEST_DATA17_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA18 0x4022 +#define regNBIF_TRAP_NP_REQUEST_DATA18_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA19 0x4023 +#define regNBIF_TRAP_NP_REQUEST_DATA19_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA20 0x4024 +#define regNBIF_TRAP_NP_REQUEST_DATA20_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA21 0x4025 +#define regNBIF_TRAP_NP_REQUEST_DATA21_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA22 0x4026 +#define regNBIF_TRAP_NP_REQUEST_DATA22_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA23 0x4027 +#define regNBIF_TRAP_NP_REQUEST_DATA23_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA24 0x4028 +#define regNBIF_TRAP_NP_REQUEST_DATA24_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA25 0x4029 +#define regNBIF_TRAP_NP_REQUEST_DATA25_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA26 0x402a +#define regNBIF_TRAP_NP_REQUEST_DATA26_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA27 0x402b +#define regNBIF_TRAP_NP_REQUEST_DATA27_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA28 0x402c +#define regNBIF_TRAP_NP_REQUEST_DATA28_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA29 0x402d +#define regNBIF_TRAP_NP_REQUEST_DATA29_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA30 0x402e +#define regNBIF_TRAP_NP_REQUEST_DATA30_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA31 0x402f +#define regNBIF_TRAP_NP_REQUEST_DATA31_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA32 0x4030 +#define regNBIF_TRAP_NP_REQUEST_DATA32_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA33 0x4031 +#define regNBIF_TRAP_NP_REQUEST_DATA33_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA34 0x4032 +#define regNBIF_TRAP_NP_REQUEST_DATA34_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA35 0x4033 +#define regNBIF_TRAP_NP_REQUEST_DATA35_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA36 0x4034 +#define regNBIF_TRAP_NP_REQUEST_DATA36_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA37 0x4035 +#define regNBIF_TRAP_NP_REQUEST_DATA37_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA38 0x4036 +#define regNBIF_TRAP_NP_REQUEST_DATA38_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA39 0x4037 +#define regNBIF_TRAP_NP_REQUEST_DATA39_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA40 0x4038 +#define regNBIF_TRAP_NP_REQUEST_DATA40_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA41 0x4039 +#define regNBIF_TRAP_NP_REQUEST_DATA41_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA42 0x403a +#define regNBIF_TRAP_NP_REQUEST_DATA42_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA43 0x403b +#define regNBIF_TRAP_NP_REQUEST_DATA43_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA44 0x403c +#define regNBIF_TRAP_NP_REQUEST_DATA44_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA45 0x403d +#define regNBIF_TRAP_NP_REQUEST_DATA45_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA46 0x403e +#define regNBIF_TRAP_NP_REQUEST_DATA46_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA47 0x403f +#define regNBIF_TRAP_NP_REQUEST_DATA47_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA48 0x4040 +#define regNBIF_TRAP_NP_REQUEST_DATA48_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA49 0x4041 +#define regNBIF_TRAP_NP_REQUEST_DATA49_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA50 0x4042 +#define regNBIF_TRAP_NP_REQUEST_DATA50_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA51 0x4043 +#define regNBIF_TRAP_NP_REQUEST_DATA51_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA52 0x4044 +#define regNBIF_TRAP_NP_REQUEST_DATA52_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA53 0x4045 +#define regNBIF_TRAP_NP_REQUEST_DATA53_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA54 0x4046 +#define regNBIF_TRAP_NP_REQUEST_DATA54_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA55 0x4047 +#define regNBIF_TRAP_NP_REQUEST_DATA55_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA56 0x4048 +#define regNBIF_TRAP_NP_REQUEST_DATA56_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA57 0x4049 +#define regNBIF_TRAP_NP_REQUEST_DATA57_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA58 0x404a +#define regNBIF_TRAP_NP_REQUEST_DATA58_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA59 0x404b +#define regNBIF_TRAP_NP_REQUEST_DATA59_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA60 0x404c +#define regNBIF_TRAP_NP_REQUEST_DATA60_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA61 0x404d +#define regNBIF_TRAP_NP_REQUEST_DATA61_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA62 0x404e +#define regNBIF_TRAP_NP_REQUEST_DATA62_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA63 0x404f +#define regNBIF_TRAP_NP_REQUEST_DATA63_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_CONTROL 0x4050 +#define regNBIF_TRAP_NP_RESPONSE_CONTROL_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE0 0x4051 +#define regNBIF_TRAP_NP_RESPONSE0_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE1 0x4052 +#define regNBIF_TRAP_NP_RESPONSE1_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE2 0x4053 +#define regNBIF_TRAP_NP_RESPONSE2_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE3 0x4054 +#define regNBIF_TRAP_NP_RESPONSE3_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE4 0x4055 +#define regNBIF_TRAP_NP_RESPONSE4_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE5 0x4056 +#define regNBIF_TRAP_NP_RESPONSE5_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA0 0x4057 +#define regNBIF_TRAP_NP_RESPONSE_DATA0_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA1 0x4058 +#define regNBIF_TRAP_NP_RESPONSE_DATA1_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA2 0x4059 +#define regNBIF_TRAP_NP_RESPONSE_DATA2_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA3 0x405a +#define regNBIF_TRAP_NP_RESPONSE_DATA3_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA4 0x405b +#define regNBIF_TRAP_NP_RESPONSE_DATA4_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA5 0x405c +#define regNBIF_TRAP_NP_RESPONSE_DATA5_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA6 0x405d +#define regNBIF_TRAP_NP_RESPONSE_DATA6_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA7 0x405e +#define regNBIF_TRAP_NP_RESPONSE_DATA7_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA8 0x405f +#define regNBIF_TRAP_NP_RESPONSE_DATA8_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA9 0x4060 +#define regNBIF_TRAP_NP_RESPONSE_DATA9_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA10 0x4061 +#define regNBIF_TRAP_NP_RESPONSE_DATA10_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA11 0x4062 +#define regNBIF_TRAP_NP_RESPONSE_DATA11_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA12 0x4063 +#define regNBIF_TRAP_NP_RESPONSE_DATA12_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA13 0x4064 +#define regNBIF_TRAP_NP_RESPONSE_DATA13_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA14 0x4065 +#define regNBIF_TRAP_NP_RESPONSE_DATA14_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA15 0x4066 +#define regNBIF_TRAP_NP_RESPONSE_DATA15_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA16 0x4067 +#define regNBIF_TRAP_NP_RESPONSE_DATA16_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA17 0x4068 +#define regNBIF_TRAP_NP_RESPONSE_DATA17_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA18 0x4069 +#define regNBIF_TRAP_NP_RESPONSE_DATA18_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA19 0x406a +#define regNBIF_TRAP_NP_RESPONSE_DATA19_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA20 0x406b +#define regNBIF_TRAP_NP_RESPONSE_DATA20_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA21 0x406c +#define regNBIF_TRAP_NP_RESPONSE_DATA21_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA22 0x406d +#define regNBIF_TRAP_NP_RESPONSE_DATA22_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA23 0x406e +#define regNBIF_TRAP_NP_RESPONSE_DATA23_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA24 0x406f +#define regNBIF_TRAP_NP_RESPONSE_DATA24_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA25 0x4070 +#define regNBIF_TRAP_NP_RESPONSE_DATA25_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA26 0x4071 +#define regNBIF_TRAP_NP_RESPONSE_DATA26_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA27 0x4072 +#define regNBIF_TRAP_NP_RESPONSE_DATA27_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA28 0x4073 +#define regNBIF_TRAP_NP_RESPONSE_DATA28_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA29 0x4074 +#define regNBIF_TRAP_NP_RESPONSE_DATA29_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA30 0x4075 +#define regNBIF_TRAP_NP_RESPONSE_DATA30_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA31 0x4076 +#define regNBIF_TRAP_NP_RESPONSE_DATA31_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA32 0x4077 +#define regNBIF_TRAP_NP_RESPONSE_DATA32_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA33 0x4078 +#define regNBIF_TRAP_NP_RESPONSE_DATA33_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA34 0x4079 +#define regNBIF_TRAP_NP_RESPONSE_DATA34_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA35 0x407a +#define regNBIF_TRAP_NP_RESPONSE_DATA35_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA36 0x407b +#define regNBIF_TRAP_NP_RESPONSE_DATA36_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA37 0x407c +#define regNBIF_TRAP_NP_RESPONSE_DATA37_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA38 0x407d +#define regNBIF_TRAP_NP_RESPONSE_DATA38_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA39 0x407e +#define regNBIF_TRAP_NP_RESPONSE_DATA39_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA40 0x407f +#define regNBIF_TRAP_NP_RESPONSE_DATA40_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA41 0x4080 +#define regNBIF_TRAP_NP_RESPONSE_DATA41_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA42 0x4081 +#define regNBIF_TRAP_NP_RESPONSE_DATA42_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA43 0x4082 +#define regNBIF_TRAP_NP_RESPONSE_DATA43_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA44 0x4083 +#define regNBIF_TRAP_NP_RESPONSE_DATA44_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA45 0x4084 +#define regNBIF_TRAP_NP_RESPONSE_DATA45_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA46 0x4085 +#define regNBIF_TRAP_NP_RESPONSE_DATA46_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA47 0x4086 +#define regNBIF_TRAP_NP_RESPONSE_DATA47_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA48 0x4087 +#define regNBIF_TRAP_NP_RESPONSE_DATA48_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA49 0x4088 +#define regNBIF_TRAP_NP_RESPONSE_DATA49_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA50 0x4089 +#define regNBIF_TRAP_NP_RESPONSE_DATA50_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA51 0x408a +#define regNBIF_TRAP_NP_RESPONSE_DATA51_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA52 0x408b +#define regNBIF_TRAP_NP_RESPONSE_DATA52_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA53 0x408c +#define regNBIF_TRAP_NP_RESPONSE_DATA53_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA54 0x408d +#define regNBIF_TRAP_NP_RESPONSE_DATA54_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA55 0x408e +#define regNBIF_TRAP_NP_RESPONSE_DATA55_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA56 0x408f +#define regNBIF_TRAP_NP_RESPONSE_DATA56_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA57 0x4090 +#define regNBIF_TRAP_NP_RESPONSE_DATA57_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA58 0x4091 +#define regNBIF_TRAP_NP_RESPONSE_DATA58_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA59 0x4092 +#define regNBIF_TRAP_NP_RESPONSE_DATA59_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA60 0x4093 +#define regNBIF_TRAP_NP_RESPONSE_DATA60_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA61 0x4094 +#define regNBIF_TRAP_NP_RESPONSE_DATA61_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA62 0x4095 +#define regNBIF_TRAP_NP_RESPONSE_DATA62_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA63 0x4096 +#define regNBIF_TRAP_NP_RESPONSE_DATA63_BASE_IDX 5 +#define regNBIF_TRAP_NP_0_CONTROL0 0x4097 +#define regNBIF_TRAP_NP_0_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_0_ADDRESS_LO 0x4098 +#define regNBIF_TRAP_NP_0_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_0_ADDRESS_HI 0x4099 +#define regNBIF_TRAP_NP_0_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_0_COMMAND 0x409a +#define regNBIF_TRAP_NP_0_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_0_ADDRESS_LO_MASK 0x409b +#define regNBIF_TRAP_NP_0_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_0_ADDRESS_HI_MASK 0x409c +#define regNBIF_TRAP_NP_0_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_0_COMMAND_MASK 0x409d +#define regNBIF_TRAP_NP_0_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_1_CONTROL0 0x409e +#define regNBIF_TRAP_NP_1_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_1_ADDRESS_LO 0x409f +#define regNBIF_TRAP_NP_1_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_1_ADDRESS_HI 0x40a0 +#define regNBIF_TRAP_NP_1_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_1_COMMAND 0x40a1 +#define regNBIF_TRAP_NP_1_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_1_ADDRESS_LO_MASK 0x40a2 +#define regNBIF_TRAP_NP_1_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_1_ADDRESS_HI_MASK 0x40a3 +#define regNBIF_TRAP_NP_1_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_1_COMMAND_MASK 0x40a4 +#define regNBIF_TRAP_NP_1_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_2_CONTROL0 0x40a5 +#define regNBIF_TRAP_NP_2_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_2_ADDRESS_LO 0x40a6 +#define regNBIF_TRAP_NP_2_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_2_ADDRESS_HI 0x40a7 +#define regNBIF_TRAP_NP_2_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_2_COMMAND 0x40a8 +#define regNBIF_TRAP_NP_2_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_2_ADDRESS_LO_MASK 0x40a9 +#define regNBIF_TRAP_NP_2_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_2_ADDRESS_HI_MASK 0x40aa +#define regNBIF_TRAP_NP_2_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_2_COMMAND_MASK 0x40ab +#define regNBIF_TRAP_NP_2_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_3_CONTROL0 0x40ac +#define regNBIF_TRAP_NP_3_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_3_ADDRESS_LO 0x40ad +#define regNBIF_TRAP_NP_3_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_3_ADDRESS_HI 0x40ae +#define regNBIF_TRAP_NP_3_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_3_COMMAND 0x40af +#define regNBIF_TRAP_NP_3_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_3_ADDRESS_LO_MASK 0x40b0 +#define regNBIF_TRAP_NP_3_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_3_ADDRESS_HI_MASK 0x40b1 +#define regNBIF_TRAP_NP_3_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_3_COMMAND_MASK 0x40b2 +#define regNBIF_TRAP_NP_3_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_4_CONTROL0 0x40b3 +#define regNBIF_TRAP_NP_4_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_4_ADDRESS_LO 0x40b4 +#define regNBIF_TRAP_NP_4_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_4_ADDRESS_HI 0x40b5 +#define regNBIF_TRAP_NP_4_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_4_COMMAND 0x40b6 +#define regNBIF_TRAP_NP_4_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_4_ADDRESS_LO_MASK 0x40b7 +#define regNBIF_TRAP_NP_4_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_4_ADDRESS_HI_MASK 0x40b8 +#define regNBIF_TRAP_NP_4_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_4_COMMAND_MASK 0x40b9 +#define regNBIF_TRAP_NP_4_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_5_CONTROL0 0x40ba +#define regNBIF_TRAP_NP_5_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_5_ADDRESS_LO 0x40bb +#define regNBIF_TRAP_NP_5_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_5_ADDRESS_HI 0x40bc +#define regNBIF_TRAP_NP_5_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_5_COMMAND 0x40bd +#define regNBIF_TRAP_NP_5_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_5_ADDRESS_LO_MASK 0x40be +#define regNBIF_TRAP_NP_5_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_5_ADDRESS_HI_MASK 0x40bf +#define regNBIF_TRAP_NP_5_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_5_COMMAND_MASK 0x40c0 +#define regNBIF_TRAP_NP_5_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_6_CONTROL0 0x40c1 +#define regNBIF_TRAP_NP_6_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_6_ADDRESS_LO 0x40c2 +#define regNBIF_TRAP_NP_6_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_6_ADDRESS_HI 0x40c3 +#define regNBIF_TRAP_NP_6_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_6_COMMAND 0x40c4 +#define regNBIF_TRAP_NP_6_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_6_ADDRESS_LO_MASK 0x40c5 +#define regNBIF_TRAP_NP_6_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_6_ADDRESS_HI_MASK 0x40c6 +#define regNBIF_TRAP_NP_6_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_6_COMMAND_MASK 0x40c7 +#define regNBIF_TRAP_NP_6_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_7_CONTROL0 0x40c8 +#define regNBIF_TRAP_NP_7_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_7_ADDRESS_LO 0x40c9 +#define regNBIF_TRAP_NP_7_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_7_ADDRESS_HI 0x40ca +#define regNBIF_TRAP_NP_7_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_7_COMMAND 0x40cb +#define regNBIF_TRAP_NP_7_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_7_ADDRESS_LO_MASK 0x40cc +#define regNBIF_TRAP_NP_7_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_7_ADDRESS_HI_MASK 0x40cd +#define regNBIF_TRAP_NP_7_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_7_COMMAND_MASK 0x40ce +#define regNBIF_TRAP_NP_7_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_8_CONTROL0 0x40cf +#define regNBIF_TRAP_NP_8_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_8_ADDRESS_LO 0x40d0 +#define regNBIF_TRAP_NP_8_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_8_ADDRESS_HI 0x40d1 +#define regNBIF_TRAP_NP_8_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_8_COMMAND 0x40d2 +#define regNBIF_TRAP_NP_8_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_8_ADDRESS_LO_MASK 0x40d3 +#define regNBIF_TRAP_NP_8_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_8_ADDRESS_HI_MASK 0x40d4 +#define regNBIF_TRAP_NP_8_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_8_COMMAND_MASK 0x40d5 +#define regNBIF_TRAP_NP_8_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_9_CONTROL0 0x40d6 +#define regNBIF_TRAP_NP_9_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_9_ADDRESS_LO 0x40d7 +#define regNBIF_TRAP_NP_9_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_9_ADDRESS_HI 0x40d8 +#define regNBIF_TRAP_NP_9_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_9_COMMAND 0x40d9 +#define regNBIF_TRAP_NP_9_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_9_ADDRESS_LO_MASK 0x40da +#define regNBIF_TRAP_NP_9_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_9_ADDRESS_HI_MASK 0x40db +#define regNBIF_TRAP_NP_9_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_9_COMMAND_MASK 0x40dc +#define regNBIF_TRAP_NP_9_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_10_CONTROL0 0x40dd +#define regNBIF_TRAP_NP_10_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_10_ADDRESS_LO 0x40de +#define regNBIF_TRAP_NP_10_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_10_ADDRESS_HI 0x40df +#define regNBIF_TRAP_NP_10_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_10_COMMAND 0x40e0 +#define regNBIF_TRAP_NP_10_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_10_ADDRESS_LO_MASK 0x40e1 +#define regNBIF_TRAP_NP_10_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_10_ADDRESS_HI_MASK 0x40e2 +#define regNBIF_TRAP_NP_10_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_10_COMMAND_MASK 0x40e3 +#define regNBIF_TRAP_NP_10_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_11_CONTROL0 0x40e4 +#define regNBIF_TRAP_NP_11_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_11_ADDRESS_LO 0x40e5 +#define regNBIF_TRAP_NP_11_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_11_ADDRESS_HI 0x40e6 +#define regNBIF_TRAP_NP_11_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_11_COMMAND 0x40e7 +#define regNBIF_TRAP_NP_11_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_11_ADDRESS_LO_MASK 0x40e8 +#define regNBIF_TRAP_NP_11_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_11_ADDRESS_HI_MASK 0x40e9 +#define regNBIF_TRAP_NP_11_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_11_COMMAND_MASK 0x40ea +#define regNBIF_TRAP_NP_11_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_12_CONTROL0 0x40eb +#define regNBIF_TRAP_NP_12_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_12_ADDRESS_LO 0x40ec +#define regNBIF_TRAP_NP_12_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_12_ADDRESS_HI 0x40ed +#define regNBIF_TRAP_NP_12_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_12_COMMAND 0x40ee +#define regNBIF_TRAP_NP_12_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_12_ADDRESS_LO_MASK 0x40ef +#define regNBIF_TRAP_NP_12_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_12_ADDRESS_HI_MASK 0x40f0 +#define regNBIF_TRAP_NP_12_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_12_COMMAND_MASK 0x40f1 +#define regNBIF_TRAP_NP_12_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_13_CONTROL0 0x40f2 +#define regNBIF_TRAP_NP_13_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_13_ADDRESS_LO 0x40f3 +#define regNBIF_TRAP_NP_13_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_13_ADDRESS_HI 0x40f4 +#define regNBIF_TRAP_NP_13_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_13_COMMAND 0x40f5 +#define regNBIF_TRAP_NP_13_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_13_ADDRESS_LO_MASK 0x40f6 +#define regNBIF_TRAP_NP_13_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_13_ADDRESS_HI_MASK 0x40f7 +#define regNBIF_TRAP_NP_13_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_13_COMMAND_MASK 0x40f8 +#define regNBIF_TRAP_NP_13_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_14_CONTROL0 0x40f9 +#define regNBIF_TRAP_NP_14_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_14_ADDRESS_LO 0x40fa +#define regNBIF_TRAP_NP_14_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_14_ADDRESS_HI 0x40fb +#define regNBIF_TRAP_NP_14_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_14_COMMAND 0x40fc +#define regNBIF_TRAP_NP_14_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_14_ADDRESS_LO_MASK 0x40fd +#define regNBIF_TRAP_NP_14_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_14_ADDRESS_HI_MASK 0x40fe +#define regNBIF_TRAP_NP_14_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_14_COMMAND_MASK 0x40ff +#define regNBIF_TRAP_NP_14_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_15_CONTROL0 0x4100 +#define regNBIF_TRAP_NP_15_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_15_ADDRESS_LO 0x4101 +#define regNBIF_TRAP_NP_15_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_15_ADDRESS_HI 0x4102 +#define regNBIF_TRAP_NP_15_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_15_COMMAND 0x4103 +#define regNBIF_TRAP_NP_15_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_15_ADDRESS_LO_MASK 0x4104 +#define regNBIF_TRAP_NP_15_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_15_ADDRESS_HI_MASK 0x4105 +#define regNBIF_TRAP_NP_15_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_15_COMMAND_MASK 0x4106 +#define regNBIF_TRAP_NP_15_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_S2_CONTROL0 0x4107 +#define regNBIF_TRAP_NP_S2_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_S2_ADDRESS_LO 0x4108 +#define regNBIF_TRAP_NP_S2_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_S2_ADDRESS_HI 0x4109 +#define regNBIF_TRAP_NP_S2_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_S2_COMMAND 0x410a +#define regNBIF_TRAP_NP_S2_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_S2_ADDRESS_LO_MASK 0x410b +#define regNBIF_TRAP_NP_S2_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_S2_ADDRESS_HI_MASK 0x410c +#define regNBIF_TRAP_NP_S2_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_S2_COMMAND_MASK 0x410d +#define regNBIF_TRAP_NP_S2_COMMAND_MASK_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_ras_bif_ras_regblk +// base address: 0x10100000 +#define regBIFL_RAS_CENTRAL_CNTL 0xe400 +#define regBIFL_RAS_CENTRAL_CNTL_BASE_IDX 5 +#define regBIFL_RAS_CENTRAL_STATUS 0xe404 +#define regBIFL_RAS_CENTRAL_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF0_CTRL 0xe408 +#define regBIFL_RAS_LEAF0_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF1_CTRL 0xe409 +#define regBIFL_RAS_LEAF1_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF2_CTRL 0xe40a +#define regBIFL_RAS_LEAF2_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF3_CTRL 0xe40b +#define regBIFL_RAS_LEAF3_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF4_CTRL 0xe40c +#define regBIFL_RAS_LEAF4_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF5_CTRL 0xe40d +#define regBIFL_RAS_LEAF5_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF6_CTRL 0xe40e +#define regBIFL_RAS_LEAF6_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF7_CTRL 0xe40f +#define regBIFL_RAS_LEAF7_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF8_CTRL 0xe410 +#define regBIFL_RAS_LEAF8_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF9_CTRL 0xe411 +#define regBIFL_RAS_LEAF9_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF10_CTRL 0xe412 +#define regBIFL_RAS_LEAF10_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF11_CTRL 0xe413 +#define regBIFL_RAS_LEAF11_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF12_CTRL 0xe414 +#define regBIFL_RAS_LEAF12_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF13_CTRL 0xe415 +#define regBIFL_RAS_LEAF13_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF14_CTRL 0xe416 +#define regBIFL_RAS_LEAF14_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF15_CTRL 0xe417 +#define regBIFL_RAS_LEAF15_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF16_CTRL 0xe418 +#define regBIFL_RAS_LEAF16_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF17_CTRL 0xe419 +#define regBIFL_RAS_LEAF17_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF18_CTRL 0xe41a +#define regBIFL_RAS_LEAF18_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF19_CTRL 0xe41b +#define regBIFL_RAS_LEAF19_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF2_MISC_CTRL 0xe42e +#define regBIFL_RAS_LEAF2_MISC_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF2_MISC_CTRL2 0xe42f +#define regBIFL_RAS_LEAF2_MISC_CTRL2_BASE_IDX 5 +#define regBIFL_RAS_LEAF_NTB_CTRL 0xe430 +#define regBIFL_RAS_LEAF_NTB_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF0_STATUS 0xe431 +#define regBIFL_RAS_LEAF0_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF1_STATUS 0xe432 +#define regBIFL_RAS_LEAF1_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF2_STATUS 0xe433 +#define regBIFL_RAS_LEAF2_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF3_STATUS 0xe434 +#define regBIFL_RAS_LEAF3_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF4_STATUS 0xe435 +#define regBIFL_RAS_LEAF4_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF5_STATUS 0xe436 +#define regBIFL_RAS_LEAF5_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF6_STATUS 0xe437 +#define regBIFL_RAS_LEAF6_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF7_STATUS 0xe438 +#define regBIFL_RAS_LEAF7_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF8_STATUS 0xe439 +#define regBIFL_RAS_LEAF8_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF9_STATUS 0xe43a +#define regBIFL_RAS_LEAF9_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF10_STATUS 0xe43b +#define regBIFL_RAS_LEAF10_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF11_STATUS 0xe43c +#define regBIFL_RAS_LEAF11_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF12_STATUS 0xe43d +#define regBIFL_RAS_LEAF12_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF13_STATUS 0xe43e +#define regBIFL_RAS_LEAF13_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF14_STATUS 0xe43f +#define regBIFL_RAS_LEAF14_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF15_STATUS 0xe440 +#define regBIFL_RAS_LEAF15_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF16_STATUS 0xe441 +#define regBIFL_RAS_LEAF16_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF17_STATUS 0xe442 +#define regBIFL_RAS_LEAF17_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF18_STATUS 0xe443 +#define regBIFL_RAS_LEAF18_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF19_STATUS 0xe444 +#define regBIFL_RAS_LEAF19_STATUS_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP 0xe450 +#define regBIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP 0xe451 +#define regBIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP 0xe452 +#define regBIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP 0xe453 +#define regBIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP 0xe458 +#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP 0xe459 +#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP 0xe45a +#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP 0xe45b +#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP 0xe460 +#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP 0xe461 +#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP 0xe462 +#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_ORIG_SDP 0xe463 +#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_ORIG_SDP_BASE_IDX 5 +#define regBIFL_IOHUB_RAS_IH_CNTL 0xe7fe +#define regBIFL_IOHUB_RAS_IH_CNTL_BASE_IDX 5 +#define regBIFL_RAS_VWR_FROM_IOHUB 0xe7ff +#define regBIFL_RAS_VWR_FROM_IOHUB_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED 0x8d88 +#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH 0x8d89 +#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL 0x8d8b +#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL 0x8d8c +#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 0x8d8d +#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL 0x8d8e +#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL 0x8d8f +#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 0x8d90 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC 0x8d91 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 0x8d92 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL 0x8d94 +#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL 0x8d95 +#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL 0x8d96 +#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 0x8d97 +#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX 5 +#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC 0x8d98 +#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX 5 +#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP 0x8d99 +#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH 0x8d6b +#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_CNTL 0x8d6d +#define regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL 0x8d6e +#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS 0x8d6f +#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 0x8d70 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL 0x8d71 +#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL 0x8d72 +#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL 0x8d74 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x8d75 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x8d75 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x8d75 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x8d75 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x8d76 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x8d76 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x8d76 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x8d76 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC 0x8d77 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 0x8d78 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP 0x8d7a +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x8d7b +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL 0x8d7b +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x8d7b +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x8d7c +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x8d7c +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x8d7c +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x8d7c +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x8d7d +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x8d7d +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x8d7d +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL 0x8d7d +#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED 0x8d7e +#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL 0x8d80 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID 0x8d81 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL 0x8d82 +#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL 0x8d83 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL 0x8d84 +#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3 0x8d85 +#define regRCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DEV0_1_RCC_ERR_INT_CNTL 0x8da6 +#define regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC 0x8da7 +#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_RESET_EN 0x8da8 +#define regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_VDM_SUPPORT 0x8da9 +#define regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 0x8daa +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 0x8dab +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_GPUIOV_REGION 0x8dac +#define regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN 0x8dad +#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL 0x8dae +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x8daf +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE 0x8daf +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0 0x8dde +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1 0x8ddf +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_BUS_CNTL 0x8de1 +#define regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONFIG_CNTL 0x8de2 +#define regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE 0x8de6 +#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE 0x8de7 +#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE 0x8de8 +#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_XDMA_LO 0x8de9 +#define regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_XDMA_HI 0x8dea +#define regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC 0x8deb +#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1 0x8dec +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BUSNUM_LIST0 0x8ded +#define regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BUSNUM_LIST1 0x8dee +#define regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2 0x8def +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM 0x8df0 +#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_HOST_BUSNUM 0x8df1 +#define regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI 0x8df2 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO 0x8df3 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI 0x8df4 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO 0x8df5 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI 0x8df6 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO 0x8df7 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI 0x8df8 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO 0x8df9 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 0x8dfa +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 0x8dfb +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL 0x8dfd +#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL 0x8dfe +#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE 0x8dff +#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL 0x8e00 +#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_MH_ARB_CNTL 0x8e01 +#define regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_SYSDEC +// base address: 0x10120000 +#define regBIF_BX1_SYSHUB_INDEX_OVLP 0x8008 +#define regBIF_BX1_SYSHUB_INDEX_OVLP_BASE_IDX 5 +#define regBIF_BX1_SYSHUB_DATA_OVLP 0x8009 +#define regBIF_BX1_SYSHUB_DATA_OVLP_BASE_IDX 5 +#define regBIF_BX1_SYSHUB_INDEX_HI_OVLP 0x800a +#define regBIF_BX1_SYSHUB_INDEX_HI_OVLP_BASE_IDX 5 +#define regBIF_BX1_PCIE_INDEX 0x800c +#define regBIF_BX1_PCIE_INDEX_BASE_IDX 5 +#define regBIF_BX1_PCIE_DATA 0x800d +#define regBIF_BX1_PCIE_DATA_BASE_IDX 5 +#define regBIF_BX1_PCIE_INDEX2 0x800e +#define regBIF_BX1_PCIE_INDEX2_BASE_IDX 5 +#define regBIF_BX1_PCIE_DATA2 0x800f +#define regBIF_BX1_PCIE_DATA2_BASE_IDX 5 +#define regBIF_BX1_PCIE_INDEX_HI 0x8010 +#define regBIF_BX1_PCIE_INDEX_HI_BASE_IDX 5 +#define regBIF_BX1_PCIE_INDEX2_HI 0x8011 +#define regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_0 0x8048 +#define regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_1 0x8049 +#define regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_2 0x804a +#define regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_3 0x804b +#define regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_0 0x804c +#define regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_1 0x804d +#define regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_2 0x804e +#define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_3 0x804f +#define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_4 0x8050 +#define regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_5 0x8051 +#define regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_6 0x8052 +#define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_7 0x8053 +#define regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_8 0x8054 +#define regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_9 0x8055 +#define regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_10 0x8056 +#define regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_11 0x8057 +#define regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_12 0x8058 +#define regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_13 0x8059 +#define regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_14 0x805a +#define regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_15 0x805b +#define regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX 5 +#define regBIF_BX1_BIF_RLC_INTR_CNTL 0x8060 +#define regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_VCE_INTR_CNTL 0x8061 +#define regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_UVD_INTR_CNTL 0x8062 +#define regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_Engine_INTR_CNTL 0x8063 +#define regBIF_BX1_BIF_Engine_INTR_CNTL_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 0x8080 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 0x8081 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 0x8082 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 0x8083 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 0x8084 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 0x8085 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 0x8086 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 0x8087 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 0x8088 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 0x8089 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 0x808a +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 0x808b +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 0x808c +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 0x808d +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 0x808e +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 0x808f +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL 0x8090 +#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL 0x8091 +#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL 0x8092 +#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x8093 +#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_0 0x8094 +#define regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_1 0x8095 +#define regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_2 0x8096 +#define regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_3 0x8097 +#define regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_4 0x8098 +#define regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_5 0x8099 +#define regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_6 0x809a +#define regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_7 0x809b +#define regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_8 0x809c +#define regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_9 0x809d +#define regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_10 0x809e +#define regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_11 0x809f +#define regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_12 0x80a0 +#define regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_13 0x80a1 +#define regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_14 0x80a2 +#define regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_15 0x80a3 +#define regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_0 0x80a4 +#define regBIF_BX1_FW_SCRATCH_0_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_1 0x80a5 +#define regBIF_BX1_FW_SCRATCH_1_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_2 0x80a6 +#define regBIF_BX1_FW_SCRATCH_2_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_3 0x80a7 +#define regBIF_BX1_FW_SCRATCH_3_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_4 0x80a8 +#define regBIF_BX1_FW_SCRATCH_4_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_5 0x80a9 +#define regBIF_BX1_FW_SCRATCH_5_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_6 0x80aa +#define regBIF_BX1_FW_SCRATCH_6_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_7 0x80ab +#define regBIF_BX1_FW_SCRATCH_7_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_8 0x80ac +#define regBIF_BX1_FW_SCRATCH_8_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_9 0x80ad +#define regBIF_BX1_FW_SCRATCH_9_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_10 0x80ae +#define regBIF_BX1_FW_SCRATCH_10_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_11 0x80af +#define regBIF_BX1_FW_SCRATCH_11_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_12 0x80b0 +#define regBIF_BX1_FW_SCRATCH_12_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_13 0x80b1 +#define regBIF_BX1_FW_SCRATCH_13_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_14 0x80b2 +#define regBIF_BX1_FW_SCRATCH_14_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_15 0x80b3 +#define regBIF_BX1_FW_SCRATCH_15_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_4 0x80b4 +#define regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_5 0x80b5 +#define regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_6 0x80b6 +#define regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_7 0x80b7 +#define regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_8 0x80b8 +#define regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_9 0x80b9 +#define regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_10 0x80ba +#define regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_11 0x80bb +#define regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_12 0x80bc +#define regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_13 0x80bd +#define regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_14 0x80be +#define regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_15 0x80bf +#define regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_PF1_MM_INDEX 0x8000 +#define regBIF_BX_PF1_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_PF1_MM_DATA 0x8001 +#define regBIF_BX_PF1_MM_DATA_BASE_IDX 5 +#define regBIF_BX_PF1_MM_INDEX_HI 0x8006 +#define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_BIFDEC1 +// base address: 0x10120000 +#define regBIF_BX1_CC_BIF_BX_STRAP0 0x8e02 +#define regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX 5 +#define regBIF_BX1_CC_BIF_BX_PINSTRAP0 0x8e04 +#define regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX 5 +#define regBIF_BX1_BIF_MM_INDACCESS_CNTL 0x8e06 +#define regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX 5 +#define regBIF_BX1_BUS_CNTL 0x8e07 +#define regBIF_BX1_BUS_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_SCRATCH0 0x8e08 +#define regBIF_BX1_BIF_SCRATCH0_BASE_IDX 5 +#define regBIF_BX1_BIF_SCRATCH1 0x8e09 +#define regBIF_BX1_BIF_SCRATCH1_BASE_IDX 5 +#define regBIF_BX1_BX_RESET_EN 0x8e0d +#define regBIF_BX1_BX_RESET_EN_BASE_IDX 5 +#define regBIF_BX1_MM_CFGREGS_CNTL 0x8e0e +#define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX 5 +#define regBIF_BX1_BX_RESET_CNTL 0x8e10 +#define regBIF_BX1_BX_RESET_CNTL_BASE_IDX 5 +#define regBIF_BX1_INTERRUPT_CNTL 0x8e11 +#define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX 5 +#define regBIF_BX1_INTERRUPT_CNTL2 0x8e12 +#define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX 5 +#define regBIF_BX1_CLKREQB_PAD_CNTL 0x8e18 +#define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC 0x8e1b +#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX 5 +#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC 0x8e1c +#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 5 +#define regBIF_BX1_BIF_DOORBELL_CNTL 0x8e1d +#define regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_DOORBELL_INT_CNTL 0x8e1e +#define regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_FB_EN 0x8e20 +#define regBIF_BX1_BIF_FB_EN_BASE_IDX 5 +#define regBIF_BX1_BIF_INTR_CNTL 0x8e21 +#define regBIF_BX1_BIF_INTR_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF 0x8e29 +#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX 5 +#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF 0x8e2a +#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 5 +#define regBIF_BX1_BACO_CNTL 0x8e2b +#define regBIF_BX1_BACO_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_BACO_EXIT_TIME0 0x8e2c +#define regBIF_BX1_BIF_BACO_EXIT_TIME0_BASE_IDX 5 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER1 0x8e2d +#define regBIF_BX1_BIF_BACO_EXIT_TIMER1_BASE_IDX 5 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER2 0x8e2e +#define regBIF_BX1_BIF_BACO_EXIT_TIMER2_BASE_IDX 5 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER3 0x8e2f +#define regBIF_BX1_BIF_BACO_EXIT_TIMER3_BASE_IDX 5 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER4 0x8e30 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER4_BASE_IDX 5 +#define regBIF_BX1_MEM_TYPE_CNTL 0x8e31 +#define regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL 0x8e33 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0 0x8e34 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1 0x8e35 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2 0x8e36 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3 0x8e37 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4 0x8e38 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5 0x8e39 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6 0x8e3a +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7 0x8e3b +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8 0x8e3c +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9 0x8e3d +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10 0x8e3e +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11 0x8e3f +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12 0x8e40 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13 0x8e41 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14 0x8e42 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15 0x8e43 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX 5 +#define regBIF_BX1_VF_REGWR_EN 0x8e44 +#define regBIF_BX1_VF_REGWR_EN_BASE_IDX 5 +#define regBIF_BX1_VF_DOORBELL_EN 0x8e45 +#define regBIF_BX1_VF_DOORBELL_EN_BASE_IDX 5 +#define regBIF_BX1_VF_FB_EN 0x8e46 +#define regBIF_BX1_VF_FB_EN_BASE_IDX 5 +#define regBIF_BX1_VF_REGWR_STATUS 0x8e47 +#define regBIF_BX1_VF_REGWR_STATUS_BASE_IDX 5 +#define regBIF_BX1_VF_DOORBELL_STATUS 0x8e48 +#define regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX 5 +#define regBIF_BX1_VF_FB_STATUS 0x8e49 +#define regBIF_BX1_VF_FB_STATUS_BASE_IDX 5 +#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL 0x8e4d +#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL 0x8e4e +#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_CNTL 0x8e4f +#define regBIF_BX1_BIF_RB_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_BASE 0x8e50 +#define regBIF_BX1_BIF_RB_BASE_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_RPTR 0x8e51 +#define regBIF_BX1_BIF_RB_RPTR_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_WPTR 0x8e52 +#define regBIF_BX1_BIF_RB_WPTR_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI 0x8e53 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO 0x8e54 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX 5 +#define regBIF_BX1_MAILBOX_INDEX 0x8e55 +#define regBIF_BX1_MAILBOX_INDEX_BASE_IDX 5 +#define regBIF_BX1_BACO_AZ_ENHANCE_CTRL 0x8e61 +#define regBIF_BX1_BACO_AZ_ENHANCE_CTRL_BASE_IDX 5 +#define regBIF_BX1_BIF_MP1_INTR_CTRL 0x8e62 +#define regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX 5 +#define regBIF_BX1_BIF_PERSTB_PAD_CNTL 0x8e65 +#define regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_PX_EN_PAD_CNTL 0x8e66 +#define regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL 0x8e67 +#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL 0x8e68 +#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL 0x8e69 +#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE 0x8e85 +#define regBIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_PF1_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_PF1_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_PF1_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_PF1_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_PF1_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_PF1_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_PF1_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_PF1_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_strap_BIFDEC1:1 +// base address: 0x10120000 +#define regRCC_STRAP2_RCC_BIF_STRAP0 0x8d20 +#define regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP1 0x8d21 +#define regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP10 0x8d22 +#define regRCC_STRAP2_RCC_BIF_STRAP10_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP11 0x8d23 +#define regRCC_STRAP2_RCC_BIF_STRAP11_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP12 0x8d24 +#define regRCC_STRAP2_RCC_BIF_STRAP12_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP13 0x8d25 +#define regRCC_STRAP2_RCC_BIF_STRAP13_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP2 0x8d26 +#define regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP3 0x8d27 +#define regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP4 0x8d28 +#define regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP5 0x8d29 +#define regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP6 0x8d2a +#define regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP7 0x8d2b +#define regRCC_STRAP2_RCC_BIF_STRAP7_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP8 0x8d2c +#define regRCC_STRAP2_RCC_BIF_STRAP8_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP9 0x8d2d +#define regRCC_STRAP2_RCC_BIF_STRAP9_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 0x8d2e +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 0x8d2f +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10 0x8d30 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11 0x8d31 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12 0x8d32 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13 0x8d33 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14 0x8d34 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP15 0x8d35 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP15_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP16 0x8d36 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP16_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP17 0x8d37 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP17_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP18 0x8d38 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP18_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 0x8d39 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 0x8d3a +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 0x8d3b +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 0x8d3c +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 0x8d3d +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 0x8d3e +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 0x8d3f +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 0x8d40 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 0x8d41 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 0x8d42 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 0x8d43 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 0x8d44 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15 0x8d45 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16 0x8d46 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17 0x8d47 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18 0x8d48 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP19 0x8d49 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP19_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 0x8d4a +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP22 0x8d4b +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP22_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP23 0x8d4c +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP23_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP24 0x8d4d +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP24_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 0x8d4e +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 0x8d4f +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 0x8d50 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 0x8d51 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 0x8d52 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 0x8d53 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP1 0x8d54 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP1_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP10 0x8d55 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP10_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP11 0x8d56 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP11_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP12 0x8d57 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP12_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP13 0x8d58 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP13_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP14 0x8d59 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP14_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP15 0x8d5a +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP15_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP16 0x8d5b +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP16_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP17 0x8d5c +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP17_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP18 0x8d5d +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP18_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP19 0x8d5e +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP19_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 0x8d5f +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20 0x8d60 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21 0x8d61 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23 0x8d62 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24 0x8d63 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 0x8d64 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 0x8d65 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 0x8d66 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 0x8d67 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 0x8d68 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP8 0x8d69 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP8_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP9 0x8d6a +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP9_BASE_IDX 5 + + +// addressBlock: nbif0_hpdma0_hpdma_private_hpdma_private_regblk +// base address: 0x10100000 +#define regNBIF_SDP_PERF_COUNTER_2 0x100a +#define regNBIF_SDP_PERF_COUNTER_2_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_STATUS3 0x10d1 +#define regNBIF_SHUB_TODET_CLIENT_STATUS3_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0 0x10d5 +#define regBIF_AER_ERR_LOG_DEV0_F0_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf0 0x10d6 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf0_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf1 0x10d7 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf1_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf2 0x10d8 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf2_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf3 0x10d9 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf3_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf4 0x10da +#define regBIF_AER_ERR_LOG_DEV0_F0_vf4_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf5 0x10db +#define regBIF_AER_ERR_LOG_DEV0_F0_vf5_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf6 0x10dc +#define regBIF_AER_ERR_LOG_DEV0_F0_vf6_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf7 0x10dd +#define regBIF_AER_ERR_LOG_DEV0_F0_vf7_BASE_IDX 5 + + +// addressBlock: nbif0_hphost0_hphost_private_hphost_private_regblk +// base address: 0x10106000 +#define regNBIF_AON_SVA_DISABLE_SAD 0x189a +#define regNBIF_AON_SVA_DISABLE_SAD_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_gdc_dma_sion_SIONDEC +// base address: 0x1400000 +#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7400 +#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7401 +#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7402 +#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7403 +#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7404 +#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7405 +#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7406 +#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7407 +#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0 0x4f7408 +#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1 0x4f7409 +#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0 0x4f740a +#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1 0x4f740b +#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f740c +#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f740d +#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f740e +#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f740f +#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7410 +#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7411 +#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7412 +#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7413 +#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7414 +#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7415 +#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7416 +#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7417 +#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7418 +#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7419 +#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0 0x4f741a +#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1 0x4f741b +#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0 0x4f741c +#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1 0x4f741d +#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0 0x4f741e +#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1 0x4f741f +#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7420 +#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7421 +#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7422 +#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7423 +#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7424 +#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7425 +#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7426 +#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7427 +#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0 0x4f7428 +#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1 0x4f7429 +#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0 0x4f742a +#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1 0x4f742b +#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0 0x4f742c +#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1 0x4f742d +#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0 0x4f742e +#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1 0x4f742f +#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0 0x4f7430 +#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1 0x4f7431 +#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0 0x4f7432 +#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1 0x4f7433 +#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0 0x4f7434 +#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1 0x4f7435 +#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0 0x4f7436 +#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1 0x4f7437 +#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0 0x4f7438 +#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1 0x4f7439 +#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0 0x4f743a +#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1 0x4f743b +#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CNTL_REG0 0x4f743c +#define regGDC_DMA_SION_CNTL_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CNTL_REG1 0x4f743d +#define regGDC_DMA_SION_CNTL_REG1_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_hst_sion_SIONDEC +// base address: 0x1400000 +#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7600 +#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7601 +#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7602 +#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7603 +#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7604 +#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7605 +#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7606 +#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7607 +#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_Req_BurstTarget_REG0 0x4f7608 +#define regGDC_HST_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_Req_BurstTarget_REG1 0x4f7609 +#define regGDC_HST_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_Req_TimeSlot_REG0 0x4f760a +#define regGDC_HST_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_Req_TimeSlot_REG1 0x4f760b +#define regGDC_HST_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f760c +#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f760d +#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f760e +#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f760f +#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7610 +#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7611 +#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7612 +#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7613 +#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7614 +#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7615 +#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7616 +#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7617 +#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7618 +#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7619 +#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0 0x4f761a +#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1 0x4f761b +#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_Req_BurstTarget_REG0 0x4f761c +#define regGDC_HST_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_Req_BurstTarget_REG1 0x4f761d +#define regGDC_HST_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_Req_TimeSlot_REG0 0x4f761e +#define regGDC_HST_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_Req_TimeSlot_REG1 0x4f761f +#define regGDC_HST_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7620 +#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7621 +#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7622 +#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7623 +#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7624 +#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7625 +#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7626 +#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7627 +#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CNTL_REG0 0x4f7628 +#define regGDC_HST_SION_CNTL_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CNTL_REG1 0x4f7629 +#define regGDC_HST_SION_CNTL_REG1_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_GDCDEC +// base address: 0x1400000 +#define regGDC1_NGDC_SDP_PORT_CTRL 0x4f0aa0 +#define regGDC1_NGDC_SDP_PORT_CTRL_BASE_IDX 3 +#define regGDC1_SHUB_REGS_IF_CTL 0x4f0aa1 +#define regGDC1_SHUB_REGS_IF_CTL_BASE_IDX 3 +#define regGDC1_NGDC_MGCG_CTRL 0x4f0aa7 +#define regGDC1_NGDC_MGCG_CTRL_BASE_IDX 3 +#define regGDC1_S2A_MISC_CNTL 0x4f0aa8 +#define regGDC1_S2A_MISC_CNTL_BASE_IDX 3 +#define regGDC1_NGDC_MCA_SMN_CTRL0 0x4f0aab +#define regGDC1_NGDC_MCA_SMN_CTRL0_BASE_IDX 3 +#define regGDC1_NGDC_EARLY_WAKEUP_CTRL 0x4f0aac +#define regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 3 +#define regGDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL 0x4f0ab8 +#define regGDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL_BASE_IDX 3 +#define regGDC1_GDC_DMA_SION_PCTRL 0x4f0ab9 +#define regGDC1_GDC_DMA_SION_PCTRL_BASE_IDX 3 +#define regGDC1_NGDC_MP4SDP_CNTL 0x4f0abb +#define regGDC1_NGDC_MP4SDP_CNTL_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF0 0x4f0b13 +#define regGDC1_DOORBELL_VCN_TARGET_VF0_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF1 0x4f0b13 +#define regGDC1_DOORBELL_VCN_TARGET_VF1_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF2 0x4f0b14 +#define regGDC1_DOORBELL_VCN_TARGET_VF2_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF3 0x4f0b14 +#define regGDC1_DOORBELL_VCN_TARGET_VF3_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF4 0x4f0b15 +#define regGDC1_DOORBELL_VCN_TARGET_VF4_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF5 0x4f0b15 +#define regGDC1_DOORBELL_VCN_TARGET_VF5_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF6 0x4f0b16 +#define regGDC1_DOORBELL_VCN_TARGET_VF6_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF7 0x4f0b16 +#define regGDC1_DOORBELL_VCN_TARGET_VF7_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_PF 0x4f0b17 +#define regGDC1_DOORBELL_ACCESS_EN_PF_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF0 0x4f0b17 +#define regGDC1_DOORBELL_ACCESS_EN_VF0_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF1 0x4f0b18 +#define regGDC1_DOORBELL_ACCESS_EN_VF1_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF2 0x4f0b18 +#define regGDC1_DOORBELL_ACCESS_EN_VF2_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF3 0x4f0b19 +#define regGDC1_DOORBELL_ACCESS_EN_VF3_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF4 0x4f0b19 +#define regGDC1_DOORBELL_ACCESS_EN_VF4_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF5 0x4f0b1a +#define regGDC1_DOORBELL_ACCESS_EN_VF5_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF6 0x4f0b1a +#define regGDC1_DOORBELL_ACCESS_EN_VF6_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF7 0x4f0b1b +#define regGDC1_DOORBELL_ACCESS_EN_VF7_BASE_IDX 3 +#define regGDC1_NGDC_CNDI_BUS_PORT_CTRL 0x4f0b1c +#define regGDC1_NGDC_CNDI_BUS_PORT_CTRL_BASE_IDX 3 +#define regGDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL 0x4f0b1d +#define regGDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_ras_gdc_ras_regblk +// base address: 0x1400000 +#define regGDCSOC_ERR_RSP_CNTL 0x4f5c00 +#define regGDCSOC_ERR_RSP_CNTL_BASE_IDX 3 +#define regGDCSOC_RAS_CENTRAL_STATUS 0x4f5c10 +#define regGDCSOC_RAS_CENTRAL_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF0_CTRL 0x4f5c20 +#define regGDCSOC_RAS_LEAF0_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF1_CTRL 0x4f5c21 +#define regGDCSOC_RAS_LEAF1_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF2_CTRL 0x4f5c22 +#define regGDCSOC_RAS_LEAF2_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF3_CTRL 0x4f5c23 +#define regGDCSOC_RAS_LEAF3_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF4_CTRL 0x4f5c24 +#define regGDCSOC_RAS_LEAF4_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF5_CTRL 0x4f5c25 +#define regGDCSOC_RAS_LEAF5_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF6_CTRL 0x4f5c26 +#define regGDCSOC_RAS_LEAF6_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF7_CTRL 0x4f5c27 +#define regGDCSOC_RAS_LEAF7_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF8_CTRL 0x4f5c28 +#define regGDCSOC_RAS_LEAF8_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF9_CTRL 0x4f5c29 +#define regGDCSOC_RAS_LEAF9_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF10_CTRL 0x4f5c2a +#define regGDCSOC_RAS_LEAF10_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF11_CTRL 0x4f5c2b +#define regGDCSOC_RAS_LEAF11_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF12_CTRL 0x4f5c2c +#define regGDCSOC_RAS_LEAF12_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF13_CTRL 0x4f5c2d +#define regGDCSOC_RAS_LEAF13_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF0_STATUS 0x4f5c30 +#define regGDCSOC_RAS_LEAF0_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF1_STATUS 0x4f5c31 +#define regGDCSOC_RAS_LEAF1_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF2_STATUS 0x4f5c32 +#define regGDCSOC_RAS_LEAF2_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF3_STATUS 0x4f5c33 +#define regGDCSOC_RAS_LEAF3_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF4_STATUS 0x4f5c34 +#define regGDCSOC_RAS_LEAF4_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF5_STATUS 0x4f5c35 +#define regGDCSOC_RAS_LEAF5_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF6_STATUS 0x4f5c36 +#define regGDCSOC_RAS_LEAF6_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF7_STATUS 0x4f5c37 +#define regGDCSOC_RAS_LEAF7_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF8_STATUS 0x4f5c38 +#define regGDCSOC_RAS_LEAF8_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF9_STATUS 0x4f5c39 +#define regGDCSOC_RAS_LEAF9_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF10_STATUS 0x4f5c3a +#define regGDCSOC_RAS_LEAF10_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF11_STATUS 0x4f5c3b +#define regGDCSOC_RAS_LEAF11_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF12_STATUS 0x4f5c3c +#define regGDCSOC_RAS_LEAF12_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF13_STATUS 0x4f5c3d +#define regGDCSOC_RAS_LEAF13_STATUS_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_sec_GDCSEC_DEC +// base address: 0x1400000 +#define regGDC_SEC_MCA_SMN_CTRL0 0x4f7001 +#define regGDC_SEC_MCA_SMN_CTRL0_BASE_IDX 3 +#define regGDC_SEC_MCA_SMN_CTRL1 0x4f7002 +#define regGDC_SEC_MCA_SMN_CTRL1_BASE_IDX 3 +#define regXCD_DOORBELL_FENCE 0x4f7003 +#define regXCD_DOORBELL_FENCE_BASE_IDX 3 +#define regSHUB_PWRBRK_DEGLITCH 0x4f7004 +#define regSHUB_PWRBRK_DEGLITCH_BASE_IDX 3 +#define regSHUB_DIE_CTRL 0x4f7005 +#define regSHUB_DIE_CTRL_BASE_IDX 3 +#define regGDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL 0x4f700a +#define regGDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL_BASE_IDX 3 +#define regXCD_DOORBELL_FENCE_1 0x4f700b +#define regXCD_DOORBELL_FENCE_1_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQUSER_0 0x4f700c +#define regNGDC_CNDI_DOORBELL_REQUSER_0_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQUSER_1 0x4f700d +#define regNGDC_CNDI_DOORBELL_REQUSER_1_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQUSER_2 0x4f700e +#define regNGDC_CNDI_DOORBELL_REQUSER_2_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQUSER_3 0x4f700f +#define regNGDC_CNDI_DOORBELL_REQUSER_3_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQUSER_4 0x4f7010 +#define regNGDC_CNDI_DOORBELL_REQUSER_4_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQUSER_5 0x4f7011 +#define regNGDC_CNDI_DOORBELL_REQUSER_5_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0 0x4f7012 +#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1 0x4f7013 +#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_rst_GDCRST_DEC +// base address: 0x1400000 +#define regSHUB_PF_FLR_RST 0x4f7800 +#define regSHUB_PF_FLR_RST_BASE_IDX 3 +#define regSHUB_GFX_DRV_VPU_RST 0x4f7801 +#define regSHUB_GFX_DRV_VPU_RST_BASE_IDX 3 +#define regSHUB_LINK_RESET 0x4f7802 +#define regSHUB_LINK_RESET_BASE_IDX 3 +#define regSHUB_HST_NIC400_SW_CTRL_RESET 0x4f7803 +#define regSHUB_HST_NIC400_SW_CTRL_RESET_BASE_IDX 3 +#define regSHUB_DEV0_PF0_VF_FLR_RST 0x4f7808 +#define regSHUB_DEV0_PF0_VF_FLR_RST_BASE_IDX 3 +#define regSHUB_DEV0_PF1_VF_FLR_RST 0x4f7809 +#define regSHUB_DEV0_PF1_VF_FLR_RST_BASE_IDX 3 +#define regSHUB_HARD_RST_CTRL 0x4f7810 +#define regSHUB_HARD_RST_CTRL_BASE_IDX 3 +#define regSHUB_SOFT_RST_CTRL 0x4f7811 +#define regSHUB_SOFT_RST_CTRL_BASE_IDX 3 +#define regSHUB_SDP_PORT_RST 0x4f7812 +#define regSHUB_SDP_PORT_RST_BASE_IDX 3 +#define regSHUB_RST_MISC_TRL 0x4f7813 +#define regSHUB_RST_MISC_TRL_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_s2a_GDCS2A_DEC +// base address: 0x1400000 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL 0x4f0aeb +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1 0x4f0aec +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL 0x4f0aed +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1 0x4f0aee +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL 0x4f0aef +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1 0x4f0af0 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL 0x4f0af1 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1 0x4f0af2 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL 0x4f0af3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1 0x4f0af4 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL 0x4f0af5 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1 0x4f0af6 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL 0x4f0af7 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1 0x4f0af8 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL 0x4f0af9 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1 0x4f0afa +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL 0x4f0afb +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1 0x4f0afc +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL 0x4f0afd +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1 0x4f0afe +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL 0x4f0aff +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1 0x4f0b00 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL 0x4f0b01 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1 0x4f0b02 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL 0x4f0b03 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1 0x4f0b04 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL 0x4f0b05 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1 0x4f0b06 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL 0x4f0b07 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1 0x4f0b08 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL 0x4f0b09 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1 0x4f0b0a +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG 0x4f0b0b +#define regGDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 3 +#define regGDC_S2A1_NBIF_GFX_DOORBELL_STATUS 0x4f0b0c +#define regGDC_S2A1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_misc_GDCMISC_DEC +// base address: 0x1400000 +#define regGDC_DMA_SION_CRED_RST 0x4f3401 +#define regGDC_DMA_SION_CRED_RST_BASE_IDX 3 +#define regGDC_HST_SION_PER_SDP_PORT_RST 0x4f3402 +#define regGDC_HST_SION_PER_SDP_PORT_RST_BASE_IDX 3 +#define regGDC_HST_SION_PER_SDP_CNTL_REG1 0x4f3403 +#define regGDC_HST_SION_PER_SDP_CNTL_REG1_BASE_IDX 3 +#define regGDC_HST_AXI_STALL_FOR_FLUSH 0x4f3404 +#define regGDC_HST_AXI_STALL_FOR_FLUSH_BASE_IDX 3 +#define regSYSHUB_SDP_DEBUG_COUNTER_CTRL 0x4f3405 +#define regSYSHUB_SDP_DEBUG_COUNTER_CTRL_BASE_IDX 3 +#define regNBIF_PWRBRK_IN_PAD_CNTL 0x4f3801 +#define regNBIF_PWRBRK_IN_PAD_CNTL_BASE_IDX 3 +#define regNBIF_PWRBRK_OUT_PAD_CNTL 0x4f3802 +#define regNBIF_PWRBRK_OUT_PAD_CNTL_BASE_IDX 3 +#define regSHUB_OOB_CRUSH_DUMP_CTRL 0x4f3803 +#define regSHUB_OOB_CRUSH_DUMP_CTRL_BASE_IDX 3 +#define regSHUB_MP_ERREVENT_MASK_CTRL 0x4f3804 +#define regSHUB_MP_ERREVENT_MASK_CTRL_BASE_IDX 3 +#define regSHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL 0x4f3805 +#define regSHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL_BASE_IDX 3 +#define regSHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL 0x4f3806 +#define regSHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_sec_misc_GDCSEC_MISC_DEC +// base address: 0x1400000 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI 0x4f2883 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI 0x4f2884 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V3_AXI 0x4f2885 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V3_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI 0x4f2886 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI 0x4f2887 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B_AXI 0x4f2888 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI 0x4f2889 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI 0x4f288a +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4_AXI 0x4f288b +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI 0x4f288c +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI 0x4f288d +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4B_AXI 0x4f288e +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4B_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI 0x4f288f +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI 0x4f2890 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V7_AXI 0x4f2891 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V7_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP 0x4f2898 +#define regGDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP 0x4f2899 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_SHUB_CNDI_ORIG_SDP 0x4f289a +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_SHUB_CNDI_ORIG_SDP_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI 0x4f28a7 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI 0x4f28a8 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B1_AXI 0x4f28a9 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B1_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_POISON_DBUG_CTRL 0x4f2c00 +#define regGDCSOC_SEC_RAS_POISON_DBUG_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_PARITY_DBUG_CTRL 0x4f2c01 +#define regGDCSOC_SEC_RAS_PARITY_DBUG_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL 0x4f2c02 +#define regGDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL 0x4f2c03 +#define regGDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL 0x4f2c04 +#define regGDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_RESPONSE_DROP_CTRL 0x4f2c05 +#define regGDCSOC_SEC_RAS_RESPONSE_DROP_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL 0x4f2c06 +#define regGDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL 0x4f2c07 +#define regGDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL 0x4f2c08 +#define regGDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL 0x4f2c09 +#define regGDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL 0x4f2c0a +#define regGDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL 0x4f2c0b +#define regGDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL 0x4f2c0c +#define regGDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL 0x4f2c0d +#define regGDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL 0x4f2c0e +#define regGDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL 0x4f2c0f +#define regGDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL 0x4f2c10 +#define regGDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL 0x4f2c11 +#define regGDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL 0x4f2c12 +#define regGDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL 0x4f2c13 +#define regGDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL 0x4f2c14 +#define regGDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL 0x4f2c15 +#define regGDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL 0x4f2c16 +#define regGDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL 0x4f2c17 +#define regGDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL 0x4f2c18 +#define regGDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL 0x4f2c19 +#define regGDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL 0x4f2c1a +#define regGDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL 0x4f2c1b +#define regGDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL 0x4f2c1c +#define regGDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL 0x4f2c1d +#define regGDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL 0x4f2c1e +#define regGDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL 0x4f2c1f +#define regGDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL 0x4f2c20 +#define regGDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL 0x4f2c21 +#define regGDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_a2s_GDCA2S_DEC +// base address: 0x1400000 +#define regA2S_CNTL_SW0 0x4f0c40 +#define regA2S_CNTL_SW0_BASE_IDX 3 +#define regA2S_CNTL_SW1 0x4f0c41 +#define regA2S_CNTL_SW1_BASE_IDX 3 +#define regA2S_CNTL_SW2 0x4f0c42 +#define regA2S_CNTL_SW2_BASE_IDX 3 +#define regA2S_CNTL_SW3 0x4f0c43 +#define regA2S_CNTL_SW3_BASE_IDX 3 +#define regA2S_CNTL_SW4 0x4f0c44 +#define regA2S_CNTL_SW4_BASE_IDX 3 +#define regA2S_CNTL_SW5 0x4f0c45 +#define regA2S_CNTL_SW5_BASE_IDX 3 +#define regA2S_CNTL_2_SW0 0x4f0c50 +#define regA2S_CNTL_2_SW0_BASE_IDX 3 +#define regA2S_CNTL_2_SW1 0x4f0c51 +#define regA2S_CNTL_2_SW1_BASE_IDX 3 +#define regA2S_CNTL_2_SW2 0x4f0c52 +#define regA2S_CNTL_2_SW2_BASE_IDX 3 +#define regA2S_CNTL_2_SW3 0x4f0c53 +#define regA2S_CNTL_2_SW3_BASE_IDX 3 +#define regA2S_CNTL_2_SW4 0x4f0c54 +#define regA2S_CNTL_2_SW4_BASE_IDX 3 +#define regA2S_CNTL_2_SW5 0x4f0c55 +#define regA2S_CNTL_2_SW5_BASE_IDX 3 +#define regA2S_WRSIZEFULL_SUPPORT_DISABLE 0x4f0c5c +#define regA2S_WRSIZEFULL_SUPPORT_DISABLE_BASE_IDX 3 +#define regROUTING_TABLE_CNTL 0x4f0c60 +#define regROUTING_TABLE_CNTL_BASE_IDX 3 +#define regROUTING_TABLE_DATA0 0x4f0c61 +#define regROUTING_TABLE_DATA0_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC0 0x4f0c68 +#define regA2S_ARB_CONTROL_FOR_VC0_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC1 0x4f0c69 +#define regA2S_ARB_CONTROL_FOR_VC1_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC2 0x4f0c6a +#define regA2S_ARB_CONTROL_FOR_VC2_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC3 0x4f0c6b +#define regA2S_ARB_CONTROL_FOR_VC3_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC4 0x4f0c6c +#define regA2S_ARB_CONTROL_FOR_VC4_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC5 0x4f0c6d +#define regA2S_ARB_CONTROL_FOR_VC5_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC6 0x4f0c6e +#define regA2S_ARB_CONTROL_FOR_VC6_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC7 0x4f0c6f +#define regA2S_ARB_CONTROL_FOR_VC7_BASE_IDX 3 +#define regA2S_RW_ARB_CNTL 0x4f0c70 +#define regA2S_RW_ARB_CNTL_BASE_IDX 3 +#define regA2S_REQ_RSP_TAG_CNTL 0x4f0c71 +#define regA2S_REQ_RSP_TAG_CNTL_BASE_IDX 3 +#define regA2S_MISC_CNTL 0x4f0c72 +#define regA2S_MISC_CNTL_BASE_IDX 3 +#define regA2S_TAG_ALLOC_0 0x4f0c74 +#define regA2S_TAG_ALLOC_0_BASE_IDX 3 +#define regA2S_TAG_ALLOC_1 0x4f0c75 +#define regA2S_TAG_ALLOC_1_BASE_IDX 3 +#define regA2S_TAG_ALLOC_2 0x4f0c76 +#define regA2S_TAG_ALLOC_2_BASE_IDX 3 +#define regA2S_TAG_ALLOC_3 0x4f0c77 +#define regA2S_TAG_ALLOC_3_BASE_IDX 3 +#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_0 0x4f0c78 +#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_0_BASE_IDX 3 +#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_1 0x4f0c79 +#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_1_BASE_IDX 3 +#define regGDC_SDP_PORT_CTRL 0x4f0c7c +#define regGDC_SDP_PORT_CTRL_BASE_IDX 3 +#define regGDC_A2S_SDP_REQ_POOLCRED_ALLOC 0x4f0c7d +#define regGDC_A2S_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 3 +#define regGDC_A2S_SDP_DAT_POOLCRED_ALLOC 0x4f0c7e +#define regGDC_A2S_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 3 +#define regSHUB_PERF_COMMON_COUNTER 0x4f0c80 +#define regSHUB_PERF_COMMON_COUNTER_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_FSM 0x4f0c81 +#define regSHUB_A2S_PERF_CNT_FSM_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_RSP_UNITID 0x4f0c83 +#define regSHUB_A2S_PERF_CNT_RSP_UNITID_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_0_CTRL 0x4f0c84 +#define regSHUB_A2S_PERF_CNT_0_CTRL_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_1_CTRL 0x4f0c85 +#define regSHUB_A2S_PERF_CNT_1_CTRL_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_2_CTRL 0x4f0c86 +#define regSHUB_A2S_PERF_CNT_2_CTRL_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_3_CTRL 0x4f0c87 +#define regSHUB_A2S_PERF_CNT_3_CTRL_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_0_VALUE_L32BIT 0x4f0c88 +#define regSHUB_A2S_PERF_CNT_0_VALUE_L32BIT_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_0_VALUE_H16BIT 0x4f0c89 +#define regSHUB_A2S_PERF_CNT_0_VALUE_H16BIT_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_1_VALUE_L32BIT 0x4f0c8a +#define regSHUB_A2S_PERF_CNT_1_VALUE_L32BIT_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_1_VALUE_H16BIT 0x4f0c8b +#define regSHUB_A2S_PERF_CNT_1_VALUE_H16BIT_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_2_VALUE_L32BIT 0x4f0c8c +#define regSHUB_A2S_PERF_CNT_2_VALUE_L32BIT_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_2_VALUE_H16BIT 0x4f0c8d +#define regSHUB_A2S_PERF_CNT_2_VALUE_H16BIT_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_3_VALUE_L32BIT 0x4f0c8e +#define regSHUB_A2S_PERF_CNT_3_VALUE_L32BIT_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_3_VALUE_H16BIT 0x4f0c8f +#define regSHUB_A2S_PERF_CNT_3_VALUE_H16BIT_BASE_IDX 3 +#define regSHUB_TO_ALL_PERF_COUNTER 0x4f0c90 +#define regSHUB_TO_ALL_PERF_COUNTER_BASE_IDX 3 +#define regGDC_PERF_COUNTER_RESET 0x4f0c91 +#define regGDC_PERF_COUNTER_RESET_BASE_IDX 3 +#define regSHUB_COM_COUNT_VALUE 0x4f0c92 +#define regSHUB_COM_COUNT_VALUE_BASE_IDX 3 +#define regA2S_QUEUE_FIFO_ARB_CNTL 0x4f0c93 +#define regA2S_QUEUE_FIFO_ARB_CNTL_BASE_IDX 3 +#define regWR_A2S_RSP_WRR_CNTL 0x4f0c94 +#define regWR_A2S_RSP_WRR_CNTL_BASE_IDX 3 +#define regRD_A2S_RSP_WRR_CNTL 0x4f0c95 +#define regRD_A2S_RSP_WRR_CNTL_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_syshub_mmreg_syshubdirect +// base address: 0x1400000 +#define regSYSHUB_DS_CTRL_SOCCLK 0x4f3c00 +#define regSYSHUB_DS_CTRL_SOCCLK_BASE_IDX 3 +#define regSYSHUB_DS_CTRL2_SOCCLK 0x4f3c01 +#define regSYSHUB_DS_CTRL2_SOCCLK_BASE_IDX 3 +#define regSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x4f3c02 +#define regSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_BASE_IDX 3 +#define regSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x4f3c03 +#define regSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_BASE_IDX 3 +#define regSYSHUB_MGCG_CTRL_SOCCLK 0x4f3c08 +#define regSYSHUB_MGCG_CTRL_SOCCLK_BASE_IDX 3 +#define regSYSHUB_SCRATCH_SOCCLK 0x4f3c0a +#define regSYSHUB_SCRATCH_SOCCLK_BASE_IDX 3 +#define regSYSHUB_HANG_CNTL_SOCCLK 0x4f3c0c +#define regSYSHUB_HANG_CNTL_SOCCLK_BASE_IDX 3 +#define regSYSHUB_SELECT_SOCCLK 0x4f3c0d +#define regSYSHUB_SELECT_SOCCLK_BASE_IDX 3 +#define regSYSHUB_DS_AW_READY_SOCCLK 0x4f3c11 +#define regSYSHUB_DS_AW_READY_SOCCLK_BASE_IDX 3 +#define regSYSHUB_DS_AR_READY_SOCCLK 0x4f3c12 +#define regSYSHUB_DS_AR_READY_SOCCLK_BASE_IDX 3 +#define regSYSHUB_DS_W_READY_SOCCLK 0x4f3c13 +#define regSYSHUB_DS_W_READY_SOCCLK_BASE_IDX 3 +#define regSYSHUB_DS_R_READY_SOCCLK 0x4f3c14 +#define regSYSHUB_DS_R_READY_SOCCLK_BASE_IDX 3 +#define regSYSHUB_DS_B_READY_SOCCLK 0x4f3c15 +#define regSYSHUB_DS_B_READY_SOCCLK_BASE_IDX 3 +#define regSYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK 0x4f3c16 +#define regSYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK_BASE_IDX 3 +#define regDMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x4f3e00 +#define regDMA_CLK0_SW0_SYSHUB_QOS_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x4f3e01 +#define regDMA_CLK0_SW1_SYSHUB_QOS_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW0_CL0_CNTL 0x4f3e40 +#define regDMA_CLK0_SW0_CL0_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW0_CL1_CNTL 0x4f3e41 +#define regDMA_CLK0_SW0_CL1_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW1_CL0_CNTL 0x4f3e60 +#define regDMA_CLK0_SW1_CL0_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW1_CL1_CNTL 0x4f3e61 +#define regDMA_CLK0_SW1_CL1_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW2_CL0_CNTL 0x4f3e80 +#define regDMA_CLK0_SW2_CL0_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW3_CL0_CNTL 0x4f3ea0 +#define regDMA_CLK0_SW3_CL0_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW4_CL0_CNTL 0x4f3ec0 +#define regDMA_CLK0_SW4_CL0_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW5_CL0_CNTL 0x4f3ee0 +#define regDMA_CLK0_SW5_CL0_CNTL_BASE_IDX 3 +#define regNIC400_0_AMIB_0_FN_MOD_BM_ISS 0x4f7c02 +#define regNIC400_0_AMIB_0_FN_MOD_BM_ISS_BASE_IDX 3 +#define regNIC400_0_AMIB_0_FN_MOD 0x4f7c42 +#define regNIC400_0_AMIB_0_FN_MOD_BASE_IDX 3 +#define regNIC400_0_ASIB_0_FN_MOD 0x4f8842 +#define regNIC400_0_ASIB_0_FN_MOD_BASE_IDX 3 +#define regNIC400_0_ASIB_0_QOS_CNTL 0x4f8843 +#define regNIC400_0_ASIB_0_QOS_CNTL_BASE_IDX 3 +#define regNIC400_0_ASIB_0_MAX_OT 0x4f8844 +#define regNIC400_0_ASIB_0_MAX_OT_BASE_IDX 3 +#define regNIC400_0_ASIB_0_MAX_COMB_OT 0x4f8845 +#define regNIC400_0_ASIB_0_MAX_COMB_OT_BASE_IDX 3 +#define regNIC400_0_ASIB_0_AW_P 0x4f8846 +#define regNIC400_0_ASIB_0_AW_P_BASE_IDX 3 +#define regNIC400_0_ASIB_0_AW_B 0x4f8847 +#define regNIC400_0_ASIB_0_AW_B_BASE_IDX 3 +#define regNIC400_0_ASIB_0_AW_R 0x4f8848 +#define regNIC400_0_ASIB_0_AW_R_BASE_IDX 3 +#define regNIC400_0_ASIB_0_AR_P 0x4f8849 +#define regNIC400_0_ASIB_0_AR_P_BASE_IDX 3 +#define regNIC400_0_ASIB_0_AR_B 0x4f884a +#define regNIC400_0_ASIB_0_AR_B_BASE_IDX 3 +#define regNIC400_0_ASIB_0_AR_R 0x4f884b +#define regNIC400_0_ASIB_0_AR_R_BASE_IDX 3 +#define regNIC400_0_ASIB_0_TARGET_FC 0x4f884c +#define regNIC400_0_ASIB_0_TARGET_FC_BASE_IDX 3 +#define regNIC400_0_ASIB_0_KI_FC 0x4f884d +#define regNIC400_0_ASIB_0_KI_FC_BASE_IDX 3 +#define regNIC400_0_ASIB_0_QOS_RANGE 0x4f884e +#define regNIC400_0_ASIB_0_QOS_RANGE_BASE_IDX 3 +#define regNIC400_0_ASIB_1_FN_MOD 0x4f8c42 +#define regNIC400_0_ASIB_1_FN_MOD_BASE_IDX 3 +#define regNIC400_0_ASIB_1_QOS_CNTL 0x4f8c43 +#define regNIC400_0_ASIB_1_QOS_CNTL_BASE_IDX 3 +#define regNIC400_0_ASIB_1_MAX_OT 0x4f8c44 +#define regNIC400_0_ASIB_1_MAX_OT_BASE_IDX 3 +#define regNIC400_0_ASIB_1_MAX_COMB_OT 0x4f8c45 +#define regNIC400_0_ASIB_1_MAX_COMB_OT_BASE_IDX 3 +#define regNIC400_0_ASIB_1_AW_P 0x4f8c46 +#define regNIC400_0_ASIB_1_AW_P_BASE_IDX 3 +#define regNIC400_0_ASIB_1_AW_B 0x4f8c47 +#define regNIC400_0_ASIB_1_AW_B_BASE_IDX 3 +#define regNIC400_0_ASIB_1_AW_R 0x4f8c48 +#define regNIC400_0_ASIB_1_AW_R_BASE_IDX 3 +#define regNIC400_0_ASIB_1_AR_P 0x4f8c49 +#define regNIC400_0_ASIB_1_AR_P_BASE_IDX 3 +#define regNIC400_0_ASIB_1_AR_B 0x4f8c4a +#define regNIC400_0_ASIB_1_AR_B_BASE_IDX 3 +#define regNIC400_0_ASIB_1_AR_R 0x4f8c4b +#define regNIC400_0_ASIB_1_AR_R_BASE_IDX 3 +#define regNIC400_0_ASIB_1_TARGET_FC 0x4f8c4c +#define regNIC400_0_ASIB_1_TARGET_FC_BASE_IDX 3 +#define regNIC400_0_ASIB_1_KI_FC 0x4f8c4d +#define regNIC400_0_ASIB_1_KI_FC_BASE_IDX 3 +#define regNIC400_0_ASIB_1_QOS_RANGE 0x4f8c4e +#define regNIC400_0_ASIB_1_QOS_RANGE_BASE_IDX 3 +#define regNIC400_0_IB_0_FN_MOD 0x4fb842 +#define regNIC400_0_IB_0_FN_MOD_BASE_IDX 3 +#define regNIC400_1_AMIB_0_FN_MOD_BM_ISS 0x4fbc02 +#define regNIC400_1_AMIB_0_FN_MOD_BM_ISS_BASE_IDX 3 +#define regNIC400_1_AMIB_0_FN_MOD 0x4fbc42 +#define regNIC400_1_AMIB_0_FN_MOD_BASE_IDX 3 +#define regNIC400_1_ASIB_0_FN_MOD 0x4fc842 +#define regNIC400_1_ASIB_0_FN_MOD_BASE_IDX 3 +#define regNIC400_1_ASIB_0_QOS_CNTL 0x4fc843 +#define regNIC400_1_ASIB_0_QOS_CNTL_BASE_IDX 3 +#define regNIC400_1_ASIB_0_MAX_OT 0x4fc844 +#define regNIC400_1_ASIB_0_MAX_OT_BASE_IDX 3 +#define regNIC400_1_ASIB_0_MAX_COMB_OT 0x4fc845 +#define regNIC400_1_ASIB_0_MAX_COMB_OT_BASE_IDX 3 +#define regNIC400_1_ASIB_0_AW_P 0x4fc846 +#define regNIC400_1_ASIB_0_AW_P_BASE_IDX 3 +#define regNIC400_1_ASIB_0_AW_B 0x4fc847 +#define regNIC400_1_ASIB_0_AW_B_BASE_IDX 3 +#define regNIC400_1_ASIB_0_AW_R 0x4fc848 +#define regNIC400_1_ASIB_0_AW_R_BASE_IDX 3 +#define regNIC400_1_ASIB_0_AR_P 0x4fc849 +#define regNIC400_1_ASIB_0_AR_P_BASE_IDX 3 +#define regNIC400_1_ASIB_0_AR_B 0x4fc84a +#define regNIC400_1_ASIB_0_AR_B_BASE_IDX 3 +#define regNIC400_1_ASIB_0_AR_R 0x4fc84b +#define regNIC400_1_ASIB_0_AR_R_BASE_IDX 3 +#define regNIC400_1_ASIB_0_TARGET_FC 0x4fc84c +#define regNIC400_1_ASIB_0_TARGET_FC_BASE_IDX 3 +#define regNIC400_1_ASIB_0_KI_FC 0x4fc84d +#define regNIC400_1_ASIB_0_KI_FC_BASE_IDX 3 +#define regNIC400_1_ASIB_0_QOS_RANGE 0x4fc84e +#define regNIC400_1_ASIB_0_QOS_RANGE_BASE_IDX 3 +#define regNIC400_1_ASIB_1_FN_MOD 0x4fcc42 +#define regNIC400_1_ASIB_1_FN_MOD_BASE_IDX 3 +#define regNIC400_1_ASIB_1_QOS_CNTL 0x4fcc43 +#define regNIC400_1_ASIB_1_QOS_CNTL_BASE_IDX 3 +#define regNIC400_1_ASIB_1_MAX_OT 0x4fcc44 +#define regNIC400_1_ASIB_1_MAX_OT_BASE_IDX 3 +#define regNIC400_1_ASIB_1_MAX_COMB_OT 0x4fcc45 +#define regNIC400_1_ASIB_1_MAX_COMB_OT_BASE_IDX 3 +#define regNIC400_1_ASIB_1_AW_P 0x4fcc46 +#define regNIC400_1_ASIB_1_AW_P_BASE_IDX 3 +#define regNIC400_1_ASIB_1_AW_B 0x4fcc47 +#define regNIC400_1_ASIB_1_AW_B_BASE_IDX 3 +#define regNIC400_1_ASIB_1_AW_R 0x4fcc48 +#define regNIC400_1_ASIB_1_AW_R_BASE_IDX 3 +#define regNIC400_1_ASIB_1_AR_P 0x4fcc49 +#define regNIC400_1_ASIB_1_AR_P_BASE_IDX 3 +#define regNIC400_1_ASIB_1_AR_B 0x4fcc4a +#define regNIC400_1_ASIB_1_AR_B_BASE_IDX 3 +#define regNIC400_1_ASIB_1_AR_R 0x4fcc4b +#define regNIC400_1_ASIB_1_AR_R_BASE_IDX 3 +#define regNIC400_1_ASIB_1_TARGET_FC 0x4fcc4c +#define regNIC400_1_ASIB_1_TARGET_FC_BASE_IDX 3 +#define regNIC400_1_ASIB_1_KI_FC 0x4fcc4d +#define regNIC400_1_ASIB_1_KI_FC_BASE_IDX 3 +#define regNIC400_1_ASIB_1_QOS_RANGE 0x4fcc4e +#define regNIC400_1_ASIB_1_QOS_RANGE_BASE_IDX 3 +#define regNIC400_1_IB_0_FN_MOD 0x4ff842 +#define regNIC400_1_IB_0_FN_MOD_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_syshub_mmreg_syshubdec +// base address: 0x0 +#define regSYSHUB_INDEX 0x0008 +#define regSYSHUB_INDEX_BASE_IDX 0 +#define regSYSHUB_DATA 0x0009 +#define regSYSHUB_DATA_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_rc_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_RC_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_RC_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_RC_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_RC_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_RC_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_RC_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_RC_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_RC_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_RC_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_RC_HEADER 0x000e +#define cfgBIF_CFG_DEV0_RC_BIST 0x000f +#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_2 0x0014 +#define cfgSUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgIO_BASE_LIMIT 0x001c +#define cfgSECONDARY_STATUS 0x001e +#define cfgMEM_BASE_LIMIT 0x0020 +#define cfgPREF_BASE_LIMIT 0x0024 +#define cfgPREF_BASE_UPPER 0x0028 +#define cfgPREF_LIMIT_UPPER 0x002c +#define cfgIO_BASE_LIMIT_HI 0x0030 +#define cfgBIF_CFG_DEV0_RC_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_RC_ROM_BASE_ADDR 0x0038 +#define cfgBIF_CFG_DEV0_RC_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_RC_INTERRUPT_PIN 0x003d +#define cfgIRQ_BRIDGE_CNTL 0x003e +#define cfgEXT_BRIDGE_CNTL 0x0040 +#define cfgBIF_CFG_DEV0_RC_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_RC_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_RC_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_RC_PCIE_CAP_LIST 0x0058 +#define cfgBIF_CFG_DEV0_RC_PCIE_CAP 0x005a +#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP 0x005c +#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL 0x0060 +#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS 0x0062 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP 0x0064 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL 0x0068 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS 0x006a +#define cfgSLOT_CAP 0x006c +#define cfgSLOT_CNTL 0x0070 +#define cfgSLOT_STATUS 0x0072 +#define cfgROOT_CNTL 0x0074 +#define cfgROOT_CAP 0x0076 +#define cfgROOT_STATUS 0x0078 +#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP2 0x007c +#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL2 0x0080 +#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS2 0x0082 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP2 0x0084 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL2 0x0088 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS2 0x008a +#define cfgSLOT_CAP2 0x008c +#define cfgSLOT_CNTL2 0x0090 +#define cfgSLOT_STATUS2 0x0092 +#define cfgBIF_CFG_DEV0_RC_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgSSID_CAP_LIST 0x00c0 +#define cfgSSID_CAP 0x00c4 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_RC_PCIE_LINK_CNTL3 0x0114 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS 0x0118 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL 0x011c +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL 0x011e +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL 0x0120 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL 0x0122 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL 0x0126 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL 0x0128 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL 0x012a +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL 0x012c +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL 0x012e +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL 0x0132 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL 0x0134 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL 0x0136 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL 0x0138 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL 0x013a +#define cfgBIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST 0x01b8 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP_16GT 0x01bc +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL_16GT 0x01c0 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS_16GT 0x01c4 +#define cfgBIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x01c8 +#define cfgBIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT 0x01cc +#define cfgBIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT 0x01d0 +#define cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT 0x01d8 +#define cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT 0x01d9 +#define cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT 0x01da +#define cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT 0x01db +#define cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT 0x01dc +#define cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT 0x01dd +#define cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT 0x01de +#define cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT 0x01df +#define cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT 0x01e0 +#define cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT 0x01e1 +#define cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT 0x01e2 +#define cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT 0x01e3 +#define cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT 0x01e4 +#define cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT 0x01e5 +#define cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT 0x01e6 +#define cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT 0x01e7 +#define cfgBIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST 0x01f8 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP_32GT 0x01fc +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL_32GT 0x0200 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS_32GT 0x0204 +#define cfgBIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1 0x0208 +#define cfgBIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2 0x020c +#define cfgBIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1 0x0210 +#define cfgBIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2 0x0214 +#define cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT 0x0218 +#define cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT 0x0219 +#define cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT 0x021a +#define cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT 0x021b +#define cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT 0x021c +#define cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT 0x021d +#define cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT 0x021e +#define cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT 0x021f +#define cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT 0x0220 +#define cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT 0x0221 +#define cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT 0x0222 +#define cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT 0x0223 +#define cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT 0x0224 +#define cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT 0x0225 +#define cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT 0x0226 +#define cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT 0x0227 +#define cfgBIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST 0x0238 +#define cfgBIF_CFG_DEV0_RC_AP_CAP 0x023c +#define cfgBIF_CFG_DEV0_RC_AP_CNTL 0x0240 +#define cfgBIF_CFG_DEV0_RC_AP_DATA1 0x0244 +#define cfgBIF_CFG_DEV0_RC_AP_DATA2 0x0248 +#define cfgBIF_CFG_DEV0_RC_AP_SEL_EN_MASK 0x024c +#define cfgBIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_CAP 0x0254 +#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_STATUS 0x0256 +#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL 0x0258 +#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS 0x025a +#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL 0x025c +#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS 0x025e +#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL 0x0260 +#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS 0x0262 +#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL 0x0264 +#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS 0x0266 +#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL 0x0268 +#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS 0x026a +#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL 0x026c +#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS 0x026e +#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL 0x0270 +#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS 0x0272 +#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL 0x0274 +#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS 0x0276 +#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL 0x0278 +#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS 0x027a +#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL 0x027c +#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS 0x027e +#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS 0x0282 +#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS 0x0286 +#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS 0x028a +#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL 0x028c +#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS 0x028e +#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS 0x0292 +#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS 0x0296 +#define cfgBIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST 0x0404 +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1 0x0408 +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2 0x040c +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL 0x0410 +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS 0x0412 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP 0x0414 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL 0x0418 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS 0x041e +#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP 0x0420 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL 0x0424 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS 0x042a +#define cfgBIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST 0x0430 +#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP 0x0434 +#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS 0x0438 +#define cfgBIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG3 0x062c +#define cfgPCIE_ROOT_ERR_CMD 0x0630 +#define cfgPCIE_ROOT_ERR_STATUS 0x0634 +#define cfgPCIE_ERR_SRC_ID 0x0638 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0664 +#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1 0x0668 +#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2 0x066c +#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST 0x06dc +#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CAP 0x06e0 +#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CNTL 0x06e2 +#define cfgBIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_RC_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_RC_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST 0x0e00 +#define cfgBIF_CFG_DEV0_RC_IDE_CAP 0x0e04 +#define cfgBIF_CFG_DEV0_RC_IDE_CNTL 0x0e08 +#define cfgBIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL 0x0e0c +#define cfgBIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS 0x0e10 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CAP 0x0e14 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL 0x0e18 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS 0x0e1c +#define cfgBIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG1 0x0e20 +#define cfgBIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2 0x0e24 +#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1 0x0e28 +#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG2 0x0e2c +#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG3 0x0e30 +#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1 0x0e34 +#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG2 0x0e38 +#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG3 0x0e3c +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CAP 0x0e40 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL 0x0e44 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS 0x0e48 +#define cfgBIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG1 0x0e4c +#define cfgBIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2 0x0e50 +#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1 0x0e54 +#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG2 0x0e58 +#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG3 0x0e5c +#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1 0x0e60 +#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG2 0x0e64 +#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG3 0x0e68 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CAP 0x0e6c +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL 0x0e70 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS 0x0e74 +#define cfgBIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG1 0x0e78 +#define cfgBIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2 0x0e7c +#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1 0x0e80 +#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG2 0x0e84 +#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG3 0x0e88 +#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1 0x0e8c +#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG2 0x0e90 +#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG3 0x0e94 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CAP 0x0e98 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL 0x0e9c +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS 0x0ea0 +#define cfgBIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG1 0x0ea4 +#define cfgBIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2 0x0ea8 +#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1 0x0eac +#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG2 0x0eb0 +#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG3 0x0eb4 +#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1 0x0eb8 +#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG2 0x0ebc +#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG3 0x0ec0 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CAP 0x0ec4 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL 0x0ec8 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS 0x0ecc +#define cfgBIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG1 0x0ed0 +#define cfgBIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2 0x0ed4 +#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1 0x0ed8 +#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG2 0x0edc +#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG3 0x0ee0 +#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1 0x0ee4 +#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG2 0x0ee8 +#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG3 0x0eec +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CAP 0x0ef0 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL 0x0ef4 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS 0x0ef8 +#define cfgBIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG1 0x0efc +#define cfgBIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2 0x0f00 +#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1 0x0f04 +#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG2 0x0f08 +#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG3 0x0f0c +#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1 0x0f10 +#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG2 0x0f14 +#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG3 0x0f18 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CAP 0x0f1c +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL 0x0f20 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS 0x0f24 +#define cfgBIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG1 0x0f28 +#define cfgBIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2 0x0f2c +#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1 0x0f30 +#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG2 0x0f34 +#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG3 0x0f38 +#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1 0x0f3c +#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG2 0x0f40 +#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG3 0x0f44 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CAP 0x0f48 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL 0x0f4c +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS 0x0f50 +#define cfgBIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG1 0x0f54 +#define cfgBIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2 0x0f58 +#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1 0x0f5c +#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG2 0x0f60 +#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG3 0x0f64 +#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1 0x0f68 +#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG2 0x0f6c +#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG3 0x0f70 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CAP 0x0f74 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL 0x0f78 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS 0x0f7c +#define cfgBIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG1 0x0f80 +#define cfgBIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2 0x0f84 +#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1 0x0f88 +#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG2 0x0f8c +#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG3 0x0f90 +#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1 0x0f94 +#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG2 0x0f98 +#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG3 0x0f9c + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF0_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF0_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF1_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF1_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF2_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF2_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF2_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF2_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF2_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF3_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF3_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF3_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF3_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF3_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF4_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF4_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF4_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF4_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF4_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF5_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF5_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF5_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF5_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF5_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF6_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF6_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF6_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF6_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF6_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF7_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF7_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF7_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF7_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF7_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf1_vf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF1_VF0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF1_VF0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF1_VF0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF1_VF0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF1_VF0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF1_VF0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF1_VF0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF1_VF0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF1_VF0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF1_VF0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF1_VF0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF1_VF0_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF1_VF0_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL 0x0776 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_sh_mask.h new file mode 100644 index 000000000000..9f8f8b3eba02 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_sh_mask.h @@ -0,0 +1,49475 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _nbio_6_3_2_SH_MASK_HEADER +#define _nbio_6_3_2_SH_MASK_HEADER + + +// addressBlock: nbif0_nbif0_bif_bx_SYSDEC +//BIF_BX0_SYSHUB_INDEX_OVLP +#define BIF_BX0_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0 +#define BIF_BX0_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL +//BIF_BX0_SYSHUB_DATA_OVLP +#define BIF_BX0_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0 +#define BIF_BX0_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL +//BIF_BX0_SYSHUB_INDEX_HI_OVLP +#define BIF_BX0_SYSHUB_INDEX_HI_OVLP__SYSHUB_OFFSET_HI__SHIFT 0x0 +#define BIF_BX0_SYSHUB_INDEX_HI_OVLP__SYSHUB_OFFSET_HI_MASK 0x0000FFFFL +//BIF_BX0_PCIE_INDEX +#define BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_DATA +#define BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define BIF_BX0_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_INDEX2 +#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_DATA2 +#define BIF_BX0_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 +#define BIF_BX0_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_INDEX_HI +#define BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK 0x0000FFFFL +//BIF_BX0_PCIE_INDEX2_HI +#define BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK 0x0000FFFFL +//BIF_BX0_SBIOS_SCRATCH_0 +#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_1 +#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_2 +#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_3 +#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_0 +#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_1 +#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_2 +#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_3 +#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_4 +#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_5 +#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_6 +#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_7 +#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_8 +#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_9 +#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_10 +#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_11 +#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_12 +#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_13 +#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_14 +#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_15 +#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX0_BIF_RLC_INTR_CNTL +//BIF_BX0_BIF_VCE_INTR_CNTL +//BIF_BX0_BIF_UVD_INTR_CNTL +//BIF_BX0_BIF_Engine_INTR_CNTL +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_CMD_COMPLETE__SHIFT 0x0 +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_HANG_SELF_RECOVERED__SHIFT 0x1 +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_HANG_NEED_FLR__SHIFT 0x2 +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_VM_BUSY_TRANSITION__SHIFT 0x3 +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_INST_SEL__SHIFT 0x1b +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_CMD_COMPLETE_MASK 0x00000001L +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_HANG_SELF_RECOVERED_MASK 0x00000002L +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_HANG_NEED_FLR_MASK 0x00000004L +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_VM_BUSY_TRANSITION_MASK 0x00000008L +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_INST_SEL_MASK 0xF8000000L +//BIF_BX0_GFX_MMIOREG_CAM_ADDR0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR1 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR2 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR3 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR4 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR5 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR6 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR7 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_CNTL +#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL +//BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL +#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL +#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_0 +#define BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_1 +#define BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_2 +#define BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_3 +#define BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_4 +#define BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_5 +#define BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_6 +#define BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_7 +#define BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_8 +#define BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_9 +#define BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_10 +#define BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_11 +#define BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_12 +#define BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_13 +#define BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_14 +#define BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_15 +#define BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_0 +#define BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_1 +#define BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_2 +#define BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_3 +#define BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_4 +#define BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_5 +#define BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_6 +#define BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_7 +#define BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_8 +#define BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_9 +#define BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_10 +#define BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_11 +#define BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_12 +#define BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_13 +#define BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_14 +#define BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_15 +#define BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_4 +#define BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_5 +#define BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_6 +#define BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_7 +#define BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_8 +#define BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_9 +#define BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_10 +#define BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_11 +#define BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_12 +#define BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_13 +#define BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_14 +#define BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_15 +#define BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dwn_dev0_BIFDEC1 +//RCC_DWN_DEV0_0_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_0_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_0_DN_PCIE_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT 0x5 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK 0x00000020L +//RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_BIFDEC1 +//RCC_DWNP_DEV0_0_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//RCC_DWNP_DEV0_0_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT 0x4 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK 0x00000010L +//RCC_DWNP_DEV0_0_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_ep_dev0_BIFDEC1 +//RCC_EP_DEV0_0_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_0_EP_PCIE_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_0_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_0_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT 0x5 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK 0x00000020L +//RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_0_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_0_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK 0x00000010L +//RCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3 +#define RCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L + + +// addressBlock: nbif0_nbif0_bif_bx_pf_SYSPFVFDEC +//BIF_BX_PF0_MM_INDEX +#define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_PF0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_PF0_MM_DATA +#define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MM_INDEX_HI +#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL +//BIF_BX_PF0_RSMU_INDEX +#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX__SHIFT 0x0 +#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX_MASK 0xFFFFFFFFL +//BIF_BX_PF0_RSMU_DATA +#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA__SHIFT 0x0 +#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_RSMU_INDEX_HI +#define BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI__SHIFT 0x0 +#define BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI_MASK 0x0000FFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_BIFDEC1 +//BIF_BX0_CC_BIF_BX_STRAP0 +#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19 +#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L +//BIF_BX0_CC_BIF_BX_PINSTRAP0 +//BIF_BX0_BIF_MM_INDACCESS_CNTL +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT 0x0 +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK 0x00000001L +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L +//BIF_BX0_BUS_CNTL +#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BIF_BX0_BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BIF_BX0_BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18 +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a +#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c +#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f +#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BIF_BX0_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L +#define BIF_BX0_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L +#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L +#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L +#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L +//BIF_BX0_BIF_SCRATCH0 +#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL +//BIF_BX0_BIF_SCRATCH1 +#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL +//BIF_BX0_BX_RESET_EN +#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L +//BIF_BX0_MM_CFGREGS_CNTL +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 +#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L +#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L +//BIF_BX0_BX_RESET_CNTL +#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L +//BIF_BX0_INTERRUPT_CNTL +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 +#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12 +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L +#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L +#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L +#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L +//BIF_BX0_INTERRUPT_CNTL2 +#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL +//BIF_BX0_CLKREQB_PAD_CNTL +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L +//BIF_BX0_BIF_FEATURES_CONTROL_MISC +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT 0xe +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x19 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK 0x00004000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x01FF0000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x02000000L +//BIF_BX0_HDP_ATOMIC_CONTROL_MISC +#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0 +#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL +//BIF_BX0_BIF_DOORBELL_CNTL +#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_LOCAL__SHIFT 0x5 +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L +#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L +#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L +#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L +#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L +#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_LOCAL_MASK 0x00000020L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L +//BIF_BX0_BIF_DOORBELL_INT_CNTL +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x17 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x00800000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L +//BIF_BX0_BIF_FB_EN +#define BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +//BIF_BX0_BIF_INTR_CNTL +#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 +#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L +//BIF_BX0_BIF_MST_TRANS_PENDING_VF +#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX0_BIF_SLV_TRANS_PENDING_VF +#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX0_BACO_CNTL +#define BIF_BX0_BACO_CNTL__BACO_EN__SHIFT 0x0 +#define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 +#define BIF_BX0_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +#define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 +#define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 +#define BIF_BX0_BACO_CNTL__BACO_MODE__SHIFT 0x8 +#define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 +#define BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT 0x10 +#define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f +#define BIF_BX0_BACO_CNTL__BACO_EN_MASK 0x00000001L +#define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L +#define BIF_BX0_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L +#define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L +#define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L +#define BIF_BX0_BACO_CNTL__BACO_MODE_MASK 0x00000100L +#define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L +#define BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC_MASK 0x00010000L +#define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L +//BIF_BX0_BIF_BACO_EXIT_TIME0 +#define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX0_BIF_BACO_EXIT_TIMER1 +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L +//BIF_BX0_BIF_BACO_EXIT_TIMER2 +#define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL +//BIF_BX0_BIF_BACO_EXIT_TIMER3 +#define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX0_BIF_BACO_EXIT_TIMER4 +#define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX0_MEM_TYPE_CNTL +#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L +//BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L +//BIF_BX0_NBIF_GFX_ADDR_LUT_0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_1 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_2 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_3 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_4 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_5 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_6 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_7 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_8 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_9 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_10 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_11 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_12 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_13 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_14 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_15 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_VF_REGWR_EN +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT 0x0 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT 0x1 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT 0x2 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT 0x3 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT 0x4 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT 0x5 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT 0x6 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT 0x7 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT 0x8 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT 0x9 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT 0xa +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT 0xb +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT 0xc +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT 0xd +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT 0xe +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT 0xf +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT 0x10 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT 0x11 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT 0x12 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT 0x13 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT 0x14 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT 0x15 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT 0x16 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT 0x17 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT 0x18 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT 0x19 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT 0x1a +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT 0x1b +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT 0x1c +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT 0x1d +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT 0x1e +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK 0x00000001L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK 0x00000002L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK 0x00000004L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK 0x00000008L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK 0x00000010L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK 0x00000020L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK 0x00000040L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK 0x00000080L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK 0x00000100L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK 0x00000200L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK 0x00000400L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK 0x00000800L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK 0x00001000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK 0x00002000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK 0x00004000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK 0x00008000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK 0x00010000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK 0x00020000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK 0x00040000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK 0x00080000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK 0x00100000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK 0x00200000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK 0x00400000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK 0x00800000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK 0x01000000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK 0x02000000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK 0x04000000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK 0x08000000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK 0x10000000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK 0x20000000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK 0x40000000L +//BIF_BX0_VF_DOORBELL_EN +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT 0x0 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT 0x1 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT 0x2 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT 0x3 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT 0x4 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT 0x5 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT 0x6 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT 0x7 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT 0x8 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT 0x9 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT 0xa +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT 0xb +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT 0xc +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT 0xd +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT 0xe +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT 0xf +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT 0x10 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT 0x11 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT 0x12 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT 0x13 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT 0x14 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT 0x15 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT 0x16 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT 0x17 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT 0x18 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT 0x19 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT 0x1a +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT 0x1b +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT 0x1c +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT 0x1d +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT 0x1e +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT 0x1f +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK 0x00000001L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK 0x00000002L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK 0x00000004L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK 0x00000008L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK 0x00000010L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK 0x00000020L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK 0x00000040L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK 0x00000080L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK 0x00000100L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK 0x00000200L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK 0x00000400L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK 0x00000800L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK 0x00001000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK 0x00002000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK 0x00004000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK 0x00008000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK 0x00010000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK 0x00020000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK 0x00040000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK 0x00080000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK 0x00100000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK 0x00200000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK 0x00400000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK 0x00800000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK 0x01000000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK 0x02000000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK 0x04000000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK 0x08000000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK 0x10000000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK 0x20000000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK 0x40000000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK 0x80000000L +//BIF_BX0_VF_FB_EN +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF0__SHIFT 0x0 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF1__SHIFT 0x1 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF2__SHIFT 0x2 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF3__SHIFT 0x3 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF4__SHIFT 0x4 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF5__SHIFT 0x5 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF6__SHIFT 0x6 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF7__SHIFT 0x7 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF8__SHIFT 0x8 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF9__SHIFT 0x9 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF10__SHIFT 0xa +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF11__SHIFT 0xb +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF12__SHIFT 0xc +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF13__SHIFT 0xd +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF14__SHIFT 0xe +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF15__SHIFT 0xf +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF16__SHIFT 0x10 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF17__SHIFT 0x11 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF18__SHIFT 0x12 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF19__SHIFT 0x13 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF20__SHIFT 0x14 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF21__SHIFT 0x15 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF22__SHIFT 0x16 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF23__SHIFT 0x17 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF24__SHIFT 0x18 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF25__SHIFT 0x19 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF26__SHIFT 0x1a +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF27__SHIFT 0x1b +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF28__SHIFT 0x1c +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF29__SHIFT 0x1d +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF30__SHIFT 0x1e +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF0_MASK 0x00000001L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF1_MASK 0x00000002L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF2_MASK 0x00000004L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF3_MASK 0x00000008L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF4_MASK 0x00000010L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF5_MASK 0x00000020L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF6_MASK 0x00000040L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF7_MASK 0x00000080L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF8_MASK 0x00000100L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF9_MASK 0x00000200L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF10_MASK 0x00000400L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF11_MASK 0x00000800L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF12_MASK 0x00001000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF13_MASK 0x00002000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF14_MASK 0x00004000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF15_MASK 0x00008000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF16_MASK 0x00010000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF17_MASK 0x00020000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF18_MASK 0x00040000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF19_MASK 0x00080000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF20_MASK 0x00100000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF21_MASK 0x00200000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF22_MASK 0x00400000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF23_MASK 0x00800000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF24_MASK 0x01000000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF25_MASK 0x02000000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF26_MASK 0x04000000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF27_MASK 0x08000000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF28_MASK 0x10000000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF29_MASK 0x20000000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF30_MASK 0x40000000L +//BIF_BX0_VF_REGWR_STATUS +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT 0x0 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT 0x1 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT 0x2 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT 0x3 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT 0x4 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT 0x5 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT 0x6 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT 0x7 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT 0x8 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT 0x9 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT 0xa +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT 0xb +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT 0xc +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT 0xd +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT 0xe +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT 0xf +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT 0x10 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT 0x11 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT 0x12 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT 0x13 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT 0x14 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT 0x15 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT 0x16 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT 0x17 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT 0x18 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT 0x19 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT 0x1a +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT 0x1b +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT 0x1c +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT 0x1d +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT 0x1e +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK 0x00000001L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK 0x00000002L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK 0x00000004L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK 0x00000008L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK 0x00000010L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK 0x00000020L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK 0x00000040L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK 0x00000080L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK 0x00000100L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK 0x00000200L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK 0x00000400L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK 0x00000800L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK 0x00001000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK 0x00002000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK 0x00004000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK 0x00008000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK 0x00010000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK 0x00020000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK 0x00040000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK 0x00080000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK 0x00100000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK 0x00200000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK 0x00400000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK 0x00800000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK 0x01000000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK 0x02000000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK 0x04000000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK 0x08000000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK 0x10000000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK 0x20000000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK 0x40000000L +//BIF_BX0_VF_DOORBELL_STATUS +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT 0x0 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT 0x1 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT 0x2 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT 0x3 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT 0x4 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT 0x5 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT 0x6 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT 0x7 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT 0x8 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT 0x9 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT 0xa +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT 0xb +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT 0xc +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT 0xd +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT 0xe +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT 0xf +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT 0x10 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT 0x11 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT 0x12 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT 0x13 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT 0x14 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT 0x15 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT 0x16 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT 0x17 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT 0x18 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT 0x19 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT 0x1a +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT 0x1b +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT 0x1c +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT 0x1d +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT 0x1e +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK 0x00000001L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK 0x00000002L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK 0x00000004L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK 0x00000008L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK 0x00000010L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK 0x00000020L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK 0x00000040L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK 0x00000080L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK 0x00000100L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK 0x00000200L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK 0x00000400L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK 0x00000800L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK 0x00001000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK 0x00002000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK 0x00004000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK 0x00008000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK 0x00010000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK 0x00020000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK 0x00040000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK 0x00080000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK 0x00100000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK 0x00200000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK 0x00400000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK 0x00800000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK 0x01000000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK 0x02000000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK 0x04000000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK 0x08000000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK 0x10000000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK 0x20000000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK 0x40000000L +//BIF_BX0_VF_FB_STATUS +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT 0x0 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT 0x1 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT 0x2 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT 0x3 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT 0x4 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT 0x5 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT 0x6 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT 0x7 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT 0x8 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT 0x9 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT 0xa +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT 0xb +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT 0xc +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT 0xd +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT 0xe +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT 0xf +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT 0x10 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT 0x11 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT 0x12 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT 0x13 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT 0x14 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT 0x15 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT 0x16 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT 0x17 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT 0x18 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT 0x19 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT 0x1a +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT 0x1b +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT 0x1c +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT 0x1d +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT 0x1e +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK 0x00000001L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK 0x00000002L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK 0x00000004L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK 0x00000008L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK 0x00000010L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK 0x00000020L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK 0x00000040L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK 0x00000080L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK 0x00000100L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK 0x00000200L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK 0x00000400L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK 0x00000800L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK 0x00001000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK 0x00002000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK 0x00004000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK 0x00008000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK 0x00010000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK 0x00020000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK 0x00040000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK 0x00080000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK 0x00100000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK 0x00200000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK 0x00400000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK 0x00800000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK 0x01000000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK 0x02000000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK 0x04000000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK 0x08000000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK 0x10000000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK 0x20000000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK 0x40000000L +//BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL +#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL +#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX0_BIF_RB_CNTL +#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_BX0_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT 0x19 +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d +#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e +#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define BIF_BX0_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L +#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L +#define BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK 0x02000000L +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L +#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L +#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//BIF_BX0_BIF_RB_BASE +#define BIF_BX0_BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_BX0_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//BIF_BX0_BIF_RB_RPTR +#define BIF_BX0_BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_BX0_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX0_BIF_RB_WPTR +#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_BX0_BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L +#define BIF_BX0_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX0_BIF_RB_WPTR_ADDR_HI +#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL +//BIF_BX0_BIF_RB_WPTR_ADDR_LO +#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//BIF_BX0_MAILBOX_INDEX +#define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 +#define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL +//BIF_BX0_BACO_AZ_ENHANCE_CTRL +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET__SHIFT 0x2 +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE__SHIFT 0x10 +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO__SHIFT 0x11 +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO__SHIFT 0x1f +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET_MASK 0x00003FFCL +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE_MASK 0x00010000L +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO_MASK 0x00020000L +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO_MASK 0x80000000L +//BIF_BX0_BIF_MP1_INTR_CTRL +#define BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT 0x0 +#define BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK 0x00000001L +//BIF_BX0_BIF_PERSTB_PAD_CNTL +#define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL +//BIF_BX0_BIF_PX_EN_PAD_CNTL +#define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x00000FFFL +//BIF_BX0_BIF_REFPADKIN_PAD_CNTL +#define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL +//BIF_BX0_BIF_CLKREQB_PAD_CNTL +#define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x7FFFFFFFL +//BIF_BX0_BIF_PWRBRK_PAD_CNTL +#define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL +//BIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE +#define BIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE__GPUIOV_SCH_CFG_SIZE__SHIFT 0x0 +#define BIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE__GPUIOV_SCH_CFG_SIZE_MASK 0x0000000FL + + +// addressBlock: nbif0_nbif0_rcc_dev0_BIFDEC1 +//RCC_DEV0_0_RCC_ERR_INT_CNTL +#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L +//RCC_DEV0_0_RCC_BACO_CNTL_MISC +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L +//RCC_DEV0_0_RCC_RESET_EN +#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf +#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L +//RCC_DEV0_0_RCC_VDM_SUPPORT +#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L +//RCC_DEV0_0_RCC_GPUIOV_REGION +#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//RCC_DEV0_0_RCC_GPU_HOSTVM_EN +#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L +//RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L +//RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET +#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE +#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL +//RCC_DEV0_0_RCC_PEER_REG_RANGE0 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_0_RCC_PEER_REG_RANGE1 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_0_RCC_BUS_CNTL +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_DEV0_0_RCC_CONFIG_CNTL +#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L +//RCC_DEV0_0_RCC_CONFIG_F0_BASE +#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL +//RCC_DEV0_0_RCC_CONFIG_APER_SIZE +#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE +#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL +//RCC_DEV0_0_RCC_XDMA_LO +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_XDMA_HI +#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL +//RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_DEV0_0_RCC_BUSNUM_CNTL1 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL +//RCC_DEV0_0_RCC_BUSNUM_LIST0 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L +//RCC_DEV0_0_RCC_BUSNUM_LIST1 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L +//RCC_DEV0_0_RCC_BUSNUM_CNTL2 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L +//RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM +#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L +//RCC_DEV0_0_RCC_HOST_BUSNUM +#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 +#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL +//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L +//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L +//RCC_DEV0_0_RCC_DEV0_LINK_CNTL +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_DEV0_0_RCC_CMN_LINK_CNTL +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG__SHIFT 0x10 +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG_MASK 0x00FF0000L +//RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL +#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_DEV0_0_RCC_MH_ARB_CNTL +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x0000FFFEL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_BIFDEC2 +//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_PBA +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L + + +// addressBlock: nbif0_nbif0_rcc_strap_BIFDEC1 +//RCC_STRAP0_RCC_BIF_STRAP0 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x14 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN__SHIFT 0x15 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GPUIOV_EN__SHIFT 0x16 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE__SHIFT 0x17 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00100000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN_MASK 0x00200000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GPUIOV_EN_MASK 0x00400000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE_MASK 0x00800000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP1 +#define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT__SHIFT 0x4 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT_MASK 0x00000010L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP10 +//RCC_STRAP0_RCC_BIF_STRAP11 +//RCC_STRAP0_RCC_BIF_STRAP12 +//RCC_STRAP0_RCC_BIF_STRAP13 +#define RCC_STRAP0_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER_MASK 0x00000FFFL +//RCC_STRAP0_RCC_BIF_STRAP2 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SPT__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWDS_SPT__SHIFT 0x2 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ARI_EN_UP__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SPT_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWDS_SPT_MASK 0x00000004L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ARI_EN_UP_MASK 0x02000000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP3 +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_BIF_STRAP4 +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_BIF_STRAP5 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP6 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL__SHIFT 0x3 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE__SHIFT 0x5 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6__SHIFT 0xf +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL_MASK 0x00000008L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE_MASK 0x00000020L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN_MASK 0x00007C00L +#define RCC_STRAP0_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6_MASK 0xFFFF8000L +//RCC_STRAP0_RCC_BIF_STRAP7 +#define RCC_STRAP0_RCC_BIF_STRAP7__STRAP_GEN6_DIS__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6__SHIFT 0x1a +#define RCC_STRAP0_RCC_BIF_STRAP7__STRAP_GEN6_DIS_MASK 0x02000000L +#define RCC_STRAP0_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6_MASK 0x04000000L +//RCC_STRAP0_RCC_BIF_STRAP8 +//RCC_STRAP0_RCC_BIF_STRAP9 +//RCC_STRAP0_RCC_DEV0_PORT_STRAP0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0_MASK 0x03000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0_MASK 0x0C000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x02000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0_MASK 0x38000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0_MASK 0x00000E00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0_MASK 0x00002000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0_MASK 0xFFFFFFFFL +//RCC_STRAP0_RCC_DEV0_PORT_STRAP16 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0_MASK 0xFFFFFFFFL +//RCC_STRAP0_RCC_DEV0_PORT_STRAP17 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0_MASK 0x0000E000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0_MASK 0x02000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0_MASK 0x0000000FL +//RCC_STRAP0_RCC_DEV0_PORT_STRAP2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP1 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0_MASK 0x000FF000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP19 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP2 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP22 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x0001F000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x003E0000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK 0x07C00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK 0xF8000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP23 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0_MASK 0xFFFFFFFFL +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP24 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0_MASK 0xFFFFFFFFL +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP3 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0_MASK 0x02000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP4 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP5 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP9 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0_MASK 0x10000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP1 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP10 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP11 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP12 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP13 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK 0x0000FFFFL +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP15 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1_MASK 0x00FFF000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1_MASK 0x01000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP16 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1_MASK 0x00FFF000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP17 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1_MASK 0x00001000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1_MASK 0x01FFE000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1_MASK 0x000FF000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP19 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP2 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP20 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP21 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP23 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP24 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP3 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1_MASK 0x02000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP4 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP5 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP6 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1__SHIFT 0xa +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000200L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1_MASK 0x00000400L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK 0x02000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1_MASK 0x08000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP7 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP8 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1_MASK 0xC0000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP9 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1_MASK 0x10000000L + + +// addressBlock: nbif0_nbif0_bif_bx_pf_BIFPFVFDEC1 +//BIF_BX_PF0_BIF_BME_STATUS +#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_PF0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF0_GPU_HDP_FLUSH_REQ +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF0_GPU_HDP_FLUSH_DONE +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF0_BIF_TRANS_PENDING +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_CONTROL +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_PF0_MAILBOX_INT_CNTL +#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_PF0_BIF_VMHV_MAILBOX +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_PF0_PARTITION_COMPUTE_CAP +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_PF0_PARTITION_MEM_CAP +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_PF0_PARTITION_COMPUTE_STATUS +#define BIF_BX_PF0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_PF0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_PF0_PARTITION_MEM_STATUS +#define BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_BIFPFVFDEC1 +//RCC_DEV0_EPF0_RCC_ERR_LOG +#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_gdc_GDCDEC +//GDC0_NGDC_SDP_PORT_CTRL +#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 +#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H__SHIFT 0x10 +#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_DIS__SHIFT 0x1f +#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x000000FFL +#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H_MASK 0x000F0000L +#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_DIS_MASK 0x80000000L +//GDC0_SHUB_REGS_IF_CTL +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT 0x1 +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK 0x00000002L +//GDC0_NGDC_MGCG_CTRL +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0 +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1 +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2 +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT 0xa +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT 0xb +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT 0xc +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT 0xd +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS__SHIFT 0xe +#define GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT 0xf +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003FCL +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK 0x00000400L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK 0x00000800L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK 0x00001000L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK 0x00002000L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS_MASK 0x00004000L +#define GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK 0x00008000L +//GDC0_S2A_MISC_CNTL +#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 +#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8 +#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa +#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc +#define GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT 0xf +#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10 +#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L +#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L +#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L +#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L +#define GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK 0x00008000L +#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L +//GDC0_NGDC_MCA_SMN_CTRL0 +#define GDC0_NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED__SHIFT 0x0 +#define GDC0_NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED_MASK 0x00000001L +//GDC0_NGDC_EARLY_WAKEUP_CTRL +#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0 +#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1 +#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2 +#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L +#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L +#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L +//GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_BYPASS__SHIFT 0x0 +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_ACCUM_SEL__SHIFT 0x1 +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_EN__SHIFT 0x2 +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_DATA__SHIFT 0x3 +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_STATUS_ACCUM_EN__SHIFT 0x4 +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_DATASTATUS_ACCUM_EN__SHIFT 0x5 +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_BYPASS_MASK 0x00000001L +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_ACCUM_SEL_MASK 0x00000002L +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_EN_MASK 0x00000004L +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_DATA_MASK 0x00000008L +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_STATUS_ACCUM_EN_MASK 0x00000010L +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_DATASTATUS_ACCUM_EN_MASK 0x00000020L +//GDC0_GDC_DMA_SION_PCTRL +#define GDC0_GDC_DMA_SION_PCTRL__BIF_SDP_DISCON_DIS__SHIFT 0x0 +#define GDC0_GDC_DMA_SION_PCTRL__SYSHUB_SDP_DISCON_DIS__SHIFT 0x3 +#define GDC0_GDC_DMA_SION_PCTRL__INT_SDP_DISCON_DIS__SHIFT 0x6 +#define GDC0_GDC_DMA_SION_PCTRL__BIF_SDP_DISCON_DIS_MASK 0x00000001L +#define GDC0_GDC_DMA_SION_PCTRL__SYSHUB_SDP_DISCON_DIS_MASK 0x00000008L +#define GDC0_GDC_DMA_SION_PCTRL__INT_SDP_DISCON_DIS_MASK 0x00000040L +//GDC0_NGDC_MP4SDP_CNTL +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN__SHIFT 0x0 +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL__SHIFT 0x1 +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN__SHIFT 0x4 +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL__SHIFT 0x5 +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN__SHIFT 0x8 +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL__SHIFT 0x9 +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN_MASK 0x00000001L +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL_MASK 0x00000006L +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN_MASK 0x00000010L +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL_MASK 0x00000060L +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN_MASK 0x00000100L +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL_MASK 0x00000600L +//GDC0_DOORBELL_VCN_TARGET_VF0 +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN0_TARGET_VF0__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN1_TARGET_VF0__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN2_TARGET_VF0__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN3_TARGET_VF0__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN0_TARGET_VF0_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN1_TARGET_VF0_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN2_TARGET_VF0_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN3_TARGET_VF0_MASK 0xF000L +//GDC0_DOORBELL_VCN_TARGET_VF1 +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN0_TARGET_VF1__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN1_TARGET_VF1__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN2_TARGET_VF1__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN3_TARGET_VF1__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN0_TARGET_VF1_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN1_TARGET_VF1_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN2_TARGET_VF1_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN3_TARGET_VF1_MASK 0xF000L +//GDC0_DOORBELL_VCN_TARGET_VF2 +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN0_TARGET_VF2__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN1_TARGET_VF2__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN2_TARGET_VF2__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN3_TARGET_VF2__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN0_TARGET_VF2_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN1_TARGET_VF2_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN2_TARGET_VF2_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN3_TARGET_VF2_MASK 0xF000L +//GDC0_DOORBELL_VCN_TARGET_VF3 +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN0_TARGET_VF3__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN1_TARGET_VF3__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN2_TARGET_VF3__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN3_TARGET_VF3__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN0_TARGET_VF3_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN1_TARGET_VF3_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN2_TARGET_VF3_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN3_TARGET_VF3_MASK 0xF000L +//GDC0_DOORBELL_VCN_TARGET_VF4 +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN0_TARGET_VF4__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN1_TARGET_VF4__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN2_TARGET_VF4__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN3_TARGET_VF4__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN0_TARGET_VF4_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN1_TARGET_VF4_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN2_TARGET_VF4_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN3_TARGET_VF4_MASK 0xF000L +//GDC0_DOORBELL_VCN_TARGET_VF5 +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN0_TARGET_VF5__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN1_TARGET_VF5__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN2_TARGET_VF5__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN3_TARGET_VF5__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN0_TARGET_VF5_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN1_TARGET_VF5_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN2_TARGET_VF5_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN3_TARGET_VF5_MASK 0xF000L +//GDC0_DOORBELL_VCN_TARGET_VF6 +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN0_TARGET_VF6__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN1_TARGET_VF6__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN2_TARGET_VF6__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN3_TARGET_VF6__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN0_TARGET_VF6_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN1_TARGET_VF6_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN2_TARGET_VF6_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN3_TARGET_VF6_MASK 0xF000L +//GDC0_DOORBELL_VCN_TARGET_VF7 +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN0_TARGET_VF7__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN1_TARGET_VF7__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN2_TARGET_VF7__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN3_TARGET_VF7__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN0_TARGET_VF7_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN1_TARGET_VF7_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN2_TARGET_VF7_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN3_TARGET_VF7_MASK 0xF000L +//GDC0_DOORBELL_ACCESS_EN_PF +#define GDC0_DOORBELL_ACCESS_EN_PF__DOORBELL_ACCESS_EN_PF__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_PF__DOORBELL_ACCESS_EN_PF_MASK 0x00FFL +//GDC0_DOORBELL_ACCESS_EN_VF0 +#define GDC0_DOORBELL_ACCESS_EN_VF0__DOORBELL_ACCESS_EN_VF0__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF0__XCD_ACCESS_EN_VF0__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF0__DOORBELL_ACCESS_EN_VF0_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF0__XCD_ACCESS_EN_VF0_MASK 0xFF00L +//GDC0_DOORBELL_ACCESS_EN_VF1 +#define GDC0_DOORBELL_ACCESS_EN_VF1__DOORBELL_ACCESS_EN_VF1__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF1__XCD_ACCESS_EN_VF1__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF1__DOORBELL_ACCESS_EN_VF1_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF1__XCD_ACCESS_EN_VF1_MASK 0xFF00L +//GDC0_DOORBELL_ACCESS_EN_VF2 +#define GDC0_DOORBELL_ACCESS_EN_VF2__DOORBELL_ACCESS_EN_VF2__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF2__XCD_ACCESS_EN_VF2__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF2__DOORBELL_ACCESS_EN_VF2_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF2__XCD_ACCESS_EN_VF2_MASK 0xFF00L +//GDC0_DOORBELL_ACCESS_EN_VF3 +#define GDC0_DOORBELL_ACCESS_EN_VF3__DOORBELL_ACCESS_EN_VF3__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF3__XCD_ACCESS_EN_VF3__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF3__DOORBELL_ACCESS_EN_VF3_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF3__XCD_ACCESS_EN_VF3_MASK 0xFF00L +//GDC0_DOORBELL_ACCESS_EN_VF4 +#define GDC0_DOORBELL_ACCESS_EN_VF4__DOORBELL_ACCESS_EN_VF4__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF4__XCD_ACCESS_EN_VF4__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF4__DOORBELL_ACCESS_EN_VF4_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF4__XCD_ACCESS_EN_VF4_MASK 0xFF00L +//GDC0_DOORBELL_ACCESS_EN_VF5 +#define GDC0_DOORBELL_ACCESS_EN_VF5__DOORBELL_ACCESS_EN_VF5__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF5__XCD_ACCESS_EN_VF5__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF5__DOORBELL_ACCESS_EN_VF5_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF5__XCD_ACCESS_EN_VF5_MASK 0xFF00L +//GDC0_DOORBELL_ACCESS_EN_VF6 +#define GDC0_DOORBELL_ACCESS_EN_VF6__DOORBELL_ACCESS_EN_VF6__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF6__XCD_ACCESS_EN_VF6__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF6__DOORBELL_ACCESS_EN_VF6_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF6__XCD_ACCESS_EN_VF6_MASK 0xFF00L +//GDC0_DOORBELL_ACCESS_EN_VF7 +#define GDC0_DOORBELL_ACCESS_EN_VF7__DOORBELL_ACCESS_EN_VF7__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF7__XCD_ACCESS_EN_VF7__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF7__DOORBELL_ACCESS_EN_VF7_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF7__XCD_ACCESS_EN_VF7_MASK 0xFF00L +//GDC0_NGDC_CNDI_BUS_PORT_CTRL +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_HYSTERESIS__SHIFT 0x0 +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_DIS_SOCCLK__SHIFT 0xc +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_HYSTERESIS__SHIFT 0xd +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_DIS_SOCCLK__SHIFT 0x19 +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_PORT_IDLE__SHIFT 0x1a +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__SHUB_CNDI_VDCI_CKEN_MASK__SHIFT 0x1b +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_HYSTERESIS_MASK 0x00000FFFL +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_DIS_SOCCLK_MASK 0x00001000L +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_HYSTERESIS_MASK 0x01FFE000L +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_DIS_SOCCLK_MASK 0x02000000L +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_PORT_IDLE_MASK 0x04000000L +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__SHUB_CNDI_VDCI_CKEN_MASK_MASK 0x08000000L +//GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC0_ALLOC__SHIFT 0x0 +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC1_ALLOC__SHIFT 0x4 +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC0_ALLOC__SHIFT 0x8 +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC1_ALLOC__SHIFT 0xc +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_REQ_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x10 +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_ORIGDATA_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x11 +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x12 +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x13 +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC0_ALLOC_MASK 0x0000000FL +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC1_ALLOC_MASK 0x000000F0L +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC0_ALLOC_MASK 0x00000F00L +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC1_ALLOC_MASK 0x0000F000L +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_REQ_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00010000L +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_ORIGDATA_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00020000L +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00040000L +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00080000L + + +// addressBlock: nbif0_nbif0_gdc_s2a_GDCS2A_DEC +//GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG +#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE_MASK 0x00000002L +//GDC_S2A0_NBIF_GFX_DOORBELL_STATUS +#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0 +#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN__SHIFT 0x10 +#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST__SHIFT 0x18 +#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x0000FFFFL +#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN_MASK 0x00010000L +#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST_MASK 0x01000000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_COMMAND +#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_STATUS +#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_LATENCY +#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_HEADER +#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_BIST +#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//VENDOR_CAP_LIST +#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//ADAPTER_ID_W +#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PMI_CAP +#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//PCIE_PWR_BUDGET_ENH_CAP_LIST +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_PWR_BUDGET_DATA_SELECT +#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE__SHIFT 0x10 +#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0x000000FFL +#define PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE_MASK 0x00010000L +//PCIE_PWR_BUDGET_DATA +#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//PCIE_PWR_BUDGET_CAP +#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT__SHIFT 0x1 +#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +#define PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT_MASK 0x02L +//PCIE_DPA_ENH_CAP_LIST +#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_DPA_CAP +#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//PCIE_DPA_LATENCY_INDICATOR +#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//PCIE_DPA_STATUS +#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//PCIE_DPA_CNTL +#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_LTR_ENH_CAP_LIST +#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_LTR_CAP +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//PCIE_BAR_ENH_CAP_LIST +#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_BAR1_CAP +#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_BAR1_CNTL +#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_BAR2_CAP +#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_BAR2_CNTL +#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_BAR3_CAP +#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_BAR3_CNTL +#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_BAR4_CAP +#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_BAR4_CNTL +#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_BAR5_CAP +#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_BAR5_CNTL +#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_BAR6_CAP +#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_BAR6_CNTL +#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//PCIE_PAGE_REQ_ENH_CAP_LIST +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_PAGE_REQ_CNTL +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L +#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L +//PCIE_PAGE_REQ_STATUS +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L +#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L +//PCIE_OUTSTAND_PAGE_REQ_CAPACITY +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL +//PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//PCIE_PASID_ENH_CAP_LIST +#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_PASID_CAP +#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED__SHIFT 0x3 +#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED_MASK 0x0008L +#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//PCIE_PASID_CNTL +#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE__SHIFT 0x3 +#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +#define PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE_MASK 0x0008L +//PCIE_SRIOV_ENH_CAP_LIST +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_SRIOV_CAP +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x3 +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000008L +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//PCIE_SRIOV_CONTROL +#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x6 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE_MASK 0x0040L +//PCIE_SRIOV_STATUS +#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//PCIE_SRIOV_INITIAL_VFS +#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//PCIE_SRIOV_TOTAL_VFS +#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//PCIE_SRIOV_NUM_VFS +#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//PCIE_SRIOV_FUNC_DEP_LINK +#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//PCIE_SRIOV_FIRST_VF_OFFSET +#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//PCIE_SRIOV_VF_STRIDE +#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//PCIE_SRIOV_VF_DEVICE_ID +#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_0 +#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_1 +#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_2 +#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_3 +#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_4 +#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_5 +#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//PCIE_VF_RESIZE_BAR_ENH_CAP_LIST +#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_VF_RESIZE_BAR1_CAP +#define PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_VF_RESIZE_BAR1_CNTL +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_VF_RESIZE_BAR2_CAP +#define PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_VF_RESIZE_BAR2_CNTL +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_VF_RESIZE_BAR3_CAP +#define PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_VF_RESIZE_BAR3_CNTL +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_VF_RESIZE_BAR4_CAP +#define PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_VF_RESIZE_BAR4_CNTL +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_VF_RESIZE_BAR5_CAP +#define PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_VF_RESIZE_BAR5_CNTL +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_VF_RESIZE_BAR6_CAP +#define PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_VF_RESIZE_BAR6_CNTL +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_DOE_ENH_CAP_LIST +#define PCIE_DOE_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_DOE_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_DOE_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_DOE_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_DOE_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_DOE_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_DOE_CAP +#define PCIE_DOE_CAP__INTR_SUPPORT__SHIFT 0x0 +#define PCIE_DOE_CAP__DOE_INTR_MSG_NUM__SHIFT 0x1 +#define PCIE_DOE_CAP__DOE_ATT_SUPPORT__SHIFT 0xc +#define PCIE_DOE_CAP__DOE_ASYNC_SUPPORT__SHIFT 0xd +#define PCIE_DOE_CAP__INTR_SUPPORT_MASK 0x00000001L +#define PCIE_DOE_CAP__DOE_INTR_MSG_NUM_MASK 0x00000FFEL +#define PCIE_DOE_CAP__DOE_ATT_SUPPORT_MASK 0x00001000L +#define PCIE_DOE_CAP__DOE_ASYNC_SUPPORT_MASK 0x00002000L +//PCIE_DOE_CNTL +#define PCIE_DOE_CNTL__DOE_ABORT__SHIFT 0x0 +#define PCIE_DOE_CNTL__DOE_INTR_EN__SHIFT 0x1 +#define PCIE_DOE_CNTL__DOE_ATT_NOT_NEED__SHIFT 0x2 +#define PCIE_DOE_CNTL__DOE_ASYNC_MSG_EN__SHIFT 0x3 +#define PCIE_DOE_CNTL__DOE_GO__SHIFT 0x1f +#define PCIE_DOE_CNTL__DOE_ABORT_MASK 0x00000001L +#define PCIE_DOE_CNTL__DOE_INTR_EN_MASK 0x00000002L +#define PCIE_DOE_CNTL__DOE_ATT_NOT_NEED_MASK 0x00000004L +#define PCIE_DOE_CNTL__DOE_ASYNC_MSG_EN_MASK 0x00000008L +#define PCIE_DOE_CNTL__DOE_GO_MASK 0x80000000L +//PCIE_DOE_STS +#define PCIE_DOE_STS__DOE_BUSY__SHIFT 0x0 +#define PCIE_DOE_STS__DOE_INTR_STS__SHIFT 0x1 +#define PCIE_DOE_STS__DOE_ERR__SHIFT 0x2 +#define PCIE_DOE_STS__DOE_ASYNC_MSG_STS__SHIFT 0x3 +#define PCIE_DOE_STS__DOE_AT_ATTENTION__SHIFT 0x4 +#define PCIE_DOE_STS__DOE_OBJ_RDY__SHIFT 0x1f +#define PCIE_DOE_STS__DOE_BUSY_MASK 0x00000001L +#define PCIE_DOE_STS__DOE_INTR_STS_MASK 0x00000002L +#define PCIE_DOE_STS__DOE_ERR_MASK 0x00000004L +#define PCIE_DOE_STS__DOE_ASYNC_MSG_STS_MASK 0x00000008L +#define PCIE_DOE_STS__DOE_AT_ATTENTION_MASK 0x00000010L +#define PCIE_DOE_STS__DOE_OBJ_RDY_MASK 0x80000000L +//PCIE_DOE_WMBOX +#define PCIE_DOE_WMBOX__DOE_WMBOX__SHIFT 0x0 +#define PCIE_DOE_WMBOX__DOE_WMBOX_MASK 0xFFFFFFFFL +//PCIE_DOE_RMBOX +#define PCIE_DOE_RMBOX__DOE_RMBOX__SHIFT 0x0 +#define PCIE_DOE_RMBOX__DOE_RMBOX_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__FUNCTION_ID__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__FUNCTION_ID_MASK 0xFF00L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH0_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH1_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH2_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH3_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH0_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH1_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH2_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH3_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH4_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH5_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH6_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH7_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH4_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH5_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH6_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH7_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH8_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH9_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH10_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH11_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH8_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH9_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH10_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH11_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH12_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH13_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH14_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH15_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH12_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH13_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH14_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH15_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH16_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH17_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH18_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH19_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH16_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH17_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH18_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH19_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgpciedecp +//BIF_CFG_DEV0_EPF0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_LINK_CAP_16GT +#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_LINK_CAP_32GT +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_AP_CAP +#define BIF_CFG_DEV0_EPF0_AP_CAP__COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_AP_CAP__SEL_EN_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_AP_CAP__COUNT_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_AP_CAP__SEL_EN_SUPPORTED_MASK 0x00000100L +//BIF_CFG_DEV0_EPF0_AP_CNTL +#define BIF_CFG_DEV0_EPF0_AP_CNTL__INX_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_AP_CNTL__NEGO_GLOBAL_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_AP_CNTL__INX_SEL_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_AP_CNTL__NEGO_GLOBAL_EN_MASK 0x00000100L +//BIF_CFG_DEV0_EPF0_AP_DATA1 +#define BIF_CFG_DEV0_EPF0_AP_DATA1__USAGE_INFOR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_AP_DATA1__DETAILS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_AP_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_AP_DATA1__USAGE_INFOR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_AP_DATA1__DETAILS_MASK 0x0000FFE0L +#define BIF_CFG_DEV0_EPF0_AP_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_AP_DATA2 +#define BIF_CFG_DEV0_EPF0_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_AP_DATA2__MODIFIED_TS_INFOR2_MASK 0x00FFFFFFL +//BIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK +#define BIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK__PCIE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK__OTHERS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK__PCIE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK__OTHERS_MASK 0xFFFFFFFEL +//BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_CAP +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_XT_SUPPORTED__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS_MASK 0x00001F00L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_MASK 0x0000E000L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_XT_SUPPORTED_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_IDE_CNTL +#define BIF_CFG_DEV0_EPF0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED_MASK 0x00000004L +//BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_rc_bifcfgdecp +//BIF_CFG_DEV0_RC0_VENDOR_ID +#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_DEVICE_ID +#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_COMMAND +#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_RC0_STATUS +#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_REVISION_ID +#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_RC0_PROG_INTERFACE +#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_SUB_CLASS +#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC0_BASE_CLASS +#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC0_CACHE_LINE +#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_LATENCY +#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_RC0_HEADER +#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_RC0_BIST +#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_RC0_BASE_ADDR_1 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_BASE_ADDR_2 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIF_CFG_DEV0_RC0_SECONDARY_STATUS +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PREF_BASE_UPPER +#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER +#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_CAP_PTR +#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_RC0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_RC0_INTERRUPT_LINE +#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_INTERRUPT_PIN +#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L +//BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIF_CFG_DEV0_RC0_PMI_CAP_LIST +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PMI_CAP +#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PCIE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_RC0_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_RC0_DEVICE_CAP +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +//BIF_CFG_DEV0_RC0_DEVICE_CNTL +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV0_RC0_DEVICE_STATUS +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_RC0_LINK_CAP +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_LINK_CNTL +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_RC0_LINK_STATUS +#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_RC0_SLOT_CAP +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIF_CFG_DEV0_RC0_SLOT_CNTL +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE_MASK 0x4000L +//BIF_CFG_DEV0_RC0_SLOT_STATUS +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIF_CFG_DEV0_RC0_ROOT_CNTL +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIF_CFG_DEV0_RC0_ROOT_CAP +#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIF_CFG_DEV0_RC0_ROOT_STATUS +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIF_CFG_DEV0_RC0_DEVICE_CAP2 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_RC0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_LINK_CAP2 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_LINK_CNTL2 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_RC0_LINK_STATUS2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_SLOT_CAP2 +#define BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK 0x00000001L +//BIF_CFG_DEV0_RC0_SLOT_CNTL2 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_SLOT_STATUS2 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_CAP_LIST +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_MSI_MSG_DATA +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_SSID_CAP_LIST +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_SSID_CAP +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_LINK_CAP_16GT +#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_LINK_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_LINK_STATUS_16GT +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_LINK_CAP_32GT +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_RC0_LINK_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_RC0_LINK_STATUS_32GT +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_AP_CAP +#define BIF_CFG_DEV0_RC0_AP_CAP__COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_AP_CAP__SEL_EN_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_AP_CAP__COUNT_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_AP_CAP__SEL_EN_SUPPORTED_MASK 0x00000100L +//BIF_CFG_DEV0_RC0_AP_CNTL +#define BIF_CFG_DEV0_RC0_AP_CNTL__INX_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_AP_CNTL__NEGO_GLOBAL_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_AP_CNTL__INX_SEL_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_AP_CNTL__NEGO_GLOBAL_EN_MASK 0x00000100L +//BIF_CFG_DEV0_RC0_AP_DATA1 +#define BIF_CFG_DEV0_RC0_AP_DATA1__USAGE_INFOR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_AP_DATA1__DETAILS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_AP_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_AP_DATA1__USAGE_INFOR_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_AP_DATA1__DETAILS_MASK 0x0000FFE0L +#define BIF_CFG_DEV0_RC0_AP_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_AP_DATA2 +#define BIF_CFG_DEV0_RC0_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_AP_DATA2__MODIFIED_TS_INFOR2_MASK 0x00FFFFFFL +//BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK +#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__PCIE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__OTHERS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__PCIE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__OTHERS_MASK 0xFFFFFFFEL +//BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS_MASK 0x00000180L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_RTR_DATA1 +#define BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_RC0_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_RTR_DATA2 +#define BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_CAP +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_XT_SUPPORTED__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS_MASK 0x00001F00L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_MASK 0x0000E000L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_XT_SUPPORTED_MASK 0x02000000L +//BIF_CFG_DEV0_RC0_IDE_CNTL +#define BIF_CFG_DEV0_RC0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED_MASK 0x00000004L +//BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_COMMAND +#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_0_STATUS +#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_LATENCY +#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_HEADER +#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_0_BIST +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PMI_CAP +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE_MASK 0x00010000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT_MASK 0x02L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE_MASK 0x0008L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__INTR_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_INTR_MSG_NUM__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_ATT_SUPPORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_ASYNC_SUPPORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__INTR_SUPPORT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_INTR_MSG_NUM_MASK 0x00000FFEL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_ATT_SUPPORT_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_ASYNC_SUPPORT_MASK 0x00002000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ABORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ATT_NOT_NEED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ASYNC_MSG_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_GO__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ABORT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ATT_NOT_NEED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ASYNC_MSG_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_GO_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_BUSY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_INTR_STS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_ASYNC_MSG_STS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_AT_ATTENTION__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_OBJ_RDY__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_BUSY_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_INTR_STS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_ERR_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_ASYNC_MSG_STS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_AT_ATTENTION_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_OBJ_RDY_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX__DOE_WMBOX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX__DOE_WMBOX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX__DOE_RMBOX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX__DOE_RMBOX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__FUNCTION_ID__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__FUNCTION_ID_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH0_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH1_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH2_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH3_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH0_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH1_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH2_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH3_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH4_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH5_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH6_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH7_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH4_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH5_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH6_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH7_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH8_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH9_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH10_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH11_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH8_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH9_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH10_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH11_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH12_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH13_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH14_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH15_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH12_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH13_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH14_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH15_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH16_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH17_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH18_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH19_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH16_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH17_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH18_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH19_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgpciedecp +//BIF_CFG_DEV0_EPF0_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_AP_CAP +#define BIF_CFG_DEV0_EPF0_0_AP_CAP__COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_AP_CAP__SEL_EN_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_AP_CAP__COUNT_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_AP_CAP__SEL_EN_SUPPORTED_MASK 0x00000100L +//BIF_CFG_DEV0_EPF0_0_AP_CNTL +#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__INX_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__NEGO_GLOBAL_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__INX_SEL_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__NEGO_GLOBAL_EN_MASK 0x00000100L +//BIF_CFG_DEV0_EPF0_0_AP_DATA1 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__USAGE_INFOR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__DETAILS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__USAGE_INFOR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__DETAILS_MASK 0x0000FFE0L +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_AP_DATA2 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA2__MODIFIED_TS_INFOR2_MASK 0x00FFFFFFL +//BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK +#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__PCIE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__OTHERS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__PCIE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__OTHERS_MASK 0xFFFFFFFEL +//BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_CAP +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_XT_SUPPORTED__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS_MASK 0x00001F00L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_MASK 0x0000E000L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_XT_SUPPORTED_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_0_IDE_CNTL +#define BIF_CFG_DEV0_EPF0_0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED_MASK 0x00000004L +//BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF0_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_HEADER +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF0_BIST +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF1_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_HEADER +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF1_BIST +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_COMMAND +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF2_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_LATENCY +#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_HEADER +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF2_BIST +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF2_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_COMMAND +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF3_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_LATENCY +#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_HEADER +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF3_BIST +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF3_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_COMMAND +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF4_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_LATENCY +#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_HEADER +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF4_BIST +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF4_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_COMMAND +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF5_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_LATENCY +#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_HEADER +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF5_BIST +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF5_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_COMMAND +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF6_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_LATENCY +#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_HEADER +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF6_BIST +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF6_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_COMMAND +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF7_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_LATENCY +#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_HEADER +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF7_BIST +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF7_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF0_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF0_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF0_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF1_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF1_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF1_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF2_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF2_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF2_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF3_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF3_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF3_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF4_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF4_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF4_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF5_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF5_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF5_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF6_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF6_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF6_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF7_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF7_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF7_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +//BIF_CFG_DEV0_EPF1_VENDOR_ID +#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_COMMAND +#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_STATUS +#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_REVISION_ID +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_SUB_CLASS +#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_BASE_CLASS +#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_CACHE_LINE +#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_LATENCY +#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_HEADER +#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF1_BIST +#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF1_CAP_PTR +#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_MIN_GRANT +#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PMI_CAP +#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//SBRN +#define SBRN__SBRN__SHIFT 0x0 +#define SBRN__SBRN_MASK 0xFFL +//FLADJ +#define FLADJ__FLADJ__SHIFT 0x0 +#define FLADJ__NFC__SHIFT 0x6 +#define FLADJ__FLADJ_MASK 0x3FL +#define FLADJ__NFC_MASK 0x40L +//BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PCIE_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_LINK_CAP +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_LINK_CNTL +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF1_LINK_STATUS +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MASK +#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_PENDING +#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_MSIX_PBA +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF1_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF1_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF1_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE_MASK 0x00010000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT_MASK 0x02L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE_MASK 0x0008L +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf1_vf0_bifcfgdecp +//BIF_CFG_DEV0_EPF1_VF0_VENDOR_ID +#define BIF_CFG_DEV0_EPF1_VF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_VF0_COMMAND +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_VF0_STATUS +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_VF0_REVISION_ID +#define BIF_CFG_DEV0_EPF1_VF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_VF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_SUB_CLASS +#define BIF_CFG_DEV0_EPF1_VF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_BASE_CLASS +#define BIF_CFG_DEV0_EPF1_VF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_CACHE_LINE +#define BIF_CFG_DEV0_EPF1_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_LATENCY +#define BIF_CFG_DEV0_EPF1_VF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_HEADER +#define BIF_CFG_DEV0_EPF1_VF0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF1_VF0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF1_VF0_BIST +#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF1_VF0_CAP_PTR +#define BIF_CFG_DEV0_EPF1_VF0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_MIN_GRANT +#define BIF_CFG_DEV0_EPF1_VF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_VF0_LINK_CAP +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_MASK +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING +#define BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_VF0_MSIX_PBA +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_VF0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbif0_nbif0_rcc_dev0_RCCPORTDEC +//RCC_DEV0_1_RCC_VDM_SUPPORT +#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_DEV0_1_RCC_BUS_CNTL +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_DEV0_1_RCC_DEV0_LINK_CNTL +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_DEV0_1_RCC_CMN_LINK_CNTL +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG__SHIFT 0x10 +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG_MASK 0x00FF0000L +//RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL +#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_DEV0_1_RCC_MH_ARB_CNTL +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x0000FFFEL +//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L + + +// addressBlock: nbif0_nbif0_rcc_ep_dev0_RCCPORTDEC +//RCC_EP_DEV0_1_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_1_EP_PCIE_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_1_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_1_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT 0x5 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK 0x00000020L +//RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_1_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_1_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK 0x00000010L +//RCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3 +#define RCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L + + +// addressBlock: nbif0_nbif0_rcc_dwn_dev0_RCCPORTDEC +//RCC_DWN_DEV0_1_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_1_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_1_DN_PCIE_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT 0x5 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK 0x00000020L +//RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_RCCPORTDEC +//RCC_DWNP_DEV0_1_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//RCC_DWNP_DEV0_1_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT 0x4 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK 0x00000010L +//RCC_DWNP_DEV0_1_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_pfc_amdgfx_RCCPFCDEC +//RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L +//RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_SENT_FLAG__SHIFT 0x9 +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_SENT_FLAG_MASK 0x00000200L +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L +//RCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL +#define RCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL__BURST_EN__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL__BURST_EN_MASK 0x00000007L +//RCC_PFC_AMDGFX_RCC_NFC +#define RCC_PFC_AMDGFX_RCC_NFC__NFC_PFV__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_NFC__NFC_PFV_MASK 0x00000001L + + +// addressBlock: nbif0_nbif0_rcc_shadow_reg_shadowdec +//SHADOW_COMMAND +#define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0 +#define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1 +#define SHADOW_COMMAND__IOEN_UP_MASK 0x0001L +#define SHADOW_COMMAND__MEMEN_UP_MASK 0x0002L +//SHADOW_BASE_ADDR_1 +#define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0 +#define SHADOW_BASE_ADDR_1__BAR1_UP_MASK 0xFFFFFFFFL +//SHADOW_BASE_ADDR_2 +#define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0 +#define SHADOW_BASE_ADDR_2__BAR2_UP_MASK 0xFFFFFFFFL +//SHADOW_SUB_BUS_NUMBER_LATENCY +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x8 +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x10 +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP_MASK 0x0000FF00L +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP_MASK 0x00FF0000L +//SHADOW_IO_BASE_LIMIT +#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x4 +#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0xc +#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP_MASK 0x00F0L +#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP_MASK 0xF000L +//SHADOW_MEM_BASE_LIMIT +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x4 +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x14 +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP_MASK 0x0000FFF0L +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP_MASK 0xFFF00000L +//SHADOW_PREF_BASE_LIMIT +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x4 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x14 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP_MASK 0x0000FFF0L +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP_MASK 0xFFF00000L +//SHADOW_PREF_BASE_UPPER +#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x0 +#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP_MASK 0xFFFFFFFFL +//SHADOW_PREF_LIMIT_UPPER +#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x0 +#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP_MASK 0xFFFFFFFFL +//SHADOW_IO_BASE_LIMIT_HI +#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x0 +#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x10 +#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP_MASK 0x0000FFFFL +#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP_MASK 0xFFFF0000L +//SHADOW_IRQ_BRIDGE_CNTL +#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x2 +#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x3 +#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x4 +#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x6 +#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP_MASK 0x0004L +#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP_MASK 0x0008L +#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP_MASK 0x0010L +#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP_MASK 0x0040L +//SUC_INDEX +#define SUC_INDEX__SUC_INDEX__SHIFT 0x0 +#define SUC_INDEX__SUC_INDEX_MASK 0xFFFFFFFFL +//SUC_DATA +#define SUC_DATA__SUC_DATA__SHIFT 0x0 +#define SUC_DATA__SUC_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_swus_SUMDEC +//SUM_INDEX +#define SUM_INDEX__SUM_INDEX__SHIFT 0x0 +#define SUM_INDEX__SUM_INDEX_MASK 0xFFFFFFFFL +//SUM_DATA +#define SUM_DATA__SUM_DATA__SHIFT 0x0 +#define SUM_DATA__SUM_DATA_MASK 0xFFFFFFFFL +//SUM_INDEX_HI +#define SUM_INDEX_HI__SUM_INDEX_HI__SHIFT 0x0 +#define SUM_INDEX_HI__SUM_INDEX_HI_MASK 0x0000FFFFL + + +// addressBlock: nbif0_nbif0_rcc_strap_rcc_strap_internal +//RCC_STRAP1_RCC_DEV0_PORT_STRAP0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0_MASK 0x03000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0_MASK 0x0C000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x02000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0_MASK 0x38000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0_MASK 0x00000E00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0_MASK 0x00002000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0_MASK 0xFFFFFFFFL +//RCC_STRAP1_RCC_DEV0_PORT_STRAP16 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0_MASK 0xFFFFFFFFL +//RCC_STRAP1_RCC_DEV0_PORT_STRAP17 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0_MASK 0x0000E000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0_MASK 0x02000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0_MASK 0x0000000FL +//RCC_DEV1_PORT_STRAP0 +//RCC_DEV1_PORT_STRAP1 +//RCC_DEV1_PORT_STRAP2 +//RCC_DEV1_PORT_STRAP3 +//RCC_DEV1_PORT_STRAP4 +//RCC_DEV1_PORT_STRAP5 +//RCC_DEV1_PORT_STRAP6 +//RCC_DEV1_PORT_STRAP7 +//RCC_DEV1_PORT_STRAP8 +//RCC_DEV1_PORT_STRAP9 +//RCC_DEV1_PORT_STRAP10 +//RCC_DEV1_PORT_STRAP11 +//RCC_DEV1_PORT_STRAP12 +//RCC_DEV1_PORT_STRAP13 +//RCC_DEV1_PORT_STRAP14 +//RCC_DEV1_PORT_STRAP15 +//RCC_DEV1_PORT_STRAP16 +//RCC_DEV2_PORT_STRAP0 +//RCC_DEV2_PORT_STRAP1 +//RCC_DEV2_PORT_STRAP2 +//RCC_DEV2_PORT_STRAP3 +//RCC_DEV2_PORT_STRAP4 +//RCC_DEV2_PORT_STRAP5 +//RCC_DEV2_PORT_STRAP6 +//RCC_DEV2_PORT_STRAP7 +//RCC_DEV2_PORT_STRAP8 +//RCC_DEV2_PORT_STRAP9 +//RCC_DEV2_PORT_STRAP10 +//RCC_DEV2_PORT_STRAP11 +//RCC_DEV2_PORT_STRAP12 +//RCC_DEV2_PORT_STRAP13 +//RCC_DEV2_PORT_STRAP14 +//RCC_DEV2_PORT_STRAP15 +//RCC_DEV2_PORT_STRAP16 +//RCC_STRAP1_RCC_BIF_STRAP0 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x14 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN__SHIFT 0x15 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GPUIOV_EN__SHIFT 0x16 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE__SHIFT 0x17 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00100000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN_MASK 0x00200000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GPUIOV_EN_MASK 0x00400000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE_MASK 0x00800000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP1 +#define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT__SHIFT 0x4 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT_MASK 0x00000010L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP2 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SPT__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWDS_SPT__SHIFT 0x2 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ARI_EN_UP__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SPT_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWDS_SPT_MASK 0x00000004L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ARI_EN_UP_MASK 0x02000000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP3 +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_BIF_STRAP4 +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_BIF_STRAP5 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP6 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL__SHIFT 0x3 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE__SHIFT 0x5 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6__SHIFT 0xf +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL_MASK 0x00000008L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE_MASK 0x00000020L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN_MASK 0x00007C00L +#define RCC_STRAP1_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6_MASK 0xFFFF8000L +//RCC_STRAP1_RCC_BIF_STRAP7 +#define RCC_STRAP1_RCC_BIF_STRAP7__STRAP_GEN6_DIS__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6__SHIFT 0x1a +#define RCC_STRAP1_RCC_BIF_STRAP7__STRAP_GEN6_DIS_MASK 0x02000000L +#define RCC_STRAP1_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6_MASK 0x04000000L +//RCC_STRAP1_RCC_BIF_STRAP8 +//RCC_STRAP1_RCC_BIF_STRAP9 +//RCC_STRAP1_RCC_BIF_STRAP10 +//RCC_STRAP1_RCC_BIF_STRAP11 +//RCC_STRAP1_RCC_BIF_STRAP12 +//RCC_STRAP1_RCC_BIF_STRAP13 +#define RCC_STRAP1_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER_MASK 0x00000FFFL +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP1 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP2 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP3 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0_MASK 0x02000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP4 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP5 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP9 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0_MASK 0x10000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0_MASK 0x000FF000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP19 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP22 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x0001F000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x003E0000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK 0x07C00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK 0xF8000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP23 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0_MASK 0xFFFFFFFFL +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP24 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0_MASK 0xFFFFFFFFL +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP1 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP2 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP3 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1_MASK 0x02000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP4 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP5 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP6 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1__SHIFT 0xa +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000200L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1_MASK 0x00000400L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK 0x02000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1_MASK 0x08000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP7 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP8 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1_MASK 0xC0000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP9 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1_MASK 0x10000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP10 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP11 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP12 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP13 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK 0x0000FFFFL +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP15 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1_MASK 0x00FFF000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1_MASK 0x01000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP16 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1_MASK 0x00FFF000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP17 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1_MASK 0x00001000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1_MASK 0x01FFE000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1_MASK 0x000FF000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP19 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP20 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP21 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP23 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP24 +//RCC_DEV0_EPF2_STRAP0 +//RCC_DEV0_EPF2_STRAP2 +//RCC_DEV0_EPF2_STRAP3 +//RCC_DEV0_EPF2_STRAP4 +//RCC_DEV0_EPF2_STRAP5 +//RCC_DEV0_EPF2_STRAP6 +//RCC_DEV0_EPF2_STRAP7 +//RCC_DEV0_EPF2_STRAP9 +//RCC_DEV0_EPF2_STRAP10 +//RCC_DEV0_EPF2_STRAP11 +//RCC_DEV0_EPF2_STRAP12 +//RCC_DEV0_EPF2_STRAP13 +//RCC_DEV0_EPF2_STRAP14 +//RCC_DEV0_EPF2_STRAP15 +//RCC_DEV0_EPF2_STRAP16 +//RCC_DEV0_EPF2_STRAP20 +//RCC_DEV0_EPF3_STRAP0 +//RCC_DEV0_EPF3_STRAP2 +//RCC_DEV0_EPF3_STRAP3 +//RCC_DEV0_EPF3_STRAP4 +//RCC_DEV0_EPF3_STRAP5 +//RCC_DEV0_EPF3_STRAP6 +//RCC_DEV0_EPF3_STRAP7 +//RCC_DEV0_EPF3_STRAP9 +//RCC_DEV0_EPF3_STRAP10 +//RCC_DEV0_EPF3_STRAP11 +//RCC_DEV0_EPF3_STRAP12 +//RCC_DEV0_EPF3_STRAP13 +//RCC_DEV0_EPF3_STRAP14 +//RCC_DEV0_EPF3_STRAP15 +//RCC_DEV0_EPF3_STRAP16 +//RCC_DEV0_EPF3_STRAP20 +//RCC_DEV0_EPF4_STRAP0 +//RCC_DEV0_EPF4_STRAP2 +//RCC_DEV0_EPF4_STRAP3 +//RCC_DEV0_EPF4_STRAP4 +//RCC_DEV0_EPF4_STRAP5 +//RCC_DEV0_EPF4_STRAP6 +//RCC_DEV0_EPF4_STRAP7 +//RCC_DEV0_EPF4_STRAP9 +//RCC_DEV0_EPF4_STRAP13 +//RCC_DEV0_EPF4_STRAP14 +//RCC_DEV0_EPF4_STRAP15 +//RCC_DEV0_EPF4_STRAP16 +//RCC_DEV0_EPF5_STRAP0 +//RCC_DEV0_EPF5_STRAP2 +//RCC_DEV0_EPF5_STRAP3 +//RCC_DEV0_EPF5_STRAP4 +//RCC_DEV0_EPF5_STRAP5 +//RCC_DEV0_EPF5_STRAP6 +//RCC_DEV0_EPF5_STRAP7 +//RCC_DEV0_EPF5_STRAP9 +//RCC_DEV0_EPF5_STRAP13 +//RCC_DEV0_EPF5_STRAP14 +//RCC_DEV0_EPF5_STRAP15 +//RCC_DEV0_EPF5_STRAP16 +//RCC_DEV0_EPF6_STRAP0 +//RCC_DEV0_EPF6_STRAP2 +//RCC_DEV0_EPF6_STRAP3 +//RCC_DEV0_EPF6_STRAP4 +//RCC_DEV0_EPF6_STRAP5 +//RCC_DEV0_EPF6_STRAP6 +//RCC_DEV0_EPF6_STRAP7 +//RCC_DEV0_EPF6_STRAP9 +//RCC_DEV0_EPF6_STRAP13 +//RCC_DEV0_EPF6_STRAP14 +//RCC_DEV0_EPF6_STRAP15 +//RCC_DEV0_EPF6_STRAP16 +//RCC_DEV0_EPF7_STRAP0 +//RCC_DEV0_EPF7_STRAP2 +//RCC_DEV0_EPF7_STRAP3 +//RCC_DEV0_EPF7_STRAP4 +//RCC_DEV0_EPF7_STRAP5 +//RCC_DEV0_EPF7_STRAP6 +//RCC_DEV0_EPF7_STRAP9 +//RCC_DEV0_EPF7_STRAP13 +//RCC_DEV0_EPF7_STRAP14 +//RCC_DEV0_EPF7_STRAP15 +//RCC_DEV0_EPF7_STRAP16 +//RCC_DEV1_EPF0_STRAP0 +//RCC_DEV1_EPF0_STRAP2 +//RCC_DEV1_EPF0_STRAP3 +//RCC_DEV1_EPF0_STRAP4 +//RCC_DEV1_EPF0_STRAP5 +//RCC_DEV1_EPF0_STRAP6 +//RCC_DEV1_EPF0_STRAP9 +//RCC_DEV1_EPF0_STRAP13 +//RCC_DEV1_EPF0_STRAP14 +//RCC_DEV1_EPF0_STRAP15 +//RCC_DEV1_EPF0_STRAP16 +//RCC_DEV1_EPF1_STRAP0 +//RCC_DEV1_EPF1_STRAP1 +//RCC_DEV1_EPF1_STRAP2 +//RCC_DEV1_EPF1_STRAP3 +//RCC_DEV1_EPF1_STRAP4 +//RCC_DEV1_EPF1_STRAP5 +//RCC_DEV1_EPF1_STRAP6 +//RCC_DEV1_EPF1_STRAP7 +//RCC_DEV1_EPF1_STRAP8 +//RCC_DEV1_EPF1_STRAP9 +//RCC_DEV1_EPF1_STRAP13 +//RCC_DEV1_EPF1_STRAP14 +//RCC_DEV1_EPF1_STRAP15 +//RCC_DEV1_EPF1_STRAP16 +//RCC_DEV1_EPF1_STRAP17 +//RCC_DEV1_EPF1_STRAP18 +//RCC_DEV1_EPF1_STRAP19 +//RCC_DEV1_EPF1_STRAP20 +//RCC_DEV1_EPF1_STRAP21 +//RCC_DEV1_EPF2_STRAP0 +//RCC_DEV1_EPF2_STRAP1 +//RCC_DEV1_EPF2_STRAP2 +//RCC_DEV1_EPF2_STRAP3 +//RCC_DEV1_EPF2_STRAP4 +//RCC_DEV1_EPF2_STRAP5 +//RCC_DEV1_EPF2_STRAP6 +//RCC_DEV1_EPF2_STRAP7 +//RCC_DEV1_EPF2_STRAP8 +//RCC_DEV1_EPF2_STRAP9 +//RCC_DEV1_EPF2_STRAP13 +//RCC_DEV1_EPF2_STRAP14 +//RCC_DEV1_EPF2_STRAP15 +//RCC_DEV1_EPF2_STRAP16 +//RCC_DEV1_EPF2_STRAP17 +//RCC_DEV1_EPF2_STRAP18 +//RCC_DEV1_EPF2_STRAP19 +//RCC_DEV1_EPF2_STRAP20 +//RCC_DEV1_EPF2_STRAP21 +//RCC_DEV1_EPF3_STRAP0 +//RCC_DEV1_EPF3_STRAP2 +//RCC_DEV1_EPF3_STRAP3 +//RCC_DEV1_EPF3_STRAP4 +//RCC_DEV1_EPF3_STRAP5 +//RCC_DEV1_EPF3_STRAP6 +//RCC_DEV1_EPF3_STRAP7 +//RCC_DEV1_EPF3_STRAP13 +//RCC_DEV1_EPF3_STRAP14 +//RCC_DEV1_EPF3_STRAP15 +//RCC_DEV1_EPF3_STRAP16 +//RCC_DEV1_EPF4_STRAP6 +//RCC_DEV1_EPF5_STRAP6 +//RCC_DEV1_EPF6_STRAP6 +//RCC_DEV2_EPF0_STRAP0 +//RCC_DEV2_EPF0_STRAP2 +//RCC_DEV2_EPF0_STRAP3 +//RCC_DEV2_EPF0_STRAP4 +//RCC_DEV2_EPF0_STRAP5 +//RCC_DEV2_EPF0_STRAP6 +//RCC_DEV2_EPF0_STRAP7 +//RCC_DEV2_EPF0_STRAP13 +//RCC_DEV2_EPF0_STRAP14 +//RCC_DEV2_EPF0_STRAP15 +//RCC_DEV2_EPF0_STRAP16 +//RCC_DEV2_EPF0_STRAP18 +//RCC_DEV2_EPF0_STRAP25 +//RCC_DEV2_EPF0_STRAP26 +//RCC_DEV2_EPF1_STRAP0 +//RCC_DEV2_EPF1_STRAP2 +//RCC_DEV2_EPF1_STRAP3 +//RCC_DEV2_EPF1_STRAP4 +//RCC_DEV2_EPF1_STRAP5 +//RCC_DEV2_EPF1_STRAP6 +//RCC_DEV2_EPF1_STRAP7 +//RCC_DEV2_EPF1_STRAP13 +//RCC_DEV2_EPF1_STRAP14 +//RCC_DEV2_EPF1_STRAP15 +//RCC_DEV2_EPF1_STRAP16 +//RCC_DEV2_EPF2_STRAP0 +//RCC_DEV2_EPF2_STRAP2 +//RCC_DEV2_EPF2_STRAP3 +//RCC_DEV2_EPF2_STRAP4 +//RCC_DEV2_EPF2_STRAP5 +//RCC_DEV2_EPF2_STRAP6 +//RCC_DEV2_EPF2_STRAP7 +//RCC_DEV2_EPF2_STRAP13 +//RCC_DEV2_EPF2_STRAP14 +//RCC_DEV2_EPF2_STRAP15 +//RCC_DEV2_EPF2_STRAP16 +//RCC_DEV2_EPF3_STRAP0 +//RCC_DEV2_EPF3_STRAP2 +//RCC_DEV2_EPF3_STRAP3 +//RCC_DEV2_EPF3_STRAP4 +//RCC_DEV2_EPF3_STRAP5 +//RCC_DEV2_EPF3_STRAP6 +//RCC_DEV2_EPF3_STRAP7 +//RCC_DEV2_EPF3_STRAP13 +//RCC_DEV2_EPF3_STRAP14 +//RCC_DEV2_EPF3_STRAP15 +//RCC_DEV2_EPF3_STRAP16 +//RCC_DEV2_EPF4_STRAP0 +//RCC_DEV2_EPF4_STRAP2 +//RCC_DEV2_EPF4_STRAP3 +//RCC_DEV2_EPF4_STRAP4 +//RCC_DEV2_EPF4_STRAP5 +//RCC_DEV2_EPF4_STRAP6 +//RCC_DEV2_EPF4_STRAP7 +//RCC_DEV2_EPF4_STRAP13 +//RCC_DEV2_EPF4_STRAP14 +//RCC_DEV2_EPF4_STRAP15 +//RCC_DEV2_EPF4_STRAP16 +//RCC_DEV2_EPF5_STRAP0 +//RCC_DEV2_EPF5_STRAP2 +//RCC_DEV2_EPF5_STRAP3 +//RCC_DEV2_EPF5_STRAP4 +//RCC_DEV2_EPF5_STRAP5 +//RCC_DEV2_EPF5_STRAP6 +//RCC_DEV2_EPF5_STRAP7 +//RCC_DEV2_EPF5_STRAP13 +//RCC_DEV2_EPF5_STRAP14 +//RCC_DEV2_EPF5_STRAP15 +//RCC_DEV2_EPF5_STRAP16 +//RCC_DEV2_EPF6_STRAP0 +//RCC_DEV2_EPF6_STRAP2 +//RCC_DEV2_EPF6_STRAP3 +//RCC_DEV2_EPF6_STRAP4 +//RCC_DEV2_EPF6_STRAP5 +//RCC_DEV2_EPF6_STRAP6 +//RCC_DEV2_EPF6_STRAP7 +//RCC_DEV2_EPF6_STRAP13 +//RCC_DEV2_EPF6_STRAP14 +//RCC_DEV2_EPF6_STRAP15 +//RCC_DEV2_EPF6_STRAP16 + + +// addressBlock: nbif0_nbif0_bif_rst_bif_rst_regblk +//HARD_RST_CTRL +#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 +#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 +#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 +#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 +#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 +#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 +#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 +#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 +#define HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x9 +#define HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0xa +#define HARD_RST_CTRL__STRAP_RST_EN__SHIFT 0x17 +#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c +#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d +#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e +#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f +#define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L +#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L +#define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L +#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L +#define HARD_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L +#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L +#define HARD_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L +#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L +#define HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000200L +#define HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000400L +#define HARD_RST_CTRL__STRAP_RST_EN_MASK 0x00800000L +#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L +#define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L +#define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L +#define HARD_RST_CTRL__CORE_RST_EN_MASK 0x80000000L +//SELF_SOFT_RST +#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0 +#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1 +#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2 +#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3 +#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4 +#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5 +#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6 +#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7 +#define SELF_SOFT_RST__PCIE_NBIF_HST_SDP_PORT_RST__SHIFT 0x18 +#define SELF_SOFT_RST__SST_HST_SDP_PORT_RST__SHIFT 0x19 +#define SELF_SOFT_RST__NBIF_PCIE_DMA_SDP_PORT_RST__SHIFT 0x1a +#define SELF_SOFT_RST__SST_DMA_SDP_PORT_RST__SHIFT 0x1b +#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c +#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d +#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e +#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f +#define SELF_SOFT_RST__DSPT0_CFG_RST_MASK 0x00000001L +#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK 0x00000002L +#define SELF_SOFT_RST__DSPT0_PRV_RST_MASK 0x00000004L +#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK 0x00000008L +#define SELF_SOFT_RST__EP0_CFG_RST_MASK 0x00000010L +#define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK 0x00000020L +#define SELF_SOFT_RST__EP0_PRV_RST_MASK 0x00000040L +#define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK 0x00000080L +#define SELF_SOFT_RST__PCIE_NBIF_HST_SDP_PORT_RST_MASK 0x01000000L +#define SELF_SOFT_RST__SST_HST_SDP_PORT_RST_MASK 0x02000000L +#define SELF_SOFT_RST__NBIF_PCIE_DMA_SDP_PORT_RST_MASK 0x04000000L +#define SELF_SOFT_RST__SST_DMA_SDP_PORT_RST_MASK 0x08000000L +#define SELF_SOFT_RST__SWUS_SHADOW_RST_MASK 0x10000000L +#define SELF_SOFT_RST__CORE_STICKY_RST_MASK 0x20000000L +#define SELF_SOFT_RST__RELOAD_STRAP_MASK 0x40000000L +#define SELF_SOFT_RST__CORE_RST_MASK 0x80000000L +//BIF_GFX_DRV_VPU_RST +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT 0x0 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT 0x3 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT 0x5 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT 0x7 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK 0x00000001L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK 0x00000002L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK 0x00000004L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK 0x00000008L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK 0x00000010L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK 0x00000020L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK 0x00000040L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK 0x00000080L +//BIF_RST_MISC_CTRL +#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0 +#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2 +#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4 +#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5 +#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6 +#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8 +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9 +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf +#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11 +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17 +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18 +#define BIF_RST_MISC_CTRL__HARD_RST_CTRL_SWUS_SHADOW_PRV_RST_EN__SHIFT 0x1a +#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK 0x00000001L +#define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK 0x0000000CL +#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK 0x00000010L +#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK 0x00000020L +#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK 0x00000040L +#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK 0x00000100L +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK 0x00000200L +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK 0x00001C00L +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK 0x00006000L +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK 0x00018000L +#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x000E0000L +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK 0x00800000L +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK 0x03000000L +#define BIF_RST_MISC_CTRL__HARD_RST_CTRL_SWUS_SHADOW_PRV_RST_EN_MASK 0x04000000L +//BIF_RST_MISC_CTRL2 +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT__SHIFT 0x0 +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT__SHIFT 0x1 +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT__SHIFT 0x2 +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT__SHIFT 0xf +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10 +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11 +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12 +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS__SHIFT 0x1e +#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT_MASK 0x00000001L +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT_MASK 0x00000002L +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT_MASK 0x00000004L +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_MASK 0x00008000L +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK 0x00010000L +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK 0x00020000L +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK 0x00040000L +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS_MASK 0x40000000L +#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK 0x80000000L +//BIF_RST_MISC_CTRL3 +#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0 +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4 +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6 +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7 +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd +#define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK 0x0000000FL +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK 0x00000030L +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK 0x00000040L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK 0x00000380L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK 0x00001C00L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK 0x0000E000L +//DEV0_PF0_FLR_RST_CTRL +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_CFG_EN__SHIFT 0x5 +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_CFG_STICKY_EN__SHIFT 0x6 +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_PRV_EN__SHIFT 0x7 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_CFG_EN__SHIFT 0xd +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_CFG_STICKY_EN__SHIFT 0xe +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_PRV_EN__SHIFT 0xf +#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10 +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT 0x1f +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_CFG_EN_MASK 0x00000020L +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_CFG_STICKY_EN_MASK 0x00000040L +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_PRV_EN_MASK 0x00000080L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK 0x00000100L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK 0x00000200L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK 0x00000400L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK 0x00000800L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK 0x00001000L +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_CFG_EN_MASK 0x00002000L +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_CFG_STICKY_EN_MASK 0x00004000L +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_PRV_EN_MASK 0x00008000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK 0x80000000L +//DEV0_PF1_FLR_RST_CTRL +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_CFG_EN__SHIFT 0x5 +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_CFG_STICKY_EN__SHIFT 0x6 +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_PRV_EN__SHIFT 0x7 +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_CFG_EN__SHIFT 0xd +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_CFG_STICKY_EN__SHIFT 0xe +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_PRV_EN__SHIFT 0xf +#define DEV0_PF1_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10 +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_CFG_EN_MASK 0x00000020L +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_CFG_STICKY_EN_MASK 0x00000040L +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_PRV_EN_MASK 0x00000080L +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_CFG_EN_MASK 0x00002000L +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_CFG_STICKY_EN_MASK 0x00004000L +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_PRV_EN_MASK 0x00008000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//BIF_INST_RESET_INTR_STS +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0 +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4 +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK 0x00000001L +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000002L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK 0x00000004L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK 0x00000008L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK 0x00000010L +//BIF_PF_FLR_INTR_STS +#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0 +#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1 +#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK 0x00000001L +#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK 0x00000002L +//BIF_D3HOTD0_INTR_STS +#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK 0x00000001L +#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK 0x00000002L +//BIF_POWER_INTR_STS +#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0 +#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10 +#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK 0x00000001L +#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK 0x00010000L +//BIF_PF_DSTATE_INTR_STS +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK 0x00000001L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK 0x00000002L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK 0x00000004L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK 0x00000008L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK 0x00000010L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK 0x00000020L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK 0x00000040L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK 0x00000080L +//SELF_SOFT_RST_2 +#define SELF_SOFT_RST_2__DSPT3_CFG_RST__SHIFT 0x0 +#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST__SHIFT 0x1 +#define SELF_SOFT_RST_2__DSPT3_PRV_RST__SHIFT 0x2 +#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST__SHIFT 0x3 +#define SELF_SOFT_RST_2__EP3_CFG_RST__SHIFT 0x4 +#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST__SHIFT 0x5 +#define SELF_SOFT_RST_2__EP3_PRV_RST__SHIFT 0x6 +#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST__SHIFT 0x7 +#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT 0x18 +#define SELF_SOFT_RST_2__STRAP_RST__SHIFT 0x19 +#define SELF_SOFT_RST_2__SWUS_SHADOW_PRV_RST__SHIFT 0x1a +#define SELF_SOFT_RST_2__DSPT3_CFG_RST_MASK 0x00000001L +#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST_MASK 0x00000002L +#define SELF_SOFT_RST_2__DSPT3_PRV_RST_MASK 0x00000004L +#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST_MASK 0x00000008L +#define SELF_SOFT_RST_2__EP3_CFG_RST_MASK 0x00000010L +#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST_MASK 0x00000020L +#define SELF_SOFT_RST_2__EP3_PRV_RST_MASK 0x00000040L +#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST_MASK 0x00000080L +#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK 0x01000000L +#define SELF_SOFT_RST_2__STRAP_RST_MASK 0x02000000L +#define SELF_SOFT_RST_2__SWUS_SHADOW_PRV_RST_MASK 0x04000000L +//SION_SDP_PORT_RST +#define SION_SDP_PORT_RST__SYSHUB_NBIFSION_SDP_PORT_RST__SHIFT 0x0 +#define SION_SDP_PORT_RST__NBIFSION_SYSHUB_SDP_PORT_RST__SHIFT 0x1 +#define SION_SDP_PORT_RST__BIF_NBIFSION_SDP_PORT_RST__SHIFT 0x2 +#define SION_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT 0x4 +#define SION_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST__SHIFT 0x5 +#define SION_SDP_PORT_RST__MP4SDP_SDP_PORT_RST__SHIFT 0x6 +#define SION_SDP_PORT_RST__NBIFSOIN_ATHUB_SDP_PORT_RST__SHIFT 0x7 +#define SION_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT 0x8 +#define SION_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT 0x9 +#define SION_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT 0xc +#define SION_SDP_PORT_RST__SION_AON_RST__SHIFT 0x18 +#define SION_SDP_PORT_RST__SYSHUB_NBIFSION_SDP_PORT_RST_MASK 0x00000001L +#define SION_SDP_PORT_RST__NBIFSION_SYSHUB_SDP_PORT_RST_MASK 0x00000002L +#define SION_SDP_PORT_RST__BIF_NBIFSION_SDP_PORT_RST_MASK 0x00000004L +#define SION_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK 0x00000010L +#define SION_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST_MASK 0x00000020L +#define SION_SDP_PORT_RST__MP4SDP_SDP_PORT_RST_MASK 0x00000040L +#define SION_SDP_PORT_RST__NBIFSOIN_ATHUB_SDP_PORT_RST_MASK 0x00000080L +#define SION_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK 0x00000100L +#define SION_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK 0x00000200L +#define SION_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK 0x00001000L +#define SION_SDP_PORT_RST__SION_AON_RST_MASK 0x01000000L +//BIF_INST_RESET_INTR_MASK +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0 +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4 +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK 0x00000001L +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000002L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK 0x00000004L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK 0x00000008L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK 0x00000010L +//BIF_PF_FLR_INTR_MASK +#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK 0x00000001L +#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK 0x00000002L +//BIF_D3HOTD0_INTR_MASK +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK 0x00000001L +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK 0x00000002L +//BIF_POWER_INTR_MASK +#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0 +#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10 +#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK 0x00000001L +#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK 0x00010000L +//BIF_PF_DSTATE_INTR_MASK +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK 0x00000001L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK 0x00000002L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK 0x00000004L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK 0x00000008L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK 0x00000010L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK 0x00000020L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK 0x00000040L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK 0x00000080L +//BIF_DEV0_PF0_VF_FLR_INTR_MASK +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF0_FLR_INTR_MASK__SHIFT 0x0 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF1_FLR_INTR_MASK__SHIFT 0x1 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF2_FLR_INTR_MASK__SHIFT 0x2 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF3_FLR_INTR_MASK__SHIFT 0x3 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF4_FLR_INTR_MASK__SHIFT 0x4 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF5_FLR_INTR_MASK__SHIFT 0x5 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF6_FLR_INTR_MASK__SHIFT 0x6 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF7_FLR_INTR_MASK__SHIFT 0x7 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_SOFTPF_FLR_INTR_MASK__SHIFT 0x1f +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF0_FLR_INTR_MASK_MASK 0x00000001L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF1_FLR_INTR_MASK_MASK 0x00000002L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF2_FLR_INTR_MASK_MASK 0x00000004L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF3_FLR_INTR_MASK_MASK 0x00000008L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF4_FLR_INTR_MASK_MASK 0x00000010L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF5_FLR_INTR_MASK_MASK 0x00000020L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF6_FLR_INTR_MASK_MASK 0x00000040L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF7_FLR_INTR_MASK_MASK 0x00000080L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_SOFTPF_FLR_INTR_MASK_MASK 0x80000000L +//BIF_DEV0_PF1_VF_FLR_INTR_MASK +#define BIF_DEV0_PF1_VF_FLR_INTR_MASK__DEV0_PF1_VF0_FLR_INTR_MASK__SHIFT 0x0 +#define BIF_DEV0_PF1_VF_FLR_INTR_MASK__DEV0_PF1_VF0_FLR_INTR_MASK_MASK 0x00000001L +//BIF_PF_FLR_RST +#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 +#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 +#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L +#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L +//BIF_PF_FLR_PROTECT +#define BIF_PF_FLR_PROTECT__DEV0_PF0_FLR_PROTECT__SHIFT 0x0 +#define BIF_PF_FLR_PROTECT__DEV0_PF1_FLR_PROTECT__SHIFT 0x1 +#define BIF_PF_FLR_PROTECT__DEV0_PF2_FLR_PROTECT__SHIFT 0x2 +#define BIF_PF_FLR_PROTECT__DEV0_PF3_FLR_PROTECT__SHIFT 0x3 +#define BIF_PF_FLR_PROTECT__DEV0_PF4_FLR_PROTECT__SHIFT 0x4 +#define BIF_PF_FLR_PROTECT__DEV0_PF5_FLR_PROTECT__SHIFT 0x5 +#define BIF_PF_FLR_PROTECT__DEV0_PF6_FLR_PROTECT__SHIFT 0x6 +#define BIF_PF_FLR_PROTECT__DEV0_PF7_FLR_PROTECT__SHIFT 0x7 +#define BIF_PF_FLR_PROTECT__DEV0_PF0_TRANS_IDLE__SHIFT 0x10 +#define BIF_PF_FLR_PROTECT__DEV0_PF1_TRANS_IDLE__SHIFT 0x11 +#define BIF_PF_FLR_PROTECT__DEV0_PF2_TRANS_IDLE__SHIFT 0x12 +#define BIF_PF_FLR_PROTECT__DEV0_PF3_TRANS_IDLE__SHIFT 0x13 +#define BIF_PF_FLR_PROTECT__DEV0_PF4_TRANS_IDLE__SHIFT 0x14 +#define BIF_PF_FLR_PROTECT__DEV0_PF5_TRANS_IDLE__SHIFT 0x15 +#define BIF_PF_FLR_PROTECT__DEV0_PF6_TRANS_IDLE__SHIFT 0x16 +#define BIF_PF_FLR_PROTECT__DEV0_PF7_TRANS_IDLE__SHIFT 0x17 +#define BIF_PF_FLR_PROTECT__DEV0_PF0_FLR_PROTECT_MASK 0x00000001L +#define BIF_PF_FLR_PROTECT__DEV0_PF1_FLR_PROTECT_MASK 0x00000002L +#define BIF_PF_FLR_PROTECT__DEV0_PF2_FLR_PROTECT_MASK 0x00000004L +#define BIF_PF_FLR_PROTECT__DEV0_PF3_FLR_PROTECT_MASK 0x00000008L +#define BIF_PF_FLR_PROTECT__DEV0_PF4_FLR_PROTECT_MASK 0x00000010L +#define BIF_PF_FLR_PROTECT__DEV0_PF5_FLR_PROTECT_MASK 0x00000020L +#define BIF_PF_FLR_PROTECT__DEV0_PF6_FLR_PROTECT_MASK 0x00000040L +#define BIF_PF_FLR_PROTECT__DEV0_PF7_FLR_PROTECT_MASK 0x00000080L +#define BIF_PF_FLR_PROTECT__DEV0_PF0_TRANS_IDLE_MASK 0x00010000L +#define BIF_PF_FLR_PROTECT__DEV0_PF1_TRANS_IDLE_MASK 0x00020000L +#define BIF_PF_FLR_PROTECT__DEV0_PF2_TRANS_IDLE_MASK 0x00040000L +#define BIF_PF_FLR_PROTECT__DEV0_PF3_TRANS_IDLE_MASK 0x00080000L +#define BIF_PF_FLR_PROTECT__DEV0_PF4_TRANS_IDLE_MASK 0x00100000L +#define BIF_PF_FLR_PROTECT__DEV0_PF5_TRANS_IDLE_MASK 0x00200000L +#define BIF_PF_FLR_PROTECT__DEV0_PF6_TRANS_IDLE_MASK 0x00400000L +#define BIF_PF_FLR_PROTECT__DEV0_PF7_TRANS_IDLE_MASK 0x00800000L +//BIF_PF_FLR_PROTECT3 +#define BIF_PF_FLR_PROTECT3__DEV0_PF0_VF_FLR_CTRL__SHIFT 0x0 +#define BIF_PF_FLR_PROTECT3__DEV0_PF1_VF_FLR_CTRL__SHIFT 0x1 +#define BIF_PF_FLR_PROTECT3__DEV0_PF0_VF_FLR_CTRL_MASK 0x00000001L +#define BIF_PF_FLR_PROTECT3__DEV0_PF1_VF_FLR_CTRL_MASK 0x00000002L +//BIF_DEV0_PF0_DSTATE_VALUE +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF1_DSTATE_VALUE +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L +//GFX_RST_CNTL_IND0 +#define GFX_RST_CNTL_IND0__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND0__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND0__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND0__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_SOFT_PF +#define GFX_RST_CNTL_SOFT_PF__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_SOFT_PF__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_SOFT_PF__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_SOFT_PF__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND1 +#define GFX_RST_CNTL_IND1__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND1__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND1__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND1__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND2 +#define GFX_RST_CNTL_IND2__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND2__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND2__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND2__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND3 +#define GFX_RST_CNTL_IND3__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND3__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND3__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND3__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND4 +#define GFX_RST_CNTL_IND4__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND4__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND4__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND4__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND5 +#define GFX_RST_CNTL_IND5__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND5__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND5__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND5__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND6 +#define GFX_RST_CNTL_IND6__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND6__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND6__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND6__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND7 +#define GFX_RST_CNTL_IND7__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND7__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND7__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND7__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND8 +#define GFX_RST_CNTL_IND8__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND8__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND8__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND8__SCRATCH_REG_MASK 0xFFFFFFFEL +//DEV0_PF0_D3HOTD0_RST_CTRL +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV0_PF1_D3HOTD0_RST_CTRL +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//BIF_DEV0_PF0_VF_FLR_PROTECT +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF0_FLR_PROTECT__SHIFT 0x0 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF1_FLR_PROTECT__SHIFT 0x1 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF2_FLR_PROTECT__SHIFT 0x2 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF3_FLR_PROTECT__SHIFT 0x3 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF4_FLR_PROTECT__SHIFT 0x4 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF5_FLR_PROTECT__SHIFT 0x5 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF6_FLR_PROTECT__SHIFT 0x6 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF7_FLR_PROTECT__SHIFT 0x7 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_SOFTPF_FLR_PROTECT__SHIFT 0x1f +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF0_FLR_PROTECT_MASK 0x00000001L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF1_FLR_PROTECT_MASK 0x00000002L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF2_FLR_PROTECT_MASK 0x00000004L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF3_FLR_PROTECT_MASK 0x00000008L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF4_FLR_PROTECT_MASK 0x00000010L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF5_FLR_PROTECT_MASK 0x00000020L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF6_FLR_PROTECT_MASK 0x00000040L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF7_FLR_PROTECT_MASK 0x00000080L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_SOFTPF_FLR_PROTECT_MASK 0x80000000L +//BIF_DEV0_PF1_VF_FLR_PROTECT +#define BIF_DEV0_PF1_VF_FLR_PROTECT__DEV0_PF1_VF0_FLR_PROTECT__SHIFT 0x0 +#define BIF_DEV0_PF1_VF_FLR_PROTECT__DEV0_PF1_VF0_FLR_PROTECT_MASK 0x00000001L +//BIF_SRIOVEN_SET_INTR_STS +#define BIF_SRIOVEN_SET_INTR_STS__DEV0_PF0_SRIOVEN_SET_INTR_STS__SHIFT 0x0 +#define BIF_SRIOVEN_SET_INTR_STS__DEV0_PF1_SRIOVEN_SET_INTR_STS__SHIFT 0x1 +#define BIF_SRIOVEN_SET_INTR_STS__DEV0_PF0_SRIOVEN_SET_INTR_STS_MASK 0x00000001L +#define BIF_SRIOVEN_SET_INTR_STS__DEV0_PF1_SRIOVEN_SET_INTR_STS_MASK 0x00000002L +//BIF_SRIOVEN_CLR_INTR_STS +#define BIF_SRIOVEN_CLR_INTR_STS__DEV0_PF0_SRIOVEN_CLR_INTR_STS__SHIFT 0x0 +#define BIF_SRIOVEN_CLR_INTR_STS__DEV0_PF1_SRIOVEN_CLR_INTR_STS__SHIFT 0x1 +#define BIF_SRIOVEN_CLR_INTR_STS__DEV0_PF0_SRIOVEN_CLR_INTR_STS_MASK 0x00000001L +#define BIF_SRIOVEN_CLR_INTR_STS__DEV0_PF1_SRIOVEN_CLR_INTR_STS_MASK 0x00000002L +//BIF_SRIOVEN_SET_INTR_MASK +#define BIF_SRIOVEN_SET_INTR_MASK__DEV0_PF0_SRIOVEN_SET_INTR_MASK__SHIFT 0x0 +#define BIF_SRIOVEN_SET_INTR_MASK__DEV0_PF1_SRIOVEN_SET_INTR_MASK__SHIFT 0x1 +#define BIF_SRIOVEN_SET_INTR_MASK__DEV0_PF0_SRIOVEN_SET_INTR_MASK_MASK 0x00000001L +#define BIF_SRIOVEN_SET_INTR_MASK__DEV0_PF1_SRIOVEN_SET_INTR_MASK_MASK 0x00000002L +//BIF_SRIOVEN_CLR_INTR_MASK +#define BIF_SRIOVEN_CLR_INTR_MASK__DEV0_PF0_SRIOVEN_CLR_INTR_MASK__SHIFT 0x0 +#define BIF_SRIOVEN_CLR_INTR_MASK__DEV0_PF1_SRIOVEN_CLR_INTR_MASK__SHIFT 0x1 +#define BIF_SRIOVEN_CLR_INTR_MASK__DEV0_PF0_SRIOVEN_CLR_INTR_MASK_MASK 0x00000001L +#define BIF_SRIOVEN_CLR_INTR_MASK__DEV0_PF1_SRIOVEN_CLR_INTR_MASK_MASK 0x00000002L +//BIF_PORT0_DSTATE_VALUE +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF0_RST_VF_FLR_IDLE +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF0_TRANS_IDLE__SHIFT 0x0 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF1_TRANS_IDLE__SHIFT 0x1 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF2_TRANS_IDLE__SHIFT 0x2 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF3_TRANS_IDLE__SHIFT 0x3 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF4_TRANS_IDLE__SHIFT 0x4 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF5_TRANS_IDLE__SHIFT 0x5 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF6_TRANS_IDLE__SHIFT 0x6 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF7_TRANS_IDLE__SHIFT 0x7 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__SOFTPF_TRANS_IDLE__SHIFT 0x1f +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF0_TRANS_IDLE_MASK 0x00000001L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF1_TRANS_IDLE_MASK 0x00000002L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF2_TRANS_IDLE_MASK 0x00000004L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF3_TRANS_IDLE_MASK 0x00000008L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF4_TRANS_IDLE_MASK 0x00000010L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF5_TRANS_IDLE_MASK 0x00000020L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF6_TRANS_IDLE_MASK 0x00000040L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF7_TRANS_IDLE_MASK 0x00000080L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__SOFTPF_TRANS_IDLE_MASK 0x80000000L +//BIF_DEV0_PF1_RST_VF_FLR_IDLE +#define BIF_DEV0_PF1_RST_VF_FLR_IDLE__DEV0_PF1_VF0_TRANS_IDLE__SHIFT 0x0 +#define BIF_DEV0_PF1_RST_VF_FLR_IDLE__DEV0_PF1_VF0_TRANS_IDLE_MASK 0x00000001L +//BIF_DEV0_PF0_VF_FLR_INTR_STS +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF0_FLR_INTR_STS__SHIFT 0x0 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF1_FLR_INTR_STS__SHIFT 0x1 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF2_FLR_INTR_STS__SHIFT 0x2 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF3_FLR_INTR_STS__SHIFT 0x3 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF4_FLR_INTR_STS__SHIFT 0x4 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF5_FLR_INTR_STS__SHIFT 0x5 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF6_FLR_INTR_STS__SHIFT 0x6 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF7_FLR_INTR_STS__SHIFT 0x7 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_SOFTPF_FLR_INTR_STS__SHIFT 0x1f +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF0_FLR_INTR_STS_MASK 0x00000001L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF1_FLR_INTR_STS_MASK 0x00000002L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF2_FLR_INTR_STS_MASK 0x00000004L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF3_FLR_INTR_STS_MASK 0x00000008L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF4_FLR_INTR_STS_MASK 0x00000010L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF5_FLR_INTR_STS_MASK 0x00000020L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF6_FLR_INTR_STS_MASK 0x00000040L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF7_FLR_INTR_STS_MASK 0x00000080L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_SOFTPF_FLR_INTR_STS_MASK 0x80000000L +//BIF_DEV0_PF1_VF_FLR_INTR_STS +#define BIF_DEV0_PF1_VF_FLR_INTR_STS__DEV0_PF1_VF0_FLR_INTR_STS__SHIFT 0x0 +#define BIF_DEV0_PF1_VF_FLR_INTR_STS__DEV0_PF1_VF0_FLR_INTR_STS_MASK 0x00000001L +//BIF_DEV0_PF0_VF_FLR_RST +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF0_FLR_RST__SHIFT 0x0 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF1_FLR_RST__SHIFT 0x1 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF2_FLR_RST__SHIFT 0x2 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF3_FLR_RST__SHIFT 0x3 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF4_FLR_RST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF5_FLR_RST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF6_FLR_RST__SHIFT 0x6 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF7_FLR_RST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_SOFTPF_FLR_RST__SHIFT 0x1f +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF0_FLR_RST_MASK 0x00000001L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF1_FLR_RST_MASK 0x00000002L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF2_FLR_RST_MASK 0x00000004L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF3_FLR_RST_MASK 0x00000008L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF4_FLR_RST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF5_FLR_RST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF6_FLR_RST_MASK 0x00000040L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF7_FLR_RST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_SOFTPF_FLR_RST_MASK 0x80000000L +//BIF_DEV0_PF1_VF_FLR_RST +#define BIF_DEV0_PF1_VF_FLR_RST__DEV0_PF1_VF0_FLR_RST__SHIFT 0x0 +#define BIF_DEV0_PF1_VF_FLR_RST__DEV0_PF1_VF0_FLR_RST_MASK 0x00000001L + + +// addressBlock: nbif0_nbif0_bif_misc_bif_misc_regblk +//DOE_PRV_CTRL0_DEV0F0 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_INT_MSG_NUMBER_DEV0F0__SHIFT 0x0 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_WRITE_THRESHOLD_DEV0F0__SHIFT 0xb +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_READ_THRESHOLD_DEV0F0__SHIFT 0x10 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_WOT_INTM_DEV0F0__SHIFT 0x15 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_ROT_INTM_DEV0F0__SHIFT 0x16 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_ABT_INTM_DEV0F0__SHIFT 0x17 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_GO_INTM_DEV0F0__SHIFT 0x18 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_PSN_INTM_DEV0F0__SHIFT 0x19 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_RUDF_INTM_DEV0F0__SHIFT 0x1a +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_INT_MSG_NUMBER_DEV0F0_MASK 0x000007FFL +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_WRITE_THRESHOLD_DEV0F0_MASK 0x0000F800L +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_READ_THRESHOLD_DEV0F0_MASK 0x001F0000L +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_WOT_INTM_DEV0F0_MASK 0x00200000L +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_ROT_INTM_DEV0F0_MASK 0x00400000L +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_ABT_INTM_DEV0F0_MASK 0x00800000L +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_GO_INTM_DEV0F0_MASK 0x01000000L +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_PSN_INTM_DEV0F0_MASK 0x02000000L +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_RUDF_INTM_DEV0F0_MASK 0x04000000L +//DOE_PRV_CMD_DEV0F0 +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_BUSY_CLR_ABORT_DEV0F0__SHIFT 0x0 +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_ERR_SET_DEV0F0__SHIFT 0x1 +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_DATA_REMAIN_DEV0F0__SHIFT 0x2 +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_DOE_RST_DEV0F0__SHIFT 0x8 +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_BUSY_CLR_NORSP_DEV0F0__SHIFT 0x9 +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_ASYNC_MSG_STS_DEV0F0__SHIFT 0xa +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_BUSY_CLR_ABORT_DEV0F0_MASK 0x00000001L +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_ERR_SET_DEV0F0_MASK 0x00000002L +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_DATA_REMAIN_DEV0F0_MASK 0x000000FCL +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_DOE_RST_DEV0F0_MASK 0x00000100L +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_BUSY_CLR_NORSP_DEV0F0_MASK 0x00000200L +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_ASYNC_MSG_STS_DEV0F0_MASK 0x00000400L +//DOE_PRV_WDATA_DEV0F0 +#define DOE_PRV_WDATA_DEV0F0__DOE_PRV_DATA_PUSH_DEV0F0__SHIFT 0x0 +#define DOE_PRV_WDATA_DEV0F0__DOE_PRV_DATA_PUSH_DEV0F0_MASK 0xFFFFFFFFL +//DOE_PRV_STS_DEV0F0 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_WRITE_OVER_THRESHOLD_DEV0F0__SHIFT 0x0 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_READ_UNDER_THRESHOLD_DEV0F0__SHIFT 0x1 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_ABORT_DET_DEV0F0__SHIFT 0x2 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_GO_DET_DEV0F0__SHIFT 0x3 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_PSN_DET_DEV0F0__SHIFT 0x4 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_UNDERFLOW_DET_DEV0F0__SHIFT 0x5 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_OCCUP_WMBOX_DEV0F0__SHIFT 0x6 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_VACA_RMBOX_DEV0F0__SHIFT 0xc +#define DOE_PRV_STS_DEV0F0__DOE_PRV_WRITE_OVER_THRESHOLD_DEV0F0_MASK 0x00000001L +#define DOE_PRV_STS_DEV0F0__DOE_PRV_READ_UNDER_THRESHOLD_DEV0F0_MASK 0x00000002L +#define DOE_PRV_STS_DEV0F0__DOE_PRV_ABORT_DET_DEV0F0_MASK 0x00000004L +#define DOE_PRV_STS_DEV0F0__DOE_PRV_GO_DET_DEV0F0_MASK 0x00000008L +#define DOE_PRV_STS_DEV0F0__DOE_PRV_PSN_DET_DEV0F0_MASK 0x00000010L +#define DOE_PRV_STS_DEV0F0__DOE_PRV_UNDERFLOW_DET_DEV0F0_MASK 0x00000020L +#define DOE_PRV_STS_DEV0F0__DOE_PRV_OCCUP_WMBOX_DEV0F0_MASK 0x00000FC0L +#define DOE_PRV_STS_DEV0F0__DOE_PRV_VACA_RMBOX_DEV0F0_MASK 0x0003F000L +//DOE_PRV_RDATA_DEV0F0 +#define DOE_PRV_RDATA_DEV0F0__DOE_PRV_RDATA_WMBOX_DEV0F0__SHIFT 0x0 +#define DOE_PRV_RDATA_DEV0F0__DOE_PRV_RDATA_WMBOX_DEV0F0_MASK 0xFFFFFFFFL +//NBIF_RC_INTR_CNTL +#define NBIF_RC_INTR_CNTL__RC_ERR_INTR_TRIG_DEV0__SHIFT 0x0 +#define NBIF_RC_INTR_CNTL__RC_ERR_INTR_TRIG_DEV0_MASK 0x00000001L +//BIF_DEV0_PF0_TDISP_CNTL +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF1_TDISP_CNTL +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF0_TDISP_CNTL +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF1_TDISP_CNTL +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF2_TDISP_CNTL +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF3_TDISP_CNTL +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF4_TDISP_CNTL +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF5_TDISP_CNTL +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF6_TDISP_CNTL +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF7_TDISP_CNTL +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF1_VF0_TDISP_CNTL +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_INTERFACE_ERROR_MASK 0x00000100L +//BIF_TDISP_ERROR_DEV0_PF0_INST0 +#define BIF_TDISP_ERROR_DEV0_PF0_INST0__BIF_TDISP_ERROR_DEV0_PF0_INST0__SHIFT 0x0 +#define BIF_TDISP_ERROR_DEV0_PF0_INST0__BIF_TDISP_ERROR_DEV0_PF0_INST0_MASK 0xFFFFFFFFL +//BIF_TDISP_ERROR_DEV0_PF1_INST0 +#define BIF_TDISP_ERROR_DEV0_PF1_INST0__BIF_TDISP_ERROR_DEV0_PF1_INST0__SHIFT 0x0 +#define BIF_TDISP_ERROR_DEV0_PF1_INST0__BIF_TDISP_ERROR_DEV0_PF1_INST0_MASK 0xFFFFFFFFL +//BIF_TDISP_UNLOCKED_DEV0_PF0_INST0 +#define BIF_TDISP_UNLOCKED_DEV0_PF0_INST0__BIF_TDISP_UNLOCKED_DEV0_PF0_INST0__SHIFT 0x0 +#define BIF_TDISP_UNLOCKED_DEV0_PF0_INST0__BIF_TDISP_UNLOCKED_DEV0_PF0_INST0_MASK 0xFFFFFFFFL +//BIF_TDISP_UNLOCKED_DEV0_PF1_INST0 +#define BIF_TDISP_UNLOCKED_DEV0_PF1_INST0__BIF_TDISP_UNLOCKED_DEV0_PF1_INST0__SHIFT 0x0 +#define BIF_TDISP_UNLOCKED_DEV0_PF1_INST0__BIF_TDISP_UNLOCKED_DEV0_PF1_INST0_MASK 0xFFFFFFFFL +//BIF_TDISP_MISC_CNTL_DEV0 +#define BIF_TDISP_MISC_CNTL_DEV0__BIF_RC_CONFIG_MONITOR_EN_DEV0__SHIFT 0x0 +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_NOT_IN_UNLOCK_FOR_VF_DEV0_PF0__SHIFT 0x5 +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_NOT_IN_ERR_FOR_VF_DEV0_PF0__SHIFT 0x6 +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_FOR_VF_DEV0_PF0__SHIFT 0x7 +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_FOR_VF_DEV0_PF0__SHIFT 0x8 +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_NOT_IN_UNLOCK_FOR_VF_DEV0_PF1__SHIFT 0x9 +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_NOT_IN_ERR_FOR_VF_DEV0_PF1__SHIFT 0xa +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_FOR_VF_DEV0_PF1__SHIFT 0xb +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_FOR_VF_DEV0_PF1__SHIFT 0xc +#define BIF_TDISP_MISC_CNTL_DEV0__BIF_RC_CONFIG_MONITOR_EN_DEV0_MASK 0x00000001L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_NOT_IN_UNLOCK_FOR_VF_DEV0_PF0_MASK 0x00000020L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_NOT_IN_ERR_FOR_VF_DEV0_PF0_MASK 0x00000040L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_FOR_VF_DEV0_PF0_MASK 0x00000080L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_FOR_VF_DEV0_PF0_MASK 0x00000100L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_NOT_IN_UNLOCK_FOR_VF_DEV0_PF1_MASK 0x00000200L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_NOT_IN_ERR_FOR_VF_DEV0_PF1_MASK 0x00000400L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_FOR_VF_DEV0_PF1_MASK 0x00000800L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_FOR_VF_DEV0_PF1_MASK 0x00001000L +//BIF_TDISP_MISC_CNTL +#define BIF_TDISP_MISC_CNTL__BIF_MSI_MSIX_IDE_TBIT_OVERRIDE__SHIFT 0x0 +#define BIF_TDISP_MISC_CNTL__REMOTE_TDISP_STATE_VECTOR_CLR__SHIFT 0x1 +#define BIF_TDISP_MISC_CNTL__NBIF_GMI_TDISP_REMOTE_TX_EN__SHIFT 0x3 +#define BIF_TDISP_MISC_CNTL__BIF_TRUSTED_IO_ERR_Intr_0_MASK__SHIFT 0x4 +#define BIF_TDISP_MISC_CNTL__DSPT_CFG_RST_TRIG_TO_UNLOCK_MASK__SHIFT 0xa +#define BIF_TDISP_MISC_CNTL__EP_CFG_RST_TRIG_TO_UNLOCK_MASK__SHIFT 0xb +#define BIF_TDISP_MISC_CNTL__TDISP_ERR_AER_DIS__SHIFT 0xc +#define BIF_TDISP_MISC_CNTL__TDISP_ERR_PRGR_AER_EN__SHIFT 0xd +#define BIF_TDISP_MISC_CNTL__BIF_TBIT_FOR_RUN_BIH_MEM__SHIFT 0xe +#define BIF_TDISP_MISC_CNTL__BIF_XT1_FOR_RUN_BIH_MEM__SHIFT 0xf +#define BIF_TDISP_MISC_CNTL__BIF_MSI_MSIX_IDE_TBIT_OVERRIDE_MASK 0x00000001L +#define BIF_TDISP_MISC_CNTL__REMOTE_TDISP_STATE_VECTOR_CLR_MASK 0x00000002L +#define BIF_TDISP_MISC_CNTL__NBIF_GMI_TDISP_REMOTE_TX_EN_MASK 0x00000008L +#define BIF_TDISP_MISC_CNTL__BIF_TRUSTED_IO_ERR_Intr_0_MASK_MASK 0x00000010L +#define BIF_TDISP_MISC_CNTL__DSPT_CFG_RST_TRIG_TO_UNLOCK_MASK_MASK 0x00000400L +#define BIF_TDISP_MISC_CNTL__EP_CFG_RST_TRIG_TO_UNLOCK_MASK_MASK 0x00000800L +#define BIF_TDISP_MISC_CNTL__TDISP_ERR_AER_DIS_MASK 0x00001000L +#define BIF_TDISP_MISC_CNTL__TDISP_ERR_PRGR_AER_EN_MASK 0x00002000L +#define BIF_TDISP_MISC_CNTL__BIF_TBIT_FOR_RUN_BIH_MEM_MASK 0x00004000L +#define BIF_TDISP_MISC_CNTL__BIF_XT1_FOR_RUN_BIH_MEM_MASK 0x00008000L +//BIF_RCC_IDE_TDISP_CNTL +#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_TDISP_PRGR_CHECK_EN__SHIFT 0x0 +#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_TDISP_PRGR_FOR_UNLOCK_CHECK_EN__SHIFT 0x1 +#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_CHECK_EN__SHIFT 0x2 +#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_TDISP_PRGR_CHECK_EN_MASK 0x00000001L +#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_TDISP_PRGR_FOR_UNLOCK_CHECK_EN_MASK 0x00000002L +#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_CHECK_EN_MASK 0x00000004L +//BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_SYSTEM_EN +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0__SHIFT 0x0 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF0__SHIFT 0x1 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF1__SHIFT 0x2 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF2__SHIFT 0x3 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF3__SHIFT 0x4 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF4__SHIFT 0x5 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF5__SHIFT 0x6 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF6__SHIFT 0x7 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF7__SHIFT 0x8 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_MASK 0x00000001L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF0_MASK 0x00000002L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF1_MASK 0x00000004L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF2_MASK 0x00000008L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF3_MASK 0x00000010L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF4_MASK 0x00000020L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF5_MASK 0x00000040L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF6_MASK 0x00000080L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF7_MASK 0x00000100L +//BIF_MASK_SYSTEM_EN +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0__SHIFT 0x0 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF0__SHIFT 0x1 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF1__SHIFT 0x2 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF2__SHIFT 0x3 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF3__SHIFT 0x4 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF4__SHIFT 0x5 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF5__SHIFT 0x6 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF6__SHIFT 0x7 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF7__SHIFT 0x8 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_MASK 0x00000001L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF0_MASK 0x00000002L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF1_MASK 0x00000004L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF2_MASK 0x00000008L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF3_MASK 0x00000010L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF4_MASK 0x00000020L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF5_MASK 0x00000040L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF6_MASK 0x00000080L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF7_MASK 0x00000100L +//GPUIOV_SCH0 +#define GPUIOV_SCH0__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH0__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH1 +#define GPUIOV_SCH1__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH1__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH2 +#define GPUIOV_SCH2__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH2__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH3 +#define GPUIOV_SCH3__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH3__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH4 +#define GPUIOV_SCH4__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH4__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH5 +#define GPUIOV_SCH5__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH5__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH6 +#define GPUIOV_SCH6__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH6__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH7 +#define GPUIOV_SCH7__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH7__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH8 +#define GPUIOV_SCH8__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH8__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH9 +#define GPUIOV_SCH9__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH9__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH10 +#define GPUIOV_SCH10__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH10__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH11 +#define GPUIOV_SCH11__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH11__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH12 +#define GPUIOV_SCH12__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH12__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH13 +#define GPUIOV_SCH13__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH13__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH14 +#define GPUIOV_SCH14__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH14__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH15 +#define GPUIOV_SCH15__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH15__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH16 +#define GPUIOV_SCH16__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH16__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH17 +#define GPUIOV_SCH17__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH17__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH18 +#define GPUIOV_SCH18__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH18__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH19 +#define GPUIOV_SCH19__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH19__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_MMHUB_P2P_CNTL +#define GPUIOV_MMHUB_P2P_CNTL__GPUIOV_MMHUB_P2P_ENABLE_REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_MMHUB_P2P_CNTL__GPUIOV_MMHUB_P2P_ENABLE_REMAP_ADDR_MASK 0x000FFFFFL +//BIF_AER_INTR_CTRL +#define BIF_AER_INTR_CTRL__BIF_AER_INTR_MASK__SHIFT 0x0 +#define BIF_AER_INTR_CTRL__BIF_AER_SMN_POSTED__SHIFT 0x1 +#define BIF_AER_INTR_CTRL__BIF_AER_SMN_WDATA_SEL__SHIFT 0x2 +#define BIF_AER_INTR_CTRL__BIF_AER_INTR_MASK_MASK 0x00000001L +#define BIF_AER_INTR_CTRL__BIF_AER_SMN_POSTED_MASK 0x00000002L +#define BIF_AER_INTR_CTRL__BIF_AER_SMN_WDATA_SEL_MASK 0x00000004L +//BIF_AER_INTR_STS +#define BIF_AER_INTR_STS__BIF_AER_INTR_STS__SHIFT 0x0 +#define BIF_AER_INTR_STS__BIF_AER_INTR_STS_MASK 0x00000001L +//BIF_PCIE_MSG_CTRL +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VALID__SHIFT 0x0 +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_PORTID__SHIFT 0x1 +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VF_VALID__SHIFT 0x3 +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VFID__SHIFT 0x4 +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VALID_MASK 0x00000001L +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_PORTID_MASK 0x00000006L +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VF_VALID_MASK 0x00000008L +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VFID_MASK 0x00003FF0L +//BIF_PCIE_MSG_HEADER_DW0 +#define BIF_PCIE_MSG_HEADER_DW0__BIF_PCIE_MSG_HEADER_DW0__SHIFT 0x0 +#define BIF_PCIE_MSG_HEADER_DW0__BIF_PCIE_MSG_HEADER_DW0_MASK 0xFFFFFFFFL +//BIF_PCIE_MSG_HEADER_DW1 +#define BIF_PCIE_MSG_HEADER_DW1__BIF_PCIE_MSG_HEADER_DW1__SHIFT 0x0 +#define BIF_PCIE_MSG_HEADER_DW1__BIF_PCIE_MSG_HEADER_DW1_MASK 0xFFFFFFFFL +//BIF_PCIE_MSG_HEADER_DW2 +#define BIF_PCIE_MSG_HEADER_DW2__BIF_PCIE_MSG_HEADER_DW2__SHIFT 0x0 +#define BIF_PCIE_MSG_HEADER_DW2__BIF_PCIE_MSG_HEADER_DW2_MASK 0xFFFFFFFFL +//BIF_PCIE_MSG_HEADER_DW3 +#define BIF_PCIE_MSG_HEADER_DW3__BIF_PCIE_MSG_HEADER_DW3__SHIFT 0x0 +#define BIF_PCIE_MSG_HEADER_DW3__BIF_PCIE_MSG_HEADER_DW3_MASK 0xFFFFFFFFL +//BIF_PCIE_MSG_DATA_DW0 +#define BIF_PCIE_MSG_DATA_DW0__BIF_PCIE_MSG_DATA_DW0__SHIFT 0x0 +#define BIF_PCIE_MSG_DATA_DW0__BIF_PCIE_MSG_DATA_DW0_MASK 0xFFFFFFFFL +//BIF_PCIE_MSG_DATA_DW1 +#define BIF_PCIE_MSG_DATA_DW1__BIF_PCIE_MSG_DATA_DW1__SHIFT 0x0 +#define BIF_PCIE_MSG_DATA_DW1__BIF_PCIE_MSG_DATA_DW1_MASK 0xFFFFFFFFL +//BIF_PCIE_MSG_DATA_DW2 +#define BIF_PCIE_MSG_DATA_DW2__BIF_PCIE_MSG_DATA_DW2__SHIFT 0x0 +#define BIF_PCIE_MSG_DATA_DW2__BIF_PCIE_MSG_DATA_DW2_MASK 0xFFFFFFFFL +//BIF_PCIE_MSG_DATA_DW3 +#define BIF_PCIE_MSG_DATA_DW3__BIF_PCIE_MSG_DATA_DW3__SHIFT 0x0 +#define BIF_PCIE_MSG_DATA_DW3__BIF_PCIE_MSG_DATA_DW3_MASK 0xFFFFFFFFL +//BIFC_SEC_AER_SMN_CTRL0 +#define BIFC_SEC_AER_SMN_CTRL0__BIF_AER_INT_REQ_ADDR__SHIFT 0x0 +#define BIFC_SEC_AER_SMN_CTRL0__BIF_AER_INT_REQ_APER_ID__SHIFT 0x14 +#define BIFC_SEC_AER_SMN_CTRL0__BIF_AER_INT_REQ_ADDR_MASK 0x000FFFFFL +#define BIFC_SEC_AER_SMN_CTRL0__BIF_AER_INT_REQ_APER_ID_MASK 0xFFF00000L +//BIFC_SEC_AER_SMN_CTRL1 +#define BIFC_SEC_AER_SMN_CTRL1__BIF_AER_INT_REQ_MCM_ADDR__SHIFT 0x0 +#define BIFC_SEC_AER_SMN_CTRL1__BIF_AER_SMN_SEC_SEL__SHIFT 0x10 +#define BIFC_SEC_AER_SMN_CTRL1__BIF_AER_INT_REQ_MCM_ADDR_MASK 0x0000FFFFL +#define BIFC_SEC_AER_SMN_CTRL1__BIF_AER_SMN_SEC_SEL_MASK 0x000F0000L +//BIFC_SEC_AER_SMN_CTRL2 +#define BIFC_SEC_AER_SMN_CTRL2__BIF_AER_INT_REQ_WDATA__SHIFT 0x0 +#define BIFC_SEC_AER_SMN_CTRL2__BIF_AER_INT_REQ_WDATA_MASK 0xFFFFFFFFL +//BIF_PCIE_ERR_CTRL0 +#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_VF_NUM__SHIFT 0x0 +#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_VF__SHIFT 0x7 +#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_PF_NUM__SHIFT 0x8 +#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_VF_NUM_MASK 0x0000007FL +#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_VF_MASK 0x00000080L +#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_PF_NUM_MASK 0x00000700L +//BIF_PCIE_ERR_CTRL1 +#define BIF_PCIE_ERR_CTRL1__BIF_CORR_ERR_EN__SHIFT 0x0 +#define BIF_PCIE_ERR_CTRL1__BIF_NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_PCIE_ERR_CTRL1__BIF_FATAL_ERR_EN__SHIFT 0x2 +#define BIF_PCIE_ERR_CTRL1__BIF_USR_REPORT_EN__SHIFT 0x3 +#define BIF_PCIE_ERR_CTRL1__BIF_SERR_EN__SHIFT 0x4 +#define BIF_PCIE_ERR_CTRL1__BIF_MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_PCIE_ERR_CTRL1__BIF_SIGNALED_SYSTEM_ERROR__SHIFT 0x9 +#define BIF_PCIE_ERR_CTRL1__BIF_PARITY_ERROR_DETECTED__SHIFT 0xa +#define BIF_PCIE_ERR_CTRL1__BIF_PCIE_DEVICE_STATUS__SHIFT 0x10 +#define BIF_PCIE_ERR_CTRL1__BIF_CORR_ERR_EN_MASK 0x00000001L +#define BIF_PCIE_ERR_CTRL1__BIF_NON_FATAL_ERR_EN_MASK 0x00000002L +#define BIF_PCIE_ERR_CTRL1__BIF_FATAL_ERR_EN_MASK 0x00000004L +#define BIF_PCIE_ERR_CTRL1__BIF_USR_REPORT_EN_MASK 0x00000008L +#define BIF_PCIE_ERR_CTRL1__BIF_SERR_EN_MASK 0x00000010L +#define BIF_PCIE_ERR_CTRL1__BIF_MASTER_DATA_PARITY_ERROR_MASK 0x00000100L +#define BIF_PCIE_ERR_CTRL1__BIF_SIGNALED_SYSTEM_ERROR_MASK 0x00000200L +#define BIF_PCIE_ERR_CTRL1__BIF_PARITY_ERROR_DETECTED_MASK 0x00000400L +#define BIF_PCIE_ERR_CTRL1__BIF_PCIE_DEVICE_STATUS_MASK 0xFFFF0000L +//BIF_PCIE_ERR_CTRL2 +#define BIF_PCIE_ERR_CTRL2__BIF_AER_FEP__SHIFT 0x0 +#define BIF_PCIE_ERR_CTRL2__BIF_AER_TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_PCIE_ERR_CTRL2__BIF_AER_LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_PCIE_ERR_CTRL2__BIF_AER_FEP_MASK 0x0000001FL +#define BIF_PCIE_ERR_CTRL2__BIF_AER_TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_PCIE_ERR_CTRL2__BIF_AER_LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_AER_UNCORR_ERR_STATUS +#define BIF_AER_UNCORR_ERR_STATUS__BIF_AER_UNCORR_ERR_STATUS__SHIFT 0x0 +#define BIF_AER_UNCORR_ERR_STATUS__BIF_AER_UNCORR_ERR_STATUS_MASK 0xFFFFFFFFL +//BIF_AER_UNCORR_ERR_MASK +#define BIF_AER_UNCORR_ERR_MASK__BIF_AER_UNCORR_ERR_MASK__SHIFT 0x0 +#define BIF_AER_UNCORR_ERR_MASK__BIF_AER_UNCORR_ERR_MASK_MASK 0xFFFFFFFFL +//BIF_AER_UNCORR_ERR_SEVERITY +#define BIF_AER_UNCORR_ERR_SEVERITY__BIF_AER_UNCORR_ERR_SEVERITY__SHIFT 0x0 +#define BIF_AER_UNCORR_ERR_SEVERITY__BIF_AER_UNCORR_ERR_SEVERITY_MASK 0xFFFFFFFFL +//BIF_AER_CORR_ERR_STATUS +#define BIF_AER_CORR_ERR_STATUS__BIF_AER_CORR_ERR_STATUS__SHIFT 0x0 +#define BIF_AER_CORR_ERR_STATUS__BIF_AER_CORR_ERR_STATUS_MASK 0xFFFFFFFFL +//BIF_AER_CORR_ERR_MASK +#define BIF_AER_CORR_ERR_MASK__BIF_AER_CORR_ERR_MASK__SHIFT 0x0 +#define BIF_AER_CORR_ERR_MASK__BIF_AER_CORR_ERR_MASK_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_0 +#define RCC_EP_STICKY_RESTORE_0__RESTORE_PCIE_TLP_HDR_0__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_0__RESTORE_PCIE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_1 +#define RCC_EP_STICKY_RESTORE_1__RESTORE_PCIE_TLP_HDR_1__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_1__RESTORE_PCIE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_2 +#define RCC_EP_STICKY_RESTORE_2__RESTORE_PCIE_TLP_HDR_2__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_2__RESTORE_PCIE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_3 +#define RCC_EP_STICKY_RESTORE_3__RESTORE_PCIE_TLP_HDR_3__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_3__RESTORE_PCIE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_4 +#define RCC_EP_STICKY_RESTORE_4__RESTORE_PCIE_TLP_HDR_4__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_4__RESTORE_PCIE_TLP_HDR_4_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_5 +#define RCC_EP_STICKY_RESTORE_5__RESTORE_PCIE_TLP_HDR_5__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_5__RESTORE_PCIE_TLP_HDR_5_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_6 +#define RCC_EP_STICKY_RESTORE_6__RESTORE_PCIE_TLP_HDR_6__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_6__RESTORE_PCIE_TLP_HDR_6_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_7 +#define RCC_EP_STICKY_RESTORE_7__RESTORE_PCIE_TLP_HDR_7__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_7__RESTORE_PCIE_TLP_HDR_7_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_8 +#define RCC_EP_STICKY_RESTORE_8__RESTORE_PCIE_TLP_HDR_8__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_8__RESTORE_PCIE_TLP_HDR_8_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_9 +#define RCC_EP_STICKY_RESTORE_9__RESTORE_PCIE_TLP_HDR_9__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_9__RESTORE_PCIE_TLP_HDR_9_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_10 +#define RCC_EP_STICKY_RESTORE_10__RESTORE_PCIE_TLP_HDR_10__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_10__RESTORE_PCIE_TLP_HDR_10_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_11 +#define RCC_EP_STICKY_RESTORE_11__RESTORE_PCIE_TLP_HDR_11__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_11__RESTORE_PCIE_TLP_HDR_11_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_12 +#define RCC_EP_STICKY_RESTORE_12__RESTORE_PCIE_TLP_HDR_12__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_12__RESTORE_PCIE_TLP_HDR_12_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_13 +#define RCC_EP_STICKY_RESTORE_13__RESTORE_PCIE_TLP_HDR_13__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_13__RESTORE_PCIE_TLP_HDR_13_MASK 0xFFFFFFFFL +//BIF_DEVICE3_STATUS +#define BIF_DEVICE3_STATUS__BIF_DEVICE3_INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_DEVICE3_STATUS__BIF_DEVICE3_SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_DEVICE3_STATUS__BIF_DEVICE3_REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_DEVICE3_STATUS__BIF_DEVICE3_INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_DEVICE3_STATUS__BIF_DEVICE3_SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_DEVICE3_STATUS__BIF_DEVICE3_REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIFC_SEC_MCTP_SMN_CTRL0 +#define BIFC_SEC_MCTP_SMN_CTRL0__MCTP_INT_REQ_ADDR__SHIFT 0x0 +#define BIFC_SEC_MCTP_SMN_CTRL0__MCTP_INT_REQ_APER_ID__SHIFT 0x14 +#define BIFC_SEC_MCTP_SMN_CTRL0__MCTP_INT_REQ_ADDR_MASK 0x000FFFFFL +#define BIFC_SEC_MCTP_SMN_CTRL0__MCTP_INT_REQ_APER_ID_MASK 0xFFF00000L +//BIFC_SEC_MCTP_SMN_CTRL1 +#define BIFC_SEC_MCTP_SMN_CTRL1__MCTP_INT_REQ_MCM_ADDR__SHIFT 0x0 +#define BIFC_SEC_MCTP_SMN_CTRL1__MCTP_SMN_SEC_SEL__SHIFT 0x10 +#define BIFC_SEC_MCTP_SMN_CTRL1__MCTP_INT_REQ_MCM_ADDR_MASK 0x0000FFFFL +#define BIFC_SEC_MCTP_SMN_CTRL1__MCTP_SMN_SEC_SEL_MASK 0x000F0000L +//NBIF_MCTP_GENERIC_CNTL +#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_SUPPORT__SHIFT 0x0 +#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_ROUTING_CODE_CHECK__SHIFT 0x1 +#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_RBID_CPLID_CNTL__SHIFT 0x2 +#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_SUPPORT_MASK 0x00000001L +#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_ROUTING_CODE_CHECK_MASK 0x00000002L +#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_RBID_CPLID_CNTL_MASK 0x00000004L +//NBIF_MCTP_GENERIC_STATUS +#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_ERR_FLAG__SHIFT 0x0 +#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_RB_EMPTY_STATUS__SHIFT 0x1 +#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_RB_FULL_STATUS__SHIFT 0x2 +#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_ERR_FLAG_MASK 0x00000001L +#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_RB_EMPTY_STATUS_MASK 0x00000002L +#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_RB_FULL_STATUS_MASK 0x00000004L +//SDPVW_UPDATE_EN +#define SDPVW_UPDATE_EN__SDPVW_UPDATE_EN__SHIFT 0x0 +#define SDPVW_UPDATE_EN__SWUS_SECBUSRST_SET_EN__SHIFT 0x1 +#define SDPVW_UPDATE_EN__SDPVW_UPDATE_EN_MASK 0x01L +#define SDPVW_UPDATE_EN__SWUS_SECBUSRST_SET_EN_MASK 0x02L +//REGS_ROM_OFFSET_CTRL +#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET__SHIFT 0x0 +#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET_MASK 0x7FL +//BIFL_SEC_RAS_POISON_DATA_DROP_CTRL +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF0_POISON_DATA_DROP_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF1_POISON_DATA_DROP_EN__SHIFT 0x1 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF2_POISON_DATA_DROP_EN__SHIFT 0x2 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF3_POISON_DATA_DROP_EN__SHIFT 0x3 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF4_POISON_DATA_DROP_EN__SHIFT 0x4 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF5_POISON_DATA_DROP_EN__SHIFT 0x5 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF6_POISON_DATA_DROP_EN__SHIFT 0x6 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF7_POISON_DATA_DROP_EN__SHIFT 0x7 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF8_POISON_DATA_DROP_EN__SHIFT 0x8 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF9_POISON_DATA_DROP_EN__SHIFT 0x9 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF10_POISON_DATA_DROP_EN__SHIFT 0xa +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF11_POISON_DATA_DROP_EN__SHIFT 0xb +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF12_POISON_DATA_DROP_EN__SHIFT 0xc +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF13_POISON_DATA_DROP_EN__SHIFT 0xd +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF14_POISON_DATA_DROP_EN__SHIFT 0xe +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF15_POISON_DATA_DROP_EN__SHIFT 0xf +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF16_POISON_DATA_DROP_EN__SHIFT 0x10 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF17_POISON_DATA_DROP_EN__SHIFT 0x11 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF18_POISON_DATA_DROP_EN__SHIFT 0x12 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF19_POISON_DATA_DROP_EN__SHIFT 0x13 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF0_POISON_DATA_DROP_EN_MASK 0x00000001L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF1_POISON_DATA_DROP_EN_MASK 0x00000002L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF2_POISON_DATA_DROP_EN_MASK 0x00000004L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF3_POISON_DATA_DROP_EN_MASK 0x00000008L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF4_POISON_DATA_DROP_EN_MASK 0x00000010L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF5_POISON_DATA_DROP_EN_MASK 0x00000020L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF6_POISON_DATA_DROP_EN_MASK 0x00000040L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF7_POISON_DATA_DROP_EN_MASK 0x00000080L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF8_POISON_DATA_DROP_EN_MASK 0x00000100L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF9_POISON_DATA_DROP_EN_MASK 0x00000200L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF10_POISON_DATA_DROP_EN_MASK 0x00000400L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF11_POISON_DATA_DROP_EN_MASK 0x00000800L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF12_POISON_DATA_DROP_EN_MASK 0x00001000L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF13_POISON_DATA_DROP_EN_MASK 0x00002000L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF14_POISON_DATA_DROP_EN_MASK 0x00004000L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF15_POISON_DATA_DROP_EN_MASK 0x00008000L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF16_POISON_DATA_DROP_EN_MASK 0x00010000L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF17_POISON_DATA_DROP_EN_MASK 0x00020000L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF18_POISON_DATA_DROP_EN_MASK 0x00040000L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF19_POISON_DATA_DROP_EN_MASK 0x00080000L +//REGS_INDEX_DATA_PAIR_CTRL +#define REGS_INDEX_DATA_PAIR_CTRL__MM_DATA_DIS__SHIFT 0x0 +#define REGS_INDEX_DATA_PAIR_CTRL__SYSHUB_DATA_DIS__SHIFT 0x1 +#define REGS_INDEX_DATA_PAIR_CTRL__PCIE_DATA_DIS__SHIFT 0x2 +#define REGS_INDEX_DATA_PAIR_CTRL__PCIE_DATA2_DIS__SHIFT 0x3 +#define REGS_INDEX_DATA_PAIR_CTRL__MM_DATA_DIS_MASK 0x00000001L +#define REGS_INDEX_DATA_PAIR_CTRL__SYSHUB_DATA_DIS_MASK 0x00000002L +#define REGS_INDEX_DATA_PAIR_CTRL__PCIE_DATA_DIS_MASK 0x00000004L +#define REGS_INDEX_DATA_PAIR_CTRL__PCIE_DATA2_DIS_MASK 0x00000008L +//BIFL_SEC_RAS_RESPONSE_DROP_CTRL +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF0_RESPONSE_DROP_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF1_RESPONSE_DROP_EN__SHIFT 0x1 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF2_RESPONSE_DROP_EN__SHIFT 0x2 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF3_RESPONSE_DROP_EN__SHIFT 0x3 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF4_RESPONSE_DROP_EN__SHIFT 0x4 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF5_RESPONSE_DROP_EN__SHIFT 0x5 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF6_RESPONSE_DROP_EN__SHIFT 0x6 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF7_RESPONSE_DROP_EN__SHIFT 0x7 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF8_RESPONSE_DROP_EN__SHIFT 0x8 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF9_RESPONSE_DROP_EN__SHIFT 0x9 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF10_RESPONSE_DROP_EN__SHIFT 0xa +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF11_RESPONSE_DROP_EN__SHIFT 0xb +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF12_RESPONSE_DROP_EN__SHIFT 0xc +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF13_RESPONSE_DROP_EN__SHIFT 0xd +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF14_RESPONSE_DROP_EN__SHIFT 0xe +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF15_RESPONSE_DROP_EN__SHIFT 0xf +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF16_RESPONSE_DROP_EN__SHIFT 0x10 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF17_RESPONSE_DROP_EN__SHIFT 0x11 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF18_RESPONSE_DROP_EN__SHIFT 0x12 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF19_RESPONSE_DROP_EN__SHIFT 0x13 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF0_RESPONSE_DROP_EN_MASK 0x00000001L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF1_RESPONSE_DROP_EN_MASK 0x00000002L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF2_RESPONSE_DROP_EN_MASK 0x00000004L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF3_RESPONSE_DROP_EN_MASK 0x00000008L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF4_RESPONSE_DROP_EN_MASK 0x00000010L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF5_RESPONSE_DROP_EN_MASK 0x00000020L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF6_RESPONSE_DROP_EN_MASK 0x00000040L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF7_RESPONSE_DROP_EN_MASK 0x00000080L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF8_RESPONSE_DROP_EN_MASK 0x00000100L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF9_RESPONSE_DROP_EN_MASK 0x00000200L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF10_RESPONSE_DROP_EN_MASK 0x00000400L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF11_RESPONSE_DROP_EN_MASK 0x00000800L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF12_RESPONSE_DROP_EN_MASK 0x00001000L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF13_RESPONSE_DROP_EN_MASK 0x00002000L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF14_RESPONSE_DROP_EN_MASK 0x00004000L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF15_RESPONSE_DROP_EN_MASK 0x00008000L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF16_RESPONSE_DROP_EN_MASK 0x00010000L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF17_RESPONSE_DROP_EN_MASK 0x00020000L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF18_RESPONSE_DROP_EN_MASK 0x00040000L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF19_RESPONSE_DROP_EN_MASK 0x00080000L +//BIFC_SEC_MCA_SMN_CTRL0 +#define BIFC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_ADDR__SHIFT 0x0 +#define BIFC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_APER_ID__SHIFT 0x14 +#define BIFC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_ADDR_MASK 0x000FFFFFL +#define BIFC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_APER_ID_MASK 0xFFF00000L +//BIFC_SEC_MCA_SMN_CTRL1 +#define BIFC_SEC_MCA_SMN_CTRL1__MCA_INT_REQ_MCM_ADDR__SHIFT 0x0 +#define BIFC_SEC_MCA_SMN_CTRL1__MCA_SMN_SEC_SEL__SHIFT 0x10 +#define BIFC_SEC_MCA_SMN_CTRL1__MCA_INT_REQ_MCM_ADDR_MASK 0x0000FFFFL +#define BIFC_SEC_MCA_SMN_CTRL1__MCA_SMN_SEC_SEL_MASK 0x000F0000L +//BIFL_SEC_RAS_POISON_DBUG_CTRL +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_POISON_DBUG_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_POISON_DBUG_EN__SHIFT 0x1 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_POISON_DBUG_EN__SHIFT 0x2 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_POISON_DBUG_EN__SHIFT 0x3 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_POISON_DBUG_EN__SHIFT 0x4 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_POISON_DBUG_EN__SHIFT 0x5 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_POISON_DBUG_EN__SHIFT 0x6 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_POISON_DBUG_EN__SHIFT 0x7 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_POISON_DBUG_EN__SHIFT 0x8 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_POISON_DBUG_EN__SHIFT 0x9 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_POISON_DBUG_EN__SHIFT 0xa +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_POISON_DBUG_EN__SHIFT 0xb +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_POISON_DBUG_EN__SHIFT 0xc +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_POISON_DBUG_EN__SHIFT 0xd +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_POISON_DBUG_EN__SHIFT 0xe +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_POISON_DBUG_EN__SHIFT 0xf +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_POISON_DBUG_EN__SHIFT 0x10 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_POISON_DBUG_EN__SHIFT 0x11 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_POISON_DBUG_EN__SHIFT 0x12 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_POISON_DBUG_EN__SHIFT 0x13 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_POISON_DBUG_EN_MASK 0x00000001L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_POISON_DBUG_EN_MASK 0x00000002L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_POISON_DBUG_EN_MASK 0x00000004L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_POISON_DBUG_EN_MASK 0x00000008L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_POISON_DBUG_EN_MASK 0x00000010L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_POISON_DBUG_EN_MASK 0x00000020L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_POISON_DBUG_EN_MASK 0x00000040L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_POISON_DBUG_EN_MASK 0x00000080L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_POISON_DBUG_EN_MASK 0x00000100L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_POISON_DBUG_EN_MASK 0x00000200L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_POISON_DBUG_EN_MASK 0x00000400L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_POISON_DBUG_EN_MASK 0x00000800L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_POISON_DBUG_EN_MASK 0x00001000L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_POISON_DBUG_EN_MASK 0x00002000L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_POISON_DBUG_EN_MASK 0x00004000L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_POISON_DBUG_EN_MASK 0x00008000L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_POISON_DBUG_EN_MASK 0x00010000L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_POISON_DBUG_EN_MASK 0x00020000L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_POISON_DBUG_EN_MASK 0x00040000L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_POISON_DBUG_EN_MASK 0x00080000L +//BIFL_SEC_RAS_PARITY_DBUG_CTRL +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_PARITY_DBUG_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_PARITY_DBUG_EN__SHIFT 0x1 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_PARITY_DBUG_EN__SHIFT 0x2 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_PARITY_DBUG_EN__SHIFT 0x3 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_PARITY_DBUG_EN__SHIFT 0x4 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_PARITY_DBUG_EN__SHIFT 0x5 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_PARITY_DBUG_EN__SHIFT 0x6 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_PARITY_DBUG_EN__SHIFT 0x7 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_PARITY_DBUG_EN__SHIFT 0x8 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_PARITY_DBUG_EN__SHIFT 0x9 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_PARITY_DBUG_EN__SHIFT 0xa +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_PARITY_DBUG_EN__SHIFT 0xb +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_PARITY_DBUG_EN__SHIFT 0xc +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_PARITY_DBUG_EN__SHIFT 0xd +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_PARITY_DBUG_EN__SHIFT 0xe +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_PARITY_DBUG_EN__SHIFT 0xf +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_PARITY_DBUG_EN__SHIFT 0x10 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_PARITY_DBUG_EN__SHIFT 0x11 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_PARITY_DBUG_EN__SHIFT 0x12 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_PARITY_DBUG_EN__SHIFT 0x13 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_PARITY_DBUG_EN_MASK 0x00000001L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_PARITY_DBUG_EN_MASK 0x00000002L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_PARITY_DBUG_EN_MASK 0x00000004L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_PARITY_DBUG_EN_MASK 0x00000008L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_PARITY_DBUG_EN_MASK 0x00000010L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_PARITY_DBUG_EN_MASK 0x00000020L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_PARITY_DBUG_EN_MASK 0x00000040L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_PARITY_DBUG_EN_MASK 0x00000080L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_PARITY_DBUG_EN_MASK 0x00000100L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_PARITY_DBUG_EN_MASK 0x00000200L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_PARITY_DBUG_EN_MASK 0x00000400L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_PARITY_DBUG_EN_MASK 0x00000800L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_PARITY_DBUG_EN_MASK 0x00001000L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_PARITY_DBUG_EN_MASK 0x00002000L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_PARITY_DBUG_EN_MASK 0x00004000L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_PARITY_DBUG_EN_MASK 0x00008000L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_PARITY_DBUG_EN_MASK 0x00010000L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_PARITY_DBUG_EN_MASK 0x00020000L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_PARITY_DBUG_EN_MASK 0x00040000L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_PARITY_DBUG_EN_MASK 0x00080000L +//BIFL_SEC_RAS_NTB_DBUG_CTRL +#define BIFL_SEC_RAS_NTB_DBUG_CTRL__BIFL_SEC_RAS_LEAF_NTB_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_NTB_DBUG_CTRL__BIFL_SEC_RAS_LEAF_NTB_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000001L +//BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x1 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x2 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x3 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x4 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x5 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x6 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x7 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x8 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x9 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xa +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xb +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xc +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xd +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xe +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xf +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x10 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x11 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x12 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x13 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000001L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000002L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000004L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000008L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000010L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000020L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000040L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000080L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000100L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000200L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000400L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000800L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00001000L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00002000L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00004000L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00008000L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00010000L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00020000L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00040000L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00080000L +//BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x1 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x2 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x3 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x4 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x5 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x6 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x7 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x8 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x9 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xa +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xb +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xc +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xd +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xe +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xf +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x10 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x11 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x12 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x13 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000001L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000002L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000004L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000008L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000010L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000020L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000040L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000080L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000100L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000200L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000400L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000800L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_TIMEOUT_DBUG_EN_MASK 0x00001000L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_TIMEOUT_DBUG_EN_MASK 0x00002000L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_TIMEOUT_DBUG_EN_MASK 0x00004000L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_TIMEOUT_DBUG_EN_MASK 0x00008000L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_TIMEOUT_DBUG_EN_MASK 0x00010000L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_TIMEOUT_DBUG_EN_MASK 0x00020000L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_TIMEOUT_DBUG_EN_MASK 0x00040000L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_TIMEOUT_DBUG_EN_MASK 0x00080000L +//BIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF0_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF0_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF0_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF0_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF1_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF1_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF1_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF1_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF2_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF2_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF2_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF2_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF3_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF3_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF3_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF3_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF4_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF4_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF4_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF4_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF5_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF5_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF5_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF5_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF6_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF6_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF6_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF6_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF7_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF7_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF7_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF7_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF8_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF8_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF8_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF8_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF9_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF9_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF9_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF9_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF10_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF10_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF10_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF10_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF11_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF11_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF11_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF11_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF12_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF12_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF12_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF12_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF13_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF13_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF13_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF13_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF14_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF14_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF14_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF14_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF15_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF15_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF15_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF15_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF16_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF16_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF16_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF16_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF17_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF17_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF17_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF17_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF18_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF18_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF18_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF18_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF19_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF19_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF19_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF19_RUSER_POISON_EN_MASK 0x000000FFL +//NBIF_STRAP_BIOS_CNTL +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN__SHIFT 0x0 +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN__SHIFT 0x1 +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN_MASK 0x00000001L +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN_MASK 0x00000002L +//SMN_MST_NORMAL_SECURITY +#define SMN_MST_NORMAL_SECURITY__SMN_MST_NORMAL_RECURITY_SEL__SHIFT 0x0 +#define SMN_MST_NORMAL_SECURITY__SMN_MST_NORMAL_RECURITY_SEL_MASK 0x0000000FL +//OVERRIDE_TYPE_FOR_CHAIN_CTRL +#define OVERRIDE_TYPE_FOR_CHAIN_CTRL__OVERRIDE_TYPE_FOR_CHAIN__SHIFT 0x0 +#define OVERRIDE_TYPE_FOR_CHAIN_CTRL__OVERRIDE_TYPE_FOR_CHAIN_MASK 0x00000001L +//PROCESSING_HINT_SUPPORT_CNTL +#define PROCESSING_HINT_SUPPORT_CNTL__PH_MASK_EN__SHIFT 0x0 +#define PROCESSING_HINT_SUPPORT_CNTL__PH_MASK_EN_MASK 0x00000001L +//DEV0_PF0_VF0_MMIO0_FENCE +#define DEV0_PF0_VF0_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF0_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF0_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF0_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF1_MMIO0_FENCE +#define DEV0_PF0_VF1_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF1_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF1_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF1_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF2_MMIO0_FENCE +#define DEV0_PF0_VF2_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF2_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF2_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF2_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF3_MMIO0_FENCE +#define DEV0_PF0_VF3_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF3_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF3_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF3_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF4_MMIO0_FENCE +#define DEV0_PF0_VF4_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF4_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF4_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF4_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF5_MMIO0_FENCE +#define DEV0_PF0_VF5_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF5_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF5_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF5_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF6_MMIO0_FENCE +#define DEV0_PF0_VF6_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF6_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF6_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF6_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF7_MMIO0_FENCE +#define DEV0_PF0_VF7_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF7_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF7_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF7_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF_MMIO0_FENCE_RANGE0_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE0_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE0_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE0_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE0_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE0_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE1_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE1_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE1_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE1_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE1_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE1_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE2_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE2_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE2_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE2_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE2_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE2_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE3_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE3_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE3_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE3_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE3_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE3_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE4_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE4_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE4_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE4_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE4_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE4_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE5_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE5_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE5_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE5_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE5_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE5_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE6_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE6_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE6_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE6_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE6_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE6_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE7_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE7_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE7_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE7_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE7_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE7_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF0_MMIO0_FENCE +#define DEV0_PF1_VF0_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF1_VF0_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF1_VF0_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF1_VF0_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF1_VF_MMIO0_FENCE_RANGE0_START +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE0_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE0_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF_MMIO0_FENCE_RANGE0_END +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE0_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE0_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF_MMIO0_FENCE_RANGE1_START +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE1_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE1_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF_MMIO0_FENCE_RANGE1_END +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE1_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE1_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF_MMIO0_FENCE_RANGE2_START +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE2_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE2_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF_MMIO0_FENCE_RANGE2_END +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE2_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE2_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF_MMIO0_FENCE_RANGE3_START +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE3_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE3_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF_MMIO0_FENCE_RANGE3_END +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE3_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE3_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_WR +#define DEV0_PF0_PF_MMIO0_FENCE_WR__ENABLE__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_WR__ENABLE_MASK 0xFFFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RD +#define DEV0_PF0_PF_MMIO0_FENCE_RD__ENABLE__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RD__ENABLE_MASK 0xFFFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE0_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE0_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE0_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE0_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE0_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE0_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE1_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE1_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE1_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE1_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE1_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE1_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE2_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE2_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE2_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE2_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE2_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE2_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE3_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE3_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE3_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE3_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE3_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE3_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE4_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE4_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE4_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE4_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE4_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE4_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE5_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE5_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE5_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE5_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE5_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE5_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE6_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE6_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE6_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE6_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE6_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE6_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE7_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE7_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE7_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE7_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE7_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE7_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE8_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE8_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE8_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE8_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE8_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE8_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE9_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE9_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE9_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE9_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE9_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE9_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE10_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE10_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE10_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE10_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE10_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE10_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE11_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE11_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE11_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE11_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE11_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE11_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE12_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE12_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE12_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE12_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE12_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE12_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE13_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE13_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE13_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE13_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE13_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE13_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE14_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE14_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE14_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE14_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE14_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE14_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE15_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE15_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE15_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE15_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE15_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE15_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE16_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE16_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE16_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE16_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE16_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE16_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE17_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE17_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE17_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE17_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE17_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE17_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE18_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE18_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE18_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE18_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE18_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE18_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE19_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE19_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE19_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE19_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE19_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE19_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE20_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE20_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE20_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE20_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE20_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE20_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE21_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE21_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE21_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE21_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE21_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE21_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE22_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE22_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE22_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE22_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE22_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE22_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE23_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE23_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE23_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE23_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE23_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE23_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE24_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE24_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE24_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE24_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE24_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE24_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE25_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE25_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE25_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE25_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE25_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE25_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE26_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE26_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE26_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE26_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE26_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE26_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE27_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE27_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE27_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE27_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE27_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE27_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE28_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE28_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE28_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE28_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE28_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE28_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE29_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE29_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE29_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE29_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE29_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE29_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE30_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE30_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE30_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE30_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE30_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE30_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE31_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE31_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE31_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE31_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE31_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE31_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_WR +#define DEV0_PF1_PF_MMIO0_FENCE_WR__ENABLE__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_WR__ENABLE_MASK 0xFFFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RD +#define DEV0_PF1_PF_MMIO0_FENCE_RD__ENABLE__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RD__ENABLE_MASK 0xFFFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE0_START +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE0_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE0_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE0_END +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE0_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE0_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE1_START +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE1_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE1_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE1_END +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE1_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE1_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE2_START +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE2_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE2_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE2_END +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE2_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE2_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE3_START +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE3_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE3_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE3_END +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE3_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE3_END__ADDRESS_MASK 0x3FFFFFFFL +//MISC_SCRATCH +#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0 +#define MISC_SCRATCH__MISC_SCRATCH0_MASK 0xFFFFFFFFL +//INTR_LINE_POLARITY +#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0 +#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK 0x000000FFL +//INTR_LINE_ENABLE +#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0 +#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK 0x000000FFL +//OUTSTANDING_VC_ALLOC +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10 +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18 +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK 0x00000003L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK 0x0000000CL +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK 0x00000030L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK 0x000000C0L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK 0x00000300L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK 0x00000C00L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK 0x00003000L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK 0x0000C000L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK 0x000F0000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK 0x03000000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK 0x0C000000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK 0xF0000000L +//BIFC_MISC_CTRL0 +#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0 +#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1 +#define BIFC_MISC_CTRL0__REG_ACTIVE_VLINK_L0_EN__SHIFT 0x3 +#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT 0x4 +#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8 +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P__SHIFT 0x9 +#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0xb +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0xc +#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT 0xd +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP__SHIFT 0xe +#define BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE__SHIFT 0xf +#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10 +#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11 +#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT 0x12 +#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT 0x13 +#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT 0x14 +#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN__SHIFT 0x15 +#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN__SHIFT 0x16 +#define BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST__SHIFT 0x17 +#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18 +#define BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST__SHIFT 0x19 +#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a +#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b +#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c +#define BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL__SHIFT 0x1d +#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST__SHIFT 0x1e +#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f +#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK 0x00000001L +#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK 0x00000006L +#define BIFC_MISC_CTRL0__REG_ACTIVE_VLINK_L0_EN_MASK 0x00000008L +#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK 0x000000F0L +#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK 0x00000100L +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P_MASK 0x00000200L +#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK 0x00000400L +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x00000800L +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x00001000L +#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK 0x00002000L +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP_MASK 0x00004000L +#define BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE_MASK 0x00008000L +#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK 0x00010000L +#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK 0x00020000L +#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK 0x00040000L +#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK 0x00080000L +#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK 0x00100000L +#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN_MASK 0x00200000L +#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN_MASK 0x00400000L +#define BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST_MASK 0x00800000L +#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK 0x01000000L +#define BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST_MASK 0x02000000L +#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK 0x04000000L +#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK 0x08000000L +#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK 0x10000000L +#define BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL_MASK 0x20000000L +#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST_MASK 0x40000000L +#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK 0x80000000L +//BIFC_MISC_CTRL1 +#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0 +#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1 +#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2 +#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3 +#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4 +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5 +#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6 +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT 0x7 +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8 +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa +#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe +#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf +#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10 +#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11 +#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12 +#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13 +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT 0x14 +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE__SHIFT 0x15 +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE__SHIFT 0x16 +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG__SHIFT 0x17 +#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT 0x18 +#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT 0x19 +#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT 0x1a +#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT 0x1b +#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT 0x1c +#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT 0x1d +#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x1e +#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK 0x00000001L +#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK 0x00000002L +#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK 0x00000004L +#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK 0x00000008L +#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK 0x00000010L +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK 0x00000020L +#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK 0x00000040L +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK 0x00000080L +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK 0x00000300L +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK 0x00000C00L +#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK 0x00001000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK 0x00002000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK 0x00004000L +#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK 0x00008000L +#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK 0x00010000L +#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK 0x00020000L +#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK 0x00040000L +#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK 0x00080000L +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK 0x00100000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_MASK 0x00200000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE_MASK 0x00400000L +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG_MASK 0x00800000L +#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK 0x01000000L +#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK 0x02000000L +#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK 0x04000000L +#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK 0x08000000L +#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK 0x10000000L +#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK 0x20000000L +#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK 0xC0000000L +//BIFC_BME_ERR_LOG_LB +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0 +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1 +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10 +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11 +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0_MASK 0x00000001L +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1_MASK 0x00000002L +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK 0x00010000L +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK 0x00020000L +//BIFC_LC_TIMER_CTRL +#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE__SHIFT 0x0 +#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE__SHIFT 0x10 +#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE_MASK 0x0000FFFFL +#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE_MASK 0xFFFF0000L +//BIFC_RCCBIH_BME_ERR_LOG0 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1 +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10 +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00000001L +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00000002L +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00010000L +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00020000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK 0xC0000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK 0xC0000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK 0xC0000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK 0xC0000000L +//BIFC_DMA_ATTR_CNTL2_DEV0 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT 0x0 +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F0__SHIFT 0x1 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT 0x4 +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F1__SHIFT 0x5 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT 0x8 +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F2__SHIFT 0x9 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT 0xc +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F3__SHIFT 0xd +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT 0x10 +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F4__SHIFT 0x11 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT 0x14 +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F5__SHIFT 0x15 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT 0x18 +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F6__SHIFT 0x19 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT 0x1c +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F7__SHIFT 0x1d +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK 0x00000001L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F0_MASK 0x00000002L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK 0x00000010L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F1_MASK 0x00000020L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK 0x00000100L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F2_MASK 0x00000200L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK 0x00001000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F3_MASK 0x00002000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK 0x00010000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F4_MASK 0x00020000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK 0x00100000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F5_MASK 0x00200000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK 0x01000000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F6_MASK 0x02000000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK 0x10000000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F7_MASK 0x20000000L +//BIFC_MISC_CTRL2 +#define BIFC_MISC_CTRL2__DIH_INTR_STFETCH_BLOCK_IN_LINKDOWN__SHIFT 0x0 +#define BIFC_MISC_CTRL2__SLOW_GMI_UPS_RSP_CRED_REL_EN__SHIFT 0x1 +#define BIFC_MISC_CTRL2__DMA_RSP_ECRC_REPORT__SHIFT 0x2 +#define BIFC_MISC_CTRL2__SLFR_IGNORE_DATAERR_EN__SHIFT 0x10 +#define BIFC_MISC_CTRL2__DATAERR_OVERRIDE_SLFR_BYTEEN_EN__SHIFT 0x11 +#define BIFC_MISC_CTRL2__PH_SUPPORT__SHIFT 0x12 +#define BIFC_MISC_CTRL2__GMI_FAIL_REQ_RTS_MASK__SHIFT 0x16 +#define BIFC_MISC_CTRL2__NBIF_AERRPT_BACKPERSURE_EN__SHIFT 0x17 +#define BIFC_MISC_CTRL2__DIH_INTR_STFETCH_BLOCK_IN_LINKDOWN_MASK 0x00000001L +#define BIFC_MISC_CTRL2__SLOW_GMI_UPS_RSP_CRED_REL_EN_MASK 0x00000002L +#define BIFC_MISC_CTRL2__DMA_RSP_ECRC_REPORT_MASK 0x00000004L +#define BIFC_MISC_CTRL2__SLFR_IGNORE_DATAERR_EN_MASK 0x00010000L +#define BIFC_MISC_CTRL2__DATAERR_OVERRIDE_SLFR_BYTEEN_EN_MASK 0x00020000L +#define BIFC_MISC_CTRL2__PH_SUPPORT_MASK 0x003C0000L +#define BIFC_MISC_CTRL2__GMI_FAIL_REQ_RTS_MASK_MASK 0x00400000L +#define BIFC_MISC_CTRL2__NBIF_AERRPT_BACKPERSURE_EN_MASK 0x00800000L +//BME_DUMMY_CNTL_0 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK 0x00000003L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK 0x0000000CL +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK 0x00000030L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK 0x000000C0L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK 0x00000300L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK 0x00000C00L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK 0x00003000L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK 0x0000C000L +//BIFC_THT_CNTL +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0 +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4 +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8 +#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x10 +#define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS__SHIFT 0x18 +#define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS__SHIFT 0x19 +#define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS__SHIFT 0x1a +#define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS__SHIFT 0x1b +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK 0x0000000FL +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK 0x000000F0L +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK 0x00000F00L +#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x00010000L +#define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS_MASK 0x01000000L +#define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS_MASK 0x02000000L +#define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS_MASK 0x04000000L +#define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS_MASK 0x08000000L +//BIFC_HSTARB_CNTL +#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0 +#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN__SHIFT 0x8 +#define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK 0x00000003L +#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN_MASK 0x00000100L +//BIFC_GSI_CNTL +#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0 +#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2 +#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x6 +#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x7 +#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x8 +#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x9 +#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0xa +#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xb +#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xd +#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN__SHIFT 0xf +#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK__SHIFT 0x10 +#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN__SHIFT 0x11 +#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN__SHIFT 0x12 +#define BIFC_GSI_CNTL__NBIF_UR_HPHIT_TRANS_DIS_EN__SHIFT 0x16 +#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE__SHIFT 0x1b +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH__SHIFT 0x1c +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH__SHIFT 0x1d +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD__SHIFT 0x1e +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL__SHIFT 0x1f +#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK 0x00000003L +#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK 0x0000003CL +#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK 0x00000040L +#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK 0x00000080L +#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK 0x00000100L +#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK 0x00000200L +#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK 0x00000400L +#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK 0x00001800L +#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK 0x00006000L +#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN_MASK 0x00008000L +#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK_MASK 0x00010000L +#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN_MASK 0x00020000L +#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN_MASK 0x00040000L +#define BIFC_GSI_CNTL__NBIF_UR_HPHIT_TRANS_DIS_EN_MASK 0x00400000L +#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE_MASK 0x08000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH_MASK 0x10000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH_MASK 0x20000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD_MASK 0x40000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL_MASK 0x80000000L +//BIFC_PCIEFUNC_CNTL +#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0 +#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10 +#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK 0x0000FFFFL +#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK 0x00010000L +//BIFC_PASID_CHECK_DIS +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT 0x0 +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT 0x1 +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK 0x00000001L +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK 0x00000002L +//BIFC_SDP_CNTL_0 +#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x8 +#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0x10 +#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x18 +#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK 0x000000FFL +#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK 0x0000FF00L +#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK 0x00FF0000L +#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK 0xFF000000L +//BIFC_SDP_CNTL_1 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT 0x1 +#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT 0x2 +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT 0x3 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x4 +#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P__SHIFT 0x5 +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x7 +#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN__SHIFT 0x8 +#define BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x9 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK 0x00000001L +#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK 0x00000002L +#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK 0x00000004L +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK 0x00000008L +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000010L +#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P_MASK 0x00000020L +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000080L +#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN_MASK 0x00000100L +#define BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00000200L +//BIFC_PASID_STS +#define BIFC_PASID_STS__PASID_STS__SHIFT 0x0 +#define BIFC_PASID_STS__PASID_STS_MASK 0x0000000FL +//BIFC_ATHUB_ACT_CNTL +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT 0x0 +#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE__SHIFT 0x3 +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT 0x8 +#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT 0x9 +#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT 0xa +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN__SHIFT 0xb +#define BIFC_ATHUB_ACT_CNTL__ERREVENT_MODE1RST_FLUSH_LOG_AER_EN__SHIFT 0xc +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK 0x00000007L +#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE_MASK 0x00000038L +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK 0x00000100L +#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER_MASK 0x00000200L +#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER_MASK 0x00000400L +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN_MASK 0x00000800L +#define BIFC_ATHUB_ACT_CNTL__ERREVENT_MODE1RST_FLUSH_LOG_AER_EN_MASK 0x00001000L +//BIFC_PERF_CNTL_0 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK 0x00000001L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK 0x00000002L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK 0x00000100L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK 0x00000200L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK 0x007F0000L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK 0x7F000000L +//BIF_MISC_BIFC_PERF_CNTL_1 +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0 +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1 +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x4 +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x5 +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x8 +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x10 +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK 0x00000001L +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK 0x00000002L +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK 0x00000010L +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK 0x00000020L +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK 0x0000FF00L +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK 0x03FF0000L +//BIFC_PERF_CNT_MMIO_RD_L32BIT +#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIFC_PERF_CNT_MMIO_WR_L32BIT +#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT +#define BIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT__SHIFT 0x0 +#define BIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT +#define BIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT__SHIFT 0x0 +#define BIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT_MASK 0xFFFFFFFFL +//NBIF_REGIF_ERRSET_CTRL +#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +//BIFC_SDP_CNTL_2 +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H__SHIFT 0x8 +#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H__SHIFT 0x10 +#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H__SHIFT 0x18 +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_MASK 0x000000FFL +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H_MASK 0x00000F00L +#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H_MASK 0x000F0000L +#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H_MASK 0x0F000000L +//NBIF_PGMST_CTRL +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT 0x0 +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT 0x8 +#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT 0xe +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK 0x00000100L +#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L +//NBIF_PGSLV_CTRL +#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT 0x0 +#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK 0x0000001FL +//NBIF_PG_MISC_CTRL +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0 +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5 +#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT 0xa +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1__SHIFT 0xd +#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT 0xe +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2__SHIFT 0x10 +#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 +#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK__SHIFT 0x1e +#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L +#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK 0x00000400L +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1_MASK 0x00002000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK 0x00004000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2_MASK 0x00010000L +#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK_MASK 0x40000000L +#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L +//SMN_MST_EP_CNTL3 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK 0x00000080L +//SMN_MST_EP_CNTL4 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK 0x00000080L +//SMN_MST_CNTL1 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT 0x0 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT 0x10 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK 0x00000001L +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK 0x00010000L +//SMN_MST_EP_CNTL5 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK 0x00000080L +//BIF_SELFRING_BUFFER_VID +#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0 +#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT 0x8 +#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT 0x10 +#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK 0x000000FFL +#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK 0x0000FF00L +#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK 0x00FF0000L +//BIF_SELFRING_VECTOR_CNTL +#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0 +#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT 0x1 +#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK 0x00000001L +#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK 0x00000002L +//HDP_ERR_STATUS_EXT +#define HDP_ERR_STATUS_EXT__HDP_ERR_STATUS_WR_EXT__SHIFT 0x0 +#define HDP_ERR_STATUS_EXT__HDP_ERR_STATUS_RD_EXT__SHIFT 0x1 +#define HDP_ERR_STATUS_EXT__HDP_ERR_STATUS_WR_EXT_MASK 0x00000001L +#define HDP_ERR_STATUS_EXT__HDP_ERR_STATUS_RD_EXT_MASK 0x00000002L +//NBIF_STRAP_WRITE_CTRL +#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x0 +#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK 0x00000001L +//NBIF_INTX_DSTATE_MISC_CNTL +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x0 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x1 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x2 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x3 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x4 +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT 0x5 +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT 0x6 +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x7 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00000001L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00000002L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00000004L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00000008L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00000010L +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK 0x00000020L +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK 0x00000040L +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000080L +//NBIF_PENDING_MISC_CNTL +#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT 0x0 +#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT 0x1 +#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK 0x00000001L +#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK 0x00000002L +//BIF_GMI_WRR_WEIGHT +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE__SHIFT 0x1d +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE__SHIFT 0x1e +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE__SHIFT 0x1f +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE_MASK 0x20000000L +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE_MASK 0x40000000L +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE_MASK 0x80000000L +//BIF_GMI_WRR_WEIGHT2 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT 0x0 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT 0x8 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT 0x10 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT 0x18 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK 0x000000FFL +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK 0x0000FF00L +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK 0x00FF0000L +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK 0xFF000000L +//BIF_GMI_WRR_WEIGHT3 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT 0x0 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT 0x8 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT 0x10 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT 0x18 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK 0x000000FFL +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK 0x0000FF00L +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK 0x00FF0000L +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK 0xFF000000L +//BIF_GMI_WRR_WEIGHT4 +#define BIF_GMI_WRR_WEIGHT4__GMI_REQ_ENTRY8_WEIGHT__SHIFT 0x0 +#define BIF_GMI_WRR_WEIGHT4__GMI_REQ_ENTRY8_WEIGHT_MASK 0x000000FFL +//NBIF_PWRBRK_REQUEST +#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT 0x0 +#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK 0x00000001L +//BIF_ATOMIC_ERR_LOG_DEV0_F0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x2 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT 0x3 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x10 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x11 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x12 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT 0x13 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00000001L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00000002L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00000004L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK 0x00000008L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00010000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00020000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00040000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK 0x00080000L +//BIF_ATOMIC_ERR_LOG_DEV0_F1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x2 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT 0x3 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x10 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x11 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x12 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT 0x13 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00000001L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00000002L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00000004L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK 0x00000008L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00010000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00020000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00040000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK 0x00080000L +//BIF_DMA_MP4_ERR_LOG +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x0 +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x1 +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x10 +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x11 +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK 0x00000001L +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00000002L +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK 0x00010000L +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00020000L +//BIF_PASID_ERR_LOG +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT 0x0 +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT 0x1 +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK 0x00000001L +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK 0x00000002L +//BIF_PASID_ERR_CLR +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT 0x0 +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT 0x1 +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK 0x00000001L +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK 0x00000002L +//NBIF_VWIRE_CTRL +#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT 0x0 +#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4 +#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8 +#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT 0x10 +#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14 +#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a +#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK 0x00000001L +#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK 0x000000F0L +#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK 0x00000100L +#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK 0x00010000L +#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK 0x00F00000L +#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK 0x0C000000L +//NBIF_MGCG_CTRL_LCLK +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT 0x0 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT 0x1 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT 0x2 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT 0xa +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT 0xb +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT 0xc +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT 0xd +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DBG_DIS_LCLK__SHIFT 0xe +#define NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK__SHIFT 0xf +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK 0x00000001L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK 0x00000002L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK 0x000003FCL +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK 0x00000400L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK 0x00000800L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK 0x00002000L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DBG_DIS_LCLK_MASK 0x00004000L +#define NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK_MASK 0x00008000L +//NBIF_DS_CTRL_LCLK +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0 +#define NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10 +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK 0x00000001L +#define NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK 0xFFFF0000L +//SMN_MST_CNTL0 +#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0 +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8 +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9 +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10 +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14 +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18 +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c +#define SMN_MST_CNTL0__SMN_ARB_MODE_MASK 0x00000003L +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK 0x00000100L +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK 0x00000200L +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK 0x00000400L +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK 0x00000800L +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK 0x00010000L +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK 0x00100000L +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK 0x01000000L +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK 0x10000000L +//SMN_MST_EP_CNTL1 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK 0x00000080L +//SMN_MST_EP_CNTL2 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK 0x00000080L +//NBIF_SDP_VWR_VCHG_DIS_CTRL +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_RST_CTRL0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_RST_CTRL1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_TRIG +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK 0x01000000L +//NBIO_LCLK_DEEPSLEEP_MASK +#define NBIO_LCLK_DEEPSLEEP_MASK__LCLK_DS_MASK__SHIFT 0x0 +#define NBIO_LCLK_DEEPSLEEP_MASK__LCLK_DS_MASK_MASK 0xFFFFFFFFL +//NBIF_DS_CTRL_USBCLK +#define NBIF_DS_CTRL_USBCLK__NBIF_USBCLK_DS_EN__SHIFT 0x0 +#define NBIF_DS_CTRL_USBCLK__USB_USBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +#define NBIF_DS_CTRL_USBCLK__NBIF_USBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 +#define NBIF_DS_CTRL_USBCLK__NBIF_USBCLK_DS_EN_MASK 0x00000001L +#define NBIF_DS_CTRL_USBCLK__USB_USBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L +#define NBIF_DS_CTRL_USBCLK__NBIF_USBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L +//NBIF_SHUB_TODET_CLIENT_MISC3 +#define NBIF_SHUB_TODET_CLIENT_MISC3__NBIF_SHUB_TODET_SLVERR_EN3__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_MISC3__NBIF_SHUB_TODET_SYNCFLOOD_EN3__SHIFT 0xa +#define NBIF_SHUB_TODET_CLIENT_MISC3__NBIF_SHUB_TODET_SLVERR_EN3_MASK 0x000003FFL +#define NBIF_SHUB_TODET_CLIENT_MISC3__NBIF_SHUB_TODET_SYNCFLOOD_EN3_MASK 0x000FFC00L +//NBIF_SHUB_TODET_CTRL +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN__SHIFT 0x0 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN__SHIFT 0x1 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT__SHIFT 0x8 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT__SHIFT 0x10 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN_MASK 0x00000001L +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN_MASK 0x00000002L +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT_MASK 0x00000700L +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT_MASK 0xFFFF0000L +//NBIF_SHUB_TODET_CLIENT_CTRL +#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_CLIENT_STATUS +#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_SYNCFLOOD_CTRL +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN__SHIFT 0x0 +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_CLIENT_CTRL2 +#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_CLIENT_STATUS2 +#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_SYNCFLOOD_CTRL2 +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2__SHIFT 0x0 +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2_MASK 0xFFFFFFFFL +//DMA_SDP_PORT_DEBUG +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_REQ_CREDIT_RDY_FOR_VC__SHIFT 0x0 +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_DAT_CREDIT_RDY_FOR_VC__SHIFT 0x8 +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_RDRSP_CREDIT_VLD_FOR_VC__SHIFT 0x10 +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_WRRSP_CREDIT_VLD_FOR_VC__SHIFT 0x18 +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_REQ_CREDIT_RDY_FOR_VC_MASK 0x000000FFL +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_DAT_CREDIT_RDY_FOR_VC_MASK 0x0000FF00L +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_RDRSP_CREDIT_VLD_FOR_VC_MASK 0x00FF0000L +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_WRRSP_CREDIT_VLD_FOR_VC_MASK 0xFF000000L +//SDP_PORT_MONITOR_CONTROL +#define SDP_PORT_MONITOR_CONTROL__DMA_SDP_PORT_MONITOR_EN__SHIFT 0x0 +#define SDP_PORT_MONITOR_CONTROL__HST_SDP_PORT_MONITOR_EN__SHIFT 0x1 +#define SDP_PORT_MONITOR_CONTROL__SDP_PORT_MONITOR_ADDRESS_EN__SHIFT 0x2 +#define SDP_PORT_MONITOR_CONTROL__SDP_PORT_MONITOR_UNITID_EN__SHIFT 0x3 +#define SDP_PORT_MONITOR_CONTROL__DMA_SDP_PORT_MONITOR_EN_MASK 0x00000001L +#define SDP_PORT_MONITOR_CONTROL__HST_SDP_PORT_MONITOR_EN_MASK 0x00000002L +#define SDP_PORT_MONITOR_CONTROL__SDP_PORT_MONITOR_ADDRESS_EN_MASK 0x00000004L +#define SDP_PORT_MONITOR_CONTROL__SDP_PORT_MONITOR_UNITID_EN_MASK 0x00000008L +//SDP_PORT_MONITOR_ADDRESS0 +#define SDP_PORT_MONITOR_ADDRESS0__SDP_PORT_MONITOR_ADDRESS0__SHIFT 0x0 +#define SDP_PORT_MONITOR_ADDRESS0__SDP_PORT_MONITOR_ADDRESS0_MASK 0xFFFFFFFFL +//SDP_PORT_MONITOR_ADDRESS1 +#define SDP_PORT_MONITOR_ADDRESS1__SDP_PORT_MONITOR_ADDRESS1__SHIFT 0x0 +#define SDP_PORT_MONITOR_ADDRESS1__SDP_PORT_MONITOR_ADDRESS1_MASK 0xFFFFFFFFL +//SDP_PORT_MONITOR_UNITID +#define SDP_PORT_MONITOR_UNITID__SDP_PORT_MONITOR_UNITID__SHIFT 0x0 +#define SDP_PORT_MONITOR_UNITID__SDP_PORT_MONITOR_UNITID_MASK 0x000007FFL +//SDP_PORT_MONITOR_INFO0 +#define SDP_PORT_MONITOR_INFO0__SDP_PORT_MONITOR_INFO_ADDRESS0__SHIFT 0x0 +#define SDP_PORT_MONITOR_INFO0__SDP_PORT_MONITOR_INFO_ADDRESS0_MASK 0xFFFFFFFFL +//SDP_PORT_MONITOR_INFO1 +#define SDP_PORT_MONITOR_INFO1__SDP_PORT_MONITOR_INFO_ADDRESS1__SHIFT 0x0 +#define SDP_PORT_MONITOR_INFO1__SDP_PORT_MONITOR_INFO_ADDRESS1_MASK 0xFFFFFFFFL +//SDP_PORT_MONITOR_INFO2 +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_BLOCKLEVEL__SHIFT 0x0 +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_CHAIN__SHIFT 0x2 +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_CMD__SHIFT 0x3 +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_IO__SHIFT 0x9 +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_PASSPW__SHIFT 0xa +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_RSPPASSPW__SHIFT 0xb +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_SECLEVEL__SHIFT 0xc +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_STREAMID__SHIFT 0x10 +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_BLOCKLEVEL_MASK 0x00000003L +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_CHAIN_MASK 0x00000004L +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_CMD_MASK 0x000001F8L +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_IO_MASK 0x00000200L +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_PASSPW_MASK 0x00000400L +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_RSPPASSPW_MASK 0x00000800L +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_SECLEVEL_MASK 0x0000F000L +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_STREAMID_MASK 0xFFFF0000L +//SDP_PORT_MONITOR_INFO3 +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_TAG__SHIFT 0x0 +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_UNITID__SHIFT 0xc +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_VC__SHIFT 0x17 +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_LEN__SHIFT 0x1a +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_TAG_MASK 0x00000FFFL +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_UNITID_MASK 0x007FF000L +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_VC_MASK 0x03800000L +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_LEN_MASK 0xFC000000L +//SDP_PORT_MONITOR_INFO4 +#define SDP_PORT_MONITOR_INFO4__SDP_PORT_MONITOR_INFO_ATTR__SHIFT 0x0 +#define SDP_PORT_MONITOR_INFO4__SDP_PORT_MONITOR_INFO_ATTR_MASK 0x000000FFL +//BIFC_BME_ERR_LOG_HB +//BIFC_GFX_INT_MONITOR_MASK +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_CTRL_MASK__SHIFT 0x0 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_ADDR_MASK__SHIFT 0x1 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_UPADDR_MASK__SHIFT 0x2 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_DATA_MASK__SHIFT 0x3 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_EDATA_MASK__SHIFT 0x4 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_ADDR_MASK__SHIFT 0x5 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_UPADDR_MASK__SHIFT 0x6 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_DATA_MASK__SHIFT 0x7 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_VEC_MASK__SHIFT 0x8 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_PEND_MASK__SHIFT 0x9 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_CTRL_MASK__SHIFT 0xa +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_CTRL_MASK_MASK 0x00000001L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_ADDR_MASK_MASK 0x00000002L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_UPADDR_MASK_MASK 0x00000004L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_DATA_MASK_MASK 0x00000008L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_EDATA_MASK_MASK 0x00000010L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_ADDR_MASK_MASK 0x00000020L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_UPADDR_MASK_MASK 0x00000040L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_DATA_MASK_MASK 0x00000080L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_VEC_MASK_MASK 0x00000100L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_PEND_MASK_MASK 0x00000200L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_CTRL_MASK_MASK 0x00000400L +//BIFC_GFX_INT_MONITOR_STS +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_CTRL_STS__SHIFT 0x0 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_ADDR_STS__SHIFT 0x1 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_UPADDR_STS__SHIFT 0x2 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_DATA_STS__SHIFT 0x3 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_EDATA_STS__SHIFT 0x4 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_ADDR_STS__SHIFT 0x5 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_UPADDR_STS__SHIFT 0x6 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_DATA_STS__SHIFT 0x7 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_VEC_STS__SHIFT 0x8 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_PEND_STS__SHIFT 0x9 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_CTRL_STS__SHIFT 0xa +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_CTRL_STS_MASK 0x00000001L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_ADDR_STS_MASK 0x00000002L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_UPADDR_STS_MASK 0x00000004L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_DATA_STS_MASK 0x00000008L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_EDATA_STS_MASK 0x00000010L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_ADDR_STS_MASK 0x00000020L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_UPADDR_STS_MASK 0x00000040L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_DATA_STS_MASK 0x00000080L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_VEC_STS_MASK 0x00000100L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_PEND_STS_MASK 0x00000200L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_CTRL_STS_MASK 0x00000400L +//BIFC_GFX_INT_MONITOR_CTRL +#define BIFC_GFX_INT_MONITOR_CTRL__GFX_INT_MONITOR_VEC_SEL__SHIFT 0x0 +#define BIFC_GFX_INT_MONITOR_CTRL__GFX_INT_MONITOR_VEC_SEL_MASK 0x0000000FL +//NBIF_FLUSH_CTRL +#define NBIF_FLUSH_CTRL__GMI_FLUSH_OT_ENABLE__SHIFT 0x0 +#define NBIF_FLUSH_CTRL__GSI_FLUSH_OT_ENABLE__SHIFT 0x1 +#define NBIF_FLUSH_CTRL__FLUSH_ADD_BUBBLE_EN__SHIFT 0x3 +#define NBIF_FLUSH_CTRL__FLUSH_ADD_BUBBLE_SEL__SHIFT 0x4 +#define NBIF_FLUSH_CTRL__NBIF_GRP1_RW_OT_SWITCH__SHIFT 0x6 +#define NBIF_FLUSH_CTRL__GMI_FLUSH_OT_ENABLE_MASK 0x00000001L +#define NBIF_FLUSH_CTRL__GSI_FLUSH_OT_ENABLE_MASK 0x00000002L +#define NBIF_FLUSH_CTRL__FLUSH_ADD_BUBBLE_EN_MASK 0x00000008L +#define NBIF_FLUSH_CTRL__FLUSH_ADD_BUBBLE_SEL_MASK 0x00000030L +#define NBIF_FLUSH_CTRL__NBIF_GRP1_RW_OT_SWITCH_MASK 0x00000040L +//NBIF_GUI_FLUSH_CNTL +#define NBIF_GUI_FLUSH_CNTL__NBIF_GUI_FLUSH_REQ_MERGE__SHIFT 0x0 +#define NBIF_GUI_FLUSH_CNTL__NBIF_GUI_FLUSH_REQ_MERGE_MASK 0x00000001L +//BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +//BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +//BIFC_GMI_SDP_REQ_POOLCRED_ALLOC +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//BIFC_GMI_SDP_DAT_POOLCRED_ALLOC +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//DISCON_HYSTERESIS_HEAD_CTRL +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x0 +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x8 +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H_MASK 0x0000000FL +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H_MASK 0x00000F00L +//BIFC_GSI_SDP_REQ_POOLCRED_ALLOC +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//BIFC_GSI_SDP_DAT_POOLCRED_ALLOC +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//BIFC_MCA_SMN_CTRL0 +#define BIFC_MCA_SMN_CTRL0__MCA_SMN_POSTED__SHIFT 0x0 +#define BIFC_MCA_SMN_CTRL0__MCA_SMN_POSTED_MASK 0x00000001L +//BIFC_MCTP_SMN_CTRL0 +#define BIFC_MCTP_SMN_CTRL0__MCTP_SMN_POSTED__SHIFT 0x0 +#define BIFC_MCTP_SMN_CTRL0__MCTP_SMN_POSTED_MASK 0x00000001L +//NBIF_REGIF_DEBUG_COUNTER_CTRL +//BIFC_EARLY_WAKEUP_CNTL +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0 +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1 +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2 +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L +//BIFC_PERF_CNT_MMIO_RD_H16BIT +#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT_MASK 0x0000FFFFL +//BIFC_PERF_CNT_MMIO_WR_H16BIT +#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT_MASK 0x0000FFFFL +//BIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT +#define BIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT__SHIFT 0x0 +#define BIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT_MASK 0x0000FFFFL +//BIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT +#define BIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT__SHIFT 0x0 +#define BIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT_MASK 0x0000FFFFL +//BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__NBIF_COM_COUNT_ENABLE__SHIFT 0x0 +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__START_COUNT_NOPULS__SHIFT 0x3 +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__LEGACY_OUT_REALTIME_SEL__SHIFT 0x4 +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__PERF_CNT_TRIG_MONI_SEL__SHIFT 0x5 +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__NBIF_COM_COUNT_ENABLE_MASK 0x00000001L +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__START_COUNT_NOPULS_MASK 0x00000008L +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__LEGACY_OUT_REALTIME_SEL_MASK 0x00000010L +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__PERF_CNT_TRIG_MONI_SEL_MASK 0x00000060L +//BIF_MISC_NBIF_SDP_PERF_CNT_FSM +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_SHADOW_TGL_DELAY_COUNT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_PERF_RESET_TGL_DELAY_COUNT__SHIFT 0x4 +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_PERF_RESET_TGL_DELAY_EN__SHIFT 0x8 +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PRE_FLD_GLOBAL_SHADOW_WR__SHIFT 0x9 +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT_DONE__SHIFT 0xa +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT0_RESET__SHIFT 0xb +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT1_RESET__SHIFT 0xc +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT2_RESET__SHIFT 0xd +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT3_RESET__SHIFT 0xe +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_REQ_UNIT_ID__SHIFT 0xf +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_SHADOW_TGL_DELAY_COUNT_MASK 0x0000000FL +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_PERF_RESET_TGL_DELAY_COUNT_MASK 0x000000F0L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_PERF_RESET_TGL_DELAY_EN_MASK 0x00000100L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PRE_FLD_GLOBAL_SHADOW_WR_MASK 0x00000200L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT_DONE_MASK 0x00000400L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT0_RESET_MASK 0x00000800L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT1_RESET_MASK 0x00001000L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT2_RESET_MASK 0x00002000L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT3_RESET_MASK 0x00004000L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_REQ_UNIT_ID_MASK 0x03FF8000L +//BIF_MISC_NBIF_SDP_PERF_COUNTER +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_0_EN__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_1_EN__SHIFT 0x1 +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_2_EN__SHIFT 0x2 +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_3_EN__SHIFT 0x3 +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_0_SEL__SHIFT 0x4 +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_1_SEL__SHIFT 0xb +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_2_SEL__SHIFT 0x12 +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_3_SEL__SHIFT 0x19 +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_0_EN_MASK 0x00000001L +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_1_EN_MASK 0x00000002L +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_2_EN_MASK 0x00000004L +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_3_EN_MASK 0x00000008L +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_0_SEL_MASK 0x000007F0L +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_1_SEL_MASK 0x0003F800L +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_2_SEL_MASK 0x01FC0000L +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_3_SEL_MASK 0xFE000000L +//BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT__SDP_PERF_CNT_0_VALUE_L32BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT__SDP_PERF_CNT_0_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT__SDP_PERF_CNT_1_VALUE_L32BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT__SDP_PERF_CNT_1_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT__SDP_PERF_CNT_2_VALUE_L32BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT__SDP_PERF_CNT_2_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT__SDP_PERF_CNT_3_VALUE_L32BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT__SDP_PERF_CNT_3_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT__SDP_PERF_CNT_0_VALUE_H16BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT__SDP_PERF_CNT_0_VALUE_H16BIT_MASK 0x0000FFFFL +//BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT__SDP_PERF_CNT_1_VALUE_H16BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT__SDP_PERF_CNT_1_VALUE_H16BIT_MASK 0x0000FFFFL +//BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT__SDP_PERF_CNT_2_VALUE_H16BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT__SDP_PERF_CNT_2_VALUE_H16BIT_MASK 0x0000FFFFL +//BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT__SDP_PERF_CNT_3_VALUE_H16BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT__SDP_PERF_CNT_3_VALUE_H16BIT_MASK 0x0000FFFFL +//BIF_MISC_NBIF_BX_PERF_CNT_FSM +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_SHADOW_TGL_DELAY_COUNT__SHIFT 0x0 +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_COUNT__SHIFT 0x4 +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_EN__SHIFT 0x8 +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_PRE_FLD_GLOBAL_SHADOW_WR__SHIFT 0x9 +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_PERF_CNT_DONE__SHIFT 0xa +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_SHADOW_TGL_DELAY_COUNT_MASK 0x0000000FL +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_COUNT_MASK 0x000000F0L +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_EN_MASK 0x00000100L +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_PRE_FLD_GLOBAL_SHADOW_WR_MASK 0x00000200L +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_PERF_CNT_DONE_MASK 0x00000400L +//NBIF_TDISP_ENTER_ERR_CNTL +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_POISONEDTLP_EN__SHIFT 0x0 +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_UR_EN__SHIFT 0x1 +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_CA_EN__SHIFT 0x2 +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_TO_EN__SHIFT 0x3 +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_POISONEDTLP_EN_MASK 0x00000001L +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_UR_EN_MASK 0x00000002L +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_CA_EN_MASK 0x00000004L +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_TO_EN_MASK 0x00000008L +//BIF_UNITID_ERR_LOG +#define BIF_UNITID_ERR_LOG__UR_UNITID_athub__SHIFT 0x0 +#define BIF_UNITID_ERR_LOG__CLEAR_UR_UNITID_athub__SHIFT 0x10 +#define BIF_UNITID_ERR_LOG__UR_UNITID_athub_MASK 0x00000001L +#define BIF_UNITID_ERR_LOG__CLEAR_UR_UNITID_athub_MASK 0x00010000L +//NBIF_COM_COUNT_VALUE +#define NBIF_COM_COUNT_VALUE__NBIF_COM_COUNT_VALUE__SHIFT 0x0 +#define NBIF_COM_COUNT_VALUE__NBIF_COM_COUNT_VALUE_MASK 0xFFFFFFFFL +//NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT0_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x0 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT1_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x1 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT2_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x2 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT3_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x3 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT4_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x4 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT5_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x5 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT6_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x6 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT7_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x7 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT0_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000001L +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT1_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000002L +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT2_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000004L +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT3_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000008L +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT4_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000010L +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT5_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000020L +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT6_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000040L +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT7_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000080L +//NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT0_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x0 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT1_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x1 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT2_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x2 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT3_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x3 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT4_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x4 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT5_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x5 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT6_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x6 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT7_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x7 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT0_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000001L +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT1_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000002L +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT2_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000004L +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT3_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000008L +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT4_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000010L +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT5_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000020L +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT6_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000040L +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT7_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000080L +//BIF_AER_CNTL +#define BIF_AER_CNTL__BIF_AER_VF_NUM__SHIFT 0x0 +#define BIF_AER_CNTL__BIF_AER_PF_NUM__SHIFT 0x8 +#define BIF_AER_CNTL__BIF_AER_ERR_PTR__SHIFT 0xb +#define BIF_AER_CNTL__BIF_AER_HeaderStoreOffset__SHIFT 0x10 +#define BIF_AER_CNTL__BIF_AER_ERR_MSG_TYPE__SHIFT 0x18 +#define BIF_AER_CNTL__BIF_AER_DEVERR__SHIFT 0x1a +#define BIF_AER_CNTL__BIF_AER_POSTED__SHIFT 0x1b +#define BIF_AER_CNTL__BIF_AER_TOTAL_OF_PF__SHIFT 0x1c +#define BIF_AER_CNTL__BIF_AER_VF_HIT__SHIFT 0x1f +#define BIF_AER_CNTL__BIF_AER_VF_NUM_MASK 0x000000FFL +#define BIF_AER_CNTL__BIF_AER_PF_NUM_MASK 0x00000700L +#define BIF_AER_CNTL__BIF_AER_ERR_PTR_MASK 0x0000F800L +#define BIF_AER_CNTL__BIF_AER_HeaderStoreOffset_MASK 0x00FF0000L +#define BIF_AER_CNTL__BIF_AER_ERR_MSG_TYPE_MASK 0x03000000L +#define BIF_AER_CNTL__BIF_AER_DEVERR_MASK 0x04000000L +#define BIF_AER_CNTL__BIF_AER_POSTED_MASK 0x08000000L +#define BIF_AER_CNTL__BIF_AER_TOTAL_OF_PF_MASK 0x70000000L +#define BIF_AER_CNTL__BIF_AER_VF_HIT_MASK 0x80000000L +//NBIF_IDE_INFO_CNTL +#define NBIF_IDE_INFO_CNTL__NBIF_PRGR_MSG_IDE_INFO_FROM_DATA_EN__SHIFT 0x0 +#define NBIF_IDE_INFO_CNTL__NBIF_PRGR_MSG_IDE_INFO_FROM_DATA_EN_MASK 0x00000001L +//BIFC_EXP_MISC_CTRL0 +#define BIFC_EXP_MISC_CTRL0__VC0_DMA_IOCFG_DIS__SHIFT 0x0 +#define BIFC_EXP_MISC_CTRL0__VC1_DMA_IOCFG_DIS__SHIFT 0x1 +#define BIFC_EXP_MISC_CTRL0__VC2_DMA_IOCFG_DIS__SHIFT 0x2 +#define BIFC_EXP_MISC_CTRL0__VC3_DMA_IOCFG_DIS__SHIFT 0x3 +#define BIFC_EXP_MISC_CTRL0__VC4_DMA_IOCFG_DIS__SHIFT 0x4 +#define BIFC_EXP_MISC_CTRL0__VC5_DMA_IOCFG_DIS__SHIFT 0x5 +#define BIFC_EXP_MISC_CTRL0__VC6_DMA_IOCFG_DIS__SHIFT 0x6 +#define BIFC_EXP_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x7 +#define BIFC_EXP_MISC_CTRL0__VC0_DMA_IOCFG_DIS_MASK 0x00000001L +#define BIFC_EXP_MISC_CTRL0__VC1_DMA_IOCFG_DIS_MASK 0x00000002L +#define BIFC_EXP_MISC_CTRL0__VC2_DMA_IOCFG_DIS_MASK 0x00000004L +#define BIFC_EXP_MISC_CTRL0__VC3_DMA_IOCFG_DIS_MASK 0x00000008L +#define BIFC_EXP_MISC_CTRL0__VC4_DMA_IOCFG_DIS_MASK 0x00000010L +#define BIFC_EXP_MISC_CTRL0__VC5_DMA_IOCFG_DIS_MASK 0x00000020L +#define BIFC_EXP_MISC_CTRL0__VC6_DMA_IOCFG_DIS_MASK 0x00000040L +#define BIFC_EXP_MISC_CTRL0__VC7_DMA_IOCFG_DIS_MASK 0x00000080L +//SECOND_HDP_MEM_FLUSH_CNTL_PF +#define SECOND_HDP_MEM_FLUSH_CNTL_PF__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_PF__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF0 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF0__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF0__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF1 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF1__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF1__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF2__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF2__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF3 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF3__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF3__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF4 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF4__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF4__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF5 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF5__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF5__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF6 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF6__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF6__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF7 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF7__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF7__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_PF +#define SECOND_HDP_REG_FLUSH_CNTL_PF__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_PF__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF0 +#define SECOND_HDP_REG_FLUSH_CNTL_VF0__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF0__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF1 +#define SECOND_HDP_REG_FLUSH_CNTL_VF1__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF1__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF2__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF2__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF3 +#define SECOND_HDP_REG_FLUSH_CNTL_VF3__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF3__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF4 +#define SECOND_HDP_REG_FLUSH_CNTL_VF4__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF4__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF5 +#define SECOND_HDP_REG_FLUSH_CNTL_VF5__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF5__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF6 +#define SECOND_HDP_REG_FLUSH_CNTL_VF6__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF6__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF7 +#define SECOND_HDP_REG_FLUSH_CNTL_VF7__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF7__ADDRESS_MASK 0x0007FFFCL +//GPU_HDP_FLUSH_GFX_FW +#define GPU_HDP_FLUSH_GFX_FW__CLEAR_ALL_VF_FLUSH_DONE__SHIFT 0x0 +#define GPU_HDP_FLUSH_GFX_FW__CLEAR_ALL_VF_FLUSH_DONE_MASK 0x00000001L +//NBIF_RRMT_CNTL +#define NBIF_RRMT_CNTL__PARTITION_MODE__SHIFT 0x0 +#define NBIF_RRMT_CNTL__AID_DIE_ID__SHIFT 0x4 +#define NBIF_RRMT_CNTL__RRMT_ENABLE__SHIFT 0x8 +#define NBIF_RRMT_CNTL__RRMT_Invalid_Address_H__SHIFT 0x10 +#define NBIF_RRMT_CNTL__PARTITION_MODE_MASK 0x00000007L +#define NBIF_RRMT_CNTL__AID_DIE_ID_MASK 0x00000030L +#define NBIF_RRMT_CNTL__RRMT_ENABLE_MASK 0x00000100L +#define NBIF_RRMT_CNTL__RRMT_Invalid_Address_H_MASK 0xFFFF0000L +//RRMT_NBIF_MISC_REG1 +#define RRMT_NBIF_MISC_REG1__RRMT_Invalid_Address_L__SHIFT 0x0 +#define RRMT_NBIF_MISC_REG1__RRMT_Invalid_Address_L_MASK 0xFFFFFFFFL +//RRMT_LUT_INDEX +#define RRMT_LUT_INDEX__RRMT_LUT_INDEX__SHIFT 0x0 +#define RRMT_LUT_INDEX__RRMT_LUT_INDEX_MASK 0x000003FFL +//RRMT_LUT_DATA +#define RRMT_LUT_DATA__RRMT_LUT_DATA__SHIFT 0x0 +#define RRMT_LUT_DATA__RRMT_LUT_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_misc_pfvf_dev0_epf0_bif_misc_pfvf_regblk +//BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF127_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_bif_misc_pfvf_dev0_epf1_bif_misc_pfvf_regblk +//BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF127_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_bif_trap_bif_trap_regblk +//NBIF_TRAP_NP_STATUS +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapReqValid__SHIFT 0x0 +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapNumber__SHIFT 0x8 +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapS2Vld__SHIFT 0xc +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapS2Number__SHIFT 0x10 +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapReqValid_MASK 0x00000001L +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapNumber_MASK 0x00000F00L +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapS2Vld_MASK 0x00001000L +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapS2Number_MASK 0x01FF0000L +//NBIF_TRAP_NP_REQUEST0 +#define NBIF_TRAP_NP_REQUEST0__NBIF_TRAP_NP_TrapReqAddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_REQUEST0__NBIF_TRAP_NP_TrapReqAddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_REQUEST1 +#define NBIF_TRAP_NP_REQUEST1__NBIF_TRAP_NP_TrapReqAddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST1__NBIF_TRAP_NP_TrapReqAddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST2 +#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqCmd__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqAttr__SHIFT 0x8 +#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqLen__SHIFT 0x10 +#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqCmd_MASK 0x0000003FL +#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqAttr_MASK 0x0000FF00L +#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqLen_MASK 0x003F0000L +//NBIF_TRAP_NP_REQUEST3 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqVC__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqBlockLevel__SHIFT 0x4 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqChain__SHIFT 0x6 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqIO__SHIFT 0x7 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqPassPW__SHIFT 0x8 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqRspPassPW__SHIFT 0x9 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqUnitID__SHIFT 0x10 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqVC_MASK 0x00000007L +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqBlockLevel_MASK 0x00000030L +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqChain_MASK 0x00000040L +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqIO_MASK 0x00000080L +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqPassPW_MASK 0x00000100L +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqRspPassPW_MASK 0x00000200L +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqUnitID_MASK 0x07FF0000L +//NBIF_TRAP_NP_REQUEST4 +#define NBIF_TRAP_NP_REQUEST4__NBIF_TRAP_NP_TrapReqSecLevel__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST4__NBIF_TRAP_NP_TrapReqSecLevel_MASK 0x0000000FL +//NBIF_TRAP_NP_REQUEST5 +#define NBIF_TRAP_NP_REQUEST5__NBIF_TRAP_NP_TrapReqDataVC__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST5__NBIF_TRAP_NP_TrapReqDataErr__SHIFT 0x4 +#define NBIF_TRAP_NP_REQUEST5__NBIF_TRAP_NP_TrapReqDataVC_MASK 0x00000007L +#define NBIF_TRAP_NP_REQUEST5__NBIF_TRAP_NP_TrapReqDataErr_MASK 0x000000F0L +//NBIF_TRAP_NP_REQUEST6 +#define NBIF_TRAP_NP_REQUEST6__NBIF_TRAP_NP_TrapReqDataParity__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST6__NBIF_TRAP_NP_TrapReqDataParity_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB0__NBIF_TRAP_NP_TrapReqDataBytEn0__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB0__NBIF_TRAP_NP_TrapReqDataBytEn0_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB1 +#define NBIF_TRAP_NP_REQUEST_DATASTRB1__NBIF_TRAP_NP_TrapReqDataBytEn1__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB1__NBIF_TRAP_NP_TrapReqDataBytEn1_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB2 +#define NBIF_TRAP_NP_REQUEST_DATASTRB2__NBIF_TRAP_NP_TrapReqDataBytEn2__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB2__NBIF_TRAP_NP_TrapReqDataBytEn2_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB3 +#define NBIF_TRAP_NP_REQUEST_DATASTRB3__NBIF_TRAP_NP_TrapReqDataBytEn3__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB3__NBIF_TRAP_NP_TrapReqDataBytEn3_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB4 +#define NBIF_TRAP_NP_REQUEST_DATASTRB4__NBIF_TRAP_NP_TrapReqDataBytEn4__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB4__NBIF_TRAP_NP_TrapReqDataBytEn4_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB5 +#define NBIF_TRAP_NP_REQUEST_DATASTRB5__NBIF_TRAP_NP_TrapReqDataBytEn5__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB5__NBIF_TRAP_NP_TrapReqDataBytEn5_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB6 +#define NBIF_TRAP_NP_REQUEST_DATASTRB6__NBIF_TRAP_NP_TrapReqDataBytEn6__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB6__NBIF_TRAP_NP_TrapReqDataBytEn6_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB7 +#define NBIF_TRAP_NP_REQUEST_DATASTRB7__NBIF_TRAP_NP_TrapReqDataBytEn7__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB7__NBIF_TRAP_NP_TrapReqDataBytEn7_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA0 +#define NBIF_TRAP_NP_REQUEST_DATA0__NBIF_TRAP_NP_TrapReqData0__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA0__NBIF_TRAP_NP_TrapReqData0_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA1 +#define NBIF_TRAP_NP_REQUEST_DATA1__NBIF_TRAP_NP_TrapReqData1__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA1__NBIF_TRAP_NP_TrapReqData1_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA2 +#define NBIF_TRAP_NP_REQUEST_DATA2__NBIF_TRAP_NP_TrapReqData2__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA2__NBIF_TRAP_NP_TrapReqData2_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA3 +#define NBIF_TRAP_NP_REQUEST_DATA3__NBIF_TRAP_NP_TrapReqData3__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA3__NBIF_TRAP_NP_TrapReqData3_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA4 +#define NBIF_TRAP_NP_REQUEST_DATA4__NBIF_TRAP_NP_TrapReqData4__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA4__NBIF_TRAP_NP_TrapReqData4_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA5 +#define NBIF_TRAP_NP_REQUEST_DATA5__NBIF_TRAP_NP_TrapReqData5__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA5__NBIF_TRAP_NP_TrapReqData5_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA6 +#define NBIF_TRAP_NP_REQUEST_DATA6__NBIF_TRAP_NP_TrapReqData6__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA6__NBIF_TRAP_NP_TrapReqData6_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA7 +#define NBIF_TRAP_NP_REQUEST_DATA7__NBIF_TRAP_NP_TrapReqData7__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA7__NBIF_TRAP_NP_TrapReqData7_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA8 +#define NBIF_TRAP_NP_REQUEST_DATA8__NBIF_TRAP_NP_TrapReqData8__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA8__NBIF_TRAP_NP_TrapReqData8_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA9 +#define NBIF_TRAP_NP_REQUEST_DATA9__NBIF_TRAP_NP_TrapReqData9__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA9__NBIF_TRAP_NP_TrapReqData9_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA10 +#define NBIF_TRAP_NP_REQUEST_DATA10__NBIF_TRAP_NP_TrapReqData10__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA10__NBIF_TRAP_NP_TrapReqData10_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA11 +#define NBIF_TRAP_NP_REQUEST_DATA11__NBIF_TRAP_NP_TrapReqData11__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA11__NBIF_TRAP_NP_TrapReqData11_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA12 +#define NBIF_TRAP_NP_REQUEST_DATA12__NBIF_TRAP_NP_TrapReqData12__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA12__NBIF_TRAP_NP_TrapReqData12_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA13 +#define NBIF_TRAP_NP_REQUEST_DATA13__NBIF_TRAP_NP_TrapReqData13__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA13__NBIF_TRAP_NP_TrapReqData13_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA14 +#define NBIF_TRAP_NP_REQUEST_DATA14__NBIF_TRAP_NP_TrapReqData14__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA14__NBIF_TRAP_NP_TrapReqData14_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA15 +#define NBIF_TRAP_NP_REQUEST_DATA15__NBIF_TRAP_NP_TrapReqData15__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA15__NBIF_TRAP_NP_TrapReqData15_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA16 +#define NBIF_TRAP_NP_REQUEST_DATA16__NBIF_TRAP_NP_TrapReqData16__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA16__NBIF_TRAP_NP_TrapReqData16_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA17 +#define NBIF_TRAP_NP_REQUEST_DATA17__NBIF_TRAP_NP_TrapReqData17__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA17__NBIF_TRAP_NP_TrapReqData17_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA18 +#define NBIF_TRAP_NP_REQUEST_DATA18__NBIF_TRAP_NP_TrapReqData18__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA18__NBIF_TRAP_NP_TrapReqData18_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA19 +#define NBIF_TRAP_NP_REQUEST_DATA19__NBIF_TRAP_NP_TrapReqData19__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA19__NBIF_TRAP_NP_TrapReqData19_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA20 +#define NBIF_TRAP_NP_REQUEST_DATA20__NBIF_TRAP_NP_TrapReqData20__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA20__NBIF_TRAP_NP_TrapReqData20_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA21 +#define NBIF_TRAP_NP_REQUEST_DATA21__NBIF_TRAP_NP_TrapReqData21__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA21__NBIF_TRAP_NP_TrapReqData21_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA22 +#define NBIF_TRAP_NP_REQUEST_DATA22__NBIF_TRAP_NP_TrapReqData22__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA22__NBIF_TRAP_NP_TrapReqData22_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA23 +#define NBIF_TRAP_NP_REQUEST_DATA23__NBIF_TRAP_NP_TrapReqData23__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA23__NBIF_TRAP_NP_TrapReqData23_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA24 +#define NBIF_TRAP_NP_REQUEST_DATA24__NBIF_TRAP_NP_TrapReqData24__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA24__NBIF_TRAP_NP_TrapReqData24_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA25 +#define NBIF_TRAP_NP_REQUEST_DATA25__NBIF_TRAP_NP_TrapReqData25__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA25__NBIF_TRAP_NP_TrapReqData25_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA26 +#define NBIF_TRAP_NP_REQUEST_DATA26__NBIF_TRAP_NP_TrapReqData26__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA26__NBIF_TRAP_NP_TrapReqData26_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA27 +#define NBIF_TRAP_NP_REQUEST_DATA27__NBIF_TRAP_NP_TrapReqData27__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA27__NBIF_TRAP_NP_TrapReqData27_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA28 +#define NBIF_TRAP_NP_REQUEST_DATA28__NBIF_TRAP_NP_TrapReqData28__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA28__NBIF_TRAP_NP_TrapReqData28_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA29 +#define NBIF_TRAP_NP_REQUEST_DATA29__NBIF_TRAP_NP_TrapReqData29__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA29__NBIF_TRAP_NP_TrapReqData29_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA30 +#define NBIF_TRAP_NP_REQUEST_DATA30__NBIF_TRAP_NP_TrapReqData30__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA30__NBIF_TRAP_NP_TrapReqData30_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA31 +#define NBIF_TRAP_NP_REQUEST_DATA31__NBIF_TRAP_NP_TrapReqData31__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA31__NBIF_TRAP_NP_TrapReqData31_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA32 +#define NBIF_TRAP_NP_REQUEST_DATA32__NBIF_TRAP_NP_TrapReqData32__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA32__NBIF_TRAP_NP_TrapReqData32_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA33 +#define NBIF_TRAP_NP_REQUEST_DATA33__NBIF_TRAP_NP_TrapReqData33__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA33__NBIF_TRAP_NP_TrapReqData33_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA34 +#define NBIF_TRAP_NP_REQUEST_DATA34__NBIF_TRAP_NP_TrapReqData34__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA34__NBIF_TRAP_NP_TrapReqData34_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA35 +#define NBIF_TRAP_NP_REQUEST_DATA35__NBIF_TRAP_NP_TrapReqData35__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA35__NBIF_TRAP_NP_TrapReqData35_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA36 +#define NBIF_TRAP_NP_REQUEST_DATA36__NBIF_TRAP_NP_TrapReqData36__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA36__NBIF_TRAP_NP_TrapReqData36_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA37 +#define NBIF_TRAP_NP_REQUEST_DATA37__NBIF_TRAP_NP_TrapReqData37__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA37__NBIF_TRAP_NP_TrapReqData37_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA38 +#define NBIF_TRAP_NP_REQUEST_DATA38__NBIF_TRAP_NP_TrapReqData38__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA38__NBIF_TRAP_NP_TrapReqData38_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA39 +#define NBIF_TRAP_NP_REQUEST_DATA39__NBIF_TRAP_NP_TrapReqData39__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA39__NBIF_TRAP_NP_TrapReqData39_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA40 +#define NBIF_TRAP_NP_REQUEST_DATA40__NBIF_TRAP_NP_TrapReqData40__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA40__NBIF_TRAP_NP_TrapReqData40_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA41 +#define NBIF_TRAP_NP_REQUEST_DATA41__NBIF_TRAP_NP_TrapReqData41__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA41__NBIF_TRAP_NP_TrapReqData41_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA42 +#define NBIF_TRAP_NP_REQUEST_DATA42__NBIF_TRAP_NP_TrapReqData42__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA42__NBIF_TRAP_NP_TrapReqData42_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA43 +#define NBIF_TRAP_NP_REQUEST_DATA43__NBIF_TRAP_NP_TrapReqData43__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA43__NBIF_TRAP_NP_TrapReqData43_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA44 +#define NBIF_TRAP_NP_REQUEST_DATA44__NBIF_TRAP_NP_TrapReqData44__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA44__NBIF_TRAP_NP_TrapReqData44_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA45 +#define NBIF_TRAP_NP_REQUEST_DATA45__NBIF_TRAP_NP_TrapReqData45__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA45__NBIF_TRAP_NP_TrapReqData45_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA46 +#define NBIF_TRAP_NP_REQUEST_DATA46__NBIF_TRAP_NP_TrapReqData46__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA46__NBIF_TRAP_NP_TrapReqData46_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA47 +#define NBIF_TRAP_NP_REQUEST_DATA47__NBIF_TRAP_NP_TrapReqData47__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA47__NBIF_TRAP_NP_TrapReqData47_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA48 +#define NBIF_TRAP_NP_REQUEST_DATA48__NBIF_TRAP_NP_TrapReqData48__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA48__NBIF_TRAP_NP_TrapReqData48_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA49 +#define NBIF_TRAP_NP_REQUEST_DATA49__NBIF_TRAP_NP_TrapReqData49__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA49__NBIF_TRAP_NP_TrapReqData49_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA50 +#define NBIF_TRAP_NP_REQUEST_DATA50__NBIF_TRAP_NP_TrapReqData50__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA50__NBIF_TRAP_NP_TrapReqData50_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA51 +#define NBIF_TRAP_NP_REQUEST_DATA51__NBIF_TRAP_NP_TrapReqData51__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA51__NBIF_TRAP_NP_TrapReqData51_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA52 +#define NBIF_TRAP_NP_REQUEST_DATA52__NBIF_TRAP_NP_TrapReqData52__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA52__NBIF_TRAP_NP_TrapReqData52_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA53 +#define NBIF_TRAP_NP_REQUEST_DATA53__NBIF_TRAP_NP_TrapReqData53__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA53__NBIF_TRAP_NP_TrapReqData53_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA54 +#define NBIF_TRAP_NP_REQUEST_DATA54__NBIF_TRAP_NP_TrapReqData54__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA54__NBIF_TRAP_NP_TrapReqData54_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA55 +#define NBIF_TRAP_NP_REQUEST_DATA55__NBIF_TRAP_NP_TrapReqData55__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA55__NBIF_TRAP_NP_TrapReqData55_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA56 +#define NBIF_TRAP_NP_REQUEST_DATA56__NBIF_TRAP_NP_TrapReqData56__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA56__NBIF_TRAP_NP_TrapReqData56_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA57 +#define NBIF_TRAP_NP_REQUEST_DATA57__NBIF_TRAP_NP_TrapReqData57__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA57__NBIF_TRAP_NP_TrapReqData57_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA58 +#define NBIF_TRAP_NP_REQUEST_DATA58__NBIF_TRAP_NP_TrapReqData58__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA58__NBIF_TRAP_NP_TrapReqData58_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA59 +#define NBIF_TRAP_NP_REQUEST_DATA59__NBIF_TRAP_NP_TrapReqData59__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA59__NBIF_TRAP_NP_TrapReqData59_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA60 +#define NBIF_TRAP_NP_REQUEST_DATA60__NBIF_TRAP_NP_TrapReqData60__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA60__NBIF_TRAP_NP_TrapReqData60_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA61 +#define NBIF_TRAP_NP_REQUEST_DATA61__NBIF_TRAP_NP_TrapReqData61__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA61__NBIF_TRAP_NP_TrapReqData61_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA62 +#define NBIF_TRAP_NP_REQUEST_DATA62__NBIF_TRAP_NP_TrapReqData62__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA62__NBIF_TRAP_NP_TrapReqData62_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA63 +#define NBIF_TRAP_NP_REQUEST_DATA63__NBIF_TRAP_NP_TrapReqData63__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA63__NBIF_TRAP_NP_TrapReqData63_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_CONTROL +#define NBIF_TRAP_NP_RESPONSE_CONTROL__NBIF_TRAP_NP_TrapRspTrigger__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_CONTROL__NBIF_TRAP_NP_TrapRspReqPassthru__SHIFT 0x1 +#define NBIF_TRAP_NP_RESPONSE_CONTROL__NBIF_TRAP_NP_TrapRspTrigger_MASK 0x00000001L +#define NBIF_TRAP_NP_RESPONSE_CONTROL__NBIF_TRAP_NP_TrapRspReqPassthru_MASK 0x00000002L +//NBIF_TRAP_NP_RESPONSE0 +#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspPassPW__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspStatus__SHIFT 0x4 +#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspDataStatus__SHIFT 0x10 +#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspPassPW_MASK 0x00000001L +#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspStatus_MASK 0x000000F0L +#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspDataStatus_MASK 0x00FF0000L +//NBIF_TRAP_NP_RESPONSE1 +#define NBIF_TRAP_NP_RESPONSE1__NBIF_TRAP_NP_TrapRspCplid__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE1__NBIF_TRAP_NP_TrapRspSrcdata__SHIFT 0x10 +#define NBIF_TRAP_NP_RESPONSE1__NBIF_TRAP_NP_TrapRspCplid_MASK 0x0000FFFFL +#define NBIF_TRAP_NP_RESPONSE1__NBIF_TRAP_NP_TrapRspSrcdata_MASK 0x003F0000L +//NBIF_TRAP_NP_RESPONSE2 +#define NBIF_TRAP_NP_RESPONSE2__NBIF_TRAP_NP_TrapRspUser0__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE2__NBIF_TRAP_NP_TrapRspUser0_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE3 +#define NBIF_TRAP_NP_RESPONSE3__NBIF_TRAP_NP_TrapRspUser1__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE3__NBIF_TRAP_NP_TrapRspUser1_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE4 +#define NBIF_TRAP_NP_RESPONSE4__NBIF_TRAP_NP_TrapRspUser2__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE4__NBIF_TRAP_NP_TrapRspUser2_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE5 +#define NBIF_TRAP_NP_RESPONSE5__NBIF_TRAP_NP_TrapRspUser3__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE5__NBIF_TRAP_NP_TrapRspUser3_MASK 0x00000007L +//NBIF_TRAP_NP_RESPONSE_DATA0 +#define NBIF_TRAP_NP_RESPONSE_DATA0__NBIF_TRAP_NP_TrapRdRspData0__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA0__NBIF_TRAP_NP_TrapRdRspData0_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA1 +#define NBIF_TRAP_NP_RESPONSE_DATA1__NBIF_TRAP_NP_TrapRdRspData1__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA1__NBIF_TRAP_NP_TrapRdRspData1_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA2 +#define NBIF_TRAP_NP_RESPONSE_DATA2__NBIF_TRAP_NP_TrapRdRspData2__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA2__NBIF_TRAP_NP_TrapRdRspData2_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA3 +#define NBIF_TRAP_NP_RESPONSE_DATA3__NBIF_TRAP_NP_TrapRdRspData3__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA3__NBIF_TRAP_NP_TrapRdRspData3_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA4 +#define NBIF_TRAP_NP_RESPONSE_DATA4__NBIF_TRAP_NP_TrapRdRspData4__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA4__NBIF_TRAP_NP_TrapRdRspData4_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA5 +#define NBIF_TRAP_NP_RESPONSE_DATA5__NBIF_TRAP_NP_TrapRdRspData5__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA5__NBIF_TRAP_NP_TrapRdRspData5_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA6 +#define NBIF_TRAP_NP_RESPONSE_DATA6__NBIF_TRAP_NP_TrapRdRspData6__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA6__NBIF_TRAP_NP_TrapRdRspData6_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA7 +#define NBIF_TRAP_NP_RESPONSE_DATA7__NBIF_TRAP_NP_TrapRdRspData7__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA7__NBIF_TRAP_NP_TrapRdRspData7_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA8 +#define NBIF_TRAP_NP_RESPONSE_DATA8__NBIF_TRAP_NP_TrapRdRspData8__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA8__NBIF_TRAP_NP_TrapRdRspData8_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA9 +#define NBIF_TRAP_NP_RESPONSE_DATA9__NBIF_TRAP_NP_TrapRdRspData9__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA9__NBIF_TRAP_NP_TrapRdRspData9_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA10 +#define NBIF_TRAP_NP_RESPONSE_DATA10__NBIF_TRAP_NP_TrapRdRspData10__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA10__NBIF_TRAP_NP_TrapRdRspData10_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA11 +#define NBIF_TRAP_NP_RESPONSE_DATA11__NBIF_TRAP_NP_TrapRdRspData11__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA11__NBIF_TRAP_NP_TrapRdRspData11_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA12 +#define NBIF_TRAP_NP_RESPONSE_DATA12__NBIF_TRAP_NP_TrapRdRspData12__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA12__NBIF_TRAP_NP_TrapRdRspData12_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA13 +#define NBIF_TRAP_NP_RESPONSE_DATA13__NBIF_TRAP_NP_TrapRdRspData13__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA13__NBIF_TRAP_NP_TrapRdRspData13_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA14 +#define NBIF_TRAP_NP_RESPONSE_DATA14__NBIF_TRAP_NP_TrapRdRspData14__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA14__NBIF_TRAP_NP_TrapRdRspData14_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA15 +#define NBIF_TRAP_NP_RESPONSE_DATA15__NBIF_TRAP_NP_TrapRdRspData15__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA15__NBIF_TRAP_NP_TrapRdRspData15_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA16 +#define NBIF_TRAP_NP_RESPONSE_DATA16__NBIF_TRAP_NP_TrapRdRspData16__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA16__NBIF_TRAP_NP_TrapRdRspData16_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA17 +#define NBIF_TRAP_NP_RESPONSE_DATA17__NBIF_TRAP_NP_TrapRdRspData17__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA17__NBIF_TRAP_NP_TrapRdRspData17_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA18 +#define NBIF_TRAP_NP_RESPONSE_DATA18__NBIF_TRAP_NP_TrapRdRspData18__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA18__NBIF_TRAP_NP_TrapRdRspData18_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA19 +#define NBIF_TRAP_NP_RESPONSE_DATA19__NBIF_TRAP_NP_TrapRdRspData19__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA19__NBIF_TRAP_NP_TrapRdRspData19_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA20 +#define NBIF_TRAP_NP_RESPONSE_DATA20__NBIF_TRAP_NP_TrapRdRspData20__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA20__NBIF_TRAP_NP_TrapRdRspData20_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA21 +#define NBIF_TRAP_NP_RESPONSE_DATA21__NBIF_TRAP_NP_TrapRdRspData21__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA21__NBIF_TRAP_NP_TrapRdRspData21_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA22 +#define NBIF_TRAP_NP_RESPONSE_DATA22__NBIF_TRAP_NP_TrapRdRspData22__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA22__NBIF_TRAP_NP_TrapRdRspData22_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA23 +#define NBIF_TRAP_NP_RESPONSE_DATA23__NBIF_TRAP_NP_TrapRdRspData23__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA23__NBIF_TRAP_NP_TrapRdRspData23_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA24 +#define NBIF_TRAP_NP_RESPONSE_DATA24__NBIF_TRAP_NP_TrapRdRspData24__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA24__NBIF_TRAP_NP_TrapRdRspData24_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA25 +#define NBIF_TRAP_NP_RESPONSE_DATA25__NBIF_TRAP_NP_TrapRdRspData25__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA25__NBIF_TRAP_NP_TrapRdRspData25_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA26 +#define NBIF_TRAP_NP_RESPONSE_DATA26__NBIF_TRAP_NP_TrapRdRspData26__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA26__NBIF_TRAP_NP_TrapRdRspData26_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA27 +#define NBIF_TRAP_NP_RESPONSE_DATA27__NBIF_TRAP_NP_TrapRdRspData27__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA27__NBIF_TRAP_NP_TrapRdRspData27_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA28 +#define NBIF_TRAP_NP_RESPONSE_DATA28__NBIF_TRAP_NP_TrapRdRspData28__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA28__NBIF_TRAP_NP_TrapRdRspData28_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA29 +#define NBIF_TRAP_NP_RESPONSE_DATA29__NBIF_TRAP_NP_TrapRdRspData29__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA29__NBIF_TRAP_NP_TrapRdRspData29_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA30 +#define NBIF_TRAP_NP_RESPONSE_DATA30__NBIF_TRAP_NP_TrapRdRspData30__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA30__NBIF_TRAP_NP_TrapRdRspData30_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA31 +#define NBIF_TRAP_NP_RESPONSE_DATA31__NBIF_TRAP_NP_TrapRdRspData31__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA31__NBIF_TRAP_NP_TrapRdRspData31_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA32 +#define NBIF_TRAP_NP_RESPONSE_DATA32__NBIF_TRAP_NP_TrapRdRspData32__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA32__NBIF_TRAP_NP_TrapRdRspData32_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA33 +#define NBIF_TRAP_NP_RESPONSE_DATA33__NBIF_TRAP_NP_TrapRdRspData33__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA33__NBIF_TRAP_NP_TrapRdRspData33_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA34 +#define NBIF_TRAP_NP_RESPONSE_DATA34__NBIF_TRAP_NP_TrapRdRspData34__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA34__NBIF_TRAP_NP_TrapRdRspData34_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA35 +#define NBIF_TRAP_NP_RESPONSE_DATA35__NBIF_TRAP_NP_TrapRdRspData35__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA35__NBIF_TRAP_NP_TrapRdRspData35_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA36 +#define NBIF_TRAP_NP_RESPONSE_DATA36__NBIF_TRAP_NP_TrapRdRspData36__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA36__NBIF_TRAP_NP_TrapRdRspData36_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA37 +#define NBIF_TRAP_NP_RESPONSE_DATA37__NBIF_TRAP_NP_TrapRdRspData37__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA37__NBIF_TRAP_NP_TrapRdRspData37_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA38 +#define NBIF_TRAP_NP_RESPONSE_DATA38__NBIF_TRAP_NP_TrapRdRspData38__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA38__NBIF_TRAP_NP_TrapRdRspData38_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA39 +#define NBIF_TRAP_NP_RESPONSE_DATA39__NBIF_TRAP_NP_TrapRdRspData39__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA39__NBIF_TRAP_NP_TrapRdRspData39_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA40 +#define NBIF_TRAP_NP_RESPONSE_DATA40__NBIF_TRAP_NP_TrapRdRspData40__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA40__NBIF_TRAP_NP_TrapRdRspData40_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA41 +#define NBIF_TRAP_NP_RESPONSE_DATA41__NBIF_TRAP_NP_TrapRdRspData41__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA41__NBIF_TRAP_NP_TrapRdRspData41_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA42 +#define NBIF_TRAP_NP_RESPONSE_DATA42__NBIF_TRAP_NP_TrapRdRspData42__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA42__NBIF_TRAP_NP_TrapRdRspData42_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA43 +#define NBIF_TRAP_NP_RESPONSE_DATA43__NBIF_TRAP_NP_TrapRdRspData43__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA43__NBIF_TRAP_NP_TrapRdRspData43_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA44 +#define NBIF_TRAP_NP_RESPONSE_DATA44__NBIF_TRAP_NP_TrapRdRspData44__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA44__NBIF_TRAP_NP_TrapRdRspData44_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA45 +#define NBIF_TRAP_NP_RESPONSE_DATA45__NBIF_TRAP_NP_TrapRdRspData45__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA45__NBIF_TRAP_NP_TrapRdRspData45_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA46 +#define NBIF_TRAP_NP_RESPONSE_DATA46__NBIF_TRAP_NP_TrapRdRspData46__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA46__NBIF_TRAP_NP_TrapRdRspData46_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA47 +#define NBIF_TRAP_NP_RESPONSE_DATA47__NBIF_TRAP_NP_TrapRdRspData47__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA47__NBIF_TRAP_NP_TrapRdRspData47_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA48 +#define NBIF_TRAP_NP_RESPONSE_DATA48__NBIF_TRAP_NP_TrapRdRspData48__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA48__NBIF_TRAP_NP_TrapRdRspData48_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA49 +#define NBIF_TRAP_NP_RESPONSE_DATA49__NBIF_TRAP_NP_TrapRdRspData49__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA49__NBIF_TRAP_NP_TrapRdRspData49_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA50 +#define NBIF_TRAP_NP_RESPONSE_DATA50__NBIF_TRAP_NP_TrapRdRspData50__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA50__NBIF_TRAP_NP_TrapRdRspData50_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA51 +#define NBIF_TRAP_NP_RESPONSE_DATA51__NBIF_TRAP_NP_TrapRdRspData51__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA51__NBIF_TRAP_NP_TrapRdRspData51_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA52 +#define NBIF_TRAP_NP_RESPONSE_DATA52__NBIF_TRAP_NP_TrapRdRspData52__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA52__NBIF_TRAP_NP_TrapRdRspData52_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA53 +#define NBIF_TRAP_NP_RESPONSE_DATA53__NBIF_TRAP_NP_TrapRdRspData53__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA53__NBIF_TRAP_NP_TrapRdRspData53_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA54 +#define NBIF_TRAP_NP_RESPONSE_DATA54__NBIF_TRAP_NP_TrapRdRspData54__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA54__NBIF_TRAP_NP_TrapRdRspData54_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA55 +#define NBIF_TRAP_NP_RESPONSE_DATA55__NBIF_TRAP_NP_TrapRdRspData55__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA55__NBIF_TRAP_NP_TrapRdRspData55_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA56 +#define NBIF_TRAP_NP_RESPONSE_DATA56__NBIF_TRAP_NP_TrapRdRspData56__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA56__NBIF_TRAP_NP_TrapRdRspData56_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA57 +#define NBIF_TRAP_NP_RESPONSE_DATA57__NBIF_TRAP_NP_TrapRdRspData57__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA57__NBIF_TRAP_NP_TrapRdRspData57_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA58 +#define NBIF_TRAP_NP_RESPONSE_DATA58__NBIF_TRAP_NP_TrapRdRspData58__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA58__NBIF_TRAP_NP_TrapRdRspData58_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA59 +#define NBIF_TRAP_NP_RESPONSE_DATA59__NBIF_TRAP_NP_TrapRdRspData59__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA59__NBIF_TRAP_NP_TrapRdRspData59_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA60 +#define NBIF_TRAP_NP_RESPONSE_DATA60__NBIF_TRAP_NP_TrapRdRspData60__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA60__NBIF_TRAP_NP_TrapRdRspData60_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA61 +#define NBIF_TRAP_NP_RESPONSE_DATA61__NBIF_TRAP_NP_TrapRdRspData61__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA61__NBIF_TRAP_NP_TrapRdRspData61_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA62 +#define NBIF_TRAP_NP_RESPONSE_DATA62__NBIF_TRAP_NP_TrapRdRspData62__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA62__NBIF_TRAP_NP_TrapRdRspData62_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA63 +#define NBIF_TRAP_NP_RESPONSE_DATA63__NBIF_TRAP_NP_TrapRdRspData63__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA63__NBIF_TRAP_NP_TrapRdRspData63_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_0_CONTROL0 +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0En__SHIFT 0x0 +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0En_MASK 0x00000001L +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_0_ADDRESS_LO +#define NBIF_TRAP_NP_0_ADDRESS_LO__NBIF_TRAP_NP_Trap0AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_0_ADDRESS_LO__NBIF_TRAP_NP_Trap0AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_0_ADDRESS_HI +#define NBIF_TRAP_NP_0_ADDRESS_HI__NBIF_TRAP_NP_Trap0AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_0_ADDRESS_HI__NBIF_TRAP_NP_Trap0AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_0_COMMAND +#define NBIF_TRAP_NP_0_COMMAND__NBIF_TRAP_NP_Trap0Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_0_COMMAND__NBIF_TRAP_NP_Trap0Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_0_COMMAND__NBIF_TRAP_NP_Trap0Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_0_COMMAND__NBIF_TRAP_NP_Trap0Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_0_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_0_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap0AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_0_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap0AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_0_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_0_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap0AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_0_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap0AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_0_COMMAND_MASK +#define NBIF_TRAP_NP_0_COMMAND_MASK__NBIF_TRAP_NP_Trap0Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_0_COMMAND_MASK__NBIF_TRAP_NP_Trap0Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_0_COMMAND_MASK__NBIF_TRAP_NP_Trap0Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_0_COMMAND_MASK__NBIF_TRAP_NP_Trap0Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_1_CONTROL0 +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1En__SHIFT 0x0 +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1En_MASK 0x00000001L +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_1_ADDRESS_LO +#define NBIF_TRAP_NP_1_ADDRESS_LO__NBIF_TRAP_NP_Trap1AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_1_ADDRESS_LO__NBIF_TRAP_NP_Trap1AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_1_ADDRESS_HI +#define NBIF_TRAP_NP_1_ADDRESS_HI__NBIF_TRAP_NP_Trap1AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_1_ADDRESS_HI__NBIF_TRAP_NP_Trap1AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_1_COMMAND +#define NBIF_TRAP_NP_1_COMMAND__NBIF_TRAP_NP_Trap1Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_1_COMMAND__NBIF_TRAP_NP_Trap1Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_1_COMMAND__NBIF_TRAP_NP_Trap1Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_1_COMMAND__NBIF_TRAP_NP_Trap1Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_1_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_1_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap1AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_1_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap1AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_1_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_1_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap1AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_1_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap1AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_1_COMMAND_MASK +#define NBIF_TRAP_NP_1_COMMAND_MASK__NBIF_TRAP_NP_Trap1Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_1_COMMAND_MASK__NBIF_TRAP_NP_Trap1Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_1_COMMAND_MASK__NBIF_TRAP_NP_Trap1Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_1_COMMAND_MASK__NBIF_TRAP_NP_Trap1Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_2_CONTROL0 +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2En__SHIFT 0x0 +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2En_MASK 0x00000001L +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_2_ADDRESS_LO +#define NBIF_TRAP_NP_2_ADDRESS_LO__NBIF_TRAP_NP_Trap2AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_2_ADDRESS_LO__NBIF_TRAP_NP_Trap2AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_2_ADDRESS_HI +#define NBIF_TRAP_NP_2_ADDRESS_HI__NBIF_TRAP_NP_Trap2AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_2_ADDRESS_HI__NBIF_TRAP_NP_Trap2AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_2_COMMAND +#define NBIF_TRAP_NP_2_COMMAND__NBIF_TRAP_NP_Trap2Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_2_COMMAND__NBIF_TRAP_NP_Trap2Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_2_COMMAND__NBIF_TRAP_NP_Trap2Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_2_COMMAND__NBIF_TRAP_NP_Trap2Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_2_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_2_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap2AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_2_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap2AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_2_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_2_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap2AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_2_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap2AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_2_COMMAND_MASK +#define NBIF_TRAP_NP_2_COMMAND_MASK__NBIF_TRAP_NP_Trap2Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_2_COMMAND_MASK__NBIF_TRAP_NP_Trap2Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_2_COMMAND_MASK__NBIF_TRAP_NP_Trap2Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_2_COMMAND_MASK__NBIF_TRAP_NP_Trap2Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_3_CONTROL0 +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3En__SHIFT 0x0 +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3En_MASK 0x00000001L +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_3_ADDRESS_LO +#define NBIF_TRAP_NP_3_ADDRESS_LO__NBIF_TRAP_NP_Trap3AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_3_ADDRESS_LO__NBIF_TRAP_NP_Trap3AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_3_ADDRESS_HI +#define NBIF_TRAP_NP_3_ADDRESS_HI__NBIF_TRAP_NP_Trap3AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_3_ADDRESS_HI__NBIF_TRAP_NP_Trap3AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_3_COMMAND +#define NBIF_TRAP_NP_3_COMMAND__NBIF_TRAP_NP_Trap3Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_3_COMMAND__NBIF_TRAP_NP_Trap3Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_3_COMMAND__NBIF_TRAP_NP_Trap3Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_3_COMMAND__NBIF_TRAP_NP_Trap3Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_3_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_3_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap3AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_3_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap3AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_3_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_3_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap3AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_3_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap3AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_3_COMMAND_MASK +#define NBIF_TRAP_NP_3_COMMAND_MASK__NBIF_TRAP_NP_Trap3Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_3_COMMAND_MASK__NBIF_TRAP_NP_Trap3Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_3_COMMAND_MASK__NBIF_TRAP_NP_Trap3Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_3_COMMAND_MASK__NBIF_TRAP_NP_Trap3Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_4_CONTROL0 +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4En__SHIFT 0x0 +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4En_MASK 0x00000001L +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_4_ADDRESS_LO +#define NBIF_TRAP_NP_4_ADDRESS_LO__NBIF_TRAP_NP_Trap4AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_4_ADDRESS_LO__NBIF_TRAP_NP_Trap4AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_4_ADDRESS_HI +#define NBIF_TRAP_NP_4_ADDRESS_HI__NBIF_TRAP_NP_Trap4AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_4_ADDRESS_HI__NBIF_TRAP_NP_Trap4AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_4_COMMAND +#define NBIF_TRAP_NP_4_COMMAND__NBIF_TRAP_NP_Trap4Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_4_COMMAND__NBIF_TRAP_NP_Trap4Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_4_COMMAND__NBIF_TRAP_NP_Trap4Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_4_COMMAND__NBIF_TRAP_NP_Trap4Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_4_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_4_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap4AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_4_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap4AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_4_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_4_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap4AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_4_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap4AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_4_COMMAND_MASK +#define NBIF_TRAP_NP_4_COMMAND_MASK__NBIF_TRAP_NP_Trap4Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_4_COMMAND_MASK__NBIF_TRAP_NP_Trap4Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_4_COMMAND_MASK__NBIF_TRAP_NP_Trap4Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_4_COMMAND_MASK__NBIF_TRAP_NP_Trap4Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_5_CONTROL0 +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5En__SHIFT 0x0 +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5En_MASK 0x00000001L +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_5_ADDRESS_LO +#define NBIF_TRAP_NP_5_ADDRESS_LO__NBIF_TRAP_NP_Trap5AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_5_ADDRESS_LO__NBIF_TRAP_NP_Trap5AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_5_ADDRESS_HI +#define NBIF_TRAP_NP_5_ADDRESS_HI__NBIF_TRAP_NP_Trap5AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_5_ADDRESS_HI__NBIF_TRAP_NP_Trap5AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_5_COMMAND +#define NBIF_TRAP_NP_5_COMMAND__NBIF_TRAP_NP_Trap5Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_5_COMMAND__NBIF_TRAP_NP_Trap5Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_5_COMMAND__NBIF_TRAP_NP_Trap5Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_5_COMMAND__NBIF_TRAP_NP_Trap5Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_5_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_5_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap5AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_5_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap5AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_5_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_5_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap5AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_5_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap5AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_5_COMMAND_MASK +#define NBIF_TRAP_NP_5_COMMAND_MASK__NBIF_TRAP_NP_Trap5Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_5_COMMAND_MASK__NBIF_TRAP_NP_Trap5Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_5_COMMAND_MASK__NBIF_TRAP_NP_Trap5Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_5_COMMAND_MASK__NBIF_TRAP_NP_Trap5Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_6_CONTROL0 +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6En__SHIFT 0x0 +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6En_MASK 0x00000001L +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_6_ADDRESS_LO +#define NBIF_TRAP_NP_6_ADDRESS_LO__NBIF_TRAP_NP_Trap6AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_6_ADDRESS_LO__NBIF_TRAP_NP_Trap6AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_6_ADDRESS_HI +#define NBIF_TRAP_NP_6_ADDRESS_HI__NBIF_TRAP_NP_Trap6AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_6_ADDRESS_HI__NBIF_TRAP_NP_Trap6AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_6_COMMAND +#define NBIF_TRAP_NP_6_COMMAND__NBIF_TRAP_NP_Trap6Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_6_COMMAND__NBIF_TRAP_NP_Trap6Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_6_COMMAND__NBIF_TRAP_NP_Trap6Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_6_COMMAND__NBIF_TRAP_NP_Trap6Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_6_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_6_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap6AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_6_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap6AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_6_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_6_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap6AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_6_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap6AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_6_COMMAND_MASK +#define NBIF_TRAP_NP_6_COMMAND_MASK__NBIF_TRAP_NP_Trap6Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_6_COMMAND_MASK__NBIF_TRAP_NP_Trap6Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_6_COMMAND_MASK__NBIF_TRAP_NP_Trap6Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_6_COMMAND_MASK__NBIF_TRAP_NP_Trap6Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_7_CONTROL0 +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7En__SHIFT 0x0 +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7En_MASK 0x00000001L +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_7_ADDRESS_LO +#define NBIF_TRAP_NP_7_ADDRESS_LO__NBIF_TRAP_NP_Trap7AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_7_ADDRESS_LO__NBIF_TRAP_NP_Trap7AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_7_ADDRESS_HI +#define NBIF_TRAP_NP_7_ADDRESS_HI__NBIF_TRAP_NP_Trap7AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_7_ADDRESS_HI__NBIF_TRAP_NP_Trap7AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_7_COMMAND +#define NBIF_TRAP_NP_7_COMMAND__NBIF_TRAP_NP_Trap7Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_7_COMMAND__NBIF_TRAP_NP_Trap7Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_7_COMMAND__NBIF_TRAP_NP_Trap7Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_7_COMMAND__NBIF_TRAP_NP_Trap7Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_7_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_7_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap7AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_7_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap7AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_7_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_7_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap7AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_7_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap7AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_7_COMMAND_MASK +#define NBIF_TRAP_NP_7_COMMAND_MASK__NBIF_TRAP_NP_Trap7Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_7_COMMAND_MASK__NBIF_TRAP_NP_Trap7Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_7_COMMAND_MASK__NBIF_TRAP_NP_Trap7Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_7_COMMAND_MASK__NBIF_TRAP_NP_Trap7Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_8_CONTROL0 +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8En__SHIFT 0x0 +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8En_MASK 0x00000001L +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_8_ADDRESS_LO +#define NBIF_TRAP_NP_8_ADDRESS_LO__NBIF_TRAP_NP_Trap8AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_8_ADDRESS_LO__NBIF_TRAP_NP_Trap8AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_8_ADDRESS_HI +#define NBIF_TRAP_NP_8_ADDRESS_HI__NBIF_TRAP_NP_Trap8AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_8_ADDRESS_HI__NBIF_TRAP_NP_Trap8AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_8_COMMAND +#define NBIF_TRAP_NP_8_COMMAND__NBIF_TRAP_NP_Trap8Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_8_COMMAND__NBIF_TRAP_NP_Trap8Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_8_COMMAND__NBIF_TRAP_NP_Trap8Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_8_COMMAND__NBIF_TRAP_NP_Trap8Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_8_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_8_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap8AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_8_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap8AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_8_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_8_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap8AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_8_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap8AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_8_COMMAND_MASK +#define NBIF_TRAP_NP_8_COMMAND_MASK__NBIF_TRAP_NP_Trap8Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_8_COMMAND_MASK__NBIF_TRAP_NP_Trap8Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_8_COMMAND_MASK__NBIF_TRAP_NP_Trap8Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_8_COMMAND_MASK__NBIF_TRAP_NP_Trap8Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_9_CONTROL0 +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9En__SHIFT 0x0 +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9En_MASK 0x00000001L +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_9_ADDRESS_LO +#define NBIF_TRAP_NP_9_ADDRESS_LO__NBIF_TRAP_NP_Trap9AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_9_ADDRESS_LO__NBIF_TRAP_NP_Trap9AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_9_ADDRESS_HI +#define NBIF_TRAP_NP_9_ADDRESS_HI__NBIF_TRAP_NP_Trap9AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_9_ADDRESS_HI__NBIF_TRAP_NP_Trap9AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_9_COMMAND +#define NBIF_TRAP_NP_9_COMMAND__NBIF_TRAP_NP_Trap9Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_9_COMMAND__NBIF_TRAP_NP_Trap9Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_9_COMMAND__NBIF_TRAP_NP_Trap9Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_9_COMMAND__NBIF_TRAP_NP_Trap9Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_9_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_9_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap9AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_9_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap9AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_9_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_9_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap9AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_9_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap9AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_9_COMMAND_MASK +#define NBIF_TRAP_NP_9_COMMAND_MASK__NBIF_TRAP_NP_Trap9Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_9_COMMAND_MASK__NBIF_TRAP_NP_Trap9Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_9_COMMAND_MASK__NBIF_TRAP_NP_Trap9Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_9_COMMAND_MASK__NBIF_TRAP_NP_Trap9Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_10_CONTROL0 +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10En__SHIFT 0x0 +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10En_MASK 0x00000001L +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_10_ADDRESS_LO +#define NBIF_TRAP_NP_10_ADDRESS_LO__NBIF_TRAP_NP_Trap10AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_10_ADDRESS_LO__NBIF_TRAP_NP_Trap10AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_10_ADDRESS_HI +#define NBIF_TRAP_NP_10_ADDRESS_HI__NBIF_TRAP_NP_Trap10AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_10_ADDRESS_HI__NBIF_TRAP_NP_Trap10AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_10_COMMAND +#define NBIF_TRAP_NP_10_COMMAND__NBIF_TRAP_NP_Trap10Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_10_COMMAND__NBIF_TRAP_NP_Trap10Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_10_COMMAND__NBIF_TRAP_NP_Trap10Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_10_COMMAND__NBIF_TRAP_NP_Trap10Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_10_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_10_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap10AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_10_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap10AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_10_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_10_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap10AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_10_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap10AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_10_COMMAND_MASK +#define NBIF_TRAP_NP_10_COMMAND_MASK__NBIF_TRAP_NP_Trap10Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_10_COMMAND_MASK__NBIF_TRAP_NP_Trap10Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_10_COMMAND_MASK__NBIF_TRAP_NP_Trap10Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_10_COMMAND_MASK__NBIF_TRAP_NP_Trap10Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_11_CONTROL0 +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11En__SHIFT 0x0 +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11En_MASK 0x00000001L +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_11_ADDRESS_LO +#define NBIF_TRAP_NP_11_ADDRESS_LO__NBIF_TRAP_NP_Trap11AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_11_ADDRESS_LO__NBIF_TRAP_NP_Trap11AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_11_ADDRESS_HI +#define NBIF_TRAP_NP_11_ADDRESS_HI__NBIF_TRAP_NP_Trap11AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_11_ADDRESS_HI__NBIF_TRAP_NP_Trap11AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_11_COMMAND +#define NBIF_TRAP_NP_11_COMMAND__NBIF_TRAP_NP_Trap11Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_11_COMMAND__NBIF_TRAP_NP_Trap11Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_11_COMMAND__NBIF_TRAP_NP_Trap11Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_11_COMMAND__NBIF_TRAP_NP_Trap11Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_11_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_11_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap11AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_11_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap11AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_11_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_11_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap11AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_11_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap11AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_11_COMMAND_MASK +#define NBIF_TRAP_NP_11_COMMAND_MASK__NBIF_TRAP_NP_Trap11Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_11_COMMAND_MASK__NBIF_TRAP_NP_Trap11Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_11_COMMAND_MASK__NBIF_TRAP_NP_Trap11Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_11_COMMAND_MASK__NBIF_TRAP_NP_Trap11Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_12_CONTROL0 +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12En__SHIFT 0x0 +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12En_MASK 0x00000001L +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_12_ADDRESS_LO +#define NBIF_TRAP_NP_12_ADDRESS_LO__NBIF_TRAP_NP_Trap12AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_12_ADDRESS_LO__NBIF_TRAP_NP_Trap12AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_12_ADDRESS_HI +#define NBIF_TRAP_NP_12_ADDRESS_HI__NBIF_TRAP_NP_Trap12AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_12_ADDRESS_HI__NBIF_TRAP_NP_Trap12AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_12_COMMAND +#define NBIF_TRAP_NP_12_COMMAND__NBIF_TRAP_NP_Trap12Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_12_COMMAND__NBIF_TRAP_NP_Trap12Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_12_COMMAND__NBIF_TRAP_NP_Trap12Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_12_COMMAND__NBIF_TRAP_NP_Trap12Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_12_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_12_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap12AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_12_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap12AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_12_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_12_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap12AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_12_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap12AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_12_COMMAND_MASK +#define NBIF_TRAP_NP_12_COMMAND_MASK__NBIF_TRAP_NP_Trap12Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_12_COMMAND_MASK__NBIF_TRAP_NP_Trap12Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_12_COMMAND_MASK__NBIF_TRAP_NP_Trap12Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_12_COMMAND_MASK__NBIF_TRAP_NP_Trap12Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_13_CONTROL0 +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13En__SHIFT 0x0 +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13En_MASK 0x00000001L +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_13_ADDRESS_LO +#define NBIF_TRAP_NP_13_ADDRESS_LO__NBIF_TRAP_NP_Trap13AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_13_ADDRESS_LO__NBIF_TRAP_NP_Trap13AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_13_ADDRESS_HI +#define NBIF_TRAP_NP_13_ADDRESS_HI__NBIF_TRAP_NP_Trap13AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_13_ADDRESS_HI__NBIF_TRAP_NP_Trap13AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_13_COMMAND +#define NBIF_TRAP_NP_13_COMMAND__NBIF_TRAP_NP_Trap13Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_13_COMMAND__NBIF_TRAP_NP_Trap13Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_13_COMMAND__NBIF_TRAP_NP_Trap13Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_13_COMMAND__NBIF_TRAP_NP_Trap13Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_13_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_13_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap13AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_13_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap13AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_13_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_13_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap13AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_13_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap13AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_13_COMMAND_MASK +#define NBIF_TRAP_NP_13_COMMAND_MASK__NBIF_TRAP_NP_Trap13Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_13_COMMAND_MASK__NBIF_TRAP_NP_Trap13Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_13_COMMAND_MASK__NBIF_TRAP_NP_Trap13Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_13_COMMAND_MASK__NBIF_TRAP_NP_Trap13Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_14_CONTROL0 +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14En__SHIFT 0x0 +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14En_MASK 0x00000001L +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_14_ADDRESS_LO +#define NBIF_TRAP_NP_14_ADDRESS_LO__NBIF_TRAP_NP_Trap14AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_14_ADDRESS_LO__NBIF_TRAP_NP_Trap14AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_14_ADDRESS_HI +#define NBIF_TRAP_NP_14_ADDRESS_HI__NBIF_TRAP_NP_Trap14AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_14_ADDRESS_HI__NBIF_TRAP_NP_Trap14AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_14_COMMAND +#define NBIF_TRAP_NP_14_COMMAND__NBIF_TRAP_NP_Trap14Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_14_COMMAND__NBIF_TRAP_NP_Trap14Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_14_COMMAND__NBIF_TRAP_NP_Trap14Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_14_COMMAND__NBIF_TRAP_NP_Trap14Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_14_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_14_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap14AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_14_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap14AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_14_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_14_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap14AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_14_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap14AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_14_COMMAND_MASK +#define NBIF_TRAP_NP_14_COMMAND_MASK__NBIF_TRAP_NP_Trap14Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_14_COMMAND_MASK__NBIF_TRAP_NP_Trap14Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_14_COMMAND_MASK__NBIF_TRAP_NP_Trap14Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_14_COMMAND_MASK__NBIF_TRAP_NP_Trap14Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_15_CONTROL0 +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15En__SHIFT 0x0 +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15En_MASK 0x00000001L +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_15_ADDRESS_LO +#define NBIF_TRAP_NP_15_ADDRESS_LO__NBIF_TRAP_NP_Trap15AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_15_ADDRESS_LO__NBIF_TRAP_NP_Trap15AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_15_ADDRESS_HI +#define NBIF_TRAP_NP_15_ADDRESS_HI__NBIF_TRAP_NP_Trap15AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_15_ADDRESS_HI__NBIF_TRAP_NP_Trap15AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_15_COMMAND +#define NBIF_TRAP_NP_15_COMMAND__NBIF_TRAP_NP_Trap15Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_15_COMMAND__NBIF_TRAP_NP_Trap15Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_15_COMMAND__NBIF_TRAP_NP_Trap15Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_15_COMMAND__NBIF_TRAP_NP_Trap15Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_15_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_15_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap15AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_15_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap15AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_15_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_15_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap15AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_15_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap15AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_15_COMMAND_MASK +#define NBIF_TRAP_NP_15_COMMAND_MASK__NBIF_TRAP_NP_Trap15Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_15_COMMAND_MASK__NBIF_TRAP_NP_Trap15Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_15_COMMAND_MASK__NBIF_TRAP_NP_Trap15Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_15_COMMAND_MASK__NBIF_TRAP_NP_Trap15Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_S2_CONTROL0 +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapEn__SHIFT 0x0 +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapSMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2Offset__SHIFT 0x4 +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapCrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapEn_MASK 0x00000001L +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapSMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2Offset_MASK 0x00003FF0L +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapCrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2En_MASK 0x80000000L +//NBIF_TRAP_NP_S2_ADDRESS_LO +#define NBIF_TRAP_NP_S2_ADDRESS_LO__NBIF_TRAP_NP_S2_TrapAddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_S2_ADDRESS_LO__NBIF_TRAP_NP_S2_TrapAddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_S2_ADDRESS_HI +#define NBIF_TRAP_NP_S2_ADDRESS_HI__NBIF_TRAP_NP_S2_TrapAddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_S2_ADDRESS_HI__NBIF_TRAP_NP_S2_TrapAddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_S2_COMMAND +#define NBIF_TRAP_NP_S2_COMMAND__NBIF_TRAP_NP_S2_TrapCmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_S2_COMMAND__NBIF_TRAP_NP_S2_TrapCmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_S2_COMMAND__NBIF_TRAP_NP_S2_TrapCmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_S2_COMMAND__NBIF_TRAP_NP_S2_TrapCmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_S2_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_S2_ADDRESS_LO_MASK__NBIF_TRAP_NP_S2_TrapAddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_S2_ADDRESS_LO_MASK__NBIF_TRAP_NP_S2_TrapAddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_S2_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_S2_ADDRESS_HI_MASK__NBIF_TRAP_NP_S2_TrapAddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_S2_ADDRESS_HI_MASK__NBIF_TRAP_NP_S2_TrapAddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_S2_COMMAND_MASK +#define NBIF_TRAP_NP_S2_COMMAND_MASK__NBIF_TRAP_NP_S2_TrapCmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_S2_COMMAND_MASK__NBIF_TRAP_NP_S2_TrapCmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_S2_COMMAND_MASK__NBIF_TRAP_NP_S2_TrapCmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_S2_COMMAND_MASK__NBIF_TRAP_NP_S2_TrapCmd1Mask_MASK 0x00003F00L + + +// addressBlock: nbif0_nbif0_bif_ras_bif_ras_regblk +//BIFL_RAS_CENTRAL_CNTL +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_HST_STALL_DIS__SHIFT 0x1b +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_STALL_DIS__SHIFT 0x1c +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS__SHIFT 0x1d +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS__SHIFT 0x1e +#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS__SHIFT 0x1f +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_HST_STALL_DIS_MASK 0x08000000L +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_STALL_DIS_MASK 0x10000000L +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS_MASK 0x20000000L +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS_MASK 0x40000000L +#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS_MASK 0x80000000L +//BIFL_RAS_CENTRAL_STATUS +#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det__SHIFT 0x0 +#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det__SHIFT 0x1 +#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det__SHIFT 0x2 +#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det__SHIFT 0x3 +#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv__SHIFT 0x1d +#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv__SHIFT 0x1e +#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv__SHIFT 0x1f +#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det_MASK 0x00000001L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det_MASK 0x00000002L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det_MASK 0x00000004L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det_MASK 0x00000008L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv_MASK 0x20000000L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv_MASK 0x40000000L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv_MASK 0x80000000L +//BIFL_RAS_LEAF0_CTRL +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF0_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF0_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF0_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF0_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF0_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF0_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF1_CTRL +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF1_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF1_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF1_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF1_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF1_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF1_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF2_CTRL +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF2_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF2_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF2_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF2_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF2_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF2_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF3_CTRL +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF3_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF3_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF3_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF3_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF3_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF3_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF4_CTRL +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF4_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF4_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF4_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF4_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF4_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF4_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF4_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF4_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF5_CTRL +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF5_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF5_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF5_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF5_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF5_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF5_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF5_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF5_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF5_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF5_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF5_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF5_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF5_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF5_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF5_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF5_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF5_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF6_CTRL +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF6_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF6_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF6_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF6_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF6_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF6_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF6_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF6_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF6_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF6_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF6_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF6_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF6_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF6_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF6_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF6_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF6_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF6_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF6_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF6_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF6_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF6_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF7_CTRL +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF7_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF7_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF7_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF7_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF7_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF7_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF7_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF7_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF7_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF7_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF7_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF7_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF7_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF7_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF7_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF7_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF7_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF7_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF7_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF7_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF7_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF7_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF8_CTRL +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF8_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF8_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF8_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF8_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF8_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF8_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF8_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF8_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF8_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF8_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF8_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF8_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF8_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF8_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF8_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF8_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF8_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF8_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF8_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF8_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF8_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF8_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF9_CTRL +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF9_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF9_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF9_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF9_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF9_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF9_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF9_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF9_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF9_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF9_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF9_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF9_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF9_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF9_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF9_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF9_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF9_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF9_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF9_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF9_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF9_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF9_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF10_CTRL +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF10_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF10_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF10_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF10_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF10_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF10_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF10_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF10_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF10_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF10_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF10_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF10_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF10_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF10_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF10_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF10_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF10_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF10_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF10_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF10_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF10_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF10_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF11_CTRL +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF11_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF11_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF11_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF11_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF11_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF11_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF11_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF11_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF11_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF11_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF11_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF11_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF11_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF11_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF11_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF11_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF11_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF11_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF11_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF11_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF11_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF11_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF12_CTRL +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF12_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF12_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF12_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF12_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF12_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF12_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF12_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF12_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF12_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF12_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF12_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF12_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF12_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF12_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF12_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF12_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF12_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF12_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF12_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF12_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF12_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF12_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF13_CTRL +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF13_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF13_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF13_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF13_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF13_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF13_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF13_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF13_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF13_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF13_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF13_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF13_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF13_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF13_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF13_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF13_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF13_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF13_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF13_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF13_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF13_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF13_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF14_CTRL +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF14_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF14_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF14_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF14_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF14_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF14_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF14_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF14_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF14_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF14_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF14_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF14_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF14_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF14_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF14_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF14_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF14_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF14_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF14_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF14_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF14_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF14_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF15_CTRL +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF15_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF15_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF15_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF15_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF15_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF15_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF15_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF15_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF15_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF15_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF15_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF15_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF15_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF15_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF15_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF15_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF15_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF15_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF15_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF15_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF15_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF15_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF16_CTRL +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF16_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF16_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF16_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF16_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF16_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF16_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF16_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF16_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF16_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF16_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF16_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF16_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF16_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF16_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF16_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF16_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF16_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF16_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF16_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF16_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF16_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF16_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF17_CTRL +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF17_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF17_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF17_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF17_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF17_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF17_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF17_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF17_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF17_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF17_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF17_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF17_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF17_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF17_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF17_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF17_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF17_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF17_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF17_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF17_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF17_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF17_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF18_CTRL +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF18_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF18_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF18_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF18_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF18_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF18_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF18_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF18_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF18_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF18_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF18_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF18_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF18_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF18_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF18_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF18_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF18_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF18_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF18_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF18_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF18_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF18_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF19_CTRL +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF19_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF19_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF19_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF19_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF19_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF19_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF19_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF19_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF19_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF19_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF19_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF19_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF19_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF19_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF19_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF19_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF19_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF19_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF19_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF19_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF19_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF19_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF2_MISC_CTRL +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS__SHIFT 0x8 +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS__SHIFT 0x9 +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_REQ__SHIFT 0xb +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_EN_DMA_REQ_CHAIN_CHK__SHIFT 0xc +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_RSP__SHIFT 0xd +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN__SHIFT 0x11 +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS_MASK 0x00000100L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS_MASK 0x00000200L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_REQ_MASK 0x00000800L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_EN_DMA_REQ_CHAIN_CHK_MASK 0x00001000L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_RSP_MASK 0x00002000L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN_MASK 0x00020000L +//BIFL_RAS_LEAF2_MISC_CTRL2 +#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID__SHIFT 0x0 +#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG__SHIFT 0xb +#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET__SHIFT 0x15 +#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_MASK 0x000007FFL +#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_MASK 0x001FF800L +#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET_MASK 0x7FE00000L +//BIFL_RAS_LEAF_NTB_CTRL +#define BIFL_RAS_LEAF_NTB_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x0 +#define BIFL_RAS_LEAF_NTB_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00000001L +//BIFL_RAS_LEAF0_STATUS +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF1_STATUS +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF2_STATUS +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF3_STATUS +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF4_STATUS +#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF4_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF4_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF4_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF4_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF5_STATUS +#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF5_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF5_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF5_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF5_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF5_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF5_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF5_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF5_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF6_STATUS +#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF6_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF6_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF6_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF6_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF6_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF6_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF6_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF6_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF7_STATUS +#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF7_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF7_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF7_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF7_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF7_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF7_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF7_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF7_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF8_STATUS +#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF8_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF8_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF8_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF8_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF8_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF8_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF8_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF8_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF9_STATUS +#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF9_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF9_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF9_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF9_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF9_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF9_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF9_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF9_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF10_STATUS +#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF10_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF10_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF10_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF10_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF10_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF10_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF10_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF10_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF11_STATUS +#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF11_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF11_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF11_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF11_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF11_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF11_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF11_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF11_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF12_STATUS +#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF12_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF12_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF12_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF12_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF12_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF12_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF12_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF12_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF13_STATUS +#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF13_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF13_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF13_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF13_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF13_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF13_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF13_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF13_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF14_STATUS +#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF14_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF14_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF14_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF14_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF14_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF14_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF14_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF14_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF15_STATUS +#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF15_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF15_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF15_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF15_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF15_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF15_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF15_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF15_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF16_STATUS +#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF16_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF16_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF16_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF16_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF16_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF16_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF16_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF16_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF17_STATUS +#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF17_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF17_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF17_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF17_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF17_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF17_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF17_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF17_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF18_STATUS +#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF18_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF18_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF18_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF18_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF18_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF18_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF18_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF18_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF19_STATUS +#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF19_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF19_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF19_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF19_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF19_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF19_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF19_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF19_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ_MASK 0x000000F0L +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_MASK 0x000000F0L +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_MASK 0x000000F0L +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP +#define BIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ_CNT__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ_CNT__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ_CNT_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ_CNT_MASK 0x000000F0L +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_CNT__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_CNT__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_CNT__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_CNT__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_CNT_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_CNT_MASK 0x000000F0L +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_CNT_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_CNT_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_CNT__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_CNT__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_CNT__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_CNT__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_CNT_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_CNT_MASK 0x000000F0L +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_CNT_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_CNT_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ_LOG__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ_LOG__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ_LOG_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ_LOG_MASK 0x000000F0L +//BIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_LOG__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_LOG__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_LOG_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_LOG_MASK 0x000000F0L +//BIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP +#define BIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_LOG__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_LOG__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_LOG_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_LOG_MASK 0x000000F0L +//BIFL_DFV_POISON_INJ_LOG_ATHUB_ORIG_SDP +//BIFL_IOHUB_RAS_IH_CNTL +#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN__SHIFT 0x0 +#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN_MASK 0x00000001L +//BIFL_RAS_VWR_FROM_IOHUB +#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG__SHIFT 0x0 +#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG_MASK 0x00000001L + + +// addressBlock: nbif0_nbif0_rcc_dwn_dev0_BIFDEC1 +//RCC_DWN_DEV0_2_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_2_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_2_DN_PCIE_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT 0x5 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK 0x00000020L +//RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_BIFDEC1 +//RCC_DWNP_DEV0_2_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//RCC_DWNP_DEV0_2_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT 0x4 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK 0x00000010L +//RCC_DWNP_DEV0_2_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_ep_dev0_BIFDEC1 +//RCC_EP_DEV0_2_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_2_EP_PCIE_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_2_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_2_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT 0x5 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK 0x00000020L +//RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_2_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_2_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK 0x00000010L +//RCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3 +#define RCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L + + +// addressBlock: nbif0_nbif0_rcc_dev0_BIFDEC1 +//RCC_DEV0_1_RCC_ERR_INT_CNTL +#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L +//RCC_DEV0_1_RCC_BACO_CNTL_MISC +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L +//RCC_DEV0_1_RCC_RESET_EN +#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf +#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L +//RCC_DEV0_2_RCC_VDM_SUPPORT +#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L +//RCC_DEV0_1_RCC_GPUIOV_REGION +#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//RCC_DEV0_1_RCC_GPU_HOSTVM_EN +#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L +//RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L +//RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET +#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE +#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL +//RCC_DEV0_1_RCC_PEER_REG_RANGE0 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_1_RCC_PEER_REG_RANGE1 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_2_RCC_BUS_CNTL +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_DEV0_1_RCC_CONFIG_CNTL +#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L +//RCC_DEV0_1_RCC_CONFIG_F0_BASE +#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL +//RCC_DEV0_1_RCC_CONFIG_APER_SIZE +#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE +#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL +//RCC_DEV0_1_RCC_XDMA_LO +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_XDMA_HI +#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL +//RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_DEV0_1_RCC_BUSNUM_CNTL1 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL +//RCC_DEV0_1_RCC_BUSNUM_LIST0 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L +//RCC_DEV0_1_RCC_BUSNUM_LIST1 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L +//RCC_DEV0_1_RCC_BUSNUM_CNTL2 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L +//RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM +#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L +//RCC_DEV0_1_RCC_HOST_BUSNUM +#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 +#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL +//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L +//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L +//RCC_DEV0_2_RCC_DEV0_LINK_CNTL +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_DEV0_2_RCC_CMN_LINK_CNTL +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG__SHIFT 0x10 +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG_MASK 0x00FF0000L +//RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL +#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_DEV0_2_RCC_MH_ARB_CNTL +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x0000FFFEL + + +// addressBlock: nbif0_nbif0_bif_bx_SYSDEC +//BIF_BX1_SYSHUB_INDEX_OVLP +#define BIF_BX1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0 +#define BIF_BX1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL +//BIF_BX1_SYSHUB_DATA_OVLP +#define BIF_BX1_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0 +#define BIF_BX1_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL +//BIF_BX1_SYSHUB_INDEX_HI_OVLP +#define BIF_BX1_SYSHUB_INDEX_HI_OVLP__SYSHUB_OFFSET_HI__SHIFT 0x0 +#define BIF_BX1_SYSHUB_INDEX_HI_OVLP__SYSHUB_OFFSET_HI_MASK 0x0000FFFFL +//BIF_BX1_PCIE_INDEX +#define BIF_BX1_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_DATA +#define BIF_BX1_PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define BIF_BX1_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_INDEX2 +#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_DATA2 +#define BIF_BX1_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 +#define BIF_BX1_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_INDEX_HI +#define BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK 0x0000FFFFL +//BIF_BX1_PCIE_INDEX2_HI +#define BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK 0x0000FFFFL +//BIF_BX1_SBIOS_SCRATCH_0 +#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_1 +#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_2 +#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_3 +#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_0 +#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_1 +#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_2 +#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_3 +#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_4 +#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_5 +#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_6 +#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_7 +#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_8 +#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_9 +#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_10 +#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_11 +#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_12 +#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_13 +#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_14 +#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_15 +#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_RLC_INTR_CNTL +//BIF_BX1_BIF_VCE_INTR_CNTL +//BIF_BX1_BIF_UVD_INTR_CNTL +//BIF_BX1_BIF_Engine_INTR_CNTL +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_CMD_COMPLETE__SHIFT 0x0 +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_HANG_SELF_RECOVERED__SHIFT 0x1 +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_HANG_NEED_FLR__SHIFT 0x2 +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_VM_BUSY_TRANSITION__SHIFT 0x3 +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_INST_SEL__SHIFT 0x1b +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_CMD_COMPLETE_MASK 0x00000001L +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_HANG_SELF_RECOVERED_MASK 0x00000002L +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_HANG_NEED_FLR_MASK 0x00000004L +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_VM_BUSY_TRANSITION_MASK 0x00000008L +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_INST_SEL_MASK 0xF8000000L +//BIF_BX1_GFX_MMIOREG_CAM_ADDR0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR1 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR2 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR3 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR4 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR5 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR6 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR7 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_CNTL +#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL +//BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL +#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL +#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_0 +#define BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_1 +#define BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_2 +#define BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_3 +#define BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_4 +#define BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_5 +#define BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_6 +#define BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_7 +#define BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_8 +#define BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_9 +#define BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_10 +#define BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_11 +#define BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_12 +#define BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_13 +#define BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_14 +#define BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_15 +#define BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_0 +#define BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_1 +#define BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_2 +#define BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_3 +#define BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_4 +#define BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_5 +#define BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_6 +#define BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_7 +#define BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_8 +#define BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_9 +#define BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_10 +#define BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_11 +#define BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_12 +#define BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_13 +#define BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_14 +#define BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_15 +#define BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_4 +#define BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_5 +#define BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_6 +#define BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_7 +#define BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_8 +#define BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_9 +#define BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_10 +#define BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_11 +#define BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_12 +#define BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_13 +#define BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_14 +#define BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_15 +#define BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_pf_SYSPFVFDEC +//BIF_BX_PF1_MM_INDEX +#define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_PF1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_PF1_MM_DATA +#define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MM_INDEX_HI +#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_BIFDEC1 +//BIF_BX1_CC_BIF_BX_STRAP0 +#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19 +#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L +//BIF_BX1_CC_BIF_BX_PINSTRAP0 +//BIF_BX1_BIF_MM_INDACCESS_CNTL +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT 0x0 +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK 0x00000001L +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L +//BIF_BX1_BUS_CNTL +#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BIF_BX1_BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BIF_BX1_BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18 +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a +#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c +#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f +#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BIF_BX1_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L +#define BIF_BX1_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L +#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L +#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L +#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L +//BIF_BX1_BIF_SCRATCH0 +#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_SCRATCH1 +#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL +//BIF_BX1_BX_RESET_EN +#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L +//BIF_BX1_MM_CFGREGS_CNTL +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 +#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L +#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L +//BIF_BX1_BX_RESET_CNTL +#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L +//BIF_BX1_INTERRUPT_CNTL +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 +#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12 +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L +#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L +#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L +#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L +//BIF_BX1_INTERRUPT_CNTL2 +#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL +//BIF_BX1_CLKREQB_PAD_CNTL +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L +//BIF_BX1_BIF_FEATURES_CONTROL_MISC +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT 0xe +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x19 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK 0x00004000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x01FF0000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x02000000L +//BIF_BX1_HDP_ATOMIC_CONTROL_MISC +#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0 +#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL +//BIF_BX1_BIF_DOORBELL_CNTL +#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_LOCAL__SHIFT 0x5 +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L +#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L +#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L +#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L +#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L +#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_LOCAL_MASK 0x00000020L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L +//BIF_BX1_BIF_DOORBELL_INT_CNTL +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x17 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x00800000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L +//BIF_BX1_BIF_FB_EN +#define BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +//BIF_BX1_BIF_INTR_CNTL +#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 +#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L +//BIF_BX1_BIF_MST_TRANS_PENDING_VF +#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX1_BIF_SLV_TRANS_PENDING_VF +#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX1_BACO_CNTL +#define BIF_BX1_BACO_CNTL__BACO_EN__SHIFT 0x0 +#define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 +#define BIF_BX1_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +#define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 +#define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 +#define BIF_BX1_BACO_CNTL__BACO_MODE__SHIFT 0x8 +#define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 +#define BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT 0x10 +#define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f +#define BIF_BX1_BACO_CNTL__BACO_EN_MASK 0x00000001L +#define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L +#define BIF_BX1_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L +#define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L +#define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L +#define BIF_BX1_BACO_CNTL__BACO_MODE_MASK 0x00000100L +#define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L +#define BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC_MASK 0x00010000L +#define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L +//BIF_BX1_BIF_BACO_EXIT_TIME0 +#define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX1_BIF_BACO_EXIT_TIMER1 +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L +//BIF_BX1_BIF_BACO_EXIT_TIMER2 +#define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL +//BIF_BX1_BIF_BACO_EXIT_TIMER3 +#define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX1_BIF_BACO_EXIT_TIMER4 +#define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX1_MEM_TYPE_CNTL +#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L +//BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L +//BIF_BX1_NBIF_GFX_ADDR_LUT_0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_1 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_2 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_3 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_4 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_5 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_6 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_7 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_8 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_9 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_10 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_11 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_12 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_13 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_14 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_15 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_VF_REGWR_EN +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT 0x0 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT 0x1 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT 0x2 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT 0x3 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT 0x4 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT 0x5 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT 0x6 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT 0x7 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT 0x8 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT 0x9 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT 0xa +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT 0xb +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT 0xc +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT 0xd +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT 0xe +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT 0xf +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT 0x10 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT 0x11 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT 0x12 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT 0x13 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT 0x14 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT 0x15 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT 0x16 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT 0x17 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT 0x18 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT 0x19 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT 0x1a +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT 0x1b +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT 0x1c +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT 0x1d +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT 0x1e +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK 0x00000001L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK 0x00000002L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK 0x00000004L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK 0x00000008L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK 0x00000010L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK 0x00000020L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK 0x00000040L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK 0x00000080L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK 0x00000100L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK 0x00000200L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK 0x00000400L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK 0x00000800L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK 0x00001000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK 0x00002000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK 0x00004000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK 0x00008000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK 0x00010000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK 0x00020000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK 0x00040000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK 0x00080000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK 0x00100000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK 0x00200000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK 0x00400000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK 0x00800000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK 0x01000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK 0x02000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK 0x04000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK 0x08000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK 0x10000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK 0x20000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK 0x40000000L +//BIF_BX1_VF_DOORBELL_EN +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT 0x0 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT 0x1 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT 0x2 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT 0x3 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT 0x4 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT 0x5 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT 0x6 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT 0x7 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT 0x8 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT 0x9 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT 0xa +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT 0xb +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT 0xc +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT 0xd +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT 0xe +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT 0xf +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT 0x10 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT 0x11 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT 0x12 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT 0x13 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT 0x14 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT 0x15 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT 0x16 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT 0x17 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT 0x18 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT 0x19 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT 0x1a +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT 0x1b +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT 0x1c +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT 0x1d +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT 0x1e +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT 0x1f +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK 0x00000001L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK 0x00000002L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK 0x00000004L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK 0x00000008L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK 0x00000010L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK 0x00000020L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK 0x00000040L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK 0x00000080L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK 0x00000100L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK 0x00000200L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK 0x00000400L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK 0x00000800L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK 0x00001000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK 0x00002000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK 0x00004000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK 0x00008000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK 0x00010000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK 0x00020000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK 0x00040000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK 0x00080000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK 0x00100000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK 0x00200000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK 0x00400000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK 0x00800000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK 0x01000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK 0x02000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK 0x04000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK 0x08000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK 0x10000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK 0x20000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK 0x40000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK 0x80000000L +//BIF_BX1_VF_FB_EN +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0__SHIFT 0x0 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1__SHIFT 0x1 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2__SHIFT 0x2 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3__SHIFT 0x3 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4__SHIFT 0x4 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5__SHIFT 0x5 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6__SHIFT 0x6 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7__SHIFT 0x7 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8__SHIFT 0x8 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9__SHIFT 0x9 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10__SHIFT 0xa +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11__SHIFT 0xb +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12__SHIFT 0xc +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13__SHIFT 0xd +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14__SHIFT 0xe +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15__SHIFT 0xf +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16__SHIFT 0x10 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17__SHIFT 0x11 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18__SHIFT 0x12 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19__SHIFT 0x13 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20__SHIFT 0x14 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21__SHIFT 0x15 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22__SHIFT 0x16 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23__SHIFT 0x17 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24__SHIFT 0x18 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25__SHIFT 0x19 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26__SHIFT 0x1a +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27__SHIFT 0x1b +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28__SHIFT 0x1c +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29__SHIFT 0x1d +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30__SHIFT 0x1e +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0_MASK 0x00000001L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1_MASK 0x00000002L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2_MASK 0x00000004L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3_MASK 0x00000008L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4_MASK 0x00000010L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5_MASK 0x00000020L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6_MASK 0x00000040L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7_MASK 0x00000080L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8_MASK 0x00000100L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9_MASK 0x00000200L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10_MASK 0x00000400L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11_MASK 0x00000800L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12_MASK 0x00001000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13_MASK 0x00002000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14_MASK 0x00004000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15_MASK 0x00008000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16_MASK 0x00010000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17_MASK 0x00020000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18_MASK 0x00040000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19_MASK 0x00080000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20_MASK 0x00100000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21_MASK 0x00200000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22_MASK 0x00400000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23_MASK 0x00800000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24_MASK 0x01000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25_MASK 0x02000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26_MASK 0x04000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27_MASK 0x08000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28_MASK 0x10000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29_MASK 0x20000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30_MASK 0x40000000L +//BIF_BX1_VF_REGWR_STATUS +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT 0x0 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT 0x1 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT 0x2 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT 0x3 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT 0x4 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT 0x5 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT 0x6 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT 0x7 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT 0x8 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT 0x9 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT 0xa +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT 0xb +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT 0xc +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT 0xd +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT 0xe +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT 0xf +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT 0x10 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT 0x11 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT 0x12 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT 0x13 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT 0x14 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT 0x15 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT 0x16 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT 0x17 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT 0x18 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT 0x19 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT 0x1a +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT 0x1b +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT 0x1c +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT 0x1d +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT 0x1e +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK 0x00000001L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK 0x00000002L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK 0x00000004L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK 0x00000008L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK 0x00000010L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK 0x00000020L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK 0x00000040L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK 0x00000080L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK 0x00000100L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK 0x00000200L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK 0x00000400L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK 0x00000800L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK 0x00001000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK 0x00002000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK 0x00004000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK 0x00008000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK 0x00010000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK 0x00020000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK 0x00040000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK 0x00080000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK 0x00100000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK 0x00200000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK 0x00400000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK 0x00800000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK 0x01000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK 0x02000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK 0x04000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK 0x08000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK 0x10000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK 0x20000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK 0x40000000L +//BIF_BX1_VF_DOORBELL_STATUS +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT 0x0 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT 0x1 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT 0x2 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT 0x3 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT 0x4 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT 0x5 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT 0x6 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT 0x7 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT 0x8 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT 0x9 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT 0xa +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT 0xb +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT 0xc +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT 0xd +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT 0xe +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT 0xf +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT 0x10 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT 0x11 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT 0x12 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT 0x13 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT 0x14 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT 0x15 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT 0x16 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT 0x17 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT 0x18 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT 0x19 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT 0x1a +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT 0x1b +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT 0x1c +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT 0x1d +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT 0x1e +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK 0x00000001L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK 0x00000002L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK 0x00000004L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK 0x00000008L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK 0x00000010L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK 0x00000020L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK 0x00000040L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK 0x00000080L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK 0x00000100L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK 0x00000200L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK 0x00000400L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK 0x00000800L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK 0x00001000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK 0x00002000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK 0x00004000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK 0x00008000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK 0x00010000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK 0x00020000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK 0x00040000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK 0x00080000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK 0x00100000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK 0x00200000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK 0x00400000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK 0x00800000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK 0x01000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK 0x02000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK 0x04000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK 0x08000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK 0x10000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK 0x20000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK 0x40000000L +//BIF_BX1_VF_FB_STATUS +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT 0x0 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT 0x1 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT 0x2 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT 0x3 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT 0x4 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT 0x5 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT 0x6 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT 0x7 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT 0x8 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT 0x9 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT 0xa +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT 0xb +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT 0xc +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT 0xd +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT 0xe +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT 0xf +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT 0x10 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT 0x11 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT 0x12 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT 0x13 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT 0x14 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT 0x15 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT 0x16 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT 0x17 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT 0x18 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT 0x19 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT 0x1a +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT 0x1b +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT 0x1c +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT 0x1d +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT 0x1e +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK 0x00000001L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK 0x00000002L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK 0x00000004L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK 0x00000008L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK 0x00000010L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK 0x00000020L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK 0x00000040L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK 0x00000080L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK 0x00000100L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK 0x00000200L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK 0x00000400L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK 0x00000800L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK 0x00001000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK 0x00002000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK 0x00004000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK 0x00008000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK 0x00010000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK 0x00020000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK 0x00040000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK 0x00080000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK 0x00100000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK 0x00200000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK 0x00400000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK 0x00800000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK 0x01000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK 0x02000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK 0x04000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK 0x08000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK 0x10000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK 0x20000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK 0x40000000L +//BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL +#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL +#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX1_BIF_RB_CNTL +#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_BX1_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT 0x19 +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d +#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e +#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define BIF_BX1_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L +#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L +#define BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK 0x02000000L +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L +#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L +#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//BIF_BX1_BIF_RB_BASE +#define BIF_BX1_BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_BX1_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_RB_RPTR +#define BIF_BX1_BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_BX1_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX1_BIF_RB_WPTR +#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_BX1_BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L +#define BIF_BX1_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX1_BIF_RB_WPTR_ADDR_HI +#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL +//BIF_BX1_BIF_RB_WPTR_ADDR_LO +#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//BIF_BX1_MAILBOX_INDEX +#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 +#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL +//BIF_BX1_BACO_AZ_ENHANCE_CTRL +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET__SHIFT 0x2 +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE__SHIFT 0x10 +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO__SHIFT 0x11 +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO__SHIFT 0x1f +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET_MASK 0x00003FFCL +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE_MASK 0x00010000L +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO_MASK 0x00020000L +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO_MASK 0x80000000L +//BIF_BX1_BIF_MP1_INTR_CTRL +#define BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT 0x0 +#define BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK 0x00000001L +//BIF_BX1_BIF_PERSTB_PAD_CNTL +#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL +//BIF_BX1_BIF_PX_EN_PAD_CNTL +#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x00000FFFL +//BIF_BX1_BIF_REFPADKIN_PAD_CNTL +#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL +//BIF_BX1_BIF_CLKREQB_PAD_CNTL +#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x7FFFFFFFL +//BIF_BX1_BIF_PWRBRK_PAD_CNTL +#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL +//BIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE +#define BIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE__GPUIOV_SCH_CFG_SIZE__SHIFT 0x0 +#define BIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE__GPUIOV_SCH_CFG_SIZE_MASK 0x0000000FL + + +// addressBlock: nbif0_nbif0_bif_bx_pf_BIFPFVFDEC1 +//BIF_BX_PF1_BIF_BME_STATUS +#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_PF1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF1_GPU_HDP_FLUSH_REQ +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF1_GPU_HDP_FLUSH_DONE +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF1_BIF_TRANS_PENDING +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_CONTROL +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_PF1_MAILBOX_INT_CNTL +#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_PF1_BIF_VMHV_MAILBOX +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_PF1_PARTITION_COMPUTE_CAP +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_PF1_PARTITION_MEM_CAP +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_PF1_PARTITION_COMPUTE_STATUS +#define BIF_BX_PF1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_PF1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_PF1_PARTITION_MEM_STATUS +#define BIF_BX_PF1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_PF1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_PF1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_PF1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_rcc_strap_BIFDEC1:1 +//RCC_STRAP2_RCC_BIF_STRAP0 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x14 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN__SHIFT 0x15 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GPUIOV_EN__SHIFT 0x16 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE__SHIFT 0x17 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00100000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN_MASK 0x00200000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GPUIOV_EN_MASK 0x00400000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE_MASK 0x00800000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP1 +#define RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT__SHIFT 0x4 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT_MASK 0x00000010L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP10 +//RCC_STRAP2_RCC_BIF_STRAP11 +//RCC_STRAP2_RCC_BIF_STRAP12 +//RCC_STRAP2_RCC_BIF_STRAP13 +#define RCC_STRAP2_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER_MASK 0x00000FFFL +//RCC_STRAP2_RCC_BIF_STRAP2 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SPT__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWDS_SPT__SHIFT 0x2 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ARI_EN_UP__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SPT_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWDS_SPT_MASK 0x00000004L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ARI_EN_UP_MASK 0x02000000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP3 +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_BIF_STRAP4 +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_BIF_STRAP5 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP6 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL__SHIFT 0x3 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE__SHIFT 0x5 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6__SHIFT 0xf +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL_MASK 0x00000008L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE_MASK 0x00000020L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN_MASK 0x00007C00L +#define RCC_STRAP2_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6_MASK 0xFFFF8000L +//RCC_STRAP2_RCC_BIF_STRAP7 +#define RCC_STRAP2_RCC_BIF_STRAP7__STRAP_GEN6_DIS__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6__SHIFT 0x1a +#define RCC_STRAP2_RCC_BIF_STRAP7__STRAP_GEN6_DIS_MASK 0x02000000L +#define RCC_STRAP2_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6_MASK 0x04000000L +//RCC_STRAP2_RCC_BIF_STRAP8 +//RCC_STRAP2_RCC_BIF_STRAP9 +//RCC_STRAP2_RCC_DEV0_PORT_STRAP0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0_MASK 0x03000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0_MASK 0x0C000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x02000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0_MASK 0x38000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0_MASK 0x00000E00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0_MASK 0x00002000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0_MASK 0xFFFFFFFFL +//RCC_STRAP2_RCC_DEV0_PORT_STRAP16 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0_MASK 0xFFFFFFFFL +//RCC_STRAP2_RCC_DEV0_PORT_STRAP17 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0_MASK 0x0000E000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0_MASK 0x02000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0_MASK 0x0000000FL +//RCC_STRAP2_RCC_DEV0_PORT_STRAP2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP1 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0_MASK 0x000FF000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP19 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP2 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP22 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x0001F000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x003E0000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK 0x07C00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK 0xF8000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP23 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0_MASK 0xFFFFFFFFL +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP24 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0_MASK 0xFFFFFFFFL +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP3 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0_MASK 0x02000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP4 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP5 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP9 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0_MASK 0x10000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP1 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP10 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP11 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP12 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP13 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK 0x0000FFFFL +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP15 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1_MASK 0x00FFF000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1_MASK 0x01000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP16 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1_MASK 0x00FFF000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP17 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1_MASK 0x00001000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1_MASK 0x01FFE000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1_MASK 0x000FF000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP19 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP2 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP20 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP21 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP23 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP24 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP3 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1_MASK 0x02000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP4 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP5 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP6 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1__SHIFT 0xa +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000200L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1_MASK 0x00000400L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK 0x02000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1_MASK 0x08000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP7 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP8 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1_MASK 0xC0000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP9 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1_MASK 0x10000000L + + +// addressBlock: nbif0_hpdma0_hpdma_private_hpdma_private_regblk +//NBIF_SDP_PERF_COUNTER_2 +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_0_SEL__SHIFT 0x0 +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_1_SEL__SHIFT 0x8 +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_2_SEL__SHIFT 0x10 +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_3_SEL__SHIFT 0x18 +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_0_SEL_MASK 0x000000FFL +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_1_SEL_MASK 0x0000FF00L +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_2_SEL_MASK 0x00FF0000L +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_3_SEL_MASK 0xFF000000L +//NBIF_SHUB_TODET_CLIENT_STATUS3 +#define NBIF_SHUB_TODET_CLIENT_STATUS3__NBIF_SHUB_TODET_CLIENT_STATUS3__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_STATUS3__NBIF_SHUB_TODET_CLIENT_STATUS3_MASK 0x000003FFL +//BIF_AER_ERR_LOG_DEV0_F0 +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0__PASID_ERR_DEV0_F0__SHIFT 0x5 +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0__PASID_ERR_CLR_DEV0_F0__SHIFT 0x15 +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0__DMA_ON_BME_LOW_DEV0_F0_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0__PASID_ERR_DEV0_F0_MASK 0x00000020L +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK 0x00100000L +#define BIF_AER_ERR_LOG_DEV0_F0__PASID_ERR_CLR_DEV0_F0_MASK 0x00200000L +//BIF_AER_ERR_LOG_DEV0_F0_vf0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_OPCODE_DEV0_F0_vf0__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf0__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_LENGTH_DEV0_F0_vf0__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_NR_DEV0_F0_vf0__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__DMA_ON_BME_LOW_DEV0_F0_vf0__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf0__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf0__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf0__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf0__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf0__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_OPCODE_DEV0_F0_vf0_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf0_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_LENGTH_DEV0_F0_vf0_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_NR_DEV0_F0_vf0_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__DMA_ON_BME_LOW_DEV0_F0_vf0_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf0_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf0_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf0_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf0_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf0_MASK 0x00100000L +//BIF_AER_ERR_LOG_DEV0_F0_vf1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_OPCODE_DEV0_F0_vf1__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf1__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_LENGTH_DEV0_F0_vf1__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_NR_DEV0_F0_vf1__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__DMA_ON_BME_LOW_DEV0_F0_vf1__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf1__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf1__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf1__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf1__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf1__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_OPCODE_DEV0_F0_vf1_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf1_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_LENGTH_DEV0_F0_vf1_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_NR_DEV0_F0_vf1_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__DMA_ON_BME_LOW_DEV0_F0_vf1_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf1_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf1_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf1_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf1_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf1_MASK 0x00100000L +//BIF_AER_ERR_LOG_DEV0_F0_vf2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_OPCODE_DEV0_F0_vf2__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf2__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_LENGTH_DEV0_F0_vf2__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_NR_DEV0_F0_vf2__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__DMA_ON_BME_LOW_DEV0_F0_vf2__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf2__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf2__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf2__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf2__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf2__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_OPCODE_DEV0_F0_vf2_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf2_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_LENGTH_DEV0_F0_vf2_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_NR_DEV0_F0_vf2_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__DMA_ON_BME_LOW_DEV0_F0_vf2_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf2_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf2_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf2_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf2_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf2_MASK 0x00100000L +//BIF_AER_ERR_LOG_DEV0_F0_vf3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_OPCODE_DEV0_F0_vf3__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf3__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_LENGTH_DEV0_F0_vf3__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_NR_DEV0_F0_vf3__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__DMA_ON_BME_LOW_DEV0_F0_vf3__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf3__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf3__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf3__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf3__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf3__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_OPCODE_DEV0_F0_vf3_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf3_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_LENGTH_DEV0_F0_vf3_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_NR_DEV0_F0_vf3_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__DMA_ON_BME_LOW_DEV0_F0_vf3_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf3_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf3_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf3_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf3_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf3_MASK 0x00100000L +//BIF_AER_ERR_LOG_DEV0_F0_vf4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_OPCODE_DEV0_F0_vf4__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf4__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_LENGTH_DEV0_F0_vf4__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_NR_DEV0_F0_vf4__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__DMA_ON_BME_LOW_DEV0_F0_vf4__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf4__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf4__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf4__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf4__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf4__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_OPCODE_DEV0_F0_vf4_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf4_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_LENGTH_DEV0_F0_vf4_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_NR_DEV0_F0_vf4_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__DMA_ON_BME_LOW_DEV0_F0_vf4_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf4_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf4_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf4_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf4_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf4_MASK 0x00100000L +//BIF_AER_ERR_LOG_DEV0_F0_vf5 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_OPCODE_DEV0_F0_vf5__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf5__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_LENGTH_DEV0_F0_vf5__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_NR_DEV0_F0_vf5__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__DMA_ON_BME_LOW_DEV0_F0_vf5__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf5__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf5__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf5__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf5__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf5__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_OPCODE_DEV0_F0_vf5_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf5_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_LENGTH_DEV0_F0_vf5_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_NR_DEV0_F0_vf5_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__DMA_ON_BME_LOW_DEV0_F0_vf5_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf5_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf5_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf5_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf5_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf5_MASK 0x00100000L +//BIF_AER_ERR_LOG_DEV0_F0_vf6 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_OPCODE_DEV0_F0_vf6__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf6__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_LENGTH_DEV0_F0_vf6__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_NR_DEV0_F0_vf6__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__DMA_ON_BME_LOW_DEV0_F0_vf6__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf6__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf6__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf6__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf6__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf6__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_OPCODE_DEV0_F0_vf6_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf6_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_LENGTH_DEV0_F0_vf6_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_NR_DEV0_F0_vf6_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__DMA_ON_BME_LOW_DEV0_F0_vf6_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf6_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf6_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf6_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf6_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf6_MASK 0x00100000L +//BIF_AER_ERR_LOG_DEV0_F0_vf7 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_OPCODE_DEV0_F0_vf7__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf7__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_LENGTH_DEV0_F0_vf7__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_NR_DEV0_F0_vf7__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__DMA_ON_BME_LOW_DEV0_F0_vf7__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf7__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf7__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf7__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf7__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf7__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_OPCODE_DEV0_F0_vf7_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf7_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_LENGTH_DEV0_F0_vf7_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_NR_DEV0_F0_vf7_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__DMA_ON_BME_LOW_DEV0_F0_vf7_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf7_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf7_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf7_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf7_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf7_MASK 0x00100000L + + +// addressBlock: nbif0_hphost0_hphost_private_hphost_private_regblk +//NBIF_AON_SVA_DISABLE_SAD +#define NBIF_AON_SVA_DISABLE_SAD__NBIF_AON_SVA_DISABLE__SHIFT 0x0 +#define NBIF_AON_SVA_DISABLE_SAD__NBIF_AON_SVA_DISABLE_MASK 0x00000001L + + +// addressBlock: nbif0_nbif0_gdc_dma_sion_SIONDEC +//GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_Req_BurstTarget_REG0 +#define GDC_DMA_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_Req_BurstTarget_REG1 +#define GDC_DMA_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_Req_TimeSlot_REG0 +#define GDC_DMA_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_Req_TimeSlot_REG1 +#define GDC_DMA_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_Req_BurstTarget_REG0 +#define GDC_DMA_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_Req_BurstTarget_REG1 +#define GDC_DMA_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_Req_TimeSlot_REG0 +#define GDC_DMA_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_Req_TimeSlot_REG1 +#define GDC_DMA_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_Req_BurstTarget_REG0 +#define GDC_DMA_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_Req_BurstTarget_REG1 +#define GDC_DMA_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_Req_TimeSlot_REG0 +#define GDC_DMA_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_Req_TimeSlot_REG1 +#define GDC_DMA_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CNTL_REG0 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L +//GDC_DMA_SION_CNTL_REG1 +#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0 +#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_CG_OFF_HYSTERESIS__SHIFT 0x8 +#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL +#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_CG_OFF_HYSTERESIS_MASK 0x0000FF00L + + +// addressBlock: nbif0_nbif0_gdc_hst_sion_SIONDEC +//GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0 +#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1 +#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0 +#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1 +#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0 +#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1 +#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0 +#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1 +#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_Req_BurstTarget_REG0 +#define GDC_HST_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_Req_BurstTarget_REG1 +#define GDC_HST_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_Req_TimeSlot_REG0 +#define GDC_HST_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_Req_TimeSlot_REG1 +#define GDC_HST_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0 +#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1 +#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0 +#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1 +#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0 +#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1 +#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0 +#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1 +#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_Req_BurstTarget_REG0 +#define GDC_HST_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_Req_BurstTarget_REG1 +#define GDC_HST_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_Req_TimeSlot_REG0 +#define GDC_HST_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_Req_TimeSlot_REG1 +#define GDC_HST_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CNTL_REG0 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L +//GDC_HST_SION_CNTL_REG1 +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0 +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_CG_OFF_HYSTERESIS__SHIFT 0x8 +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVE_ACTIVE__SHIFT 0x10 +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_CG_OFF_HYSTERESIS_MASK 0x0000FF00L +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVE_ACTIVE_MASK 0xFFFF0000L + + +// addressBlock: nbif0_nbif0_gdc_GDCDEC +//GDC1_NGDC_SDP_PORT_CTRL +#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 +#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H__SHIFT 0x10 +#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_DIS__SHIFT 0x1f +#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x000000FFL +#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H_MASK 0x000F0000L +#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_DIS_MASK 0x80000000L +//GDC1_SHUB_REGS_IF_CTL +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT 0x1 +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK 0x00000002L +//GDC1_NGDC_MGCG_CTRL +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0 +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1 +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2 +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT 0xa +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT 0xb +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT 0xc +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT 0xd +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS__SHIFT 0xe +#define GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT 0xf +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003FCL +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK 0x00000400L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK 0x00000800L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK 0x00001000L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK 0x00002000L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS_MASK 0x00004000L +#define GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK 0x00008000L +//GDC1_S2A_MISC_CNTL +#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 +#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8 +#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa +#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc +#define GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT 0xf +#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10 +#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L +#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L +#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L +#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L +#define GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK 0x00008000L +#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L +//GDC1_NGDC_MCA_SMN_CTRL0 +#define GDC1_NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED__SHIFT 0x0 +#define GDC1_NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED_MASK 0x00000001L +//GDC1_NGDC_EARLY_WAKEUP_CTRL +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0 +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1 +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2 +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L +//GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_BYPASS__SHIFT 0x0 +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_ACCUM_SEL__SHIFT 0x1 +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_EN__SHIFT 0x2 +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_DATA__SHIFT 0x3 +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_STATUS_ACCUM_EN__SHIFT 0x4 +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_DATASTATUS_ACCUM_EN__SHIFT 0x5 +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_BYPASS_MASK 0x00000001L +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_ACCUM_SEL_MASK 0x00000002L +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_EN_MASK 0x00000004L +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_DATA_MASK 0x00000008L +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_STATUS_ACCUM_EN_MASK 0x00000010L +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_DATASTATUS_ACCUM_EN_MASK 0x00000020L +//GDC1_GDC_DMA_SION_PCTRL +#define GDC1_GDC_DMA_SION_PCTRL__BIF_SDP_DISCON_DIS__SHIFT 0x0 +#define GDC1_GDC_DMA_SION_PCTRL__SYSHUB_SDP_DISCON_DIS__SHIFT 0x3 +#define GDC1_GDC_DMA_SION_PCTRL__INT_SDP_DISCON_DIS__SHIFT 0x6 +#define GDC1_GDC_DMA_SION_PCTRL__BIF_SDP_DISCON_DIS_MASK 0x00000001L +#define GDC1_GDC_DMA_SION_PCTRL__SYSHUB_SDP_DISCON_DIS_MASK 0x00000008L +#define GDC1_GDC_DMA_SION_PCTRL__INT_SDP_DISCON_DIS_MASK 0x00000040L +//GDC1_NGDC_MP4SDP_CNTL +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN__SHIFT 0x0 +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL__SHIFT 0x1 +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN__SHIFT 0x4 +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL__SHIFT 0x5 +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN__SHIFT 0x8 +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL__SHIFT 0x9 +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN_MASK 0x00000001L +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL_MASK 0x00000006L +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN_MASK 0x00000010L +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL_MASK 0x00000060L +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN_MASK 0x00000100L +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL_MASK 0x00000600L +//GDC1_DOORBELL_VCN_TARGET_VF0 +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN0_TARGET_VF0__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN1_TARGET_VF0__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN2_TARGET_VF0__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN3_TARGET_VF0__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN0_TARGET_VF0_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN1_TARGET_VF0_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN2_TARGET_VF0_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN3_TARGET_VF0_MASK 0xF000L +//GDC1_DOORBELL_VCN_TARGET_VF1 +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN0_TARGET_VF1__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN1_TARGET_VF1__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN2_TARGET_VF1__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN3_TARGET_VF1__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN0_TARGET_VF1_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN1_TARGET_VF1_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN2_TARGET_VF1_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN3_TARGET_VF1_MASK 0xF000L +//GDC1_DOORBELL_VCN_TARGET_VF2 +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN0_TARGET_VF2__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN1_TARGET_VF2__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN2_TARGET_VF2__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN3_TARGET_VF2__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN0_TARGET_VF2_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN1_TARGET_VF2_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN2_TARGET_VF2_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN3_TARGET_VF2_MASK 0xF000L +//GDC1_DOORBELL_VCN_TARGET_VF3 +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN0_TARGET_VF3__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN1_TARGET_VF3__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN2_TARGET_VF3__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN3_TARGET_VF3__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN0_TARGET_VF3_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN1_TARGET_VF3_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN2_TARGET_VF3_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN3_TARGET_VF3_MASK 0xF000L +//GDC1_DOORBELL_VCN_TARGET_VF4 +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN0_TARGET_VF4__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN1_TARGET_VF4__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN2_TARGET_VF4__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN3_TARGET_VF4__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN0_TARGET_VF4_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN1_TARGET_VF4_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN2_TARGET_VF4_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN3_TARGET_VF4_MASK 0xF000L +//GDC1_DOORBELL_VCN_TARGET_VF5 +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN0_TARGET_VF5__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN1_TARGET_VF5__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN2_TARGET_VF5__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN3_TARGET_VF5__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN0_TARGET_VF5_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN1_TARGET_VF5_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN2_TARGET_VF5_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN3_TARGET_VF5_MASK 0xF000L +//GDC1_DOORBELL_VCN_TARGET_VF6 +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN0_TARGET_VF6__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN1_TARGET_VF6__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN2_TARGET_VF6__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN3_TARGET_VF6__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN0_TARGET_VF6_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN1_TARGET_VF6_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN2_TARGET_VF6_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN3_TARGET_VF6_MASK 0xF000L +//GDC1_DOORBELL_VCN_TARGET_VF7 +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN0_TARGET_VF7__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN1_TARGET_VF7__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN2_TARGET_VF7__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN3_TARGET_VF7__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN0_TARGET_VF7_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN1_TARGET_VF7_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN2_TARGET_VF7_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN3_TARGET_VF7_MASK 0xF000L +//GDC1_DOORBELL_ACCESS_EN_PF +#define GDC1_DOORBELL_ACCESS_EN_PF__DOORBELL_ACCESS_EN_PF__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_PF__DOORBELL_ACCESS_EN_PF_MASK 0x00FFL +//GDC1_DOORBELL_ACCESS_EN_VF0 +#define GDC1_DOORBELL_ACCESS_EN_VF0__DOORBELL_ACCESS_EN_VF0__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF0__XCD_ACCESS_EN_VF0__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF0__DOORBELL_ACCESS_EN_VF0_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF0__XCD_ACCESS_EN_VF0_MASK 0xFF00L +//GDC1_DOORBELL_ACCESS_EN_VF1 +#define GDC1_DOORBELL_ACCESS_EN_VF1__DOORBELL_ACCESS_EN_VF1__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF1__XCD_ACCESS_EN_VF1__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF1__DOORBELL_ACCESS_EN_VF1_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF1__XCD_ACCESS_EN_VF1_MASK 0xFF00L +//GDC1_DOORBELL_ACCESS_EN_VF2 +#define GDC1_DOORBELL_ACCESS_EN_VF2__DOORBELL_ACCESS_EN_VF2__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF2__XCD_ACCESS_EN_VF2__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF2__DOORBELL_ACCESS_EN_VF2_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF2__XCD_ACCESS_EN_VF2_MASK 0xFF00L +//GDC1_DOORBELL_ACCESS_EN_VF3 +#define GDC1_DOORBELL_ACCESS_EN_VF3__DOORBELL_ACCESS_EN_VF3__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF3__XCD_ACCESS_EN_VF3__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF3__DOORBELL_ACCESS_EN_VF3_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF3__XCD_ACCESS_EN_VF3_MASK 0xFF00L +//GDC1_DOORBELL_ACCESS_EN_VF4 +#define GDC1_DOORBELL_ACCESS_EN_VF4__DOORBELL_ACCESS_EN_VF4__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF4__XCD_ACCESS_EN_VF4__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF4__DOORBELL_ACCESS_EN_VF4_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF4__XCD_ACCESS_EN_VF4_MASK 0xFF00L +//GDC1_DOORBELL_ACCESS_EN_VF5 +#define GDC1_DOORBELL_ACCESS_EN_VF5__DOORBELL_ACCESS_EN_VF5__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF5__XCD_ACCESS_EN_VF5__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF5__DOORBELL_ACCESS_EN_VF5_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF5__XCD_ACCESS_EN_VF5_MASK 0xFF00L +//GDC1_DOORBELL_ACCESS_EN_VF6 +#define GDC1_DOORBELL_ACCESS_EN_VF6__DOORBELL_ACCESS_EN_VF6__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF6__XCD_ACCESS_EN_VF6__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF6__DOORBELL_ACCESS_EN_VF6_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF6__XCD_ACCESS_EN_VF6_MASK 0xFF00L +//GDC1_DOORBELL_ACCESS_EN_VF7 +#define GDC1_DOORBELL_ACCESS_EN_VF7__DOORBELL_ACCESS_EN_VF7__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF7__XCD_ACCESS_EN_VF7__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF7__DOORBELL_ACCESS_EN_VF7_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF7__XCD_ACCESS_EN_VF7_MASK 0xFF00L +//GDC1_NGDC_CNDI_BUS_PORT_CTRL +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_HYSTERESIS__SHIFT 0x0 +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_DIS_SOCCLK__SHIFT 0xc +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_HYSTERESIS__SHIFT 0xd +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_DIS_SOCCLK__SHIFT 0x19 +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_PORT_IDLE__SHIFT 0x1a +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__SHUB_CNDI_VDCI_CKEN_MASK__SHIFT 0x1b +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_HYSTERESIS_MASK 0x00000FFFL +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_DIS_SOCCLK_MASK 0x00001000L +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_HYSTERESIS_MASK 0x01FFE000L +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_DIS_SOCCLK_MASK 0x02000000L +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_PORT_IDLE_MASK 0x04000000L +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__SHUB_CNDI_VDCI_CKEN_MASK_MASK 0x08000000L +//GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC0_ALLOC__SHIFT 0x0 +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC1_ALLOC__SHIFT 0x4 +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC0_ALLOC__SHIFT 0x8 +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC1_ALLOC__SHIFT 0xc +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_REQ_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x10 +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_ORIGDATA_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x11 +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x12 +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x13 +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC0_ALLOC_MASK 0x0000000FL +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC1_ALLOC_MASK 0x000000F0L +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC0_ALLOC_MASK 0x00000F00L +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC1_ALLOC_MASK 0x0000F000L +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_REQ_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00010000L +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_ORIGDATA_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00020000L +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00040000L +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00080000L + + +// addressBlock: nbif0_nbif0_gdc_ras_gdc_ras_regblk +//GDCSOC_ERR_RSP_CNTL +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS__SHIFT 0x0 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL__SHIFT 0x1 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN__SHIFT 0x2 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA__SHIFT 0x3 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN__SHIFT 0x4 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN__SHIFT 0x5 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS_MASK 0x00000001L +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL_MASK 0x00000002L +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN_MASK 0x00000004L +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA_MASK 0x00000008L +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN_MASK 0x00000010L +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN_MASK 0x00000020L +//GDCSOC_RAS_CENTRAL_STATUS +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det__SHIFT 0x0 +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det__SHIFT 0x1 +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det__SHIFT 0x2 +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det__SHIFT 0x3 +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det_MASK 0x00000001L +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det_MASK 0x00000002L +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det_MASK 0x00000004L +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det_MASK 0x00000008L +//GDCSOC_RAS_LEAF0_CTRL +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF1_CTRL +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF2_CTRL +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF3_CTRL +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF4_CTRL +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF5_CTRL +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF6_CTRL +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF7_CTRL +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF8_CTRL +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF9_CTRL +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF10_CTRL +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF11_CTRL +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF12_CTRL +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF13_CTRL +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF0_STATUS +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF1_STATUS +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF2_STATUS +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF3_STATUS +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF4_STATUS +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF5_STATUS +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF6_STATUS +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF7_STATUS +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF8_STATUS +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF9_STATUS +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF10_STATUS +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF11_STATUS +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF12_STATUS +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF13_STATUS +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L + + +// addressBlock: nbif0_nbif0_gdc_sec_GDCSEC_DEC +//GDC_SEC_MCA_SMN_CTRL0 +#define GDC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_ADDR__SHIFT 0x0 +#define GDC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_APER_ID__SHIFT 0x14 +#define GDC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_ADDR_MASK 0x000FFFFFL +#define GDC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_APER_ID_MASK 0xFFF00000L +//GDC_SEC_MCA_SMN_CTRL1 +#define GDC_SEC_MCA_SMN_CTRL1__MCA_INT_REQ_MCM_ADDR__SHIFT 0x0 +#define GDC_SEC_MCA_SMN_CTRL1__MCA_SMN_SEC_FLAG__SHIFT 0x10 +#define GDC_SEC_MCA_SMN_CTRL1__MCA_INT_REQ_MCM_ADDR_MASK 0x0000FFFFL +#define GDC_SEC_MCA_SMN_CTRL1__MCA_SMN_SEC_FLAG_MASK 0x000F0000L +//XCD_DOORBELL_FENCE +#define XCD_DOORBELL_FENCE__XCD_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x0 +#define XCD_DOORBELL_FENCE__XCD_DOORBELL_FENCE_INTR_ENABLE__SHIFT 0x1 +#define XCD_DOORBELL_FENCE__RMOTE_SDMA_SENT__SHIFT 0x8 +#define XCD_DOORBELL_FENCE__SDMA_0_SENT__SHIFT 0x9 +#define XCD_DOORBELL_FENCE__SDMA_1_SENT__SHIFT 0xa +#define XCD_DOORBELL_FENCE__SDMA_2_SENT__SHIFT 0xb +#define XCD_DOORBELL_FENCE__SDMA_3_SENT__SHIFT 0xc +#define XCD_DOORBELL_FENCE__SDMA_4_SENT__SHIFT 0xd +#define XCD_DOORBELL_FENCE__SDMA_5_SENT__SHIFT 0xe +#define XCD_DOORBELL_FENCE__SDMA_6_SENT__SHIFT 0xf +#define XCD_DOORBELL_FENCE__SDMA_7_SENT__SHIFT 0x10 +#define XCD_DOORBELL_FENCE__RMOTE_CP_SENT__SHIFT 0x11 +#define XCD_DOORBELL_FENCE__CP_0_SENT__SHIFT 0x12 +#define XCD_DOORBELL_FENCE__CP_1_SENT__SHIFT 0x13 +#define XCD_DOORBELL_FENCE__CP_2_SENT__SHIFT 0x14 +#define XCD_DOORBELL_FENCE__CP_3_SENT__SHIFT 0x15 +#define XCD_DOORBELL_FENCE__CP_4_SENT__SHIFT 0x16 +#define XCD_DOORBELL_FENCE__CP_5_SENT__SHIFT 0x17 +#define XCD_DOORBELL_FENCE__CP_6_SENT__SHIFT 0x18 +#define XCD_DOORBELL_FENCE__CP_7_SENT__SHIFT 0x19 +#define XCD_DOORBELL_FENCE__REMOTE_CLIENT_SENT__SHIFT 0x1a +#define XCD_DOORBELL_FENCE__REMOTE_CLIENT_CLR_PENDING__SHIFT 0x1b +#define XCD_DOORBELL_FENCE__SHUB_SLV_MODE__SHIFT 0x1c +#define XCD_DOORBELL_FENCE__XCD_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00000001L +#define XCD_DOORBELL_FENCE__XCD_DOORBELL_FENCE_INTR_ENABLE_MASK 0x00000002L +#define XCD_DOORBELL_FENCE__RMOTE_SDMA_SENT_MASK 0x00000100L +#define XCD_DOORBELL_FENCE__SDMA_0_SENT_MASK 0x00000200L +#define XCD_DOORBELL_FENCE__SDMA_1_SENT_MASK 0x00000400L +#define XCD_DOORBELL_FENCE__SDMA_2_SENT_MASK 0x00000800L +#define XCD_DOORBELL_FENCE__SDMA_3_SENT_MASK 0x00001000L +#define XCD_DOORBELL_FENCE__SDMA_4_SENT_MASK 0x00002000L +#define XCD_DOORBELL_FENCE__SDMA_5_SENT_MASK 0x00004000L +#define XCD_DOORBELL_FENCE__SDMA_6_SENT_MASK 0x00008000L +#define XCD_DOORBELL_FENCE__SDMA_7_SENT_MASK 0x00010000L +#define XCD_DOORBELL_FENCE__RMOTE_CP_SENT_MASK 0x00020000L +#define XCD_DOORBELL_FENCE__CP_0_SENT_MASK 0x00040000L +#define XCD_DOORBELL_FENCE__CP_1_SENT_MASK 0x00080000L +#define XCD_DOORBELL_FENCE__CP_2_SENT_MASK 0x00100000L +#define XCD_DOORBELL_FENCE__CP_3_SENT_MASK 0x00200000L +#define XCD_DOORBELL_FENCE__CP_4_SENT_MASK 0x00400000L +#define XCD_DOORBELL_FENCE__CP_5_SENT_MASK 0x00800000L +#define XCD_DOORBELL_FENCE__CP_6_SENT_MASK 0x01000000L +#define XCD_DOORBELL_FENCE__CP_7_SENT_MASK 0x02000000L +#define XCD_DOORBELL_FENCE__REMOTE_CLIENT_SENT_MASK 0x04000000L +#define XCD_DOORBELL_FENCE__REMOTE_CLIENT_CLR_PENDING_MASK 0x08000000L +#define XCD_DOORBELL_FENCE__SHUB_SLV_MODE_MASK 0x10000000L +//SHUB_PWRBRK_DEGLITCH +#define SHUB_PWRBRK_DEGLITCH__SHUB_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x0 +#define SHUB_PWRBRK_DEGLITCH__SHUB_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x8 +#define SHUB_PWRBRK_DEGLITCH__SHUB_PWRBRK_DEGLITCH_CYCLE_MASK 0x000000FFL +#define SHUB_PWRBRK_DEGLITCH__SHUB_PWRBRK_DEGLITCH_BYPASS_MASK 0x00000100L +//SHUB_DIE_CTRL +#define SHUB_DIE_CTRL__SHUB_MST_DIE__SHIFT 0x0 +#define SHUB_DIE_CTRL__SHUB_MST_DIE_MASK 0x00000001L +//GDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL +#define GDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL__GDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL__SHIFT 0x0 +#define GDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL__GDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL_MASK 0x00000007L +//XCD_DOORBELL_FENCE_1 +#define XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_FENCE__SHIFT 0x0 +#define XCD_DOORBELL_FENCE_1__XCD_1_DOORBELL_FENCE__SHIFT 0x1 +#define XCD_DOORBELL_FENCE_1__XCD_2_DOORBELL_FENCE__SHIFT 0x2 +#define XCD_DOORBELL_FENCE_1__XCD_3_DOORBELL_FENCE__SHIFT 0x3 +#define XCD_DOORBELL_FENCE_1__XCD_4_DOORBELL_FENCE__SHIFT 0x4 +#define XCD_DOORBELL_FENCE_1__XCD_5_DOORBELL_FENCE__SHIFT 0x5 +#define XCD_DOORBELL_FENCE_1__XCD_6_DOORBELL_FENCE__SHIFT 0x6 +#define XCD_DOORBELL_FENCE_1__XCD_7_DOORBELL_FENCE__SHIFT 0x7 +#define XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_DISABLE__SHIFT 0x8 +#define XCD_DOORBELL_FENCE_1__XCD_1_DOORBELL_DISABLE__SHIFT 0x9 +#define XCD_DOORBELL_FENCE_1__XCD_2_DOORBELL_DISABLE__SHIFT 0xa +#define XCD_DOORBELL_FENCE_1__XCD_3_DOORBELL_DISABLE__SHIFT 0xb +#define XCD_DOORBELL_FENCE_1__XCD_4_DOORBELL_DISABLE__SHIFT 0xc +#define XCD_DOORBELL_FENCE_1__XCD_5_DOORBELL_DISABLE__SHIFT 0xd +#define XCD_DOORBELL_FENCE_1__XCD_6_DOORBELL_DISABLE__SHIFT 0xe +#define XCD_DOORBELL_FENCE_1__XCD_7_DOORBELL_DISABLE__SHIFT 0xf +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_0_REG__SHIFT 0x10 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_1_REG__SHIFT 0x11 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_2_REG__SHIFT 0x12 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_3_REG__SHIFT 0x13 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_4_REG__SHIFT 0x14 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_5_REG__SHIFT 0x15 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_6_REG__SHIFT 0x16 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_7_REG__SHIFT 0x17 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_0_REG__SHIFT 0x18 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_1_REG__SHIFT 0x19 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_2_REG__SHIFT 0x1a +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_3_REG__SHIFT 0x1b +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_4_REG__SHIFT 0x1c +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_5_REG__SHIFT 0x1d +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_6_REG__SHIFT 0x1e +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_7_REG__SHIFT 0x1f +#define XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_FENCE_MASK 0x00000001L +#define XCD_DOORBELL_FENCE_1__XCD_1_DOORBELL_FENCE_MASK 0x00000002L +#define XCD_DOORBELL_FENCE_1__XCD_2_DOORBELL_FENCE_MASK 0x00000004L +#define XCD_DOORBELL_FENCE_1__XCD_3_DOORBELL_FENCE_MASK 0x00000008L +#define XCD_DOORBELL_FENCE_1__XCD_4_DOORBELL_FENCE_MASK 0x00000010L +#define XCD_DOORBELL_FENCE_1__XCD_5_DOORBELL_FENCE_MASK 0x00000020L +#define XCD_DOORBELL_FENCE_1__XCD_6_DOORBELL_FENCE_MASK 0x00000040L +#define XCD_DOORBELL_FENCE_1__XCD_7_DOORBELL_FENCE_MASK 0x00000080L +#define XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_DISABLE_MASK 0x00000100L +#define XCD_DOORBELL_FENCE_1__XCD_1_DOORBELL_DISABLE_MASK 0x00000200L +#define XCD_DOORBELL_FENCE_1__XCD_2_DOORBELL_DISABLE_MASK 0x00000400L +#define XCD_DOORBELL_FENCE_1__XCD_3_DOORBELL_DISABLE_MASK 0x00000800L +#define XCD_DOORBELL_FENCE_1__XCD_4_DOORBELL_DISABLE_MASK 0x00001000L +#define XCD_DOORBELL_FENCE_1__XCD_5_DOORBELL_DISABLE_MASK 0x00002000L +#define XCD_DOORBELL_FENCE_1__XCD_6_DOORBELL_DISABLE_MASK 0x00004000L +#define XCD_DOORBELL_FENCE_1__XCD_7_DOORBELL_DISABLE_MASK 0x00008000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_0_REG_MASK 0x00010000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_1_REG_MASK 0x00020000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_2_REG_MASK 0x00040000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_3_REG_MASK 0x00080000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_4_REG_MASK 0x00100000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_5_REG_MASK 0x00200000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_6_REG_MASK 0x00400000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_7_REG_MASK 0x00800000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_0_REG_MASK 0x01000000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_1_REG_MASK 0x02000000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_2_REG_MASK 0x04000000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_3_REG_MASK 0x08000000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_4_REG_MASK 0x10000000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_5_REG_MASK 0x20000000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_6_REG_MASK 0x40000000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_7_REG_MASK 0x80000000L +//NGDC_CNDI_DOORBELL_REQUSER_0 +#define NGDC_CNDI_DOORBELL_REQUSER_0__NGDC_CNDI_IH_ReqUser__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQUSER_0__NGDC_CNDI_IH_ReqUser_MASK 0x0000003FL +//NGDC_CNDI_DOORBELL_REQUSER_1 +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN0_ReqUser__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN1_ReqUser__SHIFT 0x8 +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN2_ReqUser__SHIFT 0x10 +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN3_ReqUser__SHIFT 0x18 +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN0_ReqUser_MASK 0x0000003FL +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN1_ReqUser_MASK 0x00003F00L +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN2_ReqUser_MASK 0x003F0000L +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN3_ReqUser_MASK 0x3F000000L +//NGDC_CNDI_DOORBELL_REQUSER_2 +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD0_SDMA_ReqUser__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD1_SDMA_ReqUser__SHIFT 0x8 +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD2_SDMA_ReqUser__SHIFT 0x10 +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD3_SDMA_ReqUser__SHIFT 0x18 +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD0_SDMA_ReqUser_MASK 0x0000003FL +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD1_SDMA_ReqUser_MASK 0x00003F00L +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD2_SDMA_ReqUser_MASK 0x003F0000L +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD3_SDMA_ReqUser_MASK 0x3F000000L +//NGDC_CNDI_DOORBELL_REQUSER_3 +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD4_SDMA_ReqUser__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD5_SDMA_ReqUser__SHIFT 0x8 +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD6_SDMA_ReqUser__SHIFT 0x10 +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD7_SDMA_ReqUser__SHIFT 0x18 +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD4_SDMA_ReqUser_MASK 0x0000003FL +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD5_SDMA_ReqUser_MASK 0x00003F00L +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD6_SDMA_ReqUser_MASK 0x003F0000L +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD7_SDMA_ReqUser_MASK 0x3F000000L +//NGDC_CNDI_DOORBELL_REQUSER_4 +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD0_CP_ReqUser__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD1_CP_ReqUser__SHIFT 0x8 +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD2_CP_ReqUser__SHIFT 0x10 +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD3_CP_ReqUser__SHIFT 0x18 +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD0_CP_ReqUser_MASK 0x0000003FL +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD1_CP_ReqUser_MASK 0x00003F00L +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD2_CP_ReqUser_MASK 0x003F0000L +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD3_CP_ReqUser_MASK 0x3F000000L +//NGDC_CNDI_DOORBELL_REQUSER_5 +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD4_CP_ReqUser__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD5_CP_ReqUser__SHIFT 0x8 +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD6_CP_ReqUser__SHIFT 0x10 +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD7_CP_ReqUser__SHIFT 0x18 +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD4_CP_ReqUser_MASK 0x0000003FL +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD5_CP_ReqUser_MASK 0x00003F00L +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD6_CP_ReqUser_MASK 0x003F0000L +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD7_CP_ReqUser_MASK 0x3F000000L +//NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_IH_REQADDR_32_33BIT__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN0_REQADDR_32_33BIT__SHIFT 0x2 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN1_REQADDR_32_33BIT__SHIFT 0x4 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN2_REQADDR_32_33BIT__SHIFT 0x6 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN3_REQADDR_32_33BIT__SHIFT 0x8 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD0_SDMA_REQADDR_32_33BIT__SHIFT 0xa +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD1_SDMA_REQADDR_32_33BIT__SHIFT 0xc +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD2_SDMA_REQADDR_32_33BIT__SHIFT 0xe +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD3_SDMA_REQADDR_32_33BIT__SHIFT 0x10 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD4_SDMA_REQADDR_32_33BIT__SHIFT 0x12 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD5_SDMA_REQADDR_32_33BIT__SHIFT 0x14 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD6_SDMA_REQADDR_32_33BIT__SHIFT 0x16 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD7_SDMA_REQADDR_32_33BIT__SHIFT 0x18 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_IH_REQADDR_32_33BIT_MASK 0x00000003L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN0_REQADDR_32_33BIT_MASK 0x0000000CL +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN1_REQADDR_32_33BIT_MASK 0x00000030L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN2_REQADDR_32_33BIT_MASK 0x000000C0L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN3_REQADDR_32_33BIT_MASK 0x00000300L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD0_SDMA_REQADDR_32_33BIT_MASK 0x00000C00L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD1_SDMA_REQADDR_32_33BIT_MASK 0x00003000L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD2_SDMA_REQADDR_32_33BIT_MASK 0x0000C000L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD3_SDMA_REQADDR_32_33BIT_MASK 0x00030000L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD4_SDMA_REQADDR_32_33BIT_MASK 0x000C0000L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD5_SDMA_REQADDR_32_33BIT_MASK 0x00300000L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD6_SDMA_REQADDR_32_33BIT_MASK 0x00C00000L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD7_SDMA_REQADDR_32_33BIT_MASK 0x03000000L +//NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD0_CP_REQADDR_32_33BIT__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD1_CP_REQADDR_32_33BIT__SHIFT 0x2 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD2_CP_REQADDR_32_33BIT__SHIFT 0x4 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD3_CP_REQADDR_32_33BIT__SHIFT 0x6 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD4_CP_REQADDR_32_33BIT__SHIFT 0x8 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD5_CP_REQADDR_32_33BIT__SHIFT 0xa +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD6_CP_REQADDR_32_33BIT__SHIFT 0xc +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD7_CP_REQADDR_32_33BIT__SHIFT 0xe +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD0_CP_REQADDR_32_33BIT_MASK 0x00000003L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD1_CP_REQADDR_32_33BIT_MASK 0x0000000CL +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD2_CP_REQADDR_32_33BIT_MASK 0x00000030L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD3_CP_REQADDR_32_33BIT_MASK 0x000000C0L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD4_CP_REQADDR_32_33BIT_MASK 0x00000300L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD5_CP_REQADDR_32_33BIT_MASK 0x00000C00L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD6_CP_REQADDR_32_33BIT_MASK 0x00003000L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD7_CP_REQADDR_32_33BIT_MASK 0x0000C000L + + +// addressBlock: nbif0_nbif0_gdc_rst_GDCRST_DEC +//SHUB_PF_FLR_RST +#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 +#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 +#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L +#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L +//SHUB_GFX_DRV_VPU_RST +#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT 0x0 +#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK 0x00000001L +//SHUB_LINK_RESET +#define SHUB_LINK_RESET__LINK_P0_RESET__SHIFT 0x0 +#define SHUB_LINK_RESET__LINK_P1_RESET__SHIFT 0x1 +#define SHUB_LINK_RESET__LINK_P2_RESET__SHIFT 0x2 +#define SHUB_LINK_RESET__LINK_P3_RESET__SHIFT 0x3 +#define SHUB_LINK_RESET__LINK_P0_RESET_MASK 0x00000001L +#define SHUB_LINK_RESET__LINK_P1_RESET_MASK 0x00000002L +#define SHUB_LINK_RESET__LINK_P2_RESET_MASK 0x00000004L +#define SHUB_LINK_RESET__LINK_P3_RESET_MASK 0x00000008L +//SHUB_HST_NIC400_SW_CTRL_RESET +#define SHUB_HST_NIC400_SW_CTRL_RESET__HST_NIC400_SW_CTRL_RESET__SHIFT 0x0 +#define SHUB_HST_NIC400_SW_CTRL_RESET__HST_NIC400_SW_CTRL_RESET_MASK 0x00000001L +//SHUB_DEV0_PF0_VF_FLR_RST +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF0_FLR_RST__SHIFT 0x0 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF1_FLR_RST__SHIFT 0x1 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF2_FLR_RST__SHIFT 0x2 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF3_FLR_RST__SHIFT 0x3 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF4_FLR_RST__SHIFT 0x4 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF5_FLR_RST__SHIFT 0x5 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF6_FLR_RST__SHIFT 0x6 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF7_FLR_RST__SHIFT 0x7 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_SOFTPF_FLR_RST__SHIFT 0x1f +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF0_FLR_RST_MASK 0x00000001L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF1_FLR_RST_MASK 0x00000002L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF2_FLR_RST_MASK 0x00000004L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF3_FLR_RST_MASK 0x00000008L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF4_FLR_RST_MASK 0x00000010L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF5_FLR_RST_MASK 0x00000020L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF6_FLR_RST_MASK 0x00000040L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF7_FLR_RST_MASK 0x00000080L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_SOFTPF_FLR_RST_MASK 0x80000000L +//SHUB_DEV0_PF1_VF_FLR_RST +#define SHUB_DEV0_PF1_VF_FLR_RST__DEV0_PF1_VF0_FLR_RST__SHIFT 0x0 +#define SHUB_DEV0_PF1_VF_FLR_RST__DEV0_PF1_VF0_FLR_RST_MASK 0x00000001L +//SHUB_HARD_RST_CTRL +#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0 +#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1 +#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2 +#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 +#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 +#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5 +#define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK 0x00000001L +#define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK 0x00000002L +#define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK 0x00000004L +#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L +#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L +#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L +//SHUB_SOFT_RST_CTRL +#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0 +#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1 +#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2 +#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 +#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 +#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5 +#define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK 0x00000001L +#define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK 0x00000002L +#define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK 0x00000004L +#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L +#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L +#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L +//SHUB_SDP_PORT_RST +#define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST__SHIFT 0x0 +#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST__SHIFT 0x1 +#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT 0x2 +#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST__SHIFT 0x3 +#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT 0x4 +#define SHUB_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST__SHIFT 0x5 +#define SHUB_SDP_PORT_RST__MP4_SDP_SDP_PORT_RST__SHIFT 0x6 +#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST__SHIFT 0x7 +#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT 0x8 +#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT 0x9 +#define SHUB_SDP_PORT_RST__DACCFE_NBIF_DMA_SDP_PORT_RST__SHIFT 0xa +#define SHUB_SDP_PORT_RST__DACCBE_NBIF_DMA_SDP_PORT_RST__SHIFT 0xb +#define SHUB_SDP_PORT_RST__DACCFE_HST_SDP_PORT_RST__SHIFT 0xc +#define SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST__SHIFT 0xd +#define SHUB_SDP_PORT_RST__HST_ATHUB_HST_SION_SDP_PORT_RST__SHIFT 0xe +#define SHUB_SDP_PORT_RST__SION_AON_RST__SHIFT 0x18 +#define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST_MASK 0x00000001L +#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST_MASK 0x00000002L +#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK 0x00000004L +#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST_MASK 0x00000008L +#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK 0x00000010L +#define SHUB_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST_MASK 0x00000020L +#define SHUB_SDP_PORT_RST__MP4_SDP_SDP_PORT_RST_MASK 0x00000040L +#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST_MASK 0x00000080L +#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK 0x00000100L +#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK 0x00000200L +#define SHUB_SDP_PORT_RST__DACCFE_NBIF_DMA_SDP_PORT_RST_MASK 0x00000400L +#define SHUB_SDP_PORT_RST__DACCBE_NBIF_DMA_SDP_PORT_RST_MASK 0x00000800L +#define SHUB_SDP_PORT_RST__DACCFE_HST_SDP_PORT_RST_MASK 0x00001000L +#define SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST_MASK 0x00002000L +#define SHUB_SDP_PORT_RST__HST_ATHUB_HST_SION_SDP_PORT_RST_MASK 0x00004000L +#define SHUB_SDP_PORT_RST__SION_AON_RST_MASK 0x01000000L +//SHUB_RST_MISC_TRL + + +// addressBlock: nbif0_nbif0_gdc_s2a_GDCS2A_DEC +//GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG +#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE_MASK 0x00000002L +//GDC_S2A1_NBIF_GFX_DOORBELL_STATUS +#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0 +#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN__SHIFT 0x10 +#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST__SHIFT 0x18 +#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x0000FFFFL +#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN_MASK 0x00010000L +#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST_MASK 0x01000000L + + +// addressBlock: nbif0_nbif0_gdc_misc_GDCMISC_DEC +//GDC_DMA_SION_CRED_RST +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_CRED_RST__SHIFT 0x0 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_SDP_TX_DS_MSK__SHIFT 0x1 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_SDP_RX_DS_MSK__SHIFT 0x2 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_CRED_RST__SHIFT 0x4 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_SDP_TX_DS_MSK__SHIFT 0x5 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_SDP_RX_DS_MSK__SHIFT 0x6 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_CRED_RST__SHIFT 0x8 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_SDP_TX_DS_MSK__SHIFT 0x9 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_SDP_RX_DS_MSK__SHIFT 0xa +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_CRED_RST_MASK 0x00000001L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_SDP_TX_DS_MSK_MASK 0x00000002L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_SDP_RX_DS_MSK_MASK 0x00000004L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_CRED_RST_MASK 0x00000010L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_SDP_TX_DS_MSK_MASK 0x00000020L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_SDP_RX_DS_MSK_MASK 0x00000040L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_CRED_RST_MASK 0x00000100L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_SDP_TX_DS_MSK_MASK 0x00000200L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_SDP_RX_DS_MSK_MASK 0x00000400L +//GDC_HST_SION_PER_SDP_PORT_RST +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_CRED_RST__SHIFT 0x0 +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_GSI_SDP_PORT_RST__SHIFT 0x1 +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_GSI_SDP_DISCON_DIS__SHIFT 0x2 +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_SDP_TX_DS_MSK__SHIFT 0x3 +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_SDP_RX_DS_MSK__SHIFT 0x4 +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_CRED_RST__SHIFT 0x5 +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_HSTHB_DB0_SDP_PORT_RST__SHIFT 0x6 +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_HSTHB_DB0_SDP_DISCON_DIS__SHIFT 0x7 +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_SDP_TX_DS_MSK__SHIFT 0x8 +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_SDP_RX_DS_MSK__SHIFT 0x9 +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_CRED_RST_MASK 0x00000001L +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_GSI_SDP_PORT_RST_MASK 0x00000002L +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_GSI_SDP_DISCON_DIS_MASK 0x00000004L +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_SDP_TX_DS_MSK_MASK 0x00000008L +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_SDP_RX_DS_MSK_MASK 0x00000010L +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_CRED_RST_MASK 0x00000020L +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_HSTHB_DB0_SDP_PORT_RST_MASK 0x00000040L +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_HSTHB_DB0_SDP_DISCON_DIS_MASK 0x00000080L +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_SDP_TX_DS_MSK_MASK 0x00000100L +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_SDP_RX_DS_MSK_MASK 0x00000200L +//GDC_HST_SION_PER_SDP_CNTL_REG1 +//GDC_HST_AXI_STALL_FOR_FLUSH +#define GDC_HST_AXI_STALL_FOR_FLUSH__SHUB_HST_AXI_STALL_FOR_FLUSH_GFX__SHIFT 0x0 +#define GDC_HST_AXI_STALL_FOR_FLUSH__SHUB_HST_AXI_STALL_FOR_FLUSH_GFX_MASK 0x00000001L +//SYSHUB_SDP_DEBUG_COUNTER_CTRL +#define SYSHUB_SDP_DEBUG_COUNTER_CTRL__SHUB_SDP_DEBUG_COUNTER_EN__SHIFT 0x0 +#define SYSHUB_SDP_DEBUG_COUNTER_CTRL__SHUB_SDP_DEBUG_COUNTER_EN_MASK 0x00000001L +//NBIF_PWRBRK_IN_PAD_CNTL +#define NBIF_PWRBRK_IN_PAD_CNTL__PWRBRK_IN_PAD_CNTL_BIT0__SHIFT 0x0 +#define NBIF_PWRBRK_IN_PAD_CNTL__PWRBRK_IN_PAD_CNTL__SHIFT 0x1 +#define NBIF_PWRBRK_IN_PAD_CNTL__PWRBRK_IN_PAD_CNTL_BIT0_MASK 0x00000001L +#define NBIF_PWRBRK_IN_PAD_CNTL__PWRBRK_IN_PAD_CNTL_MASK 0x000000FEL +//NBIF_PWRBRK_OUT_PAD_CNTL +#define NBIF_PWRBRK_OUT_PAD_CNTL__PWRBRK_OUT_PAD_CNTL_BIT0__SHIFT 0x0 +#define NBIF_PWRBRK_OUT_PAD_CNTL__PWRBRK_OUT_PAD_CNTL__SHIFT 0x1 +#define NBIF_PWRBRK_OUT_PAD_CNTL__PWRBRK_OUT_PAD_CNTL_BIT0_MASK 0x00000001L +#define NBIF_PWRBRK_OUT_PAD_CNTL__PWRBRK_OUT_PAD_CNTL_MASK 0x000000FEL +//SHUB_OOB_CRUSH_DUMP_CTRL +#define SHUB_OOB_CRUSH_DUMP_CTRL__REGS_SHUB_OOB_TRIGGER__SHIFT 0x0 +#define SHUB_OOB_CRUSH_DUMP_CTRL__REGS_SHUB_OOB_TRIGGER_MASK 0x00000001L +//SHUB_MP_ERREVENT_MASK_CTRL +#define SHUB_MP_ERREVENT_MASK_CTRL__SHUB_MP_ERREVENT_MASK_EN__SHIFT 0x0 +#define SHUB_MP_ERREVENT_MASK_CTRL__MCA_FATAL_OUT_PROP_EN__SHIFT 0x1 +#define SHUB_MP_ERREVENT_MASK_CTRL__SHUB_MP_ERREVENT_MASK_EN_MASK 0x00000001L +#define SHUB_MP_ERREVENT_MASK_CTRL__MCA_FATAL_OUT_PROP_EN_MASK 0x00000002L +//SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT0_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x0 +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT1_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x1 +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT2_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x2 +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT3_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x3 +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT4_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x4 +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT0_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000001L +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT1_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000002L +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT2_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000004L +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT3_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000008L +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT4_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000010L +//SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT0_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x0 +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT1_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x1 +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT2_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x2 +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT3_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x3 +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT4_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x4 +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT0_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000001L +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT1_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000002L +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT2_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000004L +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT3_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000008L +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT4_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000010L + + +// addressBlock: nbif0_nbif0_gdc_sec_misc_GDCSEC_MISC_DEC +//GDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI__DMACK0V3_EGRESS_RDATA_POISON_INJ__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI__DMACK0V3_EGRESS_RDATA_POISON_INJ_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI__DMACK0V3_EGRESS_RDATA_POISON_INJ_CNT__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI__DMACK0V3_EGRESS_RDATA_POISON_INJ_CNT_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V3_AXI +//GDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI__DMACK0B_EGRESS_RDATA_POISON_INJ__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI__DMACK0B_EGRESS_RDATA_POISON_INJ_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI__DMACK0B_EGRESS_RDATA_POISON_INJ_CNT__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI__DMACK0B_EGRESS_RDATA_POISON_INJ_CNT_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B_AXI +//GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI__DMACK0V4_EGRESS_RDATA_POISON_INJ__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI__DMACK0V4_EGRESS_RDATA_POISON_INJ_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI__DMACK0V4_EGRESS_RDATA_POISON_INJ_CNT__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI__DMACK0V4_EGRESS_RDATA_POISON_INJ_CNT_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4_AXI +//GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI__DMACK0V4B_EGRESS_RDATA_POISON_INJ__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI__DMACK0V4B_EGRESS_RDATA_POISON_INJ_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI__DMACK0V4B_EGRESS_RDATA_POISON_INJ_CNT__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI__DMACK0V4B_EGRESS_RDATA_POISON_INJ_CNT_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4B_AXI +//GDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI__DMACK0V7_EGRESS_RDATA_POISON_INJ__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI__DMACK0V7_EGRESS_RDATA_POISON_INJ_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI__DMACK0V7_EGRESS_RDATA_POISON_INJ_CNT__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI__DMACK0V7_EGRESS_RDATA_POISON_INJ_CNT_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V7_AXI +//GDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP +#define GDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_POISON_INJ__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_PARITY_INJ__SHIFT 0xc +#define GDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_POISON_INJ_MASK 0x00000F00L +#define GDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_PARITY_INJ_MASK 0x0000F000L +//GDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT__SHIFT 0xc +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT_MASK 0x00000F00L +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT_MASK 0x0000F000L +//GDCSOC_SEC_DFV_POISON_INJ_LOG_SHUB_CNDI_ORIG_SDP +//GDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI__DMACK0B1_EGRESS_RDATA_POISON_INJ__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI__DMACK0B1_EGRESS_RDATA_POISON_INJ_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI__DMACK0B1_EGRESS_RDATA_POISON_INJ_CNT__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI__DMACK0B1_EGRESS_RDATA_POISON_INJ_CNT_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B1_AXI +//GDCSOC_SEC_RAS_POISON_DBUG_CTRL +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_POISON_DBUG_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_POISON_DBUG_EN__SHIFT 0x1 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_POISON_DBUG_EN__SHIFT 0x2 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_POISON_DBUG_EN__SHIFT 0x3 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_POISON_DBUG_EN__SHIFT 0x4 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_POISON_DBUG_EN__SHIFT 0x5 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_POISON_DBUG_EN__SHIFT 0x6 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_POISON_DBUG_EN__SHIFT 0x7 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_POISON_DBUG_EN__SHIFT 0x8 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_POISON_DBUG_EN__SHIFT 0x9 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_POISON_DBUG_EN__SHIFT 0xa +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_POISON_DBUG_EN__SHIFT 0xb +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_POISON_DBUG_EN__SHIFT 0xc +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_POISON_DBUG_EN__SHIFT 0xd +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_POISON_DBUG_EN_MASK 0x00000001L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_POISON_DBUG_EN_MASK 0x00000002L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_POISON_DBUG_EN_MASK 0x00000004L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_POISON_DBUG_EN_MASK 0x00000008L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_POISON_DBUG_EN_MASK 0x00000010L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_POISON_DBUG_EN_MASK 0x00000020L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_POISON_DBUG_EN_MASK 0x00000040L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_POISON_DBUG_EN_MASK 0x00000080L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_POISON_DBUG_EN_MASK 0x00000100L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_POISON_DBUG_EN_MASK 0x00000200L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_POISON_DBUG_EN_MASK 0x00000400L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_POISON_DBUG_EN_MASK 0x00000800L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_POISON_DBUG_EN_MASK 0x00001000L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_POISON_DBUG_EN_MASK 0x00002000L +//GDCSOC_SEC_RAS_PARITY_DBUG_CTRL +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_PARITY_DBUG_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_PARITY_DBUG_EN__SHIFT 0x1 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_PARITY_DBUG_EN__SHIFT 0x2 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_PARITY_DBUG_EN__SHIFT 0x3 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_PARITY_DBUG_EN__SHIFT 0x4 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_PARITY_DBUG_EN__SHIFT 0x5 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_PARITY_DBUG_EN__SHIFT 0x6 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_PARITY_DBUG_EN__SHIFT 0x7 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_PARITY_DBUG_EN__SHIFT 0x8 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_PARITY_DBUG_EN__SHIFT 0x9 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_PARITY_DBUG_EN__SHIFT 0xa +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_PARITY_DBUG_EN__SHIFT 0xb +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_PARITY_DBUG_EN__SHIFT 0xc +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_PARITY_DBUG_EN__SHIFT 0xd +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_PARITY_DBUG_EN_MASK 0x00000001L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_PARITY_DBUG_EN_MASK 0x00000002L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_PARITY_DBUG_EN_MASK 0x00000004L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_PARITY_DBUG_EN_MASK 0x00000008L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_PARITY_DBUG_EN_MASK 0x00000010L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_PARITY_DBUG_EN_MASK 0x00000020L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_PARITY_DBUG_EN_MASK 0x00000040L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_PARITY_DBUG_EN_MASK 0x00000080L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_PARITY_DBUG_EN_MASK 0x00000100L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_PARITY_DBUG_EN_MASK 0x00000200L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_PARITY_DBUG_EN_MASK 0x00000400L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_PARITY_DBUG_EN_MASK 0x00000800L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_PARITY_DBUG_EN_MASK 0x00001000L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_PARITY_DBUG_EN_MASK 0x00002000L +//GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x1 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x2 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x3 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x4 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x5 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x6 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x7 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x8 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x9 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xa +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xb +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xc +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xd +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000001L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000002L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000004L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000008L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000010L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000020L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000040L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000080L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000100L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000200L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000400L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000800L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00001000L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00002000L +//GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x1 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x2 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x3 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x4 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x5 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x6 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x7 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x8 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x9 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xa +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xb +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xc +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xd +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000001L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000002L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000004L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000008L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000010L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000020L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000040L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000080L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000100L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000200L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000400L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000800L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_TIMEOUT_DBUG_EN_MASK 0x00001000L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_TIMEOUT_DBUG_EN_MASK 0x00002000L +//GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF0_POISON_DATA_DROP_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF1_POISON_DATA_DROP_EN__SHIFT 0x1 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF2_POISON_DATA_DROP_EN__SHIFT 0x2 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF3_POISON_DATA_DROP_EN__SHIFT 0x3 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF4_POISON_DATA_DROP_EN__SHIFT 0x4 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF5_POISON_DATA_DROP_EN__SHIFT 0x5 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF6_POISON_DATA_DROP_EN__SHIFT 0x6 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF7_POISON_DATA_DROP_EN__SHIFT 0x7 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF8_POISON_DATA_DROP_EN__SHIFT 0x8 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF9_POISON_DATA_DROP_EN__SHIFT 0x9 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF10_POISON_DATA_DROP_EN__SHIFT 0xa +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF11_POISON_DATA_DROP_EN__SHIFT 0xb +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF12_POISON_DATA_DROP_EN__SHIFT 0xc +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF13_POISON_DATA_DROP_EN__SHIFT 0xd +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF0_POISON_DATA_DROP_EN_MASK 0x00000001L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF1_POISON_DATA_DROP_EN_MASK 0x00000002L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF2_POISON_DATA_DROP_EN_MASK 0x00000004L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF3_POISON_DATA_DROP_EN_MASK 0x00000008L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF4_POISON_DATA_DROP_EN_MASK 0x00000010L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF5_POISON_DATA_DROP_EN_MASK 0x00000020L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF6_POISON_DATA_DROP_EN_MASK 0x00000040L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF7_POISON_DATA_DROP_EN_MASK 0x00000080L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF8_POISON_DATA_DROP_EN_MASK 0x00000100L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF9_POISON_DATA_DROP_EN_MASK 0x00000200L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF10_POISON_DATA_DROP_EN_MASK 0x00000400L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF11_POISON_DATA_DROP_EN_MASK 0x00000800L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF12_POISON_DATA_DROP_EN_MASK 0x00001000L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF13_POISON_DATA_DROP_EN_MASK 0x00002000L +//GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF0_RESPONSE_DROP_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF1_RESPONSE_DROP_EN__SHIFT 0x1 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF2_RESPONSE_DROP_EN__SHIFT 0x2 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF3_RESPONSE_DROP_EN__SHIFT 0x3 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF4_RESPONSE_DROP_EN__SHIFT 0x4 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF5_RESPONSE_DROP_EN__SHIFT 0x5 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF6_RESPONSE_DROP_EN__SHIFT 0x6 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF7_RESPONSE_DROP_EN__SHIFT 0x7 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF8_RESPONSE_DROP_EN__SHIFT 0x8 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF9_RESPONSE_DROP_EN__SHIFT 0x9 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF10_RESPONSE_DROP_EN__SHIFT 0xa +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF11_RESPONSE_DROP_EN__SHIFT 0xb +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF12_RESPONSE_DROP_EN__SHIFT 0xc +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF13_RESPONSE_DROP_EN__SHIFT 0xd +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF0_RESPONSE_DROP_EN_MASK 0x00000001L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF1_RESPONSE_DROP_EN_MASK 0x00000002L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF2_RESPONSE_DROP_EN_MASK 0x00000004L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF3_RESPONSE_DROP_EN_MASK 0x00000008L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF4_RESPONSE_DROP_EN_MASK 0x00000010L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF5_RESPONSE_DROP_EN_MASK 0x00000020L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF6_RESPONSE_DROP_EN_MASK 0x00000040L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF7_RESPONSE_DROP_EN_MASK 0x00000080L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF8_RESPONSE_DROP_EN_MASK 0x00000100L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF9_RESPONSE_DROP_EN_MASK 0x00000200L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF10_RESPONSE_DROP_EN_MASK 0x00000400L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF11_RESPONSE_DROP_EN_MASK 0x00000800L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF12_RESPONSE_DROP_EN_MASK 0x00001000L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF13_RESPONSE_DROP_EN_MASK 0x00002000L +//GDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF0_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF0_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF0_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF0_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF1_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF1_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF1_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF1_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF2_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF2_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF2_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF2_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF3_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF3_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF3_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF3_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF4_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF4_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF4_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF4_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF5_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF5_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF5_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF5_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF6_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF6_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF6_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF6_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF7_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF7_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF7_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF7_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF8_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF8_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF8_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF8_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF9_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF9_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF9_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF9_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF10_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF10_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF10_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF10_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF11_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF11_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF11_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF11_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF12_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF12_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF12_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF12_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF13_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF13_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF13_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF13_RUSER_POISON_EN_MASK 0x000000FFL + + +// addressBlock: nbif0_nbif0_gdc_a2s_GDCA2S_DEC +//A2S_CNTL_SW0 +#define A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT 0x0 +#define A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT 0x1 +#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10 +#define A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18 +#define A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK 0x00000001L +#define A2S_CNTL_SW0__STATIC_VC_VALUE_MASK 0x0000000EL +#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK 0xFF000000L +//A2S_CNTL_SW1 +#define A2S_CNTL_SW1__STATIC_VC_ENABLE__SHIFT 0x0 +#define A2S_CNTL_SW1__STATIC_VC_VALUE__SHIFT 0x1 +#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x10 +#define A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x18 +#define A2S_CNTL_SW1__STATIC_VC_ENABLE_MASK 0x00000001L +#define A2S_CNTL_SW1__STATIC_VC_VALUE_MASK 0x0000000EL +#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK 0xFF000000L +//A2S_CNTL_SW2 +#define A2S_CNTL_SW2__STATIC_VC_ENABLE__SHIFT 0x0 +#define A2S_CNTL_SW2__STATIC_VC_VALUE__SHIFT 0x1 +#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT 0x10 +#define A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT 0x18 +#define A2S_CNTL_SW2__STATIC_VC_ENABLE_MASK 0x00000001L +#define A2S_CNTL_SW2__STATIC_VC_VALUE_MASK 0x0000000EL +#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define A2S_CNTL_SW2__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define A2S_CNTL_SW2__WRR_WR_WEIGHT_MASK 0xFF000000L +//A2S_CNTL_SW3 +#define A2S_CNTL_SW3__STATIC_VC_ENABLE__SHIFT 0x0 +#define A2S_CNTL_SW3__STATIC_VC_VALUE__SHIFT 0x1 +#define A2S_CNTL_SW3__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define A2S_CNTL_SW3__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define A2S_CNTL_SW3__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define A2S_CNTL_SW3__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define A2S_CNTL_SW3__WRR_RD_WEIGHT__SHIFT 0x10 +#define A2S_CNTL_SW3__WRR_WR_WEIGHT__SHIFT 0x18 +#define A2S_CNTL_SW3__STATIC_VC_ENABLE_MASK 0x00000001L +#define A2S_CNTL_SW3__STATIC_VC_VALUE_MASK 0x0000000EL +#define A2S_CNTL_SW3__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define A2S_CNTL_SW3__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define A2S_CNTL_SW3__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define A2S_CNTL_SW3__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define A2S_CNTL_SW3__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define A2S_CNTL_SW3__WRR_WR_WEIGHT_MASK 0xFF000000L +//A2S_CNTL_SW4 +#define A2S_CNTL_SW4__STATIC_VC_ENABLE__SHIFT 0x0 +#define A2S_CNTL_SW4__STATIC_VC_VALUE__SHIFT 0x1 +#define A2S_CNTL_SW4__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define A2S_CNTL_SW4__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define A2S_CNTL_SW4__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define A2S_CNTL_SW4__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define A2S_CNTL_SW4__WRR_RD_WEIGHT__SHIFT 0x10 +#define A2S_CNTL_SW4__WRR_WR_WEIGHT__SHIFT 0x18 +#define A2S_CNTL_SW4__STATIC_VC_ENABLE_MASK 0x00000001L +#define A2S_CNTL_SW4__STATIC_VC_VALUE_MASK 0x0000000EL +#define A2S_CNTL_SW4__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define A2S_CNTL_SW4__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define A2S_CNTL_SW4__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define A2S_CNTL_SW4__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define A2S_CNTL_SW4__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define A2S_CNTL_SW4__WRR_WR_WEIGHT_MASK 0xFF000000L +//A2S_CNTL_SW5 +#define A2S_CNTL_SW5__STATIC_VC_ENABLE__SHIFT 0x0 +#define A2S_CNTL_SW5__STATIC_VC_VALUE__SHIFT 0x1 +#define A2S_CNTL_SW5__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define A2S_CNTL_SW5__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define A2S_CNTL_SW5__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define A2S_CNTL_SW5__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define A2S_CNTL_SW5__WRR_RD_WEIGHT__SHIFT 0x10 +#define A2S_CNTL_SW5__WRR_WR_WEIGHT__SHIFT 0x18 +#define A2S_CNTL_SW5__STATIC_VC_ENABLE_MASK 0x00000001L +#define A2S_CNTL_SW5__STATIC_VC_VALUE_MASK 0x0000000EL +#define A2S_CNTL_SW5__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define A2S_CNTL_SW5__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define A2S_CNTL_SW5__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define A2S_CNTL_SW5__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define A2S_CNTL_SW5__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define A2S_CNTL_SW5__WRR_WR_WEIGHT_MASK 0xFF000000L +//A2S_CNTL_2_SW0 +#define A2S_CNTL_2_SW0__SDP_LARGE_WR_CHAIN_DIS__SHIFT 0x0 +#define A2S_CNTL_2_SW0__SDP_LARGE_WR_CHAIN_DIS_MASK 0x00000001L +//A2S_CNTL_2_SW1 +#define A2S_CNTL_2_SW1__SDP_LARGE_WR_CHAIN_DIS__SHIFT 0x0 +#define A2S_CNTL_2_SW1__SDP_LARGE_WR_CHAIN_DIS_MASK 0x00000001L +//A2S_CNTL_2_SW2 +#define A2S_CNTL_2_SW2__SDP_LARGE_WR_CHAIN_DIS__SHIFT 0x0 +#define A2S_CNTL_2_SW2__SDP_LARGE_WR_CHAIN_DIS_MASK 0x00000001L +//A2S_CNTL_2_SW3 +#define A2S_CNTL_2_SW3__SDP_LARGE_WR_CHAIN_DIS__SHIFT 0x0 +#define A2S_CNTL_2_SW3__SDP_LARGE_WR_CHAIN_DIS_MASK 0x00000001L +//A2S_CNTL_2_SW4 +#define A2S_CNTL_2_SW4__SDP_LARGE_WR_CHAIN_DIS__SHIFT 0x0 +#define A2S_CNTL_2_SW4__SDP_LARGE_WR_CHAIN_DIS_MASK 0x00000001L +//A2S_CNTL_2_SW5 +#define A2S_CNTL_2_SW5__SDP_LARGE_WR_CHAIN_DIS__SHIFT 0x0 +#define A2S_CNTL_2_SW5__SDP_LARGE_WR_CHAIN_DIS_MASK 0x00000001L +//A2S_WRSIZEFULL_SUPPORT_DISABLE +#define A2S_WRSIZEFULL_SUPPORT_DISABLE__SHUB_A2S_WRSIZEFULL_SUPPORT_DISABLE__SHIFT 0x0 +#define A2S_WRSIZEFULL_SUPPORT_DISABLE__SHUB_A2S_WRSIZEFULL_SUPPORT_DISABLE_MASK 0x00000001L +//ROUTING_TABLE_CNTL +#define ROUTING_TABLE_CNTL__TABLE_INDEX__SHIFT 0x0 +#define ROUTING_TABLE_CNTL__TABLE_INDEX_MASK 0x0000FFFFL +//ROUTING_TABLE_DATA0 +#define ROUTING_TABLE_DATA0__TABLE_DATA0__SHIFT 0x0 +#define ROUTING_TABLE_DATA0__TABLE_DATA0_MASK 0xFFFFFFFFL +//A2S_ARB_CONTROL_FOR_VC0 +#define A2S_ARB_CONTROL_FOR_VC0__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC0__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC0__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC0__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC0__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC0__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_ARB_CONTROL_FOR_VC1 +#define A2S_ARB_CONTROL_FOR_VC1__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC1__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC1__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC1__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC1__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC1__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_ARB_CONTROL_FOR_VC2 +#define A2S_ARB_CONTROL_FOR_VC2__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC2__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC2__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC2__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC2__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC2__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_ARB_CONTROL_FOR_VC3 +#define A2S_ARB_CONTROL_FOR_VC3__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC3__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC3__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC3__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC3__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC3__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_ARB_CONTROL_FOR_VC4 +#define A2S_ARB_CONTROL_FOR_VC4__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC4__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC4__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC4__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC4__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC4__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_ARB_CONTROL_FOR_VC5 +#define A2S_ARB_CONTROL_FOR_VC5__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC5__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC5__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC5__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC5__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC5__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_ARB_CONTROL_FOR_VC6 +#define A2S_ARB_CONTROL_FOR_VC6__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC6__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC6__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC6__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC6__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC6__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_ARB_CONTROL_FOR_VC7 +#define A2S_ARB_CONTROL_FOR_VC7__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC7__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC7__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC7__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC7__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC7__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_RW_ARB_CNTL +#define A2S_RW_ARB_CNTL__A2S_WRR_WEIGHT_RD__SHIFT 0x0 +#define A2S_RW_ARB_CNTL__A2S_WRR_WEIGHT_WR__SHIFT 0x8 +#define A2S_RW_ARB_CNTL__A2S_LRG_MODE_RW__SHIFT 0x10 +#define A2S_RW_ARB_CNTL__A2S_LRG_SIZE_MODE_RW__SHIFT 0x11 +#define A2S_RW_ARB_CNTL__A2S_LRG_COUNTER_MODE_RW__SHIFT 0x12 +#define A2S_RW_ARB_CNTL__A2S_WRR_WEIGHT_RD_MASK 0x000000FFL +#define A2S_RW_ARB_CNTL__A2S_WRR_WEIGHT_WR_MASK 0x0000FF00L +#define A2S_RW_ARB_CNTL__A2S_LRG_MODE_RW_MASK 0x00010000L +#define A2S_RW_ARB_CNTL__A2S_LRG_SIZE_MODE_RW_MASK 0x00020000L +#define A2S_RW_ARB_CNTL__A2S_LRG_COUNTER_MODE_RW_MASK 0x00040000L +//A2S_REQ_RSP_TAG_CNTL +#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_MODE__SHIFT 0x0 +#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_SIZE_MODE__SHIFT 0x1 +#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_COUNTER_MODE__SHIFT 0x2 +#define A2S_REQ_RSP_TAG_CNTL__RD_A2S_RSP_ARBMODE__SHIFT 0x3 +#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_MODE__SHIFT 0x10 +#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_SIZE_MODE__SHIFT 0x11 +#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_COUNTER_MODE__SHIFT 0x12 +#define A2S_REQ_RSP_TAG_CNTL__WR_A2S_RSP_ARBMODE__SHIFT 0x13 +#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_MODE_MASK 0x00000001L +#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_SIZE_MODE_MASK 0x00000002L +#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_COUNTER_MODE_MASK 0x00000004L +#define A2S_REQ_RSP_TAG_CNTL__RD_A2S_RSP_ARBMODE_MASK 0x00000008L +#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_MODE_MASK 0x00010000L +#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_SIZE_MODE_MASK 0x00020000L +#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_COUNTER_MODE_MASK 0x00040000L +#define A2S_REQ_RSP_TAG_CNTL__WR_A2S_RSP_ARBMODE_MASK 0x00080000L +//A2S_MISC_CNTL +#define A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0 +#define A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT 0x6 +#define A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK 0x00000003L +#define A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK 0x00000040L +//A2S_TAG_ALLOC_0 +#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT 0x0 +#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT 0x8 +#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT 0x10 +#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK 0x000000FFL +#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK 0x0000FF00L +#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK 0x00FF0000L +//A2S_TAG_ALLOC_1 +#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT 0x0 +#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT 0x10 +#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT 0x18 +#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK 0x000000FFL +#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK 0x00FF0000L +#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK 0xFF000000L +//A2S_TAG_ALLOC_2 +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC5_WR__SHIFT 0x0 +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC5_RD__SHIFT 0x8 +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC6_WR__SHIFT 0x10 +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC6_RD__SHIFT 0x18 +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC5_WR_MASK 0x000000FFL +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC5_RD_MASK 0x0000FF00L +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC6_WR_MASK 0x00FF0000L +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC6_RD_MASK 0xFF000000L +//A2S_TAG_ALLOC_3 +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC4_WR__SHIFT 0x0 +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC4_RD__SHIFT 0x8 +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC2_WR__SHIFT 0x10 +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC2_RD__SHIFT 0x18 +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC4_WR_MASK 0x000000FFL +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC4_RD_MASK 0x0000FF00L +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC2_WR_MASK 0x00FF0000L +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC2_RD_MASK 0xFF000000L +//SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC0_CHAIN__SHIFT 0x0 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC1_CHAIN__SHIFT 0x8 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC2_CHAIN__SHIFT 0x10 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC3_CHAIN__SHIFT 0x18 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC0_CHAIN_MASK 0x000000FFL +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC1_CHAIN_MASK 0x0000FF00L +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC2_CHAIN_MASK 0x00FF0000L +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC3_CHAIN_MASK 0xFF000000L +//SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC4_CHAIN__SHIFT 0x0 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC5_CHAIN__SHIFT 0x8 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC6_CHAIN__SHIFT 0x10 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC7_CHAIN__SHIFT 0x18 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC4_CHAIN_MASK 0x000000FFL +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC5_CHAIN_MASK 0x0000FF00L +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC6_CHAIN_MASK 0x00FF0000L +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC7_CHAIN_MASK 0xFF000000L +//GDC_SDP_PORT_CTRL +#define GDC_SDP_PORT_CTRL__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x0 +#define GDC_SDP_PORT_CTRL__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00000001L +//GDC_A2S_SDP_REQ_POOLCRED_ALLOC +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//GDC_A2S_SDP_DAT_POOLCRED_ALLOC +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//SHUB_PERF_COMMON_COUNTER +#define SHUB_PERF_COMMON_COUNTER__SHUB_COM_COUNT_ENBALE__SHIFT 0x0 +#define SHUB_PERF_COMMON_COUNTER__SHUB_COM_COUNT_ENBALE_MASK 0x00000001L +//SHUB_A2S_PERF_CNT_FSM +#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_SHADOW_TGL_DELAY_COUNT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_PERF_RESET_TGL_DELAY_COUNT__SHIFT 0x4 +#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_PERF_RESET_TGL_DELAY_EN__SHIFT 0x8 +#define SHUB_A2S_PERF_CNT_FSM__A2S_PRE_FLD_GLOBAL_SHADOW_WR__SHIFT 0x9 +#define SHUB_A2S_PERF_CNT_FSM__A2S_PERF_CNT_DONE__SHIFT 0xa +#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_SHADOW_TGL_DELAY_COUNT_MASK 0x0000000FL +#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_PERF_RESET_TGL_DELAY_COUNT_MASK 0x000000F0L +#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_PERF_RESET_TGL_DELAY_EN_MASK 0x00000100L +#define SHUB_A2S_PERF_CNT_FSM__A2S_PRE_FLD_GLOBAL_SHADOW_WR_MASK 0x00000200L +#define SHUB_A2S_PERF_CNT_FSM__A2S_PERF_CNT_DONE_MASK 0x00000400L +//SHUB_A2S_PERF_CNT_RSP_UNITID +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_WRRSP_UNITID__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_WRRSP_UNITID_EN__SHIFT 0xf +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_RDRSP_UNITID__SHIFT 0x10 +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_RDRSP_UNITID_EN__SHIFT 0x1f +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_WRRSP_UNITID_MASK 0x000007FFL +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_WRRSP_UNITID_EN_MASK 0x00008000L +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_RDRSP_UNITID_MASK 0x07FF0000L +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_RDRSP_UNITID_EN_MASK 0x80000000L +//SHUB_A2S_PERF_CNT_0_CTRL +#define SHUB_A2S_PERF_CNT_0_CTRL__A2S_PERF_CNT_0_SEL__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_0_CTRL__A2S_PERF_CNT_0_EN__SHIFT 0x1f +#define SHUB_A2S_PERF_CNT_0_CTRL__A2S_PERF_CNT_0_SEL_MASK 0x7FFFFFFFL +#define SHUB_A2S_PERF_CNT_0_CTRL__A2S_PERF_CNT_0_EN_MASK 0x80000000L +//SHUB_A2S_PERF_CNT_1_CTRL +#define SHUB_A2S_PERF_CNT_1_CTRL__A2S_PERF_CNT_1_SEL__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_1_CTRL__A2S_PERF_CNT_1_EN__SHIFT 0x1f +#define SHUB_A2S_PERF_CNT_1_CTRL__A2S_PERF_CNT_1_SEL_MASK 0x7FFFFFFFL +#define SHUB_A2S_PERF_CNT_1_CTRL__A2S_PERF_CNT_1_EN_MASK 0x80000000L +//SHUB_A2S_PERF_CNT_2_CTRL +#define SHUB_A2S_PERF_CNT_2_CTRL__A2S_PERF_CNT_2_SEL__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_2_CTRL__A2S_PERF_CNT_2_EN__SHIFT 0x1f +#define SHUB_A2S_PERF_CNT_2_CTRL__A2S_PERF_CNT_2_SEL_MASK 0x7FFFFFFFL +#define SHUB_A2S_PERF_CNT_2_CTRL__A2S_PERF_CNT_2_EN_MASK 0x80000000L +//SHUB_A2S_PERF_CNT_3_CTRL +#define SHUB_A2S_PERF_CNT_3_CTRL__A2S_PERF_CNT_3_SEL__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_3_CTRL__A2S_PERF_CNT_3_EN__SHIFT 0x1f +#define SHUB_A2S_PERF_CNT_3_CTRL__A2S_PERF_CNT_3_SEL_MASK 0x7FFFFFFFL +#define SHUB_A2S_PERF_CNT_3_CTRL__A2S_PERF_CNT_3_EN_MASK 0x80000000L +//SHUB_A2S_PERF_CNT_0_VALUE_L32BIT +#define SHUB_A2S_PERF_CNT_0_VALUE_L32BIT__A2S_PERF_CNT_0_VALUE_L32BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_0_VALUE_L32BIT__A2S_PERF_CNT_0_VALUE_L32BIT_MASK 0xFFFFFFFFL +//SHUB_A2S_PERF_CNT_0_VALUE_H16BIT +#define SHUB_A2S_PERF_CNT_0_VALUE_H16BIT__A2S_PERF_CNT_0_VALUE_H16BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_0_VALUE_H16BIT__A2S_PERF_CNT_0_VALUE_H16BIT_MASK 0xFFFFL +//SHUB_A2S_PERF_CNT_1_VALUE_L32BIT +#define SHUB_A2S_PERF_CNT_1_VALUE_L32BIT__A2S_PERF_CNT_1_VALUE_L32BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_1_VALUE_L32BIT__A2S_PERF_CNT_1_VALUE_L32BIT_MASK 0xFFFFFFFFL +//SHUB_A2S_PERF_CNT_1_VALUE_H16BIT +#define SHUB_A2S_PERF_CNT_1_VALUE_H16BIT__A2S_PERF_CNT_1_VALUE_H16BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_1_VALUE_H16BIT__A2S_PERF_CNT_1_VALUE_H16BIT_MASK 0xFFFFL +//SHUB_A2S_PERF_CNT_2_VALUE_L32BIT +#define SHUB_A2S_PERF_CNT_2_VALUE_L32BIT__A2S_PERF_CNT_2_VALUE_L32BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_2_VALUE_L32BIT__A2S_PERF_CNT_2_VALUE_L32BIT_MASK 0xFFFFFFFFL +//SHUB_A2S_PERF_CNT_2_VALUE_H16BIT +#define SHUB_A2S_PERF_CNT_2_VALUE_H16BIT__A2S_PERF_CNT_2_VALUE_H16BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_2_VALUE_H16BIT__A2S_PERF_CNT_2_VALUE_H16BIT_MASK 0xFFFFL +//SHUB_A2S_PERF_CNT_3_VALUE_L32BIT +#define SHUB_A2S_PERF_CNT_3_VALUE_L32BIT__A2S_PERF_CNT_3_VALUE_L32BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_3_VALUE_L32BIT__A2S_PERF_CNT_3_VALUE_L32BIT_MASK 0xFFFFFFFFL +//SHUB_A2S_PERF_CNT_3_VALUE_H16BIT +#define SHUB_A2S_PERF_CNT_3_VALUE_H16BIT__A2S_PERF_CNT_3_VALUE_H16BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_3_VALUE_H16BIT__A2S_PERF_CNT_3_VALUE_H16BIT_MASK 0xFFFFL +//SHUB_TO_ALL_PERF_COUNTER +#define SHUB_TO_ALL_PERF_COUNTER__START_COUNT_NOPULS__SHIFT 0x0 +#define SHUB_TO_ALL_PERF_COUNTER__LEGACY_OUT_REALTIME_SEL__SHIFT 0x1 +#define SHUB_TO_ALL_PERF_COUNTER__PERF_CNT_TRIG_MONI_SEL__SHIFT 0x2 +#define SHUB_TO_ALL_PERF_COUNTER__START_COUNT_NOPULS_MASK 0x00000001L +#define SHUB_TO_ALL_PERF_COUNTER__LEGACY_OUT_REALTIME_SEL_MASK 0x00000002L +#define SHUB_TO_ALL_PERF_COUNTER__PERF_CNT_TRIG_MONI_SEL_MASK 0x0000000CL +//GDC_PERF_COUNTER_RESET +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT0_RESET__SHIFT 0x0 +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT1_RESET__SHIFT 0x1 +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT2_RESET__SHIFT 0x2 +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT3_RESET__SHIFT 0x3 +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT0_RESET_MASK 0x00000001L +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT1_RESET_MASK 0x00000002L +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT2_RESET_MASK 0x00000004L +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT3_RESET_MASK 0x00000008L +//SHUB_COM_COUNT_VALUE +#define SHUB_COM_COUNT_VALUE__SHUB_COM_COUNT_VALUE__SHIFT 0x0 +#define SHUB_COM_COUNT_VALUE__SHUB_COM_COUNT_VALUE_MASK 0xFFFFFFFFL +//A2S_QUEUE_FIFO_ARB_CNTL +#define A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT 0x0 +#define A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT 0xa +#define A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE__SHIFT 0x14 +#define A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE__SHIFT 0x15 +#define A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY_MASK 0x000003FFL +#define A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY_MASK 0x000FFC00L +#define A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE_MASK 0x00100000L +#define A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE_MASK 0x00200000L +//WR_A2S_RSP_WRR_CNTL +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE0__SHIFT 0x0 +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE1__SHIFT 0x4 +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE2__SHIFT 0x8 +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE3__SHIFT 0xc +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE4__SHIFT 0x10 +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE5__SHIFT 0x14 +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE6__SHIFT 0x18 +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE7__SHIFT 0x1c +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE0_MASK 0x0000000FL +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE1_MASK 0x000000F0L +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE2_MASK 0x00000F00L +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE3_MASK 0x0000F000L +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE4_MASK 0x000F0000L +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE5_MASK 0x00F00000L +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE6_MASK 0x0F000000L +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE7_MASK 0xF0000000L +//RD_A2S_RSP_WRR_CNTL +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE0__SHIFT 0x0 +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE1__SHIFT 0x4 +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE2__SHIFT 0x8 +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE3__SHIFT 0xc +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE4__SHIFT 0x10 +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE5__SHIFT 0x14 +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE6__SHIFT 0x18 +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE7__SHIFT 0x1c +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE0_MASK 0x0000000FL +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE1_MASK 0x000000F0L +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE2_MASK 0x00000F00L +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE3_MASK 0x0000F000L +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE4_MASK 0x000F0000L +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE5_MASK 0x00F00000L +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE6_MASK 0x0F000000L +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE7_MASK 0xF0000000L + + +// addressBlock: nbif0_nbif0_syshub_mmreg_syshubdirect +//SYSHUB_DS_CTRL_SOCCLK +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 +#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c +#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L +#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L +#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN_MASK 0x80000000L +//SYSHUB_DS_CTRL2_SOCCLK +#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0 +#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER_MASK 0x0000FFFFL +//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0x10 +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x11 +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x12 +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW3_bypass_en__SHIFT 0x13 +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW4_bypass_en__SHIFT 0x14 +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW5_bypass_en__SHIFT 0x15 +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_DYNAMIC_BYPASS_EN_socclk__SHIFT 0x1f +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en_MASK 0x00010000L +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en_MASK 0x00020000L +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en_MASK 0x00040000L +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW3_bypass_en_MASK 0x00080000L +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW4_bypass_en_MASK 0x00100000L +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW5_bypass_en_MASK 0x00200000L +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_DYNAMIC_BYPASS_EN_socclk_MASK 0x80000000L +//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0x10 +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x11 +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x12 +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW3_imm_en__SHIFT 0x13 +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW4_imm_en__SHIFT 0x14 +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW5_imm_en__SHIFT 0x15 +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en_MASK 0x00010000L +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en_MASK 0x00020000L +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en_MASK 0x00040000L +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW3_imm_en_MASK 0x00080000L +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW4_imm_en_MASK 0x00100000L +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW5_imm_en_MASK 0x00200000L +//SYSHUB_MGCG_CTRL_SOCCLK +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK__SHIFT 0x0 +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK__SHIFT 0x1 +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK__SHIFT 0x2 +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK__SHIFT 0xa +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK__SHIFT 0xb +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REG_DIS_SOCCLK__SHIFT 0xc +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK__SHIFT 0xd +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DBG_DIS_SOCCLK__SHIFT 0xe +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK 0x00000001L +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK_MASK 0x00000002L +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK_MASK 0x000003FCL +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK_MASK 0x00000400L +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK_MASK 0x00000800L +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REG_DIS_SOCCLK_MASK 0x00001000L +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK_MASK 0x00002000L +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DBG_DIS_SOCCLK_MASK 0x00004000L +//SYSHUB_SCRATCH_SOCCLK +#define SYSHUB_SCRATCH_SOCCLK__SCRATCH_SOCCLK__SHIFT 0x0 +#define SYSHUB_SCRATCH_SOCCLK__SCRATCH_SOCCLK_MASK 0xFFFFFFFFL +//SYSHUB_HANG_CNTL_SOCCLK +//SYSHUB_SELECT_SOCCLK +#define SYSHUB_SELECT_SOCCLK__SELECT_USB0__SHIFT 0x0 +#define SYSHUB_SELECT_SOCCLK__SELECT_USB0_MASK 0x00000001L +//SYSHUB_DS_AW_READY_SOCCLK +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL0_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x0 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL1_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x1 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL2_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x2 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL3_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x3 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL4_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x4 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL5_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x5 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL6_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x6 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL7_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x7 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL0_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000001L +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL1_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000002L +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL2_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000004L +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL3_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000008L +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL4_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000010L +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL5_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000020L +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL6_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000040L +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL7_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000080L +//SYSHUB_DS_AR_READY_SOCCLK +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL0_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x0 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL1_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x1 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL2_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x2 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL3_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x3 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL4_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x4 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL5_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x5 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL6_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x6 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL7_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x7 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL0_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000001L +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL1_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000002L +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL2_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000004L +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL3_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000008L +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL4_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000010L +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL5_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000020L +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL6_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000040L +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL7_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000080L +//SYSHUB_DS_W_READY_SOCCLK +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL0_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x0 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL1_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x1 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL2_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x2 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL3_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x3 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL4_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x4 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL5_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x5 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL6_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x6 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL7_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x7 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL0_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000001L +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL1_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000002L +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL2_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000004L +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL3_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000008L +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL4_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000010L +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL5_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000020L +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL6_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000040L +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL7_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000080L +//SYSHUB_DS_R_READY_SOCCLK +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL0_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x0 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL1_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x1 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL2_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x2 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL3_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x3 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL4_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x4 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL5_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x5 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL6_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x6 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL7_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x7 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL0_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000001L +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL1_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000002L +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL2_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000004L +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL3_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000008L +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL4_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000010L +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL5_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000020L +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL6_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000040L +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL7_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000080L +//SYSHUB_DS_B_READY_SOCCLK +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL0_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x0 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL1_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x1 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL2_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x2 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL3_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x3 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL4_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x4 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL5_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x5 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL6_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x6 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL7_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x7 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL0_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000001L +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL1_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000002L +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL2_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000004L +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL3_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000008L +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL4_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000010L +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL5_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000020L +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL6_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000040L +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL7_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000080L +//SYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK +#define SYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK__HST_SOCCLK_AXI_DEBUG_COUNTER_EN__SHIFT 0x0 +#define SYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK__DMA_SOCCLK_AXI_DEBUG_COUNTER_EN__SHIFT 0x1 +#define SYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK__HST_SOCCLK_AXI_DEBUG_COUNTER_EN_MASK 0x00000001L +#define SYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK__DMA_SOCCLK_AXI_DEBUG_COUNTER_EN_MASK 0x00000002L +//DMA_CLK0_SW0_SYSHUB_QOS_CNTL +#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L +#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL +#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L +//DMA_CLK0_SW1_SYSHUB_QOS_CNTL +#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L +#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL +#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L +//DMA_CLK0_SW0_CL0_CNTL +#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW0_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW0_CL0_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//DMA_CLK0_SW0_CL1_CNTL +#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW0_CL1_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW0_CL1_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//DMA_CLK0_SW1_CL0_CNTL +#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW1_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW1_CL0_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//DMA_CLK0_SW1_CL1_CNTL +#define DMA_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW1_CL1_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define DMA_CLK0_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define DMA_CLK0_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define DMA_CLK0_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define DMA_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW1_CL1_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +#define DMA_CLK0_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define DMA_CLK0_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define DMA_CLK0_SW1_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define DMA_CLK0_SW1_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//DMA_CLK0_SW2_CL0_CNTL +#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW2_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW2_CL0_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +//DMA_CLK0_SW3_CL0_CNTL +#define DMA_CLK0_SW3_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW3_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW3_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW3_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW3_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW3_CL0_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +//DMA_CLK0_SW4_CL0_CNTL +#define DMA_CLK0_SW4_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW4_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW4_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW4_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW4_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW4_CL0_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +//DMA_CLK0_SW5_CL0_CNTL +#define DMA_CLK0_SW5_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW5_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW5_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW5_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW5_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW5_CL0_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +//NIC400_0_AMIB_0_FN_MOD_BM_ISS +#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 +#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 +#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L +#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L +//NIC400_0_AMIB_0_FN_MOD +#define NIC400_0_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_0_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_0_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_0_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_0_ASIB_0_FN_MOD +#define NIC400_0_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_0_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_0_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_0_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_0_ASIB_0_QOS_CNTL +#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_rate__SHIFT 0x0 +#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_rate__SHIFT 0x1 +#define NIC400_0_ASIB_0_QOS_CNTL__en_awar_rate__SHIFT 0x2 +#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_fc__SHIFT 0x3 +#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_fc__SHIFT 0x4 +#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_ot__SHIFT 0x5 +#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_ot__SHIFT 0x6 +#define NIC400_0_ASIB_0_QOS_CNTL__en_awar_ot__SHIFT 0x7 +#define NIC400_0_ASIB_0_QOS_CNTL__mode_aw_fc__SHIFT 0x10 +#define NIC400_0_ASIB_0_QOS_CNTL__mode_ar_fc__SHIFT 0x14 +#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_rate_MASK 0x00000001L +#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_rate_MASK 0x00000002L +#define NIC400_0_ASIB_0_QOS_CNTL__en_awar_rate_MASK 0x00000004L +#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_fc_MASK 0x00000008L +#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_fc_MASK 0x00000010L +#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_ot_MASK 0x00000020L +#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_ot_MASK 0x00000040L +#define NIC400_0_ASIB_0_QOS_CNTL__en_awar_ot_MASK 0x00000080L +#define NIC400_0_ASIB_0_QOS_CNTL__mode_aw_fc_MASK 0x00010000L +#define NIC400_0_ASIB_0_QOS_CNTL__mode_ar_fc_MASK 0x00100000L +//NIC400_0_ASIB_0_MAX_OT +#define NIC400_0_ASIB_0_MAX_OT__aw_max_otf__SHIFT 0x0 +#define NIC400_0_ASIB_0_MAX_OT__aw_max_oti__SHIFT 0x8 +#define NIC400_0_ASIB_0_MAX_OT__ar_max_otf__SHIFT 0x10 +#define NIC400_0_ASIB_0_MAX_OT__ar_max_oti__SHIFT 0x18 +#define NIC400_0_ASIB_0_MAX_OT__aw_max_otf_MASK 0x000000FFL +#define NIC400_0_ASIB_0_MAX_OT__aw_max_oti_MASK 0x00003F00L +#define NIC400_0_ASIB_0_MAX_OT__ar_max_otf_MASK 0x00FF0000L +#define NIC400_0_ASIB_0_MAX_OT__ar_max_oti_MASK 0x3F000000L +//NIC400_0_ASIB_0_MAX_COMB_OT +#define NIC400_0_ASIB_0_MAX_COMB_OT__awar_max_otf__SHIFT 0x0 +#define NIC400_0_ASIB_0_MAX_COMB_OT__awar_max_oti__SHIFT 0x8 +#define NIC400_0_ASIB_0_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL +#define NIC400_0_ASIB_0_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L +//NIC400_0_ASIB_0_AW_P +#define NIC400_0_ASIB_0_AW_P__aw_p__SHIFT 0x18 +#define NIC400_0_ASIB_0_AW_P__aw_p_MASK 0xFF000000L +//NIC400_0_ASIB_0_AW_B +#define NIC400_0_ASIB_0_AW_B__aw_b__SHIFT 0x0 +#define NIC400_0_ASIB_0_AW_B__aw_b_MASK 0x0000FFFFL +//NIC400_0_ASIB_0_AW_R +#define NIC400_0_ASIB_0_AW_R__aw_r__SHIFT 0x14 +#define NIC400_0_ASIB_0_AW_R__aw_r_MASK 0xFFF00000L +//NIC400_0_ASIB_0_AR_P +#define NIC400_0_ASIB_0_AR_P__ar_p__SHIFT 0x18 +#define NIC400_0_ASIB_0_AR_P__ar_p_MASK 0xFF000000L +//NIC400_0_ASIB_0_AR_B +#define NIC400_0_ASIB_0_AR_B__ar_b__SHIFT 0x0 +#define NIC400_0_ASIB_0_AR_B__ar_b_MASK 0x0000FFFFL +//NIC400_0_ASIB_0_AR_R +#define NIC400_0_ASIB_0_AR_R__ar_r__SHIFT 0x14 +#define NIC400_0_ASIB_0_AR_R__ar_r_MASK 0xFFF00000L +//NIC400_0_ASIB_0_TARGET_FC +#define NIC400_0_ASIB_0_TARGET_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_0_ASIB_0_TARGET_FC__ar_tgt_latency__SHIFT 0x10 +#define NIC400_0_ASIB_0_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL +#define NIC400_0_ASIB_0_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L +//NIC400_0_ASIB_0_KI_FC +#define NIC400_0_ASIB_0_KI_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_0_ASIB_0_KI_FC__ar_tgt_latency__SHIFT 0x8 +#define NIC400_0_ASIB_0_KI_FC__aw_tgt_latency_MASK 0x00000007L +#define NIC400_0_ASIB_0_KI_FC__ar_tgt_latency_MASK 0x00000700L +//NIC400_0_ASIB_0_QOS_RANGE +#define NIC400_0_ASIB_0_QOS_RANGE__aw_min_qos__SHIFT 0x0 +#define NIC400_0_ASIB_0_QOS_RANGE__aw_max_qos__SHIFT 0x8 +#define NIC400_0_ASIB_0_QOS_RANGE__ar_min_qos__SHIFT 0x10 +#define NIC400_0_ASIB_0_QOS_RANGE__ar_max_qos__SHIFT 0x18 +#define NIC400_0_ASIB_0_QOS_RANGE__aw_min_qos_MASK 0x0000000FL +#define NIC400_0_ASIB_0_QOS_RANGE__aw_max_qos_MASK 0x00000F00L +#define NIC400_0_ASIB_0_QOS_RANGE__ar_min_qos_MASK 0x000F0000L +#define NIC400_0_ASIB_0_QOS_RANGE__ar_max_qos_MASK 0x0F000000L +//NIC400_0_ASIB_1_FN_MOD +#define NIC400_0_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_0_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_0_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_0_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_0_ASIB_1_QOS_CNTL +#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_rate__SHIFT 0x0 +#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_rate__SHIFT 0x1 +#define NIC400_0_ASIB_1_QOS_CNTL__en_awar_rate__SHIFT 0x2 +#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_fc__SHIFT 0x3 +#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_fc__SHIFT 0x4 +#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_ot__SHIFT 0x5 +#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_ot__SHIFT 0x6 +#define NIC400_0_ASIB_1_QOS_CNTL__en_awar_ot__SHIFT 0x7 +#define NIC400_0_ASIB_1_QOS_CNTL__mode_aw_fc__SHIFT 0x10 +#define NIC400_0_ASIB_1_QOS_CNTL__mode_ar_fc__SHIFT 0x14 +#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_rate_MASK 0x00000001L +#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_rate_MASK 0x00000002L +#define NIC400_0_ASIB_1_QOS_CNTL__en_awar_rate_MASK 0x00000004L +#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_fc_MASK 0x00000008L +#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_fc_MASK 0x00000010L +#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_ot_MASK 0x00000020L +#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_ot_MASK 0x00000040L +#define NIC400_0_ASIB_1_QOS_CNTL__en_awar_ot_MASK 0x00000080L +#define NIC400_0_ASIB_1_QOS_CNTL__mode_aw_fc_MASK 0x00010000L +#define NIC400_0_ASIB_1_QOS_CNTL__mode_ar_fc_MASK 0x00100000L +//NIC400_0_ASIB_1_MAX_OT +#define NIC400_0_ASIB_1_MAX_OT__aw_max_otf__SHIFT 0x0 +#define NIC400_0_ASIB_1_MAX_OT__aw_max_oti__SHIFT 0x8 +#define NIC400_0_ASIB_1_MAX_OT__ar_max_otf__SHIFT 0x10 +#define NIC400_0_ASIB_1_MAX_OT__ar_max_oti__SHIFT 0x18 +#define NIC400_0_ASIB_1_MAX_OT__aw_max_otf_MASK 0x000000FFL +#define NIC400_0_ASIB_1_MAX_OT__aw_max_oti_MASK 0x00003F00L +#define NIC400_0_ASIB_1_MAX_OT__ar_max_otf_MASK 0x00FF0000L +#define NIC400_0_ASIB_1_MAX_OT__ar_max_oti_MASK 0x3F000000L +//NIC400_0_ASIB_1_MAX_COMB_OT +#define NIC400_0_ASIB_1_MAX_COMB_OT__awar_max_otf__SHIFT 0x0 +#define NIC400_0_ASIB_1_MAX_COMB_OT__awar_max_oti__SHIFT 0x8 +#define NIC400_0_ASIB_1_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL +#define NIC400_0_ASIB_1_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L +//NIC400_0_ASIB_1_AW_P +#define NIC400_0_ASIB_1_AW_P__aw_p__SHIFT 0x18 +#define NIC400_0_ASIB_1_AW_P__aw_p_MASK 0xFF000000L +//NIC400_0_ASIB_1_AW_B +#define NIC400_0_ASIB_1_AW_B__aw_b__SHIFT 0x0 +#define NIC400_0_ASIB_1_AW_B__aw_b_MASK 0x0000FFFFL +//NIC400_0_ASIB_1_AW_R +#define NIC400_0_ASIB_1_AW_R__aw_r__SHIFT 0x14 +#define NIC400_0_ASIB_1_AW_R__aw_r_MASK 0xFFF00000L +//NIC400_0_ASIB_1_AR_P +#define NIC400_0_ASIB_1_AR_P__ar_p__SHIFT 0x18 +#define NIC400_0_ASIB_1_AR_P__ar_p_MASK 0xFF000000L +//NIC400_0_ASIB_1_AR_B +#define NIC400_0_ASIB_1_AR_B__ar_b__SHIFT 0x0 +#define NIC400_0_ASIB_1_AR_B__ar_b_MASK 0x0000FFFFL +//NIC400_0_ASIB_1_AR_R +#define NIC400_0_ASIB_1_AR_R__ar_r__SHIFT 0x14 +#define NIC400_0_ASIB_1_AR_R__ar_r_MASK 0xFFF00000L +//NIC400_0_ASIB_1_TARGET_FC +#define NIC400_0_ASIB_1_TARGET_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_0_ASIB_1_TARGET_FC__ar_tgt_latency__SHIFT 0x10 +#define NIC400_0_ASIB_1_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL +#define NIC400_0_ASIB_1_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L +//NIC400_0_ASIB_1_KI_FC +#define NIC400_0_ASIB_1_KI_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_0_ASIB_1_KI_FC__ar_tgt_latency__SHIFT 0x8 +#define NIC400_0_ASIB_1_KI_FC__aw_tgt_latency_MASK 0x00000007L +#define NIC400_0_ASIB_1_KI_FC__ar_tgt_latency_MASK 0x00000700L +//NIC400_0_ASIB_1_QOS_RANGE +#define NIC400_0_ASIB_1_QOS_RANGE__aw_min_qos__SHIFT 0x0 +#define NIC400_0_ASIB_1_QOS_RANGE__aw_max_qos__SHIFT 0x8 +#define NIC400_0_ASIB_1_QOS_RANGE__ar_min_qos__SHIFT 0x10 +#define NIC400_0_ASIB_1_QOS_RANGE__ar_max_qos__SHIFT 0x18 +#define NIC400_0_ASIB_1_QOS_RANGE__aw_min_qos_MASK 0x0000000FL +#define NIC400_0_ASIB_1_QOS_RANGE__aw_max_qos_MASK 0x00000F00L +#define NIC400_0_ASIB_1_QOS_RANGE__ar_min_qos_MASK 0x000F0000L +#define NIC400_0_ASIB_1_QOS_RANGE__ar_max_qos_MASK 0x0F000000L +//NIC400_0_IB_0_FN_MOD +#define NIC400_0_IB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_0_IB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_0_IB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_0_IB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_1_AMIB_0_FN_MOD_BM_ISS +#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 +#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 +#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L +#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L +//NIC400_1_AMIB_0_FN_MOD +#define NIC400_1_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_1_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_1_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_1_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_1_ASIB_0_FN_MOD +#define NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_1_ASIB_0_QOS_CNTL +#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_rate__SHIFT 0x0 +#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_rate__SHIFT 0x1 +#define NIC400_1_ASIB_0_QOS_CNTL__en_awar_rate__SHIFT 0x2 +#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_fc__SHIFT 0x3 +#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_fc__SHIFT 0x4 +#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_ot__SHIFT 0x5 +#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_ot__SHIFT 0x6 +#define NIC400_1_ASIB_0_QOS_CNTL__en_awar_ot__SHIFT 0x7 +#define NIC400_1_ASIB_0_QOS_CNTL__mode_aw_fc__SHIFT 0x10 +#define NIC400_1_ASIB_0_QOS_CNTL__mode_ar_fc__SHIFT 0x14 +#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_rate_MASK 0x00000001L +#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_rate_MASK 0x00000002L +#define NIC400_1_ASIB_0_QOS_CNTL__en_awar_rate_MASK 0x00000004L +#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_fc_MASK 0x00000008L +#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_fc_MASK 0x00000010L +#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_ot_MASK 0x00000020L +#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_ot_MASK 0x00000040L +#define NIC400_1_ASIB_0_QOS_CNTL__en_awar_ot_MASK 0x00000080L +#define NIC400_1_ASIB_0_QOS_CNTL__mode_aw_fc_MASK 0x00010000L +#define NIC400_1_ASIB_0_QOS_CNTL__mode_ar_fc_MASK 0x00100000L +//NIC400_1_ASIB_0_MAX_OT +#define NIC400_1_ASIB_0_MAX_OT__aw_max_otf__SHIFT 0x0 +#define NIC400_1_ASIB_0_MAX_OT__aw_max_oti__SHIFT 0x8 +#define NIC400_1_ASIB_0_MAX_OT__ar_max_otf__SHIFT 0x10 +#define NIC400_1_ASIB_0_MAX_OT__ar_max_oti__SHIFT 0x18 +#define NIC400_1_ASIB_0_MAX_OT__aw_max_otf_MASK 0x000000FFL +#define NIC400_1_ASIB_0_MAX_OT__aw_max_oti_MASK 0x00003F00L +#define NIC400_1_ASIB_0_MAX_OT__ar_max_otf_MASK 0x00FF0000L +#define NIC400_1_ASIB_0_MAX_OT__ar_max_oti_MASK 0x3F000000L +//NIC400_1_ASIB_0_MAX_COMB_OT +#define NIC400_1_ASIB_0_MAX_COMB_OT__awar_max_otf__SHIFT 0x0 +#define NIC400_1_ASIB_0_MAX_COMB_OT__awar_max_oti__SHIFT 0x8 +#define NIC400_1_ASIB_0_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL +#define NIC400_1_ASIB_0_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L +//NIC400_1_ASIB_0_AW_P +#define NIC400_1_ASIB_0_AW_P__aw_p__SHIFT 0x18 +#define NIC400_1_ASIB_0_AW_P__aw_p_MASK 0xFF000000L +//NIC400_1_ASIB_0_AW_B +#define NIC400_1_ASIB_0_AW_B__aw_b__SHIFT 0x0 +#define NIC400_1_ASIB_0_AW_B__aw_b_MASK 0x0000FFFFL +//NIC400_1_ASIB_0_AW_R +#define NIC400_1_ASIB_0_AW_R__aw_r__SHIFT 0x14 +#define NIC400_1_ASIB_0_AW_R__aw_r_MASK 0xFFF00000L +//NIC400_1_ASIB_0_AR_P +#define NIC400_1_ASIB_0_AR_P__ar_p__SHIFT 0x18 +#define NIC400_1_ASIB_0_AR_P__ar_p_MASK 0xFF000000L +//NIC400_1_ASIB_0_AR_B +#define NIC400_1_ASIB_0_AR_B__ar_b__SHIFT 0x0 +#define NIC400_1_ASIB_0_AR_B__ar_b_MASK 0x0000FFFFL +//NIC400_1_ASIB_0_AR_R +#define NIC400_1_ASIB_0_AR_R__ar_r__SHIFT 0x14 +#define NIC400_1_ASIB_0_AR_R__ar_r_MASK 0xFFF00000L +//NIC400_1_ASIB_0_TARGET_FC +#define NIC400_1_ASIB_0_TARGET_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_1_ASIB_0_TARGET_FC__ar_tgt_latency__SHIFT 0x10 +#define NIC400_1_ASIB_0_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL +#define NIC400_1_ASIB_0_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L +//NIC400_1_ASIB_0_KI_FC +#define NIC400_1_ASIB_0_KI_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_1_ASIB_0_KI_FC__ar_tgt_latency__SHIFT 0x8 +#define NIC400_1_ASIB_0_KI_FC__aw_tgt_latency_MASK 0x00000007L +#define NIC400_1_ASIB_0_KI_FC__ar_tgt_latency_MASK 0x00000700L +//NIC400_1_ASIB_0_QOS_RANGE +#define NIC400_1_ASIB_0_QOS_RANGE__aw_min_qos__SHIFT 0x0 +#define NIC400_1_ASIB_0_QOS_RANGE__aw_max_qos__SHIFT 0x8 +#define NIC400_1_ASIB_0_QOS_RANGE__ar_min_qos__SHIFT 0x10 +#define NIC400_1_ASIB_0_QOS_RANGE__ar_max_qos__SHIFT 0x18 +#define NIC400_1_ASIB_0_QOS_RANGE__aw_min_qos_MASK 0x0000000FL +#define NIC400_1_ASIB_0_QOS_RANGE__aw_max_qos_MASK 0x00000F00L +#define NIC400_1_ASIB_0_QOS_RANGE__ar_min_qos_MASK 0x000F0000L +#define NIC400_1_ASIB_0_QOS_RANGE__ar_max_qos_MASK 0x0F000000L +//NIC400_1_ASIB_1_FN_MOD +#define NIC400_1_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_1_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_1_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_1_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_1_ASIB_1_QOS_CNTL +#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_rate__SHIFT 0x0 +#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_rate__SHIFT 0x1 +#define NIC400_1_ASIB_1_QOS_CNTL__en_awar_rate__SHIFT 0x2 +#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_fc__SHIFT 0x3 +#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_fc__SHIFT 0x4 +#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_ot__SHIFT 0x5 +#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_ot__SHIFT 0x6 +#define NIC400_1_ASIB_1_QOS_CNTL__en_awar_ot__SHIFT 0x7 +#define NIC400_1_ASIB_1_QOS_CNTL__mode_aw_fc__SHIFT 0x10 +#define NIC400_1_ASIB_1_QOS_CNTL__mode_ar_fc__SHIFT 0x14 +#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_rate_MASK 0x00000001L +#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_rate_MASK 0x00000002L +#define NIC400_1_ASIB_1_QOS_CNTL__en_awar_rate_MASK 0x00000004L +#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_fc_MASK 0x00000008L +#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_fc_MASK 0x00000010L +#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_ot_MASK 0x00000020L +#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_ot_MASK 0x00000040L +#define NIC400_1_ASIB_1_QOS_CNTL__en_awar_ot_MASK 0x00000080L +#define NIC400_1_ASIB_1_QOS_CNTL__mode_aw_fc_MASK 0x00010000L +#define NIC400_1_ASIB_1_QOS_CNTL__mode_ar_fc_MASK 0x00100000L +//NIC400_1_ASIB_1_MAX_OT +#define NIC400_1_ASIB_1_MAX_OT__aw_max_otf__SHIFT 0x0 +#define NIC400_1_ASIB_1_MAX_OT__aw_max_oti__SHIFT 0x8 +#define NIC400_1_ASIB_1_MAX_OT__ar_max_otf__SHIFT 0x10 +#define NIC400_1_ASIB_1_MAX_OT__ar_max_oti__SHIFT 0x18 +#define NIC400_1_ASIB_1_MAX_OT__aw_max_otf_MASK 0x000000FFL +#define NIC400_1_ASIB_1_MAX_OT__aw_max_oti_MASK 0x00003F00L +#define NIC400_1_ASIB_1_MAX_OT__ar_max_otf_MASK 0x00FF0000L +#define NIC400_1_ASIB_1_MAX_OT__ar_max_oti_MASK 0x3F000000L +//NIC400_1_ASIB_1_MAX_COMB_OT +#define NIC400_1_ASIB_1_MAX_COMB_OT__awar_max_otf__SHIFT 0x0 +#define NIC400_1_ASIB_1_MAX_COMB_OT__awar_max_oti__SHIFT 0x8 +#define NIC400_1_ASIB_1_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL +#define NIC400_1_ASIB_1_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L +//NIC400_1_ASIB_1_AW_P +#define NIC400_1_ASIB_1_AW_P__aw_p__SHIFT 0x18 +#define NIC400_1_ASIB_1_AW_P__aw_p_MASK 0xFF000000L +//NIC400_1_ASIB_1_AW_B +#define NIC400_1_ASIB_1_AW_B__aw_b__SHIFT 0x0 +#define NIC400_1_ASIB_1_AW_B__aw_b_MASK 0x0000FFFFL +//NIC400_1_ASIB_1_AW_R +#define NIC400_1_ASIB_1_AW_R__aw_r__SHIFT 0x14 +#define NIC400_1_ASIB_1_AW_R__aw_r_MASK 0xFFF00000L +//NIC400_1_ASIB_1_AR_P +#define NIC400_1_ASIB_1_AR_P__ar_p__SHIFT 0x18 +#define NIC400_1_ASIB_1_AR_P__ar_p_MASK 0xFF000000L +//NIC400_1_ASIB_1_AR_B +#define NIC400_1_ASIB_1_AR_B__ar_b__SHIFT 0x0 +#define NIC400_1_ASIB_1_AR_B__ar_b_MASK 0x0000FFFFL +//NIC400_1_ASIB_1_AR_R +#define NIC400_1_ASIB_1_AR_R__ar_r__SHIFT 0x14 +#define NIC400_1_ASIB_1_AR_R__ar_r_MASK 0xFFF00000L +//NIC400_1_ASIB_1_TARGET_FC +#define NIC400_1_ASIB_1_TARGET_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_1_ASIB_1_TARGET_FC__ar_tgt_latency__SHIFT 0x10 +#define NIC400_1_ASIB_1_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL +#define NIC400_1_ASIB_1_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L +//NIC400_1_ASIB_1_KI_FC +#define NIC400_1_ASIB_1_KI_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_1_ASIB_1_KI_FC__ar_tgt_latency__SHIFT 0x8 +#define NIC400_1_ASIB_1_KI_FC__aw_tgt_latency_MASK 0x00000007L +#define NIC400_1_ASIB_1_KI_FC__ar_tgt_latency_MASK 0x00000700L +//NIC400_1_ASIB_1_QOS_RANGE +#define NIC400_1_ASIB_1_QOS_RANGE__aw_min_qos__SHIFT 0x0 +#define NIC400_1_ASIB_1_QOS_RANGE__aw_max_qos__SHIFT 0x8 +#define NIC400_1_ASIB_1_QOS_RANGE__ar_min_qos__SHIFT 0x10 +#define NIC400_1_ASIB_1_QOS_RANGE__ar_max_qos__SHIFT 0x18 +#define NIC400_1_ASIB_1_QOS_RANGE__aw_min_qos_MASK 0x0000000FL +#define NIC400_1_ASIB_1_QOS_RANGE__aw_max_qos_MASK 0x00000F00L +#define NIC400_1_ASIB_1_QOS_RANGE__ar_min_qos_MASK 0x000F0000L +#define NIC400_1_ASIB_1_QOS_RANGE__ar_max_qos_MASK 0x0F000000L +//NIC400_1_IB_0_FN_MOD +#define NIC400_1_IB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_1_IB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_1_IB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_1_IB_0_FN_MOD__write_iss_override_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_syshub_mmreg_syshubdec +//SYSHUB_INDEX +#define SYSHUB_INDEX__INDEX__SHIFT 0x0 +#define SYSHUB_INDEX__INDEX_MASK 0xFFFFFFFFL +//SYSHUB_DATA +#define SYSHUB_DATA__DATA__SHIFT 0x0 +#define SYSHUB_DATA__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_rc_bifcfgdecp +//BIF_CFG_DEV0_RC_VENDOR_ID +#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_DEVICE_ID +#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_COMMAND +#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_RC_STATUS +#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC_REVISION_ID +#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_RC_PROG_INTERFACE +#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_RC_SUB_CLASS +#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC_BASE_CLASS +#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC_CACHE_LINE +#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_RC_LATENCY +#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_RC_HEADER +#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_RC_BIST +#define BIF_CFG_DEV0_RC_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_RC_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_RC_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_RC_BASE_ADDR_1 +#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_BASE_ADDR_2 +#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//SUB_BUS_NUMBER_LATENCY +#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//IO_BASE_LIMIT +#define IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//SECONDARY_STATUS +#define SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 +#define SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L +#define SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//MEM_BASE_LIMIT +#define MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//PREF_BASE_LIMIT +#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//PREF_BASE_UPPER +#define PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//PREF_LIMIT_UPPER +#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//IO_BASE_LIMIT_HI +#define IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_CAP_PTR +#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_RC_ROM_BASE_ADDR +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_RC_INTERRUPT_LINE +#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_RC_INTERRUPT_PIN +#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//IRQ_BRIDGE_CNTL +#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 +#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb +#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L +#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L +//EXT_BRIDGE_CNTL +#define EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIF_CFG_DEV0_RC_PMI_CAP_LIST +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC_PMI_CAP +#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_RC_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC_PCIE_CAP +#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_RC_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_RC_DEVICE_CAP +#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_RC_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +//BIF_CFG_DEV0_RC_DEVICE_CNTL +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV0_RC_DEVICE_STATUS +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_RC_LINK_CAP +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_LINK_CNTL +#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_RC_LINK_STATUS +#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//SLOT_CAP +#define SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//SLOT_CNTL +#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define SLOT_CNTL__INBAND_PD_DISABLE__SHIFT 0xe +#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +#define SLOT_CNTL__INBAND_PD_DISABLE_MASK 0x4000L +//SLOT_STATUS +#define SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//ROOT_CNTL +#define ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//ROOT_CAP +#define ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//ROOT_STATUS +#define ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIF_CFG_DEV0_RC_DEVICE_CAP2 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC_DEVICE_CNTL2 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_RC_DEVICE_STATUS2 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_LINK_CAP2 +#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC_LINK_CNTL2 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_RC_LINK_STATUS2 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//SLOT_CAP2 +#define SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT 0x0 +#define SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK 0x00000001L +//SLOT_CNTL2 +#define SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//SLOT_STATUS2 +#define SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_CAP_LIST +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC_MSI_MSG_CNTL +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_MSI_MSG_DATA +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//SSID_CAP_LIST +#define SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//SSID_CAP +#define SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_LINK_CAP_16GT +#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_LINK_CNTL_16GT +#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_LINK_STATUS_16GT +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_LINK_CAP_32GT +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_RC_LINK_CNTL_32GT +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_RC_LINK_STATUS_32GT +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_AP_CAP +#define BIF_CFG_DEV0_RC_AP_CAP__COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_AP_CAP__SEL_EN_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_AP_CAP__COUNT_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_AP_CAP__SEL_EN_SUPPORTED_MASK 0x00000100L +//BIF_CFG_DEV0_RC_AP_CNTL +#define BIF_CFG_DEV0_RC_AP_CNTL__INX_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_AP_CNTL__NEGO_GLOBAL_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_AP_CNTL__INX_SEL_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_AP_CNTL__NEGO_GLOBAL_EN_MASK 0x00000100L +//BIF_CFG_DEV0_RC_AP_DATA1 +#define BIF_CFG_DEV0_RC_AP_DATA1__USAGE_INFOR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_AP_DATA1__DETAILS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_AP_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_AP_DATA1__USAGE_INFOR_MASK 0x00000007L +#define BIF_CFG_DEV0_RC_AP_DATA1__DETAILS_MASK 0x0000FFE0L +#define BIF_CFG_DEV0_RC_AP_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_AP_DATA2 +#define BIF_CFG_DEV0_RC_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_AP_DATA2__MODIFIED_TS_INFOR2_MASK 0x00FFFFFFL +//BIF_CFG_DEV0_RC_AP_SEL_EN_MASK +#define BIF_CFG_DEV0_RC_AP_SEL_EN_MASK__PCIE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_AP_SEL_EN_MASK__OTHERS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_AP_SEL_EN_MASK__PCIE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_AP_SEL_EN_MASK__OTHERS_MASK 0xFFFFFFFEL +//BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//PCIE_ROOT_ERR_CMD +#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//PCIE_ROOT_ERR_STATUS +#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS__SHIFT 0x7 +#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS_MASK 0x00000180L +#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//PCIE_ERR_SRC_ID +#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_ACS_CAP +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_RC_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_RTR_DATA1 +#define BIF_CFG_DEV0_RC_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_RC_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_RC_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_RC_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC_RTR_DATA2 +#define BIF_CFG_DEV0_RC_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_RC_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_RC_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_CAP +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_PCRC_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE__SHIFT 0xd +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_XT_SUPPORTED__SHIFT 0x19 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_PCRC_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS_MASK 0x00001F00L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_MASK 0x0000E000L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_XT_SUPPORTED_MASK 0x02000000L +//BIF_CFG_DEV0_RC_IDE_CNTL +#define BIF_CFG_DEV0_RC_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED_MASK 0x00000004L +//BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL + + +#endif diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 736304e73ca4..024bfdb7c157 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -2505,12 +2505,12 @@ static ssize_t amdgpu_set_pm_policy_attr(struct device *dev, .dev_attr = __ATTR(_name, 0644, amdgpu_get_pm_policy_attr, \ amdgpu_set_pm_policy_attr), \ .id = PP_PM_POLICY_##_id, \ - }; + } #define AMDGPU_PM_POLICY_ATTR_VAR(_name) pm_policy_attr_##_name.dev_attr.attr -AMDGPU_PM_POLICY_ATTR(soc_pstate, SOC_PSTATE) -AMDGPU_PM_POLICY_ATTR(xgmi_plpd, XGMI_PLPD) +AMDGPU_PM_POLICY_ATTR(soc_pstate, SOC_PSTATE); +AMDGPU_PM_POLICY_ATTR(xgmi_plpd, XGMI_PLPD); static struct attribute *pm_policy_attrs[] = { &AMDGPU_PM_POLICY_ATTR_VAR(soc_pstate), diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c index 731355bdb9bc..3650e7beeb67 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c @@ -1333,12 +1333,13 @@ static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr) dev_id = adev->pdev->device; - if ((dpm_table->mclk_table.count >= 2) - && ((dev_id == 0x67B0) || (dev_id == 0x67B1))) { - smu_data->smc_state_table.MemoryLevel[1].MinVddci = - smu_data->smc_state_table.MemoryLevel[0].MinVddci; - smu_data->smc_state_table.MemoryLevel[1].MinMvdd = - smu_data->smc_state_table.MemoryLevel[0].MinMvdd; + if ((dpm_table->mclk_table.count >= 2) && + ((dev_id == 0x67B0) || (dev_id == 0x67B1)) && + (adev->pdev->revision == 0)) { + smu_data->smc_state_table.MemoryLevel[1].MinVddc = + smu_data->smc_state_table.MemoryLevel[0].MinVddc; + smu_data->smc_state_table.MemoryLevel[1].MinVddcPhases = + smu_data->smc_state_table.MemoryLevel[0].MinVddcPhases; } smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index 7f386ff0c872..9d8b1227388f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -425,6 +425,7 @@ static int aldebaran_set_default_dpm_table(struct smu_context *smu) dpm_table->dpm_levels[0].enabled = true; dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; dpm_table->dpm_levels[1].enabled = true; + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index cd0a23f432ff..b12388134489 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -783,6 +783,10 @@ int smu_v13_0_6_get_metrics_table(struct smu_context *smu, void *metrics_table, if (ret) return ret; + if (!memchr_inv(smu_table->metrics_table, 0xff, + min(16, table_size))) + return -EHWPOISON; + smu_table->metrics_time = jiffies; } @@ -1129,6 +1133,7 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; dpm_table->clk_type = SMU_GFXCLK; + dpm_table->flags = SMU_DPM_TABLE_FINE_GRAINED; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { /* In the case of gfxclk, only fine-grained dpm is honored. * Get min/max values from FW. @@ -2070,9 +2075,9 @@ static int smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu, return -EINVAL; if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { - if (min >= max) { + if (min > max) { dev_err(smu->adev->dev, - "Minimum clk should be less than the maximum allowed clock\n"); + "Minimum clk should be less/equal to the maximum allowed clock\n"); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index db85186f2d66..977590377021 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -63,6 +63,8 @@ for ((stack_idx) = 0; (umc_mask); \ (umc_mask) >>= 4, (stack_idx)++) \ +#define NUM_JPEG_RINGS_FW 10 + #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) #define SMU_15_0_8_FEA_MAP(smu_feature, smu_15_0_8_feature) \ @@ -171,6 +173,13 @@ static const struct cmn2asic_mapping smu_v15_0_8_table_map[SMU_TABLE_COUNT] = { TAB_MAP(I2C_COMMANDS), }; +static const uint8_t smu_v15_0_8_throttler_map[] = { + [THROTTLER_PROCHOT_BIT] = (SMU_THROTTLER_PROCHOT_GFX_BIT), + [THROTTLER_THERMAL_SOCKET_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT), + [THROTTLER_THERMAL_VR_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), + [THROTTLER_THERMAL_HBM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), +}; + static size_t smu_v15_0_8_get_system_metrics_size(void) { return sizeof(SystemMetricsTable_t); @@ -1062,38 +1071,30 @@ static int smu_v15_0_8_set_driver_pptable(struct smu_context *smu) smu_table->tables[SMU_TABLE_SMU_METRICS].version = table_version; - pptable->MaxSocketPowerLimit = - SMUQ10_ROUND(static_metrics->MaxSocketPowerLimit); - pptable->MaxGfxclkFrequency = - SMUQ10_ROUND(static_metrics->MaxGfxclkFrequency); - pptable->MinGfxclkFrequency = - SMUQ10_ROUND(static_metrics->MinGfxclkFrequency); - pptable->MaxFclkFrequency = - SMUQ10_ROUND(static_metrics->MaxFclkFrequency); - pptable->MinFclkFrequency = - SMUQ10_ROUND(static_metrics->MinFclkFrequency); - pptable->MaxGl2clkFrequency = - SMUQ10_ROUND(static_metrics->MaxGl2clkFrequency); - pptable->MinGl2clkFrequency = - SMUQ10_ROUND(static_metrics->MinGl2clkFrequency); + pptable->MaxSocketPowerLimit = static_metrics->MaxSocketPowerLimit; + pptable->MaxGfxclkFrequency = static_metrics->MaxGfxclkFrequency; + pptable->MinGfxclkFrequency = static_metrics->MinGfxclkFrequency; + pptable->MaxFclkFrequency = static_metrics->MaxFclkFrequency; + pptable->MinFclkFrequency = static_metrics->MinFclkFrequency; + pptable->MaxGl2clkFrequency = static_metrics->MaxGl2clkFrequency; + pptable->MinGl2clkFrequency = static_metrics->MinGl2clkFrequency; for (i = 0; i < ARRAY_SIZE(static_metrics->UclkFrequencyTable); ++i) - pptable->UclkFrequencyTable[i] = - SMUQ10_ROUND(static_metrics->UclkFrequencyTable[i]); + pptable->UclkFrequencyTable[i] = static_metrics->UclkFrequencyTable[i]; - pptable->SocclkFrequency = SMUQ10_ROUND(static_metrics->SocclkFrequency); - pptable->LclkFrequency = SMUQ10_ROUND(static_metrics->LclkFrequency); - pptable->VclkFrequency = SMUQ10_ROUND(static_metrics->VclkFrequency); - pptable->DclkFrequency = SMUQ10_ROUND(static_metrics->DclkFrequency); + pptable->SocclkFrequency = static_metrics->SocclkFrequency; + pptable->LclkFrequency = static_metrics->LclkFrequency; + pptable->VclkFrequency = static_metrics->VclkFrequency; + pptable->DclkFrequency = static_metrics->DclkFrequency; - pptable->CTFLimitMID = SMUQ10_ROUND(static_metrics->CTFLimit_MID); - pptable->CTFLimitAID = SMUQ10_ROUND(static_metrics->CTFLimit_AID); - pptable->CTFLimitXCD = SMUQ10_ROUND(static_metrics->CTFLimit_XCD); - pptable->CTFLimitHBM = SMUQ10_ROUND(static_metrics->CTFLimit_HBM); - pptable->ThermalLimitMID = SMUQ10_ROUND(static_metrics->ThermalLimit_MID); - pptable->ThermalLimitAID = SMUQ10_ROUND(static_metrics->ThermalLimit_AID); - pptable->ThermalLimitXCD = SMUQ10_ROUND(static_metrics->ThermalLimit_XCD); - pptable->ThermalLimitHBM = SMUQ10_ROUND(static_metrics->ThermalLimit_HBM); + pptable->CTFLimitMID = static_metrics->CTFLimit_MID; + pptable->CTFLimitAID = static_metrics->CTFLimit_AID; + pptable->CTFLimitXCD = static_metrics->CTFLimit_XCD; + pptable->CTFLimitHBM = static_metrics->CTFLimit_HBM; + pptable->ThermalLimitMID = static_metrics->ThermalLimit_MID; + pptable->ThermalLimitAID = static_metrics->ThermalLimit_AID; + pptable->ThermalLimitXCD = static_metrics->ThermalLimit_XCD; + pptable->ThermalLimitHBM = static_metrics->ThermalLimit_HBM; /* use MID0 serial number by default */ pptable->PublicSerialNumberMID = @@ -1601,6 +1602,81 @@ static ssize_t smu_v15_0_8_get_temp_metrics(struct smu_context *smu, } } +static ssize_t smu_v15_0_8_get_xcp_metrics(struct smu_context *smu, int xcp_id, + void *table) +{ + struct smu_table_context *smu_table = &smu->smu_table; + const u8 num_jpeg_rings = NUM_JPEG_RINGS_FW; + struct smu_v15_0_8_partition_metrics *xcp_metrics; + MetricsTable_t *metrics; + struct amdgpu_device *adev = smu->adev; + int ret, inst, i, j, k, idx; + struct amdgpu_xcp *xcp; + u32 inst_mask; + + if (!table) + return sizeof(*xcp_metrics); + + for_each_xcp(adev->xcp_mgr, xcp, i) { + if (xcp->id == xcp_id) + break; + } + if (i == adev->xcp_mgr->num_xcps) + return -EINVAL; + + xcp_metrics = (struct smu_v15_0_8_partition_metrics *)table; + smu_v15_0_8_partition_metrics_init(xcp_metrics, 1, 1); + + ret = smu_v15_0_8_get_metrics_table_internal(smu, 1, NULL); + if (ret) + return ret; + + metrics = (MetricsTable_t *)smu_table->metrics_table; + + amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); + idx = 0; + for_each_inst(k, inst_mask) { + /* Both JPEG and VCN has same instances */ + inst = GET_INST(VCN, k); + for (j = 0; j < num_jpeg_rings; ++j) { + xcp_metrics->jpeg_busy[(idx * num_jpeg_rings) + j] = + SMUQ10_ROUND(metrics->JpegBusy[(inst * num_jpeg_rings) + j]); + } + xcp_metrics->vcn_busy[idx] = + SMUQ10_ROUND(metrics->VcnBusy[inst]); + + xcp_metrics->current_vclk[idx] = SMUQ10_ROUND(metrics->VclkFrequency[inst]); + xcp_metrics->current_dclk[idx] = SMUQ10_ROUND(metrics->DclkFrequency[inst]); + + idx++; + } + + amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); + idx = 0; + for_each_inst(k, inst_mask) { + inst = GET_INST(GC, k); + xcp_metrics->current_gfxclk[idx] = + SMUQ10_ROUND(metrics->GfxclkFrequency[inst]); + + xcp_metrics->gfx_busy_inst[idx] = SMUQ10_ROUND(metrics->GfxBusy[inst]); + xcp_metrics->gfx_busy_acc[idx] = SMUQ10_ROUND(metrics->GfxBusyAcc[inst]); + xcp_metrics->gfx_below_host_limit_ppt_acc[idx] = + SMUQ10_ROUND(metrics->GfxclkBelowHostLimitPptAcc[inst]); + xcp_metrics->gfx_below_host_limit_thm_acc[idx] = + SMUQ10_ROUND(metrics->GfxclkBelowHostLimitThmAcc[inst]); + xcp_metrics->gfx_low_utilization_acc[idx] = + SMUQ10_ROUND(metrics->GfxclkLowUtilizationAcc[inst]); + xcp_metrics->gfx_below_host_limit_total_acc[idx] = + SMUQ10_ROUND(metrics->GfxclkBelowHostLimitTotalAcc[inst]); + idx++; + } + + xcp_metrics->accumulation_counter = metrics->AccumulationCounter; + xcp_metrics->firmware_timestamp = metrics->Timestamp; + + return sizeof(*xcp_metrics); +} + static ssize_t smu_v15_0_8_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; @@ -1627,17 +1703,23 @@ static ssize_t smu_v15_0_8_get_gpu_metrics(struct smu_context *smu, void **table if (adev->umc.active_mask) { u64 mask = adev->umc.active_mask; int out_idx = 0; + u16 max_hbm_temp = 0; int stack_idx; - if (unlikely(hweight64(mask)/4 > SMU_15_0_8_MAX_HBM_STACKS)) + if (unlikely(hweight64(mask) / 4 > SMU_15_0_8_MAX_HBM_STACKS)) { dev_warn(adev->dev, "Invalid umc mask %lld\n", mask); - else { + } else { for_each_hbm_stack(stack_idx, mask) { + u16 temp; + if (!hbm_stack_mask_valid(mask)) continue; - gpu_metrics->temperature_hbm[out_idx++] = - SMUQ10_ROUND(metrics->HbmTemperature[stack_idx]); + temp = SMUQ10_ROUND(metrics->HbmTemperature[stack_idx]); + gpu_metrics->temperature_hbm[out_idx++] = temp; + if (temp > max_hbm_temp) + max_hbm_temp = temp; } + gpu_metrics->temperature_mem = max_hbm_temp; } } @@ -2199,6 +2281,71 @@ static int smu_v15_0_8_get_ppt_limit(struct smu_context *smu, return -EOPNOTSUPP; } +static uint32_t smu_v15_0_8_get_throttler_status(struct smu_context *smu) +{ + struct smu_power_context *smu_power = &smu->smu_power; + struct smu_15_0_power_context *power_context = smu_power->power_context; + uint32_t throttler_status = 0; + + throttler_status = atomic_read(&power_context->throttle_status); + dev_dbg(smu->adev->dev, "SMU Throttler status: %u", throttler_status); + + return throttler_status; +} + +static const char *const throttling_logging_label[] = { + [THROTTLER_PROCHOT_BIT] = "Prochot", + [THROTTLER_THERMAL_SOCKET_BIT] = "SOC", + [THROTTLER_THERMAL_VR_BIT] = "VR", + [THROTTLER_THERMAL_HBM_BIT] = "HBM" +}; + +static void smu_v15_0_8_log_thermal_throttling_event(struct smu_context *smu) +{ + int throttler_idx, throttling_events = 0, buf_idx = 0; + struct amdgpu_device *adev = smu->adev; + uint32_t throttler_status; + char log_buf[256]; + + throttler_status = smu_v15_0_8_get_throttler_status(smu); + if (!throttler_status) + return; + + memset(log_buf, 0, sizeof(log_buf)); + for (throttler_idx = 0; + throttler_idx < ARRAY_SIZE(throttling_logging_label); + throttler_idx++) { + if (throttler_status & (1U << throttler_idx)) { + throttling_events++; + buf_idx += snprintf( + log_buf + buf_idx, sizeof(log_buf) - buf_idx, + "%s%s", throttling_events > 1 ? " and " : "", + throttling_logging_label[throttler_idx]); + if (buf_idx >= sizeof(log_buf)) { + dev_err(adev->dev, "buffer overflow!\n"); + log_buf[sizeof(log_buf) - 1] = '\0'; + break; + } + } + } + + dev_warn(adev->dev, + "WARN: GPU is throttled, expect performance decrease. %s.\n", + log_buf); + kgd2kfd_smi_event_throttle( + smu->adev->kfd.dev, + smu_cmn_get_indep_throttler_status(throttler_status, + smu_v15_0_8_throttler_map)); +} + +static int smu_v15_0_8_enable_thermal_alert(struct smu_context *smu) +{ + if (!smu->irq_source.num_types) + return 0; + + return amdgpu_irq_get(smu->adev, &smu->irq_source, 0); +} + static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .init_allowed_features = smu_v15_0_8_init_allowed_features, .set_default_dpm_table = smu_v15_0_8_set_default_dpm_table, @@ -2216,10 +2363,14 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .get_enabled_mask = smu_v15_0_8_get_enabled_mask, .feature_is_enabled = smu_cmn_feature_is_enabled, .register_irq_handler = smu_v15_0_8_register_irq_handler, + .enable_thermal_alert = smu_v15_0_8_enable_thermal_alert, + .disable_thermal_alert = smu_v15_0_disable_thermal_alert, + .log_thermal_throttling_event = smu_v15_0_8_log_thermal_throttling_event, .setup_pptable = smu_v15_0_8_setup_pptable, .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, .wait_for_event = smu_v15_0_wait_for_event, .get_pm_metrics = smu_v15_0_8_get_pm_metrics, + .get_xcp_metrics = smu_v15_0_8_get_xcp_metrics, .mode2_reset = smu_v15_0_8_mode2_reset, .get_dpm_ultimate_freq = smu_v15_0_8_get_dpm_ultimate_freq, .get_gpu_metrics = smu_v15_0_8_get_gpu_metrics, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h index 398ce4482174..4dfc40aaffcb 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h @@ -309,5 +309,39 @@ DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_gpuboard_temp_metrics, DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_baseboard_temp_metrics, SMU_15_0_8_BASEBOARD_TEMP_METRICS_FIELDS); +#define SMU_15_0_8_PARTITION_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ + SMU_ARRAY(SMU_MATTR(CURRENT_GFXCLK), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_gfxclk, SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(CURRENT_VCLK0), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_vclk, SMU_15_0_8_MAX_VCN); \ + SMU_ARRAY(SMU_MATTR(CURRENT_DCLK0), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_dclk, SMU_15_0_8_MAX_VCN); \ + SMU_ARRAY(SMU_MATTR(GFX_BUSY_INST), SMU_MUNIT(PERCENT), \ + SMU_MTYPE(U8), gfx_busy_inst, SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(JPEG_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U8), \ + jpeg_busy, SMU_15_0_8_MAX_JPEG); \ + SMU_ARRAY(SMU_MATTR(VCN_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U8), \ + vcn_busy, SMU_15_0_8_MAX_VCN); \ + SMU_ARRAY(SMU_MATTR(GFX_BUSY_ACC), SMU_MUNIT(NONE), SMU_MTYPE(U64), \ + gfx_busy_acc, SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_PPT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_ppt_acc, \ + SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_THM_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_thm_acc, \ + SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_LOW_UTILIZATION_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_low_utilization_acc, \ + SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \ + SMU_15_0_8_MAX_XCC); \ + SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), accumulation_counter); \ + SMU_SCALAR(SMU_MATTR(FIRMWARE_TIMESTAMP), SMU_MUNIT(TIME_2), \ + SMU_MTYPE(U64), firmware_timestamp); + +DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_partition_metrics, + SMU_15_0_8_PARTITION_METRICS_FIELDS); #endif #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 3d49e58794d2..90c7127beabf 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -1370,7 +1370,7 @@ int smu_cmn_print_dpm_clk_levels(struct smu_context *smu, level_index = 1; } - if (!is_fine_grained) { + if (!is_fine_grained || count == 1) { for (i = 0; i < count; i++) { freq_match = !is_deep_sleep && smu_cmn_freqs_match( diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c index 714af5c889d7..e8cb782a6f8e 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -75,7 +75,7 @@ static void komeda_crtc_update_clock_ratio(struct komeda_crtc_state *kcrtc_st) */ static int komeda_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -279,7 +279,7 @@ komeda_crtc_do_flush(struct drm_crtc *crtc, static void komeda_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state, crtc); @@ -325,7 +325,7 @@ komeda_crtc_flush_and_wait_for_flip_done(struct komeda_crtc *kcrtc, static void komeda_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state, crtc); @@ -387,7 +387,7 @@ komeda_crtc_atomic_disable(struct drm_crtc *crtc, static void komeda_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.c b/drivers/gpu/drm/arm/display/komeda/komeda_kms.c index 6ed504099188..faa8b041373a 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.c @@ -67,7 +67,7 @@ static const struct drm_driver komeda_kms_driver = { .minor = 1, }; -static void komeda_kms_atomic_commit_hw_done(struct drm_atomic_state *state) +static void komeda_kms_atomic_commit_hw_done(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; struct komeda_kms_dev *kms = to_kdev(dev); @@ -86,7 +86,7 @@ static void komeda_kms_atomic_commit_hw_done(struct drm_atomic_state *state) drm_atomic_helper_commit_hw_done(state); } -static void komeda_kms_commit_tail(struct drm_atomic_state *old_state) +static void komeda_kms_commit_tail(struct drm_atomic_commit *old_state) { struct drm_device *dev = old_state->dev; bool fence_cookie = dma_fence_begin_signalling(); @@ -153,7 +153,7 @@ static int komeda_plane_state_list_add(struct drm_plane_state *plane_st, static int komeda_crtc_normalize_zpos(struct drm_crtc *crtc, struct drm_crtc_state *crtc_st) { - struct drm_atomic_state *state = crtc_st->state; + struct drm_atomic_commit *state = crtc_st->state; struct komeda_crtc *kcrtc = to_kcrtc(crtc); struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(crtc_st); struct komeda_plane_state *kplane_st; @@ -216,7 +216,7 @@ static int komeda_crtc_normalize_zpos(struct drm_crtc *crtc, } static int komeda_kms_check(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_st; @@ -228,7 +228,7 @@ static int komeda_kms_check(struct drm_device *dev, /* Komeda need to re-calculate resource assumption in every commit * so need to add all affected_planes (even unchanged) to - * drm_atomic_state. + * drm_atomic_commit. */ for_each_new_crtc_in_state(state, crtc, new_crtc_st, i) { err = drm_atomic_add_affected_planes(state, crtc); diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h index bbee6da43164..955f9f683ce3 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h @@ -155,7 +155,7 @@ struct komeda_component_output { * @komeda_scaler_state */ struct komeda_component_state { - /** @obj: tracking component_state by drm_atomic_state */ + /** @obj: tracking component_state by drm_atomic_commit */ struct drm_private_state obj; /** @component: backpointer to the component */ struct komeda_component *component; @@ -388,7 +388,7 @@ struct komeda_pipeline_funcs { * Represent a complete display pipeline and hold all functional components. */ struct komeda_pipeline { - /** @obj: link pipeline as private obj of drm_atomic_state */ + /** @obj: link pipeline as private obj of drm_atomic_commit */ struct drm_private_obj obj; /** @mdev: the parent komeda_dev */ struct komeda_dev *mdev; @@ -448,10 +448,10 @@ struct komeda_pipeline { * * NOTE: * Unlike the pipeline, pipeline_state doesn’t gather any component_state - * into it. It because all component will be managed by drm_atomic_state. + * into it. It because all component will be managed by drm_atomic_commit. */ struct komeda_pipeline_state { - /** @obj: tracking pipeline_state by drm_atomic_state */ + /** @obj: tracking pipeline_state by drm_atomic_commit */ struct drm_private_state obj; /** @pipe: backpointer to the pipeline */ struct komeda_pipeline *pipe; @@ -555,11 +555,11 @@ int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe, struct komeda_pipeline_state * komeda_pipeline_get_old_state(struct komeda_pipeline *pipe, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); bool komeda_pipeline_disable(struct komeda_pipeline *pipe, - struct drm_atomic_state *old_state); + struct drm_atomic_commit *old_state); void komeda_pipeline_update(struct komeda_pipeline *pipe, - struct drm_atomic_state *old_state); + struct drm_atomic_commit *old_state); void komeda_complete_data_flow_cfg(struct komeda_layer *layer, struct komeda_data_flow_cfg *dflow, diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c index 6f9b10cc831f..457b21397014 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c @@ -22,7 +22,7 @@ static inline bool is_switching_user(void *old, void *new) static struct komeda_pipeline_state * komeda_pipeline_get_state(struct komeda_pipeline *pipe, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_private_state *priv_st; @@ -35,7 +35,7 @@ komeda_pipeline_get_state(struct komeda_pipeline *pipe, struct komeda_pipeline_state * komeda_pipeline_get_old_state(struct komeda_pipeline *pipe, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_private_state *priv_st; @@ -47,7 +47,7 @@ komeda_pipeline_get_old_state(struct komeda_pipeline *pipe, static struct komeda_pipeline_state * komeda_pipeline_get_new_state(struct komeda_pipeline *pipe, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_private_state *priv_st; @@ -60,7 +60,7 @@ komeda_pipeline_get_new_state(struct komeda_pipeline *pipe, /* Assign pipeline for crtc */ static struct komeda_pipeline_state * komeda_pipeline_get_state_and_set_crtc(struct komeda_pipeline *pipe, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_crtc *crtc) { struct komeda_pipeline_state *st; @@ -97,7 +97,7 @@ komeda_pipeline_get_state_and_set_crtc(struct komeda_pipeline *pipe, static struct komeda_component_state * komeda_component_get_state(struct komeda_component *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_private_state *priv_st; @@ -112,7 +112,7 @@ komeda_component_get_state(struct komeda_component *c, static struct komeda_component_state * komeda_component_get_old_state(struct komeda_component *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_private_state *priv_st; @@ -149,7 +149,7 @@ komeda_component_get_old_state(struct komeda_component *c, */ static struct komeda_component_state * komeda_component_get_state_and_set_user(struct komeda_component *c, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, void *user, struct drm_crtc *crtc) { @@ -253,7 +253,7 @@ komeda_component_validate_private(struct komeda_component *c, /* Get current available scaler from the component->supported_outputs */ static struct komeda_scaler * komeda_component_get_avail_scaler(struct komeda_component *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct komeda_pipeline_state *pipe_st; u32 avail_scalers; @@ -505,7 +505,7 @@ komeda_scaler_validate(void *user, struct komeda_crtc_state *kcrtc_st, struct komeda_data_flow_cfg *dflow) { - struct drm_atomic_state *drm_st = kcrtc_st->base.state; + struct drm_atomic_commit *drm_st = kcrtc_st->base.state; struct komeda_component_state *c_st; struct komeda_scaler_state *st; struct komeda_scaler *scaler; @@ -669,7 +669,7 @@ komeda_compiz_set_input(struct komeda_compiz *compiz, struct komeda_crtc_state *kcrtc_st, struct komeda_data_flow_cfg *dflow) { - struct drm_atomic_state *drm_st = kcrtc_st->base.state; + struct drm_atomic_commit *drm_st = kcrtc_st->base.state; struct komeda_component_state *c_st, *old_st; struct komeda_compiz_input_cfg *cin; u16 compiz_w, compiz_h; @@ -1227,7 +1227,7 @@ static int komeda_pipeline_unbound_components(struct komeda_pipeline *pipe, struct komeda_pipeline_state *new) { - struct drm_atomic_state *drm_st = new->obj.state; + struct drm_atomic_commit *drm_st = new->obj.state; struct komeda_pipeline_state *old = priv_to_pipe_st(pipe->obj.state); struct komeda_component_state *c_st; struct komeda_component *c; @@ -1255,7 +1255,7 @@ komeda_pipeline_unbound_components(struct komeda_pipeline *pipe, int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe, struct komeda_crtc_state *kcrtc_st) { - struct drm_atomic_state *drm_st = kcrtc_st->base.state; + struct drm_atomic_commit *drm_st = kcrtc_st->base.state; struct komeda_pipeline_state *st; /* ignore the pipeline which is not affected */ @@ -1285,7 +1285,7 @@ int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe, * false: disable is complete. */ bool komeda_pipeline_disable(struct komeda_pipeline *pipe, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct komeda_pipeline_state *old; struct komeda_component *c; @@ -1330,7 +1330,7 @@ bool komeda_pipeline_disable(struct komeda_pipeline *pipe, } void komeda_pipeline_update(struct komeda_pipeline *pipe, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct komeda_pipeline_state *new = priv_to_pipe_st(pipe->obj.state); struct komeda_pipeline_state *old; diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c index 835c11fdd7ff..57a4a0c7d404 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c @@ -69,7 +69,7 @@ komeda_plane_init_data_flow(struct drm_plane_state *st, */ static int komeda_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -116,7 +116,7 @@ komeda_plane_atomic_check(struct drm_plane *plane, */ static void komeda_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { } diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c index 4b4a08cb396d..8565749a3e48 100644 --- a/drivers/gpu/drm/arm/hdlcd_crtc.c +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c @@ -175,7 +175,7 @@ static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc) } static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); @@ -186,7 +186,7 @@ static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc, } static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); @@ -212,7 +212,7 @@ static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc, } static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_pending_vblank_event *event = crtc->state->event; @@ -236,7 +236,7 @@ static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = { }; static int hdlcd_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -267,7 +267,7 @@ static int hdlcd_plane_atomic_check(struct drm_plane *plane, } static void hdlcd_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c index 18e6157b1047..ebe8e1078777 100644 --- a/drivers/gpu/drm/arm/malidp_crtc.c +++ b/drivers/gpu/drm/arm/malidp_crtc.c @@ -47,7 +47,7 @@ static enum drm_mode_status malidp_crtc_mode_valid(struct drm_crtc *crtc, } static void malidp_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct malidp_drm *malidp = crtc_to_malidp_device(crtc); struct malidp_hw_device *hwdev = malidp->dev; @@ -71,7 +71,7 @@ static void malidp_crtc_atomic_enable(struct drm_crtc *crtc, } static void malidp_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -334,7 +334,7 @@ static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc, } static int malidp_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index b765f6c9eea4..9abe800f598a 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -190,7 +190,7 @@ static int malidp_set_and_wait_config_valid(struct drm_device *drm) return (ret > 0) ? 0 : -ETIMEDOUT; } -static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state) +static void malidp_atomic_commit_hw_done(struct drm_atomic_commit *state) { struct drm_device *drm = state->dev; struct malidp_drm *malidp = drm_to_malidp(drm); @@ -231,7 +231,7 @@ static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state) drm_atomic_helper_commit_hw_done(state); } -static void malidp_atomic_commit_tail(struct drm_atomic_state *state) +static void malidp_atomic_commit_tail(struct drm_atomic_commit *state) { struct drm_device *drm = state->dev; struct malidp_drm *malidp = drm_to_malidp(drm); diff --git a/drivers/gpu/drm/arm/malidp_mw.c b/drivers/gpu/drm/arm/malidp_mw.c index fad343842038..f8be65119e3b 100644 --- a/drivers/gpu/drm/arm/malidp_mw.c +++ b/drivers/gpu/drm/arm/malidp_mw.c @@ -237,7 +237,7 @@ int malidp_mw_connector_init(struct drm_device *drm) } void malidp_mw_atomic_commit(struct drm_device *drm, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct malidp_drm *malidp = drm_to_malidp(drm); struct drm_writeback_connector *mw_conn = &malidp->mw_connector; diff --git a/drivers/gpu/drm/arm/malidp_mw.h b/drivers/gpu/drm/arm/malidp_mw.h index 19a007676a1d..53a2d6a956a9 100644 --- a/drivers/gpu/drm/arm/malidp_mw.h +++ b/drivers/gpu/drm/arm/malidp_mw.h @@ -10,5 +10,5 @@ int malidp_mw_connector_init(struct drm_device *drm); void malidp_mw_atomic_commit(struct drm_device *drm, - struct drm_atomic_state *old_state); + struct drm_atomic_commit *old_state); #endif diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c index 4b9876322501..60b3f2bb153b 100644 --- a/drivers/gpu/drm/arm/malidp_planes.c +++ b/drivers/gpu/drm/arm/malidp_planes.c @@ -490,7 +490,7 @@ static void malidp_de_prefetch_settings(struct malidp_plane *mp, } static int malidp_de_plane_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -779,7 +779,7 @@ static void malidp_de_set_plane_afbc(struct drm_plane *plane) } static void malidp_de_plane_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -900,7 +900,7 @@ static void malidp_de_plane_update(struct drm_plane *plane, } static void malidp_de_plane_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct malidp_plane *mp = to_malidp_plane(plane); diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index d40bb9cf9ff1..5e006212fea0 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -414,7 +414,7 @@ static void armada_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) } static int armada_drm_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -430,7 +430,7 @@ static int armada_drm_crtc_atomic_check(struct drm_crtc *crtc, } static void armada_drm_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -446,7 +446,7 @@ static void armada_drm_crtc_atomic_begin(struct drm_crtc *crtc, } static void armada_drm_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -474,7 +474,7 @@ static void armada_drm_crtc_atomic_flush(struct drm_crtc *crtc, } static void armada_drm_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -512,7 +512,7 @@ static void armada_drm_crtc_atomic_disable(struct drm_crtc *crtc, } static void armada_drm_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 361fdcece4b0..3da0b857ef95 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -69,7 +69,7 @@ static inline u32 armada_csc(struct drm_plane_state *state) /* === Plane support === */ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -220,7 +220,7 @@ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, } static void armada_drm_overlay_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -262,7 +262,7 @@ armada_overlay_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, struct drm_modeset_acquire_ctx *ctx) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_plane_state *plane_state; int ret = 0; @@ -270,7 +270,7 @@ armada_overlay_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, crtc_x, crtc_y, crtc_w, crtc_h, src_x, src_y, src_w, src_h); - state = drm_atomic_state_alloc(plane->dev); + state = drm_atomic_commit_alloc(plane->dev); if (!state) return -ENOMEM; @@ -297,7 +297,7 @@ armada_overlay_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, ret = drm_atomic_nonblocking_commit(state); fail: - drm_atomic_state_put(state); + drm_atomic_commit_put(state); return ret; } diff --git a/drivers/gpu/drm/armada/armada_plane.c b/drivers/gpu/drm/armada/armada_plane.c index eba12bba1e09..fe46a8e4508a 100644 --- a/drivers/gpu/drm/armada/armada_plane.c +++ b/drivers/gpu/drm/armada/armada_plane.c @@ -80,7 +80,7 @@ void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[2][3], } int armada_drm_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -130,7 +130,7 @@ int armada_drm_plane_atomic_check(struct drm_plane *plane, } static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -220,7 +220,7 @@ static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane, } static void armada_drm_primary_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); diff --git a/drivers/gpu/drm/armada/armada_plane.h b/drivers/gpu/drm/armada/armada_plane.h index 368415c609a6..69bef09ea028 100644 --- a/drivers/gpu/drm/armada/armada_plane.h +++ b/drivers/gpu/drm/armada/armada_plane.h @@ -24,7 +24,7 @@ void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[2][3], void armada_drm_plane_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state); int armada_drm_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void armada_plane_reset(struct drm_plane *plane); struct drm_plane_state *armada_plane_duplicate_state(struct drm_plane *plane); void armada_plane_destroy_state(struct drm_plane *plane, diff --git a/drivers/gpu/drm/ast/ast_cursor.c b/drivers/gpu/drm/ast/ast_cursor.c index 3fa8e75db9c0..fd19c45f2abe 100644 --- a/drivers/gpu/drm/ast/ast_cursor.c +++ b/drivers/gpu/drm/ast/ast_cursor.c @@ -164,7 +164,7 @@ static const uint32_t ast_cursor_plane_formats[] = { }; static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); struct drm_framebuffer *new_fb = new_plane_state->fb; @@ -244,7 +244,7 @@ static const u8 *ast_cursor_plane_get_argb4444(struct ast_cursor_plane *ast_curs } static void ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane); struct ast_plane *ast_plane = to_ast_plane(plane); @@ -309,7 +309,7 @@ static void ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, } static void ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(plane->dev); diff --git a/drivers/gpu/drm/ast/ast_dp.c b/drivers/gpu/drm/ast/ast_dp.c index 9d07dad358cf..5f266a05419b 100644 --- a/drivers/gpu/drm/ast/ast_dp.c +++ b/drivers/gpu/drm/ast/ast_dp.c @@ -359,7 +359,7 @@ static void ast_astdp_encoder_helper_atomic_mode_set(struct drm_encoder *encoder } static void ast_astdp_encoder_helper_atomic_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(encoder->dev); struct ast_connector *ast_connector = &ast->output.astdp.connector; @@ -374,7 +374,7 @@ static void ast_astdp_encoder_helper_atomic_enable(struct drm_encoder *encoder, } static void ast_astdp_encoder_helper_atomic_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(encoder->dev); diff --git a/drivers/gpu/drm/ast/ast_dp501.c b/drivers/gpu/drm/ast/ast_dp501.c index 98d8491ce6c9..6d6ccfad1415 100644 --- a/drivers/gpu/drm/ast/ast_dp501.c +++ b/drivers/gpu/drm/ast/ast_dp501.c @@ -469,7 +469,7 @@ static const struct drm_encoder_funcs ast_dp501_encoder_funcs = { }; static void ast_dp501_encoder_helper_atomic_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(encoder->dev); @@ -477,7 +477,7 @@ static void ast_dp501_encoder_helper_atomic_enable(struct drm_encoder *encoder, } static void ast_dp501_encoder_helper_atomic_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(encoder->dev); diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c index 91b83ec00e9c..d5ed8c5c7925 100644 --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c @@ -507,7 +507,7 @@ static const uint32_t ast_primary_plane_formats[] = { }; static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = plane->dev; struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -555,7 +555,7 @@ static void ast_handle_damage(struct ast_plane *ast_plane, struct iosys_map *src } static void ast_primary_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = plane->dev; struct ast_device *ast = to_ast_device(dev); @@ -599,7 +599,7 @@ static void ast_primary_plane_helper_atomic_update(struct drm_plane *plane, } static void ast_primary_plane_helper_atomic_enable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(plane->dev); struct ast_plane *ast_plane = to_ast_plane(plane); @@ -614,7 +614,7 @@ static void ast_primary_plane_helper_atomic_enable(struct drm_plane *plane, } static void ast_primary_plane_helper_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { /* * Keep this empty function to avoid calling @@ -722,7 +722,7 @@ static void ast_crtc_helper_mode_set_nofb(struct drm_crtc *crtc) } static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; @@ -822,7 +822,7 @@ static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc, static void ast_crtc_helper_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -844,7 +844,7 @@ ast_crtc_helper_atomic_flush(struct drm_crtc *crtc, } } -static void ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) +static void ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(crtc->dev); u8 vgacr17 = 0x00; @@ -857,7 +857,7 @@ static void ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atom ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xfc, vgacrb6); } -static void ast_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state) +static void ast_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); struct ast_device *ast = to_ast_device(crtc->dev); @@ -966,7 +966,7 @@ static int ast_crtc_init(struct ast_device *ast) * Mode config */ -static void ast_mode_config_helper_atomic_commit_tail(struct drm_atomic_state *state) +static void ast_mode_config_helper_atomic_commit_tail(struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(state->dev); diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index d8cf3d231920..9dbac2def333 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -200,7 +200,7 @@ atmel_hlcdc_crtc_mode_valid(struct drm_crtc *c, } static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = c->dev; struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); @@ -252,7 +252,7 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, } static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = c->dev; struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); @@ -458,7 +458,7 @@ static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state) } static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *s = drm_atomic_get_new_crtc_state(state, c); int ret; @@ -475,13 +475,13 @@ static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c, } static void atmel_hlcdc_crtc_atomic_begin(struct drm_crtc *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { drm_crtc_vblank_on(c); } static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); unsigned long flags; diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c index 97482fc82ec2..2f41bce574dc 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -983,7 +983,7 @@ static int atmel_hlcdc_dc_drm_suspend(struct device *dev) struct drm_device *drm_dev = dev_get_drvdata(dev); struct atmel_hlcdc_dc *dc = drm_dev->dev_private; struct regmap *regmap = dc->hlcdc->regmap; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; state = drm_atomic_helper_suspend(drm_dev); if (IS_ERR(state)) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h index 26b26185cf34..390dfbf3c77d 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -354,7 +354,7 @@ struct atmel_hlcdc_dc { struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS]; struct { u32 imr; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; } suspend; }; diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c index bccd1564216e..f17a832351e9 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c @@ -718,7 +718,7 @@ atmel_hlcdc_plane_update_disc_area(struct atmel_hlcdc_plane *plane, } static int atmel_hlcdc_plane_atomic_check(struct drm_plane *p, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *s = drm_atomic_get_new_plane_state(state, p); struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); @@ -869,7 +869,7 @@ static void atmel_xlcdc_atomic_disable(struct atmel_hlcdc_plane *plane, } static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; @@ -919,7 +919,7 @@ static void atmel_xlcdc_atomic_update(struct atmel_hlcdc_plane *plane, } static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_s = drm_atomic_get_new_plane_state(state, p); diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c index f318080f1139..821a3008a1e7 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c @@ -781,7 +781,7 @@ static const struct adv7511 *bridge_to_adv7511_const(const struct drm_bridge *br } static void adv7511_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct adv7511 *adv = bridge_to_adv7511(bridge); struct drm_connector *connector; @@ -810,7 +810,7 @@ static void adv7511_bridge_atomic_enable(struct drm_bridge *bridge, } static void adv7511_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct adv7511 *adv = bridge_to_adv7511(bridge); diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index 3e46350170d4..8cf6b73bceac 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -928,7 +928,7 @@ static int analogix_dp_bridge_attach(struct drm_bridge *bridge, static struct drm_crtc *analogix_dp_get_old_crtc(struct analogix_dp_device *dp, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_encoder *encoder = dp->encoder; struct drm_connector *connector; @@ -947,7 +947,7 @@ struct drm_crtc *analogix_dp_get_old_crtc(struct analogix_dp_device *dp, static struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_encoder *encoder = dp->encoder; struct drm_connector *connector; @@ -965,7 +965,7 @@ struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp, } static void analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct analogix_dp_device *dp = to_dp(bridge); struct drm_crtc *crtc; @@ -1018,7 +1018,7 @@ static int analogix_dp_set_bridge(struct analogix_dp_device *dp) } static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, const struct drm_display_mode *mode) { struct analogix_dp_device *dp = to_dp(bridge); @@ -1101,7 +1101,7 @@ static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge, } static void analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct analogix_dp_device *dp = to_dp(bridge); struct drm_crtc *crtc; @@ -1162,7 +1162,7 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge) } static void analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct analogix_dp_device *dp = to_dp(bridge); struct drm_crtc *old_crtc, *new_crtc; @@ -1200,7 +1200,7 @@ static void analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge, } static void analogix_dp_bridge_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct analogix_dp_device *dp = to_dp(bridge); struct drm_crtc *crtc; diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 54b02242d6db..513c11cdbc74 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -2559,7 +2559,7 @@ static int anx7625_bridge_atomic_check(struct drm_bridge *bridge, } static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct anx7625_data *ctx = bridge_to_anx7625(bridge); struct device *dev = ctx->dev; @@ -2598,7 +2598,7 @@ static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, } static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct anx7625_data *ctx = bridge_to_anx7625(bridge); struct device *dev = ctx->dev; diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c index e07a9892df4e..cf90d4468b5c 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c @@ -591,7 +591,7 @@ cdns_dsi_bridge_mode_valid(struct drm_bridge *bridge, } static void cdns_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge); struct cdns_dsi *dsi = input_to_dsi(input); @@ -701,7 +701,7 @@ static void cdns_dsi_init_link(struct cdns_dsi *dsi) } static void cdns_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge); struct cdns_dsi *dsi = input_to_dsi(input); diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c index 064c6915c896..36c07b71fe04 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c @@ -1750,7 +1750,7 @@ static void cdns_mhdp_sst_enable(struct cdns_mhdp_device *mhdp, } static void cdns_mhdp_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct cdns_mhdp_device *mhdp = bridge_to_mhdp(bridge); struct cdns_mhdp_bridge_state *mhdp_state; @@ -1841,7 +1841,7 @@ static void cdns_mhdp_atomic_enable(struct drm_bridge *bridge, } static void cdns_mhdp_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct cdns_mhdp_device *mhdp = bridge_to_mhdp(bridge); u32 resp; @@ -1963,7 +1963,7 @@ static int cdns_mhdp_atomic_check(struct drm_bridge *bridge, struct cdns_mhdp_device *mhdp = bridge_to_mhdp(bridge); const struct drm_display_mode *mode = &crtc_state->adjusted_mode; struct drm_connector_state *old_state, *new_state; - struct drm_atomic_state *state = crtc_state->state; + struct drm_atomic_commit *state = crtc_state->state; struct drm_connector *conn = mhdp->connector; u64 old_cp, new_cp; diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c b/drivers/gpu/drm/bridge/chipone-icn6211.c index 814713c5bea9..08775381b075 100644 --- a/drivers/gpu/drm/bridge/chipone-icn6211.c +++ b/drivers/gpu/drm/bridge/chipone-icn6211.c @@ -341,7 +341,7 @@ static void chipone_configure_pll(struct chipone *icn, } static void chipone_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct chipone *icn = bridge_to_chipone(bridge); struct drm_display_mode *mode = &icn->mode; @@ -444,7 +444,7 @@ static void chipone_atomic_enable(struct drm_bridge *bridge, } static void chipone_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct chipone *icn = bridge_to_chipone(bridge); int ret; @@ -481,7 +481,7 @@ static void chipone_atomic_pre_enable(struct drm_bridge *bridge, } static void chipone_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct chipone *icn = bridge_to_chipone(bridge); diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c index 7b71cde173e0..9bfaa3f93370 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -124,7 +124,7 @@ static int fsl_ldb_attach(struct drm_bridge *bridge, } static void fsl_ldb_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); const struct drm_bridge_state *bridge_state; @@ -228,7 +228,7 @@ static void fsl_ldb_atomic_enable(struct drm_bridge *bridge, } static void fsl_ldb_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c index 15fbb1be07cd..7d5fda7173e5 100644 --- a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c +++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c @@ -49,7 +49,7 @@ static int imx8mp_hdmi_pvi_bridge_attach(struct drm_bridge *bridge, } static void imx8mp_hdmi_pvi_bridge_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct imx8mp_hdmi_pvi *pvi = to_imx8mp_hdmi_pvi(bridge); struct drm_connector_state *conn_state; @@ -89,7 +89,7 @@ static void imx8mp_hdmi_pvi_bridge_enable(struct drm_bridge *bridge, } static void imx8mp_hdmi_pvi_bridge_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct imx8mp_hdmi_pvi *pvi = to_imx8mp_hdmi_pvi(bridge); diff --git a/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c b/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c index bdecee56fa49..a6ca4f5c6cc6 100644 --- a/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c +++ b/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c @@ -201,7 +201,7 @@ imx8qm_ldb_bridge_mode_set(struct drm_bridge *bridge, } static void imx8qm_ldb_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ldb_channel *ldb_ch = bridge->driver_private; struct ldb *ldb = ldb_ch->ldb; @@ -247,7 +247,7 @@ static void imx8qm_ldb_bridge_atomic_enable(struct drm_bridge *bridge, } static void imx8qm_ldb_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ldb_channel *ldb_ch = bridge->driver_private; struct ldb *ldb = ldb_ch->ldb; diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c index fbd7a37c0812..a7906314ade1 100644 --- a/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c @@ -216,7 +216,7 @@ imx8qxp_ldb_bridge_mode_set(struct drm_bridge *bridge, } static void imx8qxp_ldb_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ldb_channel *ldb_ch = bridge->driver_private; struct ldb *ldb = ldb_ch->ldb; @@ -232,7 +232,7 @@ static void imx8qxp_ldb_bridge_atomic_pre_enable(struct drm_bridge *bridge, } static void imx8qxp_ldb_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ldb_channel *ldb_ch = bridge->driver_private; struct ldb *ldb = ldb_ch->ldb; @@ -266,7 +266,7 @@ static void imx8qxp_ldb_bridge_atomic_enable(struct drm_bridge *bridge, } static void imx8qxp_ldb_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ldb_channel *ldb_ch = bridge->driver_private; struct ldb *ldb = ldb_ch->ldb; diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c index 5582456a4490..e0ee51a9ca7f 100644 --- a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c @@ -176,7 +176,7 @@ imx8qxp_pc_bridge_mode_set(struct drm_bridge *bridge, } static void imx8qxp_pc_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct imx8qxp_pc_channel *ch = bridge->driver_private; struct imx8qxp_pc *pc = ch->pc; diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c index 63a8d8b1f76b..ee6b6dbbe952 100644 --- a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c @@ -154,7 +154,7 @@ imx8qxp_pixel_link_bridge_mode_set(struct drm_bridge *bridge, } static void imx8qxp_pixel_link_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct imx8qxp_pixel_link *pl = bridge->driver_private; @@ -164,7 +164,7 @@ static void imx8qxp_pixel_link_bridge_atomic_enable(struct drm_bridge *bridge, } static void imx8qxp_pixel_link_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct imx8qxp_pixel_link *pl = bridge->driver_private; diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c index 441fd32dc91c..2e59f53f0eb6 100644 --- a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c @@ -133,7 +133,7 @@ imx8qxp_pxl2dpi_bridge_mode_set(struct drm_bridge *bridge, } static void imx8qxp_pxl2dpi_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct imx8qxp_pxl2dpi *p2d = bridge->driver_private; diff --git a/drivers/gpu/drm/bridge/inno-hdmi.c b/drivers/gpu/drm/bridge/inno-hdmi.c index 87422d15d9a2..1091af29ad8f 100644 --- a/drivers/gpu/drm/bridge/inno-hdmi.c +++ b/drivers/gpu/drm/bridge/inno-hdmi.c @@ -756,7 +756,7 @@ static int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi, return 0; } -static int inno_hdmi_setup(struct inno_hdmi *hdmi, struct drm_atomic_state *state) +static int inno_hdmi_setup(struct inno_hdmi *hdmi, struct drm_atomic_commit *state) { struct drm_bridge *bridge = &hdmi->bridge; struct drm_connector *connector; @@ -863,7 +863,7 @@ inno_hdmi_bridge_edid_read(struct drm_bridge *bridge, struct drm_connector *conn } static void inno_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); @@ -871,7 +871,7 @@ static void inno_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, } static void inno_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); diff --git a/drivers/gpu/drm/bridge/ite-it6263.c b/drivers/gpu/drm/bridge/ite-it6263.c index 766bd3a6dad8..c7d588be12cb 100644 --- a/drivers/gpu/drm/bridge/ite-it6263.c +++ b/drivers/gpu/drm/bridge/ite-it6263.c @@ -580,7 +580,7 @@ static int it6263_read_edid(void *data, u8 *buf, unsigned int block, size_t len) } static void it6263_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct it6263 *it = bridge_to_it6263(bridge); @@ -591,7 +591,7 @@ static void it6263_bridge_atomic_disable(struct drm_bridge *bridge, } static void it6263_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct it6263 *it = bridge_to_it6263(bridge); const struct drm_crtc_state *crtc_state; diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c index 37bb8123cf9b..6b7cb132a437 100644 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@ -3119,7 +3119,7 @@ it6505_bridge_mode_valid(struct drm_bridge *bridge, } static void it6505_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct it6505 *it6505 = bridge_to_it6505(bridge); struct device *dev = it6505->dev; @@ -3173,7 +3173,7 @@ static void it6505_bridge_atomic_enable(struct drm_bridge *bridge, } static void it6505_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct it6505 *it6505 = bridge_to_it6505(bridge); struct device *dev = it6505->dev; @@ -3187,7 +3187,7 @@ static void it6505_bridge_atomic_disable(struct drm_bridge *bridge, } static void it6505_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct it6505 *it6505 = bridge_to_it6505(bridge); struct device *dev = it6505->dev; @@ -3198,7 +3198,7 @@ static void it6505_bridge_atomic_pre_enable(struct drm_bridge *bridge, } static void it6505_bridge_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct it6505 *it6505 = bridge_to_it6505(bridge); struct device *dev = it6505->dev; diff --git a/drivers/gpu/drm/bridge/ite-it66121.c b/drivers/gpu/drm/bridge/ite-it66121.c index 9246e9c15a6e..19a027d75b61 100644 --- a/drivers/gpu/drm/bridge/ite-it66121.c +++ b/drivers/gpu/drm/bridge/ite-it66121.c @@ -722,7 +722,7 @@ static u32 *it66121_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, } static void it66121_bridge_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); @@ -732,7 +732,7 @@ static void it66121_bridge_enable(struct drm_bridge *bridge, } static void it66121_bridge_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); diff --git a/drivers/gpu/drm/bridge/lontium-lt9211.c b/drivers/gpu/drm/bridge/lontium-lt9211.c index 03fc8fd10f20..870175a84839 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9211.c +++ b/drivers/gpu/drm/bridge/lontium-lt9211.c @@ -455,7 +455,7 @@ static int lt9211_configure_tx(struct lt9211 *ctx, bool jeida, } static void lt9211_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lt9211 *ctx = bridge_to_lt9211(bridge); const struct drm_bridge_state *bridge_state; @@ -552,7 +552,7 @@ static void lt9211_atomic_enable(struct drm_bridge *bridge, } static void lt9211_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lt9211 *ctx = bridge_to_lt9211(bridge); int ret; diff --git a/drivers/gpu/drm/bridge/lontium-lt9611.c b/drivers/gpu/drm/bridge/lontium-lt9611.c index 4517aee83332..0f49b13193b9 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9611.c +++ b/drivers/gpu/drm/bridge/lontium-lt9611.c @@ -657,7 +657,7 @@ lt9611_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len) /* bridge funcs */ static void lt9611_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lt9611 *lt9611 = bridge_to_lt9611(bridge); struct drm_connector *connector; @@ -704,7 +704,7 @@ static void lt9611_bridge_atomic_enable(struct drm_bridge *bridge, } static void lt9611_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lt9611 *lt9611 = bridge_to_lt9611(bridge); int ret; @@ -782,7 +782,7 @@ static enum drm_mode_status lt9611_bridge_mode_valid(struct drm_bridge *bridge, } static void lt9611_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lt9611 *lt9611 = bridge_to_lt9611(bridge); static const struct reg_sequence reg_cfg[] = { @@ -802,7 +802,7 @@ static void lt9611_bridge_atomic_pre_enable(struct drm_bridge *bridge, } static void lt9611_bridge_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lt9611 *lt9611 = bridge_to_lt9611(bridge); diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/bridge/microchip-lvds.c index 12fc442f9867..5fb8633f43c5 100644 --- a/drivers/gpu/drm/bridge/microchip-lvds.c +++ b/drivers/gpu/drm/bridge/microchip-lvds.c @@ -129,7 +129,7 @@ static int mchp_lvds_attach(struct drm_bridge *bridge, } static void mchp_lvds_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mchp_lvds *lvds = bridge_to_lvds(bridge); struct drm_connector *connector; @@ -158,7 +158,7 @@ static void mchp_lvds_atomic_enable(struct drm_bridge *bridge, } static void mchp_lvds_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mchp_lvds *lvds = bridge_to_lvds(bridge); diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c index 2f7429b24fc2..3c9ae93c4f67 100644 --- a/drivers/gpu/drm/bridge/nwl-dsi.c +++ b/drivers/gpu/drm/bridge/nwl-dsi.c @@ -737,7 +737,7 @@ static int nwl_dsi_disable(struct nwl_dsi *dsi) } static void nwl_dsi_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct nwl_dsi *dsi = bridge_to_dsi(bridge); int ret; @@ -898,7 +898,7 @@ nwl_dsi_bridge_mode_set(struct drm_bridge *bridge, } static void nwl_dsi_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct nwl_dsi *dsi = bridge_to_dsi(bridge); int ret; diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c index 184a8b7049a7..4978ec98a082 100644 --- a/drivers/gpu/drm/bridge/panel.c +++ b/drivers/gpu/drm/bridge/panel.c @@ -111,7 +111,7 @@ static void panel_bridge_detach(struct drm_bridge *bridge) } static void panel_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *atomic_state) + struct drm_atomic_commit *atomic_state) { struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge); struct drm_encoder *encoder = bridge->encoder; @@ -130,7 +130,7 @@ static void panel_bridge_atomic_pre_enable(struct drm_bridge *bridge, } static void panel_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *atomic_state) + struct drm_atomic_commit *atomic_state) { struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge); struct drm_encoder *encoder = bridge->encoder; @@ -149,7 +149,7 @@ static void panel_bridge_atomic_enable(struct drm_bridge *bridge, } static void panel_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *atomic_state) + struct drm_atomic_commit *atomic_state) { struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge); struct drm_encoder *encoder = bridge->encoder; @@ -168,7 +168,7 @@ static void panel_bridge_atomic_disable(struct drm_bridge *bridge, } static void panel_bridge_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *atomic_state) + struct drm_atomic_commit *atomic_state) { struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge); struct drm_encoder *encoder = bridge->encoder; diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c index 825777a5758f..b93514023baa 100644 --- a/drivers/gpu/drm/bridge/parade-ps8640.c +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -437,7 +437,7 @@ static const struct dev_pm_ops ps8640_pm_ops = { }; static void ps8640_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; @@ -472,7 +472,7 @@ static void ps8640_atomic_pre_enable(struct drm_bridge *bridge, } static void ps8640_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index c3eb437ef1b0..9ee0515074c7 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -1640,7 +1640,7 @@ static int samsung_dsim_init(struct samsung_dsim *dsi) } static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct samsung_dsim *dsi = bridge_to_dsi(bridge); int ret; @@ -1668,7 +1668,7 @@ static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge, } static void samsung_dsim_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct samsung_dsim *dsi = bridge_to_dsi(bridge); @@ -1679,7 +1679,7 @@ static void samsung_dsim_atomic_enable(struct drm_bridge *bridge, } static void samsung_dsim_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct samsung_dsim *dsi = bridge_to_dsi(bridge); @@ -1691,7 +1691,7 @@ static void samsung_dsim_atomic_disable(struct drm_bridge *bridge, } static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct samsung_dsim *dsi = bridge_to_dsi(bridge); diff --git a/drivers/gpu/drm/bridge/sii902x.c b/drivers/gpu/drm/bridge/sii902x.c index 12497f5ce4ff..ea543be4ae3e 100644 --- a/drivers/gpu/drm/bridge/sii902x.c +++ b/drivers/gpu/drm/bridge/sii902x.c @@ -321,7 +321,7 @@ static const struct drm_connector_helper_funcs sii902x_connector_helper_funcs = }; static void sii902x_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sii902x *sii902x = bridge_to_sii902x(bridge); @@ -335,7 +335,7 @@ static void sii902x_bridge_atomic_disable(struct drm_bridge *bridge, } static void sii902x_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sii902x *sii902x = bridge_to_sii902x(bridge); struct drm_connector *connector; diff --git a/drivers/gpu/drm/bridge/ssd2825.c b/drivers/gpu/drm/bridge/ssd2825.c index f2fdbf7c117d..91f1510fc2d4 100644 --- a/drivers/gpu/drm/bridge/ssd2825.c +++ b/drivers/gpu/drm/bridge/ssd2825.c @@ -482,7 +482,7 @@ static int ssd2825_setup_pll(struct ssd2825_priv *priv, } static void ssd2825_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ssd2825_priv *priv = bridge_to_ssd2825(bridge); struct mipi_dsi_device *dsi_dev = priv->output.dev; @@ -585,7 +585,7 @@ static void ssd2825_bridge_atomic_pre_enable(struct drm_bridge *bridge, } static void ssd2825_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ssd2825_priv *priv = bridge_to_ssd2825(bridge); struct mipi_dsi_device *dsi_dev = priv->output.dev; @@ -607,7 +607,7 @@ static void ssd2825_bridge_atomic_enable(struct drm_bridge *bridge, } static void ssd2825_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ssd2825_priv *priv = bridge_to_ssd2825(bridge); int ret; diff --git a/drivers/gpu/drm/bridge/synopsys/dw-dp.c b/drivers/gpu/drm/bridge/synopsys/dw-dp.c index 3f4530c117c7..21541be094c4 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-dp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-dp.c @@ -1644,7 +1644,7 @@ static int dw_dp_link_enable(struct dw_dp *dp) } static void dw_dp_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dw_dp *dp = bridge_to_dp(bridge); struct drm_connector *connector; @@ -1697,7 +1697,7 @@ static void dw_dp_reset(struct dw_dp *dp) } static void dw_dp_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dw_dp *dp = bridge_to_dp(bridge); diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c index d649a1cf07f5..0dbb12743609 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -750,7 +750,7 @@ static struct i2c_adapter *dw_hdmi_qp_i2c_adapter(struct dw_hdmi_qp *hdmi) } static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dw_hdmi_qp *hdmi = bridge->driver_private; struct drm_connector_state *conn_state; @@ -785,7 +785,7 @@ static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge, } static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dw_hdmi_qp *hdmi = bridge->driver_private; diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index f4a1ebb79716..41b3a9cfa2f5 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -2531,7 +2531,7 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) } static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *old_state = drm_atomic_get_old_connector_state(state, connector); @@ -2979,7 +2979,7 @@ static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, } static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dw_hdmi *hdmi = bridge->driver_private; @@ -2993,7 +2993,7 @@ static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, } static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dw_hdmi *hdmi = bridge->driver_private; struct drm_connector *connector; diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index ef7be20a59cd..af176e136f85 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -939,7 +939,7 @@ static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) } static void dw_mipi_dsi_bridge_post_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; @@ -1027,7 +1027,7 @@ static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi, } static void dw_mipi_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); @@ -1048,7 +1048,7 @@ static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, } static void dw_mipi_dsi_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c index a4bfd3ad166d..b2a022d266d9 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c @@ -750,7 +750,7 @@ static int dw_mipi_dsi2_bridge_atomic_check(struct drm_bridge *bridge, } static void dw_mipi_dsi2_bridge_post_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dw_mipi_dsi2 *dsi2 = bridge_to_dsi2(bridge); const struct dw_mipi_dsi2_phy_ops *phy_ops = dsi2->plat_data->phy_ops; @@ -826,7 +826,7 @@ static void dw_mipi_dsi2_mode_set(struct dw_mipi_dsi2 *dsi2, } static void dw_mipi_dsi2_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dw_mipi_dsi2 *dsi2 = bridge_to_dsi2(bridge); @@ -845,7 +845,7 @@ static void dw_mipi_dsi2_bridge_mode_set(struct drm_bridge *bridge, } static void dw_mipi_dsi2_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dw_mipi_dsi2 *dsi2 = bridge_to_dsi2(bridge); diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc358762.c index 98df3e667d4a..3d75d9cfa45e 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c @@ -150,7 +150,7 @@ static int tc358762_init(struct tc358762 *ctx) } static void tc358762_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tc358762 *ctx = bridge_to_tc358762(bridge); int ret; @@ -173,7 +173,7 @@ static void tc358762_post_disable(struct drm_bridge *bridge, } static void tc358762_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tc358762 *ctx = bridge_to_tc358762(bridge); int ret; @@ -191,7 +191,7 @@ static void tc358762_pre_enable(struct drm_bridge *bridge, } static void tc358762_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tc358762 *ctx = bridge_to_tc358762(bridge); int ret; diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 4097fef4b86b..7188935fdb82 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -1557,7 +1557,7 @@ static int tc_edp_stream_disable(struct tc_data *tc) } static void tc_dpi_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tc_data *tc = bridge_to_tc(bridge); @@ -1572,7 +1572,7 @@ static void tc_dpi_bridge_atomic_enable(struct drm_bridge *bridge, } static void tc_dpi_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tc_data *tc = bridge_to_tc(bridge); int ret; @@ -1583,7 +1583,7 @@ static void tc_dpi_bridge_atomic_disable(struct drm_bridge *bridge, } static void tc_edp_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tc_data *tc = bridge_to_tc(bridge); int ret; @@ -1609,7 +1609,7 @@ static void tc_edp_bridge_atomic_enable(struct drm_bridge *bridge, } static void tc_edp_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tc_data *tc = bridge_to_tc(bridge); int ret; diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index e0b5a4b5abbe..0f2820b37302 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -672,7 +672,7 @@ tc358768_bridge_mode_valid(struct drm_bridge *bridge, } static void tc358768_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tc358768_priv *priv = bridge_to_tc358768(bridge); int ret; @@ -695,7 +695,7 @@ static void tc358768_bridge_atomic_disable(struct drm_bridge *bridge, } static void tc358768_bridge_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tc358768_priv *priv = bridge_to_tc358768(bridge); @@ -776,7 +776,7 @@ static u32 tc358768_dsi_bytes_to_ns(struct tc358768_priv *priv, u32 val) } static void tc358768_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tc358768_priv *priv = bridge_to_tc358768(bridge); struct mipi_dsi_device *dsi_dev = priv->output.dev; @@ -1195,7 +1195,7 @@ static void tc358768_config_video_format(struct tc358768_priv *priv) } static void tc358768_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tc358768_priv *priv = bridge_to_tc358768(bridge); int ret; diff --git a/drivers/gpu/drm/bridge/tc358775.c b/drivers/gpu/drm/bridge/tc358775.c index 366b12db0e7c..e067b671cece 100644 --- a/drivers/gpu/drm/bridge/tc358775.c +++ b/drivers/gpu/drm/bridge/tc358775.c @@ -287,7 +287,7 @@ static inline struct tc_data *bridge_to_tc(struct drm_bridge *b) } static void tc_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tc_data *tc = bridge_to_tc(bridge); struct device *dev = &tc->dsi->dev; @@ -311,7 +311,7 @@ static void tc_bridge_atomic_pre_enable(struct drm_bridge *bridge, } static void tc_bridge_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tc_data *tc = bridge_to_tc(bridge); struct device *dev = &tc->dsi->dev; @@ -371,7 +371,7 @@ static void d2l_write(struct i2c_client *i2c, u16 addr, u32 val) } static void tc_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tc_data *tc = bridge_to_tc(bridge); u32 hback_porch, hsync_len, hfront_porch, hactive, htime1, htime2; diff --git a/drivers/gpu/drm/bridge/ti-dlpc3433.c b/drivers/gpu/drm/bridge/ti-dlpc3433.c index b07f7c9d5890..9c35eade0a78 100644 --- a/drivers/gpu/drm/bridge/ti-dlpc3433.c +++ b/drivers/gpu/drm/bridge/ti-dlpc3433.c @@ -105,7 +105,7 @@ static const struct regmap_config dlpc_regmap_config = { }; static void dlpc_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dlpc *dlpc = bridge_to_dlpc(bridge); struct device *dev = dlpc->dev; @@ -170,7 +170,7 @@ static void dlpc_atomic_enable(struct drm_bridge *bridge, } static void dlpc_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dlpc *dlpc = bridge_to_dlpc(bridge); int ret; @@ -193,7 +193,7 @@ static void dlpc_atomic_pre_enable(struct drm_bridge *bridge, } static void dlpc_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dlpc *dlpc = bridge_to_dlpc(bridge); diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c index 2b6f6a54edb7..42b451432bbb 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -518,7 +518,7 @@ static void sn65dsi83_release_resources(void *data) } static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); const unsigned int dual_factor = ctx->lvds_dual_link ? 2 : 1; @@ -706,7 +706,7 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, } static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); unsigned int pval; @@ -738,7 +738,7 @@ static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, } static void sn65dsi83_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); int idx; diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 1336ffab103f..0884ec459cc5 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -278,7 +278,7 @@ static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata, static struct drm_display_mode * get_new_adjusted_display_mode(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector *connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); @@ -291,7 +291,7 @@ get_new_adjusted_display_mode(struct drm_bridge *bridge, } static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { u32 bit_rate_khz, clk_freq_khz; struct drm_display_mode *mode = @@ -323,7 +323,7 @@ static const u32 ti_sn_bridge_dsiclk_lut[] = { }; static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { int i; u32 refclk_rate; @@ -361,7 +361,7 @@ static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata, } static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { mutex_lock(&pdata->comms_mutex); @@ -824,7 +824,7 @@ ti_sn_bridge_mode_valid(struct drm_bridge *bridge, } static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); @@ -833,7 +833,7 @@ static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge, } static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { unsigned int bit_rate_mhz, clk_freq_mhz; unsigned int val; @@ -869,7 +869,7 @@ static const unsigned int ti_sn_bridge_dp_rate_lut[] = { }; static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, unsigned int bpp) { unsigned int bit_rate_khz, dp_rate_mhz; @@ -975,7 +975,7 @@ static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata) } static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_display_mode *mode = get_new_adjusted_display_mode(&pdata->bridge, state); @@ -1088,7 +1088,7 @@ static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx, } static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); struct drm_connector *connector; @@ -1179,7 +1179,7 @@ static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge, } static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); @@ -1193,7 +1193,7 @@ static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge, } static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); diff --git a/drivers/gpu/drm/bridge/ti-tdp158.c b/drivers/gpu/drm/bridge/ti-tdp158.c index 27053d020df7..3a19967f213f 100644 --- a/drivers/gpu/drm/bridge/ti-tdp158.c +++ b/drivers/gpu/drm/bridge/ti-tdp158.c @@ -19,7 +19,7 @@ struct tdp158 { }; static void tdp158_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { int err; struct tdp158 *tdp158 = bridge->driver_private; @@ -36,7 +36,7 @@ static void tdp158_enable(struct drm_bridge *bridge, } static void tdp158_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tdp158 *tdp158 = bridge->driver_private; diff --git a/drivers/gpu/drm/ci/xfails/vkms-none-skips.txt b/drivers/gpu/drm/ci/xfails/vkms-none-skips.txt index 716d2d4e452d..afcc09d1683d 100644 --- a/drivers/gpu/drm/ci/xfails/vkms-none-skips.txt +++ b/drivers/gpu/drm/ci/xfails/vkms-none-skips.txt @@ -288,8 +288,8 @@ kms_cursor_edge_walk@128x128-left-edge # ? __pfx_drm_property_free_blob+0x10/0x10 # ? vkms_atomic_crtc_destroy_state+0x31/0x40 [vkms] # ? vkms_atomic_crtc_destroy_state+0x10/0x40 [vkms] -# drm_atomic_state_default_clear+0x137/0x2f0 -# __drm_atomic_state_free+0x6c/0xb0 +# drm_atomic_commit_default_clear+0x137/0x2f0 +# __drm_atomic_commit_free+0x6c/0xb0 # drm_atomic_helper_update_plane+0x100/0x150 # drm_mode_cursor_universal+0x10e/0x270 # drm_mode_cursor_common+0x115/0x240 @@ -394,8 +394,8 @@ kms_cursor_edge_walk@128x128-left-edge # ? __pfx_drm_property_free_blob+0x10/0x10 # ? vkms_atomic_crtc_destroy_state+0x31/0x40 [vkms] # ? vkms_atomic_crtc_destroy_state+0x10/0x40 [vkms] -# drm_atomic_state_default_clear+0x137/0x2f0 -# __drm_atomic_state_free+0x6c/0xb0 +# drm_atomic_commit_default_clear+0x137/0x2f0 +# __drm_atomic_commit_free+0x6c/0xb0 # drm_atomic_helper_update_plane+0x100/0x150 # drm_mode_cursor_universal+0x10e/0x270 # drm_mode_cursor_common+0x115/0x240 @@ -500,8 +500,8 @@ kms_cursor_edge_walk@128x128-left-edge # ? __pfx_drm_property_free_blob+0x10/0x10 # ? vkms_atomic_crtc_destroy_state+0x31/0x40 [vkms] # ? vkms_atomic_crtc_destroy_state+0x10/0x40 [vkms] -# drm_atomic_state_default_clear+0x137/0x2f0 -# __drm_atomic_state_free+0x6c/0xb0 +# drm_atomic_commit_default_clear+0x137/0x2f0 +# __drm_atomic_commit_free+0x6c/0xb0 # drm_atomic_helper_update_plane+0x100/0x150 # drm_mode_cursor_universal+0x10e/0x270 # drm_mode_cursor_common+0x115/0x240 @@ -606,8 +606,8 @@ kms_cursor_edge_walk@128x128-left-edge # ? __pfx_drm_property_free_blob+0x10/0x10 # ? vkms_atomic_crtc_destroy_state+0x31/0x40 [vkms] # ? vkms_atomic_crtc_destroy_state+0x10/0x40 [vkms] -# drm_atomic_state_default_clear+0x137/0x2f0 -# __drm_atomic_state_free+0x6c/0xb0 +# drm_atomic_commit_default_clear+0x137/0x2f0 +# __drm_atomic_commit_free+0x6c/0xb0 # drm_atomic_helper_update_plane+0x100/0x150 # drm_mode_cursor_universal+0x10e/0x270 # drm_mode_cursor_common+0x115/0x240 @@ -712,8 +712,8 @@ kms_cursor_edge_walk@128x128-left-edge # ? __pfx_drm_property_free_blob+0x10/0x10 # ? vkms_atomic_crtc_destroy_state+0x31/0x40 [vkms] # ? vkms_atomic_crtc_destroy_state+0x10/0x40 [vkms] -# drm_atomic_state_default_clear+0x137/0x2f0 -# __drm_atomic_state_free+0x6c/0xb0 +# drm_atomic_commit_default_clear+0x137/0x2f0 +# __drm_atomic_commit_free+0x6c/0xb0 # drm_atomic_helper_update_plane+0x100/0x150 # drm_mode_cursor_universal+0x10e/0x270 # drm_mode_cursor_common+0x115/0x240 diff --git a/drivers/gpu/drm/display/drm_bridge_connector.c b/drivers/gpu/drm/display/drm_bridge_connector.c index d85ceb80c137..649969fca141 100644 --- a/drivers/gpu/drm/display/drm_bridge_connector.c +++ b/drivers/gpu/drm/display/drm_bridge_connector.c @@ -371,7 +371,7 @@ drm_bridge_connector_mode_valid(struct drm_connector *connector, } static int drm_bridge_connector_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_bridge_connector *bridge_connector = to_drm_bridge_connector(connector); diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index 8757972e8e24..35dc4f24ae53 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -4433,7 +4433,7 @@ EXPORT_SYMBOL(drm_dp_mst_get_edid); * Total slots in the atomic state assigned for this port, or a negative error * code if the port no longer exists */ -int drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, +int drm_dp_atomic_find_time_slots(struct drm_atomic_commit *state, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int pbn) { @@ -4523,7 +4523,7 @@ EXPORT_SYMBOL(drm_dp_atomic_find_time_slots); * Returns: * 0 on success, negative error code otherwise */ -int drm_dp_atomic_release_time_slots(struct drm_atomic_state *state, +int drm_dp_atomic_release_time_slots(struct drm_atomic_commit *state, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port) { @@ -4591,7 +4591,7 @@ EXPORT_SYMBOL(drm_dp_atomic_release_time_slots); * Returns: * 0 if all CRTC commits were retrieved successfully, negative error code otherwise */ -int drm_dp_mst_atomic_setup_commit(struct drm_atomic_state *state) +int drm_dp_mst_atomic_setup_commit(struct drm_atomic_commit *state) { struct drm_dp_mst_topology_mgr *mgr; struct drm_dp_mst_topology_state *mst_state; @@ -4641,7 +4641,7 @@ EXPORT_SYMBOL(drm_dp_mst_atomic_setup_commit); * All MST drivers must call this function after calling drm_atomic_helper_wait_for_dependencies(), * or whatever their equivalent of that is. */ -void drm_dp_mst_atomic_wait_for_dependencies(struct drm_atomic_state *state) +void drm_dp_mst_atomic_wait_for_dependencies(struct drm_atomic_commit *state) { struct drm_dp_mst_topology_state *old_mst_state, *new_mst_state; struct drm_dp_mst_topology_mgr *mgr; @@ -4698,7 +4698,7 @@ EXPORT_SYMBOL(drm_dp_mst_atomic_wait_for_dependencies); int drm_dp_mst_root_conn_atomic_check(struct drm_connector_state *new_conn_state, struct drm_dp_mst_topology_mgr *mgr) { - struct drm_atomic_state *state = new_conn_state->state; + struct drm_atomic_commit *state = new_conn_state->state; struct drm_connector_state *old_conn_state = drm_atomic_get_old_connector_state(state, new_conn_state->connector); struct drm_crtc_state *crtc_state; @@ -5436,7 +5436,7 @@ drm_dp_mst_atomic_check_payload_alloc_limits(struct drm_dp_mst_topology_mgr *mgr * See also: * drm_dp_mst_atomic_enable_dsc() */ -int drm_dp_mst_add_affected_dsc_crtcs(struct drm_atomic_state *state, struct drm_dp_mst_topology_mgr *mgr) +int drm_dp_mst_add_affected_dsc_crtcs(struct drm_atomic_commit *state, struct drm_dp_mst_topology_mgr *mgr) { struct drm_dp_mst_topology_state *mst_state; struct drm_dp_mst_atomic_payload *pos; @@ -5486,7 +5486,7 @@ EXPORT_SYMBOL(drm_dp_mst_add_affected_dsc_crtcs); /** * drm_dp_mst_atomic_enable_dsc - Set DSC Enable Flag to On/Off - * @state: Pointer to the new drm_atomic_state + * @state: Pointer to the new drm_atomic_commit * @port: Pointer to the affected MST Port * @pbn: Newly recalculated bw required for link with DSC enabled * @enable: Boolean flag to enable or disable DSC on the port @@ -5497,7 +5497,7 @@ EXPORT_SYMBOL(drm_dp_mst_add_affected_dsc_crtcs); * ports have DSC enabled * */ -int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state *state, +int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_commit *state, struct drm_dp_mst_port *port, int pbn, bool enable) { @@ -5576,7 +5576,7 @@ EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc); * - %-EINVAL, if the new state is invalid, because the root port has * too many payloads. */ -int drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state, +int drm_dp_mst_atomic_check_mgr(struct drm_atomic_commit *state, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_topology_state *mst_state, struct drm_dp_mst_port **failing_port) @@ -5623,7 +5623,7 @@ EXPORT_SYMBOL(drm_dp_mst_atomic_check_mgr); * Returns: * 0 if the new state is valid, negative error code otherwise. */ -int drm_dp_mst_atomic_check(struct drm_atomic_state *state) +int drm_dp_mst_atomic_check(struct drm_atomic_commit *state) { struct drm_dp_mst_topology_mgr *mgr; struct drm_dp_mst_topology_state *mst_state; @@ -5660,7 +5660,7 @@ EXPORT_SYMBOL(drm_dp_mst_topology_state_funcs); * RETURNS: * The MST topology state or error pointer. */ -struct drm_dp_mst_topology_state *drm_atomic_get_mst_topology_state(struct drm_atomic_state *state, +struct drm_dp_mst_topology_state *drm_atomic_get_mst_topology_state(struct drm_atomic_commit *state, struct drm_dp_mst_topology_mgr *mgr) { return to_dp_mst_topology_state(drm_atomic_get_private_obj_state(state, &mgr->base)); @@ -5681,7 +5681,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); * in the global atomic state */ struct drm_dp_mst_topology_state * -drm_atomic_get_old_mst_topology_state(struct drm_atomic_state *state, +drm_atomic_get_old_mst_topology_state(struct drm_atomic_commit *state, struct drm_dp_mst_topology_mgr *mgr) { struct drm_private_state *old_priv_state = @@ -5705,7 +5705,7 @@ EXPORT_SYMBOL(drm_atomic_get_old_mst_topology_state); * in the global atomic state */ struct drm_dp_mst_topology_state * -drm_atomic_get_new_mst_topology_state(struct drm_atomic_state *state, +drm_atomic_get_new_mst_topology_state(struct drm_atomic_commit *state, struct drm_dp_mst_topology_mgr *mgr) { struct drm_private_state *new_priv_state = diff --git a/drivers/gpu/drm/display/drm_dp_tunnel.c b/drivers/gpu/drm/display/drm_dp_tunnel.c index 6519b4244728..76c6bc84a806 100644 --- a/drivers/gpu/drm/display/drm_dp_tunnel.c +++ b/drivers/gpu/drm/display/drm_dp_tunnel.c @@ -149,6 +149,7 @@ struct drm_dp_tunnel { bool bw_alloc_enabled:1; bool has_io_error:1; bool destroyed:1; + bool pr_optimization_support:1; }; struct drm_dp_tunnel_group_state; @@ -508,6 +509,8 @@ create_tunnel(struct drm_dp_tunnel_mgr *mgr, tunnel->bw_alloc_supported = tunnel_reg_bw_alloc_supported(regs); tunnel->bw_alloc_enabled = tunnel_reg_bw_alloc_enabled(regs); + tunnel->pr_optimization_support = tunnel_reg(regs, DP_TUNNELING_CAPABILITIES) & + DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT; if (!add_tunnel_to_group(mgr, drv_group_id, tunnel)) { kfree(tunnel); @@ -1036,6 +1039,20 @@ bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel) } EXPORT_SYMBOL(drm_dp_tunnel_bw_alloc_is_enabled); +/** + * drm_dp_tunnel_pr_optimization_supported - Query the PR BW optimization support + * @tunnel: Tunnel object + * + * Query if the PR BW optimization is supported for @tunnel. + * + * Returns %true if the PR BW optimiation is supported for @tunnel. + */ +bool drm_dp_tunnel_pr_optimization_supported(const struct drm_dp_tunnel *tunnel) +{ + return tunnel && tunnel->pr_optimization_support; +} +EXPORT_SYMBOL(drm_dp_tunnel_pr_optimization_supported); + static int clear_bw_req_state(struct drm_dp_aux *aux) { u8 bw_req_mask = DP_BW_REQUEST_SUCCEEDED | DP_BW_REQUEST_FAILED; @@ -1369,7 +1386,7 @@ int drm_dp_tunnel_available_bw(const struct drm_dp_tunnel *tunnel) EXPORT_SYMBOL(drm_dp_tunnel_available_bw); static struct drm_dp_tunnel_group_state * -drm_dp_tunnel_atomic_get_group_state(struct drm_atomic_state *state, +drm_dp_tunnel_atomic_get_group_state(struct drm_atomic_commit *state, const struct drm_dp_tunnel *tunnel) { return (struct drm_dp_tunnel_group_state *) @@ -1528,7 +1545,7 @@ static const struct drm_private_state_funcs tunnel_group_funcs = { * Return the state or an ERR_PTR() error on failure. */ struct drm_dp_tunnel_state * -drm_dp_tunnel_atomic_get_state(struct drm_atomic_state *state, +drm_dp_tunnel_atomic_get_state(struct drm_atomic_commit *state, struct drm_dp_tunnel *tunnel) { struct drm_dp_tunnel_group_state *group_state; @@ -1556,7 +1573,7 @@ EXPORT_SYMBOL(drm_dp_tunnel_atomic_get_state); * Return the old state or NULL if the tunnel's atomic state is not in @state. */ struct drm_dp_tunnel_state * -drm_dp_tunnel_atomic_get_old_state(struct drm_atomic_state *state, +drm_dp_tunnel_atomic_get_old_state(struct drm_atomic_commit *state, const struct drm_dp_tunnel *tunnel) { struct drm_dp_tunnel_group_state *old_group_state; @@ -1580,7 +1597,7 @@ EXPORT_SYMBOL(drm_dp_tunnel_atomic_get_old_state); * Return the new state or NULL if the tunnel's atomic state is not in @state. */ struct drm_dp_tunnel_state * -drm_dp_tunnel_atomic_get_new_state(struct drm_atomic_state *state, +drm_dp_tunnel_atomic_get_new_state(struct drm_atomic_commit *state, const struct drm_dp_tunnel *tunnel) { struct drm_dp_tunnel_group_state *new_group_state; @@ -1706,7 +1723,7 @@ static int clear_stream_bw(struct drm_dp_tunnel_state *tunnel_state, * * Returns 0 in case of success, a negative error code otherwise. */ -int drm_dp_tunnel_atomic_set_stream_bw(struct drm_atomic_state *state, +int drm_dp_tunnel_atomic_set_stream_bw(struct drm_atomic_commit *state, struct drm_dp_tunnel *tunnel, u8 stream_id, int bw) { @@ -1783,7 +1800,7 @@ EXPORT_SYMBOL(drm_dp_tunnel_atomic_get_required_bw); * Return 0 in case of success - with the stream IDs in @stream_mask - or a * negative error code in case of failure. */ -int drm_dp_tunnel_atomic_get_group_streams_in_state(struct drm_atomic_state *state, +int drm_dp_tunnel_atomic_get_group_streams_in_state(struct drm_atomic_commit *state, const struct drm_dp_tunnel *tunnel, u32 *stream_mask) { @@ -1861,7 +1878,7 @@ drm_dp_tunnel_atomic_check_group_bw(struct drm_dp_tunnel_group_state *new_group_ * check failed - with @failed_stream_mask containing the streams failing the * check - or a negative error code otherwise. */ -int drm_dp_tunnel_atomic_check_stream_bws(struct drm_atomic_state *state, +int drm_dp_tunnel_atomic_check_stream_bws(struct drm_atomic_commit *state, u32 *failed_stream_mask) { struct drm_dp_tunnel_group_state *new_group_state; diff --git a/drivers/gpu/drm/display/drm_hdmi_state_helper.c b/drivers/gpu/drm/display/drm_hdmi_state_helper.c index 9f3b696aceeb..4867edbf2622 100644 --- a/drivers/gpu/drm/display/drm_hdmi_state_helper.c +++ b/drivers/gpu/drm/display/drm_hdmi_state_helper.c @@ -348,7 +348,7 @@ output_color_format_to_hdmi_colorspace(const struct drm_connector *connector, static const struct drm_display_mode * connector_state_get_mode(const struct drm_connector_state *conn_state) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_crtc_state *crtc_state; struct drm_crtc *crtc; @@ -858,7 +858,7 @@ hdmi_generate_infoframes(const struct drm_connector *connector, * Zero on success, or an errno code otherwise. */ int drm_atomic_helper_connector_hdmi_check(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *old_conn_state = drm_atomic_get_old_connector_state(state, connector); @@ -1000,7 +1000,7 @@ static int write_or_clear_infoframe(struct drm_connector *connector, * Zero on success, error code on failure. */ int drm_atomic_helper_connector_hdmi_update_infoframes(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { const struct drm_connector_hdmi_funcs *funcs = connector->hdmi.funcs; struct drm_connector_state *old_conn_state = diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 54bab7e9f935..170de30c28ae 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -95,15 +95,15 @@ int drm_crtc_commit_wait(struct drm_crtc_commit *commit) EXPORT_SYMBOL(drm_crtc_commit_wait); /** - * drm_atomic_state_default_release - - * release memory initialized by drm_atomic_state_init + * drm_atomic_commit_default_release - + * release memory initialized by drm_atomic_commit_init * @state: atomic state * - * Free all the memory allocated by drm_atomic_state_init. + * Free all the memory allocated by drm_atomic_commit_init. * This should only be used by drivers which are still subclassing - * &drm_atomic_state and haven't switched to &drm_private_state yet. + * &drm_atomic_commit and haven't switched to &drm_private_state yet. */ -void drm_atomic_state_default_release(struct drm_atomic_state *state) +void drm_atomic_commit_default_release(struct drm_atomic_commit *state) { kfree(state->connectors); kfree(state->crtcs); @@ -111,19 +111,19 @@ void drm_atomic_state_default_release(struct drm_atomic_state *state) kfree(state->colorops); kfree(state->private_objs); } -EXPORT_SYMBOL(drm_atomic_state_default_release); +EXPORT_SYMBOL(drm_atomic_commit_default_release); /** - * drm_atomic_state_init - init new atomic state + * drm_atomic_commit_init - init new atomic state * @dev: DRM device * @state: atomic state * * Default implementation for filling in a new atomic state. * This should only be used by drivers which are still subclassing - * &drm_atomic_state and haven't switched to &drm_private_state yet. + * &drm_atomic_commit and haven't switched to &drm_private_state yet. */ int -drm_atomic_state_init(struct drm_device *dev, struct drm_atomic_state *state) +drm_atomic_commit_init(struct drm_device *dev, struct drm_atomic_commit *state) { kref_init(&state->ref); @@ -145,7 +145,7 @@ drm_atomic_state_init(struct drm_device *dev, struct drm_atomic_state *state) goto fail; /* - * Because drm_atomic_state can be committed asynchronously we need our + * Because drm_atomic_commit can be committed asynchronously we need our * own reference and cannot rely on the on implied by drm_file in the * ioctl call. */ @@ -156,29 +156,29 @@ drm_atomic_state_init(struct drm_device *dev, struct drm_atomic_state *state) return 0; fail: - drm_atomic_state_default_release(state); + drm_atomic_commit_default_release(state); return -ENOMEM; } -EXPORT_SYMBOL(drm_atomic_state_init); +EXPORT_SYMBOL(drm_atomic_commit_init); /** - * drm_atomic_state_alloc - allocate atomic state + * drm_atomic_commit_alloc - allocate atomic state * @dev: DRM device * * This allocates an empty atomic state to track updates. */ -struct drm_atomic_state * -drm_atomic_state_alloc(struct drm_device *dev) +struct drm_atomic_commit * +drm_atomic_commit_alloc(struct drm_device *dev) { struct drm_mode_config *config = &dev->mode_config; if (!config->funcs->atomic_state_alloc) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; state = kzalloc_obj(*state); if (!state) return NULL; - if (drm_atomic_state_init(dev, state) < 0) { + if (drm_atomic_commit_init(dev, state) < 0) { kfree(state); return NULL; } @@ -187,17 +187,17 @@ drm_atomic_state_alloc(struct drm_device *dev) return config->funcs->atomic_state_alloc(dev); } -EXPORT_SYMBOL(drm_atomic_state_alloc); +EXPORT_SYMBOL(drm_atomic_commit_alloc); /** - * drm_atomic_state_default_clear - clear base atomic state + * drm_atomic_commit_default_clear - clear base atomic state * @state: atomic state * * Default implementation for clearing atomic state. * This should only be used by drivers which are still subclassing - * &drm_atomic_state and haven't switched to &drm_private_state yet. + * &drm_atomic_commit and haven't switched to &drm_private_state yet. */ -void drm_atomic_state_default_clear(struct drm_atomic_state *state) +void drm_atomic_commit_default_clear(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; struct drm_mode_config *config = &dev->mode_config; @@ -287,10 +287,10 @@ void drm_atomic_state_default_clear(struct drm_atomic_state *state) state->fake_commit = NULL; } } -EXPORT_SYMBOL(drm_atomic_state_default_clear); +EXPORT_SYMBOL(drm_atomic_commit_default_clear); /** - * drm_atomic_state_clear - clear state object + * drm_atomic_commit_clear - clear state object * @state: atomic state * * When the w/w mutex algorithm detects a deadlock we need to back off and drop @@ -303,7 +303,7 @@ EXPORT_SYMBOL(drm_atomic_state_default_clear); * Hence we must clear all cached state and completely start over, using this * function. */ -void drm_atomic_state_clear(struct drm_atomic_state *state) +void drm_atomic_commit_clear(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; struct drm_mode_config *config = &dev->mode_config; @@ -311,37 +311,37 @@ void drm_atomic_state_clear(struct drm_atomic_state *state) if (config->funcs->atomic_state_clear) config->funcs->atomic_state_clear(state); else - drm_atomic_state_default_clear(state); + drm_atomic_commit_default_clear(state); } -EXPORT_SYMBOL(drm_atomic_state_clear); +EXPORT_SYMBOL(drm_atomic_commit_clear); /** - * __drm_atomic_state_free - free all memory for an atomic state + * __drm_atomic_commit_free - free all memory for an atomic state * @ref: This atomic state to deallocate * * This frees all memory associated with an atomic state, including all the * per-object state for planes, CRTCs and connectors. */ -void __drm_atomic_state_free(struct kref *ref) +void __drm_atomic_commit_free(struct kref *ref) { - struct drm_atomic_state *state = container_of(ref, typeof(*state), ref); + struct drm_atomic_commit *state = container_of(ref, typeof(*state), ref); struct drm_device *dev = state->dev; struct drm_mode_config *config = &dev->mode_config; - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); drm_dbg_atomic(state->dev, "Freeing atomic state %p\n", state); if (config->funcs->atomic_state_free) { config->funcs->atomic_state_free(state); } else { - drm_atomic_state_default_release(state); + drm_atomic_commit_default_release(state); kfree(state); } drm_dev_put(dev); } -EXPORT_SYMBOL(__drm_atomic_state_free); +EXPORT_SYMBOL(__drm_atomic_commit_free); /** * drm_atomic_get_crtc_state - get CRTC state @@ -353,7 +353,7 @@ EXPORT_SYMBOL(__drm_atomic_state_free); * is consistent. * * WARNING: Drivers may only add new CRTC states to a @state if - * drm_atomic_state.allow_modeset is set, or if it's a driver-internal commit + * drm_atomic_commit.allow_modeset is set, or if it's a driver-internal commit * not created by userspace through an IOCTL call. * * Returns: @@ -362,7 +362,7 @@ EXPORT_SYMBOL(__drm_atomic_state_free); * entire atomic sequence must be restarted. All other errors are fatal. */ struct drm_crtc_state * -drm_atomic_get_crtc_state(struct drm_atomic_state *state, +drm_atomic_get_crtc_state(struct drm_atomic_commit *state, struct drm_crtc *crtc) { int ret, index = drm_crtc_index(crtc); @@ -544,7 +544,7 @@ static int drm_atomic_connector_check(struct drm_connector *connector, * entire atomic sequence must be restarted. All other errors are fatal. */ struct drm_plane_state * -drm_atomic_get_plane_state(struct drm_atomic_state *state, +drm_atomic_get_plane_state(struct drm_atomic_commit *state, struct drm_plane *plane) { int ret, index = drm_plane_index(plane); @@ -608,7 +608,7 @@ EXPORT_SYMBOL(drm_atomic_get_plane_state); * entire atomic sequence must be restarted. All other errors are fatal. */ struct drm_colorop_state * -drm_atomic_get_colorop_state(struct drm_atomic_state *state, +drm_atomic_get_colorop_state(struct drm_atomic_commit *state, struct drm_colorop *colorop) { int ret, index = drm_colorop_index(colorop); @@ -650,7 +650,7 @@ EXPORT_SYMBOL(drm_atomic_get_colorop_state); * NULL if the colorop is not part of the global atomic state. */ struct drm_colorop_state * -drm_atomic_get_old_colorop_state(struct drm_atomic_state *state, +drm_atomic_get_old_colorop_state(struct drm_atomic_commit *state, struct drm_colorop *colorop) { return state->colorops[drm_colorop_index(colorop)].old_state; @@ -666,7 +666,7 @@ EXPORT_SYMBOL(drm_atomic_get_old_colorop_state); * NULL if the colorop is not part of the global atomic state. */ struct drm_colorop_state * -drm_atomic_get_new_colorop_state(struct drm_atomic_state *state, +drm_atomic_get_new_colorop_state(struct drm_atomic_commit *state, struct drm_colorop *colorop) { return state->colorops[drm_colorop_index(colorop)].new_state; @@ -901,9 +901,9 @@ static void drm_atomic_plane_print_state(struct drm_printer *p, * directly. Sequence of the actual hardware state commit is not handled, * drivers might need to keep track of struct drm_crtc_commit within subclassed * structure of &drm_private_state as necessary, e.g. similar to - * &drm_plane_state.commit. See also &drm_atomic_state.fake_commit. + * &drm_plane_state.commit. See also &drm_atomic_commit.fake_commit. * - * All private state structures contained in a &drm_atomic_state update can be + * All private state structures contained in a &drm_atomic_commit update can be * iterated using for_each_oldnew_private_obj_in_state(), * for_each_new_private_obj_in_state() and for_each_old_private_obj_in_state(). * Drivers are recommended to wrap these for each type of driver private state @@ -911,7 +911,7 @@ static void drm_atomic_plane_print_state(struct drm_printer *p, * least if they want to iterate over all objects of a given type. * * An earlier way to handle driver private state was by subclassing struct - * &drm_atomic_state. But since that encourages non-standard ways to implement + * &drm_atomic_commit. But since that encourages non-standard ways to implement * the check/commit split atomic requires (by using e.g. "check and rollback or * commit instead" of "duplicate state, check, then either commit or release * duplicated state) it is deprecated in favour of using &drm_private_state. @@ -981,7 +981,7 @@ EXPORT_SYMBOL(drm_atomic_private_obj_fini); * Either the allocated state or the error code encoded into a pointer. */ struct drm_private_state * -drm_atomic_get_private_obj_state(struct drm_atomic_state *state, +drm_atomic_get_private_obj_state(struct drm_atomic_commit *state, struct drm_private_obj *obj) { int index, num_objs, ret; @@ -1039,7 +1039,7 @@ EXPORT_SYMBOL(drm_atomic_get_private_obj_state); * or NULL if the private_obj is not part of the global atomic state. */ struct drm_private_state * -drm_atomic_get_old_private_obj_state(const struct drm_atomic_state *state, +drm_atomic_get_old_private_obj_state(const struct drm_atomic_commit *state, struct drm_private_obj *obj) { int i; @@ -1061,7 +1061,7 @@ EXPORT_SYMBOL(drm_atomic_get_old_private_obj_state); * or NULL if the private_obj is not part of the global atomic state. */ struct drm_private_state * -drm_atomic_get_new_private_obj_state(const struct drm_atomic_state *state, +drm_atomic_get_new_private_obj_state(const struct drm_atomic_commit *state, struct drm_private_obj *obj) { int i; @@ -1096,7 +1096,7 @@ EXPORT_SYMBOL(drm_atomic_get_new_private_obj_state); * not connected. */ struct drm_connector * -drm_atomic_get_old_connector_for_encoder(const struct drm_atomic_state *state, +drm_atomic_get_old_connector_for_encoder(const struct drm_atomic_commit *state, struct drm_encoder *encoder) { struct drm_connector_state *conn_state; @@ -1133,7 +1133,7 @@ EXPORT_SYMBOL(drm_atomic_get_old_connector_for_encoder); * not connected. */ struct drm_connector * -drm_atomic_get_new_connector_for_encoder(const struct drm_atomic_state *state, +drm_atomic_get_new_connector_for_encoder(const struct drm_atomic_commit *state, struct drm_encoder *encoder) { struct drm_connector_state *conn_state; @@ -1214,7 +1214,7 @@ EXPORT_SYMBOL(drm_atomic_get_connector_for_encoder); * not connected. */ struct drm_crtc * -drm_atomic_get_old_crtc_for_encoder(struct drm_atomic_state *state, +drm_atomic_get_old_crtc_for_encoder(struct drm_atomic_commit *state, struct drm_encoder *encoder) { struct drm_connector *connector; @@ -1244,7 +1244,7 @@ EXPORT_SYMBOL(drm_atomic_get_old_crtc_for_encoder); * not connected. */ struct drm_crtc * -drm_atomic_get_new_crtc_for_encoder(struct drm_atomic_state *state, +drm_atomic_get_new_crtc_for_encoder(struct drm_atomic_commit *state, struct drm_encoder *encoder) { struct drm_connector *connector; @@ -1277,7 +1277,7 @@ EXPORT_SYMBOL(drm_atomic_get_new_crtc_for_encoder); * entire atomic sequence must be restarted. All other errors are fatal. */ struct drm_connector_state * -drm_atomic_get_connector_state(struct drm_atomic_state *state, +drm_atomic_get_connector_state(struct drm_atomic_commit *state, struct drm_connector *connector) { int ret, index; @@ -1388,7 +1388,7 @@ static void drm_atomic_connector_print_state(struct drm_printer *p, * entire atomic sequence must be restarted. */ struct drm_bridge_state * -drm_atomic_get_bridge_state(struct drm_atomic_state *state, +drm_atomic_get_bridge_state(struct drm_atomic_commit *state, struct drm_bridge *bridge) { struct drm_private_state *obj_state; @@ -1410,7 +1410,7 @@ EXPORT_SYMBOL(drm_atomic_get_bridge_state); * the bridge is not part of the global atomic state. */ struct drm_bridge_state * -drm_atomic_get_old_bridge_state(const struct drm_atomic_state *state, +drm_atomic_get_old_bridge_state(const struct drm_atomic_commit *state, struct drm_bridge *bridge) { struct drm_private_state *obj_state; @@ -1432,7 +1432,7 @@ EXPORT_SYMBOL(drm_atomic_get_old_bridge_state); * the bridge is not part of the global atomic state. */ struct drm_bridge_state * -drm_atomic_get_new_bridge_state(const struct drm_atomic_state *state, +drm_atomic_get_new_bridge_state(const struct drm_atomic_commit *state, struct drm_bridge *bridge) { struct drm_private_state *obj_state; @@ -1462,7 +1462,7 @@ EXPORT_SYMBOL(drm_atomic_get_new_bridge_state); * sequence must be restarted. All other errors are fatal. */ int -drm_atomic_add_encoder_bridges(struct drm_atomic_state *state, +drm_atomic_add_encoder_bridges(struct drm_atomic_commit *state, struct drm_encoder *encoder) { struct drm_bridge_state *bridge_state; @@ -1506,7 +1506,7 @@ EXPORT_SYMBOL(drm_atomic_add_encoder_bridges); * sequence must be restarted. All other errors are fatal. */ int -drm_atomic_add_affected_connectors(struct drm_atomic_state *state, +drm_atomic_add_affected_connectors(struct drm_atomic_commit *state, struct drm_crtc *crtc) { struct drm_mode_config *config = &state->dev->mode_config; @@ -1570,7 +1570,7 @@ EXPORT_SYMBOL(drm_atomic_add_affected_connectors); * sequence must be restarted. All other errors are fatal. */ int -drm_atomic_add_affected_planes(struct drm_atomic_state *state, +drm_atomic_add_affected_planes(struct drm_atomic_commit *state, struct drm_crtc *crtc) { const struct drm_crtc_state *old_crtc_state = @@ -1622,7 +1622,7 @@ EXPORT_SYMBOL(drm_atomic_add_affected_planes); * sequence must be restarted. All other errors are fatal. */ int -drm_atomic_add_affected_colorops(struct drm_atomic_state *state, +drm_atomic_add_affected_colorops(struct drm_atomic_commit *state, struct drm_plane *plane) { struct drm_colorop *colorop; @@ -1658,7 +1658,7 @@ EXPORT_SYMBOL(drm_atomic_add_affected_colorops); * Returns: * 0 on success, negative error code on failure. */ -int drm_atomic_check_only(struct drm_atomic_state *state) +int drm_atomic_check_only(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; struct drm_mode_config *config = &dev->mode_config; @@ -1766,12 +1766,12 @@ EXPORT_SYMBOL(drm_atomic_check_only); * backoff dance and restart. All other errors are fatal. * * This function will take its own reference on @state. - * Callers should always release their reference with drm_atomic_state_put(). + * Callers should always release their reference with drm_atomic_commit_put(). * * Returns: * 0 on success, negative error code on failure. */ -int drm_atomic_commit(struct drm_atomic_state *state) +int drm_atomic_commit(struct drm_atomic_commit *state) { struct drm_mode_config *config = &state->dev->mode_config; struct drm_printer p = drm_info_printer(state->dev->dev); @@ -1799,12 +1799,12 @@ EXPORT_SYMBOL(drm_atomic_commit); * backoff dance and restart. All other errors are fatal. * * This function will take its own reference on @state. - * Callers should always release their reference with drm_atomic_state_put(). + * Callers should always release their reference with drm_atomic_commit_put(). * * Returns: * 0 on success, negative error code on failure. */ -int drm_atomic_nonblocking_commit(struct drm_atomic_state *state) +int drm_atomic_nonblocking_commit(struct drm_atomic_commit *state) { struct drm_mode_config *config = &state->dev->mode_config; int ret; @@ -1843,7 +1843,7 @@ int __drm_atomic_helper_disable_plane(struct drm_plane *plane, } EXPORT_SYMBOL(__drm_atomic_helper_disable_plane); -static int update_output_state(struct drm_atomic_state *state, +static int update_output_state(struct drm_atomic_commit *state, struct drm_mode_set *set) { struct drm_device *dev = set->crtc->dev; @@ -1913,7 +1913,7 @@ static int update_output_state(struct drm_atomic_state *state, /* just used from drm-client and atomic-helper: */ int __drm_atomic_helper_set_config(struct drm_mode_set *set, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state; struct drm_plane_state *primary_state; @@ -2007,7 +2007,7 @@ static void drm_atomic_private_obj_print_state(struct drm_printer *p, * Note that this function looks into the new state objects and hence its not * safe to be used after the call to drm_atomic_helper_commit_hw_done(). */ -void drm_atomic_print_new_state(const struct drm_atomic_state *state, +void drm_atomic_print_new_state(const struct drm_atomic_commit *state, struct drm_printer *p) { struct drm_plane *plane; diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index a768398a1884..51f39edc31ed 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -77,7 +77,7 @@ * helpers. */ static void -drm_atomic_helper_plane_changed(struct drm_atomic_state *state, +drm_atomic_helper_plane_changed(struct drm_atomic_commit *state, struct drm_plane_state *old_plane_state, struct drm_plane_state *plane_state, struct drm_plane *plane) @@ -104,7 +104,7 @@ drm_atomic_helper_plane_changed(struct drm_atomic_state *state, } } -static int handle_conflicting_encoders(struct drm_atomic_state *state, +static int handle_conflicting_encoders(struct drm_atomic_commit *state, bool disable_conflicting_encoders) { struct drm_connector_state *new_conn_state; @@ -218,7 +218,7 @@ static int handle_conflicting_encoders(struct drm_atomic_state *state, } static void -set_best_encoder(struct drm_atomic_state *state, +set_best_encoder(struct drm_atomic_commit *state, struct drm_connector_state *conn_state, struct drm_encoder *encoder) { @@ -259,7 +259,7 @@ set_best_encoder(struct drm_atomic_state *state, } static void -steal_encoder(struct drm_atomic_state *state, +steal_encoder(struct drm_atomic_commit *state, struct drm_encoder *encoder) { struct drm_crtc_state *crtc_state; @@ -290,7 +290,7 @@ steal_encoder(struct drm_atomic_state *state, } static int -update_connector_routing(struct drm_atomic_state *state, +update_connector_routing(struct drm_atomic_commit *state, struct drm_connector *connector, struct drm_connector_state *old_connector_state, struct drm_connector_state *new_connector_state, @@ -416,7 +416,7 @@ update_connector_routing(struct drm_atomic_state *state, } static int -mode_fixup(struct drm_atomic_state *state) +mode_fixup(struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; @@ -546,7 +546,7 @@ static enum drm_mode_status mode_valid_path(struct drm_connector *connector, } static int -mode_valid(struct drm_atomic_state *state) +mode_valid(struct drm_atomic_commit *state) { struct drm_connector_state *conn_state; struct drm_connector *connector; @@ -578,7 +578,7 @@ mode_valid(struct drm_atomic_state *state) return 0; } -static int drm_atomic_check_valid_clones(struct drm_atomic_state *state, +static int drm_atomic_check_valid_clones(struct drm_atomic_commit *state, struct drm_crtc *crtc) { struct drm_encoder *drm_enc; @@ -647,7 +647,7 @@ static int drm_atomic_check_valid_clones(struct drm_atomic_state *state, */ int drm_atomic_helper_check_modeset(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; @@ -841,7 +841,7 @@ EXPORT_SYMBOL(drm_atomic_helper_check_modeset); */ int drm_atomic_helper_check_wb_connector_state(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(state, connector); @@ -1017,7 +1017,7 @@ EXPORT_SYMBOL(drm_atomic_helper_check_crtc_primary_plane); */ int drm_atomic_helper_check_planes(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; @@ -1105,7 +1105,7 @@ EXPORT_SYMBOL(drm_atomic_helper_check_planes); * Zero for success or -errno */ int drm_atomic_helper_check(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { int ret; @@ -1174,7 +1174,7 @@ crtc_needs_disable(struct drm_crtc_state *old_state, */ void drm_atomic_helper_commit_encoder_bridge_disable(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector *connector; struct drm_connector_state *old_conn_state, *new_conn_state; @@ -1251,7 +1251,7 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_encoder_bridge_disable); * it, disables it. */ void -drm_atomic_helper_commit_crtc_disable(struct drm_device *dev, struct drm_atomic_state *state) +drm_atomic_helper_commit_crtc_disable(struct drm_device *dev, struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; @@ -1313,7 +1313,7 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_crtc_disable); * it, post-disables all encoder bridges. */ void -drm_atomic_helper_commit_encoder_bridge_post_disable(struct drm_device *dev, struct drm_atomic_state *state) +drm_atomic_helper_commit_encoder_bridge_post_disable(struct drm_device *dev, struct drm_atomic_commit *state) { struct drm_connector *connector; struct drm_connector_state *old_conn_state, *new_conn_state; @@ -1367,7 +1367,7 @@ drm_atomic_helper_commit_encoder_bridge_post_disable(struct drm_device *dev, str EXPORT_SYMBOL(drm_atomic_helper_commit_encoder_bridge_post_disable); static void -disable_outputs(struct drm_device *dev, struct drm_atomic_state *state) +disable_outputs(struct drm_device *dev, struct drm_atomic_commit *state) { drm_atomic_helper_commit_encoder_bridge_disable(dev, state); @@ -1395,7 +1395,7 @@ disable_outputs(struct drm_device *dev, struct drm_atomic_state *state) */ void drm_atomic_helper_update_legacy_modeset_state(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector *connector; struct drm_connector_state *old_conn_state, *new_conn_state; @@ -1462,7 +1462,7 @@ EXPORT_SYMBOL(drm_atomic_helper_update_legacy_modeset_state); * Updates the timestamping constants used for precise vblank timestamps * by calling drm_calc_timestamping_constants() for all enabled crtcs in @state. */ -void drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_state *state) +void drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_commit *state) { struct drm_crtc_state *new_crtc_state; struct drm_crtc *crtc; @@ -1486,7 +1486,7 @@ EXPORT_SYMBOL(drm_atomic_helper_calc_timestamping_constants); * chain and change the mode in all bridges as well. */ void -drm_atomic_helper_commit_crtc_set_mode(struct drm_device *dev, struct drm_atomic_state *state) +drm_atomic_helper_commit_crtc_set_mode(struct drm_device *dev, struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; @@ -1564,7 +1564,7 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_crtc_set_mode); * PM since planes updates then only happen when the CRTC is actually enabled. */ void drm_atomic_helper_commit_modeset_disables(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { disable_outputs(dev, state); @@ -1585,7 +1585,7 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_modeset_disables); * commit on each connector. */ void drm_atomic_helper_commit_writebacks(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector *connector; struct drm_connector_state *new_conn_state; @@ -1615,7 +1615,7 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_writebacks); * the entire bridge chain. */ void -drm_atomic_helper_commit_encoder_bridge_pre_enable(struct drm_device *dev, struct drm_atomic_state *state) +drm_atomic_helper_commit_encoder_bridge_pre_enable(struct drm_device *dev, struct drm_atomic_commit *state) { struct drm_connector *connector; struct drm_connector_state *new_conn_state; @@ -1657,7 +1657,7 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_encoder_bridge_pre_enable); * it, enables it. */ void -drm_atomic_helper_commit_crtc_enable(struct drm_device *dev, struct drm_atomic_state *state) +drm_atomic_helper_commit_crtc_enable(struct drm_device *dev, struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state; @@ -1697,7 +1697,7 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_crtc_enable); * it, enables the entire bridge chain. */ void -drm_atomic_helper_commit_encoder_bridge_enable(struct drm_device *dev, struct drm_atomic_state *state) +drm_atomic_helper_commit_encoder_bridge_enable(struct drm_device *dev, struct drm_atomic_commit *state) { struct drm_connector *connector; struct drm_connector_state *new_conn_state; @@ -1757,7 +1757,7 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_encoder_bridge_enable); * PM since planes updates then only happen when the CRTC is actually enabled. */ void drm_atomic_helper_commit_modeset_enables(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { drm_atomic_helper_commit_crtc_enable(dev, state); @@ -1774,7 +1774,7 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_modeset_enables); * next vblank, and inform all the fences of the deadline. */ static void set_fence_deadline(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; @@ -1832,7 +1832,7 @@ static void set_fence_deadline(struct drm_device *dev, * Returns zero if success or < 0 if dma_fence_wait() fails. */ int drm_atomic_helper_wait_for_fences(struct drm_device *dev, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, bool pre_swap) { struct drm_plane *plane; @@ -1881,7 +1881,7 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for_fences); */ void drm_atomic_helper_wait_for_vblanks(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; @@ -1942,7 +1942,7 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for_vblanks); * initialized using drm_atomic_helper_setup_commit(). */ void drm_atomic_helper_wait_for_flip_done(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc *crtc; int i; @@ -1980,7 +1980,7 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for_flip_done); * Note that the default ordering of how the various stages are called is to * match the legacy modeset helper library closest. */ -void drm_atomic_helper_commit_tail(struct drm_atomic_state *state) +void drm_atomic_helper_commit_tail(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; @@ -2010,7 +2010,7 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_tail); * commit. Otherwise, one should use the default implementation * drm_atomic_helper_commit_tail(). */ -void drm_atomic_helper_commit_tail_rpm(struct drm_atomic_state *state) +void drm_atomic_helper_commit_tail_rpm(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; @@ -2031,7 +2031,7 @@ void drm_atomic_helper_commit_tail_rpm(struct drm_atomic_state *state) } EXPORT_SYMBOL(drm_atomic_helper_commit_tail_rpm); -static void commit_tail(struct drm_atomic_state *state) +static void commit_tail(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; const struct drm_mode_config_helper_funcs *funcs; @@ -2081,13 +2081,13 @@ static void commit_tail(struct drm_atomic_state *state) drm_atomic_helper_commit_cleanup_done(state); - drm_atomic_state_put(state); + drm_atomic_commit_put(state); } static void commit_work(struct work_struct *work) { - struct drm_atomic_state *state = container_of(work, - struct drm_atomic_state, + struct drm_atomic_commit *state = container_of(work, + struct drm_atomic_commit, commit_work); commit_tail(state); } @@ -2106,7 +2106,7 @@ static void commit_work(struct work_struct *work) * fails the commit should be treated like a normal synchronous commit. */ int drm_atomic_helper_async_check(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; @@ -2190,7 +2190,7 @@ EXPORT_SYMBOL(drm_atomic_helper_async_check); * TODO: Implement full swap instead of doing in-place changes. */ void drm_atomic_helper_async_commit(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane *plane; struct drm_plane_state *plane_state; @@ -2243,7 +2243,7 @@ EXPORT_SYMBOL(drm_atomic_helper_async_commit); * Zero for success or -errno. */ int drm_atomic_helper_commit(struct drm_device *dev, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, bool nonblock) { int ret; @@ -2305,7 +2305,7 @@ int drm_atomic_helper_commit(struct drm_device *dev, * make sure work items don't artificially stall on each another. */ - drm_atomic_state_get(state); + drm_atomic_commit_get(state); if (nonblock) queue_work(system_dfl_wq, &state->commit_work); else @@ -2347,7 +2347,7 @@ EXPORT_SYMBOL(drm_atomic_helper_commit); * must be done as one global operation, and enabling or disabling a CRTC can * take a long time. But even that is not required. * - * IMPORTANT: A &drm_atomic_state update for multiple CRTCs is sequenced + * IMPORTANT: A &drm_atomic_commit update for multiple CRTCs is sequenced * against all CRTCs therein. Therefore for atomic state updates which only flip * planes the driver must not get the struct &drm_crtc_state of unrelated CRTCs * in its atomic check code: This would prevent committing of atomic updates to @@ -2442,7 +2442,7 @@ static void init_commit(struct drm_crtc_commit *commit, struct drm_crtc *crtc) } static struct drm_crtc_commit * -crtc_or_fake_commit(struct drm_atomic_state *state, struct drm_crtc *crtc) +crtc_or_fake_commit(struct drm_atomic_commit *state, struct drm_crtc *crtc) { if (crtc) { struct drm_crtc_state *new_crtc_state; @@ -2501,14 +2501,14 @@ crtc_or_fake_commit(struct drm_atomic_state *state, struct drm_crtc *crtc) * using the core structure &drm_crtc_commit. * * By default there's no need to clean up resources allocated by this function - * explicitly: drm_atomic_state_default_clear() will take care of that + * explicitly: drm_atomic_commit_default_clear() will take care of that * automatically. * * Returns: * 0 on success. -EBUSY when userspace schedules nonblocking commits too fast, * -ENOMEM on allocation failures and -EINTR when a signal is pending. */ -int drm_atomic_helper_setup_commit(struct drm_atomic_state *state, +int drm_atomic_helper_setup_commit(struct drm_atomic_commit *state, bool nonblock) { struct drm_crtc *crtc; @@ -2633,7 +2633,7 @@ EXPORT_SYMBOL(drm_atomic_helper_setup_commit); * This is part of the atomic helper support for nonblocking commits, see * drm_atomic_helper_setup_commit() for an overview. */ -void drm_atomic_helper_wait_for_dependencies(struct drm_atomic_state *state) +void drm_atomic_helper_wait_for_dependencies(struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state; @@ -2688,7 +2688,7 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for_dependencies); * This is part of the atomic helper support for nonblocking commits, see * drm_atomic_helper_setup_commit() for an overview. */ -void drm_atomic_helper_fake_vblank(struct drm_atomic_state *state) +void drm_atomic_helper_fake_vblank(struct drm_atomic_commit *state) { struct drm_crtc_state *new_crtc_state; struct drm_crtc *crtc; @@ -2726,7 +2726,7 @@ EXPORT_SYMBOL(drm_atomic_helper_fake_vblank); * This is part of the atomic helper support for nonblocking commits, see * drm_atomic_helper_setup_commit() for an overview. */ -void drm_atomic_helper_commit_hw_done(struct drm_atomic_state *state) +void drm_atomic_helper_commit_hw_done(struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; @@ -2766,12 +2766,12 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_hw_done); * * This signals completion of the atomic update @state, including any * cleanup work. If used, it must be called right before calling - * drm_atomic_state_put(). + * drm_atomic_commit_put(). * * This is part of the atomic helper support for nonblocking commits, see * drm_atomic_helper_setup_commit() for an overview. */ -void drm_atomic_helper_commit_cleanup_done(struct drm_atomic_state *state) +void drm_atomic_helper_commit_cleanup_done(struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state; @@ -2812,7 +2812,7 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_cleanup_done); * 0 on success, negative error code on failure. */ int drm_atomic_helper_prepare_planes(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector *connector; struct drm_connector_state *new_conn_state; @@ -2901,7 +2901,7 @@ EXPORT_SYMBOL(drm_atomic_helper_prepare_planes); * use drm_atomic_helper_cleanup_planes(). */ void drm_atomic_helper_unprepare_planes(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane *plane; struct drm_plane_state *new_plane_state; @@ -2970,7 +2970,7 @@ static bool plane_crtc_active(const struct drm_plane_state *state) * This should not be copied blindly by drivers. */ void drm_atomic_helper_commit_planes(struct drm_device *dev, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, uint32_t flags) { struct drm_crtc *crtc; @@ -3093,7 +3093,7 @@ drm_atomic_helper_commit_planes_on_crtc(struct drm_crtc_state *old_crtc_state) { const struct drm_crtc_helper_funcs *crtc_funcs; struct drm_crtc *crtc = old_crtc_state->crtc; - struct drm_atomic_state *old_state = old_crtc_state->state; + struct drm_atomic_commit *old_state = old_crtc_state->state; struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc); struct drm_plane *plane; @@ -3200,7 +3200,7 @@ EXPORT_SYMBOL(drm_atomic_helper_disable_planes_on_crtc); * drm_atomic_helper_unprepare_planes() in this case. */ void drm_atomic_helper_cleanup_planes(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane *plane; struct drm_plane_state *old_plane_state; @@ -3249,7 +3249,7 @@ EXPORT_SYMBOL(drm_atomic_helper_cleanup_planes); * Returns 0 on success. Can return -ERESTARTSYS when @stall is true and the * waiting for the previous commits has been interrupted. */ -int drm_atomic_helper_swap_state(struct drm_atomic_state *state, +int drm_atomic_helper_swap_state(struct drm_atomic_commit *state, bool stall) { int i, ret; @@ -3404,11 +3404,11 @@ int drm_atomic_helper_update_plane(struct drm_plane *plane, uint32_t src_w, uint32_t src_h, struct drm_modeset_acquire_ctx *ctx) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_plane_state *plane_state; int ret = 0; - state = drm_atomic_state_alloc(plane->dev); + state = drm_atomic_commit_alloc(plane->dev); if (!state) return -ENOMEM; @@ -3437,7 +3437,7 @@ int drm_atomic_helper_update_plane(struct drm_plane *plane, ret = drm_atomic_commit(state); fail: - drm_atomic_state_put(state); + drm_atomic_commit_put(state); return ret; } EXPORT_SYMBOL(drm_atomic_helper_update_plane); @@ -3455,11 +3455,11 @@ EXPORT_SYMBOL(drm_atomic_helper_update_plane); int drm_atomic_helper_disable_plane(struct drm_plane *plane, struct drm_modeset_acquire_ctx *ctx) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_plane_state *plane_state; int ret = 0; - state = drm_atomic_state_alloc(plane->dev); + state = drm_atomic_commit_alloc(plane->dev); if (!state) return -ENOMEM; @@ -3479,7 +3479,7 @@ int drm_atomic_helper_disable_plane(struct drm_plane *plane, ret = drm_atomic_commit(state); fail: - drm_atomic_state_put(state); + drm_atomic_commit_put(state); return ret; } EXPORT_SYMBOL(drm_atomic_helper_disable_plane); @@ -3503,11 +3503,11 @@ EXPORT_SYMBOL(drm_atomic_helper_disable_plane); int drm_atomic_helper_set_config(struct drm_mode_set *set, struct drm_modeset_acquire_ctx *ctx) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_crtc *crtc = set->crtc; int ret = 0; - state = drm_atomic_state_alloc(crtc->dev); + state = drm_atomic_commit_alloc(crtc->dev); if (!state) return -ENOMEM; @@ -3523,7 +3523,7 @@ int drm_atomic_helper_set_config(struct drm_mode_set *set, ret = drm_atomic_commit(state); fail: - drm_atomic_state_put(state); + drm_atomic_commit_put(state); return ret; } EXPORT_SYMBOL(drm_atomic_helper_set_config); @@ -3554,7 +3554,7 @@ EXPORT_SYMBOL(drm_atomic_helper_set_config); int drm_atomic_helper_disable_all(struct drm_device *dev, struct drm_modeset_acquire_ctx *ctx) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_connector_state *conn_state; struct drm_connector *conn; struct drm_plane_state *plane_state; @@ -3563,7 +3563,7 @@ int drm_atomic_helper_disable_all(struct drm_device *dev, struct drm_crtc *crtc; int ret, i; - state = drm_atomic_state_alloc(dev); + state = drm_atomic_commit_alloc(dev); if (!state) return -ENOMEM; @@ -3607,7 +3607,7 @@ int drm_atomic_helper_disable_all(struct drm_device *dev, ret = drm_atomic_commit(state); free: - drm_atomic_state_put(state); + drm_atomic_commit_put(state); return ret; } EXPORT_SYMBOL(drm_atomic_helper_disable_all); @@ -3634,11 +3634,11 @@ EXPORT_SYMBOL(drm_atomic_helper_disable_all); int drm_atomic_helper_reset_crtc(struct drm_crtc *crtc, struct drm_modeset_acquire_ctx *ctx) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_crtc_state *crtc_state; int ret; - state = drm_atomic_state_alloc(crtc->dev); + state = drm_atomic_commit_alloc(crtc->dev); if (!state) return -ENOMEM; @@ -3654,7 +3654,7 @@ int drm_atomic_helper_reset_crtc(struct drm_crtc *crtc, ret = drm_atomic_commit(state); out: - drm_atomic_state_put(state); + drm_atomic_commit_put(state); return ret; } @@ -3715,18 +3715,18 @@ EXPORT_SYMBOL(drm_atomic_helper_shutdown); * See also: * drm_atomic_helper_suspend(), drm_atomic_helper_resume() */ -struct drm_atomic_state * +struct drm_atomic_commit * drm_atomic_helper_duplicate_state(struct drm_device *dev, struct drm_modeset_acquire_ctx *ctx) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_connector *conn; struct drm_connector_list_iter conn_iter; struct drm_plane *plane; struct drm_crtc *crtc; int err = 0; - state = drm_atomic_state_alloc(dev); + state = drm_atomic_commit_alloc(dev); if (!state) return ERR_PTR(-ENOMEM); @@ -3778,7 +3778,7 @@ drm_atomic_helper_duplicate_state(struct drm_device *dev, free: if (err < 0) { - drm_atomic_state_put(state); + drm_atomic_commit_put(state); state = ERR_PTR(err); } @@ -3811,10 +3811,10 @@ EXPORT_SYMBOL(drm_atomic_helper_duplicate_state); * drm_atomic_helper_duplicate_state(), drm_atomic_helper_disable_all(), * drm_atomic_helper_resume(), drm_atomic_helper_commit_duplicated_state() */ -struct drm_atomic_state *drm_atomic_helper_suspend(struct drm_device *dev) +struct drm_atomic_commit *drm_atomic_helper_suspend(struct drm_device *dev) { struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; int err; /* This can never be returned, but it makes the compiler happy */ @@ -3828,7 +3828,7 @@ struct drm_atomic_state *drm_atomic_helper_suspend(struct drm_device *dev) err = drm_atomic_helper_disable_all(dev, &ctx); if (err < 0) { - drm_atomic_state_put(state); + drm_atomic_commit_put(state); state = ERR_PTR(err); goto unlock; } @@ -3857,7 +3857,7 @@ EXPORT_SYMBOL(drm_atomic_helper_suspend); * See also: * drm_atomic_helper_suspend() */ -int drm_atomic_helper_commit_duplicated_state(struct drm_atomic_state *state, +int drm_atomic_helper_commit_duplicated_state(struct drm_atomic_commit *state, struct drm_modeset_acquire_ctx *ctx) { int i, ret; @@ -3909,7 +3909,7 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_duplicated_state); * drm_atomic_helper_suspend() */ int drm_atomic_helper_resume(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_modeset_acquire_ctx ctx; int err; @@ -3921,13 +3921,13 @@ int drm_atomic_helper_resume(struct drm_device *dev, err = drm_atomic_helper_commit_duplicated_state(state, &ctx); DRM_MODESET_LOCK_ALL_END(dev, ctx, err); - drm_atomic_state_put(state); + drm_atomic_commit_put(state); return err; } EXPORT_SYMBOL(drm_atomic_helper_resume); -static int page_flip_common(struct drm_atomic_state *state, +static int page_flip_common(struct drm_atomic_commit *state, struct drm_crtc *crtc, struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, @@ -3990,10 +3990,10 @@ int drm_atomic_helper_page_flip(struct drm_crtc *crtc, struct drm_modeset_acquire_ctx *ctx) { struct drm_plane *plane = crtc->primary; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; int ret = 0; - state = drm_atomic_state_alloc(plane->dev); + state = drm_atomic_commit_alloc(plane->dev); if (!state) return -ENOMEM; @@ -4005,7 +4005,7 @@ int drm_atomic_helper_page_flip(struct drm_crtc *crtc, ret = drm_atomic_nonblocking_commit(state); fail: - drm_atomic_state_put(state); + drm_atomic_commit_put(state); return ret; } EXPORT_SYMBOL(drm_atomic_helper_page_flip); @@ -4034,11 +4034,11 @@ int drm_atomic_helper_page_flip_target(struct drm_crtc *crtc, struct drm_modeset_acquire_ctx *ctx) { struct drm_plane *plane = crtc->primary; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_crtc_state *crtc_state; int ret = 0; - state = drm_atomic_state_alloc(plane->dev); + state = drm_atomic_commit_alloc(plane->dev); if (!state) return -ENOMEM; @@ -4057,7 +4057,7 @@ int drm_atomic_helper_page_flip_target(struct drm_crtc *crtc, ret = drm_atomic_nonblocking_commit(state); fail: - drm_atomic_state_put(state); + drm_atomic_commit_put(state); return ret; } EXPORT_SYMBOL(drm_atomic_helper_page_flip_target); diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index 76746ad4a1bb..cc70508d4fdb 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -589,7 +589,7 @@ EXPORT_SYMBOL(drm_atomic_helper_connector_tv_reset); * %0 for success, a negative error code on error. */ int drm_atomic_helper_connector_tv_check(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *old_conn_state = drm_atomic_get_old_connector_state(state, connector); diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 5bd5bf6661df..6441b55cc274 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -347,13 +347,13 @@ drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state, } EXPORT_SYMBOL(drm_atomic_set_crtc_for_connector); -static void set_out_fence_for_crtc(struct drm_atomic_state *state, +static void set_out_fence_for_crtc(struct drm_atomic_commit *state, struct drm_crtc *crtc, s32 __user *fence_ptr) { state->crtcs[drm_crtc_index(crtc)].out_fence_ptr = fence_ptr; } -static s32 __user *get_out_fence_for_crtc(struct drm_atomic_state *state, +static s32 __user *get_out_fence_for_crtc(struct drm_atomic_commit *state, struct drm_crtc *crtc) { s32 __user *fence_ptr; @@ -364,7 +364,7 @@ static s32 __user *get_out_fence_for_crtc(struct drm_atomic_state *state, return fence_ptr; } -static int set_out_fence_for_connector(struct drm_atomic_state *state, +static int set_out_fence_for_connector(struct drm_atomic_commit *state, struct drm_connector *connector, s32 __user *fence_ptr) { @@ -381,7 +381,7 @@ static int set_out_fence_for_connector(struct drm_atomic_state *state, return 0; } -static s32 __user *get_out_fence_for_connector(struct drm_atomic_state *state, +static s32 __user *get_out_fence_for_connector(struct drm_atomic_commit *state, struct drm_connector *connector) { unsigned int index = drm_connector_index(connector); @@ -1104,7 +1104,7 @@ static struct drm_pending_vblank_event *create_vblank_event( return e; } -int drm_atomic_connector_commit_dpms(struct drm_atomic_state *state, +int drm_atomic_connector_commit_dpms(struct drm_atomic_commit *state, struct drm_connector *connector, int mode) { @@ -1171,7 +1171,7 @@ static int drm_atomic_check_prop_changes(int ret, uint64_t old_val, uint64_t pro return 0; } -int drm_atomic_set_property(struct drm_atomic_state *state, +int drm_atomic_set_property(struct drm_atomic_commit *state, struct drm_file *file_priv, struct drm_mode_object *obj, struct drm_property *prop, @@ -1374,7 +1374,7 @@ static int setup_out_fence(struct drm_out_fence_state *fence_state, } static int prepare_signaling(struct drm_device *dev, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_mode_atomic *arg, struct drm_file *file_priv, struct drm_out_fence_state **fence_state, @@ -1499,7 +1499,7 @@ static int prepare_signaling(struct drm_device *dev, } static void complete_signaling(struct drm_device *dev, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_out_fence_state *fence_state, unsigned int num_fences, bool install_fds) @@ -1522,7 +1522,7 @@ static void complete_signaling(struct drm_device *dev, /* * Free the allocated event. drm_atomic_helper_setup_commit * can allocate an event too, so only free it if it's ours - * to prevent a double free in drm_atomic_state_clear. + * to prevent a double free in drm_atomic_commit_clear. */ if (event && (event->base.fence || event->base.file_priv)) { drm_event_cancel_free(dev, &event->base); @@ -1549,7 +1549,7 @@ static void complete_signaling(struct drm_device *dev, } static void -set_async_flip(struct drm_atomic_state *state) +set_async_flip(struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; @@ -1569,7 +1569,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, uint32_t __user *props_ptr = (uint32_t __user *)(unsigned long)(arg->props_ptr); uint64_t __user *prop_values_ptr = (uint64_t __user *)(unsigned long)(arg->prop_values_ptr); unsigned int copied_objs, copied_props; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_modeset_acquire_ctx ctx; struct drm_out_fence_state *fence_state; int ret = 0; @@ -1618,7 +1618,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, return -EINVAL; } - state = drm_atomic_state_alloc(dev); + state = drm_atomic_commit_alloc(dev); if (!state) return -ENOMEM; @@ -1726,13 +1726,13 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, complete_signaling(dev, state, fence_state, num_fences, !ret); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry; } - drm_atomic_state_put(state); + drm_atomic_commit_put(state); drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); diff --git a/drivers/gpu/drm/drm_blend.c b/drivers/gpu/drm/drm_blend.c index 1f3af27d2418..2f0d1ba285be 100644 --- a/drivers/gpu/drm/drm_blend.c +++ b/drivers/gpu/drm/drm_blend.c @@ -449,7 +449,7 @@ int drm_plane_create_zpos_immutable_property(struct drm_plane *plane, } EXPORT_SYMBOL(drm_plane_create_zpos_immutable_property); -static int drm_atomic_state_zpos_cmp(const void *a, const void *b) +static int drm_atomic_commit_zpos_cmp(const void *a, const void *b) { const struct drm_plane_state *sa = *(struct drm_plane_state **)a; const struct drm_plane_state *sb = *(struct drm_plane_state **)b; @@ -463,7 +463,7 @@ static int drm_atomic_state_zpos_cmp(const void *a, const void *b) static int drm_atomic_helper_crtc_normalize_zpos(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) { - struct drm_atomic_state *state = crtc_state->state; + struct drm_atomic_commit *state = crtc_state->state; struct drm_device *dev = crtc->dev; int total_planes = dev->mode_config.num_total_plane; struct drm_plane_state **states; @@ -494,7 +494,7 @@ static int drm_atomic_helper_crtc_normalize_zpos(struct drm_crtc *crtc, plane->base.id, plane->name, plane_state->zpos); } - sort(states, n, sizeof(*states), drm_atomic_state_zpos_cmp, NULL); + sort(states, n, sizeof(*states), drm_atomic_commit_zpos_cmp, NULL); for (i = 0; i < n; i++) { plane = states[i]->plane; @@ -529,7 +529,7 @@ static int drm_atomic_helper_crtc_normalize_zpos(struct drm_crtc *crtc, * Zero for success or -errno */ int drm_atomic_normalize_zpos(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c index d4b3478258ec..ce180f0b26b2 100644 --- a/drivers/gpu/drm/drm_bridge.c +++ b/drivers/gpu/drm/drm_bridge.c @@ -799,7 +799,7 @@ EXPORT_SYMBOL(drm_bridge_chain_mode_set); * Note: the bridge passed should be the one closest to the encoder */ void drm_atomic_bridge_chain_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_encoder *encoder; struct drm_bridge *iter; @@ -824,7 +824,7 @@ void drm_atomic_bridge_chain_disable(struct drm_bridge *bridge, EXPORT_SYMBOL(drm_atomic_bridge_chain_disable); static void drm_atomic_bridge_call_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { if (state && bridge->funcs->atomic_post_disable) bridge->funcs->atomic_post_disable(bridge, state); @@ -857,7 +857,7 @@ static void drm_atomic_bridge_call_post_disable(struct drm_bridge *bridge, * Note: the bridge passed should be the one closest to the encoder */ void drm_atomic_bridge_chain_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_encoder *encoder; struct drm_bridge *next, *limit; @@ -921,7 +921,7 @@ void drm_atomic_bridge_chain_post_disable(struct drm_bridge *bridge, EXPORT_SYMBOL(drm_atomic_bridge_chain_post_disable); static void drm_atomic_bridge_call_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { if (state && bridge->funcs->atomic_pre_enable) bridge->funcs->atomic_pre_enable(bridge, state); @@ -953,7 +953,7 @@ static void drm_atomic_bridge_call_pre_enable(struct drm_bridge *bridge, * Note: the bridge passed should be the one closest to the encoder */ void drm_atomic_bridge_chain_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_encoder *encoder; struct drm_bridge *iter, *next, *limit; @@ -1023,7 +1023,7 @@ EXPORT_SYMBOL(drm_atomic_bridge_chain_pre_enable); * Note: the bridge passed should be the one closest to the encoder */ void drm_atomic_bridge_chain_enable(struct drm_bridge *first_bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { if (!first_bridge) return; @@ -1248,7 +1248,7 @@ drm_atomic_bridge_chain_select_bus_fmts(struct drm_bridge *bridge, static void drm_atomic_bridge_propagate_bus_flags(struct drm_bridge *bridge, struct drm_connector *conn, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_bridge_state *bridge_state, *next_bridge_state; u32 output_flags = 0; diff --git a/drivers/gpu/drm/drm_client_modeset.c b/drivers/gpu/drm/drm_client_modeset.c index bb49b8361271..0080a8e9556a 100644 --- a/drivers/gpu/drm/drm_client_modeset.c +++ b/drivers/gpu/drm/drm_client_modeset.c @@ -1035,14 +1035,14 @@ static int drm_client_modeset_commit_atomic(struct drm_client_dev *client, bool { struct drm_device *dev = client->dev; struct drm_plane *plane; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_modeset_acquire_ctx ctx; struct drm_mode_set *mode_set; int ret; drm_modeset_acquire_init(&ctx, 0); - state = drm_atomic_state_alloc(dev); + state = drm_atomic_commit_alloc(dev); if (!state) { ret = -ENOMEM; goto out_ctx; @@ -1107,7 +1107,7 @@ static int drm_client_modeset_commit_atomic(struct drm_client_dev *client, bool if (ret == -EDEADLK) goto backoff; - drm_atomic_state_put(state); + drm_atomic_commit_put(state); out_ctx: drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); @@ -1115,7 +1115,7 @@ static int drm_client_modeset_commit_atomic(struct drm_client_dev *client, bool return ret; backoff: - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); drm_modeset_backoff(&ctx); goto retry; diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index c598b99673fc..3bcf82cf61a7 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -280,7 +280,7 @@ static int drm_crtc_legacy_gamma_set(struct drm_crtc *crtc, struct drm_modeset_acquire_ctx *ctx) { struct drm_device *dev = crtc->dev; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_crtc_state *crtc_state; struct drm_property_blob *blob; struct drm_color_lut *blob_data; @@ -300,7 +300,7 @@ static int drm_crtc_legacy_gamma_set(struct drm_crtc *crtc, else return -ENODEV; - state = drm_atomic_state_alloc(crtc->dev); + state = drm_atomic_commit_alloc(crtc->dev); if (!state) return -ENOMEM; @@ -339,7 +339,7 @@ static int drm_crtc_legacy_gamma_set(struct drm_crtc *crtc, ret = drm_atomic_commit(state); fail: - drm_atomic_state_put(state); + drm_atomic_commit_put(state); drm_property_blob_put(blob); return ret; } @@ -831,7 +831,7 @@ static void fill_palette_332(struct drm_crtc *crtc, u16 r, u16 g, u16 b, } /** - * drm_crtc_fill_palette_332 - Programs a default palette for R332-like formats + * drm_crtc_fill_palette_332 - Programs a default palette for RGB332-like formats * @crtc: The displaying CRTC * @set_palette: Callback for programming the hardware gamma LUT * diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index 5de9aaa5ba04..4a8cfe046e4a 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -446,7 +446,7 @@ EXPORT_SYMBOL(drm_crtc_helper_set_mode); * RETURNS: * Zero on success, or an errno code otherwise. */ -int drm_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) +int drm_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h index c09409229644..83146ffef00c 100644 --- a/drivers/gpu/drm/drm_crtc_internal.h +++ b/drivers/gpu/drm/drm_crtc_internal.h @@ -44,7 +44,7 @@ enum drm_connector_force; enum drm_mode_status; struct cea_sad; -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_bridge; struct drm_connector; struct drm_crtc; @@ -248,16 +248,16 @@ void drm_atomic_debugfs_init(struct drm_device *dev); int __drm_atomic_helper_disable_plane(struct drm_plane *plane, struct drm_plane_state *plane_state); int __drm_atomic_helper_set_config(struct drm_mode_set *set, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); -void drm_atomic_print_new_state(const struct drm_atomic_state *state, +void drm_atomic_print_new_state(const struct drm_atomic_commit *state, struct drm_printer *p); /* drm_atomic_uapi.c */ -int drm_atomic_connector_commit_dpms(struct drm_atomic_state *state, +int drm_atomic_connector_commit_dpms(struct drm_atomic_commit *state, struct drm_connector *connector, int mode); -int drm_atomic_set_property(struct drm_atomic_state *state, +int drm_atomic_set_property(struct drm_atomic_commit *state, struct drm_file *file_priv, struct drm_mode_object *obj, struct drm_property *prop, diff --git a/drivers/gpu/drm/drm_damage_helper.c b/drivers/gpu/drm/drm_damage_helper.c index 1b6850aa1688..74a7f4252ecf 100644 --- a/drivers/gpu/drm/drm_damage_helper.c +++ b/drivers/gpu/drm/drm_damage_helper.c @@ -66,7 +66,7 @@ static void convert_clip_rect_to_rect(const struct drm_clip_rect *src, * full plane update should happen. It also ensure helper iterator will return * &drm_plane_state.src as damage. */ -void drm_atomic_helper_check_plane_damage(struct drm_atomic_state *state, +void drm_atomic_helper_check_plane_damage(struct drm_atomic_commit *state, struct drm_plane_state *plane_state) { struct drm_crtc_state *crtc_state; @@ -114,7 +114,7 @@ int drm_atomic_helper_dirtyfb(struct drm_framebuffer *fb, struct drm_modeset_acquire_ctx ctx; struct drm_property_blob *damage = NULL; struct drm_mode_rect *rects = NULL; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_plane *plane; int ret = 0; @@ -125,7 +125,7 @@ int drm_atomic_helper_dirtyfb(struct drm_framebuffer *fb, drm_modeset_acquire_init(&ctx, file_priv ? DRM_MODESET_ACQUIRE_INTERRUPTIBLE : 0); - state = drm_atomic_state_alloc(fb->dev); + state = drm_atomic_commit_alloc(fb->dev); if (!state) { ret = -ENOMEM; goto out_drop_locks; @@ -184,7 +184,7 @@ int drm_atomic_helper_dirtyfb(struct drm_framebuffer *fb, out: if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry; @@ -192,7 +192,7 @@ int drm_atomic_helper_dirtyfb(struct drm_framebuffer *fb, drm_property_blob_put(damage); kfree(rects); - drm_atomic_state_put(state); + drm_atomic_commit_put(state); out_drop_locks: drm_modeset_drop_locks(&ctx); diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index a80a335f4148..38d25dce7f33 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -763,7 +763,7 @@ static int setcmap_atomic(struct fb_cmap *cmap, struct fb_info *info) struct drm_property_blob *gamma_lut = NULL; struct drm_modeset_acquire_ctx ctx; struct drm_crtc_state *crtc_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_mode_set *modeset; struct drm_crtc *crtc; u16 *r, *g, *b; @@ -772,7 +772,7 @@ static int setcmap_atomic(struct fb_cmap *cmap, struct fb_info *info) drm_modeset_acquire_init(&ctx, 0); - state = drm_atomic_state_alloc(dev); + state = drm_atomic_commit_alloc(dev); if (!state) { ret = -ENOMEM; goto out_ctx; @@ -831,7 +831,7 @@ static int setcmap_atomic(struct fb_cmap *cmap, struct fb_info *info) goto backoff; drm_property_blob_put(gamma_lut); - drm_atomic_state_put(state); + drm_atomic_commit_put(state); out_ctx: drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); @@ -839,7 +839,7 @@ static int setcmap_atomic(struct fb_cmap *cmap, struct fb_info *info) return ret; backoff: - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); drm_modeset_backoff(&ctx); goto retry; } diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c index 147ac19f851b..d32aceb6ca9b 100644 --- a/drivers/gpu/drm/drm_framebuffer.c +++ b/drivers/gpu/drm/drm_framebuffer.c @@ -1000,7 +1000,7 @@ static int atomic_remove_fb(struct drm_framebuffer *fb) { struct drm_modeset_acquire_ctx ctx; struct drm_device *dev = fb->dev; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_plane *plane; struct drm_connector *conn __maybe_unused; struct drm_connector_state *conn_state; @@ -1011,7 +1011,7 @@ static int atomic_remove_fb(struct drm_framebuffer *fb) retry_disable: drm_modeset_acquire_init(&ctx, 0); - state = drm_atomic_state_alloc(dev); + state = drm_atomic_commit_alloc(dev); if (!state) { ret = -ENOMEM; goto out; @@ -1081,12 +1081,12 @@ static int atomic_remove_fb(struct drm_framebuffer *fb) unlock: if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); drm_modeset_backoff(&ctx); goto retry; } - drm_atomic_state_put(state); + drm_atomic_commit_put(state); out: drm_modeset_drop_locks(&ctx); diff --git a/drivers/gpu/drm/drm_gem_framebuffer_helper.c b/drivers/gpu/drm/drm_gem_framebuffer_helper.c index 9166c353f131..88808e972cc1 100644 --- a/drivers/gpu/drm/drm_gem_framebuffer_helper.c +++ b/drivers/gpu/drm/drm_gem_framebuffer_helper.c @@ -172,8 +172,8 @@ int drm_gem_fb_init_with_funcs(struct drm_device *dev, } for (i = 0; i < info->num_planes; i++) { - unsigned int width = mode_cmd->width / (i ? info->hsub : 1); - unsigned int height = mode_cmd->height / (i ? info->vsub : 1); + unsigned int width = drm_format_info_plane_width(info, mode_cmd->width, i); + unsigned int height = drm_format_info_plane_height(info, mode_cmd->height, i); unsigned int min_size; objs[i] = drm_gem_object_lookup(file, mode_cmd->handles[i]); diff --git a/drivers/gpu/drm/drm_gpusvm.c b/drivers/gpu/drm/drm_gpusvm.c index 8526d6d3c828..365a9c0b522a 100644 --- a/drivers/gpu/drm/drm_gpusvm.c +++ b/drivers/gpu/drm/drm_gpusvm.c @@ -1065,6 +1065,11 @@ drm_gpusvm_range_find_or_insert(struct drm_gpusvm *gpusvm, goto err_notifier_remove; } + if (vas->vm_flags & (VM_IO | VM_PFNMAP)) { + err = -EIO; + goto err_notifier_remove; + } + range = drm_gpusvm_range_find(notifier, fault_addr, fault_addr + 1); if (range) goto out_mmunlock; diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c index 9ab6113d74a2..25cf04d029f7 100644 --- a/drivers/gpu/drm/drm_mipi_dbi.c +++ b/drivers/gpu/drm/drm_mipi_dbi.c @@ -344,7 +344,7 @@ EXPORT_SYMBOL(drm_mipi_dbi_crtc_helper_mode_valid); * 0 on success, or a negative errno code otherwise. */ int drm_mipi_dbi_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); struct drm_crtc_state *new_crtc_state = NULL; @@ -375,7 +375,7 @@ EXPORT_SYMBOL(drm_mipi_dbi_plane_helper_atomic_check); * this as their struct &drm_plane_helper_funcs.atomic_update callback. */ void drm_mipi_dbi_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = plane->state; struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); @@ -434,7 +434,7 @@ static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev) * Returns: * 0 on success, or a negative errno code otherwise. */ -int drm_mipi_dbi_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) +int drm_mipi_dbi_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); int ret; @@ -461,7 +461,7 @@ EXPORT_SYMBOL(drm_mipi_dbi_crtc_helper_atomic_check); * struct &drm_crtc_helper_funcs.atomic_disable callback. */ void drm_mipi_dbi_crtc_helper_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(crtc->dev); diff --git a/drivers/gpu/drm/drm_mode_object.c b/drivers/gpu/drm/drm_mode_object.c index 2d943a610b88..21fc9deda437 100644 --- a/drivers/gpu/drm/drm_mode_object.c +++ b/drivers/gpu/drm/drm_mode_object.c @@ -561,11 +561,11 @@ static int set_property_atomic(struct drm_mode_object *obj, uint64_t prop_value) { struct drm_device *dev = prop->dev; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_modeset_acquire_ctx ctx; int ret; - state = drm_atomic_state_alloc(dev); + state = drm_atomic_commit_alloc(dev); if (!state) return -ENOMEM; @@ -590,12 +590,12 @@ static int set_property_atomic(struct drm_mode_object *obj, } out: if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); drm_modeset_backoff(&ctx); goto retry; } - drm_atomic_state_put(state); + drm_atomic_commit_put(state); drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); diff --git a/drivers/gpu/drm/drm_modeset_helper.c b/drivers/gpu/drm/drm_modeset_helper.c index d7721df744e7..e54584da4c3d 100644 --- a/drivers/gpu/drm/drm_modeset_helper.c +++ b/drivers/gpu/drm/drm_modeset_helper.c @@ -190,7 +190,7 @@ EXPORT_SYMBOL(drm_crtc_init); */ int drm_mode_config_helper_suspend(struct drm_device *dev) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; if (!dev) return 0; diff --git a/drivers/gpu/drm/drm_ras.c b/drivers/gpu/drm/drm_ras.c index b2fa5ab86d87..d6eab29a1394 100644 --- a/drivers/gpu/drm/drm_ras.c +++ b/drivers/gpu/drm/drm_ras.c @@ -26,7 +26,7 @@ * efficient lookup by ID. Nodes can be registered or unregistered * dynamically at runtime. * - * A Generic Netlink family `drm_ras` exposes two main operations to + * A Generic Netlink family `drm_ras` exposes the below operations to * userspace: * * 1. LIST_NODES: Dump all currently registered RAS nodes. @@ -37,6 +37,10 @@ * Returns all counters of a node if only Node ID is provided or specific * error counters. * + * 3. CLEAR_ERROR_COUNTER: Clear error counter of a given node. + * Userspace must provide Node ID, Error ID. + * Clears specific error counter of a node if supported. + * * Node registration: * * - drm_ras_node_register(): Registers a new node and assigns @@ -66,6 +70,8 @@ * operation, fetching all counters from a specific node. * - drm_ras_nl_get_error_counter_doit(): Implements the GET_ERROR_COUNTER doit * operation, fetching a counter value from a specific node. + * - drm_ras_nl_clear_error_counter_doit(): Implements the CLEAR_ERROR_COUNTER doit + * operation, clearing a counter value from a specific node. */ static DEFINE_XARRAY_ALLOC(drm_ras_xa); @@ -314,6 +320,41 @@ int drm_ras_nl_get_error_counter_doit(struct sk_buff *skb, return doit_reply_value(info, node_id, error_id); } +/** + * drm_ras_nl_clear_error_counter_doit() - Clear an error counter of a node + * @skb: Netlink message buffer + * @info: Generic Netlink info containing attributes of the request + * + * Extracts the node ID and error ID from the netlink attributes and + * clears the current value. + * + * Return: 0 on success, or negative errno on failure. + */ +int drm_ras_nl_clear_error_counter_doit(struct sk_buff *skb, + struct genl_info *info) +{ + struct drm_ras_node *node; + u32 node_id, error_id; + + if (!info->attrs || + GENL_REQ_ATTR_CHECK(info, DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID) || + GENL_REQ_ATTR_CHECK(info, DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID)) + return -EINVAL; + + node_id = nla_get_u32(info->attrs[DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID]); + error_id = nla_get_u32(info->attrs[DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID]); + + node = xa_load(&drm_ras_xa, node_id); + if (!node || !node->clear_error_counter) + return -ENOENT; + + if (error_id < node->error_counter_range.first || + error_id > node->error_counter_range.last) + return -EINVAL; + + return node->clear_error_counter(node, error_id); +} + /** * drm_ras_node_register() - Register a new RAS node * @node: Node structure to register diff --git a/drivers/gpu/drm/drm_ras_nl.c b/drivers/gpu/drm/drm_ras_nl.c index 16803d0c4a44..dea1c1b2494e 100644 --- a/drivers/gpu/drm/drm_ras_nl.c +++ b/drivers/gpu/drm/drm_ras_nl.c @@ -22,6 +22,12 @@ static const struct nla_policy drm_ras_get_error_counter_dump_nl_policy[DRM_RAS_ [DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID] = { .type = NLA_U32, }, }; +/* DRM_RAS_CMD_CLEAR_ERROR_COUNTER - do */ +static const struct nla_policy drm_ras_clear_error_counter_nl_policy[DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID + 1] = { + [DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID] = { .type = NLA_U32, }, + [DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID] = { .type = NLA_U32, }, +}; + /* Ops table for drm_ras */ static const struct genl_split_ops drm_ras_nl_ops[] = { { @@ -43,6 +49,13 @@ static const struct genl_split_ops drm_ras_nl_ops[] = { .maxattr = DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID, .flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DUMP, }, + { + .cmd = DRM_RAS_CMD_CLEAR_ERROR_COUNTER, + .doit = drm_ras_nl_clear_error_counter_doit, + .policy = drm_ras_clear_error_counter_nl_policy, + .maxattr = DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID, + .flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DO, + }, }; struct genl_family drm_ras_nl_family __ro_after_init = { diff --git a/drivers/gpu/drm/drm_ras_nl.h b/drivers/gpu/drm/drm_ras_nl.h index 06ccd9342773..a398643572a5 100644 --- a/drivers/gpu/drm/drm_ras_nl.h +++ b/drivers/gpu/drm/drm_ras_nl.h @@ -18,6 +18,8 @@ int drm_ras_nl_get_error_counter_doit(struct sk_buff *skb, struct genl_info *info); int drm_ras_nl_get_error_counter_dumpit(struct sk_buff *skb, struct netlink_callback *cb); +int drm_ras_nl_clear_error_counter_doit(struct sk_buff *skb, + struct genl_info *info); extern struct genl_family drm_ras_nl_family; diff --git a/drivers/gpu/drm/drm_self_refresh_helper.c b/drivers/gpu/drm/drm_self_refresh_helper.c index c08e7f590ca5..37ec7fb00f03 100644 --- a/drivers/gpu/drm/drm_self_refresh_helper.c +++ b/drivers/gpu/drm/drm_self_refresh_helper.c @@ -73,7 +73,7 @@ static void drm_self_refresh_helper_entry_work(struct work_struct *work) struct drm_crtc *crtc = sr_data->crtc; struct drm_device *dev = crtc->dev; struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_connector *conn; struct drm_connector_state *conn_state; struct drm_crtc_state *crtc_state; @@ -81,7 +81,7 @@ static void drm_self_refresh_helper_entry_work(struct work_struct *work) drm_modeset_acquire_init(&ctx, 0); - state = drm_atomic_state_alloc(dev); + state = drm_atomic_commit_alloc(dev); if (!state) { ret = -ENOMEM; goto out_drop_locks; @@ -117,13 +117,13 @@ static void drm_self_refresh_helper_entry_work(struct work_struct *work) out: if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry; } - drm_atomic_state_put(state); + drm_atomic_commit_put(state); out_drop_locks: drm_modeset_drop_locks(&ctx); @@ -143,7 +143,7 @@ static void drm_self_refresh_helper_entry_work(struct work_struct *work) * entering self refresh mode after activity. */ void -drm_self_refresh_helper_update_avg_times(struct drm_atomic_state *state, +drm_self_refresh_helper_update_avg_times(struct drm_atomic_commit *state, unsigned int commit_time_ms, unsigned int new_self_refresh_mask) { @@ -185,7 +185,7 @@ EXPORT_SYMBOL(drm_self_refresh_helper_update_avg_times); * At the end, we queue up the self refresh entry work so we can enter PSR after * the desired delay. */ -void drm_self_refresh_helper_alter_state(struct drm_atomic_state *state) +void drm_self_refresh_helper_alter_state(struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; diff --git a/drivers/gpu/drm/drm_simple_kms_helper.c b/drivers/gpu/drm/drm_simple_kms_helper.c index 4d91513a1e34..8e1d07b9f1e3 100644 --- a/drivers/gpu/drm/drm_simple_kms_helper.c +++ b/drivers/gpu/drm/drm_simple_kms_helper.c @@ -53,7 +53,7 @@ drm_simple_kms_crtc_mode_valid(struct drm_crtc *crtc, } static int drm_simple_kms_crtc_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); int ret; @@ -70,7 +70,7 @@ static int drm_simple_kms_crtc_check(struct drm_crtc *crtc, } static void drm_simple_kms_crtc_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane *plane; struct drm_simple_display_pipe *pipe; @@ -84,7 +84,7 @@ static void drm_simple_kms_crtc_enable(struct drm_crtc *crtc, } static void drm_simple_kms_crtc_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_simple_display_pipe *pipe; @@ -169,7 +169,7 @@ static const struct drm_crtc_funcs drm_simple_kms_crtc_funcs = { }; static int drm_simple_kms_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -198,7 +198,7 @@ static int drm_simple_kms_plane_atomic_check(struct drm_plane *plane, } static void drm_simple_kms_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_pstate = drm_atomic_get_old_plane_state(state, plane); diff --git a/drivers/gpu/drm/drm_vblank_helper.c b/drivers/gpu/drm/drm_vblank_helper.c index a04a6ba1b0ca..d3f8147ecdc1 100644 --- a/drivers/gpu/drm/drm_vblank_helper.c +++ b/drivers/gpu/drm/drm_vblank_helper.c @@ -49,7 +49,7 @@ * See also struct &drm_crtc_helper_funcs.atomic_flush. */ void drm_crtc_vblank_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = crtc->dev; struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -82,7 +82,7 @@ EXPORT_SYMBOL(drm_crtc_vblank_atomic_flush); * See also struct &drm_crtc_helper_funcs.atomic_enable. */ void drm_crtc_vblank_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { drm_crtc_vblank_on(crtc); } @@ -99,7 +99,7 @@ EXPORT_SYMBOL(drm_crtc_vblank_atomic_enable); * See also struct &drm_crtc_funcs.atomic_disable. */ void drm_crtc_vblank_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { drm_crtc_vblank_off(crtc); } diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index 41252caccd67..b071c019670d 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c @@ -19,7 +19,7 @@ #include "exynos_drm_plane.h" static void exynos_drm_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); @@ -30,7 +30,7 @@ static void exynos_drm_crtc_atomic_enable(struct drm_crtc *crtc, } static void exynos_drm_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); @@ -48,7 +48,7 @@ static void exynos_drm_crtc_atomic_disable(struct drm_crtc *crtc, } static int exynos_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -64,7 +64,7 @@ static int exynos_crtc_atomic_check(struct drm_crtc *crtc, } static void exynos_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); @@ -73,7 +73,7 @@ static void exynos_crtc_atomic_begin(struct drm_crtc *crtc, } static void exynos_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index da043bd357a4..5c04ef87e400 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -230,7 +230,7 @@ exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config, } static int exynos_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -254,7 +254,7 @@ static int exynos_plane_atomic_check(struct drm_plane *plane, } static void exynos_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -269,7 +269,7 @@ static void exynos_plane_atomic_update(struct drm_plane *plane, } static void exynos_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane); diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c index 2af60d98f48f..9ef16f5eb613 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c @@ -21,7 +21,7 @@ #include "fsl_dcu_drm_plane.h" static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = crtc->dev; struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; @@ -43,7 +43,7 @@ static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc, } static void fsl_dcu_drm_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -64,7 +64,7 @@ static void fsl_dcu_drm_crtc_atomic_disable(struct drm_crtc *crtc, } static void fsl_dcu_drm_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = crtc->dev; struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c index a9b3467263d6..b34f880c1e09 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c @@ -36,7 +36,7 @@ static int fsl_dcu_drm_plane_index(struct drm_plane *plane) } static int fsl_dcu_drm_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -62,7 +62,7 @@ static int fsl_dcu_drm_plane_atomic_check(struct drm_plane *plane, } static void fsl_dcu_drm_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private; unsigned int value; @@ -78,7 +78,7 @@ static void fsl_dcu_drm_plane_atomic_disable(struct drm_plane *plane, } static void fsl_dcu_drm_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private; diff --git a/drivers/gpu/drm/gud/gud_connector.c b/drivers/gpu/drm/gud/gud_connector.c index a91a7e96cb88..ea0cca58b7c8 100644 --- a/drivers/gpu/drm/gud/gud_connector.c +++ b/drivers/gpu/drm/gud/gud_connector.c @@ -62,13 +62,13 @@ static void gud_connector_backlight_update_status_work(struct work_struct *work) struct drm_connector_state *connector_state; struct drm_device *drm = connector->dev; struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; int idx, ret; if (!drm_dev_enter(drm, &idx)) return; - state = drm_atomic_state_alloc(drm); + state = drm_atomic_commit_alloc(drm); if (!state) { ret = -ENOMEM; goto exit; @@ -89,12 +89,12 @@ static void gud_connector_backlight_update_status_work(struct work_struct *work) ret = drm_atomic_commit(state); out: if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); drm_modeset_backoff(&ctx); goto retry; } - drm_atomic_state_put(state); + drm_atomic_commit_put(state); drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); @@ -285,7 +285,7 @@ static int gud_connector_get_modes(struct drm_connector *connector) } static int gud_connector_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *new_state; struct drm_crtc_state *new_crtc_state; diff --git a/drivers/gpu/drm/gud/gud_internal.h b/drivers/gpu/drm/gud/gud_internal.h index 8eec8335f5f9..95744b0b6c72 100644 --- a/drivers/gpu/drm/gud/gud_internal.h +++ b/drivers/gpu/drm/gud/gud_internal.h @@ -63,13 +63,13 @@ int gud_usb_set_u8(struct gud_device *gdrm, u8 request, u8 val); void gud_clear_damage(struct gud_device *gdrm); void gud_flush_work(struct work_struct *work); void gud_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void gud_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); int gud_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void gud_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *atomic_state); + struct drm_atomic_commit *atomic_state); int gud_connector_fill_properties(struct drm_connector_state *connector_state, struct gud_property_req *properties); int gud_get_connectors(struct gud_device *gdrm); diff --git a/drivers/gpu/drm/gud/gud_pipe.c b/drivers/gpu/drm/gud/gud_pipe.c index 495804e1d200..5ef887d8485a 100644 --- a/drivers/gpu/drm/gud/gud_pipe.c +++ b/drivers/gpu/drm/gud/gud_pipe.c @@ -451,7 +451,7 @@ static void gud_fb_handle_damage(struct gud_device *gdrm, struct drm_framebuffer } int gud_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct gud_device *gdrm = to_gud_device(plane->dev); struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); @@ -581,7 +581,7 @@ int gud_plane_atomic_check(struct drm_plane *plane, } void gud_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct gud_device *gdrm = to_gud_device(drm); @@ -598,7 +598,7 @@ void gud_crtc_atomic_enable(struct drm_crtc *crtc, } void gud_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct gud_device *gdrm = to_gud_device(drm); @@ -614,7 +614,7 @@ void gud_crtc_atomic_disable(struct drm_crtc *crtc, } void gud_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *atomic_state) + struct drm_atomic_commit *atomic_state) { struct drm_device *drm = plane->dev; struct gud_device *gdrm = to_gud_device(drm); diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c index 89bed78f1466..e276b8ca213c 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c @@ -53,7 +53,7 @@ static const struct hibmc_dislay_pll_config hibmc_pll_table[] = { }; static int hibmc_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -99,7 +99,7 @@ static int hibmc_plane_atomic_check(struct drm_plane *plane, } static void hibmc_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -172,7 +172,7 @@ static void hibmc_crtc_dpms(struct drm_crtc *crtc, u32 dpms) } static void hibmc_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { u32 reg; struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); @@ -191,7 +191,7 @@ static void hibmc_crtc_atomic_enable(struct drm_crtc *crtc, } static void hibmc_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { u32 reg; struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); @@ -392,7 +392,7 @@ static void hibmc_crtc_mode_set_nofb(struct drm_crtc *crtc) } static void hibmc_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { u32 reg; struct drm_device *dev = crtc->dev; @@ -412,7 +412,7 @@ static void hibmc_crtc_atomic_begin(struct drm_crtc *crtc, } static void hibmc_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { unsigned long flags; diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c index 616821e3c933..2da04ac89d4d 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c @@ -148,7 +148,7 @@ static inline int hibmc_dp_prepare(struct hibmc_dp *dp, struct drm_display_mode } static void hibmc_dp_encoder_enable(struct drm_encoder *drm_encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct hibmc_dp *dp = container_of(drm_encoder, struct hibmc_dp, encoder); struct drm_display_mode *mode = &drm_encoder->crtc->state->mode; @@ -160,7 +160,7 @@ static void hibmc_dp_encoder_enable(struct drm_encoder *drm_encoder, } static void hibmc_dp_encoder_disable(struct drm_encoder *drm_encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct hibmc_dp *dp = container_of(drm_encoder, struct hibmc_dp, encoder); diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c index 76384b4581bf..902c5dace4ff 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -438,7 +438,7 @@ static void ade_dump_regs(void __iomem *base) { } #endif static void ade_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); struct ade_hw_ctx *ctx = kcrtc->hw_ctx; @@ -461,7 +461,7 @@ static void ade_crtc_atomic_enable(struct drm_crtc *crtc, } static void ade_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); struct ade_hw_ctx *ctx = kcrtc->hw_ctx; @@ -487,7 +487,7 @@ static void ade_crtc_mode_set_nofb(struct drm_crtc *crtc) } static void ade_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); struct ade_hw_ctx *ctx = kcrtc->hw_ctx; @@ -500,7 +500,7 @@ static void ade_crtc_atomic_begin(struct drm_crtc *crtc, } static void ade_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); @@ -759,7 +759,7 @@ static void ade_disable_channel(struct kirin_plane *kplane) } static int ade_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -806,7 +806,7 @@ static int ade_plane_atomic_check(struct drm_plane *plane, } static void ade_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -820,7 +820,7 @@ static void ade_plane_atomic_update(struct drm_plane *plane, } static void ade_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct kirin_plane *kplane = to_kirin_plane(plane); diff --git a/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c b/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c index 7978f8c8108c..1bbb7de5ab49 100644 --- a/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c +++ b/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c @@ -102,7 +102,7 @@ static const uint64_t hyperv_modifiers[] = { }; static void hyperv_crtc_helper_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct hyperv_drm_device *hv = to_hv(crtc->dev); struct drm_plane *plane = &hv->plane; @@ -136,7 +136,7 @@ static const struct drm_crtc_funcs hyperv_crtc_funcs = { }; static int hyperv_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); struct hyperv_drm_device *hv = to_hv(plane->dev); @@ -168,7 +168,7 @@ static int hyperv_plane_atomic_check(struct drm_plane *plane, } static void hyperv_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct hyperv_drm_device *hv = to_hv(plane->dev); struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index 52a3a59b4ba2..028a2c97361d 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -153,7 +153,7 @@ config DRM_I915_TRACE_GTT config DRM_I915_SW_FENCE_DEBUG_OBJECTS bool "Enable additional driver debugging for fence objects" depends on DRM_I915 - select DEBUG_OBJECTS + depends on DEBUG_OBJECTS default n help Choose this option to turn on extra driver debugging that may affect diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index b677720a1c2d..07802a7f4ce5 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -80,6 +80,7 @@ i915-y += \ i915_display_pc8.o \ i915_dpt.o \ i915_dsb_buffer.o \ + i915_fb_pin.o \ i915_hdcp_gsc.o \ i915_initial_plane.o \ i915_overlay.o \ @@ -255,6 +256,7 @@ i915-y += \ display/intel_cursor.o \ display/intel_dbuf_bw.o \ display/intel_de.o \ + display/intel_display_clock_gating.o \ display/intel_display.o \ display/intel_display_conversion.o \ display/intel_display_driver.o \ @@ -279,7 +281,6 @@ i915-y += \ display/intel_drrs.o \ display/intel_dsb.o \ display/intel_fb.o \ - display/intel_fb_pin.o \ display/intel_fbc.o \ display/intel_fdi.o \ display/intel_fifo_underrun.o \ @@ -295,6 +296,7 @@ i915-y += \ display/intel_link_bw.o \ display/intel_load_detect.o \ display/intel_lpe_audio.o \ + display/intel_mchbar.o \ display/intel_modeset_lock.o \ display/intel_modeset_setup.o \ display/intel_modeset_verify.o \ @@ -325,8 +327,7 @@ i915-$(CONFIG_ACPI) += \ display/intel_acpi.o \ display/intel_opregion.o i915-$(CONFIG_DRM_FBDEV_EMULATION) += \ - display/intel_fbdev.o \ - display/intel_fbdev_fb.o + display/intel_fbdev.o i915-$(CONFIG_DEBUG_FS) += \ display/intel_display_debugfs.o \ display/intel_display_debugfs_params.o \ diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c index 5fe5067c4237..380e07d11647 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c @@ -592,7 +592,7 @@ intel_hdmi_hotplug(struct intel_encoder *encoder, } int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct intel_display *display = to_intel_display(connector->dev); struct drm_connector_list_iter conn_iter; diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.h b/drivers/gpu/drm/i915/display/g4x_hdmi.h index 039d2bdba06c..c37f4d218669 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.h +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.h @@ -11,7 +11,7 @@ #include "i915_reg_defs.h" enum port; -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_connector; struct intel_display; @@ -19,7 +19,7 @@ struct intel_display; bool g4x_hdmi_init(struct intel_display *display, i915_reg_t hdmi_reg, enum port port); int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); #else static inline bool g4x_hdmi_init(struct intel_display *display, i915_reg_t hdmi_reg, int port) @@ -27,7 +27,7 @@ static inline bool g4x_hdmi_init(struct intel_display *display, return false; } static inline int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { return 0; } diff --git a/drivers/gpu/drm/i915/display/i9xx_display_sr.c b/drivers/gpu/drm/i915/display/i9xx_display_sr.c index 935419441709..1eb2f636cc65 100644 --- a/drivers/gpu/drm/i915/display/i9xx_display_sr.c +++ b/drivers/gpu/drm/i915/display/i9xx_display_sr.c @@ -4,13 +4,13 @@ */ #include +#include #include "i9xx_display_sr.h" #include "i9xx_wm_regs.h" #include "intel_de.h" #include "intel_display_regs.h" #include "intel_gmbus.h" -#include "intel_pci_config.h" static void i9xx_display_save_swf(struct intel_display *display) { diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 9c16753a1f3b..70734d32a409 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -1240,7 +1240,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fb->width, fb->height, fb->format->cpp[0] * 8, base, fb->pitches[0], plane_config->size); - plane_config->fb = intel_fb; + plane_config->fb = &intel_fb->base; } bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc, diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index 9e170e79dcf6..33d8f6b6afea 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -19,7 +19,7 @@ #include "intel_display_utils.h" #include "intel_dram.h" #include "intel_fb.h" -#include "intel_mchbar_regs.h" +#include "intel_mchbar.h" #include "intel_wm.h" #include "skl_watermark.h" #include "vlv_sideband.h" @@ -118,41 +118,41 @@ static void chv_set_memory_dvfs(struct intel_display *display, bool enable) u32 val; int ret; - vlv_punit_get(display->drm); + vlv_punit_get(display); - val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2); + val = vlv_punit_read(display, PUNIT_REG_DDR_SETUP2); if (enable) val &= ~FORCE_DDR_HIGH_FREQ; else val |= FORCE_DDR_HIGH_FREQ; val &= ~FORCE_DDR_LOW_FREQ; val |= FORCE_DDR_FREQ_REQ_ACK; - vlv_punit_write(display->drm, PUNIT_REG_DDR_SETUP2, val); + vlv_punit_write(display, PUNIT_REG_DDR_SETUP2, val); - ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2), + ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DDR_SETUP2), (val & FORCE_DDR_FREQ_REQ_ACK) == 0, 500, 3000, false); if (ret) drm_err(display->drm, "timed out waiting for Punit DDR DVFS request\n"); - vlv_punit_put(display->drm); + vlv_punit_put(display); } static void chv_set_memory_pm5(struct intel_display *display, bool enable) { u32 val; - vlv_punit_get(display->drm); + vlv_punit_get(display); - val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); + val = vlv_punit_read(display, PUNIT_REG_DSPSSPM); if (enable) val |= DSP_MAXFIFO_PM5_ENABLE; else val &= ~DSP_MAXFIFO_PM5_ENABLE; - vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); + vlv_punit_write(display, PUNIT_REG_DSPSSPM, val); - vlv_punit_put(display->drm); + vlv_punit_put(display); } #define FW_WM(value, plane) \ @@ -2742,12 +2742,11 @@ static void ilk_compute_wm_level(struct intel_display *display, static void hsw_read_wm_latency(struct intel_display *display, u16 wm[]) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); u64 sskpd; display->wm.num_levels = 5; - sskpd = intel_uncore_read64(uncore, MCH_SSKPD); + sskpd = intel_mchbar_read64_2x32(display, MCH_SSKPD); wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd); if (wm[0] == 0) @@ -2760,12 +2759,11 @@ static void hsw_read_wm_latency(struct intel_display *display, u16 wm[]) static void snb_read_wm_latency(struct intel_display *display, u16 wm[]) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 sskpd; display->wm.num_levels = 4; - sskpd = intel_uncore_read(uncore, MCH_SSKPD); + sskpd = intel_mchbar_read(display, MCH_SSKPD); wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd); wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd); @@ -2775,12 +2773,11 @@ static void snb_read_wm_latency(struct intel_display *display, u16 wm[]) static void ilk_read_wm_latency(struct intel_display *display, u16 wm[]) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 mltr; display->wm.num_levels = 3; - mltr = intel_uncore_read(uncore, MLTR_ILK); + mltr = intel_mchbar_read(display, MLTR_ILK); /* ILK primary LP0 latency is 700 ns */ wm[0] = 7; @@ -3534,7 +3531,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc) crtc->wm.active.ilk = *active; } -static int ilk_sanitize_watermarks_add_affected(struct drm_atomic_state *state) +static int ilk_sanitize_watermarks_add_affected(struct drm_atomic_commit *state) { struct drm_plane *plane; struct intel_crtc *crtc; @@ -3578,7 +3575,7 @@ static int ilk_sanitize_watermarks_add_affected(struct drm_atomic_state *state) */ void ilk_wm_sanitize(struct intel_display *display) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct intel_atomic_state *intel_state; struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; @@ -3587,13 +3584,13 @@ void ilk_wm_sanitize(struct intel_display *display) int i; /* Only supported on platforms that use atomic watermark design */ - if (!display->funcs.wm->optimize_watermarks) + if (!display->wm.funcs->optimize_watermarks) return; if (drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 9)) return; - state = drm_atomic_state_alloc(display->drm); + state = drm_atomic_commit_alloc(display->drm); if (drm_WARN_ON(display->drm, !state)) return; @@ -3631,7 +3628,7 @@ void ilk_wm_sanitize(struct intel_display *display) fail: if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); drm_modeset_backoff(&ctx); goto retry; } @@ -3650,7 +3647,7 @@ void ilk_wm_sanitize(struct intel_display *display) drm_WARN(display->drm, ret, "Could not determine valid watermarks for inherited state\n"); - drm_atomic_state_put(state); + drm_atomic_commit_put(state); drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); @@ -3918,9 +3915,9 @@ static void vlv_wm_get_hw_state(struct intel_display *display) wm->level = VLV_WM_LEVEL_PM2; if (display->platform.cherryview) { - vlv_punit_get(display->drm); + vlv_punit_get(display); - val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); + val = vlv_punit_read(display, PUNIT_REG_DSPSSPM); if (val & DSP_MAXFIFO_PM5_ENABLE) wm->level = VLV_WM_LEVEL_PM5; @@ -3933,11 +3930,11 @@ static void vlv_wm_get_hw_state(struct intel_display *display) * HIGH/LOW bits so that we don't actually change * the current state. */ - val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2); + val = vlv_punit_read(display, PUNIT_REG_DDR_SETUP2); val |= FORCE_DDR_FREQ_REQ_ACK; - vlv_punit_write(display->drm, PUNIT_REG_DDR_SETUP2, val); + vlv_punit_write(display, PUNIT_REG_DDR_SETUP2, val); - ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2), + ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DDR_SETUP2), (val & FORCE_DDR_FREQ_REQ_ACK) == 0, 500, 3000, false); if (ret) { @@ -3946,12 +3943,12 @@ static void vlv_wm_get_hw_state(struct intel_display *display) "assuming DDR DVFS is disabled\n"); display->wm.num_levels = VLV_WM_LEVEL_PM5 + 1; } else { - val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2); + val = vlv_punit_read(display, PUNIT_REG_DDR_SETUP2); if ((val & FORCE_DDR_HIGH_FREQ) == 0) wm->level = VLV_WM_LEVEL_DDR_DVFS; } - vlv_punit_put(display->drm); + vlv_punit_put(display); } for_each_intel_crtc(display->drm, crtc) { @@ -4155,34 +4152,34 @@ void i9xx_wm_init(struct intel_display *display) /* For FIFO watermark updates */ if (HAS_PCH_SPLIT(display)) { ilk_setup_wm_latency(display); - display->funcs.wm = &ilk_wm_funcs; + display->wm.funcs = &ilk_wm_funcs; } else if (display->platform.valleyview || display->platform.cherryview) { vlv_setup_wm_latency(display); - display->funcs.wm = &vlv_wm_funcs; + display->wm.funcs = &vlv_wm_funcs; } else if (display->platform.g4x) { g4x_setup_wm_latency(display); - display->funcs.wm = &g4x_wm_funcs; + display->wm.funcs = &g4x_wm_funcs; } else if (display->platform.pineview) { if (!pnv_get_cxsr_latency(display)) { drm_info(display->drm, "Unknown FSB/MEM, disabling CxSR\n"); /* Disable CxSR and never update its watermark again */ intel_set_memory_cxsr(display, false); - display->funcs.wm = &nop_funcs; + display->wm.funcs = &nop_funcs; } else { - display->funcs.wm = &pnv_wm_funcs; + display->wm.funcs = &pnv_wm_funcs; } } else if (DISPLAY_VER(display) == 4) { - display->funcs.wm = &i965_wm_funcs; + display->wm.funcs = &i965_wm_funcs; } else if (DISPLAY_VER(display) == 3) { - display->funcs.wm = &i9xx_wm_funcs; + display->wm.funcs = &i9xx_wm_funcs; } else if (DISPLAY_VER(display) == 2) { if (INTEL_NUM_PIPES(display) == 1) - display->funcs.wm = &i845_wm_funcs; + display->wm.funcs = &i845_wm_funcs; else - display->funcs.wm = &i9xx_wm_funcs; + display->wm.funcs = &i9xx_wm_funcs; } else { drm_err(display->drm, "unexpected fall-through in %s\n", __func__); - display->funcs.wm = &nop_funcs; + display->wm.funcs = &nop_funcs; } } diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index 71b7325917b6..38bbd6964d8e 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -112,7 +112,7 @@ int intel_digital_connector_atomic_set_property(struct drm_connector *connector, } int intel_digital_connector_atomic_check(struct drm_connector *conn, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *new_state = drm_atomic_get_new_connector_state(state, conn); @@ -320,12 +320,12 @@ intel_crtc_destroy_state(struct drm_crtc *crtc, kfree(crtc_state); } -struct drm_atomic_state * +struct drm_atomic_commit * intel_atomic_state_alloc(struct drm_device *dev) { struct intel_atomic_state *state = kzalloc_obj(*state); - if (!state || drm_atomic_state_init(dev, &state->base) < 0) { + if (!state || drm_atomic_commit_init(dev, &state->base) < 0) { kfree(state); return NULL; } @@ -333,20 +333,20 @@ intel_atomic_state_alloc(struct drm_device *dev) return &state->base; } -void intel_atomic_state_free(struct drm_atomic_state *_state) +void intel_atomic_state_free(struct drm_atomic_commit *_state) { struct intel_atomic_state *state = to_intel_atomic_state(_state); - drm_atomic_state_default_release(&state->base); + drm_atomic_commit_default_release(&state->base); kfree(state->global_objs); kfree(state); } -void intel_atomic_state_clear(struct drm_atomic_state *s) +void intel_atomic_state_clear(struct drm_atomic_commit *s) { struct intel_atomic_state *state = to_intel_atomic_state(s); - drm_atomic_state_default_clear(&state->base); + drm_atomic_commit_default_clear(&state->base); intel_atomic_clear_global_state(state); /* state->internal not reset on purpose */ @@ -357,7 +357,7 @@ void intel_atomic_state_clear(struct drm_atomic_state *s) } struct intel_crtc_state * -intel_atomic_get_crtc_state(struct drm_atomic_state *state, +intel_atomic_get_crtc_state(struct drm_atomic_commit *state, struct intel_crtc *crtc) { struct drm_crtc_state *crtc_state; diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h index a5a7e2906ba8..4dc5205a4733 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.h +++ b/drivers/gpu/drm/i915/display/intel_atomic.h @@ -8,7 +8,7 @@ #include -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_connector; struct drm_connector_state; struct drm_crtc; @@ -29,7 +29,7 @@ int intel_digital_connector_atomic_set_property(struct drm_connector *connector, struct drm_property *property, u64 val); int intel_digital_connector_atomic_check(struct drm_connector *conn, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); struct drm_connector_state * intel_digital_connector_duplicate_state(struct drm_connector *connector); bool intel_connector_needs_modeset(struct intel_atomic_state *state, @@ -43,12 +43,12 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); void intel_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state); void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state); -struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); -void intel_atomic_state_free(struct drm_atomic_state *state); -void intel_atomic_state_clear(struct drm_atomic_state *state); +struct drm_atomic_commit *intel_atomic_state_alloc(struct drm_device *dev); +void intel_atomic_state_free(struct drm_atomic_commit *state); +void intel_atomic_state_clear(struct drm_atomic_commit *state); struct intel_crtc_state * -intel_atomic_get_crtc_state(struct drm_atomic_state *state, +intel_atomic_get_crtc_state(struct drm_atomic_commit *state, struct intel_crtc *crtc); #endif /* __INTEL_ATOMIC_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index 081627e0d917..0810facb80e1 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -754,10 +754,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder, crtc->base.base.id, crtc->base.name, drm_eld_size(crtc_state->eld)); - if (display->funcs.audio) - display->funcs.audio->audio_codec_enable(encoder, - crtc_state, - conn_state); + if (display->audio.funcs) + display->audio.funcs->audio_codec_enable(encoder, crtc_state, conn_state); mutex_lock(&display->audio.mutex); @@ -813,10 +811,8 @@ void intel_audio_codec_disable(struct intel_encoder *encoder, encoder->base.base.id, encoder->base.name, crtc->base.base.id, crtc->base.name); - if (display->funcs.audio) - display->funcs.audio->audio_codec_disable(encoder, - old_crtc_state, - old_conn_state); + if (display->audio.funcs) + display->audio.funcs->audio_codec_disable(encoder, old_crtc_state, old_conn_state); mutex_lock(&display->audio.mutex); @@ -864,8 +860,8 @@ void intel_audio_codec_get_config(struct intel_encoder *encoder, if (!crtc_state->has_audio) return; - if (display->funcs.audio) - display->funcs.audio->audio_codec_get_config(encoder, crtc_state); + if (display->audio.funcs) + display->audio.funcs->audio_codec_get_config(encoder, crtc_state); } static const struct intel_audio_funcs g4x_audio_funcs = { @@ -893,12 +889,12 @@ static const struct intel_audio_funcs hsw_audio_funcs = { void intel_audio_hooks_init(struct intel_display *display) { if (display->platform.g4x) - display->funcs.audio = &g4x_audio_funcs; + display->audio.funcs = &g4x_audio_funcs; else if (display->platform.valleyview || display->platform.cherryview || HAS_PCH_CPT(display) || HAS_PCH_IBX(display)) - display->funcs.audio = &ibx_audio_funcs; + display->audio.funcs = &ibx_audio_funcs; else if (display->platform.haswell || DISPLAY_VER(display) >= 8) - display->funcs.audio = &hsw_audio_funcs; + display->audio.funcs = &hsw_audio_funcs; } struct aud_ts_cdclk_m_n { @@ -958,7 +954,7 @@ static void glk_force_audio_cdclk(struct intel_display *display, bool enable) { struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct intel_crtc *crtc; int ret; @@ -967,7 +963,7 @@ static void glk_force_audio_cdclk(struct intel_display *display, return; drm_modeset_acquire_init(&ctx, 0); - state = drm_atomic_state_alloc(display->drm); + state = drm_atomic_commit_alloc(display->drm); if (drm_WARN_ON(display->drm, !state)) return; @@ -978,14 +974,14 @@ static void glk_force_audio_cdclk(struct intel_display *display, ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc, enable); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); drm_modeset_backoff(&ctx); goto retry; } drm_WARN_ON(display->drm, ret); - drm_atomic_state_put(state); + drm_atomic_commit_put(state); drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c index 34e95f05936e..b128896cb1c2 100644 --- a/drivers/gpu/drm/i915/display/intel_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_backlight.c @@ -11,6 +11,7 @@ #include #include +#include #include "intel_backlight.h" #include "intel_backlight_regs.h" @@ -23,7 +24,6 @@ #include "intel_dp_aux_backlight.h" #include "intel_dsi_dcs_backlight.h" #include "intel_panel.h" -#include "intel_pci_config.h" #include "intel_pps.h" #include "intel_quirks.h" diff --git a/drivers/gpu/drm/i915/display/intel_bo.c b/drivers/gpu/drm/i915/display/intel_bo.c index 3b82d38a0504..8ecdbb7e39f3 100644 --- a/drivers/gpu/drm/i915/display/intel_bo.c +++ b/drivers/gpu/drm/i915/display/intel_bo.c @@ -85,3 +85,30 @@ struct drm_gem_object *intel_bo_framebuffer_lookup(struct intel_display *display { return display->parent->bo->framebuffer_lookup(display->drm, filp, user_mode_cmd); } + +#if IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION) +u32 intel_bo_fbdev_pitch_align(struct intel_display *display, u32 stride) +{ + return display->parent->bo->fbdev_pitch_align(stride); +} + +struct drm_gem_object *intel_bo_fbdev_create(struct intel_display *display, int size) +{ + return display->parent->bo->fbdev_create(display->drm, size); +} + +void intel_bo_fbdev_destroy(struct drm_gem_object *obj) +{ + struct intel_display *display = to_intel_display(obj->dev); + + display->parent->bo->fbdev_destroy(obj); +} + +int intel_bo_fbdev_fill_info(struct drm_gem_object *obj, struct fb_info *info, + struct i915_vma *vma) +{ + struct intel_display *display = to_intel_display(obj->dev); + + return display->parent->bo->fbdev_fill_info(obj, info, vma); +} +#endif diff --git a/drivers/gpu/drm/i915/display/intel_bo.h b/drivers/gpu/drm/i915/display/intel_bo.h index aec188c706c2..348f7fa66960 100644 --- a/drivers/gpu/drm/i915/display/intel_bo.h +++ b/drivers/gpu/drm/i915/display/intel_bo.h @@ -10,6 +10,8 @@ struct drm_file; struct drm_gem_object; struct drm_mode_fb_cmd2; struct drm_scanout_buffer; +struct fb_info; +struct i915_vma; struct intel_display; struct intel_framebuffer; struct seq_file; @@ -31,4 +33,10 @@ struct drm_gem_object *intel_bo_framebuffer_lookup(struct intel_display *display struct drm_file *filp, const struct drm_mode_fb_cmd2 *user_mode_cmd); +u32 intel_bo_fbdev_pitch_align(struct intel_display *display, u32 stride); +struct drm_gem_object *intel_bo_fbdev_create(struct intel_display *display, int size); +void intel_bo_fbdev_destroy(struct drm_gem_object *obj); +int intel_bo_fbdev_fill_info(struct drm_gem_object *obj, struct fb_info *info, + struct i915_vma *vma); + #endif /* __INTEL_BO__ */ diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 07b4531a4376..9c3a9bbb49f6 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -9,14 +9,14 @@ #include "intel_bw.h" #include "intel_crtc.h" +#include "intel_de.h" #include "intel_display_core.h" #include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_display_utils.h" #include "intel_dram.h" -#include "intel_mchbar_regs.h" +#include "intel_mchbar.h" #include "intel_parent.h" -#include "intel_uncore.h" #include "skl_watermark.h" struct intel_bw_state { @@ -28,9 +28,6 @@ struct intel_bw_state { */ u8 pipe_sagv_reject; - /* bitmask of active pipes */ - u8 active_pipes; - /* * From MTL onwards, to lock a QGV point, punit expects the peak BW of * the selected QGV point as the parameter in multiples of 100MB/s @@ -74,11 +71,10 @@ static int dg1_mchbar_read_qgv_point_info(struct intel_display *display, struct intel_qgv_point *sp, int point) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 dclk_ratio, dclk_reference; u32 val; - val = intel_uncore_read(uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC); + val = intel_mchbar_read(display, SA_PERF_STATUS_0_0_0_MCHBAR_PC); dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val); if (val & DG1_QCLK_REFERENCE) dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */ @@ -86,18 +82,18 @@ static int dg1_mchbar_read_qgv_point_info(struct intel_display *display, dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */ sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000); - val = intel_uncore_read(uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); + val = intel_mchbar_read(display, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); if (val & DG1_GEAR_TYPE) sp->dclk *= 2; if (sp->dclk == 0) return -EINVAL; - val = intel_uncore_read(uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR); + val = intel_mchbar_read(display, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR); sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val); sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val); - val = intel_uncore_read(uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH); + val = intel_mchbar_read(display, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH); sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val); sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val); @@ -211,12 +207,11 @@ static int icl_pcode_restrict_qgv_points(struct intel_display *display, static int mtl_read_qgv_point_info(struct intel_display *display, struct intel_qgv_point *sp, int point) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 val, val2; u16 dclk; - val = intel_uncore_read(uncore, MTL_MEM_SS_INFO_QGV_POINT_LOW(point)); - val2 = intel_uncore_read(uncore, MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); + val = intel_de_read(display, MTL_MEM_SS_INFO_QGV_POINT_LOW(point)); + val2 = intel_de_read(display, MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000); sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); @@ -1265,31 +1260,6 @@ static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *chan return 0; } -static int intel_bw_modeset_checks(struct intel_atomic_state *state) -{ - const struct intel_bw_state *old_bw_state; - struct intel_bw_state *new_bw_state; - int ret; - - if (!intel_any_crtc_active_changed(state)) - return 0; - - new_bw_state = intel_atomic_get_bw_state(state); - if (IS_ERR(new_bw_state)) - return PTR_ERR(new_bw_state); - - old_bw_state = intel_atomic_get_old_bw_state(state); - - new_bw_state->active_pipes = - intel_calc_active_pipes(state, old_bw_state->active_pipes); - - ret = intel_atomic_lock_global_state(&new_bw_state->base); - if (ret) - return ret; - - return 0; -} - static int intel_bw_check_sagv_mask(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); @@ -1346,10 +1316,6 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) if (DISPLAY_VER(display) < 9) return 0; - ret = intel_bw_modeset_checks(state); - if (ret) - return ret; - ret = intel_bw_check_sagv_mask(state); if (ret) return ret; @@ -1410,7 +1376,6 @@ void intel_bw_update_hw_state(struct intel_display *display) if (DISPLAY_VER(display) < 9) return; - bw_state->active_pipes = 0; bw_state->pipe_sagv_reject = 0; for_each_intel_crtc(display->drm, crtc) { @@ -1418,9 +1383,6 @@ void intel_bw_update_hw_state(struct intel_display *display) to_intel_crtc_state(crtc->base.state); enum pipe pipe = crtc->pipe; - if (crtc_state->hw.active) - bw_state->active_pipes |= BIT(pipe); - if (DISPLAY_VER(display) >= 11) intel_bw_crtc_update(bw_state, crtc_state); @@ -1504,10 +1466,6 @@ bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state) bool intel_bw_can_enable_sagv(struct intel_display *display, const struct intel_bw_state *bw_state) { - if (DISPLAY_VER(display) < 11 && - bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes)) - return false; - return bw_state->pipe_sagv_reject == 0; } diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c index b167af31de5b..c2d2746c5f04 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.c +++ b/drivers/gpu/drm/i915/display/intel_casf.c @@ -61,10 +61,10 @@ const u16 filtercoeff_3[] = { FILTER_COEFF_0_125, }; -static void intel_casf_filter_lut_load(struct intel_crtc *crtc, - const struct intel_crtc_state *crtc_state) +static void intel_casf_filter_lut_load(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); int i; intel_de_write(display, SHRPLUT_INDEX(crtc->pipe), @@ -75,53 +75,35 @@ static void intel_casf_filter_lut_load(struct intel_crtc *crtc, sharpness_lut[i]); } -void intel_casf_update_strength(struct intel_crtc_state *crtc_state) -{ - struct intel_display *display = to_intel_display(crtc_state); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - int win_size; - - intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), FILTER_STRENGTH_MASK, - FILTER_STRENGTH(crtc_state->hw.casf_params.strength)); - - win_size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, 1)); - - intel_de_write_fw(display, SKL_PS_WIN_SZ(crtc->pipe, 1), win_size); -} - static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state) { const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode; u32 total_pixels = mode->hdisplay * mode->vdisplay; if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER) - crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3; + crtc_state->pch_pfit.casf.win_size = SHARPNESS_FILTER_SIZE_3X3; else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER) - crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5; + crtc_state->pch_pfit.casf.win_size = SHARPNESS_FILTER_SIZE_5X5; else - crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7; + crtc_state->pch_pfit.casf.win_size = SHARPNESS_FILTER_SIZE_7X7; } +static void intel_casf_scaler_compute_coef(struct intel_crtc_state *crtc_state); + int intel_casf_compute_config(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - if (!HAS_CASF(display)) + if (crtc_state->hw.sharpness_strength == 0) return 0; - if (crtc_state->uapi.sharpness_strength == 0) { - crtc_state->hw.casf_params.casf_enable = false; - crtc_state->hw.casf_params.strength = 0; - return 0; - } - /* CASF with joiner not supported in hardware */ if (crtc_state->joiner_pipes) { drm_dbg_kms(display->drm, "CASF not supported with joiner\n"); return -EINVAL; } - crtc_state->hw.casf_params.casf_enable = true; + crtc_state->pch_pfit.casf.enable = true; /* * HW takes a value in form (1.0 + strength) in 4.4 fixed format. @@ -131,12 +113,12 @@ int intel_casf_compute_config(struct intel_crtc_state *crtc_state) * 6.3125 in 4.4 format is b01100101 which is equal to 101. * Also 85 + 16 = 101. */ - crtc_state->hw.casf_params.strength = - min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10; + crtc_state->pch_pfit.casf.strength = + min(crtc_state->hw.sharpness_strength, 0xEF) + 0x10; intel_casf_compute_win_size(crtc_state); - intel_casf_scaler_compute_config(crtc_state); + intel_casf_scaler_compute_coef(crtc_state); return 0; } @@ -151,35 +133,27 @@ void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state) if (sharp & FILTER_EN) { if (drm_WARN_ON(display->drm, REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16)) - crtc_state->hw.casf_params.strength = 0; + crtc_state->pch_pfit.casf.strength = 0; else - crtc_state->hw.casf_params.strength = + crtc_state->pch_pfit.casf.strength = REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp); - crtc_state->hw.casf_params.casf_enable = true; - crtc_state->hw.casf_params.win_size = + crtc_state->pch_pfit.casf.enable = true; + crtc_state->pch_pfit.casf.win_size = REG_FIELD_GET(FILTER_SIZE_MASK, sharp); } } -bool intel_casf_needs_scaler(const struct intel_crtc_state *crtc_state) -{ - if (crtc_state->hw.casf_params.casf_enable) - return true; - - return false; -} - static int casf_coeff_tap(int i) { return i % SCALER_FILTER_NUM_TAPS; } -static u32 casf_coeff(struct intel_crtc_state *crtc_state, int t) +static u32 casf_coeff(const struct intel_crtc_state *crtc_state, int t) { struct scaler_filter_coeff value; u32 coeff; - value = crtc_state->hw.casf_params.coeff[t]; + value = crtc_state->pch_pfit.casf.coeff[t]; value.sign = 0; coeff = value.sign << 15 | value.exp << 12 | value.mantissa << 3; @@ -189,10 +163,10 @@ static u32 casf_coeff(struct intel_crtc_state *crtc_state, int t) /* * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set. * To enable casf: program scaler coefficients with the coeffients - * that are calculated and stored in hw.casf_params.coeff as per + * that are calculated and stored in pch_pfit.casf.coeff as per * SCALER_COEFFICIENT_FORMAT */ -static void intel_casf_write_coeff(struct intel_crtc_state *crtc_state) +static void intel_casf_write_coeff(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -240,16 +214,16 @@ static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff, } } -void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state) +static void intel_casf_scaler_compute_coef(struct intel_crtc_state *crtc_state) { const u16 *filtercoeff; u16 filter_coeff[SCALER_FILTER_NUM_TAPS]; u16 sumcoeff = 0; int i; - if (crtc_state->hw.casf_params.win_size == 0) + if (crtc_state->pch_pfit.casf.win_size == 0) filtercoeff = filtercoeff_1; - else if (crtc_state->hw.casf_params.win_size == 1) + else if (crtc_state->pch_pfit.casf.win_size == 1) filtercoeff = filtercoeff_2; else filtercoeff = filtercoeff_3; @@ -259,37 +233,13 @@ void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state) for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++) { filter_coeff[i] = (*(filtercoeff + i) * 100 / sumcoeff); - convert_sharpness_coef_binary(&crtc_state->hw.casf_params.coeff[i], + convert_sharpness_coef_binary(&crtc_state->pch_pfit.casf.coeff[i], filter_coeff[i]); } } -void intel_casf_enable(struct intel_crtc_state *crtc_state) +void intel_casf_setup(const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(crtc_state); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - u32 sharpness_ctl; - - intel_casf_filter_lut_load(crtc, crtc_state); - + intel_casf_filter_lut_load(crtc_state); intel_casf_write_coeff(crtc_state); - - sharpness_ctl = FILTER_EN | FILTER_STRENGTH(crtc_state->hw.casf_params.strength); - - sharpness_ctl |= crtc_state->hw.casf_params.win_size; - - intel_de_write(display, SHARPNESS_CTL(crtc->pipe), sharpness_ctl); - - skl_scaler_setup_casf(crtc_state); -} - -void intel_casf_disable(const struct intel_crtc_state *crtc_state) -{ - struct intel_display *display = to_intel_display(crtc_state); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - - intel_de_write(display, SKL_PS_CTRL(crtc->pipe, 1), 0); - intel_de_write(display, SKL_PS_WIN_POS(crtc->pipe, 1), 0); - intel_de_write(display, SHARPNESS_CTL(crtc->pipe), 0); - intel_de_write(display, SKL_PS_WIN_SZ(crtc->pipe, 1), 0); } diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h index b3fb0bcb3f5b..3ebb7522af0a 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.h +++ b/drivers/gpu/drm/i915/display/intel_casf.h @@ -11,11 +11,7 @@ struct intel_crtc_state; int intel_casf_compute_config(struct intel_crtc_state *crtc_state); -void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state); void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state); -void intel_casf_enable(struct intel_crtc_state *crtc_state); -void intel_casf_disable(const struct intel_crtc_state *crtc_state); -void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state); -bool intel_casf_needs_scaler(const struct intel_crtc_state *crtc_state); +void intel_casf_setup(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_CASF_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index a47736613f6e..a1bf01021d65 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -28,6 +28,8 @@ #include #include #include +#include +#include #include "hsw_ips.h" #include "intel_atomic.h" @@ -41,12 +43,10 @@ #include "intel_display_utils.h" #include "intel_display_wa.h" #include "intel_dram.h" -#include "intel_mchbar_regs.h" +#include "intel_mchbar.h" #include "intel_parent.h" -#include "intel_pci_config.h" #include "intel_plane.h" #include "intel_psr.h" -#include "intel_step.h" #include "intel_vdsc.h" #include "skl_watermark.h" #include "skl_watermark_regs.h" @@ -170,27 +170,27 @@ struct intel_cdclk_funcs { void intel_cdclk_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { - display->funcs.cdclk->get_cdclk(display, cdclk_config); + display->cdclk.funcs->get_cdclk(display, cdclk_config); } static void intel_cdclk_set_cdclk(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); + display->cdclk.funcs->set_cdclk(display, cdclk_config, pipe); } static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); - return display->funcs.cdclk->modeset_calc_cdclk(state); + return display->cdclk.funcs->modeset_calc_cdclk(state); } static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, int cdclk) { - return display->funcs.cdclk->calc_voltage_level(cdclk); + return display->cdclk.funcs->calc_voltage_level(cdclk); } static void fixed_133mhz_get_cdclk(struct intel_display *display, @@ -376,8 +376,8 @@ static unsigned int intel_hpll_vco(struct intel_display *display) else return 0; - tmp = intel_de_read(display, display->platform.pineview || - display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO); + tmp = intel_mchbar_read(display, display->platform.pineview || + display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO); vco = vco_table[tmp & 0x7]; if (vco == 0) @@ -613,9 +613,9 @@ static void vlv_get_cdclk(struct intel_display *display, cdclk_config->vco = vlv_clock_get_hpll_vco(display->drm); cdclk_config->cdclk = vlv_clock_get_cdclk(display->drm); - vlv_punit_get(display->drm); - val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); - vlv_punit_put(display->drm); + vlv_punit_get(display); + val = vlv_punit_read(display, PUNIT_REG_DSPSSPM); + vlv_punit_put(display); if (display->platform.valleyview) cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> @@ -691,17 +691,17 @@ static void vlv_set_cdclk(struct intel_display *display, */ wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); - vlv_iosf_sb_get(display->drm, - BIT(VLV_IOSF_SB_CCK) | - BIT(VLV_IOSF_SB_BUNIT) | - BIT(VLV_IOSF_SB_PUNIT)); + intel_parent_vlv_iosf_get(display, + BIT(VLV_IOSF_SB_CCK) | + BIT(VLV_IOSF_SB_BUNIT) | + BIT(VLV_IOSF_SB_PUNIT)); - val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); + val = vlv_punit_read(display, PUNIT_REG_DSPSSPM); val &= ~DSPFREQGUAR_MASK; val |= (cmd << DSPFREQGUAR_SHIFT); - vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); + vlv_punit_write(display, PUNIT_REG_DSPSSPM, val); - ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM), + ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DSPSSPM), (val & DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 500, 50 * 1000, false); if (ret) @@ -714,12 +714,12 @@ static void vlv_set_cdclk(struct intel_display *display, cdclk) - 1; /* adjust cdclk divider */ - val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL); + val = vlv_cck_read(display, CCK_DISPLAY_CLOCK_CONTROL); val &= ~CCK_FREQUENCY_VALUES; val |= divider; - vlv_cck_write(display->drm, CCK_DISPLAY_CLOCK_CONTROL, val); + vlv_cck_write(display, CCK_DISPLAY_CLOCK_CONTROL, val); - ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL), + ret = poll_timeout_us(val = vlv_cck_read(display, CCK_DISPLAY_CLOCK_CONTROL), (val & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 500, 50 * 1000, false); if (ret) @@ -727,7 +727,7 @@ static void vlv_set_cdclk(struct intel_display *display, } /* adjust self-refresh exit latency value */ - val = vlv_bunit_read(display->drm, BUNIT_REG_BISOC); + val = vlv_bunit_read(display, BUNIT_REG_BISOC); val &= ~0x7f; /* @@ -738,12 +738,12 @@ static void vlv_set_cdclk(struct intel_display *display, val |= 4500 / 250; /* 4.5 usec */ else val |= 3000 / 250; /* 3.0 usec */ - vlv_bunit_write(display->drm, BUNIT_REG_BISOC, val); + vlv_bunit_write(display, BUNIT_REG_BISOC, val); - vlv_iosf_sb_put(display->drm, - BIT(VLV_IOSF_SB_CCK) | - BIT(VLV_IOSF_SB_BUNIT) | - BIT(VLV_IOSF_SB_PUNIT)); + intel_parent_vlv_iosf_put(display, + BIT(VLV_IOSF_SB_CCK) | + BIT(VLV_IOSF_SB_BUNIT) | + BIT(VLV_IOSF_SB_PUNIT)); intel_update_cdclk(display); @@ -780,19 +780,19 @@ static void chv_set_cdclk(struct intel_display *display, */ wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); - vlv_punit_get(display->drm); - val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); + vlv_punit_get(display); + val = vlv_punit_read(display, PUNIT_REG_DSPSSPM); val &= ~DSPFREQGUAR_MASK_CHV; val |= (cmd << DSPFREQGUAR_SHIFT_CHV); - vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); + vlv_punit_write(display, PUNIT_REG_DSPSSPM, val); - ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM), + ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DSPSSPM), (val & DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 500, 50 * 1000, false); if (ret) drm_err(display->drm, "timed out waiting for CDCLK change\n"); - vlv_punit_put(display->drm); + vlv_punit_put(display); intel_update_cdclk(display); @@ -2619,7 +2619,7 @@ static void intel_set_cdclk(struct intel_display *display, if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) return; - if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) + if (drm_WARN_ON_ONCE(display->drm, !display->cdclk.funcs->set_cdclk)) return; intel_cdclk_dump_config(display, cdclk_config, context); @@ -4042,100 +4042,100 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = { void intel_init_cdclk_hooks(struct intel_display *display) { if (DISPLAY_VER(display) >= 35) { - display->funcs.cdclk = &xe3lpd_cdclk_funcs; + display->cdclk.funcs = &xe3lpd_cdclk_funcs; display->cdclk.table = xe3p_lpd_cdclk_table; } else if (DISPLAY_VER(display) >= 30) { - display->funcs.cdclk = &xe3lpd_cdclk_funcs; + display->cdclk.funcs = &xe3lpd_cdclk_funcs; display->cdclk.table = xe3lpd_cdclk_table; } else if (DISPLAY_VER(display) >= 20) { - display->funcs.cdclk = &rplu_cdclk_funcs; + display->cdclk.funcs = &rplu_cdclk_funcs; display->cdclk.table = xe2lpd_cdclk_table; } else if (DISPLAY_VERx100(display) >= 1401) { - display->funcs.cdclk = &rplu_cdclk_funcs; + display->cdclk.funcs = &rplu_cdclk_funcs; display->cdclk.table = xe2hpd_cdclk_table; } else if (DISPLAY_VER(display) >= 14) { - display->funcs.cdclk = &rplu_cdclk_funcs; + display->cdclk.funcs = &rplu_cdclk_funcs; display->cdclk.table = mtl_cdclk_table; } else if (display->platform.dg2) { - display->funcs.cdclk = &tgl_cdclk_funcs; + display->cdclk.funcs = &tgl_cdclk_funcs; display->cdclk.table = dg2_cdclk_table; } else if (display->platform.alderlake_p) { /* Wa_22011320316:adl-p[a0] */ if (intel_display_wa(display, INTEL_DISPLAY_WA_22011320316)) { display->cdclk.table = adlp_a_step_cdclk_table; - display->funcs.cdclk = &tgl_cdclk_funcs; + display->cdclk.funcs = &tgl_cdclk_funcs; } else if (display->platform.alderlake_p_raptorlake_u) { display->cdclk.table = rplu_cdclk_table; - display->funcs.cdclk = &rplu_cdclk_funcs; + display->cdclk.funcs = &rplu_cdclk_funcs; } else { display->cdclk.table = adlp_cdclk_table; - display->funcs.cdclk = &tgl_cdclk_funcs; + display->cdclk.funcs = &tgl_cdclk_funcs; } } else if (display->platform.rocketlake) { - display->funcs.cdclk = &tgl_cdclk_funcs; + display->cdclk.funcs = &tgl_cdclk_funcs; display->cdclk.table = rkl_cdclk_table; } else if (DISPLAY_VER(display) >= 12) { - display->funcs.cdclk = &tgl_cdclk_funcs; + display->cdclk.funcs = &tgl_cdclk_funcs; display->cdclk.table = icl_cdclk_table; } else if (display->platform.jasperlake || display->platform.elkhartlake) { - display->funcs.cdclk = &ehl_cdclk_funcs; + display->cdclk.funcs = &ehl_cdclk_funcs; display->cdclk.table = icl_cdclk_table; } else if (DISPLAY_VER(display) >= 11) { - display->funcs.cdclk = &icl_cdclk_funcs; + display->cdclk.funcs = &icl_cdclk_funcs; display->cdclk.table = icl_cdclk_table; } else if (display->platform.geminilake || display->platform.broxton) { - display->funcs.cdclk = &bxt_cdclk_funcs; + display->cdclk.funcs = &bxt_cdclk_funcs; if (display->platform.geminilake) display->cdclk.table = glk_cdclk_table; else display->cdclk.table = bxt_cdclk_table; } else if (DISPLAY_VER(display) == 9) { - display->funcs.cdclk = &skl_cdclk_funcs; + display->cdclk.funcs = &skl_cdclk_funcs; } else if (display->platform.broadwell) { - display->funcs.cdclk = &bdw_cdclk_funcs; + display->cdclk.funcs = &bdw_cdclk_funcs; } else if (display->platform.haswell) { - display->funcs.cdclk = &hsw_cdclk_funcs; + display->cdclk.funcs = &hsw_cdclk_funcs; } else if (display->platform.cherryview) { - display->funcs.cdclk = &chv_cdclk_funcs; + display->cdclk.funcs = &chv_cdclk_funcs; } else if (display->platform.valleyview) { - display->funcs.cdclk = &vlv_cdclk_funcs; + display->cdclk.funcs = &vlv_cdclk_funcs; } else if (display->platform.sandybridge || display->platform.ivybridge) { - display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; + display->cdclk.funcs = &fixed_400mhz_cdclk_funcs; } else if (display->platform.ironlake) { - display->funcs.cdclk = &ilk_cdclk_funcs; + display->cdclk.funcs = &ilk_cdclk_funcs; } else if (display->platform.gm45) { - display->funcs.cdclk = &gm45_cdclk_funcs; + display->cdclk.funcs = &gm45_cdclk_funcs; } else if (display->platform.g45) { - display->funcs.cdclk = &g33_cdclk_funcs; + display->cdclk.funcs = &g33_cdclk_funcs; } else if (display->platform.i965gm) { - display->funcs.cdclk = &i965gm_cdclk_funcs; + display->cdclk.funcs = &i965gm_cdclk_funcs; } else if (display->platform.i965g) { - display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; + display->cdclk.funcs = &fixed_400mhz_cdclk_funcs; } else if (display->platform.pineview) { - display->funcs.cdclk = &pnv_cdclk_funcs; + display->cdclk.funcs = &pnv_cdclk_funcs; } else if (display->platform.g33) { - display->funcs.cdclk = &g33_cdclk_funcs; + display->cdclk.funcs = &g33_cdclk_funcs; } else if (display->platform.i945gm) { - display->funcs.cdclk = &i945gm_cdclk_funcs; + display->cdclk.funcs = &i945gm_cdclk_funcs; } else if (display->platform.i945g) { - display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; + display->cdclk.funcs = &fixed_400mhz_cdclk_funcs; } else if (display->platform.i915gm) { - display->funcs.cdclk = &i915gm_cdclk_funcs; + display->cdclk.funcs = &i915gm_cdclk_funcs; } else if (display->platform.i915g) { - display->funcs.cdclk = &i915g_cdclk_funcs; + display->cdclk.funcs = &i915g_cdclk_funcs; } else if (display->platform.i865g) { - display->funcs.cdclk = &i865g_cdclk_funcs; + display->cdclk.funcs = &i865g_cdclk_funcs; } else if (display->platform.i85x) { - display->funcs.cdclk = &i85x_cdclk_funcs; + display->cdclk.funcs = &i85x_cdclk_funcs; } else if (display->platform.i845g) { - display->funcs.cdclk = &i845g_cdclk_funcs; + display->cdclk.funcs = &i845g_cdclk_funcs; } else if (display->platform.i830) { - display->funcs.cdclk = &i830_cdclk_funcs; + display->cdclk.funcs = &i830_cdclk_funcs; } - if (drm_WARN(display->drm, !display->funcs.cdclk, + if (drm_WARN(display->drm, !display->cdclk.funcs, "Unknown platform. Assuming i830\n")) - display->funcs.cdclk = &i830_cdclk_funcs; + display->cdclk.funcs = &i830_cdclk_funcs; } int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index e7950655434b..0531c60e5e5d 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1933,7 +1933,7 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state) if (crtc_state->dsb_color) return; - display->funcs.color->load_luts(crtc_state); + display->color.funcs->load_luts(crtc_state); } void intel_color_commit_noarm(struct intel_dsb *dsb, @@ -1941,8 +1941,8 @@ void intel_color_commit_noarm(struct intel_dsb *dsb, { struct intel_display *display = to_intel_display(crtc_state); - if (display->funcs.color->color_commit_noarm) - display->funcs.color->color_commit_noarm(dsb, crtc_state); + if (display->color.funcs->color_commit_noarm) + display->color.funcs->color_commit_noarm(dsb, crtc_state); } void intel_color_commit_arm(struct intel_dsb *dsb, @@ -1950,15 +1950,15 @@ void intel_color_commit_arm(struct intel_dsb *dsb, { struct intel_display *display = to_intel_display(crtc_state); - display->funcs.color->color_commit_arm(dsb, crtc_state); + display->color.funcs->color_commit_arm(dsb, crtc_state); } void intel_color_post_update(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - if (display->funcs.color->color_post_update) - display->funcs.color->color_post_update(crtc_state); + if (display->color.funcs->color_post_update) + display->color.funcs->color_post_update(crtc_state); } void intel_color_modeset(const struct intel_crtc_state *crtc_state) @@ -2022,7 +2022,7 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, if (!intel_color_uses_dsb(crtc_state)) return; - display->funcs.color->load_luts(crtc_state); + display->color.funcs->load_luts(crtc_state); if (crtc_state->use_dsb && intel_color_uses_chained_dsb(crtc_state)) { intel_vrr_send_push(crtc_state->dsb_color, crtc_state); @@ -2113,19 +2113,19 @@ int intel_color_check(struct intel_atomic_state *state, if (!intel_crtc_needs_color_update(new_crtc_state)) return 0; - return display->funcs.color->color_check(state, crtc); + return display->color.funcs->color_check(state, crtc); } void intel_color_get_config(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - display->funcs.color->get_config(crtc_state); + display->color.funcs->get_config(crtc_state); - display->funcs.color->read_luts(crtc_state); + display->color.funcs->read_luts(crtc_state); - if (display->funcs.color->read_csc) - display->funcs.color->read_csc(crtc_state); + if (display->color.funcs->read_csc) + display->color.funcs->read_csc(crtc_state); } bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state, @@ -2142,7 +2142,7 @@ bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state, if (!is_pre_csc_lut && crtc_state->c8_planes) return true; - return display->funcs.color->lut_equal(crtc_state, blob1, blob2, + return display->color.funcs->lut_equal(crtc_state, blob1, blob2, is_pre_csc_lut); } @@ -4253,8 +4253,8 @@ intel_color_load_plane_csc_matrix(struct intel_dsb *dsb, { struct intel_display *display = to_intel_display(plane_state); - if (display->funcs.color->load_plane_csc_matrix) - display->funcs.color->load_plane_csc_matrix(dsb, plane_state); + if (display->color.funcs->load_plane_csc_matrix) + display->color.funcs->load_plane_csc_matrix(dsb, plane_state); } static void @@ -4263,8 +4263,8 @@ intel_color_load_plane_luts(struct intel_dsb *dsb, { struct intel_display *display = to_intel_display(plane_state); - if (display->funcs.color->load_plane_luts) - display->funcs.color->load_plane_luts(dsb, plane_state); + if (display->color.funcs->load_plane_luts) + display->color.funcs->load_plane_luts(dsb, plane_state); } bool @@ -4346,29 +4346,29 @@ void intel_color_init_hooks(struct intel_display *display) { if (HAS_GMCH(display)) { if (display->platform.cherryview) - display->funcs.color = &chv_color_funcs; + display->color.funcs = &chv_color_funcs; else if (display->platform.valleyview) - display->funcs.color = &vlv_color_funcs; + display->color.funcs = &vlv_color_funcs; else if (DISPLAY_VER(display) >= 4) - display->funcs.color = &i965_color_funcs; + display->color.funcs = &i965_color_funcs; else - display->funcs.color = &i9xx_color_funcs; + display->color.funcs = &i9xx_color_funcs; } else { if (DISPLAY_VER(display) >= 12) - display->funcs.color = &tgl_color_funcs; + display->color.funcs = &tgl_color_funcs; else if (DISPLAY_VER(display) == 11) - display->funcs.color = &icl_color_funcs; + display->color.funcs = &icl_color_funcs; else if (DISPLAY_VER(display) == 10) - display->funcs.color = &glk_color_funcs; + display->color.funcs = &glk_color_funcs; else if (DISPLAY_VER(display) == 9) - display->funcs.color = &skl_color_funcs; + display->color.funcs = &skl_color_funcs; else if (DISPLAY_VER(display) == 8) - display->funcs.color = &bdw_color_funcs; + display->color.funcs = &bdw_color_funcs; else if (display->platform.haswell) - display->funcs.color = &hsw_color_funcs; + display->color.funcs = &hsw_color_funcs; else if (DISPLAY_VER(display) == 7) - display->funcs.color = &ivb_color_funcs; + display->color.funcs = &ivb_color_funcs; else - display->funcs.color = &ilk_color_funcs; + display->color.funcs = &ilk_color_funcs; } } diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 6aa6a1dd6e1b..adab1cf2f3c4 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -850,7 +850,7 @@ intel_crt_detect(struct drm_connector *connector, struct intel_display *display = to_intel_display(connector->dev); struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); struct intel_encoder *encoder = &crt->base; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct ref_tracker *wakeref; int status; diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 234843b8f83a..4493483f10a9 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -250,7 +250,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, str_enabled_disabled(pipe_config->has_sel_update), str_enabled_disabled(pipe_config->has_panel_replay), str_enabled_disabled(pipe_config->enable_psr2_sel_fetch)); - drm_printf(&p, "minimum HBlank: %d\n", pipe_config->min_hblank); + drm_printf(&p, "minimum hblank: %d\n", pipe_config->min_hblank); } drm_printf(&p, "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", @@ -320,19 +320,23 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, drm_printf(&p, "pipe mode: " DRM_MODE_FMT "\n", DRM_MODE_ARG(&pipe_config->hw.pipe_mode)); intel_dump_crtc_timings(&p, &pipe_config->hw.pipe_mode); - drm_printf(&p, "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d, min cdclk %d\n", - pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), - pipe_config->pixel_rate, pipe_config->min_cdclk); + drm_printf(&p, "port clock: %d, pixel rate %d, min cdclk %d, min voltage level %d\n", + pipe_config->port_clock, pipe_config->pixel_rate, + pipe_config->min_cdclk, pipe_config->min_voltage_level); drm_printf(&p, "linetime: %d, ips linetime: %d\n", pipe_config->linetime, pipe_config->ips_linetime); if (DISPLAY_VER(display) >= 9) - drm_printf(&p, "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d, scaling_filter: %d\n", + drm_printf(&p, "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d, scaling_filter: %d, sharpness_strength: %d\n", crtc->num_scalers, pipe_config->scaler_state.scaler_users, pipe_config->scaler_state.scaler_id, - pipe_config->hw.scaling_filter); + pipe_config->hw.scaling_filter, + pipe_config->hw.sharpness_strength); + + drm_printf(&p, "pipe src: " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_config->pipe_src)); if (HAS_GMCH(display)) drm_printf(&p, "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", @@ -345,6 +349,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, str_enabled_disabled(pipe_config->pch_pfit.enabled), str_yes_no(pipe_config->pch_pfit.force_thru)); + drm_printf(&p, "sharpness strength: %d, sharpness tap size: %d, sharpness enable: %d\n", + pipe_config->pch_pfit.casf.strength, + pipe_config->pch_pfit.casf.win_size, + pipe_config->pch_pfit.casf.enable); + drm_printf(&p, "ips: %i, double wide: %i, drrs: %i\n", pipe_config->ips_enabled, pipe_config->double_wide, pipe_config->has_drrs); @@ -380,11 +389,6 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, intel_vdsc_state_dump(&p, 0, pipe_config); - drm_printf(&p, "sharpness strength: %d, sharpness tap size: %d, sharpness enable: %d\n", - pipe_config->hw.casf_params.strength, - pipe_config->hw.casf_params.win_size, - pipe_config->hw.casf_params.casf_enable); - dump_planes: if (!state) return; diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 7e59409bbf01..d832e44ef62a 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -492,7 +492,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, wakeref = intel_cx0_phy_transaction_begin(encoder); - trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(display->drm, !trans)) { intel_cx0_phy_transaction_end(encoder, wakeref); return; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ebefa889bc8c..2681940a5cfe 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -33,6 +33,7 @@ #include #include #include +#include #include "icl_dsi.h" #include "intel_alpm.h" @@ -81,7 +82,6 @@ #include "intel_psr.h" #include "intel_quirks.h" #include "intel_snps_phy.h" -#include "intel_step.h" #include "intel_tc.h" #include "intel_vdsc.h" #include "intel_vdsc_regs.h" @@ -140,7 +140,7 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, enum port port = encoder->port; const struct intel_ddi_buf_trans *trans; - trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(display->drm, !trans)) return; @@ -172,7 +172,7 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, enum port port = encoder->port; const struct intel_ddi_buf_trans *trans; - trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(display->drm, !trans)) return; @@ -1106,7 +1106,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, const struct intel_ddi_buf_trans *trans; int n_entries; - trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(display->drm, !trans)) return; @@ -1132,7 +1132,7 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; int n_entries; - encoder->get_buf_trans(encoder, crtc_state, &n_entries); + intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); if (drm_WARN_ON(display->drm, n_entries < 1)) n_entries = 1; @@ -1175,7 +1175,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, int n_entries, ln; u32 val; - trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(display->drm, !trans)) return; @@ -1293,7 +1293,7 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) return; - trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(display->drm, !trans)) return; @@ -1394,7 +1394,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) return; - trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(display->drm, !trans)) return; @@ -1511,7 +1511,7 @@ int intel_ddi_level(struct intel_encoder *encoder, const struct intel_ddi_buf_trans *trans; int level, n_entries; - trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(display->drm, !trans)) return 0; diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 395dba8c9e4d..4cd1e4d76c7a 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1123,8 +1123,8 @@ static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_dp14[] = { { .lt = { 1, 2, 0, 28, 7 } }, { .lt = { 0, 3, 0, 35, 13 } }, { .lt = { 1, 1, 0, 27, 0 } }, - { .lt = { 1, 2, 0, 31, 4 } }, - { .lt = { 0, 3, 0, 39, 9 } }, + { .lt = { 1, 2, 0, 31, 5 } }, + { .lt = { 0, 3, 0, 37, 11 } }, { .lt = { 1, 2, 0, 35, 0 } }, { .lt = { 0, 3, 0, 41, 7 } }, { .lt = { 0, 3, 0, 48, 0 } }, @@ -1852,3 +1852,10 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) MISSING_CASE(pdev->device); } } + +const struct intel_ddi_buf_trans *intel_ddi_buf_trans_get(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + return encoder->get_buf_trans(encoder, crtc_state, n_entries); +} diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h index cec332090a20..9698697f3917 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h @@ -77,5 +77,8 @@ struct intel_ddi_buf_trans { bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table); void intel_ddi_buf_trans_init(struct intel_encoder *encoder); +const struct intel_ddi_buf_trans * +intel_ddi_buf_trans_get(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, int *n_entries); #endif diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c index d2a418da2d54..a96e83d76eaa 100644 --- a/drivers/gpu/drm/i915/display/intel_de.c +++ b/drivers/gpu/drm/i915/display/intel_de.c @@ -176,3 +176,11 @@ void intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val) intel_uncore_write8(__to_uncore(display), reg, val); } + +u16 intel_de_read16(struct intel_display *display, i915_reg_t reg) +{ + /* this is only used on MCHBAR registers on pre-SNB */ + drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 6); + + return intel_uncore_read16(__to_uncore(display), reg); +} diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h index f87b84ab9d6d..14f9dc7b6dfd 100644 --- a/drivers/gpu/drm/i915/display/intel_de.h +++ b/drivers/gpu/drm/i915/display/intel_de.h @@ -19,6 +19,7 @@ static inline struct intel_uncore *__to_uncore(struct intel_display *display) u8 intel_de_read8(struct intel_display *display, i915_reg_t reg); void intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val); +u16 intel_de_read16(struct intel_display *display, i915_reg_t reg); static inline u32 intel_de_read(struct intel_display *display, i915_reg_t reg) @@ -35,8 +36,8 @@ intel_de_read(struct intel_display *display, i915_reg_t reg) } static inline u64 -intel_de_read64_2x32(struct intel_display *display, - i915_reg_t lower_reg, i915_reg_t upper_reg) +intel_de_read64_2x32_volatile(struct intel_display *display, + i915_reg_t lower_reg, i915_reg_t upper_reg) { u64 val; @@ -52,6 +53,18 @@ intel_de_read64_2x32(struct intel_display *display, return val; } +static inline u64 +intel_de_read64_2x32(struct intel_display *display, i915_reg_t reg) +{ + i915_reg_t upper_reg = _MMIO(i915_mmio_reg_offset(reg) + 4); + u32 lower, upper; + + lower = intel_de_read(display, reg); + upper = intel_de_read(display, upper_reg); + + return (u64)upper << 32 | lower; +} + static inline void intel_de_posting_read(struct intel_display *display, i915_reg_t reg) { diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ad2fe10b6b1f..d5cf1476c7b9 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -58,7 +58,6 @@ #include "intel_audio.h" #include "intel_bo.h" #include "intel_bw.h" -#include "intel_casf.h" #include "intel_cdclk.h" #include "intel_clock_gating.h" #include "intel_color.h" @@ -988,24 +987,6 @@ static bool audio_disabling(const struct intel_crtc_state *old_crtc_state, memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0); } -static bool intel_casf_enabling(const struct intel_crtc_state *new_crtc_state, - const struct intel_crtc_state *old_crtc_state) -{ - if (!new_crtc_state->hw.active) - return false; - - return is_enabling(hw.casf_params.casf_enable, old_crtc_state, new_crtc_state); -} - -static bool intel_casf_disabling(const struct intel_crtc_state *old_crtc_state, - const struct intel_crtc_state *new_crtc_state) -{ - if (!new_crtc_state->hw.active) - return false; - - return is_disabling(hw.casf_params.casf_enable, old_crtc_state, new_crtc_state); -} - static bool intel_crtc_lobf_enabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -1187,9 +1168,6 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, if (audio_disabling(old_crtc_state, new_crtc_state)) intel_encoders_audio_disable(state, crtc); - if (intel_casf_disabling(old_crtc_state, new_crtc_state)) - intel_casf_disable(new_crtc_state); - intel_drrs_deactivate(old_crtc_state); if (hsw_ips_pre_update(state, crtc)) @@ -2184,7 +2162,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state, if (DISPLAY_VER(display) != 2) intel_set_cpu_fifo_underrun_reporting(display, pipe, false); - if (!display->funcs.wm->initial_watermarks) + if (!display->wm.funcs->initial_watermarks) intel_update_watermarks(display); /* clock the pipe down to 640x480@60 to potentially save power */ @@ -4073,7 +4051,7 @@ bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - if (!display->funcs.display->get_pipe_config(crtc, crtc_state)) + if (!display->modeset.funcs->get_pipe_config(crtc, crtc_state)) return false; crtc_state->hw.active = true; @@ -4308,14 +4286,9 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, return ret; } - ret = intel_casf_compute_config(crtc_state); - if (ret) - return ret; - if (DISPLAY_VER(display) >= 9) { if (intel_crtc_needs_modeset(crtc_state) || - intel_crtc_needs_fastset(crtc_state) || - intel_casf_needs_scaler(crtc_state)) { + intel_crtc_needs_fastset(crtc_state)) { ret = skl_update_scaler_crtc(crtc_state); if (ret) return ret; @@ -4550,6 +4523,7 @@ intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, drm_mode_copy(&crtc_state->hw.adjusted_mode, &crtc_state->uapi.adjusted_mode); crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; + crtc_state->hw.sharpness_strength = crtc_state->uapi.sharpness_strength; intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); } @@ -4615,6 +4589,7 @@ copy_joiner_crtc_state_modeset(struct intel_atomic_state *state, drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode, &primary_crtc_state->hw.adjusted_mode); secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter; + secondary_crtc_state->hw.sharpness_strength = primary_crtc_state->hw.sharpness_strength; if (primary_crtc_state->dp_tunnel_ref.tunnel) drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel, @@ -5368,12 +5343,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); PIPE_CONF_CHECK_RECT(pch_pfit.dst); + PIPE_CONF_CHECK_BOOL(pch_pfit.casf.enable); + PIPE_CONF_CHECK_I(pch_pfit.casf.win_size); + PIPE_CONF_CHECK_I(pch_pfit.casf.strength); PIPE_CONF_CHECK_I(scaler_state.scaler_id); PIPE_CONF_CHECK_I(pixel_rate); - PIPE_CONF_CHECK_BOOL(hw.casf_params.casf_enable); - PIPE_CONF_CHECK_I(hw.casf_params.win_size); - PIPE_CONF_CHECK_I(hw.casf_params.strength); PIPE_CONF_CHECK_X(gamma_mode); if (display->platform.cherryview) @@ -5658,11 +5633,11 @@ int intel_modeset_commit_pipes(struct intel_display *display, u8 pipe_mask, struct drm_modeset_acquire_ctx *ctx) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct intel_crtc *crtc; int ret; - state = drm_atomic_state_alloc(display->drm); + state = drm_atomic_commit_alloc(display->drm); if (!state) return -ENOMEM; @@ -5683,7 +5658,7 @@ int intel_modeset_commit_pipes(struct intel_display *display, ret = drm_atomic_commit(state); out: - drm_atomic_state_put(state); + drm_atomic_commit_put(state); return ret; } @@ -6402,7 +6377,7 @@ static int intel_atomic_check_config_and_link(struct intel_atomic_state *state) * @_state: state to validate */ int intel_atomic_check(struct drm_device *dev, - struct drm_atomic_state *_state) + struct drm_atomic_commit *_state) { struct intel_display *display = to_intel_display(dev); struct intel_atomic_state *state = to_intel_atomic_state(_state); @@ -6428,6 +6403,10 @@ int intel_atomic_check(struct drm_device *dev, if (new_crtc_state->uapi.scaling_filter != old_crtc_state->uapi.scaling_filter) new_crtc_state->uapi.mode_changed = true; + + if (new_crtc_state->uapi.sharpness_strength != + old_crtc_state->uapi.sharpness_strength) + new_crtc_state->uapi.mode_changed = true; } intel_vrr_check_modeset(state); @@ -6760,7 +6739,9 @@ static void intel_enable_crtc(struct intel_atomic_state *state, intel_psr_notify_pipe_change(state, crtc, true); - display->funcs.display->crtc_enable(state, crtc); + display->modeset.funcs->crtc_enable(state, crtc); + + intel_crtc_wait_for_next_vblank(crtc); /* vblanks work again, re-enable pipe CRC. */ intel_crtc_enable_pipe_crc(crtc); @@ -6801,11 +6782,6 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, intel_vrr_set_transcoder_timings(new_crtc_state); } - if (intel_casf_enabling(new_crtc_state, old_crtc_state)) - intel_casf_enable(new_crtc_state); - else if (new_crtc_state->hw.casf_params.strength != old_crtc_state->hw.casf_params.strength) - intel_casf_update_strength(new_crtc_state); - intel_fbc_update(state, crtc); drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF)); @@ -6896,7 +6872,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state, intel_psr_notify_pipe_change(state, crtc, false); - display->funcs.display->crtc_disable(state, crtc); + display->modeset.funcs->crtc_disable(state, crtc); for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, intel_crtc_joined_pipe_mask(old_crtc_state)) { @@ -7215,7 +7191,7 @@ static void intel_atomic_cleanup_work(struct work_struct *work) drm_atomic_helper_cleanup_planes(display->drm, &state->base); drm_atomic_helper_commit_cleanup_done(&state->base); - drm_atomic_state_put(&state->base); + drm_atomic_commit_put(&state->base); } static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) @@ -7548,7 +7524,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) } /* Now enable the clocks, plane, pipe, and connectors that we set up. */ - display->funcs.display->commit_modeset_enables(state); + display->modeset.funcs->commit_modeset_enables(state); /* FIXME probably need to sequence this properly */ intel_program_dpkgc_latency(state); @@ -7719,7 +7695,7 @@ static int intel_atomic_swap_state(struct intel_atomic_state *state) return 0; } -int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, +int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_commit *_state, bool nonblock) { struct intel_display *display = to_intel_display(dev); @@ -7774,7 +7750,7 @@ int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, return ret; } - drm_atomic_state_get(&state->base); + drm_atomic_commit_get(&state->base); INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); if (nonblock && state->modeset) { @@ -8221,7 +8197,7 @@ intel_mode_valid_max_plane_size(struct intel_display *display, return MODE_OK; } -static const struct intel_display_funcs skl_display_funcs = { +static const struct intel_modeset_funcs skl_display_funcs = { .get_pipe_config = hsw_get_pipe_config, .crtc_enable = hsw_crtc_enable, .crtc_disable = hsw_crtc_disable, @@ -8230,7 +8206,7 @@ static const struct intel_display_funcs skl_display_funcs = { .fixup_initial_plane_config = skl_fixup_initial_plane_config, }; -static const struct intel_display_funcs ddi_display_funcs = { +static const struct intel_modeset_funcs ddi_display_funcs = { .get_pipe_config = hsw_get_pipe_config, .crtc_enable = hsw_crtc_enable, .crtc_disable = hsw_crtc_disable, @@ -8239,7 +8215,7 @@ static const struct intel_display_funcs ddi_display_funcs = { .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, }; -static const struct intel_display_funcs pch_split_display_funcs = { +static const struct intel_modeset_funcs pch_split_display_funcs = { .get_pipe_config = ilk_get_pipe_config, .crtc_enable = ilk_crtc_enable, .crtc_disable = ilk_crtc_disable, @@ -8248,7 +8224,7 @@ static const struct intel_display_funcs pch_split_display_funcs = { .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, }; -static const struct intel_display_funcs vlv_display_funcs = { +static const struct intel_modeset_funcs vlv_display_funcs = { .get_pipe_config = i9xx_get_pipe_config, .crtc_enable = valleyview_crtc_enable, .crtc_disable = i9xx_crtc_disable, @@ -8257,7 +8233,7 @@ static const struct intel_display_funcs vlv_display_funcs = { .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, }; -static const struct intel_display_funcs i9xx_display_funcs = { +static const struct intel_modeset_funcs i9xx_display_funcs = { .get_pipe_config = i9xx_get_pipe_config, .crtc_enable = i9xx_crtc_enable, .crtc_disable = i9xx_crtc_disable, @@ -8273,27 +8249,27 @@ static const struct intel_display_funcs i9xx_display_funcs = { void intel_init_display_hooks(struct intel_display *display) { if (DISPLAY_VER(display) >= 9) { - display->funcs.display = &skl_display_funcs; + display->modeset.funcs = &skl_display_funcs; } else if (HAS_DDI(display)) { - display->funcs.display = &ddi_display_funcs; + display->modeset.funcs = &ddi_display_funcs; } else if (HAS_PCH_SPLIT(display)) { - display->funcs.display = &pch_split_display_funcs; + display->modeset.funcs = &pch_split_display_funcs; } else if (display->platform.cherryview || display->platform.valleyview) { - display->funcs.display = &vlv_display_funcs; + display->modeset.funcs = &vlv_display_funcs; } else { - display->funcs.display = &i9xx_display_funcs; + display->modeset.funcs = &i9xx_display_funcs; } } int intel_initial_commit(struct intel_display *display) { - struct drm_atomic_state *state = NULL; + struct drm_atomic_commit *state = NULL; struct drm_modeset_acquire_ctx ctx; struct intel_crtc *crtc; int ret = 0; - state = drm_atomic_state_alloc(display->drm); + state = drm_atomic_commit_alloc(display->drm); if (!state) return -ENOMEM; @@ -8347,12 +8323,12 @@ int intel_initial_commit(struct intel_display *display) out: if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); drm_modeset_backoff(&ctx); goto retry; } - drm_atomic_state_put(state); + drm_atomic_commit_put(state); drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 1e76a455d7c4..a43ada0c0502 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -30,7 +30,7 @@ #include "i915_reg_defs.h" #include "intel_display_limits.h" -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_device; struct drm_display_mode; struct drm_encoder; @@ -354,7 +354,7 @@ enum phy_fia { _intel_modeset_secondary_pipes(crtc_state), \ i) -int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); +int intel_atomic_check(struct drm_device *dev, struct drm_atomic_commit *state); u8 intel_calc_enabled_pipes(struct intel_atomic_state *state, u8 enabled_pipes); u8 intel_calc_active_pipes(struct intel_atomic_state *state, @@ -493,7 +493,7 @@ int intel_initial_commit(struct intel_display *display); void intel_panel_sanitize_ssc(struct intel_display *display); enum drm_mode_status intel_mode_valid(struct drm_device *dev, const struct drm_display_mode *mode); -int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, +int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_commit *_state, bool nonblock); /* modesetting asserts */ diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c new file mode 100644 index 000000000000..d036c7e5863d --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2026 Intel Corporation + */ + +#include + +#include "intel_de.h" +#include "i9xx_plane_regs.h" +#include "intel_display.h" +#include "intel_display_clock_gating.h" +#include "intel_display_core.h" +#include "intel_display_regs.h" + +static void intel_display_gen9_init_clock_gating(struct intel_display *display) +{ + /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */ + intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP); + + /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */ + intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM); + + /* + * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl + * Display WA #0859: skl,bxt,kbl,glk,cfl + */ + intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE); +} + +void intel_display_skl_init_clock_gating(struct intel_display *display) +{ + /* + * WaCompressedResourceDisplayNewHashMode:skl,kbl + * Display WA #0390: skl,kbl + * + * Must match Sampler, Pixel Back End, and Media. See + * WaCompressedResourceSamplerPbeMediaNewHashMode. + */ + intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE); + + intel_display_gen9_init_clock_gating(display); + + /* + * WaFbcTurnOffFbcWatermark:skl + * Display WA #0562: skl + */ + intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); +} + +void intel_display_kbl_init_clock_gating(struct intel_display *display) +{ + /* + * WaCompressedResourceDisplayNewHashMode:skl,kbl + * Display WA #0390: skl,kbl + * + * Must match Sampler, Pixel Back End, and Media. See + * WaCompressedResourceSamplerPbeMediaNewHashMode. + */ + intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE); + + intel_display_gen9_init_clock_gating(display); + + /* + * WaFbcTurnOffFbcWatermark:kbl + * Display WA #0562: kbl + */ + intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); +} + +void intel_display_cfl_init_clock_gating(struct intel_display *display) +{ + /* + * WaCompressedResourceDisplayNewHashMode:skl,kbl (and cfl, cml) + * Display WA #0390: skl,kbl (and cfl, cml) + * + * Must match Sampler, Pixel Back End, and Media. See + * WaCompressedResourceSamplerPbeMediaNewHashMode. + * + * NOTE: this is the same workaround used for skl and kbl, + * because the original implementation was checking HAS_LLC(), + * which cfl/cml have, even though the comment for the + * workaround doesn't mention it. + * + */ + intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE); + + intel_display_gen9_init_clock_gating(display); + + /* + * WaFbcTurnOffFbcWatermark:cfl + * Display WA #0562: cfl + */ + intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); +} + +void intel_display_bxt_init_clock_gating(struct intel_display *display) +{ + intel_display_gen9_init_clock_gating(display); + + /* + * Wa: Backlight PWM may stop in the asserted state, causing backlight + * to stay fully on. + */ + intel_de_write(display, GEN9_CLKGATE_DIS_0, + intel_de_read(display, GEN9_CLKGATE_DIS_0) | + PWM1_GATING_DIS | PWM2_GATING_DIS); + + /* + * Lower the display internal timeout. + * This is needed to avoid any hard hangs when DSI port PLL + * is off and a MMIO access is attempted by any privilege + * application, using batch buffers or any other means. + */ + intel_de_write(display, RM_TIMEOUT, MMIO_TIMEOUT_US(950)); + + /* + * WaFbcTurnOffFbcWatermark:bxt + * Display WA #0562: bxt + */ + intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); +} + +void intel_display_glk_init_clock_gating(struct intel_display *display) +{ + intel_display_gen9_init_clock_gating(display); + + /* + * WaDisablePWMClockGating:glk + * Backlight PWM may stop in the asserted state, causing backlight + * to stay fully on. + */ + intel_de_write(display, GEN9_CLKGATE_DIS_0, + intel_de_read(display, GEN9_CLKGATE_DIS_0) | + PWM1_GATING_DIS | PWM2_GATING_DIS); +} + +void intel_display_bdw_clock_gating_disable_fbcq(struct intel_display *display) +{ + /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ + intel_de_rmw(display, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); +} + +void intel_display_bdw_clock_gating_vblank_in_srd(struct intel_display *display) +{ + enum pipe pipe; + + /* WaPsrDPAMaskVBlankInSRD:hsw */ + intel_de_rmw(display, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); + + for_each_pipe(display, pipe) { + /* WaPsrDPRSUnmaskVBlankInSRD:hsw,bdw */ + intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 0, + BDW_UNMASK_VBL_TO_REGS_IN_SRD); + } +} + +void intel_display_bdw_clock_gating_kvm_notif(struct intel_display *display) +{ + /* WaKVMNotificationOnConfigChange:bdw */ + intel_de_rmw(display, CHICKEN_PAR2_1, 0, + KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); +} + +void intel_display_hsw_init_clock_gating(struct intel_display *display) +{ + enum pipe pipe; + + /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ + intel_de_rmw(display, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); + + /* WaPsrDPAMaskVBlankInSRD:hsw */ + intel_de_rmw(display, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); + + for_each_pipe(display, pipe) { + /* WaPsrDPRSUnmaskVBlankInSRD:hsw,bdw */ + intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 0, + HSW_UNMASK_VBL_TO_REGS_IN_SRD); + } +} + +void intel_display_disable_trickle_feed(struct intel_display *display) +{ + enum pipe pipe; + + for_each_pipe(display, pipe) { + intel_de_rmw(display, DSPCNTR(display, pipe), 0, + DISP_TRICKLE_FEED_DISABLE); + + intel_de_rmw(display, DSPSURF(display, pipe), 0, 0); + intel_de_posting_read(display, DSPSURF(display, pipe)); + } +} + +void intel_display_ilk_init_clock_gating(struct intel_display *display) +{ + u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; + + /* + * Required for FBC + * WaFbcDisableDpfcClockGating:ilk + */ + dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | + ILK_DPFCUNIT_CLOCK_GATE_DISABLE | + ILK_DPFDUNIT_CLOCK_GATE_ENABLE; + + intel_de_write(display, ILK_DISPLAY_CHICKEN2, + intel_de_read(display, ILK_DISPLAY_CHICKEN2) | + ILK_DPARB_GATE | ILK_VSDPFD_FULL); + dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; + intel_de_write(display, DISP_ARB_CTL, + intel_de_read(display, DISP_ARB_CTL) | + DISP_FBC_WM_DIS); + + if (display->platform.ironlake && display->platform.mobile) { + /* WaFbcAsynchFlipDisableFbcQueue:ilk */ + intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); + intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE); + } + + intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate); + intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); + + intel_display_disable_trickle_feed(display); +} + +void intel_display_gen6_init_clock_gating(struct intel_display *display) +{ + u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; + + intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate); + intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); + + intel_de_write(display, ILK_DISPLAY_CHICKEN1, + intel_de_read(display, ILK_DISPLAY_CHICKEN1) | + ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); + intel_de_write(display, ILK_DISPLAY_CHICKEN2, + intel_de_read(display, ILK_DISPLAY_CHICKEN2) | + ILK_DPARB_GATE | ILK_VSDPFD_FULL); + intel_de_write(display, ILK_DSPCLK_GATE_D, + intel_de_read(display, ILK_DSPCLK_GATE_D) | + ILK_DPARBUNIT_CLOCK_GATE_ENABLE | + ILK_DPFDUNIT_CLOCK_GATE_ENABLE); + + intel_display_disable_trickle_feed(display); +} + +void intel_display_ivb_init_clock_gating(struct intel_display *display) +{ + intel_de_write(display, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); + intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); +} + +void intel_display_g4x_init_clock_gating(struct intel_display *display) +{ + u32 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | + OVRUNIT_CLOCK_GATE_DISABLE | + OVCUNIT_CLOCK_GATE_DISABLE; + + if (display->platform.gm45) + dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; + + intel_de_write(display, DSPCLK_GATE_D, dspclk_gate); + + intel_display_disable_trickle_feed(display); +} + +void intel_display_i965gm_init_clock_gating(struct intel_display *display) +{ + intel_de_write(display, DSPCLK_GATE_D, 0); +} diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h new file mode 100644 index 000000000000..b6dd34ca92dd --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Intel Corporation + */ + +#ifndef __INTEL_DISPLAY_CLOCK_GATING_H__ +#define __INTEL_DISPLAY_CLOCK_GATING_H__ + +struct intel_display; + +void intel_display_skl_init_clock_gating(struct intel_display *display); +void intel_display_kbl_init_clock_gating(struct intel_display *display); +void intel_display_cfl_init_clock_gating(struct intel_display *display); +void intel_display_bxt_init_clock_gating(struct intel_display *display); +void intel_display_glk_init_clock_gating(struct intel_display *display); +void intel_display_bdw_clock_gating_disable_fbcq(struct intel_display *display); +void intel_display_bdw_clock_gating_vblank_in_srd(struct intel_display *display); +void intel_display_bdw_clock_gating_kvm_notif(struct intel_display *display); +void intel_display_hsw_init_clock_gating(struct intel_display *display); +void intel_display_disable_trickle_feed(struct intel_display *display); +void intel_display_ilk_init_clock_gating(struct intel_display *display); +void intel_display_gen6_init_clock_gating(struct intel_display *display); +void intel_display_ivb_init_clock_gating(struct intel_display *display); +void intel_display_g4x_init_clock_gating(struct intel_display *display); +void intel_display_i965gm_init_clock_gating(struct intel_display *display); + +#endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index d9baca2d5aaf..76745ce6a716 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -47,7 +47,7 @@ struct intel_dpll_global_funcs; struct intel_dpll_mgr; struct intel_fbdev; struct intel_fdi_funcs; -struct intel_hotplug_funcs; +struct intel_hotplug_irq_funcs; struct intel_initial_plane_config; struct intel_opregion; struct intel_overlay; @@ -59,7 +59,7 @@ struct task_struct; /* Amount of PSF GV points, BSpec precisely defines this */ #define I915_NUM_PSF_GV_POINTS 3 -struct intel_display_funcs { +struct intel_modeset_funcs { /* * Returns the active state of the crtc, and if the crtc is active, * fills out the pipe-config with the hw state. @@ -100,6 +100,9 @@ struct intel_audio_state { }; struct intel_audio { + /* internal display audio functions */ + const struct intel_audio_funcs *funcs; + /* hda/i915 audio component */ struct i915_audio_component *component; bool component_registered; @@ -124,6 +127,9 @@ struct intel_audio { * dpll, because on some platforms plls share registers. */ struct intel_dpll_global { + /* internal dpll functions */ + const struct intel_dpll_global_funcs *funcs; + struct mutex lock; int num_dpll; @@ -152,6 +158,9 @@ struct intel_frontbuffer_tracking { }; struct intel_hotplug { + /* internal hotplug irq functions */ + const struct intel_hotplug_irq_funcs *funcs; + struct delayed_work hotplug_work; const u32 *hpd, *pch_hpd; @@ -244,6 +253,9 @@ struct intel_vbt_data { }; struct intel_wm { + /* internal watermark functions */ + const struct intel_wm_funcs *funcs; + /* * Raw watermark latency values: * in 0.1us units for WM0, @@ -297,33 +309,6 @@ struct intel_display { /* list of all intel_crtcs sorted by pipe */ struct list_head pipe_list; - /* Display functions */ - struct { - /* Top level crtc-ish functions */ - const struct intel_display_funcs *display; - - /* Display CDCLK functions */ - const struct intel_cdclk_funcs *cdclk; - - /* Display pll funcs */ - const struct intel_dpll_global_funcs *dpll; - - /* irq display functions */ - const struct intel_hotplug_funcs *hotplug; - - /* pm display functions */ - const struct intel_wm_funcs *wm; - - /* fdi display functions */ - const struct intel_fdi_funcs *fdi; - - /* Display internal color functions */ - const struct intel_color_funcs *color; - - /* Display internal audio functions */ - const struct intel_audio_funcs *audio; - } funcs; - struct { bool any_task_allowed; struct task_struct *allowed_task; @@ -351,6 +336,9 @@ struct intel_display { } bw; struct { + /* Internal CDCLK functions */ + const struct intel_cdclk_funcs *funcs; + /* The current hardware cdclk configuration */ struct intel_cdclk_config hw; @@ -365,6 +353,9 @@ struct intel_display { } cdclk; struct { + /* internal color functions */ + const struct intel_color_funcs *funcs; + struct drm_property_blob *glk_linear_degamma_lut; } color; @@ -418,6 +409,9 @@ struct intel_display { } fbdev; struct { + /* internal fdi functions */ + const struct intel_fdi_funcs *funcs; + unsigned int pll_freq; u32 rx_config; } fdi; @@ -518,6 +512,11 @@ struct intel_display { u32 pipestat_irq_mask[I915_MAX_PIPES]; } irq; + struct { + /* Top level crtc-ish functions */ + const struct intel_modeset_funcs *funcs; + } modeset; + struct { /* protected by wm.wm_mutex */ u16 linetime[I915_MAX_PIPES]; @@ -559,12 +558,15 @@ struct intel_display { unsigned long mask; } quirks; + struct { + u32 count; + } reset; + struct { /* restore state for suspend/resume and display reset */ - struct drm_atomic_state *modeset_state; + struct drm_atomic_commit *modeset_state; struct drm_modeset_acquire_ctx reset_ctx; /* modeset stuck tracking for reset */ - atomic_t pending_fb_pin; u32 saveDSPARB; u32 saveSWF0[16]; u32 saveSWF1[16]; diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 2614c4863c87..81bef000a4e3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -27,6 +27,7 @@ #include "intel_display_power.h" #include "intel_display_power_well.h" #include "intel_display_regs.h" +#include "intel_display_reset.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_dmc.h" @@ -416,11 +417,12 @@ static void intel_scaler_info(struct seq_file *m, struct intel_crtc *crtc) /* Not all platforms have a scaler */ if (num_scalers) { - seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d scaling_filter=%d", + seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d scaling_filter=%d sharpness_strength=%d", num_scalers, crtc_state->scaler_state.scaler_users, crtc_state->scaler_state.scaler_id, - crtc_state->hw.scaling_filter); + crtc_state->hw.scaling_filter, + crtc_state->hw.sharpness_strength); for (i = 0; i < num_scalers; i++) { const struct intel_scaler *sc = @@ -837,6 +839,7 @@ void intel_display_debugfs_register(struct intel_display *display) intel_bios_debugfs_register(display); intel_cdclk_debugfs_register(display); + intel_display_reset_debugfs_register(display); intel_dmc_debugfs_register(display); intel_dp_test_debugfs_register(display); intel_fbc_debugfs_register(display); diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index be55ef8ea617..7260990038dd 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "intel_cx0_phy_regs.h" #include "intel_de.h" @@ -21,7 +22,6 @@ #include "intel_display_types.h" #include "intel_display_wa.h" #include "intel_fbc.h" -#include "intel_step.h" __diag_push(); __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info"); diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 1170ac346615..074e3ba8fb77 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -200,6 +200,7 @@ struct intel_display_platforms { #define HAS_PSR_TRANS_PUSH_FRAME_CHANGE(__display) (DISPLAY_VER(__display) >= 20) #define HAS_SAGV(__display) (DISPLAY_VER(__display) >= 9 && \ !(__display)->platform.broxton && !(__display)->platform.geminilake) +#define HAS_SAGV_WM(__display) (DISPLAY_VER(__display) >= 12 && !(__display)->platform.rocketlake) #define HAS_TRANSCODER(__display, trans) ((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \ BIT(trans)) != 0) #define HAS_UNCOMPRESSED_JOINER(__display) (DISPLAY_VER(__display) >= 13) diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index 9c2f7ad6c7b7..8e6c3dfab5c0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -680,7 +680,7 @@ void intel_display_driver_unregister(struct intel_display *display) */ int intel_display_driver_suspend(struct intel_display *display) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; int ret; if (!HAS_DISPLAY(display)) @@ -704,7 +704,7 @@ int intel_display_driver_suspend(struct intel_display *display) int __intel_display_driver_resume(struct intel_display *display, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_modeset_acquire_ctx *ctx) { struct drm_crtc_state *crtc_state; @@ -743,7 +743,7 @@ __intel_display_driver_resume(struct intel_display *display, void intel_display_driver_resume(struct intel_display *display) { - struct drm_atomic_state *state = display->restore.modeset_state; + struct drm_atomic_commit *state = display->restore.modeset_state; struct drm_modeset_acquire_ctx ctx; int ret; @@ -778,5 +778,5 @@ void intel_display_driver_resume(struct intel_display *display) drm_err(display->drm, "Restoring old state failed with %i\n", ret); if (state) - drm_atomic_state_put(state); + drm_atomic_commit_put(state); } diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.h b/drivers/gpu/drm/i915/display/intel_display_driver.h index 2966ff91b219..5270c26a32e0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.h +++ b/drivers/gpu/drm/i915/display/intel_display_driver.h @@ -8,7 +8,7 @@ #include -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_modeset_acquire_ctx; struct intel_display; struct pci_dev; @@ -29,7 +29,7 @@ void intel_display_driver_resume(struct intel_display *display); /* interface for intel_display_reset.c */ int __intel_display_driver_resume(struct intel_display *display, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_modeset_acquire_ctx *ctx); void intel_display_driver_enable_user_access(struct intel_display *display); diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 70c1bba7c0a8..b5bfdebc66ca 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -2458,6 +2458,10 @@ void dg1_de_irq_postinstall(struct intel_display *display) intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); } +struct intel_display_irq_funcs { + void (*reset)(struct intel_display *display); +}; + void intel_display_irq_init(struct intel_display *display) { spin_lock_init(&display->irq.lock); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index ec96b141c74c..80ecf373fb19 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -8,6 +8,7 @@ #include #include +#include #include "intel_backlight_regs.h" #include "intel_cdclk.h" @@ -24,13 +25,12 @@ #include "intel_display_wa.h" #include "intel_dmc.h" #include "intel_dram.h" -#include "intel_mchbar_regs.h" +#include "intel_mchbar.h" #include "intel_parent.h" #include "intel_pch_refclk.h" #include "intel_pmdemand.h" #include "intel_pps_regs.h" #include "intel_snps_phy.h" -#include "intel_step.h" #include "skl_watermark.h" #include "skl_watermark_regs.h" #include "vlv_sideband.h" @@ -1252,7 +1252,7 @@ static void assert_can_disable_lcpll(struct intel_display *display) static u32 hsw_read_dcomp(struct intel_display *display) { if (display->platform.haswell) - return intel_de_read(display, D_COMP_HSW); + return intel_mchbar_read(display, D_COMP_HSW); else return intel_de_read(display, D_COMP_BDW); } @@ -1420,9 +1420,7 @@ static void hsw_disable_pc8(struct intel_display *display) intel_init_pch_refclk(display); /* Many display registers don't survive PC8+ */ -#ifdef I915 /* FIXME */ intel_clock_gating_init(display->drm); -#endif } static void intel_pch_reset_handshake(struct intel_display *display, @@ -1890,9 +1888,9 @@ static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0) { bool ret; - vlv_punit_get(display->drm); - ret = (vlv_punit_read(display->drm, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; - vlv_punit_put(display->drm); + vlv_punit_get(display); + ret = (vlv_punit_read(display, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; + vlv_punit_put(display); return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c index 65204d68a759..3400080d78d2 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c @@ -4,13 +4,13 @@ */ #include +#include #include "intel_display_core.h" #include "intel_display_power_map.h" #include "intel_display_power_well.h" #include "intel_display_regs.h" #include "intel_display_types.h" -#include "vlv_iosf_sb_reg.h" #define __LIST_INLINE_ELEMS(__elem_type, ...) \ ((__elem_type[]) { __VA_ARGS__ }) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index f855f0f88694..6fbfd46461b0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -34,7 +34,6 @@ #include "intel_vga.h" #include "skl_watermark.h" #include "vlv_dpio_phy_regs.h" -#include "vlv_iosf_sb_reg.h" #include "vlv_sideband.h" /* @@ -1189,28 +1188,28 @@ static void vlv_set_power_well(struct intel_display *display, state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : PUNIT_PWRGT_PWR_GATE(pw_idx); - vlv_punit_get(display->drm); + vlv_punit_get(display); - val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS); + val = vlv_punit_read(display, PUNIT_REG_PWRGT_STATUS); if ((val & mask) == state) goto out; - ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL); + ctrl = vlv_punit_read(display, PUNIT_REG_PWRGT_CTRL); ctrl &= ~mask; ctrl |= state; - vlv_punit_write(display->drm, PUNIT_REG_PWRGT_CTRL, ctrl); + vlv_punit_write(display, PUNIT_REG_PWRGT_CTRL, ctrl); - ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS), + ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_PWRGT_STATUS), (val & mask) == state, 500, 100 * 1000, false); if (ret) drm_err(display->drm, "timeout setting power well state %08x (%08x)\n", state, - vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL)); + vlv_punit_read(display, PUNIT_REG_PWRGT_CTRL)); out: - vlv_punit_put(display->drm); + vlv_punit_put(display); } static void vlv_power_well_enable(struct intel_display *display, @@ -1237,9 +1236,9 @@ static bool vlv_power_well_enabled(struct intel_display *display, mask = PUNIT_PWRGT_MASK(pw_idx); ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); - vlv_punit_get(display->drm); + vlv_punit_get(display); - state = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask; + state = vlv_punit_read(display, PUNIT_REG_PWRGT_STATUS) & mask; /* * We only ever set the power-on and power-gate states, anything * else is unexpected. @@ -1253,10 +1252,10 @@ static bool vlv_power_well_enabled(struct intel_display *display, * A transient state at this point would mean some unexpected party * is poking at the power controls too. */ - ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL) & mask; + ctrl = vlv_punit_read(display, PUNIT_REG_PWRGT_CTRL) & mask; drm_WARN_ON(display->drm, ctrl != state); - vlv_punit_put(display->drm); + vlv_punit_put(display); return enabled; } @@ -1533,30 +1532,30 @@ static void chv_dpio_cmn_power_well_enable(struct intel_display *display, drm_err(display->drm, "Display PHY %d is not power up\n", phy); - vlv_dpio_get(display->drm); + vlv_dpio_get(display); /* Enable dynamic power down */ - tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW28); + tmp = vlv_dpio_read(display, phy, CHV_CMN_DW28); tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; - vlv_dpio_write(display->drm, phy, CHV_CMN_DW28, tmp); + vlv_dpio_write(display, phy, CHV_CMN_DW28, tmp); if (id == VLV_DISP_PW_DPIO_CMN_BC) { - tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW6_CH1); + tmp = vlv_dpio_read(display, phy, CHV_CMN_DW6_CH1); tmp |= DPIO_DYNPWRDOWNEN_CH1; - vlv_dpio_write(display->drm, phy, CHV_CMN_DW6_CH1, tmp); + vlv_dpio_write(display, phy, CHV_CMN_DW6_CH1, tmp); } else { /* * Force the non-existing CL2 off. BXT does this * too, so maybe it saves some power even though * CL2 doesn't exist? */ - tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW30); + tmp = vlv_dpio_read(display, phy, CHV_CMN_DW30); tmp |= DPIO_CL2_LDOFUSE_PWRENB; - vlv_dpio_write(display->drm, phy, CHV_CMN_DW30, tmp); + vlv_dpio_write(display, phy, CHV_CMN_DW30, tmp); } - vlv_dpio_put(display->drm); + vlv_dpio_put(display); display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); intel_de_write(display, DISPLAY_PHY_CONTROL, @@ -1624,9 +1623,9 @@ static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_ph else reg = CHV_CMN_DW6_CH1; - vlv_dpio_get(display->drm); - val = vlv_dpio_read(display->drm, phy, reg); - vlv_dpio_put(display->drm); + vlv_dpio_get(display); + val = vlv_dpio_read(display, phy, reg); + vlv_dpio_put(display); /* * This assumes !override is only used when the port is disabled. @@ -1740,9 +1739,9 @@ static bool chv_pipe_power_well_enabled(struct intel_display *display, bool enabled; u32 state, ctrl; - vlv_punit_get(display->drm); + vlv_punit_get(display); - state = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); + state = vlv_punit_read(display, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); /* * We only ever set the power-on and power-gate states, anything * else is unexpected. @@ -1755,10 +1754,10 @@ static bool chv_pipe_power_well_enabled(struct intel_display *display, * A transient state at this point would mean some unexpected party * is poking at the power controls too. */ - ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); + ctrl = vlv_punit_read(display, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); drm_WARN_ON(display->drm, ctrl << 16 != state); - vlv_punit_put(display->drm); + vlv_punit_put(display); return enabled; } @@ -1774,29 +1773,29 @@ static void chv_set_pipe_power_well(struct intel_display *display, state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); - vlv_punit_get(display->drm); + vlv_punit_get(display); - ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); + ctrl = vlv_punit_read(display, PUNIT_REG_DSPSSPM); if ((ctrl & DP_SSS_MASK(pipe)) == state) goto out; ctrl &= ~DP_SSC_MASK(pipe); ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); - vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, ctrl); + vlv_punit_write(display, PUNIT_REG_DSPSSPM, ctrl); - ret = poll_timeout_us(ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM), + ret = poll_timeout_us(ctrl = vlv_punit_read(display, PUNIT_REG_DSPSSPM), (ctrl & DP_SSS_MASK(pipe)) == state, 500, 100 * 1000, false); if (ret) drm_err(display->drm, "timeout setting power well state %08x (%08x)\n", state, - vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM)); + vlv_punit_read(display, PUNIT_REG_DSPSSPM)); #undef COND out: - vlv_punit_put(display->drm); + vlv_punit_put(display); } static void chv_pipe_power_well_sync_hw(struct intel_display *display, diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index 4746e9ebd920..bc508995ad8b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -217,6 +217,34 @@ # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) + +#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) +#define ILK_FBCQ_DIS REG_BIT(22) +#define ILK_PABSTRETCH_DIS REG_BIT(21) +#define ILK_SABSTRETCH_DIS REG_BIT(20) +#define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) +#define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) +#define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) +#define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) +#define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) +#define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) +#define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) +#define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) +#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) +#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) + +#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) +/* Required on all Ironlake and Sandybridge according to the B-Spec. */ +#define ILK_ELPIN_409_SELECT REG_BIT(25) +#define ILK_DPARB_GATE REG_BIT(22) +#define ILK_VSDPFD_FULL REG_BIT(21) + +#define ILK_DSPCLK_GATE_D _MMIO(0x42020) +#define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28) +#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9) +#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8) +#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7) +#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5) /* * This bit must be set on the 830 to prevent hangs when turning off the * overlay scaler. @@ -405,6 +433,9 @@ #define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3) #define IGNORE_PSR2_HW_TRACKING REG_BIT(1) +#define CHICKEN_PAR2_1 _MMIO(0x42090) +#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) + /* * GEN9 clock gating regs */ @@ -2263,6 +2294,7 @@ #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) +#define TRANS_DP2_PR_TUNNELING_ENABLE REG_BIT(26) #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) #define _TRANS_DP2_VFREQHIGH_A 0x600a4 diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c b/drivers/gpu/drm/i915/display/intel_display_reset.c index d00ef5bdcbda..504ec7043cd9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reset.c +++ b/drivers/gpu/drm/i915/display/intel_display_reset.c @@ -3,6 +3,8 @@ * Copyright © 2023 Intel Corporation */ +#include + #include #include @@ -16,28 +18,23 @@ #include "intel_hotplug.h" #include "intel_pps.h" -bool intel_display_reset_test(struct intel_display *display) +bool intel_display_reset_supported(struct intel_display *display) { - return display->params.force_reset_modeset_test; + return display && HAS_DISPLAY(display); } -/* returns true if intel_display_reset_finish() needs to be called */ -bool intel_display_reset_prepare(struct intel_display *display, - modeset_stuck_fn modeset_stuck, void *context) +bool intel_display_reset_test(struct intel_display *display) +{ + return display && HAS_DISPLAY(display) && + display->params.force_reset_modeset_test; +} + +void intel_display_reset_prepare(struct intel_display *display) { struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; int ret; - if (!HAS_DISPLAY(display)) - return false; - - if (atomic_read(&display->restore.pending_fb_pin)) { - drm_dbg_kms(display->drm, - "Modeset potentially stuck, unbreaking through wedging\n"); - modeset_stuck(context); - } - /* * Need mode_config.mutex so that we don't * trample ongoing ->detect() and whatnot. @@ -60,32 +57,28 @@ bool intel_display_reset_prepare(struct intel_display *display, ret = PTR_ERR(state); drm_err(display->drm, "Duplicating state failed with %i\n", ret); - return true; + return; } ret = drm_atomic_helper_disable_all(display->drm, ctx); if (ret) { drm_err(display->drm, "Suspending crtc's failed with %i\n", ret); - drm_atomic_state_put(state); - return true; + drm_atomic_commit_put(state); + return; } + display->reset.count++; display->restore.modeset_state = state; state->acquire_ctx = ctx; - - return true; } void intel_display_reset_finish(struct intel_display *display, bool test_only) { struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; int ret; - if (!HAS_DISPLAY(display)) - return; - state = fetch_and_zero(&display->restore.modeset_state); if (!state) goto unlock; @@ -118,9 +111,16 @@ void intel_display_reset_finish(struct intel_display *display, bool test_only) intel_hpd_poll_disable(display); } - drm_atomic_state_put(state); + drm_atomic_commit_put(state); unlock: drm_modeset_drop_locks(ctx); drm_modeset_acquire_fini(ctx); mutex_unlock(&display->drm->mode_config.mutex); } + +void intel_display_reset_debugfs_register(struct intel_display *display) +{ + debugfs_create_u32("intel_display_reset_count", 0400, + display->drm->debugfs_root, + &display->reset.count); +} diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.h b/drivers/gpu/drm/i915/display/intel_display_reset.h index 8b3bda134454..b88c330a3441 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reset.h +++ b/drivers/gpu/drm/i915/display/intel_display_reset.h @@ -10,11 +10,11 @@ struct intel_display; -typedef void modeset_stuck_fn(void *context); - +bool intel_display_reset_supported(struct intel_display *display); bool intel_display_reset_test(struct intel_display *display); -bool intel_display_reset_prepare(struct intel_display *display, - modeset_stuck_fn modeset_stuck, void *context); +void intel_display_reset_prepare(struct intel_display *display); void intel_display_reset_finish(struct intel_display *display, bool test_only); +void intel_display_reset_debugfs_register(struct intel_display *display); + #endif /* __INTEL_RESET_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index f6cd0a062090..26e59110e743 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -633,7 +633,7 @@ struct dpll { }; struct intel_atomic_state { - struct drm_atomic_state base; + struct drm_atomic_commit base; struct ref_tracker *wakeref; @@ -683,14 +683,15 @@ struct intel_plane_state { struct i915_vma *ggtt_vma; struct i915_vma *dpt_vma; - unsigned long flags; -#define PLANE_HAS_FENCE BIT(0) struct intel_fb_view view; /* for legacy cursor fb unpin */ struct drm_vblank_work unpin_work; + /* fenced region ID (-1 if none) */ + s8 fence_id; + /* Plane pxp decryption state */ bool decrypt; @@ -755,9 +756,7 @@ struct intel_plane_state { }; struct intel_initial_plane_config { - struct intel_framebuffer *fb; - struct intel_memory_region *mem; - resource_size_t phys_base; + struct drm_framebuffer *fb; struct i915_vma *vma; int size; u32 base; @@ -997,7 +996,7 @@ struct intel_casf { struct scaler_filter_coeff coeff[SCALER_FILTER_NUM_TAPS]; u8 strength; u8 win_size; - bool casf_enable; + bool enable; }; struct intel_crtc_state { @@ -1036,7 +1035,7 @@ struct intel_crtc_state { struct drm_property_blob *degamma_lut, *gamma_lut, *ctm; struct drm_display_mode mode, pipe_mode, adjusted_mode; enum drm_scaling_filter scaling_filter; - struct intel_casf casf_params; + u8 sharpness_strength; } hw; /* actual state of LUTs */ @@ -1223,6 +1222,7 @@ struct intel_crtc_state { /* Panel fitter placement and size for Ironlake+ */ struct { + struct intel_casf casf; struct drm_rect dst; bool enabled; bool force_thru; diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c index 081a4092cd13..7d3d63a59882 100644 --- a/drivers/gpu/drm/i915/display/intel_display_wa.c +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c @@ -4,12 +4,12 @@ */ #include +#include #include "intel_de.h" #include "intel_display_core.h" #include "intel_display_regs.h" #include "intel_display_wa.h" -#include "intel_step.h" static void gen11_display_wa_apply(struct intel_display *display) { diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 1667a829e708..0df4f42ba3e3 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -505,6 +505,14 @@ static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) static u32 pipedmc_interrupt_mask(struct intel_display *display) { + /* + * TODO: Check if PIPEDMC_ERROR bit enabling causes errors + * on PTL, enable it if validation passes + */ + if (DISPLAY_VER(display) >= 35) + return PIPEDMC_FLIPQ_PROG_DONE | + PIPEDMC_ERROR; + /* * FIXME PIPEDMC_ERROR not enabled for now due to LNL pipe B * triggering it during the first DC state transition. Figure @@ -1574,10 +1582,10 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, struct intel_dmc *dmc = display_to_dmc(display); u32 dc5_cur_count; - if (DISPLAY_VER(dmc->display) < 14) + if (DISPLAY_VER(display) < 14) return; - dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT); + dc5_cur_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT); if (!start_tracking) dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start; diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c index 73a3101514f3..ddf1a1f1ebc3 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -46,7 +46,7 @@ * atomic variant of waiting MMIO. */ #define DMC_WAKELOCK_CTL_TIMEOUT_US 5000 -#define DMC_WAKELOCK_HOLD_TIME 50 +#define DMC_WAKELOCK_HOLD_TIME 5 /* * Possible non-negative values for the enable_dmc_wl param. diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 4955bd8b11d7..86123614b7ba 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1234,28 +1234,11 @@ int intel_dp_output_format_link_bpp_x16(enum intel_output_format output_format, return fxp_q4_from_int(pipe_bpp); } -static enum intel_output_format -intel_dp_sink_format(struct intel_connector *connector, - const struct drm_display_mode *mode) -{ - const struct drm_display_info *info = &connector->base.display_info; - - if (drm_mode_is_420_only(info, mode)) - return INTEL_OUTPUT_FORMAT_YCBCR420; - - return INTEL_OUTPUT_FORMAT_RGB; -} - static int intel_dp_mode_min_link_bpp_x16(struct intel_connector *connector, - const struct drm_display_mode *mode) + const struct drm_display_mode *mode, + enum intel_output_format output_format) { - enum intel_output_format output_format, sink_format; - - sink_format = intel_dp_sink_format(connector, mode); - - output_format = intel_dp_output_format(connector, sink_format); - return intel_dp_output_format_link_bpp_x16(output_format, intel_dp_min_bpp(output_format)); } @@ -1317,23 +1300,29 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, return MODE_OK; } +static int frl_required_bw(int clock, int bpc, + enum intel_output_format sink_format) +{ + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) + clock /= 2; + + return clock * bpc * 3; +} + static enum drm_mode_status intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_mode *mode, - int target_clock) + int target_clock, + enum intel_output_format sink_format) { struct intel_dp *intel_dp = intel_attached_dp(connector); - const struct drm_display_info *info = &connector->base.display_info; - enum drm_mode_status status; - enum intel_output_format sink_format; /* If PCON supports FRL MODE, check FRL bandwidth constraints */ if (intel_dp->dfp.pcon_max_frl_bw) { - int link_bpp_x16 = intel_dp_mode_min_link_bpp_x16(connector, mode); - int target_bw; - int max_frl_bw; + int target_bw, max_frl_bw; - target_bw = fxp_q4_to_int_roundup(link_bpp_x16) * target_clock; + /* Assume 8bpc for the FRL bandwidth check */ + target_bw = frl_required_bw(target_clock, 8, sink_format); max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; @@ -1350,25 +1339,36 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, target_clock > intel_dp->dfp.max_dotclock) return MODE_CLOCK_HIGH; - sink_format = intel_dp_sink_format(connector, mode); - /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ - status = intel_dp_tmds_clock_valid(intel_dp, target_clock, - 8, sink_format, true); + return intel_dp_tmds_clock_valid(intel_dp, target_clock, + 8, sink_format, true); +} - if (status != MODE_OK) { - if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || - !connector->base.ycbcr_420_allowed || - !drm_mode_is_420_also(info, mode)) - return status; - sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - status = intel_dp_tmds_clock_valid(intel_dp, target_clock, - 8, sink_format, true); - if (status != MODE_OK) - return status; +static enum drm_mode_status +intel_dp_sink_format_valid(struct intel_connector *connector, + const struct drm_display_mode *mode, + enum intel_output_format sink_format) +{ + struct intel_dp *intel_dp = intel_attached_dp(connector); + const struct drm_display_info *info = &connector->base.display_info; + + switch (sink_format) { + case INTEL_OUTPUT_FORMAT_YCBCR420: + if (intel_dp->dfp.min_tmds_clock && + !intel_dp_has_hdmi_sink(intel_dp)) + return MODE_NO_420; + + if (!connector->base.ycbcr_420_allowed || + !drm_mode_is_420(info, mode)) + return MODE_NO_420; + + return MODE_OK; + case INTEL_OUTPUT_FORMAT_RGB: + return MODE_OK; + default: + MISSING_CASE(sink_format); + return MODE_BAD; } - - return MODE_OK; } int intel_dp_max_hdisplay_per_pipe(struct intel_display *display) @@ -1442,15 +1442,14 @@ bool intel_dp_dotclk_valid(struct intel_display *display, } static enum drm_mode_status -intel_dp_mode_valid(struct drm_connector *_connector, - const struct drm_display_mode *mode) +intel_dp_mode_valid_format(struct intel_connector *connector, + const struct drm_display_mode *mode, + int target_clock, + enum intel_output_format sink_format) { - struct intel_display *display = to_intel_display(_connector->dev); - struct intel_connector *connector = to_intel_connector(_connector); + struct intel_display *display = to_intel_display(connector); struct intel_dp *intel_dp = intel_attached_dp(connector); - enum intel_output_format sink_format, output_format; - const struct drm_display_mode *fixed_mode; - int target_clock = mode->clock; + enum intel_output_format output_format; int max_rate, mode_rate, max_lanes, max_link_clock; u16 dsc_max_compressed_bpp = 0; enum drm_mode_status status; @@ -1458,29 +1457,10 @@ intel_dp_mode_valid(struct drm_connector *_connector, int num_joined_pipes; int link_bpp_x16; - status = intel_cpu_transcoder_mode_valid(display, mode); + status = intel_dp_sink_format_valid(connector, mode, sink_format); if (status != MODE_OK) return status; - if (mode->flags & DRM_MODE_FLAG_DBLCLK) - return MODE_H_ILLEGAL; - - if (mode->clock < 10000) - return MODE_CLOCK_LOW; - - if (intel_dp_hdisplay_bad(display, mode->hdisplay)) - return MODE_H_ILLEGAL; - - fixed_mode = intel_panel_fixed_mode(connector, mode); - if (intel_dp_is_edp(intel_dp) && fixed_mode) { - status = intel_panel_mode_valid(connector, mode); - if (status != MODE_OK) - return status; - - target_clock = fixed_mode->clock; - } - - sink_format = intel_dp_sink_format(connector, mode); output_format = intel_dp_output_format(connector, sink_format); max_link_clock = intel_dp_max_link_rate(intel_dp); @@ -1488,7 +1468,8 @@ intel_dp_mode_valid(struct drm_connector *_connector, max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); - link_bpp_x16 = intel_dp_mode_min_link_bpp_x16(connector, mode); + link_bpp_x16 = intel_dp_mode_min_link_bpp_x16(connector, mode, + output_format); mode_rate = intel_dp_link_required(max_link_clock, max_lanes, target_clock, mode->hdisplay, link_bpp_x16, 0); @@ -1578,7 +1559,70 @@ intel_dp_mode_valid(struct drm_connector *_connector, if (status != MODE_OK) return status; - return intel_dp_mode_valid_downstream(connector, mode, target_clock); + return intel_dp_mode_valid_downstream(connector, mode, + target_clock, sink_format); +} + +static enum drm_mode_status +intel_dp_mode_valid(struct drm_connector *_connector, + const struct drm_display_mode *mode) +{ + struct intel_display *display = to_intel_display(_connector->dev); + struct intel_connector *connector = to_intel_connector(_connector); + const struct drm_display_info *info = &connector->base.display_info; + struct intel_dp *intel_dp = intel_attached_dp(connector); + const struct drm_display_mode *fixed_mode; + int target_clock = mode->clock; + enum drm_mode_status status; + + status = intel_cpu_transcoder_mode_valid(display, mode); + if (status != MODE_OK) + return status; + + if (mode->flags & DRM_MODE_FLAG_DBLCLK) + return MODE_H_ILLEGAL; + + if (mode->clock < 10000) + return MODE_CLOCK_LOW; + + if (intel_dp_hdisplay_bad(display, mode->hdisplay)) + return MODE_H_ILLEGAL; + + fixed_mode = intel_panel_fixed_mode(connector, mode); + if (intel_dp_is_edp(intel_dp) && fixed_mode) { + status = intel_panel_mode_valid(connector, mode); + if (status != MODE_OK) + return status; + + target_clock = fixed_mode->clock; + } + + /* + * TODO: Even when using a 4:2:0 sink_format intel_dp_output_format() + * will always choose a 4:4:4 output_format if the DFP can do the + * 4:4:4->4:2:0 conversion for us. Thus a mode may still be rejected + * if we only have enough DP link bandwidth for 4:2:0 but not for + * 4:4:4. Another attempt with an explicit 4:2:0 output_format might + * be needed here. intel_dp_compute_config() would need the same + * logic, or else the actual modeset would still fail. + * + * Also a lot of the checks only depend on output_format but not + * sink_format, so we are potentially doing redundant work by + * testing the same output_format for two different sink_formats. + */ + if (drm_mode_is_420_only(info, mode)) { + status = intel_dp_mode_valid_format(connector, mode, target_clock, + INTEL_OUTPUT_FORMAT_YCBCR420); + } else { + status = intel_dp_mode_valid_format(connector, mode, target_clock, + INTEL_OUTPUT_FORMAT_RGB); + + if (status != MODE_OK && drm_mode_is_420_also(info, mode)) + status = intel_dp_mode_valid_format(connector, mode, target_clock, + INTEL_OUTPUT_FORMAT_YCBCR420); + } + + return status; } bool intel_dp_source_supports_tps3(struct intel_display *display) @@ -3124,6 +3168,21 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; } +static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + if (!intel_dp->as_sdp_supported) + return false; + + /* + * #TODO Implement AS SDP for DP branch device. + */ + if (drm_dp_is_branch(intel_dp->dpcd)) + return false; + + return crtc_state->vrr.enable; +} + static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -3131,7 +3190,12 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported) + /* + * #FIXME: SDP/infoframe updates aren’t truly atomic, and with the new + * cdclk->tc clock crossing we may transiently send a corrupted packet + * if the update lands mid‑transmission. + */ + if (!intel_dp_needs_as_sdp(intel_dp, crtc_state)) return; crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); @@ -3330,41 +3394,59 @@ static int intel_dp_compute_output_format(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state, - bool respect_downstream_limits) + bool respect_downstream_limits, + enum intel_output_format sink_format) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct intel_connector *connector = intel_dp->attached_connector; + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + + if (intel_dp_sink_format_valid(connector, adjusted_mode, + sink_format) != MODE_OK) + return -EINVAL; + + crtc_state->sink_format = sink_format; + crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format); + + return intel_dp_compute_link_config(encoder, crtc_state, conn_state, + respect_downstream_limits); +} + +static int +intel_dp_compute_formats(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + bool respect_downstream_limits) { struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_connector *connector = intel_dp->attached_connector; const struct drm_display_info *info = &connector->base.display_info; const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - bool ycbcr_420_only; int ret; - ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); + if (drm_mode_is_420_only(info, adjusted_mode)) { + ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state, + respect_downstream_limits, + INTEL_OUTPUT_FORMAT_YCBCR420); - if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) { - drm_dbg_kms(display->drm, - "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); - crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; + if (ret && !respect_downstream_limits) { + drm_dbg_kms(display->drm, + "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); + + ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state, + respect_downstream_limits, + INTEL_OUTPUT_FORMAT_RGB); + } } else { - crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode); - } + ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state, + respect_downstream_limits, + INTEL_OUTPUT_FORMAT_RGB); - crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format); - - ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, - respect_downstream_limits); - if (ret) { - if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || - !connector->base.ycbcr_420_allowed || - !drm_mode_is_420_also(info, adjusted_mode)) - return ret; - - crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - crtc_state->output_format = intel_dp_output_format(connector, - crtc_state->sink_format); - ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, - respect_downstream_limits); + if (ret && drm_mode_is_420_also(info, adjusted_mode)) + ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state, + respect_downstream_limits, + INTEL_OUTPUT_FORMAT_YCBCR420); } return ret; @@ -3539,18 +3621,15 @@ intel_dp_compute_config(struct intel_encoder *encoder, * Try to respect downstream TMDS clock limits first, if * that fails assume the user might know something we don't. */ - ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true); + ret = intel_dp_compute_formats(encoder, pipe_config, conn_state, true); if (ret) - ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false); + ret = intel_dp_compute_formats(encoder, pipe_config, conn_state, false); if (ret) return ret; - if ((intel_dp_is_edp(intel_dp) && fixed_mode) || - pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { - ret = intel_pfit_compute_config(pipe_config, conn_state); - if (ret) - return ret; - } + ret = intel_pfit_compute_config(pipe_config, conn_state); + if (ret) + return ret; pipe_config->limited_color_range = intel_dp_limited_color_range(pipe_config, conn_state); @@ -4505,7 +4584,7 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY, &connector->dp.fec_capability) < 0) { - drm_err(display->drm, "Failed to read FEC DPCD register\n"); + drm_dbg_kms(display->drm, "Could not read FEC DPCD register\n"); return; } @@ -6733,7 +6812,7 @@ static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, } static int intel_dp_connector_atomic_check(struct drm_connector *_connector, - struct drm_atomic_state *_state) + struct drm_atomic_commit *_state) { struct intel_connector *connector = to_intel_connector(_connector); struct intel_display *display = to_intel_display(connector); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 54c585c59b90..a26094223f78 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -742,11 +742,14 @@ static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, int link_bw, int rate_select, int lane_count, - bool enhanced_framing) + bool enhanced_framing, bool post_lt_adj_req) { if (enhanced_framing) lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; + if (post_lt_adj_req) + lane_count |= DP_POST_LT_ADJ_REQ_GRANTED; + if (link_bw) { /* DP and eDP v1.3 and earlier link bw set method. */ u8 link_config[] = { link_bw, lane_count }; @@ -825,12 +828,21 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, return DP_TRAINING_PATTERN_2; } +static bool intel_dp_use_post_lt_adj_req(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + return intel_dp->set_idle_link_train && + drm_dp_post_lt_adj_req_supported(intel_dp->dpcd) && + intel_dp_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX) != DP_TRAINING_PATTERN_4; +} + static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, u8 link_bw, u8 rate_select) { intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count, - crtc_state->enhanced_framing); + crtc_state->enhanced_framing, + intel_dp_use_post_lt_adj_req(intel_dp, crtc_state)); } /* @@ -1091,6 +1103,109 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, return channel_eq; } +static bool +intel_dp_post_lt_adj_req(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + u8 link_status[DP_LINK_STATUS_SIZE]; + unsigned long deadline; + bool timeout = false; + bool success = false; + int changes = 0; + + if (!intel_dp_use_post_lt_adj_req(intel_dp, crtc_state)) + return true; + + if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, + link_status) < 0) { + lt_err(intel_dp, DP_PHY_DPRX, "Failed to get link status\n"); + return false; + } + + deadline = jiffies + msecs_to_jiffies_timeout(200); + + for (;;) { + /* Make sure clock is still ok */ + if (!drm_dp_clock_recovery_ok(link_status, + crtc_state->lane_count)) { + intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); + lt_dbg(intel_dp, DP_PHY_DPRX, + "Clock recovery check failed, cannot continue POST_LT_ADJ_REQ\n"); + break; + } + + if (!drm_dp_channel_eq_ok(link_status, + crtc_state->lane_count)) { + intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); + lt_dbg(intel_dp, DP_PHY_DPRX, "Channel EQ check failed. cannot continue POST_LT_ADJ_REQ\n"); + break; + } + + if (!drm_dp_post_lt_adj_req_in_progress(link_status)) { + success = true; + intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); + lt_dbg(intel_dp, DP_PHY_DPRX, + "POST_LT_ADJ_REQ done (%d changes). DP Training successful\n", changes); + break; + } + + if (changes == 6) { + success = true; + intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); + lt_dbg(intel_dp, DP_PHY_DPRX, + "POST_LT_ADJ_REQ limit reached (%d changes). DP Training successful\n", changes); + break; + } + + if (timeout) { + success = true; + intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); + lt_dbg(intel_dp, DP_PHY_DPRX, + "POST_LT_ADJ_REQ timeout reached (%d changes). DP Training successful\n", changes); + break; + } + + fsleep(5000); + + if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, + link_status) < 0) { + lt_err(intel_dp, DP_PHY_DPRX, "Failed to get link status\n"); + break; + } + + /* Update training set as requested by target */ + if (intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status)) { + deadline = jiffies + msecs_to_jiffies_timeout(200); + changes++; + + if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { + lt_err(intel_dp, DP_PHY_DPRX, "Failed to update link training\n"); + break; + } + } else if (time_after(jiffies, deadline)) { + timeout = true; + } + } + + return success; +} + +static void intel_dp_stop_post_lt_adj_req(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + u8 lane_count; + + if (!intel_dp_use_post_lt_adj_req(intel_dp, crtc_state)) + return; + + /* clear DP_POST_LT_ADJ_REQ_GRANTED */ + lane_count = crtc_state->lane_count; + if (crtc_state->enhanced_framing) + lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; + + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count); +} + static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy) { @@ -1389,6 +1504,11 @@ intel_dp_link_train_all_phys(struct intel_dp *intel_dp, intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); intel_dp->set_idle_link_train(intel_dp, crtc_state); + if (ret) + ret = intel_dp_post_lt_adj_req(intel_dp, crtc_state); + + intel_dp_stop_post_lt_adj_req(intel_dp, crtc_state); + return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h index 1ba22ed6db08..33dcbde6a408 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h @@ -21,7 +21,7 @@ void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr); void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, int link_bw, int rate_select, int lane_count, - bool enhanced_framing); + bool enhanced_framing, bool post_lt_adj_req); bool intel_dp_get_adjust_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 887b6de14e46..8f73e01db17c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "intel_atomic.h" #include "intel_audio.h" @@ -56,7 +57,6 @@ #include "intel_link_bw.h" #include "intel_pfit.h" #include "intel_psr.h" -#include "intel_step.h" #include "intel_vdsc.h" #include "intel_vrr.h" #include "skl_scaler.h" @@ -251,7 +251,7 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, int min_bpp_x16, int max_bpp_x16, int bpp_step_x16, bool dsc) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_atomic_state *state = crtc_state->uapi.state; + struct drm_atomic_commit *state = crtc_state->uapi.state; struct drm_dp_mst_topology_state *mst_state = NULL; struct intel_connector *connector = to_intel_connector(conn_state->connector); @@ -721,7 +721,10 @@ static int mst_stream_compute_config(struct intel_encoder *encoder, pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; - pipe_config->has_pch_encoder = false; + + ret = intel_pfit_compute_config(pipe_config, conn_state); + if (ret) + return ret; for_each_joiner_candidate(connector, adjusted_mode, num_joined_pipes) { if (num_joined_pipes > 1) @@ -996,7 +999,7 @@ mst_connector_atomic_topology_check(struct intel_connector *connector, static int mst_connector_atomic_check(struct drm_connector *_connector, - struct drm_atomic_state *_state) + struct drm_atomic_commit *_state) { struct intel_atomic_state *state = to_intel_atomic_state(_state); struct intel_connector *connector = to_intel_connector(_connector); @@ -1603,7 +1606,7 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, static struct drm_encoder * mst_connector_atomic_best_encoder(struct drm_connector *_connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct intel_connector *connector = to_intel_connector(_connector); struct drm_connector_state *connector_state = @@ -2144,7 +2147,7 @@ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp) intel_dp_link_training_set_mode(intel_dp, link_rate, false); intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count, - drm_dp_enhanced_frame_cap(intel_dp->dpcd)); + drm_dp_enhanced_frame_cap(intel_dp->dpcd), false); intel_mst_set_probed_link_params(intel_dp, link_rate, lane_count); } diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c index 7363c9817297..11712a151f72 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c @@ -296,6 +296,24 @@ bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp) return drm_dp_tunnel_bw_alloc_is_enabled(intel_dp->tunnel); } +/** + * intel_dp_tunnel_pr_optimization_supported - Query the PR BW optimization support + * @intel_dp: DP port object + * + * Query whether a DP tunnel supports the PR BW optimization. + * + * Returns %true if the BW allocation mode is supported on @intel_dp. + */ +bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp *intel_dp) +{ + struct intel_display *display = to_intel_display(intel_dp); + + if (DISPLAY_VER(display) < 35) + return false; + + return drm_dp_tunnel_pr_optimization_supported(intel_dp->tunnel); +} + /** * intel_dp_tunnel_suspend - Suspend a DP tunnel connected on a port * @intel_dp: DP port object diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h index 10ab9eebcef6..8273e681a512 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h @@ -32,6 +32,7 @@ void intel_dp_tunnel_resume(struct intel_dp *intel_dp, void intel_dp_tunnel_suspend(struct intel_dp *intel_dp); bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp); +bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp *intel_dp); void intel_dp_tunnel_atomic_cleanup_inherited_state(struct intel_atomic_state *state); @@ -76,6 +77,11 @@ static inline bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp return false; } +static inline bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp *intel_dp) +{ + return false; +} + static inline void intel_dp_tunnel_atomic_cleanup_inherited_state(struct intel_atomic_state *state) {} diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 8027bab2951b..68802b652316 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -301,7 +301,7 @@ void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder, enum dpio_phy phy; int lane, n_entries; - trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(display->drm, !trans)) return; @@ -724,46 +724,46 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, u32 val; int i; - vlv_dpio_get(display->drm); + vlv_dpio_get(display); /* Clear calc init */ - val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS01_DW10(ch)); val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; - vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val); + vlv_dpio_write(display, phy, VLV_PCS01_DW10(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS23_DW10(ch)); val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; - vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val); + vlv_dpio_write(display, phy, VLV_PCS23_DW10(ch), val); } - val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW9(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS01_DW9(ch)); val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; - vlv_dpio_write(display->drm, phy, VLV_PCS01_DW9(ch), val); + vlv_dpio_write(display, phy, VLV_PCS01_DW9(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW9(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS23_DW9(ch)); val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; - vlv_dpio_write(display->drm, phy, VLV_PCS23_DW9(ch), val); + vlv_dpio_write(display, phy, VLV_PCS23_DW9(ch), val); } /* Program swing deemph */ for (i = 0; i < crtc_state->lane_count; i++) { - val = vlv_dpio_read(display->drm, phy, CHV_TX_DW4(ch, i)); + val = vlv_dpio_read(display, phy, CHV_TX_DW4(ch, i)); val &= ~DPIO_SWING_DEEMPH9P5_MASK; val |= DPIO_SWING_DEEMPH9P5(deemph_reg_value); - vlv_dpio_write(display->drm, phy, CHV_TX_DW4(ch, i), val); + vlv_dpio_write(display, phy, CHV_TX_DW4(ch, i), val); } /* Program swing margin */ for (i = 0; i < crtc_state->lane_count; i++) { - val = vlv_dpio_read(display->drm, phy, CHV_TX_DW2(ch, i)); + val = vlv_dpio_read(display, phy, CHV_TX_DW2(ch, i)); val &= ~DPIO_SWING_MARGIN000_MASK; val |= DPIO_SWING_MARGIN000(margin_reg_value); @@ -776,7 +776,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, val &= ~DPIO_UNIQ_TRANS_SCALE_MASK; val |= DPIO_UNIQ_TRANS_SCALE(0x9a); - vlv_dpio_write(display->drm, phy, CHV_TX_DW2(ch, i), val); + vlv_dpio_write(display, phy, CHV_TX_DW2(ch, i), val); } /* @@ -786,26 +786,26 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, * 27 for ch0 and ch1. */ for (i = 0; i < crtc_state->lane_count; i++) { - val = vlv_dpio_read(display->drm, phy, CHV_TX_DW3(ch, i)); + val = vlv_dpio_read(display, phy, CHV_TX_DW3(ch, i)); if (uniq_trans_scale) val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; else val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; - vlv_dpio_write(display->drm, phy, CHV_TX_DW3(ch, i), val); + vlv_dpio_write(display, phy, CHV_TX_DW3(ch, i), val); } /* Start swing calculation */ - val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS01_DW10(ch)); val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; - vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val); + vlv_dpio_write(display, phy, VLV_PCS01_DW10(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS23_DW10(ch)); val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; - vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val); + vlv_dpio_write(display, phy, VLV_PCS23_DW10(ch), val); } - vlv_dpio_put(display->drm); + vlv_dpio_put(display); } static void __chv_data_lane_soft_reset(struct intel_encoder *encoder, @@ -818,38 +818,38 @@ static void __chv_data_lane_soft_reset(struct intel_encoder *encoder, enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); u32 val; - val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW0(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS01_DW0(ch)); if (reset) val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); else val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; - vlv_dpio_write(display->drm, phy, VLV_PCS01_DW0(ch), val); + vlv_dpio_write(display, phy, VLV_PCS01_DW0(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW0(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS23_DW0(ch)); if (reset) val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); else val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; - vlv_dpio_write(display->drm, phy, VLV_PCS23_DW0(ch), val); + vlv_dpio_write(display, phy, VLV_PCS23_DW0(ch), val); } - val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW1(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS01_DW1(ch)); val |= CHV_PCS_REQ_SOFTRESET_EN; if (reset) val &= ~DPIO_PCS_CLK_SOFT_RESET; else val |= DPIO_PCS_CLK_SOFT_RESET; - vlv_dpio_write(display->drm, phy, VLV_PCS01_DW1(ch), val); + vlv_dpio_write(display, phy, VLV_PCS01_DW1(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW1(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS23_DW1(ch)); val |= CHV_PCS_REQ_SOFTRESET_EN; if (reset) val &= ~DPIO_PCS_CLK_SOFT_RESET; else val |= DPIO_PCS_CLK_SOFT_RESET; - vlv_dpio_write(display->drm, phy, VLV_PCS23_DW1(ch), val); + vlv_dpio_write(display, phy, VLV_PCS23_DW1(ch), val); } } @@ -859,9 +859,9 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); - vlv_dpio_get(display->drm); + vlv_dpio_get(display); __chv_data_lane_soft_reset(encoder, crtc_state, reset); - vlv_dpio_put(display->drm); + vlv_dpio_put(display); } void chv_phy_pre_pll_enable(struct intel_encoder *encoder, @@ -887,47 +887,47 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, chv_phy_powergate_lanes(encoder, true, lane_mask); - vlv_dpio_get(display->drm); + vlv_dpio_get(display); /* Assert data lane reset */ __chv_data_lane_soft_reset(encoder, crtc_state, true); /* program left/right clock distribution */ if (pipe != PIPE_B) { - val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0); + val = vlv_dpio_read(display, phy, CHV_CMN_DW5_CH0); val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); if (ch == DPIO_CH0) val |= CHV_BUFLEFTENA1_FORCE; if (ch == DPIO_CH1) val |= CHV_BUFRIGHTENA1_FORCE; - vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val); + vlv_dpio_write(display, phy, CHV_CMN_DW5_CH0, val); } else { - val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1); + val = vlv_dpio_read(display, phy, CHV_CMN_DW1_CH1); val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); if (ch == DPIO_CH0) val |= CHV_BUFLEFTENA2_FORCE; if (ch == DPIO_CH1) val |= CHV_BUFRIGHTENA2_FORCE; - vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val); + vlv_dpio_write(display, phy, CHV_CMN_DW1_CH1, val); } /* program clock channel usage */ - val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW8(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS01_DW8(ch)); val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; if (pipe == PIPE_B) val |= DPIO_PCS_USEDCLKCHANNEL; else val &= ~DPIO_PCS_USEDCLKCHANNEL; - vlv_dpio_write(display->drm, phy, VLV_PCS01_DW8(ch), val); + vlv_dpio_write(display, phy, VLV_PCS01_DW8(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW8(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS23_DW8(ch)); val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; if (pipe == PIPE_B) val |= DPIO_PCS_USEDCLKCHANNEL; else val &= ~DPIO_PCS_USEDCLKCHANNEL; - vlv_dpio_write(display->drm, phy, VLV_PCS23_DW8(ch), val); + vlv_dpio_write(display, phy, VLV_PCS23_DW8(ch), val); } /* @@ -935,14 +935,14 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, * matches the pipe, but here we need to * pick the CL based on the port. */ - val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW19(ch)); + val = vlv_dpio_read(display, phy, CHV_CMN_DW19(ch)); if (pipe == PIPE_B) val |= CHV_CMN_USEDCLKCHANNEL; else val &= ~CHV_CMN_USEDCLKCHANNEL; - vlv_dpio_write(display->drm, phy, CHV_CMN_DW19(ch), val); + vlv_dpio_write(display, phy, CHV_CMN_DW19(ch), val); - vlv_dpio_put(display->drm); + vlv_dpio_put(display); } void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, @@ -956,17 +956,17 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, int data, i, stagger; u32 val; - vlv_dpio_get(display->drm); + vlv_dpio_get(display); /* allow hardware to manage TX FIFO reset source */ - val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS01_DW11(ch)); val &= ~DPIO_LANEDESKEW_STRAP_OVRD; - vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val); + vlv_dpio_write(display, phy, VLV_PCS01_DW11(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS23_DW11(ch)); val &= ~DPIO_LANEDESKEW_STRAP_OVRD; - vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val); + vlv_dpio_write(display, phy, VLV_PCS23_DW11(ch), val); } /* Program Tx lane latency optimal setting*/ @@ -976,7 +976,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, data = 0; else data = (i == 1) ? 0 : DPIO_UPAR; - vlv_dpio_write(display->drm, phy, CHV_TX_DW14(ch, i), data); + vlv_dpio_write(display, phy, CHV_TX_DW14(ch, i), data); } /* Data lane stagger programming */ @@ -991,17 +991,17 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, else stagger = 0x2; - val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS01_DW11(ch)); val |= DPIO_TX2_STAGGER_MASK(0x1f); - vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val); + vlv_dpio_write(display, phy, VLV_PCS01_DW11(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch)); + val = vlv_dpio_read(display, phy, VLV_PCS23_DW11(ch)); val |= DPIO_TX2_STAGGER_MASK(0x1f); - vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val); + vlv_dpio_write(display, phy, VLV_PCS23_DW11(ch), val); } - vlv_dpio_write(display->drm, phy, VLV_PCS01_DW12(ch), + vlv_dpio_write(display, phy, VLV_PCS01_DW12(ch), DPIO_LANESTAGGER_STRAP(stagger) | DPIO_LANESTAGGER_STRAP_OVRD | DPIO_TX1_STAGGER_MASK(0x1f) | @@ -1009,7 +1009,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, DPIO_TX2_STAGGER_MULT(0)); if (crtc_state->lane_count > 2) { - vlv_dpio_write(display->drm, phy, VLV_PCS23_DW12(ch), + vlv_dpio_write(display, phy, VLV_PCS23_DW12(ch), DPIO_LANESTAGGER_STRAP(stagger) | DPIO_LANESTAGGER_STRAP_OVRD | DPIO_TX1_STAGGER_MASK(0x1f) | @@ -1020,7 +1020,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, /* Deassert data lane reset */ __chv_data_lane_soft_reset(encoder, crtc_state, false); - vlv_dpio_put(display->drm); + vlv_dpio_put(display); } void chv_phy_release_cl2_override(struct intel_encoder *encoder) @@ -1042,20 +1042,20 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder, enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe; u32 val; - vlv_dpio_get(display->drm); + vlv_dpio_get(display); /* disable left/right clock distribution */ if (pipe != PIPE_B) { - val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0); + val = vlv_dpio_read(display, phy, CHV_CMN_DW5_CH0); val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); - vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val); + vlv_dpio_write(display, phy, CHV_CMN_DW5_CH0, val); } else { - val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1); + val = vlv_dpio_read(display, phy, CHV_CMN_DW1_CH1); val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); - vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val); + vlv_dpio_write(display, phy, CHV_CMN_DW1_CH1, val); } - vlv_dpio_put(display->drm); + vlv_dpio_put(display); /* * Leave the power down bit cleared for at least one @@ -1079,22 +1079,22 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); - vlv_dpio_get(display->drm); + vlv_dpio_get(display); - vlv_dpio_write(display->drm, phy, VLV_TX_DW5_GRP(ch), 0x00000000); - vlv_dpio_write(display->drm, phy, VLV_TX_DW4_GRP(ch), demph_reg_value); - vlv_dpio_write(display->drm, phy, VLV_TX_DW2_GRP(ch), + vlv_dpio_write(display, phy, VLV_TX_DW5_GRP(ch), 0x00000000); + vlv_dpio_write(display, phy, VLV_TX_DW4_GRP(ch), demph_reg_value); + vlv_dpio_write(display, phy, VLV_TX_DW2_GRP(ch), uniqtranscale_reg_value); - vlv_dpio_write(display->drm, phy, VLV_TX_DW3_GRP(ch), 0x0C782040); + vlv_dpio_write(display, phy, VLV_TX_DW3_GRP(ch), 0x0C782040); if (tx3_demph) - vlv_dpio_write(display->drm, phy, VLV_TX_DW4(ch, 3), tx3_demph); + vlv_dpio_write(display, phy, VLV_TX_DW4(ch, 3), tx3_demph); - vlv_dpio_write(display->drm, phy, VLV_PCS_DW11_GRP(ch), 0x00030000); - vlv_dpio_write(display->drm, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value); - vlv_dpio_write(display->drm, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN); + vlv_dpio_write(display, phy, VLV_PCS_DW11_GRP(ch), 0x00030000); + vlv_dpio_write(display, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value); + vlv_dpio_write(display, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN); - vlv_dpio_put(display->drm); + vlv_dpio_put(display); } void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, @@ -1106,23 +1106,23 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); /* Program Tx lane resets to default */ - vlv_dpio_get(display->drm); + vlv_dpio_get(display); - vlv_dpio_write(display->drm, phy, VLV_PCS_DW0_GRP(ch), + vlv_dpio_write(display, phy, VLV_PCS_DW0_GRP(ch), DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); - vlv_dpio_write(display->drm, phy, VLV_PCS_DW1_GRP(ch), + vlv_dpio_write(display, phy, VLV_PCS_DW1_GRP(ch), DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | DPIO_PCS_CLK_DATAWIDTH_8_10 | DPIO_PCS_CLK_SOFT_RESET); /* Fix up inter-pair skew failure */ - vlv_dpio_write(display->drm, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00); - vlv_dpio_write(display->drm, phy, VLV_TX_DW11_GRP(ch), 0x00001500); - vlv_dpio_write(display->drm, phy, VLV_TX_DW14_GRP(ch), 0x40400000); + vlv_dpio_write(display, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00); + vlv_dpio_write(display, phy, VLV_TX_DW11_GRP(ch), 0x00001500); + vlv_dpio_write(display, phy, VLV_TX_DW14_GRP(ch), 0x40400000); - vlv_dpio_put(display->drm); + vlv_dpio_put(display); } void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, @@ -1137,20 +1137,20 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, enum pipe pipe = crtc->pipe; u32 val; - vlv_dpio_get(display->drm); + vlv_dpio_get(display); /* Enable clock channels for this port */ val = DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; if (pipe == PIPE_B) val |= DPIO_PCS_USEDCLKCHANNEL; val |= 0xc4; - vlv_dpio_write(display->drm, phy, VLV_PCS_DW8_GRP(ch), val); + vlv_dpio_write(display, phy, VLV_PCS_DW8_GRP(ch), val); /* Program lane clock */ - vlv_dpio_write(display->drm, phy, VLV_PCS_DW14_GRP(ch), 0x00760018); - vlv_dpio_write(display->drm, phy, VLV_PCS_DW23_GRP(ch), 0x00400888); + vlv_dpio_write(display, phy, VLV_PCS_DW14_GRP(ch), 0x00760018); + vlv_dpio_write(display, phy, VLV_PCS_DW23_GRP(ch), 0x00400888); - vlv_dpio_put(display->drm); + vlv_dpio_put(display); } void vlv_phy_reset_lanes(struct intel_encoder *encoder, @@ -1161,10 +1161,10 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder, enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); - vlv_dpio_get(display->drm); - vlv_dpio_write(display->drm, phy, VLV_PCS_DW0_GRP(ch), 0x00000000); - vlv_dpio_write(display->drm, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060); - vlv_dpio_put(display->drm); + vlv_dpio_get(display); + vlv_dpio_write(display, phy, VLV_PCS_DW0_GRP(ch), 0x00000000); + vlv_dpio_write(display, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060); + vlv_dpio_put(display); } void vlv_wait_port_ready(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index c7d37e74fbe9..f40807a5566b 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -528,9 +528,9 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state) if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) return; - vlv_dpio_get(display->drm); - tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW3(ch)); - vlv_dpio_put(display->drm); + vlv_dpio_get(display); + tmp = vlv_dpio_read(display, phy, VLV_PLL_DW3(ch)); + vlv_dpio_put(display); clock.m1 = REG_FIELD_GET(DPIO_M1_DIV_MASK, tmp); clock.m2 = REG_FIELD_GET(DPIO_M2_DIV_MASK, tmp); @@ -556,13 +556,13 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state) if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) return; - vlv_dpio_get(display->drm); - cmn_dw13 = vlv_dpio_read(display->drm, phy, CHV_CMN_DW13(ch)); - pll_dw0 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW0(ch)); - pll_dw1 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW1(ch)); - pll_dw2 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW2(ch)); - pll_dw3 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW3(ch)); - vlv_dpio_put(display->drm); + vlv_dpio_get(display); + cmn_dw13 = vlv_dpio_read(display, phy, CHV_CMN_DW13(ch)); + pll_dw0 = vlv_dpio_read(display, phy, CHV_PLL_DW0(ch)); + pll_dw1 = vlv_dpio_read(display, phy, CHV_PLL_DW1(ch)); + pll_dw2 = vlv_dpio_read(display, phy, CHV_PLL_DW2(ch)); + pll_dw3 = vlv_dpio_read(display, phy, CHV_PLL_DW3(ch)); + vlv_dpio_put(display); clock.m1 = REG_FIELD_GET(DPIO_CHV_M1_DIV_MASK, pll_dw1) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; clock.m2 = REG_FIELD_GET(DPIO_CHV_M2_DIV_MASK, pll_dw0) << 22; @@ -1735,7 +1735,7 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, if (!crtc_state->hw.enable) return 0; - ret = display->funcs.dpll->crtc_compute_clock(state, crtc); + ret = display->dpll.funcs->crtc_compute_clock(state, crtc); if (ret) { drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n", crtc->base.base.id, crtc->base.name); @@ -1759,10 +1759,10 @@ int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state, if (!crtc_state->hw.enable || crtc_state->intel_dpll) return 0; - if (!display->funcs.dpll->crtc_get_dpll) + if (!display->dpll.funcs->crtc_get_dpll) return 0; - ret = display->funcs.dpll->crtc_get_dpll(state, crtc); + ret = display->dpll.funcs->crtc_get_dpll(state, crtc); if (ret) { drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", crtc->base.base.id, crtc->base.name); @@ -1776,27 +1776,27 @@ void intel_dpll_init_clock_hook(struct intel_display *display) { if (HAS_LT_PHY(display)) - display->funcs.dpll = &xe3plpd_dpll_funcs; + display->dpll.funcs = &xe3plpd_dpll_funcs; else if (DISPLAY_VER(display) >= 14) - display->funcs.dpll = &mtl_dpll_funcs; + display->dpll.funcs = &mtl_dpll_funcs; else if (display->platform.dg2) - display->funcs.dpll = &dg2_dpll_funcs; + display->dpll.funcs = &dg2_dpll_funcs; else if (DISPLAY_VER(display) >= 9 || HAS_DDI(display)) - display->funcs.dpll = &hsw_dpll_funcs; + display->dpll.funcs = &hsw_dpll_funcs; else if (HAS_PCH_SPLIT(display)) - display->funcs.dpll = &ilk_dpll_funcs; + display->dpll.funcs = &ilk_dpll_funcs; else if (display->platform.cherryview) - display->funcs.dpll = &chv_dpll_funcs; + display->dpll.funcs = &chv_dpll_funcs; else if (display->platform.valleyview) - display->funcs.dpll = &vlv_dpll_funcs; + display->dpll.funcs = &vlv_dpll_funcs; else if (display->platform.g4x) - display->funcs.dpll = &g4x_dpll_funcs; + display->dpll.funcs = &g4x_dpll_funcs; else if (display->platform.pineview) - display->funcs.dpll = &pnv_dpll_funcs; + display->dpll.funcs = &pnv_dpll_funcs; else if (DISPLAY_VER(display) != 2) - display->funcs.dpll = &i9xx_dpll_funcs; + display->dpll.funcs = &i9xx_dpll_funcs; else - display->funcs.dpll = &i8xx_dpll_funcs; + display->dpll.funcs = &i8xx_dpll_funcs; } static bool i9xx_has_pps(struct intel_display *display) @@ -1866,24 +1866,24 @@ static void vlv_pllb_recal_opamp(struct intel_display *display, * PLLB opamp always calibrates to max value of 0x3f, force enable it * and set it to a reasonable value instead. */ - tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW17(ch)); + tmp = vlv_dpio_read(display, phy, VLV_PLL_DW17(ch)); tmp &= 0xffffff00; tmp |= 0x00000030; - vlv_dpio_write(display->drm, phy, VLV_PLL_DW17(ch), tmp); + vlv_dpio_write(display, phy, VLV_PLL_DW17(ch), tmp); - tmp = vlv_dpio_read(display->drm, phy, VLV_REF_DW11); + tmp = vlv_dpio_read(display, phy, VLV_REF_DW11); tmp &= 0x00ffffff; tmp |= 0x8c000000; - vlv_dpio_write(display->drm, phy, VLV_REF_DW11, tmp); + vlv_dpio_write(display, phy, VLV_REF_DW11, tmp); - tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW17(ch)); + tmp = vlv_dpio_read(display, phy, VLV_PLL_DW17(ch)); tmp &= 0xffffff00; - vlv_dpio_write(display->drm, phy, VLV_PLL_DW17(ch), tmp); + vlv_dpio_write(display, phy, VLV_PLL_DW17(ch), tmp); - tmp = vlv_dpio_read(display->drm, phy, VLV_REF_DW11); + tmp = vlv_dpio_read(display, phy, VLV_REF_DW11); tmp &= 0x00ffffff; tmp |= 0xb0000000; - vlv_dpio_write(display->drm, phy, VLV_REF_DW11, tmp); + vlv_dpio_write(display, phy, VLV_REF_DW11, tmp); } static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) @@ -1896,7 +1896,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) enum pipe pipe = crtc->pipe; u32 tmp, coreclk; - vlv_dpio_get(display->drm); + vlv_dpio_get(display); /* See eDP HDMI DPIO driver vbios notes doc */ @@ -1905,15 +1905,15 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) vlv_pllb_recal_opamp(display, phy, ch); /* Set up Tx target for periodic Rcomp update */ - vlv_dpio_write(display->drm, phy, VLV_PCS_DW17_BCAST, 0x0100000f); + vlv_dpio_write(display, phy, VLV_PCS_DW17_BCAST, 0x0100000f); /* Disable target IRef on PLL */ - tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW16(ch)); + tmp = vlv_dpio_read(display, phy, VLV_PLL_DW16(ch)); tmp &= 0x00ffffff; - vlv_dpio_write(display->drm, phy, VLV_PLL_DW16(ch), tmp); + vlv_dpio_write(display, phy, VLV_PLL_DW16(ch), tmp); /* Disable fast lock */ - vlv_dpio_write(display->drm, phy, VLV_CMN_DW0, 0x610); + vlv_dpio_write(display, phy, VLV_CMN_DW0, 0x610); /* Set idtafcrecal before PLL is enabled */ tmp = DPIO_M1_DIV(clock->m1) | @@ -1929,42 +1929,42 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) * Note: don't use the DAC post divider as it seems unstable. */ tmp |= DPIO_S1_DIV(DPIO_S1_DIV_HDMIDP); - vlv_dpio_write(display->drm, phy, VLV_PLL_DW3(ch), tmp); + vlv_dpio_write(display, phy, VLV_PLL_DW3(ch), tmp); tmp |= DPIO_ENABLE_CALIBRATION; - vlv_dpio_write(display->drm, phy, VLV_PLL_DW3(ch), tmp); + vlv_dpio_write(display, phy, VLV_PLL_DW3(ch), tmp); /* Set HBR and RBR LPF coefficients */ if (crtc_state->port_clock == 162000 || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - vlv_dpio_write(display->drm, phy, VLV_PLL_DW18(ch), 0x009f0003); + vlv_dpio_write(display, phy, VLV_PLL_DW18(ch), 0x009f0003); else - vlv_dpio_write(display->drm, phy, VLV_PLL_DW18(ch), 0x00d0000f); + vlv_dpio_write(display, phy, VLV_PLL_DW18(ch), 0x00d0000f); if (intel_crtc_has_dp_encoder(crtc_state)) { /* Use SSC source */ if (pipe == PIPE_A) - vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df40000); + vlv_dpio_write(display, phy, VLV_PLL_DW5(ch), 0x0df40000); else - vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df70000); + vlv_dpio_write(display, phy, VLV_PLL_DW5(ch), 0x0df70000); } else { /* HDMI or VGA */ /* Use bend source */ if (pipe == PIPE_A) - vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df70000); + vlv_dpio_write(display, phy, VLV_PLL_DW5(ch), 0x0df70000); else - vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df40000); + vlv_dpio_write(display, phy, VLV_PLL_DW5(ch), 0x0df40000); } - coreclk = vlv_dpio_read(display->drm, phy, VLV_PLL_DW7(ch)); + coreclk = vlv_dpio_read(display, phy, VLV_PLL_DW7(ch)); coreclk = (coreclk & 0x0000ff00) | 0x01c00000; if (intel_crtc_has_dp_encoder(crtc_state)) coreclk |= 0x01000000; - vlv_dpio_write(display->drm, phy, VLV_PLL_DW7(ch), coreclk); + vlv_dpio_write(display, phy, VLV_PLL_DW7(ch), coreclk); - vlv_dpio_write(display->drm, phy, VLV_PLL_DW19(ch), 0x87871000); + vlv_dpio_write(display, phy, VLV_PLL_DW19(ch), 0x87871000); - vlv_dpio_put(display->drm); + vlv_dpio_put(display); } static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state) @@ -2019,44 +2019,44 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) m2_frac = clock->m2 & 0x3fffff; - vlv_dpio_get(display->drm); + vlv_dpio_get(display); /* p1 and p2 divider */ - vlv_dpio_write(display->drm, phy, CHV_CMN_DW13(ch), + vlv_dpio_write(display, phy, CHV_CMN_DW13(ch), DPIO_CHV_S1_DIV(5) | DPIO_CHV_P1_DIV(clock->p1) | DPIO_CHV_P2_DIV(clock->p2) | DPIO_CHV_K_DIV(1)); /* Feedback post-divider - m2 */ - vlv_dpio_write(display->drm, phy, CHV_PLL_DW0(ch), + vlv_dpio_write(display, phy, CHV_PLL_DW0(ch), DPIO_CHV_M2_DIV(clock->m2 >> 22)); /* Feedback refclk divider - n and m1 */ - vlv_dpio_write(display->drm, phy, CHV_PLL_DW1(ch), + vlv_dpio_write(display, phy, CHV_PLL_DW1(ch), DPIO_CHV_M1_DIV(DPIO_CHV_M1_DIV_BY_2) | DPIO_CHV_N_DIV(1)); /* M2 fraction division */ - vlv_dpio_write(display->drm, phy, CHV_PLL_DW2(ch), + vlv_dpio_write(display, phy, CHV_PLL_DW2(ch), DPIO_CHV_M2_FRAC_DIV(m2_frac)); /* M2 fraction division enable */ - tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW3(ch)); + tmp = vlv_dpio_read(display, phy, CHV_PLL_DW3(ch)); tmp &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); tmp |= DPIO_CHV_FEEDFWD_GAIN(2); if (m2_frac) tmp |= DPIO_CHV_FRAC_DIV_EN; - vlv_dpio_write(display->drm, phy, CHV_PLL_DW3(ch), tmp); + vlv_dpio_write(display, phy, CHV_PLL_DW3(ch), tmp); /* Program digital lock detect threshold */ - tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW9(ch)); + tmp = vlv_dpio_read(display, phy, CHV_PLL_DW9(ch)); tmp &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); tmp |= DPIO_CHV_INT_LOCK_THRESHOLD(0x5); if (!m2_frac) tmp |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; - vlv_dpio_write(display->drm, phy, CHV_PLL_DW9(ch), tmp); + vlv_dpio_write(display, phy, CHV_PLL_DW9(ch), tmp); /* Loop filter */ if (clock->vco == 5400000) { @@ -2081,19 +2081,19 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) DPIO_CHV_GAIN_CTRL(0x3); tribuf_calcntr = 0; } - vlv_dpio_write(display->drm, phy, CHV_PLL_DW6(ch), loopfilter); + vlv_dpio_write(display, phy, CHV_PLL_DW6(ch), loopfilter); - tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW8(ch)); + tmp = vlv_dpio_read(display, phy, CHV_PLL_DW8(ch)); tmp &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; tmp |= DPIO_CHV_TDC_TARGET_CNT(tribuf_calcntr); - vlv_dpio_write(display->drm, phy, CHV_PLL_DW8(ch), tmp); + vlv_dpio_write(display, phy, CHV_PLL_DW8(ch), tmp); /* AFC Recal */ - vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch), - vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch)) | + vlv_dpio_write(display, phy, CHV_CMN_DW14(ch), + vlv_dpio_read(display, phy, CHV_CMN_DW14(ch)) | DPIO_AFC_RECAL); - vlv_dpio_put(display->drm); + vlv_dpio_put(display); } static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) @@ -2106,14 +2106,14 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) enum pipe pipe = crtc->pipe; u32 tmp; - vlv_dpio_get(display->drm); + vlv_dpio_get(display); /* Enable back the 10bit clock to display controller */ - tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch)); + tmp = vlv_dpio_read(display, phy, CHV_CMN_DW14(ch)); tmp |= DPIO_DCLKP_EN; - vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch), tmp); + vlv_dpio_write(display, phy, CHV_CMN_DW14(ch), tmp); - vlv_dpio_put(display->drm); + vlv_dpio_put(display); /* * Need to wait > 100ns between dclkp clock enable bit and PLL enable. @@ -2247,14 +2247,14 @@ void chv_disable_pll(struct intel_display *display, enum pipe pipe) intel_de_write(display, DPLL(display, pipe), val); intel_de_posting_read(display, DPLL(display, pipe)); - vlv_dpio_get(display->drm); + vlv_dpio_get(display); /* Disable 10bit clock to display controller */ - val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch)); + val = vlv_dpio_read(display, phy, CHV_CMN_DW14(ch)); val &= ~DPIO_DCLKP_EN; - vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch), val); + vlv_dpio_write(display, phy, CHV_CMN_DW14(ch), val); - vlv_dpio_put(display->drm); + vlv_dpio_put(display); } void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index f5d4f7146fbc..a9d88cecb338 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -25,6 +25,7 @@ #include #include +#include #include "bxt_dpio_phy_regs.h" #include "intel_cx0_phy.h" @@ -41,7 +42,6 @@ #include "intel_lt_phy.h" #include "intel_mg_phy_regs.h" #include "intel_pch_refclk.h" -#include "intel_step.h" #include "intel_tc.h" /** @@ -134,7 +134,7 @@ intel_atomic_duplicate_dpll_state(struct intel_display *display, } static struct intel_dpll_state * -intel_atomic_get_dpll_state(struct drm_atomic_state *s) +intel_atomic_get_dpll_state(struct drm_atomic_commit *s) { struct intel_atomic_state *state = to_intel_atomic_state(s); struct intel_display *display = to_intel_display(state); diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c index bd281d4b4c05..f103f7cba018 100644 --- a/drivers/gpu/drm/i915/display/intel_dram.c +++ b/drivers/gpu/drm/i915/display/intel_dram.c @@ -9,14 +9,14 @@ #include #include +#include "intel_de.h" #include "intel_display_core.h" #include "intel_display_utils.h" #include "intel_display_regs.h" #include "intel_dram.h" -#include "intel_mchbar_regs.h" +#include "intel_mchbar.h" #include "intel_parent.h" -#include "intel_uncore.h" -#include "vlv_iosf_sb.h" +#include "vlv_sideband.h" struct dram_dimm_info { u16 size; @@ -58,18 +58,15 @@ const char *intel_dram_type_str(enum intel_dram_type type) static enum intel_dram_type pnv_dram_type(struct intel_display *display) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); - - return intel_uncore_read(uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3 ? + return intel_mchbar_read(display, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3 ? INTEL_DRAM_DDR3 : INTEL_DRAM_DDR2; } static unsigned int pnv_mem_freq(struct intel_display *display) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 tmp; - tmp = intel_uncore_read(uncore, CLKCFG); + tmp = intel_mchbar_read(display, CLKCFG); switch (tmp & CLKCFG_MEM_MASK) { case CLKCFG_MEM_533: @@ -85,10 +82,9 @@ static unsigned int pnv_mem_freq(struct intel_display *display) static unsigned int ilk_mem_freq(struct intel_display *display) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); u16 ddrpll; - ddrpll = intel_uncore_read16(uncore, DDRMPLL1); + ddrpll = intel_mchbar_read16(display, DDRMPLL1); switch (ddrpll & 0xff) { case 0xc: return 800000; @@ -109,9 +105,9 @@ static unsigned int chv_mem_freq(struct intel_display *display) { u32 val; - vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK)); - val = vlv_iosf_sb_read(display->drm, VLV_IOSF_SB_CCK, CCK_FUSE_REG); - vlv_iosf_sb_put(display->drm, BIT(VLV_IOSF_SB_CCK)); + vlv_cck_get(display); + val = vlv_cck_read(display, CCK_FUSE_REG); + vlv_cck_put(display); switch ((val >> 2) & 0x7) { case 3: @@ -125,9 +121,9 @@ static unsigned int vlv_mem_freq(struct intel_display *display) { u32 val; - vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_PUNIT)); - val = vlv_iosf_sb_read(display->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS); - vlv_iosf_sb_put(display->drm, BIT(VLV_IOSF_SB_PUNIT)); + vlv_punit_get(display); + val = vlv_punit_read(display, PUNIT_REG_GPU_FREQ_STS); + vlv_punit_put(display); switch ((val >> 6) & 3) { case 0: @@ -158,7 +154,6 @@ unsigned int intel_mem_freq(struct intel_display *display) static unsigned int i9xx_fsb_freq(struct intel_display *display) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 fsb; /* @@ -169,7 +164,7 @@ static unsigned int i9xx_fsb_freq(struct intel_display *display) * don't know which registers have that information, * and all the relevant docs have gone to bit heaven :( */ - fsb = intel_uncore_read(uncore, CLKCFG) & CLKCFG_FSB_MASK; + fsb = intel_mchbar_read(display, CLKCFG) & CLKCFG_FSB_MASK; if (display->platform.pineview || display->platform.mobile) { switch (fsb) { @@ -214,10 +209,9 @@ static unsigned int i9xx_fsb_freq(struct intel_display *display) static unsigned int ilk_fsb_freq(struct intel_display *display) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); u16 fsb; - fsb = intel_uncore_read16(uncore, CSIPLL0) & 0x3ff; + fsb = intel_mchbar_read16(display, CSIPLL0) & 0x3ff; switch (fsb) { case 0x00c: @@ -484,7 +478,6 @@ intel_is_dram_symmetric(const struct dram_channel_info *ch0, static int skl_dram_get_channels_info(struct intel_display *display, struct dram_info *dram_info) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); struct dram_channel_info ch0 = {}, ch1 = {}; u32 val; int ret; @@ -492,12 +485,12 @@ skl_dram_get_channels_info(struct intel_display *display, struct dram_info *dram /* Assume 16Gb+ DIMMs are present until proven otherwise */ dram_info->has_16gb_dimms = true; - val = intel_uncore_read(uncore, SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); + val = intel_mchbar_read(display, SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); ret = skl_dram_get_channel_info(display, &ch0, 0, val); if (ret == 0) dram_info->num_channels++; - val = intel_uncore_read(uncore, SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN); + val = intel_mchbar_read(display, SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN); ret = skl_dram_get_channel_info(display, &ch1, 1, val); if (ret == 0) dram_info->num_channels++; @@ -528,10 +521,9 @@ skl_dram_get_channels_info(struct intel_display *display, struct dram_info *dram static enum intel_dram_type skl_get_dram_type(struct intel_display *display) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 val; - val = intel_uncore_read(uncore, SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN); + val = intel_mchbar_read(display, SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN); switch (val & SKL_DRAM_DDR_TYPE_MASK) { case SKL_DRAM_DDR_TYPE_DDR3: @@ -642,7 +634,6 @@ static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val) static int bxt_get_dram_info(struct intel_display *display, struct dram_info *dram_info) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 val; u8 valid_ranks = 0; int i; @@ -654,7 +645,7 @@ static int bxt_get_dram_info(struct intel_display *display, struct dram_info *dr struct dram_dimm_info dimm; enum intel_dram_type type; - val = intel_uncore_read(uncore, BXT_D_CR_DRP0_DUNIT(i)); + val = intel_mchbar_read(display, BXT_D_CR_DRP0_DUNIT(i)); if (val == 0xFFFFFFFF) continue; @@ -767,8 +758,7 @@ static int gen12_get_dram_info(struct intel_display *display, struct dram_info * static int xelpdp_get_dram_info(struct intel_display *display, struct dram_info *dram_info) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); - u32 val = intel_uncore_read(uncore, MTL_MEM_SS_INFO_GLOBAL); + u32 val = intel_de_read(display, MTL_MEM_SS_INFO_GLOBAL); switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) { case 0: diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 5768619f840f..1c0859d5f829 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -521,6 +521,11 @@ bool intel_fb_needs_64k_phys(u64 modifier) INTEL_PLANE_CAP_NEED64K_PHYS); } +bool intel_fb_needs_cpu_access(const struct drm_framebuffer *fb) +{ + return intel_fb_rc_ccs_cc_plane(fb) >= 0; +} + /** * intel_fb_is_tile4_modifier: Check if a modifier is a tile4 modifier type * @modifier: Modifier to check @@ -876,15 +881,6 @@ static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_pl *tile_height = 1; } -unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane) -{ - unsigned int tile_width, tile_height; - - intel_tile_dims(fb, color_plane, &tile_width, &tile_height); - - return fb->pitches[color_plane] * tile_height; -} - unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, int color_plane, unsigned int height) @@ -1261,6 +1257,10 @@ static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) if (intel_fb_is_ccs_modifier(fb->modifier)) return false; + /* TODO implement remapping with DPT */ + if (intel_fb_uses_dpt(fb)) + return false; + /* Linear needs a page aligned stride for remapping */ if (fb->modifier == DRM_FORMAT_MOD_LINEAR) { unsigned int alignment = intel_tile_size(display) - 1; @@ -1274,7 +1274,7 @@ static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) return true; } -bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb) +static bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb) { struct intel_display *display = to_intel_display(fb->base.dev); @@ -1287,9 +1287,9 @@ bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - return DISPLAY_VER(display) < 4 || + return intel_plane_needs_fence(display) || (plane->fbc && !plane_state->no_fbc_reason && - plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); + i915_gtt_view_is_normal(&plane_state->view.gtt)); } static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation) @@ -1511,7 +1511,7 @@ static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_p plane_view_height_tiles(fb, color_plane, dims, y)); } - if (view->gtt.type == I915_GTT_VIEW_ROTATED) { + if (i915_gtt_view_is_rotated(&view->gtt)) { drm_WARN_ON(display->drm, remap_info->linear); check_array_bounds(display, view->gtt.rotated.plane, color_plane); @@ -1536,7 +1536,7 @@ static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_p /* rotate the tile dimensions to match the GTT view */ swap(tile_width, tile_height); } else { - drm_WARN_ON(display->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED); + drm_WARN_ON(display->drm, !i915_gtt_view_is_remapped(&view->gtt)); check_array_bounds(display, view->gtt.remapped.plane, color_plane); @@ -1632,13 +1632,14 @@ calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane, static void intel_fb_view_init(struct intel_display *display, struct intel_fb_view *view, - enum i915_gtt_view_type view_type) + enum i915_gtt_view_type view_type, + const struct intel_framebuffer *fb) { memset(view, 0, sizeof(*view)); view->gtt.type = view_type; - if (view_type == I915_GTT_VIEW_REMAPPED && - (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)) + if (i915_gtt_view_is_remapped(&view->gtt) && + intel_fb_needs_pot_stride_remap(fb)) view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE; } @@ -1704,16 +1705,19 @@ int intel_fill_fb_info(struct intel_display *display, struct intel_framebuffer * int i, num_planes = fb->base.format->num_planes; unsigned int tile_size = intel_tile_size(display); - intel_fb_view_init(display, &fb->normal_view, I915_GTT_VIEW_NORMAL); + intel_fb_view_init(display, &fb->normal_view, + I915_GTT_VIEW_NORMAL, fb); drm_WARN_ON(display->drm, intel_fb_supports_90_270_rotation(fb) && intel_fb_needs_pot_stride_remap(fb)); if (intel_fb_supports_90_270_rotation(fb)) - intel_fb_view_init(display, &fb->rotated_view, I915_GTT_VIEW_ROTATED); + intel_fb_view_init(display, &fb->rotated_view, + I915_GTT_VIEW_ROTATED, fb); if (intel_fb_needs_pot_stride_remap(fb)) - intel_fb_view_init(display, &fb->remapped_view, I915_GTT_VIEW_REMAPPED); + intel_fb_view_init(display, &fb->remapped_view, + I915_GTT_VIEW_REMAPPED, fb); for (i = 0; i < num_planes; i++) { struct fb_plane_view_dims view_dims; @@ -1840,8 +1844,9 @@ static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) u32 gtt_offset = 0; intel_fb_view_init(display, &plane_state->view, - drm_rotation_90_or_270(rotation) ? I915_GTT_VIEW_ROTATED : - I915_GTT_VIEW_REMAPPED); + drm_rotation_90_or_270(rotation) ? + I915_GTT_VIEW_ROTATED : I915_GTT_VIEW_REMAPPED, + intel_fb); src_x = plane_state->uapi.src.x1 >> 16; src_y = plane_state->uapi.src.y1 >> 16; diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 22514d5f2bb6..0a027e2595b2 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -38,6 +38,7 @@ bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier); bool intel_fb_is_mc_ccs_modifier(u64 modifier); bool intel_fb_needs_64k_phys(u64 modifier); bool intel_fb_is_tile4_modifier(u64 modifier); +bool intel_fb_needs_cpu_access(const struct drm_framebuffer *fb); bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane); int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb); @@ -62,7 +63,6 @@ int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane); unsigned int intel_tile_size(struct intel_display *display); unsigned int intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane); unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane); -unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane); unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, int color_plane, unsigned int height); @@ -78,7 +78,6 @@ u32 intel_plane_compute_aligned_offset(int *x, int *y, const struct intel_plane_state *plane_state, int color_plane); -bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb); bool intel_plane_uses_fence(const struct intel_plane_state *plane_state); bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb); diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h b/drivers/gpu/drm/i915/display/intel_fb_pin.h index 81ab79da1af7..5825503c38ea 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.h +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h @@ -8,22 +8,29 @@ #include -struct drm_framebuffer; +struct drm_gem_object; struct i915_vma; struct intel_plane_state; struct i915_gtt_view; struct iosys_map; -struct i915_vma * -intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, - const struct i915_gtt_view *view, - unsigned int alignment, - unsigned int phys_alignment, - unsigned int vtd_guard, - bool uses_fence, - unsigned long *out_flags); +struct intel_fb_pin_params { + const struct i915_gtt_view *view; + unsigned int alignment; + unsigned int phys_alignment; + unsigned int vtd_guard; + bool needs_cpu_lmem_access; + bool needs_low_address; + bool needs_physical; + bool needs_fence; +}; -void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags); +struct i915_vma * +intel_fb_pin_to_ggtt(struct drm_gem_object *obj, + const struct intel_fb_pin_params *pin_params, + int *out_fence_id); + +void intel_fb_unpin_vma(struct i915_vma *vma, int fence_id); int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, const struct intel_plane_state *old_plane_state); diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index ea0ce00c8474..a7d02dd6ca96 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -44,6 +44,7 @@ #include #include #include +#include #include "i9xx_plane_regs.h" #include "intel_de.h" @@ -58,7 +59,6 @@ #include "intel_fbc_regs.h" #include "intel_frontbuffer.h" #include "intel_parent.h" -#include "intel_step.h" #define for_each_fbc_id(__display, __fbc_id) \ for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \ @@ -1458,13 +1458,10 @@ static void intel_fbc_update_state(struct intel_atomic_state *state, fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state); - drm_WARN_ON(display->drm, plane_state->flags & PLANE_HAS_FENCE && + drm_WARN_ON(display->drm, plane_state->fence_id >= 0 && !intel_fbc_has_fences(display)); - if (plane_state->flags & PLANE_HAS_FENCE) - fbc_state->fence_id = intel_parent_vma_fence_id(display, plane_state->ggtt_vma); - else - fbc_state->fence_id = -1; + fbc_state->fence_id = plane_state->fence_id; fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state); fbc_state->cfb_size = intel_fbc_cfb_size(plane_state); @@ -1487,9 +1484,7 @@ static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state) * so have no fence associated with it) due to aperture constraints * at the time of pinning. */ - return DISPLAY_VER(display) >= 9 || - (plane_state->flags & PLANE_HAS_FENCE && - intel_parent_vma_fence_id(display, plane_state->ggtt_vma) != -1); + return DISPLAY_VER(display) >= 9 || plane_state->fence_id >= 0; } static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state) diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index bdaaf3edba0c..9ab0ac49abb7 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -54,13 +54,12 @@ #include "intel_fb.h" #include "intel_fb_pin.h" #include "intel_fbdev.h" -#include "intel_fbdev_fb.h" #include "intel_frontbuffer.h" +#include "intel_plane.h" struct intel_fbdev { struct intel_framebuffer *fb; struct i915_vma *vma; - unsigned long vma_flags; }; static struct intel_fbdev *to_intel_fbdev(struct drm_fb_helper *fb_helper) @@ -141,7 +140,7 @@ static void intel_fbdev_fb_destroy(struct fb_info *info) * the info->screen_base mmaping. Leaking the VMA is simpler than * trying to rectify all the possible error paths leading here. */ - intel_fb_unpin_vma(ifbdev->vma, ifbdev->vma_flags); + intel_fb_unpin_vma(ifbdev->vma, -1); drm_framebuffer_remove(fb_helper->fb); drm_client_release(&fb_helper->client); @@ -204,7 +203,8 @@ static const struct drm_fb_helper_funcs intel_fb_helper_funcs = { .fb_set_suspend = intelfb_set_suspend, }; -static void intel_fbdev_fill_mode_cmd(struct drm_fb_helper_surface_size *sizes, +static void intel_fbdev_fill_mode_cmd(struct intel_display *display, + struct drm_fb_helper_surface_size *sizes, struct drm_mode_fb_cmd2 *mode_cmd) { /* we don't do packed 24bpp */ @@ -215,7 +215,7 @@ static void intel_fbdev_fill_mode_cmd(struct drm_fb_helper_surface_size *sizes, mode_cmd->width = sizes->surface_width; mode_cmd->height = sizes->surface_height; - mode_cmd->pitches[0] = intel_fbdev_fb_pitch_align(mode_cmd->width * DIV_ROUND_UP(sizes->surface_bpp, 8)); + mode_cmd->pitches[0] = intel_bo_fbdev_pitch_align(display, mode_cmd->width * DIV_ROUND_UP(sizes->surface_bpp, 8)); mode_cmd->pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, sizes->surface_depth); mode_cmd->modifier[0] = DRM_FORMAT_MOD_LINEAR; @@ -230,12 +230,12 @@ __intel_fbdev_fb_alloc(struct intel_display *display, struct drm_gem_object *obj; int size; - intel_fbdev_fill_mode_cmd(sizes, &mode_cmd); + intel_fbdev_fill_mode_cmd(display, sizes, &mode_cmd); size = mode_cmd.pitches[0] * mode_cmd.height; size = PAGE_ALIGN(size); - obj = intel_fbdev_fb_bo_create(display->drm, size); + obj = intel_bo_fbdev_create(display, size); if (IS_ERR(obj)) { fb = ERR_CAST(obj); goto err; @@ -247,7 +247,7 @@ __intel_fbdev_fb_alloc(struct intel_display *display, mode_cmd.modifier[0]), &mode_cmd); if (IS_ERR(fb)) { - intel_fbdev_fb_bo_destroy(obj); + intel_bo_fbdev_destroy(obj); goto err; } @@ -265,11 +265,11 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, { struct intel_display *display = to_intel_display(helper->dev); struct intel_fbdev *ifbdev = to_intel_fbdev(helper); + struct intel_fb_pin_params pin_params = {}; struct intel_framebuffer *fb = ifbdev->fb; struct fb_info *info = helper->info; struct ref_tracker *wakeref; struct i915_vma *vma; - unsigned long flags = 0; bool prealloc = false; struct drm_gem_object *obj; int ret; @@ -306,15 +306,20 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, sizes->fb_height = fb->base.height; } + obj = intel_fb_bo(&fb->base); + /* Pin the GGTT vma for our access via info->screen_base. * This also validates that any existing fb inherited from the * BIOS is suitable for own access. */ - vma = intel_fb_pin_to_ggtt(&fb->base, &fb->normal_view.gtt, - fb->min_alignment, 0, - intel_fb_view_vtd_guard(&fb->base, &fb->normal_view, - DRM_MODE_ROTATE_0), - false, &flags); + pin_params.view = &fb->normal_view.gtt; + pin_params.alignment = fb->min_alignment; + pin_params.vtd_guard = intel_fb_view_vtd_guard(&fb->base, + &fb->normal_view, + DRM_MODE_ROTATE_0); + pin_params.needs_low_address = intel_plane_needs_low_address(display); + + vma = intel_fb_pin_to_ggtt(obj, &pin_params, NULL); if (IS_ERR(vma)) { ret = PTR_ERR(vma); goto out_unlock; @@ -325,9 +330,7 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, info->fbops = &intelfb_ops; - obj = intel_fb_bo(&fb->base); - - ret = intel_fbdev_fb_fill_info(display->drm, info, obj, vma); + ret = intel_bo_fbdev_fill_info(obj, info, vma); if (ret) goto out_unpin; @@ -345,14 +348,13 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, drm_dbg_kms(display->drm, "allocated %dx%d fb\n", fb->base.width, fb->base.height); ifbdev->fb = fb; ifbdev->vma = vma; - ifbdev->vma_flags = flags; intel_display_rpm_put(display, wakeref); return 0; out_unpin: - intel_fb_unpin_vma(vma, flags); + intel_fb_unpin_vma(vma, -1); out_unlock: intel_display_rpm_put(display, wakeref); diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c deleted file mode 100644 index 6f84eb6355de..000000000000 --- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2023 Intel Corporation - */ - -#include - -#include - -#include "gem/i915_gem_lmem.h" - -#include "i915_drv.h" -#include "intel_fbdev_fb.h" - -u32 intel_fbdev_fb_pitch_align(u32 stride) -{ - return ALIGN(stride, 64); -} - -bool intel_fbdev_fb_prefer_stolen(struct drm_device *drm, unsigned int size) -{ - struct drm_i915_private *i915 = to_i915(drm); - - /* Skip stolen on MTL as Wa_22018444074 mitigation. */ - if (IS_METEORLAKE(i915)) - return false; - - /* - * If the FB is too big, just don't use it since fbdev is not very - * important and we should probably use that space with FBC or other - * features. - */ - return i915->dsm.usable_size >= size * 2; -} - -struct drm_gem_object *intel_fbdev_fb_bo_create(struct drm_device *drm, int size) -{ - struct drm_i915_private *i915 = to_i915(drm); - struct drm_i915_gem_object *obj; - - obj = ERR_PTR(-ENODEV); - if (HAS_LMEM(i915)) { - obj = i915_gem_object_create_lmem(i915, size, - I915_BO_ALLOC_CONTIGUOUS | - I915_BO_ALLOC_USER); - } else { - if (intel_fbdev_fb_prefer_stolen(drm, size)) - obj = i915_gem_object_create_stolen(i915, size); - else - drm_info(drm, "Allocating fbdev: Stolen memory not preferred.\n"); - - if (IS_ERR(obj)) - obj = i915_gem_object_create_shmem(i915, size); - } - - if (IS_ERR(obj)) { - drm_err(drm, "failed to allocate framebuffer (%pe)\n", obj); - return ERR_PTR(-ENOMEM); - } - - return &obj->base; -} - -void intel_fbdev_fb_bo_destroy(struct drm_gem_object *obj) -{ - drm_gem_object_put(obj); -} - -int intel_fbdev_fb_fill_info(struct drm_device *drm, struct fb_info *info, - struct drm_gem_object *_obj, struct i915_vma *vma) -{ - struct drm_i915_private *i915 = to_i915(drm); - struct drm_i915_gem_object *obj = to_intel_bo(_obj); - struct i915_gem_ww_ctx ww; - void __iomem *vaddr; - int ret; - - if (i915_gem_object_is_lmem(obj)) { - struct intel_memory_region *mem = obj->mm.region; - - /* Use fbdev's framebuffer from lmem for discrete */ - info->fix.smem_start = - (unsigned long)(mem->io.start + - i915_gem_object_get_dma_address(obj, 0) - - mem->region.start); - info->fix.smem_len = obj->base.size; - } else { - struct i915_ggtt *ggtt = to_gt(i915)->ggtt; - - /* Our framebuffer is the entirety of fbdev's system memory */ - info->fix.smem_start = - (unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma)); - info->fix.smem_len = vma->size; - } - - for_i915_gem_ww(&ww, ret, false) { - ret = i915_gem_object_lock(vma->obj, &ww); - - if (ret) - continue; - - vaddr = i915_vma_pin_iomap(vma); - if (IS_ERR(vaddr)) { - drm_err(drm, - "Failed to remap framebuffer into virtual memory (%pe)\n", vaddr); - ret = PTR_ERR(vaddr); - continue; - } - } - - if (ret) - return ret; - - info->screen_base = vaddr; - info->screen_size = intel_bo_to_drm_bo(obj)->size; - - return 0; -} diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.h b/drivers/gpu/drm/i915/display/intel_fbdev_fb.h deleted file mode 100644 index 34ed2b9c2b4f..000000000000 --- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2023 Intel Corporation - */ - -#ifndef __INTEL_FBDEV_FB_H__ -#define __INTEL_FBDEV_FB_H__ - -#include - -struct drm_device; -struct drm_gem_object; -struct drm_mode_fb_cmd2; -struct fb_info; -struct i915_vma; - -u32 intel_fbdev_fb_pitch_align(u32 stride); -struct drm_gem_object *intel_fbdev_fb_bo_create(struct drm_device *drm, int size); -void intel_fbdev_fb_bo_destroy(struct drm_gem_object *obj); -int intel_fbdev_fb_fill_info(struct drm_device *drm, struct fb_info *info, - struct drm_gem_object *obj, struct i915_vma *vma); -bool intel_fbdev_fb_prefer_stolen(struct drm_device *drm, unsigned int size); - -#endif diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 24ce8a7842c7..cd4c38691aed 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -11,6 +11,7 @@ #include "intel_atomic.h" #include "intel_crtc.h" #include "intel_ddi.h" +#include "intel_ddi_buf_trans.h" #include "intel_de.h" #include "intel_display_regs.h" #include "intel_display_types.h" @@ -122,7 +123,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc, { struct intel_display *display = to_intel_display(crtc); - display->funcs.fdi->fdi_link_train(crtc, crtc_state); + display->fdi.funcs->fdi_link_train(crtc, crtc_state); } /** @@ -185,7 +186,7 @@ static int ilk_check_fdi_lanes(struct intel_display *display, enum pipe pipe, struct intel_crtc_state *pipe_config, enum pipe *pipe_to_reduce) { - struct drm_atomic_state *state = pipe_config->uapi.state; + struct drm_atomic_commit *state = pipe_config->uapi.state; struct intel_crtc *other_crtc; struct intel_crtc_state *other_crtc_state; @@ -852,7 +853,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, u32 temp, i, rx_ctl_val; int n_entries; - encoder->get_buf_trans(encoder, crtc_state, &n_entries); + intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); hsw_prepare_dp_ddi_buffers(encoder, crtc_state); @@ -1108,11 +1109,11 @@ void intel_fdi_init_hook(struct intel_display *display) { if (display->platform.ironlake) { - display->funcs.fdi = &ilk_funcs; + display->fdi.funcs = &ilk_funcs; } else if (display->platform.sandybridge) { - display->funcs.fdi = &gen6_funcs; + display->fdi.funcs = &gen6_funcs; } else if (display->platform.ivybridge) { /* FIXME: detect B0+ stepping and use auto training */ - display->funcs.fdi = &ivb_funcs; + display->fdi.funcs = &ivb_funcs; } } diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c b/drivers/gpu/drm/i915/display/intel_flipq.c index 253dc2e96d2d..333d28faf4ca 100644 --- a/drivers/gpu/drm/i915/display/intel_flipq.c +++ b/drivers/gpu/drm/i915/display/intel_flipq.c @@ -6,6 +6,7 @@ #include #include +#include #include "intel_crtc.h" #include "intel_de.h" @@ -17,7 +18,6 @@ #include "intel_dmc_regs.h" #include "intel_dsb.h" #include "intel_flipq.h" -#include "intel_step.h" #include "intel_vblank.h" #include "intel_vrr.h" diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 892eab4b6f92..982f698e9814 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "intel_connector.h" #include "intel_de.h" @@ -33,7 +34,6 @@ #include "intel_hdcp_regs.h" #include "intel_hdcp_shim.h" #include "intel_parent.h" -#include "intel_step.h" #define USE_HDCP_GSC(__display) (DISPLAY_VER(__display) >= 14) @@ -72,6 +72,7 @@ intel_hdcp_adjust_hdcp_line_rekeying(struct intel_encoder *encoder, static int intel_conn_to_vcpi(struct intel_atomic_state *state, struct intel_connector *connector) { + struct intel_display *display = to_intel_display(state); struct drm_dp_mst_topology_mgr *mgr; struct drm_dp_mst_atomic_payload *payload; struct drm_dp_mst_topology_state *mst_state; @@ -79,13 +80,19 @@ static int intel_conn_to_vcpi(struct intel_atomic_state *state, /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */ if (!connector->mst.port) return 0; - mgr = connector->mst.port->mgr; - drm_modeset_lock(&mgr->base.lock, state->base.acquire_ctx); - mst_state = to_drm_dp_mst_topology_state(mgr->base.state); - payload = drm_atomic_get_mst_payload_state(mst_state, connector->mst.port); - if (drm_WARN_ON(mgr->dev, !payload)) + mgr = connector->mst.port->mgr; + mst_state = drm_atomic_get_new_mst_topology_state(&state->base, mgr); + if (!mst_state) { + drm_dbg_kms(display->drm, "MST topology still not created\n"); return 0; + } + + payload = drm_atomic_get_mst_payload_state(mst_state, connector->mst.port); + if (!payload) { + drm_dbg_kms(display->drm, "MST Payload not present\n"); + return 0; + } return payload->vcpi; } diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 05e898d10a2b..3d66b9ed1d90 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2021,6 +2021,51 @@ intel_hdmi_mode_clock_valid(struct drm_connector *_connector, int clock, return status; } +static enum drm_mode_status +intel_hdmi_sink_format_valid(struct intel_connector *connector, + const struct drm_display_mode *mode, + bool has_hdmi_sink, + enum intel_output_format sink_format) +{ + const struct drm_display_info *info = &connector->base.display_info; + + switch (sink_format) { + case INTEL_OUTPUT_FORMAT_YCBCR420: + if (!has_hdmi_sink || + !connector->base.ycbcr_420_allowed || + !drm_mode_is_420(info, mode)) + return MODE_NO_420; + + return MODE_OK; + case INTEL_OUTPUT_FORMAT_RGB: + return MODE_OK; + default: + MISSING_CASE(sink_format); + return MODE_BAD; + } +} + +static enum drm_mode_status +intel_hdmi_mode_valid_format(struct intel_connector *connector, + const struct drm_display_mode *mode, + int clock, bool has_hdmi_sink, + enum intel_output_format sink_format) +{ + struct intel_display *display = to_intel_display(connector); + enum drm_mode_status status; + + status = intel_hdmi_sink_format_valid(connector, mode, + has_hdmi_sink, sink_format); + if (status != MODE_OK) + return status; + + status = intel_pfit_mode_valid(display, mode, sink_format, 0); + if (status != MODE_OK) + return status; + + return intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format); +} + static enum drm_mode_status intel_hdmi_mode_valid(struct drm_connector *_connector, const struct drm_display_mode *mode) @@ -2028,12 +2073,11 @@ intel_hdmi_mode_valid(struct drm_connector *_connector, struct intel_connector *connector = to_intel_connector(_connector); struct intel_display *display = to_intel_display(connector); struct intel_hdmi *hdmi = intel_attached_hdmi(connector); + const struct drm_display_info *info = &connector->base.display_info; enum drm_mode_status status; int clock = mode->clock; int max_dotclk = display->cdclk.max_dotclk_freq; bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->base.state); - bool ycbcr_420_only; - enum intel_output_format sink_format; status = intel_cpu_transcoder_mode_valid(display, mode); if (status != MODE_OK) @@ -2060,31 +2104,20 @@ intel_hdmi_mode_valid(struct drm_connector *_connector, if (clock > 600000) return MODE_CLOCK_HIGH; - ycbcr_420_only = drm_mode_is_420_only(&connector->base.display_info, mode); + if (drm_mode_is_420_only(info, mode)) { + status = intel_hdmi_mode_valid_format(connector, mode, clock, has_hdmi_sink, + INTEL_OUTPUT_FORMAT_YCBCR420); + } else { + status = intel_hdmi_mode_valid_format(connector, mode, clock, has_hdmi_sink, + INTEL_OUTPUT_FORMAT_RGB); - if (ycbcr_420_only) - sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - else - sink_format = INTEL_OUTPUT_FORMAT_RGB; - - status = intel_pfit_mode_valid(display, mode, sink_format, 0); + if (status != MODE_OK && drm_mode_is_420_also(info, mode)) + status = intel_hdmi_mode_valid_format(connector, mode, clock, has_hdmi_sink, + INTEL_OUTPUT_FORMAT_YCBCR420); + } if (status != MODE_OK) return status; - status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format); - if (status != MODE_OK) { - if (ycbcr_420_only || - !connector->base.ycbcr_420_allowed || - !drm_mode_is_420_also(&connector->base.display_info, mode)) - return status; - - sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, - sink_format); - if (status != MODE_OK) - return status; - } - return intel_mode_valid_max_plane_size(display, mode, 1); } @@ -2241,20 +2274,6 @@ static bool intel_hdmi_has_audio(struct intel_encoder *encoder, return intel_conn_state->force_audio == HDMI_AUDIO_ON; } -static enum intel_output_format -intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state, - struct intel_connector *connector, - bool ycbcr_420_output) -{ - if (!crtc_state->has_hdmi_sink) - return INTEL_OUTPUT_FORMAT_RGB; - - if (connector->base.ycbcr_420_allowed && ycbcr_420_output) - return INTEL_OUTPUT_FORMAT_YCBCR420; - else - return INTEL_OUTPUT_FORMAT_RGB; -} - static enum intel_output_format intel_hdmi_output_format(const struct intel_crtc_state *crtc_state) { @@ -2263,37 +2282,55 @@ intel_hdmi_output_format(const struct intel_crtc_state *crtc_state) static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, - const struct drm_connector_state *conn_state, - bool respect_downstream_limits) + struct intel_connector *connector, + bool respect_downstream_limits, + enum intel_output_format sink_format) +{ + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + + if (intel_hdmi_sink_format_valid(connector, adjusted_mode, + crtc_state->has_hdmi_sink, sink_format) != MODE_OK) + return -EINVAL; + + crtc_state->sink_format = sink_format; + crtc_state->output_format = intel_hdmi_output_format(crtc_state); + + return intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); +} + +static int intel_hdmi_compute_formats(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state, + bool respect_downstream_limits) { struct intel_display *display = to_intel_display(encoder); struct intel_connector *connector = to_intel_connector(conn_state->connector); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; const struct drm_display_info *info = &connector->base.display_info; - bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); int ret; - crtc_state->sink_format = - intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only); + if (drm_mode_is_420_only(info, adjusted_mode)) { + ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector, + respect_downstream_limits, + INTEL_OUTPUT_FORMAT_YCBCR420); - if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) { - drm_dbg_kms(display->drm, - "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); - crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; - } + if (ret && !respect_downstream_limits) { + drm_dbg_kms(display->drm, + "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); - crtc_state->output_format = intel_hdmi_output_format(crtc_state); - ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); - if (ret) { - if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || - !crtc_state->has_hdmi_sink || - !connector->base.ycbcr_420_allowed || - !drm_mode_is_420_also(info, adjusted_mode)) - return ret; + ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector, + respect_downstream_limits, + INTEL_OUTPUT_FORMAT_RGB); + } + } else { + ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector, + respect_downstream_limits, + INTEL_OUTPUT_FORMAT_RGB); - crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - crtc_state->output_format = intel_hdmi_output_format(crtc_state); - ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); + if (ret && drm_mode_is_420_also(info, adjusted_mode)) + ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector, + respect_downstream_limits, + INTEL_OUTPUT_FORMAT_YCBCR420); } return ret; @@ -2370,9 +2407,9 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, * Try to respect downstream TMDS clock limits first, if * that fails assume the user might know something we don't. */ - ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true); + ret = intel_hdmi_compute_formats(encoder, pipe_config, conn_state, true); if (ret) - ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false); + ret = intel_hdmi_compute_formats(encoder, pipe_config, conn_state, false); if (ret) { drm_dbg_kms(display->drm, "unsupported HDMI clock (%d kHz), rejecting mode\n", @@ -2380,11 +2417,9 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, return ret; } - if (intel_hdmi_is_ycbcr420(pipe_config)) { - ret = intel_pfit_compute_config(pipe_config, conn_state); - if (ret) - return ret; - } + ret = intel_pfit_compute_config(pipe_config, conn_state); + if (ret) + return ret; pipe_config->limited_color_range = intel_hdmi_limited_color_range(pipe_config, conn_state); @@ -2656,7 +2691,7 @@ static const struct drm_connector_funcs intel_hdmi_connector_funcs = { }; static int intel_hdmi_connector_atomic_check(struct drm_connector *_connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct intel_connector *connector = to_intel_connector(_connector); struct intel_display *display = to_intel_display(connector); diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c index 8865cb2ac569..539fd555edce 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c @@ -1420,7 +1420,7 @@ static void i915_hpd_irq_setup(struct intel_display *display) hotplug_en); } -struct intel_hotplug_funcs { +struct intel_hotplug_irq_funcs { /* Enable HPD sense and interrupts for all present encoders */ void (*hpd_irq_setup)(struct intel_display *display); /* Enable HPD sense for a single encoder */ @@ -1428,7 +1428,7 @@ struct intel_hotplug_funcs { }; #define HPD_FUNCS(platform) \ -static const struct intel_hotplug_funcs platform##_hpd_funcs = { \ +static const struct intel_hotplug_irq_funcs platform##_hpd_funcs = { \ .hpd_irq_setup = platform##_hpd_irq_setup, \ .hpd_enable_detection = platform##_hpd_enable_detection, \ } @@ -1447,8 +1447,8 @@ void intel_hpd_enable_detection(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - if (display->funcs.hotplug) - display->funcs.hotplug->hpd_enable_detection(encoder); + if (display->hotplug.funcs) + display->hotplug.funcs->hpd_enable_detection(encoder); } void intel_hpd_irq_setup(struct intel_display *display) @@ -1457,8 +1457,8 @@ void intel_hpd_irq_setup(struct intel_display *display) !display->irq.vlv_display_irqs_enabled) return; - if (display->funcs.hotplug) - display->funcs.hotplug->hpd_irq_setup(display); + if (display->hotplug.funcs) + display->hotplug.funcs->hpd_irq_setup(display); } void intel_hotplug_irq_init(struct intel_display *display) @@ -1469,23 +1469,23 @@ void intel_hotplug_irq_init(struct intel_display *display) if (HAS_GMCH(display)) { if (HAS_HOTPLUG(display)) - display->funcs.hotplug = &i915_hpd_funcs; + display->hotplug.funcs = &i915_hpd_funcs; } else { if (HAS_PCH_DG2(display)) - display->funcs.hotplug = &icp_hpd_funcs; + display->hotplug.funcs = &icp_hpd_funcs; else if (HAS_PCH_DG1(display)) - display->funcs.hotplug = &dg1_hpd_funcs; + display->hotplug.funcs = &dg1_hpd_funcs; else if (DISPLAY_VER(display) >= 14) - display->funcs.hotplug = &xelpdp_hpd_funcs; + display->hotplug.funcs = &xelpdp_hpd_funcs; else if (DISPLAY_VER(display) >= 11) - display->funcs.hotplug = &gen11_hpd_funcs; + display->hotplug.funcs = &gen11_hpd_funcs; else if (display->platform.geminilake || display->platform.broxton) - display->funcs.hotplug = &bxt_hpd_funcs; + display->hotplug.funcs = &bxt_hpd_funcs; else if (INTEL_PCH_TYPE(display) >= PCH_ICP) - display->funcs.hotplug = &icp_hpd_funcs; + display->hotplug.funcs = &icp_hpd_funcs; else if (INTEL_PCH_TYPE(display) >= PCH_SPT) - display->funcs.hotplug = &spt_hpd_funcs; + display->hotplug.funcs = &spt_hpd_funcs; else - display->funcs.hotplug = &ilk_hpd_funcs; + display->hotplug.funcs = &ilk_hpd_funcs; } } diff --git a/drivers/gpu/drm/i915/display/intel_initial_plane.c b/drivers/gpu/drm/i915/display/intel_initial_plane.c index ee545c033da6..034fe199c2a1 100644 --- a/drivers/gpu/drm/i915/display/intel_initial_plane.c +++ b/drivers/gpu/drm/i915/display/intel_initial_plane.c @@ -1,26 +1,51 @@ // SPDX-License-Identifier: MIT /* Copyright © 2025 Intel Corporation */ +#include + +#include #include #include +#include "intel_crtc.h" +#include "intel_de.h" #include "intel_display_core.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_fb.h" #include "intel_frontbuffer.h" #include "intel_initial_plane.h" +#include "intel_parent.h" #include "intel_plane.h" +struct intel_initial_plane_configs { + struct intel_initial_plane_config config[I915_MAX_PIPES]; +}; + void intel_initial_plane_vblank_wait(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); + u32 start_ts, end_ts; + int ret; - display->parent->initial_plane->vblank_wait(&crtc->base); + /* xe doesn't have interrupts enabled this early */ + if (intel_parent_irq_enabled(display)) { + intel_crtc_wait_for_next_vblank(crtc); + return; + } + + start_ts = intel_de_read(display, PIPE_FRMTMSTMP(crtc->pipe)); + + ret = poll_timeout_us(end_ts = intel_de_read(display, PIPE_FRMTMSTMP(crtc->pipe)), + end_ts != start_ts, 1000, 1000 * 1000, false); + if (ret) + drm_warn(display->drm, "[CRTC:%d:%s] early vblank wait timed out\n", + crtc->base.base.id, crtc->base.name); } static const struct intel_plane_state * intel_reuse_initial_plane_obj(struct intel_crtc *this, - const struct intel_initial_plane_config plane_configs[]) + const struct intel_initial_plane_configs *all_plane_configs) { struct intel_display *display = to_intel_display(this); struct intel_crtc *crtc; @@ -39,7 +64,8 @@ intel_reuse_initial_plane_obj(struct intel_crtc *this, if (!plane_state->ggtt_vma) continue; - if (plane_configs[this->pipe].base == plane_configs[crtc->pipe].base) + if (all_plane_configs->config[this->pipe].base == + all_plane_configs->config[crtc->pipe].base) return plane_state; } @@ -50,17 +76,38 @@ static struct drm_gem_object * intel_alloc_initial_plane_obj(struct intel_display *display, struct intel_initial_plane_config *plane_config) { - struct intel_framebuffer *fb = plane_config->fb; + struct drm_framebuffer *fb = plane_config->fb; - switch (fb->base.modifier) { + switch (fb->modifier) { case DRM_FORMAT_MOD_LINEAR: + break; case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Y_TILED: - case I915_FORMAT_MOD_4_TILED: - break; + /* fenced region needed for linear CPU access to tiled FB */ + if (intel_parent_has_fenced_regions(display)) + break; + fallthrough; default: drm_dbg_kms(display->drm, "Unsupported modifier for initial FB: 0x%llx\n", - fb->base.modifier); + fb->modifier); + return NULL; + } + + /* + * Would need to preserve the DPT, its GGTT + * mapping, and the actual FB memory. + */ + if (intel_fb_modifier_uses_dpt(display, fb->modifier)) { + drm_dbg_kms(display->drm, "DPT not supported for initial FB\n"); + return NULL; + } + + /* + * Would need to preserve the 270 degree rotated + * GGTT mapping used by the display hardware. + */ + if (drm_rotation_90_or_270(plane_config->rotation)) { + drm_dbg_kms(display->drm, "90/270 degree rotation not supported for initial FB\n"); return NULL; } @@ -69,10 +116,10 @@ intel_alloc_initial_plane_obj(struct intel_display *display, static void intel_find_initial_plane_obj(struct intel_crtc *crtc, - struct intel_initial_plane_config plane_configs[]) + struct intel_initial_plane_configs *all_plane_configs) { struct intel_display *display = to_intel_display(crtc); - struct intel_initial_plane_config *plane_config = &plane_configs[crtc->pipe]; + struct intel_initial_plane_config *plane_config = &all_plane_configs->config[crtc->pipe]; struct intel_plane *plane = to_intel_plane(crtc->base.primary); struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); struct drm_framebuffer *fb; @@ -88,12 +135,12 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc, return; if (intel_alloc_initial_plane_obj(display, plane_config)) { - fb = &plane_config->fb->base; + fb = plane_config->fb; vma = plane_config->vma; } else { const struct intel_plane_state *other_plane_state; - other_plane_state = intel_reuse_initial_plane_obj(crtc, plane_configs); + other_plane_state = intel_reuse_initial_plane_obj(crtc, all_plane_configs); if (!other_plane_state) goto nofb; @@ -144,7 +191,7 @@ static void plane_config_fini(struct intel_display *display, struct intel_initial_plane_config *plane_config) { if (plane_config->fb) { - struct drm_framebuffer *fb = &plane_config->fb->base; + struct drm_framebuffer *fb = plane_config->fb; /* We may only have the stub and not a full framebuffer */ if (drm_framebuffer_read_refcount(fb)) @@ -158,14 +205,14 @@ static void plane_config_fini(struct intel_display *display, void intel_initial_plane_config(struct intel_display *display) { - struct intel_initial_plane_config plane_configs[I915_MAX_PIPES] = {}; + struct intel_initial_plane_configs all_plane_configs = {}; struct intel_crtc *crtc; for_each_intel_crtc(display->drm, crtc) { const struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); struct intel_initial_plane_config *plane_config = - &plane_configs[crtc->pipe]; + &all_plane_configs.config[crtc->pipe]; if (!crtc_state->hw.active) continue; @@ -177,15 +224,15 @@ void intel_initial_plane_config(struct intel_display *display) * can even allow for smooth boot transitions if the BIOS * fb is large enough for the active pipe configuration. */ - display->funcs.display->get_initial_plane_config(crtc, plane_config); + display->modeset.funcs->get_initial_plane_config(crtc, plane_config); /* * If the fb is shared between multiple heads, we'll * just get the first one. */ - intel_find_initial_plane_obj(crtc, plane_configs); + intel_find_initial_plane_obj(crtc, &all_plane_configs); - if (display->funcs.display->fixup_initial_plane_config(crtc, plane_config)) + if (display->modeset.funcs->fixup_initial_plane_config(crtc, plane_config)) intel_initial_plane_vblank_wait(crtc); plane_config_fini(display, plane_config); diff --git a/drivers/gpu/drm/i915/display/intel_load_detect.c b/drivers/gpu/drm/i915/display/intel_load_detect.c index aad52d0d83e1..2f767b15a7f9 100644 --- a/drivers/gpu/drm/i915/display/intel_load_detect.c +++ b/drivers/gpu/drm/i915/display/intel_load_detect.c @@ -20,7 +20,7 @@ static const struct drm_display_mode load_detect_mode = { 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), }; -static int intel_modeset_disable_planes(struct drm_atomic_state *state, +static int intel_modeset_disable_planes(struct drm_atomic_commit *state, struct drm_crtc *crtc) { struct drm_plane *plane; @@ -45,7 +45,7 @@ static int intel_modeset_disable_planes(struct drm_atomic_state *state, return 0; } -struct drm_atomic_state * +struct drm_atomic_commit * intel_load_detect_get_pipe(struct drm_connector *connector, struct drm_modeset_acquire_ctx *ctx) { @@ -55,7 +55,7 @@ intel_load_detect_get_pipe(struct drm_connector *connector, struct intel_crtc *possible_crtc; struct intel_crtc *crtc = NULL; struct drm_mode_config *config = &display->drm->mode_config; - struct drm_atomic_state *state = NULL, *restore_state = NULL; + struct drm_atomic_commit *state = NULL, *restore_state = NULL; struct drm_connector_state *connector_state; struct intel_crtc_state *crtc_state; int ret; @@ -118,8 +118,8 @@ intel_load_detect_get_pipe(struct drm_connector *connector, } found: - state = drm_atomic_state_alloc(display->drm); - restore_state = drm_atomic_state_alloc(display->drm); + state = drm_atomic_commit_alloc(display->drm); + restore_state = drm_atomic_commit_alloc(display->drm); if (!state || !restore_state) { ret = -ENOMEM; goto fail; @@ -177,7 +177,7 @@ intel_load_detect_get_pipe(struct drm_connector *connector, goto fail; } - drm_atomic_state_put(state); + drm_atomic_commit_put(state); /* let the connector get through one full cycle before testing */ intel_crtc_wait_for_next_vblank(crtc); @@ -186,11 +186,11 @@ intel_load_detect_get_pipe(struct drm_connector *connector, fail: if (state) { - drm_atomic_state_put(state); + drm_atomic_commit_put(state); state = NULL; } if (restore_state) { - drm_atomic_state_put(restore_state); + drm_atomic_commit_put(restore_state); restore_state = NULL; } @@ -201,7 +201,7 @@ intel_load_detect_get_pipe(struct drm_connector *connector, } void intel_load_detect_release_pipe(struct drm_connector *connector, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_modeset_acquire_ctx *ctx) { struct intel_display *display = to_intel_display(connector->dev); @@ -221,5 +221,5 @@ void intel_load_detect_release_pipe(struct drm_connector *connector, if (ret) drm_dbg_kms(display->drm, "Couldn't release load detect pipe: %i\n", ret); - drm_atomic_state_put(state); + drm_atomic_commit_put(state); } diff --git a/drivers/gpu/drm/i915/display/intel_load_detect.h b/drivers/gpu/drm/i915/display/intel_load_detect.h index aed51901b9ba..7525988e45b1 100644 --- a/drivers/gpu/drm/i915/display/intel_load_detect.h +++ b/drivers/gpu/drm/i915/display/intel_load_detect.h @@ -6,15 +6,15 @@ #ifndef __INTEL_LOAD_DETECT_H__ #define __INTEL_LOAD_DETECT_H__ -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_connector; struct drm_modeset_acquire_ctx; -struct drm_atomic_state * +struct drm_atomic_commit * intel_load_detect_get_pipe(struct drm_connector *connector, struct drm_modeset_acquire_ctx *ctx); void intel_load_detect_release_pipe(struct drm_connector *connector, - struct drm_atomic_state *old, + struct drm_atomic_commit *old, struct drm_modeset_acquire_ctx *ctx); #endif /* __INTEL_LOAD_DETECT_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c index 117b60656ca1..775493306a83 100644 --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c @@ -70,11 +70,11 @@ #include #include +#include #include "intel_audio_regs.h" #include "intel_de.h" #include "intel_lpe_audio.h" -#include "intel_pci_config.h" #define HAS_LPE_AUDIO(display) ((display)->audio.lpe.platdev) diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c index 657ad5cb0eff..e2f9e1a2745f 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c @@ -2135,7 +2135,7 @@ void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder, wakeref = intel_lt_phy_transaction_begin(encoder); - trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(display->drm, !trans)) { intel_lt_phy_transaction_end(encoder, wakeref); return; diff --git a/drivers/gpu/drm/i915/display/intel_mchbar.c b/drivers/gpu/drm/i915/display/intel_mchbar.c new file mode 100644 index 000000000000..a0d0a796c6bb --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_mchbar.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2026 Intel Corporation + */ + +#include + +#include + +#include "intel_de.h" +#include "intel_display_core.h" +#include "intel_mchbar.h" + +static bool has_mchbar_mirror(struct intel_display *display) +{ + return DISPLAY_VER(display) < 14; +} + +static u32 mchbar_mirror_base(struct intel_display *display) +{ + if (DISPLAY_VER(display) >= 6) + return MCHBAR_MIRROR_BASE_SNB; + else + return MCHBAR_MIRROR_BASE; +} + +static u32 mchbar_mirror_end(struct intel_display *display) +{ + if (DISPLAY_VER(display) >= 12 && !display->platform.rocketlake) + return MCHBAR_MIRROR_END_TGL; + else if (DISPLAY_VER(display) >= 11) + return MCHBAR_MIRROR_END_ICL_RKL; + else if (DISPLAY_VER(display) >= 6) + return MCHBAR_MIRROR_END_SNB; + else + return MCHBAR_MIRROR_END; +} + +static u32 mchbar_mirror_len(struct intel_display *display) +{ + return mchbar_mirror_end(display) - mchbar_mirror_base(display) + 1; +} + +static bool is_mchbar_reg(struct intel_display *display, i915_reg_t reg) +{ + return has_mchbar_mirror(display) && + in_range32(i915_mmio_reg_offset(reg), + mchbar_mirror_base(display), + mchbar_mirror_len(display)); +} + +static void assert_is_mchbar_reg(struct intel_display *display, i915_reg_t reg) +{ + drm_WARN(display->drm, !is_mchbar_reg(display, reg), + "Reading non-MCHBAR register 0x%x\n", + i915_mmio_reg_offset(reg)); +} + +u16 intel_mchbar_read16(struct intel_display *display, i915_reg_t reg) +{ + assert_is_mchbar_reg(display, reg); + + return intel_de_read16(display, reg); +} + +u32 intel_mchbar_read(struct intel_display *display, i915_reg_t reg) +{ + assert_is_mchbar_reg(display, reg); + + return intel_de_read(display, reg); +} + +u64 intel_mchbar_read64_2x32(struct intel_display *display, i915_reg_t reg) +{ + assert_is_mchbar_reg(display, reg); + + return intel_de_read64_2x32(display, reg); +} diff --git a/drivers/gpu/drm/i915/display/intel_mchbar.h b/drivers/gpu/drm/i915/display/intel_mchbar.h new file mode 100644 index 000000000000..fb645c64796c --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_mchbar.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ + +#ifndef __INTEL_MCHBAR_H__ +#define __INTEL_MCHBAR_H__ + +#include + +#include + +#include "i915_reg_defs.h" + +struct intel_display; + +u16 intel_mchbar_read16(struct intel_display *display, i915_reg_t reg); +u32 intel_mchbar_read(struct intel_display *display, i915_reg_t reg); +u64 intel_mchbar_read64_2x32(struct intel_display *display, i915_reg_t reg); + +#endif /* __INTEL_MCHBAR_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_modeset_lock.c b/drivers/gpu/drm/i915/display/intel_modeset_lock.c index 8fb6fd849a75..eb6a5a99328b 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_lock.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_lock.c @@ -36,7 +36,7 @@ void _intel_modeset_lock_end(struct drm_modeset_acquire_ctx *ctx, { if (*ret == -EDEADLK) { if (state) - drm_atomic_state_clear(&state->base); + drm_atomic_commit_clear(&state->base); *ret = drm_modeset_backoff(ctx); if (*ret == 0) { diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index 4086f16a12bf..e88082c8caac 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -44,7 +44,7 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); struct intel_plane *plane; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct intel_crtc *temp_crtc; enum pipe pipe = crtc->pipe; @@ -59,7 +59,7 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc, intel_plane_disable_noatomic(crtc, plane); } - state = drm_atomic_state_alloc(display->drm); + state = drm_atomic_commit_alloc(display->drm); if (!state) { drm_dbg_kms(display->drm, "failed to disable [CRTC:%d:%s], out of memory", @@ -83,9 +83,9 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc, drm_WARN_ON(display->drm, IS_ERR(temp_crtc_state) || ret); } - display->funcs.display->crtc_disable(to_intel_atomic_state(state), crtc); + display->modeset.funcs->crtc_disable(to_intel_atomic_state(state), crtc); - drm_atomic_state_put(state); + drm_atomic_commit_put(state); drm_dbg_kms(display->drm, "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", @@ -333,6 +333,7 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; + crtc_state->uapi.sharpness_strength = crtc_state->hw.sharpness_strength; if (DISPLAY_INFO(display)->color.degamma_lut_size) { /* assume 1:1 mapping */ diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index e25be56e678b..9f88b7cac9f7 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -34,13 +34,13 @@ #include #include #include +#include #include "intel_acpi.h" #include "intel_backlight.h" #include "intel_display_core.h" #include "intel_display_types.h" #include "intel_opregion.h" -#include "intel_pci_config.h" #define OPREGION_HEADER_OFFSET 0 #define OPREGION_ACPI_OFFSET 0x100 diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c index 12a325ceae6f..a809aa2950ac 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.c +++ b/drivers/gpu/drm/i915/display/intel_overlay.c @@ -481,13 +481,9 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, if (ret != 0) return ret; - atomic_inc(&display->restore.pending_fb_pin); - vma = intel_parent_overlay_pin_fb(display, obj, &offset); - if (IS_ERR(vma)) { - ret = PTR_ERR(vma); - goto out_pin_section; - } + if (IS_ERR(vma)) + return PTR_ERR(vma); if (!intel_parent_overlay_is_active(display)) { const struct intel_crtc_state *crtc_state = @@ -571,8 +567,6 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, out_unpin: intel_parent_overlay_unpin_fb(display, vma); -out_pin_section: - atomic_dec(&display->restore.pending_fb_pin); return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_parent.c b/drivers/gpu/drm/i915/display/intel_parent.c index 2e3bad2b3e6b..67b21a42d354 100644 --- a/drivers/gpu/drm/i915/display/intel_parent.c +++ b/drivers/gpu/drm/i915/display/intel_parent.c @@ -19,6 +19,7 @@ #include #include +#include #include "intel_display_core.h" #include "intel_parent.h" @@ -338,13 +339,37 @@ void intel_parent_stolen_node_free(struct intel_display *display, const struct i display->parent->stolen->node_free(node); } -/* vma */ -int intel_parent_vma_fence_id(struct intel_display *display, const struct i915_vma *vma) +/* vlv iosf */ +void intel_parent_vlv_iosf_get(struct intel_display *display, unsigned long unit_mask) { - if (!display->parent->vma) - return -1; + if (drm_WARN_ON_ONCE(display->drm, !display->parent->vlv_iosf)) + return; - return display->parent->vma->fence_id(vma); + display->parent->vlv_iosf->get(display->drm, unit_mask); +} + +void intel_parent_vlv_iosf_put(struct intel_display *display, unsigned long unit_mask) +{ + if (drm_WARN_ON_ONCE(display->drm, !display->parent->vlv_iosf)) + return; + + display->parent->vlv_iosf->put(display->drm, unit_mask); +} + +u32 intel_parent_vlv_iosf_read(struct intel_display *display, enum vlv_iosf_sb_unit unit, u32 addr) +{ + if (drm_WARN_ON_ONCE(display->drm, !display->parent->vlv_iosf)) + return 0; + + return display->parent->vlv_iosf->read(display->drm, unit, addr); +} + +int intel_parent_vlv_iosf_write(struct intel_display *display, enum vlv_iosf_sb_unit unit, u32 addr, u32 val) +{ + if (drm_WARN_ON_ONCE(display->drm, !display->parent->vlv_iosf)) + return -EINVAL; + + return display->parent->vlv_iosf->write(display->drm, unit, addr, val); } /* generic */ diff --git a/drivers/gpu/drm/i915/display/intel_parent.h b/drivers/gpu/drm/i915/display/intel_parent.h index 2013e5ed5aa9..5f0c835b9416 100644 --- a/drivers/gpu/drm/i915/display/intel_parent.h +++ b/drivers/gpu/drm/i915/display/intel_parent.h @@ -6,6 +6,7 @@ #include +enum vlv_iosf_sb_unit; struct dma_fence; struct drm_file; struct drm_gem_object; @@ -109,8 +110,11 @@ u64 intel_parent_stolen_node_size(struct intel_display *display, const struct in struct intel_stolen_node *intel_parent_stolen_node_alloc(struct intel_display *display); void intel_parent_stolen_node_free(struct intel_display *display, const struct intel_stolen_node *node); -/* vma */ -int intel_parent_vma_fence_id(struct intel_display *display, const struct i915_vma *vma); +/* vlv iosf */ +void intel_parent_vlv_iosf_get(struct intel_display *display, unsigned long unit_mask); +void intel_parent_vlv_iosf_put(struct intel_display *display, unsigned long unit_mask); +u32 intel_parent_vlv_iosf_read(struct intel_display *display, enum vlv_iosf_sb_unit unit, u32 addr); +int intel_parent_vlv_iosf_write(struct intel_display *display, enum vlv_iosf_sb_unit unit, u32 addr, u32 val); /* generic */ bool intel_parent_has_auxccs(struct intel_display *display); diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c index 6dda496190e0..5b170c74a510 100644 --- a/drivers/gpu/drm/i915/display/intel_pfit.c +++ b/drivers/gpu/drm/i915/display/intel_pfit.c @@ -186,6 +186,7 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); @@ -195,11 +196,22 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state, /* Native modes don't need fitting */ if (adjusted_mode->crtc_hdisplay == pipe_src_w && adjusted_mode->crtc_vdisplay == pipe_src_h && - crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420) + crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 && + crtc_state->hw.sharpness_strength == 0) return 0; switch (conn_state->scaling_mode) { case DRM_MODE_SCALE_CENTER: + if (adjusted_mode->crtc_hdisplay < pipe_src_w || + adjusted_mode->crtc_vdisplay < pipe_src_h) { + drm_dbg_kms(display->drm, + "[CRTC:%d:%s] pfit center mode source (%dx%d) exceeds display (%dx%d)\n", + crtc->base.base.id, crtc->base.name, + pipe_src_w, pipe_src_h, + adjusted_mode->crtc_hdisplay, + adjusted_mode->crtc_vdisplay); + return -EINVAL; + } width = pipe_src_w; height = pipe_src_h; x = (adjusted_mode->crtc_hdisplay - width + 1)/2; @@ -249,6 +261,16 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state, return -EINVAL; } + if (crtc_state->hw.sharpness_strength && + (width != pipe_src_w || height != pipe_src_h || + crtc_state->hw.scaling_filter != DRM_SCALING_FILTER_DEFAULT || + crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)) { + drm_dbg_kms(display->drm, + "[CRTC:%d:%s] no scaling/YCbCr output with sharpness filter\n", + crtc->base.base.id, crtc->base.name); + return -EINVAL; + } + drm_rect_init(&crtc_state->pch_pfit.dst, x, y, width, height); crtc_state->pch_pfit.enabled = true; diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c index 57586c78582d..5434d7f823d4 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c @@ -284,7 +284,7 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable) { struct intel_display *display = to_intel_display(crtc); struct intel_crtc_state *pipe_config; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_modeset_acquire_ctx ctx; int ret; @@ -293,7 +293,7 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable) drm_modeset_acquire_init(&ctx, 0); - state = drm_atomic_state_alloc(display->drm); + state = drm_atomic_commit_alloc(display->drm); if (!state) { ret = -ENOMEM; goto unlock; @@ -321,12 +321,12 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable) put_state: if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); drm_modeset_backoff(&ctx); goto retry; } - drm_atomic_state_put(state); + drm_atomic_commit_put(state); unlock: drm_WARN(display->drm, ret, "Toggling workaround to %i returns %i\n", enable, ret); diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c index 5390ceb21ca4..c181a7d063ec 100644 --- a/drivers/gpu/drm/i915/display/intel_plane.c +++ b/drivers/gpu/drm/i915/display/intel_plane.c @@ -70,6 +70,7 @@ static void intel_plane_state_reset(struct intel_plane_state *plane_state, __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base); plane_state->scaler_id = -1; + plane_state->fence_id = -1; } struct intel_plane *intel_plane_alloc(void) @@ -137,7 +138,7 @@ intel_plane_duplicate_state(struct drm_plane *plane) intel_state->ggtt_vma = NULL; intel_state->dpt_vma = NULL; - intel_state->flags = 0; + intel_state->fence_id = -1; intel_state->damage = DRM_RECT_INIT(0, 0, 0, 0); /* add reference to fb */ @@ -170,6 +171,19 @@ intel_plane_destroy_state(struct drm_plane *plane, kfree(plane_state); } +bool intel_plane_needs_low_address(struct intel_display *display) +{ + /* + * Valleyview is definitely limited to scanning out the first + * 512MiB. Lets presume this behaviour was inherited from the + * g4x display engine and that all earlier gen are similarly + * limited. Testing suggests that it is a little more + * complicated than this. For example, Cherryview appears quite + * happy to scanout from anywhere within its global aperture. + */ + return HAS_GMCH(display); +} + bool intel_plane_needs_physical(struct intel_plane *plane) { struct intel_display *display = to_intel_display(plane); @@ -178,6 +192,15 @@ bool intel_plane_needs_physical(struct intel_plane *plane) DISPLAY_INFO(display)->cursor_needs_physical; } +bool intel_plane_needs_fence(struct intel_display *display) +{ + /* + * pre-i965 planes use the fence for tiled scanout. + * i965+ planes have their own tiled scanout control bit. + */ + return DISPLAY_VER(display) < 4; +} + bool intel_plane_can_async_flip(struct intel_plane *plane, const struct drm_format_info *info, u64 modifier) @@ -364,7 +387,7 @@ intel_plane_color_copy_uapi_to_hw_state(struct intel_plane_state *plane_state, { struct drm_colorop *iter_colorop, *colorop; struct drm_colorop_state *new_colorop_state; - struct drm_atomic_state *state = plane_state->uapi.state; + struct drm_atomic_commit *state = plane_state->uapi.state; struct intel_colorop *intel_colorop; struct drm_property_blob *blob; struct intel_atomic_state *intel_atomic_state = to_intel_atomic_state(state); diff --git a/drivers/gpu/drm/i915/display/intel_plane.h b/drivers/gpu/drm/i915/display/intel_plane.h index 5a8f2f3baab5..7b5456f56f42 100644 --- a/drivers/gpu/drm/i915/display/intel_plane.h +++ b/drivers/gpu/drm/i915/display/intel_plane.h @@ -15,6 +15,7 @@ struct drm_rect; struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; +struct intel_display; struct intel_dsb; struct intel_plane; struct intel_plane_state; @@ -79,7 +80,9 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state); void intel_plane_set_invisible(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state); void intel_plane_helper_add(struct intel_plane *plane); +bool intel_plane_needs_low_address(struct intel_display *display); bool intel_plane_needs_physical(struct intel_plane *plane); +bool intel_plane_needs_fence(struct intel_display *display); void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_plane_state, struct intel_plane_state *new_plane_state); int intel_plane_add_affected(struct intel_atomic_state *state, diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c index 244806a26da3..7819b724795b 100644 --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c @@ -6,6 +6,7 @@ #include #include +#include #include "intel_atomic.h" #include "intel_bw.h" @@ -17,7 +18,6 @@ #include "intel_display_utils.h" #include "intel_display_wa.h" #include "intel_pmdemand.h" -#include "intel_step.h" #include "skl_watermark.h" struct pmdemand_params { diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 53c10ae76ab5..9958230a3dd9 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "intel_alpm.h" #include "intel_atomic.h" @@ -44,6 +45,7 @@ #include "intel_dmc.h" #include "intel_dp.h" #include "intel_dp_aux.h" +#include "intel_dp_tunnel.h" #include "intel_dsb.h" #include "intel_frontbuffer.h" #include "intel_hdmi.h" @@ -51,7 +53,6 @@ #include "intel_psr_regs.h" #include "intel_quirks.h" #include "intel_snps_phy.h" -#include "intel_step.h" #include "intel_vblank.h" #include "intel_vdsc.h" #include "intel_vrr.h" @@ -694,6 +695,9 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp); + if (intel_has_quirk(display, QUIRK_DISABLE_PSR2)) + return; + if (DISPLAY_VER(display) >= 9 && connector->dp.psr_caps.dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { bool y_req = connector->dp.psr_caps.dpcd[1] & @@ -1031,11 +1035,27 @@ static u8 frames_before_su_entry(struct intel_dp *intel_dp) return frames_before_su_entry; } +static bool intel_psr_allow_pr_bw_optimization(struct intel_dp *intel_dp) +{ + if (intel_dp_is_edp(intel_dp)) + return false; + + if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) + return false; + + if (!intel_dp_tunnel_pr_optimization_supported(intel_dp)) + return false; + + return true; +} + static void dg2_activate_panel_replay(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); struct intel_psr *psr = &intel_dp->psr; enum transcoder cpu_transcoder = intel_dp->psr.transcoder; + u32 dp2_ctl_set = TRANS_DP2_PANEL_REPLAY_ENABLE; + u32 dp2_ctl_clear = 0; if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { u32 val = psr->su_region_et_enabled ? @@ -1048,12 +1068,16 @@ static void dg2_activate_panel_replay(struct intel_dp *intel_dp) val); } + if (intel_psr_allow_pr_bw_optimization(intel_dp)) + dp2_ctl_set |= TRANS_DP2_PR_TUNNELING_ENABLE; + else + dp2_ctl_clear = TRANS_DP2_PR_TUNNELING_ENABLE; + intel_de_rmw(display, PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder), 0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME); - intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, - TRANS_DP2_PANEL_REPLAY_ENABLE); + intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), dp2_ctl_clear, dp2_ctl_set); } static void hsw_activate_psr2(struct intel_dp *intel_dp) @@ -3358,11 +3382,11 @@ static int intel_psr_fastset_force(struct intel_display *display) { struct drm_connector_list_iter conn_iter; struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_connector *conn; int err = 0; - state = drm_atomic_state_alloc(display->drm); + state = drm_atomic_commit_alloc(display->drm); if (!state) return -ENOMEM; @@ -3404,7 +3428,7 @@ static int intel_psr_fastset_force(struct intel_display *display) err = drm_atomic_commit(state); if (err == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); err = drm_modeset_backoff(&ctx); if (!err) goto retry; @@ -3412,7 +3436,7 @@ static int intel_psr_fastset_force(struct intel_display *display) drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); - drm_atomic_state_put(state); + drm_atomic_commit_put(state); return err; } diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c index 883f297d4b83..33245f44c0d5 100644 --- a/drivers/gpu/drm/i915/display/intel_quirks.c +++ b/drivers/gpu/drm/i915/display/intel_quirks.c @@ -94,6 +94,12 @@ static void quirk_disable_edp_panel_replay(struct intel_dp *intel_dp) drm_info(display->drm, "Applying disable Panel Replay quirk\n"); } +static void quirk_disable_psr2(struct intel_display *display) +{ + intel_set_quirk(display, QUIRK_DISABLE_PSR2); + drm_info(display->drm, "PSR2 support not currently available for this setup, applying disable PSR2 quirk\n"); +} + struct intel_quirk { int device; int subsystem_vendor; @@ -250,6 +256,9 @@ static struct intel_quirk intel_quirks[] = { /* Dell XPS 13 7390 2-in-1 */ { 0x8a52, 0x1028, 0x08b0, quirk_edp_limit_rate_hbr2 }, + + /* Xiaomi Book Pro 14 2026 */ + { 0xb081, 0x1d72, 0x2424, quirk_disable_psr2 }, }; static const struct intel_dpcd_quirk intel_dpcd_quirks[] = { @@ -269,6 +278,14 @@ static const struct intel_dpcd_quirk intel_dpcd_quirks[] = { .sink_oui = SINK_OUI(0x00, 0x22, 0xb9), .hook = quirk_disable_edp_panel_replay, }, + /* Dell XPS 16 DA16260 */ + { + .device = DEVICE_ID_ANY, + .subsystem_vendor = 0x1028, + .subsystem_device = 0x0dba, + .sink_oui = SINK_OUI(0x00, 0x22, 0xb9), + .hook = quirk_disable_edp_panel_replay, + }, }; void intel_init_quirks(struct intel_display *display) diff --git a/drivers/gpu/drm/i915/display/intel_quirks.h b/drivers/gpu/drm/i915/display/intel_quirks.h index 83214eb94b0c..970a4fe52faf 100644 --- a/drivers/gpu/drm/i915/display/intel_quirks.h +++ b/drivers/gpu/drm/i915/display/intel_quirks.h @@ -22,6 +22,7 @@ enum intel_quirk_id { QUIRK_FW_SYNC_LEN, QUIRK_EDP_LIMIT_RATE_HBR2, QUIRK_DISABLE_EDP_PANEL_REPLAY, + QUIRK_DISABLE_PSR2, }; void intel_init_quirks(struct intel_display *display); diff --git a/drivers/gpu/drm/i915/display/intel_rom.c b/drivers/gpu/drm/i915/display/intel_rom.c index d573059fb0d9..54f842c09fb0 100644 --- a/drivers/gpu/drm/i915/display/intel_rom.c +++ b/drivers/gpu/drm/i915/display/intel_rom.c @@ -7,8 +7,9 @@ #include +#include "intel_de.h" +#include "intel_display_types.h" #include "intel_rom.h" -#include "intel_uncore.h" #include "intel_oprom_regs.h" struct intel_rom { @@ -17,7 +18,7 @@ struct intel_rom { void __iomem *oprom; /* for SPI */ - struct intel_uncore *uncore; + struct intel_display *display; loff_t offset; size_t size; @@ -30,10 +31,10 @@ struct intel_rom { static u32 spi_read32(struct intel_rom *rom, loff_t offset) { - intel_uncore_write(rom->uncore, PRIMARY_SPI_ADDRESS, - rom->offset + offset); + intel_de_write(rom->display, PRIMARY_SPI_ADDRESS, + rom->offset + offset); - return intel_uncore_read(rom->uncore, PRIMARY_SPI_TRIGGER); + return intel_de_read(rom->display, PRIMARY_SPI_TRIGGER); } static u16 spi_read16(struct intel_rom *rom, loff_t offset) @@ -50,13 +51,13 @@ struct intel_rom *intel_rom_spi(struct drm_device *drm) if (!rom) return NULL; - rom->uncore = to_intel_uncore(drm); + rom->display = to_intel_display(drm); - static_region = intel_uncore_read(rom->uncore, SPI_STATIC_REGIONS); + static_region = intel_de_read(rom->display, SPI_STATIC_REGIONS); static_region &= OPTIONROM_SPI_REGIONID_MASK; - intel_uncore_write(rom->uncore, PRIMARY_SPI_REGIONID, static_region); + intel_de_write(rom->display, PRIMARY_SPI_REGIONID, static_region); - rom->offset = intel_uncore_read(rom->uncore, OROM_OFFSET) & OROM_OFFSET_MASK; + rom->offset = intel_de_read(rom->display, OROM_OFFSET) & OROM_OFFSET_MASK; rom->size = 0x200000; diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index 2e1af9e869de..db90a0a651c8 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -2512,7 +2512,7 @@ static const struct drm_connector_funcs intel_sdvo_connector_funcs = { }; static int intel_sdvo_atomic_check(struct drm_connector *conn, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *new_conn_state = drm_atomic_get_new_connector_state(state, conn); diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index 295030742294..5e5dde8f3e3a 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -72,7 +72,7 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, enum phy phy = intel_encoder_to_phy(encoder); int n_entries, ln; - trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); if (drm_WARN_ON_ONCE(display->drm, !trans)) return; diff --git a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c index 4981cc34da05..a62146133f99 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c +++ b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c @@ -46,7 +46,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, struct drm_intel_sprite_colorkey *set = data; struct drm_plane *plane; struct drm_plane_state *plane_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_modeset_acquire_ctx ctx; int ret = 0; @@ -80,7 +80,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, drm_modeset_acquire_init(&ctx, 0); - state = drm_atomic_state_alloc(plane->dev); + state = drm_atomic_commit_alloc(plane->dev); if (!state) { ret = -ENOMEM; goto out; @@ -116,11 +116,11 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, if (ret != -EDEADLK) break; - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); drm_modeset_backoff(&ctx); } - drm_atomic_state_put(state); + drm_atomic_commit_put(state); out: drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index a21dd4e3fe4c..fc0d470fe949 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -1799,11 +1799,11 @@ static int reset_link(struct intel_tc_port *tc) { struct intel_display *display = to_intel_display(tc->dig_port); struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *_state; + struct drm_atomic_commit *_state; struct intel_atomic_state *state; int ret; - _state = drm_atomic_state_alloc(display->drm); + _state = drm_atomic_commit_alloc(display->drm); if (!_state) return -ENOMEM; @@ -1813,7 +1813,7 @@ static int reset_link(struct intel_tc_port *tc) intel_modeset_lock_ctx_retry(&ctx, state, 0, ret) ret = reset_link_commit(tc, state, &ctx); - drm_atomic_state_put(&state->base); + drm_atomic_commit_put(&state->base); return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c index 8fbf0adb5699..0a926c6f25f4 100644 --- a/drivers/gpu/drm/i915/display/intel_tv.c +++ b/drivers/gpu/drm/i915/display/intel_tv.c @@ -1724,7 +1724,7 @@ intel_tv_detect(struct drm_connector *connector, return connector->status; if (force) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; state = intel_load_detect_get_pipe(connector, ctx); if (IS_ERR(state)) @@ -1847,7 +1847,7 @@ static const struct drm_connector_funcs intel_tv_connector_funcs = { }; static int intel_tv_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *new_state; struct drm_crtc_state *new_crtc_state; diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 1b7cfe226ff8..0726a2abed38 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -109,8 +109,8 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc) * we get a low value that's stable across two reads of the high * register. */ - frame = intel_de_read64_2x32(display, PIPEFRAMEPIXEL(display, pipe), - PIPEFRAME(display, pipe)); + frame = intel_de_read64_2x32_volatile(display, PIPEFRAMEPIXEL(display, pipe), + PIPEFRAME(display, pipe)); pixel = frame & PIPE_PIXEL_MASK; frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff; diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 8a957804cb97..1b09992ce9fd 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -55,6 +55,16 @@ bool intel_vrr_is_capable(struct intel_connector *connector) if (connector->mst.dp) return false; intel_dp = intel_attached_dp(connector); + /* + * Among non-MST DP branch devices, only an HDMI 2.1 sink connected + * via a PCON could support VRR. However, supporting VRR through a + * PCON requires non-trivial changes that are not implemented yet. + * Until that support exists, avoid VRR on all DP branch devices. + * + * TODO: Add support for VRR for DP->HDMI 2.1 PCON. + */ + if (drm_dp_is_branch(intel_dp->dpcd)) + return false; if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd)) return false; @@ -1053,11 +1063,9 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) if (crtc_state->cmrr.enable) { crtc_state->cmrr.cmrr_n = - intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder), - TRANS_CMRR_N_HI(display, cpu_transcoder)); + intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder)); crtc_state->cmrr.cmrr_m = - intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder), - TRANS_CMRR_M_HI(display, cpu_transcoder)); + intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder)); } if (DISPLAY_VER(display) >= 13) { diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c index f887a664fe22..b4aded774ce6 100644 --- a/drivers/gpu/drm/i915/display/intel_wm.c +++ b/drivers/gpu/drm/i915/display/intel_wm.c @@ -48,8 +48,8 @@ */ void intel_update_watermarks(struct intel_display *display) { - if (display->funcs.wm->update_wm) - display->funcs.wm->update_wm(display); + if (display->wm.funcs->update_wm) + display->wm.funcs->update_wm(display); } int intel_wm_compute(struct intel_atomic_state *state, @@ -57,10 +57,10 @@ int intel_wm_compute(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(state); - if (!display->funcs.wm->compute_watermarks) + if (!display->wm.funcs->compute_watermarks) return 0; - return display->funcs.wm->compute_watermarks(state, crtc); + return display->wm.funcs->compute_watermarks(state, crtc); } bool intel_initial_watermarks(struct intel_atomic_state *state, @@ -68,8 +68,8 @@ bool intel_initial_watermarks(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(state); - if (display->funcs.wm->initial_watermarks) { - display->funcs.wm->initial_watermarks(state, crtc); + if (display->wm.funcs->initial_watermarks) { + display->wm.funcs->initial_watermarks(state, crtc); return true; } @@ -81,8 +81,8 @@ void intel_atomic_update_watermarks(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(state); - if (display->funcs.wm->atomic_update_watermarks) - display->funcs.wm->atomic_update_watermarks(state, crtc); + if (display->wm.funcs->atomic_update_watermarks) + display->wm.funcs->atomic_update_watermarks(state, crtc); } void intel_optimize_watermarks(struct intel_atomic_state *state, @@ -90,30 +90,30 @@ void intel_optimize_watermarks(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(state); - if (display->funcs.wm->optimize_watermarks) - display->funcs.wm->optimize_watermarks(state, crtc); + if (display->wm.funcs->optimize_watermarks) + display->wm.funcs->optimize_watermarks(state, crtc); } int intel_compute_global_watermarks(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); - if (display->funcs.wm->compute_global_watermarks) - return display->funcs.wm->compute_global_watermarks(state); + if (display->wm.funcs->compute_global_watermarks) + return display->wm.funcs->compute_global_watermarks(state); return 0; } void intel_wm_get_hw_state(struct intel_display *display) { - if (display->funcs.wm->get_hw_state) - return display->funcs.wm->get_hw_state(display); + if (display->wm.funcs->get_hw_state) + return display->wm.funcs->get_hw_state(display); } void intel_wm_sanitize(struct intel_display *display) { - if (display->funcs.wm->sanitize) - return display->funcs.wm->sanitize(display); + if (display->wm.funcs->sanitize) + return display->wm.funcs->sanitize(display); } bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state, diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index 7c5cb188ebf0..308b8d363bba 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -270,6 +270,11 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) { const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; int width, height; + int ret; + + ret = intel_casf_compute_config(crtc_state); + if (ret) + return ret; if (crtc_state->pch_pfit.enabled) { width = drm_rect_width(&crtc_state->pch_pfit.dst); @@ -284,8 +289,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) drm_rect_width(&crtc_state->pipe_src), drm_rect_height(&crtc_state->pipe_src), width, height, NULL, 0, - crtc_state->pch_pfit.enabled || - intel_casf_needs_scaler(crtc_state)); + crtc_state->pch_pfit.enabled); } /** @@ -323,19 +327,24 @@ int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, need_scaler); } +static bool scaler_has_casf(struct intel_display *display, int scaler_id) +{ + return HAS_CASF(display) && scaler_id == 1; +} + static int intel_allocate_scaler(struct intel_crtc_scaler_state *scaler_state, struct intel_crtc *crtc, struct intel_plane_state *plane_state, bool casf_scaler) { + struct intel_display *display = to_intel_display(crtc); int i; for (i = 0; i < crtc->num_scalers; i++) { if (scaler_state->scalers[i].in_use) continue; - /* CASF needs second scaler */ - if (!plane_state && casf_scaler && i != 1) + if (casf_scaler && !scaler_has_casf(display, i)) continue; scaler_state->scalers[i].in_use = true; @@ -529,14 +538,11 @@ static int setup_crtc_scaler(struct intel_atomic_state *state, struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; - if (intel_casf_needs_scaler(crtc_state) && crtc_state->pch_pfit.enabled) - return -EINVAL; - return intel_atomic_setup_scaler(crtc_state, hweight32(scaler_state->scaler_users), crtc, "CRTC", crtc->base.base.id, NULL, &scaler_state->scaler_id, - intel_casf_needs_scaler(crtc_state)); + crtc_state->pch_pfit.casf.enable); } static int setup_plane_scaler(struct intel_atomic_state *state, @@ -725,9 +731,9 @@ static void glk_program_nearest_filter_coefs(struct intel_display *display, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0); } -static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter) +static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, bool casf) { - if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) + if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR || casf) return (PS_FILTER_PROGRAMMED | PS_Y_VERT_FILTER_SELECT(0) | PS_Y_HORZ_FILTER_SELECT(0) | @@ -752,50 +758,14 @@ static void skl_scaler_setup_filter(struct intel_display *display, } } -#define CASF_SCALER_FILTER_SELECT \ - (PS_FILTER_PROGRAMMED | \ - PS_Y_VERT_FILTER_SELECT(0) | \ - PS_Y_HORZ_FILTER_SELECT(0) | \ - PS_UV_VERT_FILTER_SELECT(0) | \ - PS_UV_HORZ_FILTER_SELECT(0)) - -void skl_scaler_setup_casf(struct intel_crtc_state *crtc_state) +static u32 casf_sharpness_ctl(const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_display *display = to_intel_display(crtc); - struct drm_display_mode *adjusted_mode = - &crtc_state->hw.adjusted_mode; - struct intel_crtc_scaler_state *scaler_state = - &crtc_state->scaler_state; - struct drm_rect src, dest; - int id, width, height; - int x = 0, y = 0; - enum pipe pipe = crtc->pipe; - u32 ps_ctrl; + if (!crtc_state->pch_pfit.casf.enable) + return 0; - width = adjusted_mode->crtc_hdisplay; - height = adjusted_mode->crtc_vdisplay; - - drm_rect_init(&dest, x, y, width, height); - - width = drm_rect_width(&dest); - height = drm_rect_height(&dest); - id = scaler_state->scaler_id; - - drm_rect_init(&src, 0, 0, - drm_rect_width(&crtc_state->pipe_src) << 16, - drm_rect_height(&crtc_state->pipe_src) << 16); - - trace_intel_pipe_scaler_update_arm(crtc, id, x, y, width, height); - - ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode | - CASF_SCALER_FILTER_SELECT; - - intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl); - intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id), - PS_WIN_XPOS(x) | PS_WIN_YPOS(y)); - intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id), - PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height)); + return FILTER_EN | + FILTER_STRENGTH(crtc_state->pch_pfit.casf.strength) | + crtc_state->pch_pfit.casf.win_size; } void skl_pfit_enable(const struct intel_crtc_state *crtc_state) @@ -839,12 +809,20 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state) id = scaler_state->scaler_id; ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode | - skl_scaler_get_filter_select(crtc_state->hw.scaling_filter); + skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, + crtc_state->pch_pfit.casf.enable); trace_intel_pipe_scaler_update_arm(crtc, id, x, y, width, height); - skl_scaler_setup_filter(display, NULL, pipe, id, 0, - crtc_state->hw.scaling_filter); + if (crtc_state->pch_pfit.casf.enable) + intel_casf_setup(crtc_state); + else + skl_scaler_setup_filter(display, NULL, pipe, id, 0, + crtc_state->hw.scaling_filter); + + if (scaler_has_casf(display, id)) + intel_de_write_fw(display, SHARPNESS_CTL(crtc->pipe), + casf_sharpness_ctl(crtc_state)); intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl); @@ -905,7 +883,7 @@ skl_program_plane_scaler(struct intel_dsb *dsb, } ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode | - skl_scaler_get_filter_select(plane_state->hw.scaling_filter); + skl_scaler_get_filter_select(plane_state->hw.scaling_filter, false); trace_intel_plane_scaler_update_arm(plane, scaler_id, crtc_x, crtc_y, crtc_w, crtc_h); @@ -932,6 +910,9 @@ static void skl_detach_scaler(struct intel_dsb *dsb, trace_intel_scaler_disable_arm(crtc, id); + if (scaler_has_casf(display, id)) + intel_de_write_dsb(display, dsb, SHARPNESS_CTL(crtc->pipe), 0); + intel_de_write_dsb(display, dsb, SKL_PS_CTRL(crtc->pipe, id), 0); intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(crtc->pipe, id), 0); intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(crtc->pipe, id), 0); @@ -982,22 +963,19 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state) id = i; - /* Read CASF regs for second scaler */ - if (HAS_CASF(display) && id == 1) + if (scaler_has_casf(display, i)) intel_casf_sharpness_get_config(crtc_state); - if (!crtc_state->hw.casf_params.casf_enable) - crtc_state->pch_pfit.enabled = true; + crtc_state->pch_pfit.enabled = true; pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, i)); size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, i)); - if (!crtc_state->hw.casf_params.casf_enable) - drm_rect_init(&crtc_state->pch_pfit.dst, - REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), - REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), - REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), - REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); + drm_rect_init(&crtc_state->pch_pfit.dst, + REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), + REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), + REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), + REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); scaler_state->scalers[i].in_use = true; break; diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h index 7e8d819c019d..5deabca909e6 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.h +++ b/drivers/gpu/drm/i915/display/skl_scaler.h @@ -36,8 +36,6 @@ void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state); void skl_scaler_get_config(struct intel_crtc_state *crtc_state); -void skl_scaler_setup_casf(struct intel_crtc_state *crtc_state); - enum drm_mode_status skl_scaler_mode_valid(struct intel_display *display, const struct drm_display_mode *mode, diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 11ba42c67e3e..ef431dd32e74 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "intel_bo.h" #include "intel_color.h" @@ -25,7 +26,6 @@ #include "intel_plane.h" #include "intel_psr.h" #include "intel_psr_regs.h" -#include "intel_step.h" #include "skl_scaler.h" #include "skl_universal_plane.h" #include "skl_universal_plane_regs.h" @@ -2126,6 +2126,19 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) return 0; } + +/* Divide a U16.16 fixed-point value by 2, staying in fixed-point domain */ +static inline u32 fp_16_16_div2(u32 fp) +{ + return fp >> 1; +} + +/* Convert a U16.16 fixed-point value to integer, rounding up */ +static inline int fp_16_16_to_int_ceil(u32 fp) +{ + return DIV_ROUND_UP(fp, 1 << 16); +} + static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state); @@ -2139,10 +2152,16 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) int min_height = intel_plane_min_height(plane, fb, uv_plane, rotation); int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation); int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation); - int x = plane_state->uapi.src.x1 >> 17; - int y = plane_state->uapi.src.y1 >> 17; - int w = drm_rect_width(&plane_state->uapi.src) >> 17; - int h = drm_rect_height(&plane_state->uapi.src) >> 17; + + /* + * LNL+ UV surface start/size = + * ceiling(half of Y plane start/size). Use ceiling division + * unconditionally; it is a no-op for even values. + */ + int x = fp_16_16_to_int_ceil(fp_16_16_div2(plane_state->uapi.src.x1)); + int y = fp_16_16_to_int_ceil(fp_16_16_div2(plane_state->uapi.src.y1)); + int w = fp_16_16_to_int_ceil(fp_16_16_div2(drm_rect_width(&plane_state->uapi.src))); + int h = fp_16_16_to_int_ceil(fp_16_16_div2(drm_rect_height(&plane_state->uapi.src))); u32 offset; /* FIXME not quite sure how/if these apply to the chroma plane */ @@ -3148,12 +3167,6 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, fb->format = drm_get_format_info(display->drm, fourcc, fb->modifier); - if (!display->params.enable_dpt && - intel_fb_modifier_uses_dpt(display, fb->modifier)) { - drm_dbg_kms(display->drm, "DPT disabled, skipping initial FB\n"); - goto error; - } - /* * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr * while i915 HW rotation is clockwise, that's why this swapping. @@ -3206,7 +3219,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, fb->width, fb->height, fb->format->cpp[0] * 8, base, fb->pitches[0], plane_config->size); - plane_config->fb = intel_fb; + plane_config->fb = &intel_fb->base; return; error: diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index e0ac4e2ce4dc..96d2dcbe7bbc 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -308,15 +308,6 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) enum plane_id plane_id; int max_level = INT_MAX; - if (!intel_has_sagv(display)) - return false; - - if (!crtc_state->hw.active) - return true; - - if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE) - return false; - for_each_plane_id_on_crtc(crtc, plane_id) { const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; @@ -359,9 +350,6 @@ static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum plane_id plane_id; - if (!crtc_state->hw.active) - return true; - for_each_plane_id_on_crtc(crtc, plane_id) { const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; @@ -377,6 +365,9 @@ bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); + if (!display->sagv.block_time_us) + return false; + if (!display->params.enable_sagv) return false; @@ -388,7 +379,13 @@ bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) if (crtc_state->inherited) return false; - if (DISPLAY_VER(display) >= 12) + if (!crtc_state->hw.active) + return true; + + if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE) + return false; + + if (HAS_SAGV_WM(display)) return tgl_crtc_can_enable_sagv(crtc_state); else return skl_crtc_can_enable_sagv(crtc_state); @@ -1939,7 +1936,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, result->enable = true; result->auto_min_alloc_wm_enable = xe3_auto_min_alloc_capable(plane, level); - if (DISPLAY_VER(display) < 12 && display->sagv.block_time_us) + if (!HAS_SAGV_WM(display) && display->sagv.block_time_us) result->can_sagv = latency >= display->sagv.block_time_us; } @@ -2065,7 +2062,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state, skl_compute_transition_wm(display, &wm->trans_wm, &wm->wm[0], &wm_params); - if (DISPLAY_VER(display) >= 12) { + if (HAS_SAGV_WM(display)) { tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm); skl_compute_transition_wm(display, &wm->sagv.trans_wm, @@ -2324,7 +2321,7 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state) } } - if (DISPLAY_VER(display) >= 12 && + if (HAS_SAGV_WM(display) && display->sagv.block_time_us && skl_prefill_vblank_too_short(&ctx, crtc_state, display->sagv.block_time_us)) { @@ -2616,6 +2613,26 @@ skl_print_plane_ddb_changes(struct intel_plane *plane, skl_ddb_entry_size(old), skl_ddb_entry_size(new)); } +#define PLANE_WM_EN_FMT "%cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm" +#define PLANE_WM_EN_ARGS(__wm) \ + enast((__wm)->wm[0].enable), enast((__wm)->wm[1].enable), \ + enast((__wm)->wm[2].enable), enast((__wm)->wm[3].enable), \ + enast((__wm)->wm[4].enable), enast((__wm)->wm[5].enable), \ + enast((__wm)->wm[6].enable), enast((__wm)->wm[7].enable), \ + enast((__wm)->trans_wm.enable), \ + enast((__wm)->sagv.wm0.enable), \ + enast((__wm)->sagv.trans_wm.enable) + +#define PLANE_WM_FMT "%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" +#define PLANE_WM_ARGS(__wm, __field) \ + (__wm)->wm[0].__field, (__wm)->wm[1].__field, \ + (__wm)->wm[2].__field, (__wm)->wm[3].__field, \ + (__wm)->wm[4].__field, (__wm)->wm[5].__field, \ + (__wm)->wm[6].__field, (__wm)->wm[7].__field, \ + (__wm)->trans_wm.__field, \ + (__wm)->sagv.wm0.__field, \ + (__wm)->sagv.trans_wm.__field + static noinline_for_stack void skl_print_plane_wm_changes(struct intel_plane *plane, const struct skl_plane_wm *old_wm, @@ -2624,112 +2641,44 @@ skl_print_plane_wm_changes(struct intel_plane *plane, struct intel_display *display = to_intel_display(plane); drm_dbg_kms(display->drm, - "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm" - " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n", + "[PLANE:%d:%s] level " PLANE_WM_EN_FMT " -> " PLANE_WM_EN_FMT "\n", plane->base.base.id, plane->base.name, - enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable), - enast(old_wm->wm[2].enable), enast(old_wm->wm[3].enable), - enast(old_wm->wm[4].enable), enast(old_wm->wm[5].enable), - enast(old_wm->wm[6].enable), enast(old_wm->wm[7].enable), - enast(old_wm->trans_wm.enable), - enast(old_wm->sagv.wm0.enable), - enast(old_wm->sagv.trans_wm.enable), - enast(new_wm->wm[0].enable), enast(new_wm->wm[1].enable), - enast(new_wm->wm[2].enable), enast(new_wm->wm[3].enable), - enast(new_wm->wm[4].enable), enast(new_wm->wm[5].enable), - enast(new_wm->wm[6].enable), enast(new_wm->wm[7].enable), - enast(new_wm->trans_wm.enable), - enast(new_wm->sagv.wm0.enable), - enast(new_wm->sagv.trans_wm.enable)); + PLANE_WM_EN_ARGS(old_wm), + PLANE_WM_EN_ARGS(new_wm)); drm_dbg_kms(display->drm, - "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d" - " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n", + "[PLANE:%d:%s] lines " PLANE_WM_FMT " -> " PLANE_WM_FMT "\n", plane->base.base.id, plane->base.name, - enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines, - enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].lines, - enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].lines, - enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].lines, - enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].lines, - enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].lines, - enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].lines, - enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].lines, - enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.lines, - enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.lines, - enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.lines, - enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].lines, - enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].lines, - enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].lines, - enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].lines, - enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].lines, - enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].lines, - enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].lines, - enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].lines, - enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.lines, - enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.lines, - enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines); + PLANE_WM_ARGS(old_wm, lines), + PLANE_WM_ARGS(new_wm, lines)); drm_dbg_kms(display->drm, - "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" - " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", + "[PLANE:%d:%s] blocks " PLANE_WM_FMT " -> " PLANE_WM_FMT "\n", plane->base.base.id, plane->base.name, - old_wm->wm[0].blocks, old_wm->wm[1].blocks, - old_wm->wm[2].blocks, old_wm->wm[3].blocks, - old_wm->wm[4].blocks, old_wm->wm[5].blocks, - old_wm->wm[6].blocks, old_wm->wm[7].blocks, - old_wm->trans_wm.blocks, - old_wm->sagv.wm0.blocks, - old_wm->sagv.trans_wm.blocks, - new_wm->wm[0].blocks, new_wm->wm[1].blocks, - new_wm->wm[2].blocks, new_wm->wm[3].blocks, - new_wm->wm[4].blocks, new_wm->wm[5].blocks, - new_wm->wm[6].blocks, new_wm->wm[7].blocks, - new_wm->trans_wm.blocks, - new_wm->sagv.wm0.blocks, - new_wm->sagv.trans_wm.blocks); + PLANE_WM_ARGS(old_wm, blocks), + PLANE_WM_ARGS(new_wm, blocks)); drm_dbg_kms(display->drm, - "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" - " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", + "[PLANE:%d:%s] min_ddb " PLANE_WM_FMT " -> " PLANE_WM_FMT "\n", plane->base.base.id, plane->base.name, - old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc, - old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc, - old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc, - old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc, - old_wm->trans_wm.min_ddb_alloc, - old_wm->sagv.wm0.min_ddb_alloc, - old_wm->sagv.trans_wm.min_ddb_alloc, - new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc, - new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc, - new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc, - new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc, - new_wm->trans_wm.min_ddb_alloc, - new_wm->sagv.wm0.min_ddb_alloc, - new_wm->sagv.trans_wm.min_ddb_alloc); + PLANE_WM_ARGS(old_wm, min_ddb_alloc), + PLANE_WM_ARGS(new_wm, min_ddb_alloc)); if (DISPLAY_VER(display) >= 11) return; drm_dbg_kms(display->drm, - "[PLANE:%d:%s] min_ddb_uv %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" - " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", + "[PLANE:%d:%s] min_ddb_uv " PLANE_WM_FMT " -> " PLANE_WM_FMT "\n", plane->base.base.id, plane->base.name, - old_wm->wm[0].min_ddb_alloc_uv, old_wm->wm[1].min_ddb_alloc_uv, - old_wm->wm[2].min_ddb_alloc_uv, old_wm->wm[3].min_ddb_alloc_uv, - old_wm->wm[4].min_ddb_alloc_uv, old_wm->wm[5].min_ddb_alloc_uv, - old_wm->wm[6].min_ddb_alloc_uv, old_wm->wm[7].min_ddb_alloc_uv, - old_wm->trans_wm.min_ddb_alloc_uv, - old_wm->sagv.wm0.min_ddb_alloc_uv, - old_wm->sagv.trans_wm.min_ddb_alloc_uv, - new_wm->wm[0].min_ddb_alloc_uv, new_wm->wm[1].min_ddb_alloc_uv, - new_wm->wm[2].min_ddb_alloc_uv, new_wm->wm[3].min_ddb_alloc_uv, - new_wm->wm[4].min_ddb_alloc_uv, new_wm->wm[5].min_ddb_alloc_uv, - new_wm->wm[6].min_ddb_alloc_uv, new_wm->wm[7].min_ddb_alloc_uv, - new_wm->trans_wm.min_ddb_alloc_uv, - new_wm->sagv.wm0.min_ddb_alloc_uv, - new_wm->sagv.trans_wm.min_ddb_alloc_uv); + PLANE_WM_ARGS(old_wm, min_ddb_alloc_uv), + PLANE_WM_ARGS(new_wm, min_ddb_alloc_uv)); } +#undef PLANE_WM_EN_FMT +#undef PLANE_WM_EN_ARGS +#undef PLANE_WM_FMT +#undef PLANE_WM_ARGS + static void skl_print_wm_changes(struct intel_atomic_state *state) { @@ -2997,8 +2946,9 @@ skl_compute_wm(struct intel_atomic_state *state) * other crtcs can't be allowed to use the more optimal * normal (ie. non-SAGV) watermarks. */ - pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(display) && - DISPLAY_VER(display) >= 12 && + pipe_wm->use_sagv_wm = + HAS_SAGV_WM(display) && + !HAS_HW_SAGV_WM(display) && intel_crtc_can_enable_sagv(new_crtc_state); ret = skl_wm_add_affected_planes(state, crtc); @@ -3064,7 +3014,7 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe)); skl_wm_level_from_reg_val(display, val, &wm->sagv.trans_wm); - } else if (DISPLAY_VER(display) >= 12) { + } else if (HAS_SAGV_WM(display)) { wm->sagv.wm0 = wm->wm[0]; wm->sagv.trans_wm = wm->trans_wm; } @@ -3919,6 +3869,40 @@ void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc, sizeof(crtc_state->wm.skl.optimal.planes[plane->id])); } +static void skl_wm_level_verify(struct intel_plane *plane, + const char *wm_name, + const struct skl_wm_level *hw_wm_level, + const struct skl_wm_level *sw_wm_level) +{ + struct intel_display *display = to_intel_display(plane); + + if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) + return; + + drm_err(display->drm, + "[PLANE:%d:%s] mismatch in %s (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", + plane->base.base.id, plane->base.name, wm_name, + sw_wm_level->enable, sw_wm_level->blocks, sw_wm_level->lines, + hw_wm_level->enable, hw_wm_level->blocks, hw_wm_level->lines); +} + +static void skl_ddb_entry_verify(struct intel_plane *plane, + const char *ddb_name, + const struct skl_ddb_entry *hw_ddb_entry, + const struct skl_ddb_entry *sw_ddb_entry) +{ + struct intel_display *display = to_intel_display(plane); + + if (skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) + return; + + drm_err(display->drm, + "[PLANE:%d:%s] mismatch in %s (expected (%u,%u), found (%u,%u))\n", + plane->base.base.id, plane->base.name, ddb_name, + sw_ddb_entry->start, sw_ddb_entry->end, + hw_ddb_entry->start, hw_ddb_entry->end); +} + void intel_wm_state_verify(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -3958,86 +3942,42 @@ void intel_wm_state_verify(struct intel_atomic_state *state, hw_enabled_slices); for_each_intel_plane_on_crtc(display->drm, crtc, plane) { - const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; - const struct skl_wm_level *hw_wm_level, *sw_wm_level; + const struct skl_plane_wm *hw_plane_wm = + &hw->wm.planes[plane->id]; + const struct skl_plane_wm *sw_plane_wm = + &sw_wm->planes[plane->id]; - /* Watermarks */ for (level = 0; level < display->wm.num_levels; level++) { - hw_wm_level = &hw->wm.planes[plane->id].wm[level]; - sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); + char wm_name[16]; - if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) - continue; + snprintf(wm_name, sizeof(wm_name), "WM%d", level); - drm_err(display->drm, - "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", - plane->base.base.id, plane->base.name, level, - sw_wm_level->enable, - sw_wm_level->blocks, - sw_wm_level->lines, - hw_wm_level->enable, - hw_wm_level->blocks, - hw_wm_level->lines); + skl_wm_level_verify(plane, wm_name, + &hw_plane_wm->wm[level], + skl_plane_wm_level(sw_wm, plane->id, level)); } - hw_wm_level = &hw->wm.planes[plane->id].trans_wm; - sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); + skl_wm_level_verify(plane, "trans WM", + &hw_plane_wm->trans_wm, + skl_plane_trans_wm(sw_wm, plane->id)); - if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { - drm_err(display->drm, - "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", - plane->base.base.id, plane->base.name, - sw_wm_level->enable, - sw_wm_level->blocks, - sw_wm_level->lines, - hw_wm_level->enable, - hw_wm_level->blocks, - hw_wm_level->lines); + if (HAS_HW_SAGV_WM(display)) { + skl_wm_level_verify(plane, "SAGV WM", + &hw_plane_wm->sagv.wm0, + &sw_plane_wm->sagv.wm0); + + skl_wm_level_verify(plane, "SAGV trans WM", + &hw_plane_wm->sagv.trans_wm, + &sw_plane_wm->sagv.trans_wm); } - hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; - sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; + skl_ddb_entry_verify(plane, "DDB", + &hw->ddb[plane->id], + &new_crtc_state->wm.skl.plane_ddb[plane->id]); - if (HAS_HW_SAGV_WM(display) && - !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { - drm_err(display->drm, - "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", - plane->base.base.id, plane->base.name, - sw_wm_level->enable, - sw_wm_level->blocks, - sw_wm_level->lines, - hw_wm_level->enable, - hw_wm_level->blocks, - hw_wm_level->lines); - } - - hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; - sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; - - if (HAS_HW_SAGV_WM(display) && - !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { - drm_err(display->drm, - "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", - plane->base.base.id, plane->base.name, - sw_wm_level->enable, - sw_wm_level->blocks, - sw_wm_level->lines, - hw_wm_level->enable, - hw_wm_level->blocks, - hw_wm_level->lines); - } - - /* DDB */ - hw_ddb_entry = &hw->ddb[plane->id]; - sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[plane->id]; - - if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { - drm_err(display->drm, - "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", - plane->base.base.id, plane->base.name, - sw_ddb_entry->start, sw_ddb_entry->end, - hw_ddb_entry->start, hw_ddb_entry->end); - } + skl_ddb_entry_verify(plane, "DDB Y", + &hw->ddb_y[plane->id], + &new_crtc_state->wm.skl.plane_ddb_y[plane->id]); } kfree(hw); @@ -4055,7 +3995,7 @@ void skl_wm_init(struct intel_display *display) skl_setup_wm_latency(display); - display->funcs.wm = &skl_wm_funcs; + display->wm.funcs = &skl_wm_funcs; } static int skl_watermark_ipc_status_show(struct seq_file *m, void *data) diff --git a/drivers/gpu/drm/i915/display/vlv_clock.c b/drivers/gpu/drm/i915/display/vlv_clock.c index 1abdae453514..a589cdb74903 100644 --- a/drivers/gpu/drm/i915/display/vlv_clock.c +++ b/drivers/gpu/drm/i915/display/vlv_clock.c @@ -22,11 +22,11 @@ int vlv_clock_get_hpll_vco(struct drm_device *drm) int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; if (!display->vlv_clock.hpll_freq) { - vlv_cck_get(drm); + vlv_cck_get(display); /* Obtain SKU information */ - hpll_freq = vlv_cck_read(drm, CCK_FUSE_REG) & + hpll_freq = vlv_cck_read(display, CCK_FUSE_REG) & CCK_FUSE_HPLL_FREQ_MASK; - vlv_cck_put(drm); + vlv_cck_put(display); display->vlv_clock.hpll_freq = vco_freq[hpll_freq] * 1000; @@ -39,12 +39,13 @@ int vlv_clock_get_hpll_vco(struct drm_device *drm) static int vlv_clock_get_cck(struct drm_device *drm, const char *name, u32 reg, int ref_freq) { + struct intel_display *display = to_intel_display(drm); u32 val; int divider; - vlv_cck_get(drm); - val = vlv_cck_read(drm, reg); - vlv_cck_put(drm); + vlv_cck_get(display); + val = vlv_cck_read(display, reg); + vlv_cck_put(display); divider = val & CCK_FREQUENCY_VALUES; diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index d4db73c184e5..76e8cd0f65a4 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -254,16 +254,16 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, static void band_gap_reset(struct intel_display *display) { - vlv_flisdsi_get(display->drm); + vlv_flisdsi_get(display); - vlv_flisdsi_write(display->drm, 0x08, 0x0001); - vlv_flisdsi_write(display->drm, 0x0F, 0x0005); - vlv_flisdsi_write(display->drm, 0x0F, 0x0025); + vlv_flisdsi_write(display, 0x08, 0x0001); + vlv_flisdsi_write(display, 0x0F, 0x0005); + vlv_flisdsi_write(display, 0x0F, 0x0025); udelay(150); - vlv_flisdsi_write(display->drm, 0x0F, 0x0000); - vlv_flisdsi_write(display->drm, 0x08, 0x0000); + vlv_flisdsi_write(display, 0x0F, 0x0000); + vlv_flisdsi_write(display, 0x08, 0x0000); - vlv_flisdsi_put(display->drm); + vlv_flisdsi_put(display); } static int intel_dsi_compute_config(struct intel_encoder *encoder, @@ -461,11 +461,11 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) drm_dbg_kms(display->drm, "\n"); - vlv_flisdsi_get(display->drm); + vlv_flisdsi_get(display); /* program rcomp for compliance, reduce from 50 ohms to 45 ohms * needed everytime after power gate */ - vlv_flisdsi_write(display->drm, 0x04, 0x0004); - vlv_flisdsi_put(display->drm); + vlv_flisdsi_write(display, 0x04, 0x0004); + vlv_flisdsi_put(display); /* bandgap reset is needed after everytime we do power gate */ band_gap_reset(display); diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c index a2da6285890b..68b73cca2aec 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c @@ -219,11 +219,11 @@ void vlv_dsi_pll_enable(struct intel_encoder *encoder, drm_dbg_kms(display->drm, "\n"); - vlv_cck_get(display->drm); + vlv_cck_get(display); - vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, 0); - vlv_cck_write(display->drm, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div); - vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, + vlv_cck_write(display, CCK_REG_DSI_PLL_CONTROL, 0); + vlv_cck_write(display, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div); + vlv_cck_write(display, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN); /* wait at least 0.5 us after ungating before enabling VCO, @@ -231,17 +231,17 @@ void vlv_dsi_pll_enable(struct intel_encoder *encoder, */ usleep_range(10, 50); - vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl); + vlv_cck_write(display, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl); - ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL), + ret = poll_timeout_us(val = vlv_cck_read(display, CCK_REG_DSI_PLL_CONTROL), val & DSI_PLL_LOCK, 500, 20 * 1000, false); if (ret) { - vlv_cck_put(display->drm); + vlv_cck_put(display); drm_err(display->drm, "DSI PLL lock failed\n"); return; } - vlv_cck_put(display->drm); + vlv_cck_put(display); drm_dbg_kms(display->drm, "DSI PLL locked\n"); } @@ -253,14 +253,14 @@ void vlv_dsi_pll_disable(struct intel_encoder *encoder) drm_dbg_kms(display->drm, "\n"); - vlv_cck_get(display->drm); + vlv_cck_get(display); - tmp = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL); + tmp = vlv_cck_read(display, CCK_REG_DSI_PLL_CONTROL); tmp &= ~DSI_PLL_VCO_EN; tmp |= DSI_PLL_LDO_GATE; - vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, tmp); + vlv_cck_write(display, CCK_REG_DSI_PLL_CONTROL, tmp); - vlv_cck_put(display->drm); + vlv_cck_put(display); } static bool has_dsic_clock(struct intel_display *display) @@ -333,10 +333,10 @@ u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, drm_dbg_kms(display->drm, "\n"); - vlv_cck_get(display->drm); - pll_ctl = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL); - pll_div = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_DIVIDER); - vlv_cck_put(display->drm); + vlv_cck_get(display); + pll_ctl = vlv_cck_read(display, CCK_REG_DSI_PLL_CONTROL); + pll_div = vlv_cck_read(display, CCK_REG_DSI_PLL_DIVIDER); + vlv_cck_put(display); config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK; config->dsi_pll.div = pll_div; @@ -603,9 +603,9 @@ static void assert_dsi_pll(struct intel_display *display, bool state) { bool cur_state; - vlv_cck_get(display->drm); - cur_state = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN; - vlv_cck_put(display->drm); + vlv_cck_get(display); + cur_state = vlv_cck_read(display, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN; + vlv_cck_put(display); INTEL_DISPLAY_STATE_WARN(display, cur_state != state, "DSI PLL state assertion failure (expected %s, current %s)\n", diff --git a/drivers/gpu/drm/i915/display/vlv_sideband.c b/drivers/gpu/drm/i915/display/vlv_sideband.c index e18045f2b89d..068f58bd9a2b 100644 --- a/drivers/gpu/drm/i915/display/vlv_sideband.c +++ b/drivers/gpu/drm/i915/display/vlv_sideband.c @@ -6,8 +6,74 @@ #include "intel_display_core.h" #include "intel_display_types.h" #include "intel_dpio_phy.h" +#include "intel_parent.h" #include "vlv_sideband.h" +void vlv_bunit_get(struct intel_display *display) +{ + intel_parent_vlv_iosf_get(display, BIT(VLV_IOSF_SB_BUNIT)); +} + +u32 vlv_bunit_read(struct intel_display *display, u32 reg) +{ + return intel_parent_vlv_iosf_read(display, VLV_IOSF_SB_BUNIT, reg); +} + +void vlv_bunit_write(struct intel_display *display, u32 reg, u32 val) +{ + intel_parent_vlv_iosf_write(display, VLV_IOSF_SB_BUNIT, reg, val); +} + +void vlv_bunit_put(struct intel_display *display) +{ + intel_parent_vlv_iosf_put(display, BIT(VLV_IOSF_SB_BUNIT)); +} + +void vlv_cck_get(struct intel_display *display) +{ + intel_parent_vlv_iosf_get(display, BIT(VLV_IOSF_SB_CCK)); +} + +u32 vlv_cck_read(struct intel_display *display, u32 reg) +{ + return intel_parent_vlv_iosf_read(display, VLV_IOSF_SB_CCK, reg); +} + +void vlv_cck_write(struct intel_display *display, u32 reg, u32 val) +{ + intel_parent_vlv_iosf_write(display, VLV_IOSF_SB_CCK, reg, val); +} + +void vlv_cck_put(struct intel_display *display) +{ + intel_parent_vlv_iosf_put(display, BIT(VLV_IOSF_SB_CCK)); +} + +void vlv_ccu_get(struct intel_display *display) +{ + intel_parent_vlv_iosf_get(display, BIT(VLV_IOSF_SB_CCU)); +} + +u32 vlv_ccu_read(struct intel_display *display, u32 reg) +{ + return intel_parent_vlv_iosf_read(display, VLV_IOSF_SB_CCU, reg); +} + +void vlv_ccu_write(struct intel_display *display, u32 reg, u32 val) +{ + intel_parent_vlv_iosf_write(display, VLV_IOSF_SB_CCU, reg, val); +} + +void vlv_ccu_put(struct intel_display *display) +{ + intel_parent_vlv_iosf_put(display, BIT(VLV_IOSF_SB_CCU)); +} + +void vlv_dpio_get(struct intel_display *display) +{ + intel_parent_vlv_iosf_get(display, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2)); +} + static enum vlv_iosf_sb_unit vlv_dpio_phy_to_unit(struct intel_display *display, enum dpio_phy phy) { @@ -21,13 +87,12 @@ static enum vlv_iosf_sb_unit vlv_dpio_phy_to_unit(struct intel_display *display, return VLV_IOSF_SB_DPIO; } -u32 vlv_dpio_read(struct drm_device *drm, enum dpio_phy phy, int reg) +u32 vlv_dpio_read(struct intel_display *display, enum dpio_phy phy, int reg) { - struct intel_display *display = to_intel_display(drm); enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(display, phy); u32 val; - val = vlv_iosf_sb_read(drm, unit, reg); + val = intel_parent_vlv_iosf_read(display, unit, reg); /* * FIXME: There might be some registers where all 1's is a valid value, @@ -40,11 +105,70 @@ u32 vlv_dpio_read(struct drm_device *drm, enum dpio_phy phy, int reg) return val; } -void vlv_dpio_write(struct drm_device *drm, +void vlv_dpio_write(struct intel_display *display, enum dpio_phy phy, int reg, u32 val) { - struct intel_display *display = to_intel_display(drm); enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(display, phy); - vlv_iosf_sb_write(drm, unit, reg, val); + intel_parent_vlv_iosf_write(display, unit, reg, val); +} + +void vlv_dpio_put(struct intel_display *display) +{ + intel_parent_vlv_iosf_put(display, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2)); +} + +void vlv_flisdsi_get(struct intel_display *display) +{ + intel_parent_vlv_iosf_get(display, BIT(VLV_IOSF_SB_FLISDSI)); +} + +u32 vlv_flisdsi_read(struct intel_display *display, u32 reg) +{ + return intel_parent_vlv_iosf_read(display, VLV_IOSF_SB_FLISDSI, reg); +} + +void vlv_flisdsi_write(struct intel_display *display, u32 reg, u32 val) +{ + intel_parent_vlv_iosf_write(display, VLV_IOSF_SB_FLISDSI, reg, val); +} + +void vlv_flisdsi_put(struct intel_display *display) +{ + intel_parent_vlv_iosf_put(display, BIT(VLV_IOSF_SB_FLISDSI)); +} + +void vlv_nc_get(struct intel_display *display) +{ + intel_parent_vlv_iosf_get(display, BIT(VLV_IOSF_SB_NC)); +} + +u32 vlv_nc_read(struct intel_display *display, u8 addr) +{ + return intel_parent_vlv_iosf_read(display, VLV_IOSF_SB_NC, addr); +} + +void vlv_nc_put(struct intel_display *display) +{ + intel_parent_vlv_iosf_put(display, BIT(VLV_IOSF_SB_NC)); +} + +void vlv_punit_get(struct intel_display *display) +{ + intel_parent_vlv_iosf_get(display, BIT(VLV_IOSF_SB_PUNIT)); +} + +u32 vlv_punit_read(struct intel_display *display, u32 addr) +{ + return intel_parent_vlv_iosf_read(display, VLV_IOSF_SB_PUNIT, addr); +} + +int vlv_punit_write(struct intel_display *display, u32 addr, u32 val) +{ + return intel_parent_vlv_iosf_write(display, VLV_IOSF_SB_PUNIT, addr, val); +} + +void vlv_punit_put(struct intel_display *display) +{ + intel_parent_vlv_iosf_put(display, BIT(VLV_IOSF_SB_PUNIT)); } diff --git a/drivers/gpu/drm/i915/display/vlv_sideband.h b/drivers/gpu/drm/i915/display/vlv_sideband.h index 2c240d81fead..60a66abc1649 100644 --- a/drivers/gpu/drm/i915/display/vlv_sideband.h +++ b/drivers/gpu/drm/i915/display/vlv_sideband.h @@ -4,153 +4,45 @@ #ifndef _VLV_SIDEBAND_H_ #define _VLV_SIDEBAND_H_ -#include #include -#include "vlv_iosf_sb.h" -#include "vlv_iosf_sb_reg.h" +#include enum dpio_phy; -struct drm_device; +struct intel_display; -static inline void vlv_bunit_get(struct drm_device *drm) -{ - vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_BUNIT)); -} +void vlv_bunit_get(struct intel_display *display); +u32 vlv_bunit_read(struct intel_display *display, u32 reg); +void vlv_bunit_write(struct intel_display *display, u32 reg, u32 val); +void vlv_bunit_put(struct intel_display *display); -static inline u32 vlv_bunit_read(struct drm_device *drm, u32 reg) -{ - return vlv_iosf_sb_read(drm, VLV_IOSF_SB_BUNIT, reg); -} +void vlv_cck_get(struct intel_display *display); +u32 vlv_cck_read(struct intel_display *display, u32 reg); +void vlv_cck_write(struct intel_display *display, u32 reg, u32 val); +void vlv_cck_put(struct intel_display *display); -static inline void vlv_bunit_write(struct drm_device *drm, u32 reg, u32 val) -{ - vlv_iosf_sb_write(drm, VLV_IOSF_SB_BUNIT, reg, val); -} +void vlv_ccu_get(struct intel_display *display); +u32 vlv_ccu_read(struct intel_display *display, u32 reg); +void vlv_ccu_write(struct intel_display *display, u32 reg, u32 val); +void vlv_ccu_put(struct intel_display *display); -static inline void vlv_bunit_put(struct drm_device *drm) -{ - vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_BUNIT)); -} +void vlv_dpio_get(struct intel_display *display); +u32 vlv_dpio_read(struct intel_display *display, enum dpio_phy phy, int reg); +void vlv_dpio_write(struct intel_display *display, enum dpio_phy phy, int reg, u32 val); +void vlv_dpio_put(struct intel_display *display); -static inline void vlv_cck_get(struct drm_device *drm) -{ - vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_CCK)); -} +void vlv_flisdsi_get(struct intel_display *display); +u32 vlv_flisdsi_read(struct intel_display *display, u32 reg); +void vlv_flisdsi_write(struct intel_display *display, u32 reg, u32 val); +void vlv_flisdsi_put(struct intel_display *display); -static inline u32 vlv_cck_read(struct drm_device *drm, u32 reg) -{ - return vlv_iosf_sb_read(drm, VLV_IOSF_SB_CCK, reg); -} +void vlv_nc_get(struct intel_display *display); +u32 vlv_nc_read(struct intel_display *display, u8 addr); +void vlv_nc_put(struct intel_display *display); -static inline void vlv_cck_write(struct drm_device *drm, u32 reg, u32 val) -{ - vlv_iosf_sb_write(drm, VLV_IOSF_SB_CCK, reg, val); -} - -static inline void vlv_cck_put(struct drm_device *drm) -{ - vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_CCK)); -} - -static inline void vlv_ccu_get(struct drm_device *drm) -{ - vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_CCU)); -} - -static inline u32 vlv_ccu_read(struct drm_device *drm, u32 reg) -{ - return vlv_iosf_sb_read(drm, VLV_IOSF_SB_CCU, reg); -} - -static inline void vlv_ccu_write(struct drm_device *drm, u32 reg, u32 val) -{ - vlv_iosf_sb_write(drm, VLV_IOSF_SB_CCU, reg, val); -} - -static inline void vlv_ccu_put(struct drm_device *drm) -{ - vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_CCU)); -} - -static inline void vlv_dpio_get(struct drm_device *drm) -{ - vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2)); -} - -#ifdef I915 -u32 vlv_dpio_read(struct drm_device *drm, enum dpio_phy phy, int reg); -void vlv_dpio_write(struct drm_device *drm, - enum dpio_phy phy, int reg, u32 val); -#else -static inline u32 vlv_dpio_read(struct drm_device *drm, int phy, int reg) -{ - return 0; -} -static inline void vlv_dpio_write(struct drm_device *drm, - int phy, int reg, u32 val) -{ -} -#endif - -static inline void vlv_dpio_put(struct drm_device *drm) -{ - vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2)); -} - -static inline void vlv_flisdsi_get(struct drm_device *drm) -{ - vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_FLISDSI)); -} - -static inline u32 vlv_flisdsi_read(struct drm_device *drm, u32 reg) -{ - return vlv_iosf_sb_read(drm, VLV_IOSF_SB_FLISDSI, reg); -} - -static inline void vlv_flisdsi_write(struct drm_device *drm, u32 reg, u32 val) -{ - vlv_iosf_sb_write(drm, VLV_IOSF_SB_FLISDSI, reg, val); -} - -static inline void vlv_flisdsi_put(struct drm_device *drm) -{ - vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_FLISDSI)); -} - -static inline void vlv_nc_get(struct drm_device *drm) -{ - vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_NC)); -} - -static inline u32 vlv_nc_read(struct drm_device *drm, u8 addr) -{ - return vlv_iosf_sb_read(drm, VLV_IOSF_SB_NC, addr); -} - -static inline void vlv_nc_put(struct drm_device *drm) -{ - vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_NC)); -} - -static inline void vlv_punit_get(struct drm_device *drm) -{ - vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_PUNIT)); -} - -static inline u32 vlv_punit_read(struct drm_device *drm, u32 addr) -{ - return vlv_iosf_sb_read(drm, VLV_IOSF_SB_PUNIT, addr); -} - -static inline int vlv_punit_write(struct drm_device *drm, u32 addr, u32 val) -{ - return vlv_iosf_sb_write(drm, VLV_IOSF_SB_PUNIT, addr, val); -} - -static inline void vlv_punit_put(struct drm_device *drm) -{ - vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_PUNIT)); -} +void vlv_punit_get(struct intel_display *display); +u32 vlv_punit_read(struct intel_display *display, u32 addr); +int vlv_punit_write(struct intel_display *display, u32 addr, u32 val); +void vlv_punit_put(struct intel_display *display); #endif /* _VLV_SIDEBAND_H_ */ diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c index 77f85359f279..1cfdcf5c1118 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include "gem/i915_gem_lmem.h" #include "gem/i915_gem_region.h" @@ -23,8 +25,6 @@ #include "i915_reg.h" #include "i915_utils.h" #include "i915_vgpu.h" -#include "intel_mchbar_regs.h" -#include "intel_pci_config.h" struct intel_stolen_node { struct drm_i915_private *i915; diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 08c4e735481b..64ca5bbc53c6 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "gem/i915_gem_lmem.h" @@ -20,7 +21,6 @@ #include "intel_gpu_commands.h" #include "intel_gt.h" #include "intel_gt_regs.h" -#include "intel_pci_config.h" #include "intel_ring.h" #include "i915_drv.h" #include "i915_pci.h" diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c index ac9aede82320..6efc1ed3831b 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c @@ -7,6 +7,7 @@ #include #include +#include #include "display/intel_display.h" #include "i915_drv.h" @@ -15,7 +16,6 @@ #include "i915_pvinfo.h" #include "i915_vgpu.h" #include "intel_gt_regs.h" -#include "intel_mchbar_regs.h" /** * DOC: fence register handling diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index d76121e117e1..5c7f862f7100 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -6,6 +6,7 @@ #include #include #include +#include #include "gem/i915_gem_internal.h" #include "gem/i915_gem_lmem.h" @@ -28,7 +29,6 @@ #include "intel_gt_requests.h" #include "intel_migrate.h" #include "intel_mocs.h" -#include "intel_pci_config.h" #include "intel_rc6.h" #include "intel_renderstate.h" #include "intel_rps.h" diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c index babaf16e72f2..adf2512e2ed5 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c @@ -19,7 +19,6 @@ #include "intel_gt_pm_debugfs.h" #include "intel_gt_regs.h" #include "intel_llc.h" -#include "intel_mchbar_regs.h" #include "intel_pcode.h" #include "intel_rc6.h" #include "intel_rps.h" diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c index bcd707e3d436..82d9a8e50867 100644 --- a/drivers/gpu/drm/i915/gt/intel_llc.c +++ b/drivers/gpu/drm/i915/gt/intel_llc.c @@ -7,12 +7,12 @@ #include #include +#include #include "i915_drv.h" #include "i915_reg.h" #include "intel_gt.h" #include "intel_llc.h" -#include "intel_mchbar_regs.h" #include "intel_pcode.h" #include "intel_rps.h" diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index a30060fd4429..b8a39567a334 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -4,12 +4,12 @@ */ #include +#include #include "i915_drv.h" #include "i915_pci.h" #include "i915_reg.h" #include "intel_memory_region.h" -#include "intel_pci_config.h" #include "intel_region_lmem.h" #include "intel_region_ttm.h" #include "gem/i915_gem_lmem.h" diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 984d0056c01c..0b5f3fc58009 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -7,6 +7,9 @@ #include #include +#include +#include + #include "display/intel_display_reset.h" #include "display/intel_overlay.h" #include "gem/i915_gem_context.h" @@ -27,8 +30,6 @@ #include "intel_gt_pm.h" #include "intel_gt_print.h" #include "intel_gt_requests.h" -#include "intel_mchbar_regs.h" -#include "intel_pci_config.h" #include "intel_reset.h" #define RESET_MAX_RETRIES 3 @@ -966,6 +967,7 @@ static void nop_submit_request(struct i915_request *request) static void __intel_gt_set_wedged(struct intel_gt *gt) { + struct intel_display *display = gt->i915->display; struct intel_engine_cs *engine; intel_engine_mask_t awake; enum intel_engine_id id; @@ -983,7 +985,8 @@ static void __intel_gt_set_wedged(struct intel_gt *gt) awake = reset_prepare(gt); /* Even if the GPU reset fails, it should still stop the engines */ - if (!intel_gt_gpu_reset_clobbers_display(gt)) + if (!intel_gt_gpu_reset_clobbers_display(gt) && + !intel_display_reset_test(display)) intel_gt_reset_all_engines(gt); for_each_engine(engine, gt, id) @@ -1397,11 +1400,6 @@ int intel_engine_reset(struct intel_engine_cs *engine, const char *msg) return err; } -static void display_reset_modeset_stuck(void *gt) -{ - intel_gt_set_wedged(gt); -} - static void intel_gt_reset_global(struct intel_gt *gt, u32 engine_mask, const char *reason) @@ -1424,16 +1422,25 @@ static void intel_gt_reset_global(struct intel_gt *gt, bool need_display_reset; bool reset_display; - need_display_reset = intel_gt_gpu_reset_clobbers_display(gt) && + need_display_reset = + intel_display_reset_supported(display) && + intel_gt_gpu_reset_clobbers_display(gt) && intel_has_gpu_reset(gt); - reset_display = intel_display_reset_test(display) || + reset_display = + intel_display_reset_test(display) || need_display_reset; - if (reset_display) - reset_display = intel_display_reset_prepare(display, - display_reset_modeset_stuck, - gt); + if (reset_display) { + if (atomic_read(&i915->pending_fb_pin)) { + drm_dbg_kms(&i915->drm, + "Modeset potentially stuck, unbreaking through wedging\n"); + + intel_gt_set_wedged(gt); + } + + intel_display_reset_prepare(display); + } intel_gt_reset(gt, engine_mask, reason); @@ -1501,9 +1508,10 @@ void intel_gt_handle_error(struct intel_gt *gt, /* * Try engine reset when available. We fall back to full reset if - * single reset fails. + * single reset fails. Display reset test needs a full reset. */ - if (!intel_uc_uses_guc_submission(>->uc) && + if (!intel_display_reset_test(gt->i915->display) && + !intel_uc_uses_guc_submission(>->uc) && intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) { local_bh_disable(); for_each_engine_masked(engine, gt, engine_mask, tmp) { diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 844f2716a386..a33b19c04737 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -5,9 +5,10 @@ #include -#include #include +#include #include +#include #include "display/intel_display_rps.h" #include "display/vlv_clock.h" @@ -25,7 +26,6 @@ #include "intel_gt_pm_irq.h" #include "intel_gt_print.h" #include "intel_gt_regs.h" -#include "intel_mchbar_regs.h" #include "intel_pcode.h" #include "intel_rps.h" #include "vlv_iosf_sb.h" diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c index fa9af08f9708..a75f05ff1110 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c @@ -16,7 +16,6 @@ #include "i915_wait_util.h" #include "intel_guc_print.h" #include "intel_guc_slpc.h" -#include "intel_mchbar_regs.h" /** * DOC: SLPC - Dynamic Frequency management diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c index 1937e04d3791..e00c1478a24e 100644 --- a/drivers/gpu/drm/i915/gvt/cfg_space.c +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c @@ -32,10 +32,10 @@ */ #include +#include #include "gvt.h" #include "i915_drv.h" -#include "intel_pci_config.h" enum { INTEL_GVT_PCI_BAR_GTTMMIO = 0, diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index a34f56630af9..9f61867e2478 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -71,7 +71,6 @@ #include "i915_drv.h" #include "i915_pvinfo.h" #include "i915_reg.h" -#include "intel_mchbar_regs.h" #include "sched_policy.h" /* XXX FIXME i915 has changed PP_XXX definition */ diff --git a/drivers/gpu/drm/i915/i915_bo.c b/drivers/gpu/drm/i915/i915_bo.c index 1789f7cab05c..559341103ca7 100644 --- a/drivers/gpu/drm/i915/i915_bo.c +++ b/drivers/gpu/drm/i915/i915_bo.c @@ -1,11 +1,14 @@ // SPDX-License-Identifier: MIT /* Copyright © 2024 Intel Corporation */ +#include + #include #include #include #include "display/intel_fb.h" +#include "gem/i915_gem_lmem.h" #include "gem/i915_gem_mman.h" #include "gem/i915_gem_object.h" #include "gem/i915_gem_object_frontbuffer.h" @@ -141,6 +144,111 @@ i915_bo_framebuffer_lookup(struct drm_device *drm, return intel_bo_to_drm_bo(obj); } +#if IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION) +static u32 i915_bo_fbdev_pitch_align(u32 stride) +{ + return ALIGN(stride, 64); +} + +bool i915_bo_fbdev_prefer_stolen(struct drm_i915_private *i915, unsigned int size) +{ + /* Skip stolen on MTL as Wa_22018444074 mitigation. */ + if (IS_METEORLAKE(i915)) + return false; + + /* + * If the FB is too big, just don't use it since fbdev is not very + * important and we should probably use that space with FBC or other + * features. + */ + return i915->dsm.usable_size >= size * 2; +} + +static struct drm_gem_object *i915_bo_fbdev_create(struct drm_device *drm, int size) +{ + struct drm_i915_private *i915 = to_i915(drm); + struct drm_i915_gem_object *obj; + + obj = ERR_PTR(-ENODEV); + if (HAS_LMEM(i915)) { + obj = i915_gem_object_create_lmem(i915, size, + I915_BO_ALLOC_CONTIGUOUS | + I915_BO_ALLOC_USER); + } else { + if (i915_bo_fbdev_prefer_stolen(i915, size)) + obj = i915_gem_object_create_stolen(i915, size); + else + drm_info(drm, "Allocating fbdev: Stolen memory not preferred.\n"); + + if (IS_ERR(obj)) + obj = i915_gem_object_create_shmem(i915, size); + } + + if (IS_ERR(obj)) { + drm_err(drm, "failed to allocate framebuffer (%pe)\n", obj); + return ERR_PTR(-ENOMEM); + } + + return &obj->base; +} + +static void i915_bo_fbdev_destroy(struct drm_gem_object *obj) +{ + drm_gem_object_put(obj); +} + +static int i915_bo_fbdev_fill_info(struct drm_gem_object *_obj, struct fb_info *info, + struct i915_vma *vma) +{ + struct drm_i915_private *i915 = to_i915(_obj->dev); + struct drm_i915_gem_object *obj = to_intel_bo(_obj); + struct i915_gem_ww_ctx ww; + void __iomem *vaddr; + int ret; + + if (i915_gem_object_is_lmem(obj)) { + struct intel_memory_region *mem = obj->mm.region; + + /* Use fbdev's framebuffer from lmem for discrete */ + info->fix.smem_start = + (unsigned long)(mem->io.start + + i915_gem_object_get_dma_address(obj, 0) - + mem->region.start); + info->fix.smem_len = obj->base.size; + } else { + struct i915_ggtt *ggtt = to_gt(i915)->ggtt; + + /* Our framebuffer is the entirety of fbdev's system memory */ + info->fix.smem_start = + (unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma)); + info->fix.smem_len = vma->size; + } + + for_i915_gem_ww(&ww, ret, false) { + ret = i915_gem_object_lock(vma->obj, &ww); + + if (ret) + continue; + + vaddr = i915_vma_pin_iomap(vma); + if (IS_ERR(vaddr)) { + drm_err(&i915->drm, + "Failed to remap framebuffer into virtual memory (%pe)\n", vaddr); + ret = PTR_ERR(vaddr); + continue; + } + } + + if (ret) + return ret; + + info->screen_base = vaddr; + info->screen_size = intel_bo_to_drm_bo(obj)->size; + + return 0; +} +#endif + const struct intel_display_bo_interface i915_display_bo_interface = { .is_tiled = i915_bo_is_tiled, .is_userptr = i915_bo_is_userptr, @@ -153,4 +261,10 @@ const struct intel_display_bo_interface i915_display_bo_interface = { .framebuffer_init = i915_bo_framebuffer_init, .framebuffer_fini = i915_bo_framebuffer_fini, .framebuffer_lookup = i915_bo_framebuffer_lookup, +#if IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION) + .fbdev_create = i915_bo_fbdev_create, + .fbdev_destroy = i915_bo_fbdev_destroy, + .fbdev_fill_info = i915_bo_fbdev_fill_info, + .fbdev_pitch_align = i915_bo_fbdev_pitch_align, +#endif }; diff --git a/drivers/gpu/drm/i915/i915_bo.h b/drivers/gpu/drm/i915/i915_bo.h index 57255d052dd9..39ba62696550 100644 --- a/drivers/gpu/drm/i915/i915_bo.h +++ b/drivers/gpu/drm/i915/i915_bo.h @@ -4,6 +4,12 @@ #ifndef __I915_BO_H__ #define __I915_BO_H__ +#include + +struct drm_i915_private; + +bool i915_bo_fbdev_prefer_stolen(struct drm_i915_private *i915, unsigned int size); + extern const struct intel_display_bo_interface i915_display_bo_interface; #endif /* __I915_BO_H__ */ diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 4778ba664ec7..a3e27f9e4f47 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -34,6 +34,7 @@ #include #include #include +#include #include "gem/i915_gem_context.h" #include "gt/intel_gt.h" @@ -57,7 +58,6 @@ #include "i915_reg.h" #include "i915_scheduler.h" #include "i915_wait_util.h" -#include "intel_mchbar_regs.h" static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) { diff --git a/drivers/gpu/drm/i915/i915_dpt.c b/drivers/gpu/drm/i915/i915_dpt.c index 9f47bb563c85..fcd7cced771d 100644 --- a/drivers/gpu/drm/i915/i915_dpt.c +++ b/drivers/gpu/drm/i915/i915_dpt.c @@ -129,7 +129,6 @@ static void dpt_cleanup(struct i915_address_space *vm) struct i915_vma *i915_dpt_pin_to_ggtt(struct intel_dpt *dpt, unsigned int alignment) { struct drm_i915_private *i915 = dpt->vm.i915; - struct intel_display *display = i915->display; struct ref_tracker *wakeref; struct i915_vma *vma; void __iomem *iomem; @@ -141,7 +140,7 @@ struct i915_vma *i915_dpt_pin_to_ggtt(struct intel_dpt *dpt, unsigned int alignm pin_flags |= PIN_MAPPABLE; wakeref = intel_runtime_pm_get(&i915->runtime_pm); - atomic_inc(&display->restore.pending_fb_pin); + atomic_inc(&i915->pending_fb_pin); for_i915_gem_ww(&ww, err, true) { err = i915_gem_object_lock(dpt->obj, &ww); @@ -171,7 +170,7 @@ struct i915_vma *i915_dpt_pin_to_ggtt(struct intel_dpt *dpt, unsigned int alignm dpt->obj->mm.dirty = true; - atomic_dec(&display->restore.pending_fb_pin); + atomic_dec(&i915->pending_fb_pin); intel_runtime_pm_put(&i915->runtime_pm, wakeref); return err ? ERR_PTR(err) : vma; diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index 385a634c3ed0..a4bd4f8e18b2 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -122,7 +122,6 @@ #include "intel_cpu_info.h" #include "intel_gvt.h" #include "intel_memory_region.h" -#include "intel_pci_config.h" #include "intel_pcode.h" #include "intel_region_ttm.h" #include "vlv_iosf_sb.h" @@ -311,6 +310,7 @@ static void i915_driver_late_release(struct drm_i915_private *dev_priv) i915_params_free(&dev_priv->params); intel_display_device_remove(display); + dev_priv->display = NULL; } /** @@ -750,9 +750,8 @@ static bool has_auxccs(struct drm_device *drm) { struct drm_i915_private *i915 = to_i915(drm); - return IS_GRAPHICS_VER(i915, 9, 12) || - IS_ALDERLAKE_P(i915) || - IS_METEORLAKE(i915); + return IS_GRAPHICS_VER(i915, 9, 12) && + !HAS_FLAT_CCS(i915); } static bool has_fenced_regions(struct drm_device *drm) @@ -780,7 +779,7 @@ static const struct intel_display_parent_interface parent = { .rpm = &i915_display_rpm_interface, .rps = &i915_display_rps_interface, .stolen = &i915_display_stolen_interface, - .vma = &i915_display_vma_interface, + .vlv_iosf = &i915_display_vlv_iosf_interface, .fence_priority_display = fence_priority_display, .has_auxccs = has_auxccs, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index dafee3dcd1c5..844ed79e7211 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -315,6 +315,8 @@ struct drm_i915_private { /* The TTM device structure. */ struct ttm_device bdev; + atomic_t pending_fb_pin; + I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) /* diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/i915_fb_pin.c similarity index 66% rename from drivers/gpu/drm/i915/display/intel_fb_pin.c rename to drivers/gpu/drm/i915/i915_fb_pin.c index 738d77a1468a..b0e121462ca3 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/i915_fb_pin.c @@ -9,30 +9,24 @@ #include +#include "display/intel_display_core.h" +#include "display/intel_display_types.h" +#include "display/intel_fb.h" +#include "display/intel_fb_pin.h" +#include "display/intel_plane.h" + #include "gem/i915_gem_domain.h" #include "gem/i915_gem_object.h" +#include "i915_dpt.h" #include "i915_drv.h" #include "i915_vma.h" -#include "intel_display_core.h" -#include "intel_display_rpm.h" -#include "intel_display_types.h" -#include "i915_dpt.h" -#include "intel_fb.h" -#include "intel_fb_pin.h" -#include "intel_plane.h" static struct i915_vma * -intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, - const struct i915_gtt_view *view, - unsigned int alignment, - unsigned long *out_flags, - struct intel_dpt *dpt) +intel_fb_pin_to_dpt(struct drm_gem_object *_obj, struct intel_dpt *dpt, + const struct intel_fb_pin_params *pin_params) { - struct drm_device *dev = fb->dev; - struct intel_display *display = to_intel_display(dev); - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_gem_object *_obj = intel_fb_bo(fb); + struct drm_i915_private *i915 = to_i915(_obj->dev); struct drm_i915_gem_object *obj = to_intel_bo(_obj); struct i915_address_space *vm = i915_dpt_to_vm(dpt); struct i915_gem_ww_ctx ww; @@ -43,20 +37,20 @@ intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, * We are not syncing against the binding (and potential migrations) * below, so this vm must never be async. */ - if (drm_WARN_ON(&dev_priv->drm, vm->bind_async_flags)) + if (drm_WARN_ON(&i915->drm, vm->bind_async_flags)) return ERR_PTR(-EINVAL); if (WARN_ON(!i915_gem_object_is_framebuffer(obj))) return ERR_PTR(-EINVAL); - atomic_inc(&display->restore.pending_fb_pin); + atomic_inc(&i915->pending_fb_pin); for_i915_gem_ww(&ww, ret, true) { ret = i915_gem_object_lock(obj, &ww); if (ret) continue; - if (HAS_LMEM(dev_priv)) { + if (HAS_LMEM(i915)) { unsigned int flags = obj->flags; /* @@ -65,7 +59,7 @@ intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, * ensure it is always in the mappable part of lmem, if this is * a small-bar device. */ - if (intel_fb_rc_ccs_cc_plane(fb) >= 0) + if (pin_params->needs_cpu_lmem_access) flags &= ~I915_BO_ALLOC_GPU_ONLY; ret = __i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0, flags); @@ -77,19 +71,20 @@ intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, if (ret) continue; - vma = i915_vma_instance(obj, vm, view); + vma = i915_vma_instance(obj, vm, pin_params->view); if (IS_ERR(vma)) { ret = PTR_ERR(vma); continue; } - if (i915_vma_misplaced(vma, 0, alignment, 0)) { + if (i915_vma_misplaced(vma, 0, pin_params->alignment, 0)) { ret = i915_vma_unbind(vma); if (ret) continue; } - ret = i915_vma_pin_ww(vma, &ww, 0, alignment, PIN_GLOBAL); + ret = i915_vma_pin_ww(vma, &ww, 0, pin_params->alignment, + PIN_GLOBAL); if (ret) continue; } @@ -98,41 +93,36 @@ intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, goto err; } - vma->display_alignment = max(vma->display_alignment, alignment); + vma->display_alignment = max(vma->display_alignment, + pin_params->alignment); i915_gem_object_flush_if_display(obj); i915_vma_get(vma); err: - atomic_dec(&display->restore.pending_fb_pin); + atomic_dec(&i915->pending_fb_pin); return vma; } struct i915_vma * -intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, - const struct i915_gtt_view *view, - unsigned int alignment, - unsigned int phys_alignment, - unsigned int vtd_guard, - bool uses_fence, - unsigned long *out_flags) +intel_fb_pin_to_ggtt(struct drm_gem_object *_obj, + const struct intel_fb_pin_params *pin_params, + int *out_fence_id) { - struct drm_device *dev = fb->dev; - struct intel_display *display = to_intel_display(dev); - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_gem_object *_obj = intel_fb_bo(fb); + struct drm_i915_private *i915 = to_i915(_obj->dev); struct drm_i915_gem_object *obj = to_intel_bo(_obj); - struct ref_tracker *wakeref; + intel_wakeref_t wakeref; struct i915_gem_ww_ctx ww; struct i915_vma *vma; unsigned int pinctl; int ret; - if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))) + if (drm_WARN_ON(&i915->drm, !i915_gem_object_is_framebuffer(obj))) return ERR_PTR(-EINVAL); - if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))) + if (drm_WARN_ON(&i915->drm, pin_params->alignment && + !is_power_of_2(pin_params->alignment))) return ERR_PTR(-EINVAL); /* @@ -142,42 +132,40 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, * intel_runtime_pm_put(), so it is correct to wrap only the * pin/unpin/fence and not more. */ - wakeref = intel_display_rpm_get(display); + wakeref = intel_runtime_pm_get(&i915->runtime_pm); - atomic_inc(&display->restore.pending_fb_pin); + atomic_inc(&i915->pending_fb_pin); - /* - * Valleyview is definitely limited to scanning out the first - * 512MiB. Lets presume this behaviour was inherited from the - * g4x display engine and that all earlier gen are similarly - * limited. Testing suggests that it is a little more - * complicated than this. For example, Cherryview appears quite - * happy to scanout from anywhere within its global aperture. - */ pinctl = 0; - if (HAS_GMCH(display)) + /* PIN_MAPPABLE limits the address to GMADR size */ + if (pin_params->needs_low_address) pinctl |= PIN_MAPPABLE; i915_gem_ww_ctx_init(&ww, true); retry: ret = i915_gem_object_lock(obj, &ww); - if (!ret && phys_alignment) - ret = i915_gem_object_attach_phys(obj, phys_alignment); - else if (!ret && HAS_LMEM(dev_priv)) + if (!ret && pin_params->needs_physical) + ret = i915_gem_object_attach_phys(obj, pin_params->phys_alignment); + else if (!ret && HAS_LMEM(i915)) ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0); if (!ret) ret = i915_gem_object_pin_pages(obj); if (ret) goto err; - vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment, - vtd_guard, view, pinctl); + vma = i915_gem_object_pin_to_display_plane(obj, &ww, + pin_params->alignment, + pin_params->vtd_guard, + pin_params->view, pinctl); if (IS_ERR(vma)) { ret = PTR_ERR(vma); goto err_unpin; } - if (uses_fence && i915_vma_is_map_and_fenceable(vma)) { + if (out_fence_id) + *out_fence_id = -1; + + if (out_fence_id && i915_vma_is_map_and_fenceable(vma)) { /* * Install a fence for tiled scan-out. Pre-i965 always needs a * fence, whereas 965+ only requires a fence if using @@ -196,14 +184,14 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, * mode that matches the user configuration. */ ret = i915_vma_pin_fence(vma); - if (ret != 0 && DISPLAY_VER(display) < 4) { + if (ret != 0 && pin_params->needs_fence) { i915_vma_unpin(vma); goto err_unpin; } ret = 0; if (vma->fence) - *out_flags |= PLANE_HAS_FENCE; + *out_fence_id = vma->fence->id; } i915_vma_get(vma); @@ -220,14 +208,14 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, if (ret) vma = ERR_PTR(ret); - atomic_dec(&display->restore.pending_fb_pin); - intel_display_rpm_put(display, wakeref); + atomic_dec(&i915->pending_fb_pin); + intel_runtime_pm_put(&i915->runtime_pm, wakeref); return vma; } -void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags) +void intel_fb_unpin_vma(struct i915_vma *vma, int fence_id) { - if (flags & PLANE_HAS_FENCE) + if (fence_id >= 0) i915_vma_unpin_fence(vma); i915_vma_unpin(vma); i915_vma_put(vma); @@ -265,35 +253,46 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, const struct intel_plane_state *old_plane_state) { struct intel_display *display = to_intel_display(plane_state); + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); struct i915_vma *vma; if (!intel_fb_uses_dpt(&fb->base)) { - vma = intel_fb_pin_to_ggtt(&fb->base, &plane_state->view.gtt, - intel_plane_fb_min_alignment(plane_state), - intel_plane_fb_min_phys_alignment(plane_state), - intel_plane_fb_vtd_guard(plane_state), - intel_plane_uses_fence(plane_state), - &plane_state->flags); + struct intel_fb_pin_params pin_params = { + .view = &plane_state->view.gtt, + .alignment = intel_plane_fb_min_alignment(plane_state), + .phys_alignment = intel_plane_fb_min_phys_alignment(plane_state), + .vtd_guard = intel_plane_fb_vtd_guard(plane_state), + .needs_cpu_lmem_access = intel_fb_needs_cpu_access(&fb->base), + .needs_low_address = intel_plane_needs_low_address(display), + .needs_physical = intel_plane_needs_physical(plane), + .needs_fence = intel_plane_needs_fence(display), + }; + int fence_id = -1; + + vma = intel_fb_pin_to_ggtt(intel_fb_bo(&fb->base), &pin_params, + intel_plane_uses_fence(plane_state) ? &fence_id : NULL); if (IS_ERR(vma)) return PTR_ERR(vma); plane_state->ggtt_vma = vma; - + plane_state->fence_id = fence_id; } else { - unsigned int alignment = intel_plane_fb_min_alignment(plane_state); + struct intel_fb_pin_params pin_params = { + .view = &plane_state->view.gtt, + .alignment = intel_plane_fb_min_alignment(plane_state), + .needs_cpu_lmem_access = intel_fb_needs_cpu_access(&fb->base), + }; - vma = i915_dpt_pin_to_ggtt(fb->dpt, alignment / 512); + vma = i915_dpt_pin_to_ggtt(fb->dpt, pin_params.alignment / 512); if (IS_ERR(vma)) return PTR_ERR(vma); plane_state->ggtt_vma = vma; - vma = intel_fb_pin_to_dpt(&fb->base, &plane_state->view.gtt, - alignment, &plane_state->flags, - fb->dpt); + vma = intel_fb_pin_to_dpt(intel_fb_bo(&fb->base), fb->dpt, &pin_params); if (IS_ERR(vma)) { i915_dpt_unpin_from_ggtt(fb->dpt); plane_state->ggtt_vma = NULL; @@ -308,7 +307,7 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, * The DPT object contains only one vma, and there is no VT-d * guard, so the VMA's offset within the DPT is always 0. */ - drm_WARN_ON(display->drm, i915_dpt_offset(plane_state->dpt_vma)); + drm_WARN_ON(&i915->drm, i915_dpt_offset(plane_state->dpt_vma)); } /* @@ -338,12 +337,14 @@ void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) if (!intel_fb_uses_dpt(&fb->base)) { vma = fetch_and_zero(&old_plane_state->ggtt_vma); - if (vma) - intel_fb_unpin_vma(vma, old_plane_state->flags); + if (vma) { + intel_fb_unpin_vma(vma, old_plane_state->fence_id); + old_plane_state->fence_id = -1; + } } else { vma = fetch_and_zero(&old_plane_state->dpt_vma); if (vma) - intel_fb_unpin_vma(vma, old_plane_state->flags); + intel_fb_unpin_vma(vma, -1); vma = fetch_and_zero(&old_plane_state->ggtt_vma); if (vma) diff --git a/drivers/gpu/drm/i915/i915_freq.c b/drivers/gpu/drm/i915/i915_freq.c index 9bdaea34aef9..9547d087555f 100644 --- a/drivers/gpu/drm/i915/i915_freq.c +++ b/drivers/gpu/drm/i915/i915_freq.c @@ -2,10 +2,10 @@ /* Copyright © 2025 Intel Corporation */ #include +#include #include "i915_drv.h" #include "i915_freq.h" -#include "intel_mchbar_regs.h" unsigned int i9xx_fsb_freq(struct drm_i915_private *i915) { diff --git a/drivers/gpu/drm/i915/i915_gmch.c b/drivers/gpu/drm/i915/i915_gmch.c index 2d55831b3c58..b0ef6ef577a3 100644 --- a/drivers/gpu/drm/i915/i915_gmch.c +++ b/drivers/gpu/drm/i915/i915_gmch.c @@ -5,10 +5,10 @@ #include #include +#include #include "i915_drv.h" #include "i915_gmch.h" -#include "intel_pci_config.h" static void i915_gmch_bridge_release(struct drm_device *dev, void *bridge) { diff --git a/drivers/gpu/drm/i915/i915_gtt_view_types.h b/drivers/gpu/drm/i915/i915_gtt_view_types.h index c084f67bc880..9c4f38db32ff 100644 --- a/drivers/gpu/drm/i915/i915_gtt_view_types.h +++ b/drivers/gpu/drm/i915/i915_gtt_view_types.h @@ -56,4 +56,19 @@ struct i915_gtt_view { }; }; +static inline bool i915_gtt_view_is_normal(const struct i915_gtt_view *view) +{ + return view->type == I915_GTT_VIEW_NORMAL; +} + +static inline bool i915_gtt_view_is_remapped(const struct i915_gtt_view *view) +{ + return view->type == I915_GTT_VIEW_REMAPPED; +} + +static inline bool i915_gtt_view_is_rotated(const struct i915_gtt_view *view) +{ + return view->type == I915_GTT_VIEW_ROTATED; +} + #endif /* __I915_GTT_VIEW_TYPES_H__ */ diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c index c4a799f5fe92..da643b38064c 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.c +++ b/drivers/gpu/drm/i915/i915_hwmon.c @@ -10,11 +10,11 @@ #include #include +#include #include "i915_drv.h" #include "i915_hwmon.h" #include "i915_reg.h" -#include "intel_mchbar_regs.h" #include "intel_pcode.h" #include "gt/intel_gt.h" #include "gt/intel_gt_regs.h" diff --git a/drivers/gpu/drm/i915/i915_initial_plane.c b/drivers/gpu/drm/i915/i915_initial_plane.c index 390a9248d631..4902c0748664 100644 --- a/drivers/gpu/drm/i915/i915_initial_plane.c +++ b/drivers/gpu/drm/i915/i915_initial_plane.c @@ -9,18 +9,13 @@ #include "display/intel_crtc.h" #include "display/intel_display_types.h" #include "display/intel_fb.h" -#include "display/intel_fbdev_fb.h" #include "gem/i915_gem_lmem.h" #include "gem/i915_gem_region.h" +#include "i915_bo.h" #include "i915_drv.h" #include "i915_initial_plane.h" -static void i915_initial_plane_vblank_wait(struct drm_crtc *crtc) -{ - intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); -} - static enum intel_memory_type initial_plane_memory_type(struct drm_i915_private *i915) { @@ -34,14 +29,14 @@ initial_plane_memory_type(struct drm_i915_private *i915) static bool initial_plane_phys(struct drm_i915_private *i915, - struct intel_initial_plane_config *plane_config) + u32 base, resource_size_t *out_phys_base, + struct intel_memory_region **out_mem) { struct i915_ggtt *ggtt = to_gt(i915)->ggtt; struct intel_memory_region *mem; enum intel_memory_type mem_type; bool is_present, is_local; dma_addr_t dma_addr; - u32 base; mem_type = initial_plane_memory_type(i915); mem = intel_memory_region_by_type(i915, mem_type); @@ -52,7 +47,7 @@ initial_plane_phys(struct drm_i915_private *i915, return false; } - base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT); + base = round_down(base, I915_GTT_MIN_ALIGNMENT); dma_addr = intel_ggtt_read_entry(&ggtt->vm, base, &is_present, &is_local); @@ -77,8 +72,8 @@ initial_plane_phys(struct drm_i915_private *i915, drm_dbg(&i915->drm, "Using dma_addr=%pa, based on initial plane programming\n", &dma_addr); - plane_config->phys_base = dma_addr - mem->region.start; - plane_config->mem = mem; + *out_phys_base = dma_addr - mem->region.start; + *out_mem = mem; return true; } @@ -99,12 +94,9 @@ initial_plane_vma(struct drm_i915_private *i915, if (plane_config->size == 0) return NULL; - if (!initial_plane_phys(i915, plane_config)) + if (!initial_plane_phys(i915, plane_config->base, &phys_base, &mem)) return NULL; - phys_base = plane_config->phys_base; - mem = plane_config->mem; - base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT); size = round_up(plane_config->base + plane_config->size, mem->min_page_size); @@ -118,7 +110,7 @@ initial_plane_vma(struct drm_i915_private *i915, if (IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION) && IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) && mem == i915->mm.stolen_region && - !intel_fbdev_fb_prefer_stolen(&i915->drm, size)) { + !i915_bo_fbdev_prefer_stolen(i915, size)) { drm_dbg_kms(&i915->drm, "Initial FB size exceeds half of stolen, discarding\n"); return NULL; } @@ -140,7 +132,7 @@ initial_plane_vma(struct drm_i915_private *i915, i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE); - tiling = intel_fb_modifier_to_tiling(plane_config->fb->base.modifier); + tiling = intel_fb_modifier_to_tiling(plane_config->fb->modifier); switch (tiling) { case I915_TILING_NONE: @@ -148,7 +140,7 @@ initial_plane_vma(struct drm_i915_private *i915, case I915_TILING_X: case I915_TILING_Y: obj->tiling_and_stride = - plane_config->fb->base.pitches[0] | + plane_config->fb->pitches[0] | tiling; break; default: @@ -226,7 +218,7 @@ i915_alloc_initial_plane_obj(struct drm_device *drm, { struct drm_i915_private *i915 = to_i915(drm); struct drm_mode_fb_cmd2 mode_cmd = {}; - struct drm_framebuffer *fb = &plane_config->fb->base; + struct drm_framebuffer *fb = plane_config->fb; struct i915_vma *vma; vma = initial_plane_vma(i915, plane_config); @@ -268,7 +260,7 @@ i915_initial_plane_setup(struct drm_plane_state *_plane_state, plane_state->ggtt_vma = i915_vma_get(vma); if (intel_plane_uses_fence(plane_state) && i915_vma_pin_fence(vma) == 0 && vma->fence) - plane_state->flags |= PLANE_HAS_FENCE; + plane_state->fence_id = vma->fence->id; plane_state->surf = i915_ggtt_offset(plane_state->ggtt_vma); @@ -285,7 +277,6 @@ static void i915_plane_config_fini(struct intel_initial_plane_config *plane_conf } const struct intel_display_initial_plane_interface i915_display_initial_plane_interface = { - .vblank_wait = i915_initial_plane_vblank_wait, .alloc_obj = i915_alloc_initial_plane_obj, .setup = i915_initial_plane_setup, .config_fini = i915_plane_config_fini, diff --git a/drivers/gpu/drm/i915/i915_overlay.c b/drivers/gpu/drm/i915/i915_overlay.c index c2d712bd2b0d..6de550a17756 100644 --- a/drivers/gpu/drm/i915/i915_overlay.c +++ b/drivers/gpu/drm/i915/i915_overlay.c @@ -7,6 +7,7 @@ #include #include +#include #include "gem/i915_gem_internal.h" #include "gem/i915_gem_object_frontbuffer.h" @@ -18,7 +19,6 @@ #include "i915_drv.h" #include "i915_overlay.h" #include "i915_reg.h" -#include "intel_pci_config.h" #include "display/intel_frontbuffer.h" @@ -354,11 +354,14 @@ static struct i915_vma *i915_overlay_pin_fb(struct drm_device *drm, struct drm_gem_object *obj, u32 *offset) { + struct drm_i915_private *i915 = to_i915(drm); struct drm_i915_gem_object *new_bo = to_intel_bo(obj); struct i915_gem_ww_ctx ww; struct i915_vma *vma; int ret; + atomic_inc(&i915->pending_fb_pin); + i915_gem_ww_ctx_init(&ww, true); retry: ret = i915_gem_object_lock(new_bo, &ww); @@ -373,6 +376,9 @@ static struct i915_vma *i915_overlay_pin_fb(struct drm_device *drm, goto retry; } i915_gem_ww_ctx_fini(&ww); + + atomic_dec(&i915->pending_fb_pin); + if (ret) return ERR_PTR(ret); diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index d966a00520f1..82415af47d54 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -24,6 +24,7 @@ #include #include +#include #include #include "display/intel_display_driver.h" @@ -35,7 +36,6 @@ #include "i915_drv.h" #include "i915_pci.h" #include "i915_reg.h" -#include "intel_pci_config.h" __diag_push(); __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for device info"); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5d99b99b0c57..64e906380131 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -494,21 +494,6 @@ #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ #define GEN7_FF_DS_SCHED_HW (0x0 << 4) -#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) -#define ILK_FBCQ_DIS REG_BIT(22) -#define ILK_PABSTRETCH_DIS REG_BIT(21) -#define ILK_SABSTRETCH_DIS REG_BIT(20) -#define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) -#define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) -#define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) -#define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) -#define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) -#define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) -#define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) -#define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) -#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) -#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) - #define DPLL_TEST _MMIO(0x606c) #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) @@ -700,26 +685,10 @@ #define DG1_MSTR_IRQ REG_BIT(31) #define DG1_MSTR_TILE(t) REG_BIT(t) -#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) -/* Required on all Ironlake and Sandybridge according to the B-Spec. */ -#define ILK_ELPIN_409_SELECT REG_BIT(25) -#define ILK_DPARB_GATE REG_BIT(22) -#define ILK_VSDPFD_FULL REG_BIT(21) - -#define ILK_DSPCLK_GATE_D _MMIO(0x42020) -#define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28) -#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9) -#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8) -#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7) -#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5) - #define IVB_CHICKEN3 _MMIO(0x4200c) #define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5) #define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2) -#define CHICKEN_PAR2_1 _MMIO(0x42090) -#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) - #define VLV_PMWGICZ _MMIO(0x1300a4) #define HSW_EDRAM_CAP _MMIO(0x120010) diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 6a3a4d4244dc..afc192d9931b 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -27,7 +27,6 @@ #include #include -#include #include "display/intel_fb.h" #include "display/intel_frontbuffer.h" @@ -2333,12 +2332,3 @@ int __init i915_vma_module_init(void) return 0; } - -static int i915_vma_fence_id(const struct i915_vma *vma) -{ - return vma->fence ? vma->fence->id : -1; -} - -const struct intel_display_vma_interface i915_display_vma_interface = { - .fence_id = i915_vma_fence_id, -}; diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index fa2d9b429db6..892306ab935d 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -476,6 +476,4 @@ int i915_vma_module_init(void); I915_SELFTEST_DECLARE(int i915_vma_get_pages(struct i915_vma *vma)); I915_SELFTEST_DECLARE(void i915_vma_put_pages(struct i915_vma *vma)); -extern const struct intel_display_vma_interface i915_display_vma_interface; - #endif diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index ee2489a2fbe7..86bdeb20f427 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -26,13 +26,11 @@ */ #include -#include #include +#include +#include -#include "display/i9xx_plane_regs.h" -#include "display/intel_display.h" -#include "display/intel_display_core.h" -#include "display/intel_display_regs.h" +#include "display/intel_display_clock_gating.h" #include "display/intel_pch.h" #include "gt/intel_engine_regs.h" #include "gt/intel_gt.h" @@ -42,43 +40,14 @@ #include "i915_drv.h" #include "i915_reg.h" #include "intel_clock_gating.h" -#include "intel_mchbar_regs.h" #include "vlv_iosf_sb.h" struct drm_i915_clock_gating_funcs { void (*init_clock_gating)(struct drm_i915_private *i915); }; -static void gen9_init_clock_gating(struct drm_i915_private *i915) -{ - if (HAS_LLC(i915)) { - /* - * WaCompressedResourceDisplayNewHashMode:skl,kbl - * Display WA #0390: skl,kbl - * - * Must match Sampler, Pixel Back End, and Media. See - * WaCompressedResourceSamplerPbeMediaNewHashMode. - */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE); - } - - /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP); - - /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */ - intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM); - - /* - * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl - * Display WA #0859: skl,bxt,kbl,glk,cfl - */ - intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE); -} - static void bxt_init_clock_gating(struct drm_i915_private *i915) { - gen9_init_clock_gating(i915); - /* WaDisableSDEUnitClockGating:bxt */ intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); @@ -88,111 +57,23 @@ static void bxt_init_clock_gating(struct drm_i915_private *i915) */ intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); - /* - * Wa: Backlight PWM may stop in the asserted state, causing backlight - * to stay fully on. - */ - intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0, - intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | - PWM1_GATING_DIS | PWM2_GATING_DIS); - - /* - * Lower the display internal timeout. - * This is needed to avoid any hard hangs when DSI port PLL - * is off and a MMIO access is attempted by any privilege - * application, using batch buffers or any other means. - */ - intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950)); - - /* - * WaFbcTurnOffFbcWatermark:bxt - * Display WA #0562: bxt - */ - intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); + intel_display_bxt_init_clock_gating(i915->display); } static void glk_init_clock_gating(struct drm_i915_private *i915) { - gen9_init_clock_gating(i915); - - /* - * WaDisablePWMClockGating:glk - * Backlight PWM may stop in the asserted state, causing backlight - * to stay fully on. - */ - intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0, - intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | - PWM1_GATING_DIS | PWM2_GATING_DIS); -} - -static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) -{ - struct intel_display *display = dev_priv->display; - enum pipe pipe; - - for_each_pipe(display, pipe) { - intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe), - 0, DISP_TRICKLE_FEED_DISABLE); - - intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe), - 0, 0); - intel_uncore_posting_read(&dev_priv->uncore, - DSPSURF(display, pipe)); - } + intel_display_glk_init_clock_gating(i915->display); } static void ilk_init_clock_gating(struct drm_i915_private *i915) { - u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; - - /* - * Required for FBC - * WaFbcDisableDpfcClockGating:ilk - */ - dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | - ILK_DPFCUNIT_CLOCK_GATE_DISABLE | - ILK_DPFDUNIT_CLOCK_GATE_ENABLE; - intel_uncore_write(&i915->uncore, PCH_3DCGDIS0, MARIUNIT_CLOCK_GATE_DISABLE | SVSMUNIT_CLOCK_GATE_DISABLE); intel_uncore_write(&i915->uncore, PCH_3DCGDIS1, VFMUNIT_CLOCK_GATE_DISABLE); - /* - * According to the spec the following bits should be set in - * order to enable memory self-refresh - * The bit 22/21 of 0x42004 - * The bit 5 of 0x42020 - * The bit 15 of 0x45000 - */ - intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2, - (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | - ILK_DPARB_GATE | ILK_VSDPFD_FULL)); - dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; - intel_uncore_write(&i915->uncore, DISP_ARB_CTL, - (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) | - DISP_FBC_WM_DIS)); - - /* - * Based on the document from hardware guys the following bits - * should be set unconditionally in order to enable FBC. - * The bit 22 of 0x42000 - * The bit 22 of 0x42004 - * The bit 7,8,9 of 0x42020. - */ - if (IS_IRONLAKE_M(i915)) { - /* WaFbcAsynchFlipDisableFbcQueue:ilk */ - intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); - intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE); - } - - intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); - - intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); - - g4x_disable_trickle_feed(i915); - + intel_display_ilk_init_clock_gating(i915->display); intel_pch_init_clock_gating(i915->display); } @@ -209,11 +90,7 @@ static void gen6_check_mch_setup(struct drm_i915_private *i915) static void gen6_init_clock_gating(struct drm_i915_private *i915) { - u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; - - intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); - - intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); + intel_display_gen6_init_clock_gating(i915->display); intel_uncore_write(&i915->uncore, GEN6_UCGCTL1, intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) | @@ -248,19 +125,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *i915) * * WaFbcAsynchFlipDisableFbcQueue:snb */ - intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1, - intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) | - ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); - intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2, - intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | - ILK_DPARB_GATE | ILK_VSDPFD_FULL); - intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, - intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) | - ILK_DPARBUNIT_CLOCK_GATE_ENABLE | - ILK_DPFDUNIT_CLOCK_GATE_ENABLE); - - g4x_disable_trickle_feed(i915); - intel_pch_init_clock_gating(i915->display); gen6_check_mch_setup(i915); @@ -302,22 +166,15 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915) static void cfl_init_clock_gating(struct drm_i915_private *i915) { intel_pch_init_clock_gating(i915->display); - gen9_init_clock_gating(i915); /* WAC6entrylatency:cfl */ intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); - /* - * WaFbcTurnOffFbcWatermark:cfl - * Display WA #0562: cfl - */ - intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); + intel_display_cfl_init_clock_gating(i915->display); } static void kbl_init_clock_gating(struct drm_i915_private *i915) { - gen9_init_clock_gating(i915); - /* WAC6entrylatency:kbl */ intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); @@ -331,17 +188,11 @@ static void kbl_init_clock_gating(struct drm_i915_private *i915) intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE); - /* - * WaFbcTurnOffFbcWatermark:kbl - * Display WA #0562: kbl - */ - intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); + intel_display_kbl_init_clock_gating(i915->display); } static void skl_init_clock_gating(struct drm_i915_private *i915) { - gen9_init_clock_gating(i915); - /* WaDisableDopClockGating:skl */ intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL, GEN7_DOP_CLOCK_GATE_ENABLE, 0); @@ -349,32 +200,17 @@ static void skl_init_clock_gating(struct drm_i915_private *i915) /* WAC6entrylatency:skl */ intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); - /* - * WaFbcTurnOffFbcWatermark:skl - * Display WA #0562: skl - */ - intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); + intel_display_skl_init_clock_gating(i915->display); } static void bdw_init_clock_gating(struct drm_i915_private *i915) { - struct intel_display *display = i915->display; - enum pipe pipe; - - /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); + intel_display_bdw_clock_gating_disable_fbcq(i915->display); /* WaSwitchSolVfFArbitrationPriority:bdw */ intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); - /* WaPsrDPAMaskVBlankInSRD:bdw */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); - - for_each_pipe(display, pipe) { - /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), - 0, BDW_UNMASK_VBL_TO_REGS_IN_SRD); - } + intel_display_bdw_clock_gating_vblank_in_srd(i915->display); /* WaVSRefCountFullforceMissDisable:bdw */ /* WaDSRefCountFullforceMissDisable:bdw */ @@ -390,9 +226,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *i915) /* WaProgramL3SqcReg1Default:bdw */ gen8_set_l3sqc_credits(i915, 30, 2); - /* WaKVMNotificationOnConfigChange:bdw */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1, - 0, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); + intel_display_bdw_clock_gating_kvm_notif(i915->display); intel_pch_init_clock_gating(i915->display); @@ -406,20 +240,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *i915) static void hsw_init_clock_gating(struct drm_i915_private *i915) { - struct intel_display *display = i915->display; - enum pipe pipe; - - /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); - - /* WaPsrDPAMaskVBlankInSRD:hsw */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); - - for_each_pipe(display, pipe) { - /* WaPsrDPRSUnmaskVBlankInSRD:hsw */ - intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), - 0, HSW_UNMASK_VBL_TO_REGS_IN_SRD); - } + intel_display_hsw_init_clock_gating(i915->display); /* This is required by WaCatErrorRejectionIssue:hsw */ intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, @@ -435,10 +256,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915) { struct intel_display *display = i915->display; - intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); - - /* WaFbcAsynchFlipDisableFbcQueue:ivb */ - intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); + intel_display_ivb_init_clock_gating(display); /* WaDisableBackToBackFlipFix:ivb */ intel_uncore_write(&i915->uncore, IVB_CHICKEN3, @@ -467,13 +285,12 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915) intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); - g4x_disable_trickle_feed(i915); + intel_display_disable_trickle_feed(display); intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK, GEN6_MBC_SNPCR_MED); - if (!HAS_PCH_NOP(display)) - intel_pch_init_clock_gating(display); + intel_pch_init_clock_gating(display); gen6_check_mch_setup(i915); } @@ -540,21 +357,12 @@ static void chv_init_clock_gating(struct drm_i915_private *i915) static void g4x_init_clock_gating(struct drm_i915_private *i915) { - u32 dspclk_gate; - intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0); intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | GS_UNIT_CLOCK_GATE_DISABLE | CL_UNIT_CLOCK_GATE_DISABLE); intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0); - dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | - OVRUNIT_CLOCK_GATE_DISABLE | - OVCUNIT_CLOCK_GATE_DISABLE; - if (IS_GM45(i915)) - dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; - intel_uncore_write(&i915->uncore, DSPCLK_GATE_D, dspclk_gate); - - g4x_disable_trickle_feed(i915); + intel_display_g4x_init_clock_gating(i915->display); } static void i965gm_init_clock_gating(struct drm_i915_private *i915) @@ -563,7 +371,7 @@ static void i965gm_init_clock_gating(struct drm_i915_private *i915) intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); intel_uncore_write(uncore, RENCLK_GATE_D2, 0); - intel_uncore_write(uncore, DSPCLK_GATE_D, 0); + intel_display_i965gm_init_clock_gating(i915->display); intel_uncore_write(uncore, RAMCLK_GATE_D, 0); intel_uncore_write16(uncore, DEUC, 0); intel_uncore_write(uncore, diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index ae42818ab6e0..de118fae0a49 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -7,6 +7,7 @@ #include #include +#include #include "display/bxt_dpio_phy_regs.h" #include "display/i9xx_plane_regs.h" @@ -44,7 +45,6 @@ #include "i915_pvinfo.h" #include "i915_reg.h" #include "intel_gvt.h" -#include "intel_mchbar_regs.h" #define MMIO_F(reg, s) do { \ int ret; \ diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index 27dc0e40a8d7..796c9b070e41 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -277,6 +277,7 @@ void mock_destroy_device(struct drm_i915_private *i915) struct device *dev = i915->drm.dev; intel_display_device_remove(i915->display); + i915->display = NULL; devres_release_group(dev, NULL); put_device(dev); diff --git a/drivers/gpu/drm/i915/vlv_iosf_sb.c b/drivers/gpu/drm/i915/vlv_iosf_sb.c index 38a75651b0dc..1f0332b4ad0d 100644 --- a/drivers/gpu/drm/i915/vlv_iosf_sb.c +++ b/drivers/gpu/drm/i915/vlv_iosf_sb.c @@ -4,6 +4,7 @@ */ #include +#include #include "i915_drv.h" #include "i915_iosf_mbi.h" @@ -229,3 +230,10 @@ void vlv_iosf_sb_fini(struct drm_i915_private *i915) if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) mutex_destroy(&i915->vlv_iosf_sb.lock); } + +const struct intel_display_vlv_iosf_interface i915_display_vlv_iosf_interface = { + .get = vlv_iosf_sb_get, + .put = vlv_iosf_sb_put, + .read = vlv_iosf_sb_read, + .write = vlv_iosf_sb_write, +}; diff --git a/drivers/gpu/drm/i915/vlv_iosf_sb.h b/drivers/gpu/drm/i915/vlv_iosf_sb.h index e2fea29a30ea..8129ba11c750 100644 --- a/drivers/gpu/drm/i915/vlv_iosf_sb.h +++ b/drivers/gpu/drm/i915/vlv_iosf_sb.h @@ -8,23 +8,11 @@ #include -#include "vlv_iosf_sb_reg.h" +#include struct drm_device; struct drm_i915_private; -enum vlv_iosf_sb_unit { - VLV_IOSF_SB_BUNIT, - VLV_IOSF_SB_CCK, - VLV_IOSF_SB_CCU, - VLV_IOSF_SB_DPIO, - VLV_IOSF_SB_DPIO_2, - VLV_IOSF_SB_FLISDSI, - VLV_IOSF_SB_GPIO, - VLV_IOSF_SB_NC, - VLV_IOSF_SB_PUNIT, -}; - void vlv_iosf_sb_init(struct drm_i915_private *i915); void vlv_iosf_sb_fini(struct drm_i915_private *i915); @@ -34,4 +22,6 @@ void vlv_iosf_sb_put(struct drm_device *drm, unsigned long unit_mask); u32 vlv_iosf_sb_read(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr); int vlv_iosf_sb_write(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr, u32 val); +extern const struct intel_display_vlv_iosf_interface i915_display_vlv_iosf_interface; + #endif /* _VLV_IOSF_SB_H_ */ diff --git a/drivers/gpu/drm/imagination/pvr_fw_trace.c b/drivers/gpu/drm/imagination/pvr_fw_trace.c index 458d9ab8193e..6bb5baa6c41b 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_trace.c +++ b/drivers/gpu/drm/imagination/pvr_fw_trace.c @@ -558,6 +558,6 @@ pvr_fw_trace_debugfs_init(struct pvr_device *pvr_dev, struct dentry *dir) &pvr_fw_trace_fops); } - debugfs_create_file("trace_mask", 0600, dir, fw_trace, + debugfs_create_file("trace_mask", 0600, dir, pvr_dev, &pvr_fw_trace_mask_fops); } diff --git a/drivers/gpu/drm/imx/dc/dc-crtc.c b/drivers/gpu/drm/imx/dc/dc-crtc.c index 608c610662dc..764510ff90a4 100644 --- a/drivers/gpu/drm/imx/dc/dc-crtc.c +++ b/drivers/gpu/drm/imx/dc/dc-crtc.c @@ -148,7 +148,7 @@ dc_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) } static int -dc_crtc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) +dc_crtc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -164,7 +164,7 @@ dc_crtc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) } static void -dc_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state) +dc_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -188,7 +188,7 @@ dc_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state) } static void -dc_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state) +dc_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -222,7 +222,7 @@ dc_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state) } static void -dc_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) +dc_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -294,7 +294,7 @@ dc_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) } static void -dc_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state) +dc_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/imx/dc/dc-plane.c b/drivers/gpu/drm/imx/dc/dc-plane.c index e40d5d66c5c1..dea7404fe659 100644 --- a/drivers/gpu/drm/imx/dc/dc-plane.c +++ b/drivers/gpu/drm/imx/dc/dc-plane.c @@ -89,7 +89,7 @@ static int dc_plane_check_fb(struct drm_plane_state *state) } static int -dc_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) +dc_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -127,7 +127,7 @@ dc_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) } static void -dc_plane_atomic_update(struct drm_plane *plane, struct drm_atomic_state *state) +dc_plane_atomic_update(struct drm_plane *plane, struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -176,7 +176,7 @@ dc_plane_atomic_update(struct drm_plane *plane, struct drm_atomic_state *state) } static void dc_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dc_plane *dplane = to_dc_plane(plane); const struct dc_fu_ops *fu_ops; diff --git a/drivers/gpu/drm/imx/dcss/dcss-crtc.c b/drivers/gpu/drm/imx/dcss/dcss-crtc.c index af91e45b5d13..ab41759a9f52 100644 --- a/drivers/gpu/drm/imx/dcss/dcss-crtc.c +++ b/drivers/gpu/drm/imx/dcss/dcss-crtc.c @@ -53,13 +53,13 @@ static const struct drm_crtc_funcs dcss_crtc_funcs = { }; static void dcss_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { drm_crtc_vblank_on(crtc); } static void dcss_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dcss_crtc *dcss_crtc = container_of(crtc, struct dcss_crtc, base); @@ -78,7 +78,7 @@ static void dcss_crtc_atomic_flush(struct drm_crtc *crtc, } static void dcss_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -114,7 +114,7 @@ static void dcss_crtc_atomic_enable(struct drm_crtc *crtc, } static void dcss_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/imx/dcss/dcss-plane.c b/drivers/gpu/drm/imx/dcss/dcss-plane.c index c014ef70dfd1..1746dc5d4b64 100644 --- a/drivers/gpu/drm/imx/dcss/dcss-plane.c +++ b/drivers/gpu/drm/imx/dcss/dcss-plane.c @@ -140,7 +140,7 @@ static bool dcss_plane_is_source_size_allowed(u16 src_w, u16 src_h, u32 pix_fmt) } static int dcss_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -267,7 +267,7 @@ static bool dcss_plane_needs_setup(struct drm_plane_state *state, } static void dcss_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -352,7 +352,7 @@ static void dcss_plane_atomic_update(struct drm_plane *plane, } static void dcss_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dcss_plane *dcss_plane = to_dcss_plane(plane); struct dcss_dev *dcss = plane->dev->dev_private; diff --git a/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c b/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c index eddb471119c6..51a0ec043248 100644 --- a/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c +++ b/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c @@ -38,7 +38,7 @@ module_param(legacyfb_depth, int, 0444); DEFINE_DRM_GEM_DMA_FOPS(imx_drm_driver_fops); static int imx_drm_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { int ret; @@ -68,7 +68,7 @@ static const struct drm_mode_config_funcs imx_drm_mode_config_funcs = { .atomic_commit = drm_atomic_helper_commit, }; -static void imx_drm_atomic_commit_tail(struct drm_atomic_state *state) +static void imx_drm_atomic_commit_tail(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; struct drm_plane *plane; diff --git a/drivers/gpu/drm/imx/ipuv3/imx-drm.h b/drivers/gpu/drm/imx/ipuv3/imx-drm.h index 0c85bf83ffbf..2c0f4bd2569b 100644 --- a/drivers/gpu/drm/imx/ipuv3/imx-drm.h +++ b/drivers/gpu/drm/imx/ipuv3/imx-drm.h @@ -26,6 +26,6 @@ int imx_drm_encoder_parse_of(struct drm_device *drm, struct drm_encoder *encoder, struct device_node *np); int ipu_planes_assign_pre(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); #endif /* _IMX_DRM_H_ */ diff --git a/drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c index a18b9d1a68b6..1405e50ee56b 100644 --- a/drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c +++ b/drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c @@ -47,7 +47,7 @@ static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc) } static void ipu_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); @@ -79,7 +79,7 @@ static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc, } static void ipu_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -226,7 +226,7 @@ static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc, } static int ipu_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -239,13 +239,13 @@ static int ipu_crtc_atomic_check(struct drm_crtc *crtc, } static void ipu_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { drm_crtc_vblank_on(crtc); } static void ipu_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { spin_lock_irq(&crtc->dev->event_lock); if (crtc->state->event) { diff --git a/drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c index c1c7be4e26c6..c7ec09e557c1 100644 --- a/drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c +++ b/drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c @@ -365,7 +365,7 @@ static const struct drm_plane_funcs ipu_plane_funcs = { }; static int ipu_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -527,7 +527,7 @@ static int ipu_plane_atomic_check(struct drm_plane *plane, } static void ipu_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ipu_plane *ipu_plane = to_ipu_plane(plane); @@ -572,7 +572,7 @@ static void ipu_calculate_bursts(u32 width, u32 cpp, u32 stride, } static void ipu_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -804,7 +804,7 @@ bool ipu_plane_atomic_update_pending(struct drm_plane *plane) return false; } int ipu_planes_assign_pre(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_crtc_state, *crtc_state; struct drm_plane_state *plane_state; diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index 70088db34f69..42c86f195c66 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -140,7 +140,7 @@ to_ingenic_drm_priv_state(struct drm_private_state *state) } static struct ingenic_drm_private_state * -ingenic_drm_get_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state) +ingenic_drm_get_priv_state(struct ingenic_drm *priv, struct drm_atomic_commit *state) { struct drm_private_state *priv_state; @@ -152,7 +152,7 @@ ingenic_drm_get_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *st } static struct ingenic_drm_private_state * -ingenic_drm_get_new_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state) +ingenic_drm_get_new_priv_state(struct ingenic_drm *priv, struct drm_atomic_commit *state) { struct drm_private_state *priv_state; @@ -229,7 +229,7 @@ static int ingenic_drm_update_pixclk(struct notifier_block *nb, } static void ingenic_drm_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ingenic_drm *priv = drm_device_get_priv(bridge->dev); @@ -241,7 +241,7 @@ static void ingenic_drm_bridge_atomic_enable(struct drm_bridge *bridge, } static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ingenic_drm *priv = drm_crtc_get_priv(crtc); struct ingenic_drm_private_state *priv_state; @@ -260,7 +260,7 @@ static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, } static void ingenic_drm_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ingenic_drm *priv = drm_device_get_priv(bridge->dev); unsigned int var; @@ -274,7 +274,7 @@ static void ingenic_drm_bridge_atomic_disable(struct drm_bridge *bridge, } static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { drm_crtc_vblank_off(crtc); } @@ -334,7 +334,7 @@ static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv, } static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -404,7 +404,7 @@ ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode } static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -426,7 +426,7 @@ static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc, } static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ingenic_drm *priv = drm_crtc_get_priv(crtc); struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, @@ -459,7 +459,7 @@ static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc, } static int ingenic_drm_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); @@ -556,7 +556,7 @@ void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane) } static void ingenic_drm_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ingenic_drm *priv = drm_device_get_priv(plane->dev); @@ -660,7 +660,7 @@ static void ingenic_drm_update_palette(struct ingenic_drm *priv, } static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ingenic_drm *priv = drm_device_get_priv(plane->dev); struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/ingenic/ingenic-ipu.c b/drivers/gpu/drm/ingenic/ingenic-ipu.c index 34545b9c8c33..56143a191f36 100644 --- a/drivers/gpu/drm/ingenic/ingenic-ipu.c +++ b/drivers/gpu/drm/ingenic/ingenic-ipu.c @@ -86,7 +86,7 @@ to_ingenic_ipu_priv_state(struct drm_private_state *state) } static struct ingenic_ipu_private_state * -ingenic_ipu_get_priv_state(struct ingenic_ipu *priv, struct drm_atomic_state *state) +ingenic_ipu_get_priv_state(struct ingenic_ipu *priv, struct drm_atomic_commit *state) { struct drm_private_state *priv_state; @@ -98,7 +98,7 @@ ingenic_ipu_get_priv_state(struct ingenic_ipu *priv, struct drm_atomic_state *st } static struct ingenic_ipu_private_state * -ingenic_ipu_get_new_priv_state(struct ingenic_ipu *priv, struct drm_atomic_state *state) +ingenic_ipu_get_new_priv_state(struct ingenic_ipu *priv, struct drm_atomic_commit *state) { struct drm_private_state *priv_state; @@ -321,7 +321,7 @@ static inline bool osd_changed(struct drm_plane_state *state, } static void ingenic_ipu_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane); struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, plane); @@ -565,7 +565,7 @@ static void ingenic_ipu_plane_atomic_update(struct drm_plane *plane, } static int ingenic_ipu_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); @@ -653,7 +653,7 @@ static int ingenic_ipu_plane_atomic_check(struct drm_plane *plane, } static void ingenic_ipu_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane); diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 647872f65bff..1dcdc55b0069 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -66,7 +66,7 @@ static const struct drm_crtc_funcs kmb_crtc_funcs = { }; static void kmb_crtc_set_mode(struct drm_crtc *crtc, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct drm_device *dev = crtc->dev; struct drm_display_mode *m = &crtc->state->adjusted_mode; @@ -133,7 +133,7 @@ static void kmb_crtc_set_mode(struct drm_crtc *crtc, } static void kmb_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct kmb_drm_private *kmb = crtc_to_kmb_priv(crtc); @@ -143,7 +143,7 @@ static void kmb_crtc_atomic_enable(struct drm_crtc *crtc, } static void kmb_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct kmb_drm_private *kmb = crtc_to_kmb_priv(crtc); struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -156,7 +156,7 @@ static void kmb_crtc_atomic_disable(struct drm_crtc *crtc, } static void kmb_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = crtc->dev; struct kmb_drm_private *kmb = to_kmb(dev); @@ -166,7 +166,7 @@ static void kmb_crtc_atomic_begin(struct drm_crtc *crtc, } static void kmb_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = crtc->dev; struct kmb_drm_private *kmb = to_kmb(dev); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 1f0c10d317fe..52ec4c236982 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -52,7 +52,7 @@ struct kmb_drm_private { struct kmb_clock kmb_clk; struct drm_crtc crtc; struct kmb_plane *plane; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; spinlock_t irq_lock; int irq_lcd; int sys_clk_mhz; diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index df84b5a79a6c..59d0e856392f 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -1333,7 +1333,7 @@ static u32 mipi_tx_init_dphy(struct kmb_dsi *kmb_dsi, } static void connect_lcd_to_mipi(struct kmb_dsi *kmb_dsi, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct regmap *msscam; @@ -1353,7 +1353,7 @@ static void connect_lcd_to_mipi(struct kmb_dsi *kmb_dsi, } int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode, - int sys_clk_mhz, struct drm_atomic_state *old_state) + int sys_clk_mhz, struct drm_atomic_commit *old_state) { u64 data_rate; diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 09dc88743d77..0faadeb9f1dd 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -380,7 +380,7 @@ int kmb_dsi_host_bridge_init(struct device *dev); struct kmb_dsi *kmb_dsi_init(struct platform_device *pdev); void kmb_dsi_host_unregister(struct kmb_dsi *kmb_dsi); int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode, - int sys_clk_mhz, struct drm_atomic_state *old_state); + int sys_clk_mhz, struct drm_atomic_commit *old_state); int kmb_dsi_map_mmio(struct kmb_dsi *kmb_dsi); int kmb_dsi_clk_init(struct kmb_dsi *kmb_dsi); int kmb_dsi_encoder_init(struct drm_device *dev, struct kmb_dsi *kmb_dsi); diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index a935ff1503cd..a0001edb1e21 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -90,7 +90,7 @@ static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) } static int kmb_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -139,7 +139,7 @@ static int kmb_plane_atomic_check(struct drm_plane *plane, } static void kmb_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct kmb_plane *kmb_plane = to_kmb_plane(plane); int plane_id = kmb_plane->id; @@ -339,7 +339,7 @@ static void kmb_plane_set_alpha(struct kmb_drm_private *kmb, } static void kmb_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); diff --git a/drivers/gpu/drm/logicvc/logicvc_crtc.c b/drivers/gpu/drm/logicvc/logicvc_crtc.c index 43a675d03808..81e5b80736fa 100644 --- a/drivers/gpu/drm/logicvc/logicvc_crtc.c +++ b/drivers/gpu/drm/logicvc/logicvc_crtc.c @@ -36,7 +36,7 @@ logicvc_crtc_mode_valid(struct drm_crtc *drm_crtc, } static void logicvc_crtc_atomic_begin(struct drm_crtc *drm_crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct logicvc_crtc *crtc = logicvc_crtc(drm_crtc); struct drm_crtc_state *old_state = @@ -60,7 +60,7 @@ static void logicvc_crtc_atomic_begin(struct drm_crtc *drm_crtc, } static void logicvc_crtc_atomic_enable(struct drm_crtc *drm_crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct logicvc_crtc *crtc = logicvc_crtc(drm_crtc); struct logicvc_drm *logicvc = logicvc_drm(drm_crtc->dev); @@ -150,7 +150,7 @@ static void logicvc_crtc_atomic_enable(struct drm_crtc *drm_crtc, } static void logicvc_crtc_atomic_disable(struct drm_crtc *drm_crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct logicvc_drm *logicvc = logicvc_drm(drm_crtc->dev); struct drm_device *drm_dev = drm_crtc->dev; diff --git a/drivers/gpu/drm/logicvc/logicvc_layer.c b/drivers/gpu/drm/logicvc/logicvc_layer.c index eab4d773f92b..7f5ba000188a 100644 --- a/drivers/gpu/drm/logicvc/logicvc_layer.c +++ b/drivers/gpu/drm/logicvc/logicvc_layer.c @@ -81,7 +81,7 @@ static bool logicvc_layer_format_inverted(uint32_t format) } static int logicvc_plane_atomic_check(struct drm_plane *drm_plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm_dev = drm_plane->dev; struct logicvc_layer *layer = logicvc_layer(drm_plane); @@ -135,7 +135,7 @@ static int logicvc_plane_atomic_check(struct drm_plane *drm_plane, } static void logicvc_plane_atomic_update(struct drm_plane *drm_plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct logicvc_layer *layer = logicvc_layer(drm_plane); struct logicvc_drm *logicvc = logicvc_drm(drm_plane->dev); @@ -232,7 +232,7 @@ static void logicvc_plane_atomic_update(struct drm_plane *drm_plane, } static void logicvc_plane_atomic_disable(struct drm_plane *drm_plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct logicvc_layer *layer = logicvc_layer(drm_plane); struct logicvc_drm *logicvc = logicvc_drm(drm_plane->dev); diff --git a/drivers/gpu/drm/loongson/lsdc_crtc.c b/drivers/gpu/drm/loongson/lsdc_crtc.c index 587fbe285e9e..16b8f36a4071 100644 --- a/drivers/gpu/drm/loongson/lsdc_crtc.c +++ b/drivers/gpu/drm/loongson/lsdc_crtc.c @@ -793,7 +793,7 @@ static int lsdc_pixpll_atomic_check(struct drm_crtc *crtc, } static int lsdc_crtc_helper_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -855,7 +855,7 @@ static void lsdc_crtc_send_vblank(struct drm_crtc *crtc) } static void lsdc_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lsdc_crtc *lcrtc = to_lsdc_crtc(crtc); @@ -866,7 +866,7 @@ static void lsdc_crtc_atomic_enable(struct drm_crtc *crtc, } static void lsdc_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lsdc_crtc *lcrtc = to_lsdc_crtc(crtc); @@ -883,7 +883,7 @@ static void lsdc_crtc_atomic_disable(struct drm_crtc *crtc, } static void lsdc_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { spin_lock_irq(&crtc->dev->event_lock); if (crtc->state->event) { diff --git a/drivers/gpu/drm/loongson/lsdc_output_7a1000.c b/drivers/gpu/drm/loongson/lsdc_output_7a1000.c index ccca67e01fd9..5c483baa3762 100644 --- a/drivers/gpu/drm/loongson/lsdc_output_7a1000.c +++ b/drivers/gpu/drm/loongson/lsdc_output_7a1000.c @@ -63,7 +63,7 @@ static int ls7a1000_dpi_connector_get_modes(struct drm_connector *conn) static struct drm_encoder * ls7a1000_dpi_connector_get_best_encoder(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lsdc_output *output = connector_to_lsdc_output(connector); diff --git a/drivers/gpu/drm/loongson/lsdc_output_7a2000.c b/drivers/gpu/drm/loongson/lsdc_output_7a2000.c index aa7daee4c065..a9798b3dadee 100644 --- a/drivers/gpu/drm/loongson/lsdc_output_7a2000.c +++ b/drivers/gpu/drm/loongson/lsdc_output_7a2000.c @@ -67,7 +67,7 @@ static int ls7a2000_connector_get_modes(struct drm_connector *connector) static struct drm_encoder * ls7a2000_connector_get_best_encoder(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lsdc_output *output = connector_to_lsdc_output(connector); @@ -332,7 +332,7 @@ static int ls7a2000_hdmi_set_avi_infoframe(struct drm_encoder *encoder, } static void ls7a2000_hdmi_atomic_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lsdc_output *output = encoder_to_lsdc_output(encoder); struct lsdc_display_pipe *dispipe = output_to_display_pipe(output); @@ -355,7 +355,7 @@ static void ls7a2000_hdmi_atomic_disable(struct drm_encoder *encoder, } static void ls7a2000_hdmi_atomic_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *ddev = encoder->dev; struct lsdc_device *ldev = to_lsdc(ddev); diff --git a/drivers/gpu/drm/loongson/lsdc_plane.c b/drivers/gpu/drm/loongson/lsdc_plane.c index 9675344128d0..bea42215796d 100644 --- a/drivers/gpu/drm/loongson/lsdc_plane.c +++ b/drivers/gpu/drm/loongson/lsdc_plane.c @@ -48,7 +48,7 @@ static u64 lsdc_fb_base_addr(struct drm_framebuffer *fb) } static int lsdc_primary_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); struct drm_crtc *crtc = new_plane_state->crtc; @@ -67,7 +67,7 @@ static int lsdc_primary_atomic_check(struct drm_plane *plane, } static void lsdc_primary_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lsdc_primary *primary = to_lsdc_primary(plane); const struct lsdc_primary_plane_ops *ops = primary->ops; @@ -87,7 +87,7 @@ static void lsdc_primary_atomic_update(struct drm_plane *plane, } static void lsdc_primary_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { /* * Do nothing, just prevent call into atomic_update(). @@ -172,7 +172,7 @@ static const struct drm_plane_helper_funcs lsdc_primary_helper_funcs = { }; static int lsdc_cursor_plane_atomic_async_check(struct drm_plane *plane, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, bool flip) { struct drm_plane_state *new_state; @@ -219,7 +219,7 @@ static int lsdc_cursor_plane_atomic_async_check(struct drm_plane *plane, } static void lsdc_cursor_plane_atomic_async_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lsdc_cursor *cursor = to_lsdc_cursor(plane); const struct lsdc_cursor_plane_ops *ops = cursor->ops; @@ -268,7 +268,7 @@ static void lsdc_cursor_plane_atomic_async_update(struct drm_plane *plane, /* ls7a1000 cursor plane helpers */ static int ls7a1000_cursor_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state; struct drm_crtc_state *new_crtc_state; @@ -298,7 +298,7 @@ static int ls7a1000_cursor_plane_atomic_check(struct drm_plane *plane, } static void ls7a1000_cursor_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lsdc_cursor *cursor = to_lsdc_cursor(plane); struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); @@ -320,7 +320,7 @@ static void ls7a1000_cursor_plane_atomic_update(struct drm_plane *plane, } static void ls7a1000_cursor_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lsdc_cursor *cursor = to_lsdc_cursor(plane); const struct lsdc_cursor_plane_ops *ops = cursor->ops; @@ -341,7 +341,7 @@ static const struct drm_plane_helper_funcs ls7a1000_cursor_plane_helper_funcs = /* ls7a2000 cursor plane helpers */ static int ls7a2000_cursor_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state; struct drm_crtc_state *new_crtc_state; @@ -379,7 +379,7 @@ static int ls7a2000_cursor_plane_atomic_check(struct drm_plane *plane, /* Update the format, size and location of the cursor */ static void ls7a2000_cursor_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lsdc_cursor *cursor = to_lsdc_cursor(plane); struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); @@ -416,7 +416,7 @@ static void ls7a2000_cursor_plane_atomic_update(struct drm_plane *plane, } static void ls7a2000_cursor_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lsdc_cursor *cursor = to_lsdc_cursor(plane); const struct lsdc_cursor_plane_ops *hw_ops = cursor->ops; diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c index fcb16f3f7b23..caa02a708d0a 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -681,7 +681,7 @@ static void mtk_crtc_disable_vblank(struct drm_crtc *crtc) } static void mtk_crtc_update_output(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { int crtc_index = drm_crtc_index(crtc); int i; @@ -763,7 +763,7 @@ void mtk_crtc_plane_disable(struct drm_crtc *crtc, struct drm_plane *plane) } void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc); @@ -774,7 +774,7 @@ void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, } static void mtk_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc); struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; @@ -802,7 +802,7 @@ static void mtk_crtc_atomic_enable(struct drm_crtc *crtc, } static void mtk_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc); struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; @@ -843,7 +843,7 @@ static void mtk_crtc_atomic_disable(struct drm_crtc *crtc, } static void mtk_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -868,7 +868,7 @@ static void mtk_crtc_atomic_begin(struct drm_crtc *crtc, } static void mtk_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc); int i; diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.h b/drivers/gpu/drm/mediatek/mtk_crtc.h index 828f109b83e7..a6b8697cca97 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_crtc.h @@ -23,7 +23,7 @@ int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, struct mtk_plane_state *state); void mtk_crtc_plane_disable(struct drm_crtc *crtc, struct drm_plane *plane); void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, - struct drm_atomic_state *plane_state); + struct drm_atomic_commit *plane_state); struct device *mtk_crtc_dma_dev_get(struct drm_crtc *crtc); #endif /* MTK_CRTC_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c index c52cc7c2e200..eefbc7e0f9c8 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -2374,7 +2374,7 @@ static void mtk_dp_bridge_detach(struct drm_bridge *bridge) } static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge); int ret; @@ -2428,7 +2428,7 @@ static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge, } static void mtk_dp_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 1fc3df4b5485..d48da019a4a3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -63,7 +63,7 @@ struct mtk_drm_private { struct device_node *comp_node[DDP_COMPONENT_DRM_ID_MAX]; struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_DRM_ID_MAX]; struct mtk_mmsys_driver_data *data; - struct drm_atomic_state *suspend_state; + struct drm_atomic_commit *suspend_state; unsigned int mbox_index; struct mtk_drm_private **all_drm_private; }; diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 8be32cde2924..46cf4b043f12 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -827,7 +827,7 @@ static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge, } static void mtk_dsi_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_dsi *dsi = bridge_to_dsi(bridge); @@ -835,7 +835,7 @@ static void mtk_dsi_bridge_atomic_disable(struct drm_bridge *bridge, } static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_dsi *dsi = bridge_to_dsi(bridge); @@ -846,7 +846,7 @@ static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge, } static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_dsi *dsi = bridge_to_dsi(bridge); int ret; @@ -857,7 +857,7 @@ static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge, } static void mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_dsi *dsi = bridge_to_dsi(bridge); diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 1ea259854780..17b10de5ff60 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -999,7 +999,7 @@ static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge, } static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); @@ -1016,7 +1016,7 @@ static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, } static void mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); @@ -1030,7 +1030,7 @@ static void mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge, } static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); @@ -1051,7 +1051,7 @@ static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, } static void mtk_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c index b5c738380dc2..81787cc95d2a 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c @@ -1010,7 +1010,7 @@ static void mtk_hdmi_v2_handle_plugged_change(struct mtk_hdmi *hdmi, bool plugge } static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); struct drm_connector_state *conn_state; @@ -1048,7 +1048,7 @@ static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge, } static void mtk_hdmi_v2_bridge_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); int ret; @@ -1069,7 +1069,7 @@ static void mtk_hdmi_v2_bridge_enable(struct drm_bridge *bridge, } static void mtk_hdmi_v2_bridge_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); @@ -1086,7 +1086,7 @@ static void mtk_hdmi_v2_bridge_disable(struct drm_bridge *bridge, } static void mtk_hdmi_v2_bridge_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediatek/mtk_plane.c index 86c6f60eadb3..2598c8edb443 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -80,7 +80,7 @@ static void mtk_plane_destroy_state(struct drm_plane *plane, } static int mtk_plane_atomic_async_check(struct drm_plane *plane, - struct drm_atomic_state *state, bool flip) + struct drm_atomic_commit *state, bool flip) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -193,7 +193,7 @@ static void mtk_plane_update_new_state(struct drm_plane_state *new_state, } static void mtk_plane_atomic_async_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -228,7 +228,7 @@ static const struct drm_plane_funcs mtk_plane_funcs = { }; static int mtk_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -260,7 +260,7 @@ static int mtk_plane_atomic_check(struct drm_plane *plane, } static void mtk_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -277,7 +277,7 @@ static void mtk_plane_atomic_disable(struct drm_plane *plane, } static void mtk_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c index d70616da8ce2..b77d2d24ead1 100644 --- a/drivers/gpu/drm/meson/meson_crtc.c +++ b/drivers/gpu/drm/meson/meson_crtc.c @@ -82,7 +82,7 @@ static const struct drm_crtc_funcs meson_crtc_funcs = { }; static void meson_g12a_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_crtc *meson_crtc = to_meson_crtc(crtc); struct drm_crtc_state *crtc_state = crtc->state; @@ -118,7 +118,7 @@ static void meson_g12a_crtc_atomic_enable(struct drm_crtc *crtc, } static void meson_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_crtc *meson_crtc = to_meson_crtc(crtc); struct drm_crtc_state *crtc_state = crtc->state; @@ -146,7 +146,7 @@ static void meson_crtc_atomic_enable(struct drm_crtc *crtc, } static void meson_g12a_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_crtc *meson_crtc = to_meson_crtc(crtc); struct meson_drm *priv = meson_crtc->priv; @@ -171,7 +171,7 @@ static void meson_g12a_crtc_atomic_disable(struct drm_crtc *crtc, } static void meson_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_crtc *meson_crtc = to_meson_crtc(crtc); struct meson_drm *priv = meson_crtc->priv; @@ -201,7 +201,7 @@ static void meson_crtc_atomic_disable(struct drm_crtc *crtc, } static void meson_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_crtc *meson_crtc = to_meson_crtc(crtc); unsigned long flags; @@ -217,7 +217,7 @@ static void meson_crtc_atomic_begin(struct drm_crtc *crtc, } static void meson_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_crtc *meson_crtc = to_meson_crtc(crtc); struct meson_drm *priv = meson_crtc->priv; diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c b/drivers/gpu/drm/meson/meson_encoder_cvbs.c index 41ba6d2139ee..8b26a0031cde 100644 --- a/drivers/gpu/drm/meson/meson_encoder_cvbs.c +++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.c @@ -139,7 +139,7 @@ static int meson_encoder_cvbs_atomic_check(struct drm_bridge *bridge, } static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_encoder_cvbs *encoder_cvbs = bridge_to_meson_encoder_cvbs(bridge); struct meson_drm *priv = encoder_cvbs->priv; @@ -190,7 +190,7 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge, } static void meson_encoder_cvbs_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_encoder_cvbs *meson_encoder_cvbs = bridge_to_meson_encoder_cvbs(bridge); diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.c b/drivers/gpu/drm/meson/meson_encoder_dsi.c index eba246791c68..c1f4685073bb 100644 --- a/drivers/gpu/drm/meson/meson_encoder_dsi.c +++ b/drivers/gpu/drm/meson/meson_encoder_dsi.c @@ -42,7 +42,7 @@ static int meson_encoder_dsi_attach(struct drm_bridge *bridge, } static void meson_encoder_dsi_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_encoder_dsi *encoder_dsi = bridge_to_meson_encoder_dsi(bridge); struct meson_drm *priv = encoder_dsi->priv; @@ -79,7 +79,7 @@ static void meson_encoder_dsi_atomic_enable(struct drm_bridge *bridge, } static void meson_encoder_dsi_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_encoder_dsi *meson_encoder_dsi = bridge_to_meson_encoder_dsi(bridge); diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c index 8e00ae6edbb1..55c0601df3c6 100644 --- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c +++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c @@ -189,7 +189,7 @@ static enum drm_mode_status meson_encoder_hdmi_mode_valid(struct drm_bridge *bri } static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_encoder_hdmi *encoder_hdmi = bridge_to_meson_encoder_hdmi(bridge); unsigned int ycrcb_map = VPU_HDMI_OUTPUT_CBYCR; @@ -252,7 +252,7 @@ static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge, } static void meson_encoder_hdmi_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_encoder_hdmi *encoder_hdmi = bridge_to_meson_encoder_hdmi(bridge); struct meson_drm *priv = encoder_hdmi->priv; diff --git a/drivers/gpu/drm/meson/meson_overlay.c b/drivers/gpu/drm/meson/meson_overlay.c index 783572b16963..7047807f1a3e 100644 --- a/drivers/gpu/drm/meson/meson_overlay.c +++ b/drivers/gpu/drm/meson/meson_overlay.c @@ -167,7 +167,7 @@ struct meson_overlay { #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) static int meson_overlay_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -470,7 +470,7 @@ static void meson_overlay_setup_scaler_params(struct meson_drm *priv, } static void meson_overlay_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_overlay *meson_overlay = to_meson_overlay(plane); struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, @@ -724,7 +724,7 @@ static void meson_overlay_atomic_update(struct drm_plane *plane, } static void meson_overlay_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_overlay *meson_overlay = to_meson_overlay(plane); struct meson_drm *priv = meson_overlay->priv; diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c index f8d0e0874a5d..2d88fe87a11a 100644 --- a/drivers/gpu/drm/meson/meson_plane.c +++ b/drivers/gpu/drm/meson/meson_plane.c @@ -73,7 +73,7 @@ struct meson_plane { #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) static int meson_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -132,7 +132,7 @@ static u32 meson_g12a_afbcd_line_stride(struct meson_drm *priv) } static void meson_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_plane *meson_plane = to_meson_plane(plane); struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, @@ -398,7 +398,7 @@ static void meson_plane_atomic_update(struct drm_plane *plane, } static void meson_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct meson_plane *meson_plane = to_meson_plane(plane); struct meson_drm *priv = meson_plane->priv; diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.h b/drivers/gpu/drm/mgag200/mgag200_drv.h index a875c4bf8cbe..3732c62351bb 100644 --- a/drivers/gpu/drm/mgag200/mgag200_drv.h +++ b/drivers/gpu/drm/mgag200/mgag200_drv.h @@ -253,14 +253,14 @@ struct mgag200_device_funcs { * success, the calculated parameters should be stored in the CRTC's * state in struct @mgag200_crtc_state.pixpllc. */ - int (*pixpllc_atomic_check)(struct drm_crtc *crtc, struct drm_atomic_state *new_state); + int (*pixpllc_atomic_check)(struct drm_crtc *crtc, struct drm_atomic_commit *new_state); /* * Program PIXPLLC from the CRTC state. The parameters should have been * stored in struct @mgag200_crtc_state.pixpllc by the corresponding * implementation of @pixpllc_atomic_check. */ - void (*pixpllc_atomic_update)(struct drm_crtc *crtc, struct drm_atomic_state *old_state); + void (*pixpllc_atomic_update)(struct drm_crtc *crtc, struct drm_atomic_commit *old_state); }; struct mga_device { @@ -332,11 +332,11 @@ struct mga_device *mgag200_g200_device_create(struct pci_dev *pdev, const struct struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const struct drm_driver *drv, enum mga_type type); void mgag200_g200wb_init_registers(struct mga_device *mdev); -void mgag200_g200wb_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_state *old_state); +void mgag200_g200wb_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_commit *old_state); struct mga_device *mgag200_g200wb_device_create(struct pci_dev *pdev, const struct drm_driver *drv); struct mga_device *mgag200_g200ev_device_create(struct pci_dev *pdev, const struct drm_driver *drv); void mgag200_g200eh_init_registers(struct mga_device *mdev); -void mgag200_g200eh_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_state *old_state); +void mgag200_g200eh_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_commit *old_state); struct mga_device *mgag200_g200eh_device_create(struct pci_dev *pdev, const struct drm_driver *drv); struct mga_device *mgag200_g200eh3_device_create(struct pci_dev *pdev, @@ -356,7 +356,7 @@ struct drm_crtc; struct drm_crtc_state; struct drm_display_mode; struct drm_plane; -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_scanout_buffer; extern const uint32_t mgag200_primary_plane_formats[]; @@ -364,13 +364,13 @@ extern const size_t mgag200_primary_plane_formats_size; extern const uint64_t mgag200_primary_plane_fmtmods[]; int mgag200_primary_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *new_state); + struct drm_atomic_commit *new_state); void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *old_state); + struct drm_atomic_commit *old_state); void mgag200_primary_plane_helper_atomic_enable(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *old_state); + struct drm_atomic_commit *old_state); int mgag200_primary_plane_helper_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer *sb); @@ -395,10 +395,10 @@ void mgag200_crtc_load_gamma(struct mga_device *mdev, enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode); -int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state); -void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *old_state); -void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *old_state); -void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *old_state); +int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *new_state); +void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_commit *old_state); +void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_commit *old_state); +void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_commit *old_state); #define MGAG200_CRTC_HELPER_FUNCS \ .mode_valid = mgag200_crtc_helper_mode_valid, \ diff --git a/drivers/gpu/drm/mgag200/mgag200_g200.c b/drivers/gpu/drm/mgag200/mgag200_g200.c index a5e291b344db..9e6b4618fadd 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200.c @@ -62,7 +62,7 @@ static void mgag200_g200_init_registers(struct mgag200_g200_device *g200) * PIXPLLC */ -static int mgag200_g200_pixpllc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state) +static int mgag200_g200_pixpllc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *new_state) { static const int post_div_max = 7; static const int in_div_min = 1; @@ -138,7 +138,7 @@ static int mgag200_g200_pixpllc_atomic_check(struct drm_crtc *crtc, struct drm_a } static void mgag200_g200_pixpllc_atomic_update(struct drm_crtc *crtc, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct drm_device *dev = crtc->dev; struct mga_device *mdev = to_mga_device(dev); diff --git a/drivers/gpu/drm/mgag200/mgag200_g200eh.c b/drivers/gpu/drm/mgag200/mgag200_g200eh.c index d2aa931f579d..e64bfeafbefc 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200eh.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200eh.c @@ -41,7 +41,7 @@ void mgag200_g200eh_init_registers(struct mga_device *mdev) */ static int mgag200_g200eh_pixpllc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *new_state) + struct drm_atomic_commit *new_state) { static const unsigned int vcomax = 800000; static const unsigned int vcomin = 400000; @@ -91,7 +91,7 @@ static int mgag200_g200eh_pixpllc_atomic_check(struct drm_crtc *crtc, } void mgag200_g200eh_pixpllc_atomic_update(struct drm_crtc *crtc, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct drm_device *dev = crtc->dev; struct mga_device *mdev = to_mga_device(dev); diff --git a/drivers/gpu/drm/mgag200/mgag200_g200eh3.c b/drivers/gpu/drm/mgag200/mgag200_g200eh3.c index 7bea7a728f56..183b7676ea6a 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200eh3.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200eh3.c @@ -16,7 +16,7 @@ */ static int mgag200_g200eh3_pixpllc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *new_state) + struct drm_atomic_commit *new_state) { static const unsigned int vcomax = 3000000; static const unsigned int vcomin = 1500000; diff --git a/drivers/gpu/drm/mgag200/mgag200_g200eh5.c b/drivers/gpu/drm/mgag200/mgag200_g200eh5.c index 36da6529d74f..dc375c055b0e 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200eh5.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200eh5.c @@ -18,7 +18,7 @@ */ static int mgag200_g200eh5_pixpllc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *new_state) + struct drm_atomic_commit *new_state) { const unsigned long long VCO_MAX = 10 * GIGA; // Hz const unsigned long long VCO_MIN = 2500 * MEGA; // Hz diff --git a/drivers/gpu/drm/mgag200/mgag200_g200er.c b/drivers/gpu/drm/mgag200/mgag200_g200er.c index 8fa8fe943abf..205678a57bfe 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200er.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200er.c @@ -58,7 +58,7 @@ static void mgag200_g200er_reset_tagfifo(struct mga_device *mdev) */ static int mgag200_g200er_pixpllc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *new_state) + struct drm_atomic_commit *new_state) { static const unsigned int vcomax = 1488000; static const unsigned int vcomin = 1056000; @@ -119,7 +119,7 @@ static int mgag200_g200er_pixpllc_atomic_check(struct drm_crtc *crtc, } static void mgag200_g200er_pixpllc_atomic_update(struct drm_crtc *crtc, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct drm_device *dev = crtc->dev; struct mga_device *mdev = to_mga_device(dev); @@ -182,7 +182,7 @@ static const struct drm_plane_funcs mgag200_g200er_primary_plane_funcs = { }; static void mgag200_g200er_crtc_helper_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct drm_device *dev = crtc->dev; struct mga_device *mdev = to_mga_device(dev); diff --git a/drivers/gpu/drm/mgag200/mgag200_g200ev.c b/drivers/gpu/drm/mgag200/mgag200_g200ev.c index 3fadbeb10af9..d60693ac0749 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200ev.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200ev.c @@ -47,7 +47,7 @@ static void mgag200_g200ev_set_hiprilvl(struct mga_device *mdev) */ static int mgag200_g200ev_pixpllc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *new_state) + struct drm_atomic_commit *new_state) { static const unsigned int vcomax = 550000; static const unsigned int vcomin = 150000; @@ -98,7 +98,7 @@ static int mgag200_g200ev_pixpllc_atomic_check(struct drm_crtc *crtc, } static void mgag200_g200ev_pixpllc_atomic_update(struct drm_crtc *crtc, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct drm_device *dev = crtc->dev; struct mga_device *mdev = to_mga_device(dev); @@ -183,7 +183,7 @@ static const struct drm_plane_funcs mgag200_g200ev_primary_plane_funcs = { }; static void mgag200_g200ev_crtc_helper_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct drm_device *dev = crtc->dev; struct mga_device *mdev = to_mga_device(dev); diff --git a/drivers/gpu/drm/mgag200/mgag200_g200ew3.c b/drivers/gpu/drm/mgag200/mgag200_g200ew3.c index e387a455eae5..9c14d0eb66bc 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200ew3.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200ew3.c @@ -23,7 +23,7 @@ static void mgag200_g200ew3_init_registers(struct mga_device *mdev) */ static int mgag200_g200ew3_pixpllc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *new_state) + struct drm_atomic_commit *new_state) { static const unsigned int vcomax = 800000; static const unsigned int vcomin = 400000; diff --git a/drivers/gpu/drm/mgag200/mgag200_g200se.c b/drivers/gpu/drm/mgag200/mgag200_g200se.c index 5c2185d6b707..349ec36f6d49 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200se.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200se.c @@ -120,7 +120,7 @@ static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev, */ static int mgag200_g200se_00_pixpllc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *new_state) + struct drm_atomic_commit *new_state) { static const unsigned int vcomax = 320000; static const unsigned int vcomin = 160000; @@ -176,7 +176,7 @@ static int mgag200_g200se_00_pixpllc_atomic_check(struct drm_crtc *crtc, } static void mgag200_g200se_00_pixpllc_atomic_update(struct drm_crtc *crtc, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct drm_device *dev = crtc->dev; struct mga_device *mdev = to_mga_device(dev); @@ -203,7 +203,7 @@ static void mgag200_g200se_00_pixpllc_atomic_update(struct drm_crtc *crtc, } static int mgag200_g200se_04_pixpllc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *new_state) + struct drm_atomic_commit *new_state) { static const unsigned int vcomax = 1600000; static const unsigned int vcomin = 800000; @@ -277,7 +277,7 @@ static int mgag200_g200se_04_pixpllc_atomic_check(struct drm_crtc *crtc, } static void mgag200_g200se_04_pixpllc_atomic_update(struct drm_crtc *crtc, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct drm_device *dev = crtc->dev; struct mga_device *mdev = to_mga_device(dev); @@ -321,7 +321,7 @@ static const struct drm_plane_funcs mgag200_g200se_primary_plane_funcs = { }; static void mgag200_g200se_crtc_helper_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct drm_device *dev = crtc->dev; struct mga_device *mdev = to_mga_device(dev); diff --git a/drivers/gpu/drm/mgag200/mgag200_g200wb.c b/drivers/gpu/drm/mgag200/mgag200_g200wb.c index d847fa8ded8c..f65d4238422f 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200wb.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200wb.c @@ -39,7 +39,7 @@ void mgag200_g200wb_init_registers(struct mga_device *mdev) */ static int mgag200_g200wb_pixpllc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *new_state) + struct drm_atomic_commit *new_state) { static const unsigned int vcomax = 550000; static const unsigned int vcomin = 150000; @@ -90,7 +90,7 @@ static int mgag200_g200wb_pixpllc_atomic_check(struct drm_crtc *crtc, } void mgag200_g200wb_pixpllc_atomic_update(struct drm_crtc *crtc, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct drm_device *dev = crtc->dev; struct mga_device *mdev = to_mga_device(dev); diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c index bd346b828773..7e07fc3f1a60 100644 --- a/drivers/gpu/drm/mgag200/mgag200_mode.c +++ b/drivers/gpu/drm/mgag200/mgag200_mode.c @@ -463,7 +463,7 @@ const uint64_t mgag200_primary_plane_fmtmods[] = { }; int mgag200_primary_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *new_state) + struct drm_atomic_commit *new_state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(new_state, plane); struct drm_framebuffer *new_fb = new_plane_state->fb; @@ -498,7 +498,7 @@ int mgag200_primary_plane_helper_atomic_check(struct drm_plane *plane, } void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct drm_device *dev = plane->dev; struct mga_device *mdev = to_mga_device(dev); @@ -521,7 +521,7 @@ void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane, } void mgag200_primary_plane_helper_atomic_enable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = plane->dev; struct mga_device *mdev = to_mga_device(dev); @@ -534,7 +534,7 @@ void mgag200_primary_plane_helper_atomic_enable(struct drm_plane *plane, } void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct drm_device *dev = plane->dev; struct mga_device *mdev = to_mga_device(dev); @@ -597,7 +597,7 @@ enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc, return MODE_OK; } -int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state) +int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *new_state) { struct drm_device *dev = crtc->dev; struct mga_device *mdev = to_mga_device(dev); @@ -631,7 +631,7 @@ int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_st return 0; } -void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *old_state) +void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_commit *old_state) { struct drm_crtc_state *crtc_state = crtc->state; struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); @@ -648,7 +648,7 @@ void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_s } } -void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *old_state) +void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_commit *old_state) { struct drm_device *dev = crtc->dev; struct mga_device *mdev = to_mga_device(dev); @@ -672,7 +672,7 @@ void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_ mgag200_enable_display(mdev); } -void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *old_state) +void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_commit *old_state) { struct mga_device *mdev = to_mga_device(crtc->dev); @@ -727,7 +727,7 @@ void mgag200_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_st * Mode config */ -static void mgag200_mode_config_helper_atomic_commit_tail(struct drm_atomic_state *state) +static void mgag200_mode_config_helper_atomic_commit_tail(struct drm_atomic_commit *state) { struct mga_device *mdev = to_mga_device(state->dev); diff --git a/drivers/gpu/drm/mgag200/mgag200_vga_bmc.c b/drivers/gpu/drm/mgag200/mgag200_vga_bmc.c index a855f1734316..805636990b55 100644 --- a/drivers/gpu/drm/mgag200/mgag200_vga_bmc.c +++ b/drivers/gpu/drm/mgag200/mgag200_vga_bmc.c @@ -10,7 +10,7 @@ #include "mgag200_drv.h" static void mgag200_vga_bmc_encoder_atomic_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mga_device *mdev = to_mga_device(encoder->dev); @@ -19,7 +19,7 @@ static void mgag200_vga_bmc_encoder_atomic_disable(struct drm_encoder *encoder, } static void mgag200_vga_bmc_encoder_atomic_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mga_device *mdev = to_mga_device(encoder->dev); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 411a6fa832b5..42d0a529b4d5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -899,7 +899,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc) } static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); struct drm_encoder *encoder; @@ -940,7 +940,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, } static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dpu_crtc *dpu_crtc; struct drm_device *dev; @@ -1188,7 +1188,7 @@ static void dpu_crtc_atomic_print_state(struct drm_printer *p, } static void dpu_crtc_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -1267,7 +1267,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc, } static void dpu_crtc_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); struct drm_encoder *encoder; @@ -1324,7 +1324,7 @@ static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate) static int dpu_crtc_assign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) { int total_planes = crtc->dev->mode_config.num_total_plane; - struct drm_atomic_state *state = crtc_state->state; + struct drm_atomic_commit *state = crtc_state->state; struct dpu_global_state *global_state; struct drm_plane_state **states; struct drm_plane *plane; @@ -1520,7 +1520,7 @@ int dpu_crtc_check_mode_changed(struct drm_crtc_state *old_crtc_state, } static int dpu_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index eba1d52211f6..778e231d4967 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -655,7 +655,7 @@ struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) void dpu_encoder_update_topology(struct drm_encoder *drm_enc, struct msm_display_topology *topology, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, const struct drm_display_mode *adj_mode) { struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); @@ -716,7 +716,7 @@ void dpu_encoder_update_topology(struct drm_encoder *drm_enc, } } -bool dpu_encoder_needs_modeset(struct drm_encoder *drm_enc, struct drm_atomic_state *state) +bool dpu_encoder_needs_modeset(struct drm_encoder *drm_enc, struct drm_atomic_commit *state) { struct drm_connector *connector; struct drm_connector_state *conn_state; @@ -1335,7 +1335,7 @@ void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) } static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dpu_encoder_virt *dpu_enc = NULL; int ret = 0; @@ -1382,7 +1382,7 @@ static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, } static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dpu_encoder_virt *dpu_enc = NULL; struct drm_crtc *crtc; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index ca1ca2e51d7e..4942097e7613 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -84,10 +84,10 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc); void dpu_encoder_update_topology(struct drm_encoder *drm_enc, struct msm_display_topology *topology, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, const struct drm_display_mode *adj_mode); -bool dpu_encoder_needs_modeset(struct drm_encoder *drm_enc, struct drm_atomic_state *state); +bool dpu_encoder_needs_modeset(struct drm_encoder *drm_enc, struct drm_atomic_commit *state); void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc, struct drm_writeback_job *job); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 35f7af4743d7..657d956a6ca4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -331,7 +331,7 @@ dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms) * This acquires the modeset lock set aside for global state, creates * a new duplicated private object state. */ -struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s) +struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_commit *s) { struct msm_drm_private *priv = s->dev->dev_private; struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); @@ -449,7 +449,7 @@ static void dpu_kms_disable_commit(struct msm_kms *kms) pm_runtime_put_sync(&dpu_kms->pdev->dev); } -static int dpu_kms_check_mode_changed(struct msm_kms *kms, struct drm_atomic_state *state) +static int dpu_kms_check_mode_changed(struct msm_kms *kms, struct drm_atomic_commit *state) { struct drm_crtc_state *new_crtc_state; struct drm_crtc_state *old_crtc_state; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index bb3393bd102e..e39831a397b1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -138,7 +138,7 @@ struct dpu_global_state { struct dpu_global_state *dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms); struct dpu_global_state - *__must_check dpu_kms_get_global_state(struct drm_atomic_state *s); + *__must_check dpu_kms_get_global_state(struct drm_atomic_commit *s); /** * Debugfs functions - extra helper functions for debugfs support diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 3c315d5805b8..5642f3bc3568 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1049,7 +1049,7 @@ static bool dpu_plane_get_single_pipe_in_stage(struct dpu_plane_state *pstate, } static int dpu_plane_atomic_check_sspp(struct drm_plane *plane, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, const struct drm_crtc_state *crtc_state) { struct drm_plane_state *new_plane_state = @@ -1170,7 +1170,7 @@ static int dpu_plane_try_multirect_shared(struct dpu_plane_state *pstate, } static int dpu_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = drm_atomic_get_plane_state(state, plane); @@ -1250,7 +1250,7 @@ static int dpu_plane_assign_resource_in_stage(struct dpu_sw_pipe *pipe, static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, struct dpu_global_state *global_state, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_plane_state *plane_state, const struct drm_crtc_state *crtc_state, struct drm_plane_state **prev_adjacent_plane_state) @@ -1311,7 +1311,7 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, static int dpu_plane_assign_resources(struct drm_crtc *crtc, struct dpu_global_state *global_state, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_plane_state *plane_state, const struct drm_crtc_state *crtc_state) { @@ -1349,7 +1349,7 @@ static int dpu_plane_assign_resources(struct drm_crtc *crtc, } int dpu_assign_plane_resources(struct dpu_global_state *global_state, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_crtc *crtc, struct drm_plane_state **states, unsigned int num_planes) @@ -1617,7 +1617,7 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane) } static void dpu_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index 1ef5a041b8ac..d2e7c8c25115 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -70,7 +70,7 @@ static inline void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool en #endif int dpu_assign_plane_resources(struct dpu_global_state *global_state, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_crtc *crtc, struct drm_plane_state **states, unsigned int num_planes); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c index 7545c0293efb..54bd7c354b63 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c @@ -26,7 +26,7 @@ static int dpu_wb_conn_get_modes(struct drm_connector *connector) } static int dpu_wb_conn_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); struct dpu_wb_connector *dpu_wb_conn = to_dpu_wb_conn(wb_conn); diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c index e8066f9fd534..57dfce58450b 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c @@ -255,7 +255,7 @@ static void mdp4_crtc_mode_set_nofb(struct drm_crtc *crtc) } static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); struct mdp4_kms *mdp4_kms = get_kms(crtc); @@ -284,7 +284,7 @@ static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc, } static void mdp4_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); struct mdp4_kms *mdp4_kms = get_kms(crtc); @@ -307,7 +307,7 @@ static void mdp4_crtc_atomic_enable(struct drm_crtc *crtc, } static int mdp4_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); DBG("%s: check", mdp4_crtc->name); @@ -316,14 +316,14 @@ static int mdp4_crtc_atomic_check(struct drm_crtc *crtc, } static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); DBG("%s: begin", mdp4_crtc->name); } static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); struct drm_device *dev = crtc->dev; diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c index 098c3b5ff2b2..9459f70ce0ba 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c @@ -102,13 +102,13 @@ static void mdp4_plane_cleanup_fb(struct drm_plane *plane, static int mdp4_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { return 0; } static void mdp4_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c index b29541bc4843..4c4a897fc1ee 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c @@ -485,7 +485,7 @@ static u32 mdp5_crtc_get_vblank_counter(struct drm_crtc *crtc) } static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); @@ -531,7 +531,7 @@ static void mdp5_crtc_vblank_on(struct drm_crtc *crtc) } static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); @@ -690,7 +690,7 @@ static enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc, } static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -787,13 +787,13 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, } static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { DBG("%s: begin", crtc->name); } static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c index 2d26b07b06f5..0a004ab9fc85 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -79,7 +79,7 @@ mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms) * This acquires the modeset lock set aside for global state, creates * a new duplicated private object state. */ -struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s) +struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_commit *s) { struct msm_drm_private *priv = s->dev->dev_private; struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); @@ -160,7 +160,7 @@ static void mdp5_disable_commit(struct msm_kms *kms) pm_runtime_put_sync(&mdp5_kms->pdev->dev); } -static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) +static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_commit *state) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); struct mdp5_global_state *global_state; diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h index 36b6842dfc9c..7bf2172fce0b 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h @@ -77,7 +77,7 @@ struct mdp5_kms { struct mdp5_global_state { struct drm_private_state base; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct mdp5_kms *mdp5_kms; struct mdp5_hw_pipe_state hwpipe; @@ -86,7 +86,7 @@ struct mdp5_global_state { }; struct mdp5_global_state * mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms); -struct mdp5_global_state *__must_check mdp5_get_global_state(struct drm_atomic_state *s); +struct mdp5_global_state *__must_check mdp5_get_global_state(struct drm_atomic_commit *s); /* Atomic plane state. Subclasses the base drm_plane_state in order to * track assigned hwpipe and hw specific state. diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c index 2822b533f807..253b29629ed7 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c @@ -35,7 +35,7 @@ static int get_right_pair_idx(struct mdp5_kms *mdp5_kms, int lm) return -1; } -int mdp5_mixer_assign(struct drm_atomic_state *s, struct drm_crtc *crtc, +int mdp5_mixer_assign(struct drm_atomic_commit *s, struct drm_crtc *crtc, uint32_t caps, struct mdp5_hw_mixer **mixer, struct mdp5_hw_mixer **r_mixer) { @@ -116,7 +116,7 @@ int mdp5_mixer_assign(struct drm_atomic_state *s, struct drm_crtc *crtc, return 0; } -int mdp5_mixer_release(struct drm_atomic_state *s, struct mdp5_hw_mixer *mixer) +int mdp5_mixer_release(struct drm_atomic_commit *s, struct mdp5_hw_mixer *mixer) { struct mdp5_global_state *global_state = mdp5_get_global_state(s); struct mdp5_hw_mixer_state *new_state; diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h index 2bedd75835bc..46bca461b2d0 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h @@ -27,10 +27,10 @@ struct mdp5_hw_mixer_state { struct mdp5_hw_mixer *mdp5_mixer_init(struct drm_device *dev, const struct mdp5_lm_instance *lm); -int mdp5_mixer_assign(struct drm_atomic_state *s, struct drm_crtc *crtc, +int mdp5_mixer_assign(struct drm_atomic_commit *s, struct drm_crtc *crtc, uint32_t caps, struct mdp5_hw_mixer **mixer, struct mdp5_hw_mixer **r_mixer); -int mdp5_mixer_release(struct drm_atomic_state *s, +int mdp5_mixer_release(struct drm_atomic_commit *s, struct mdp5_hw_mixer *mixer); #endif /* __MDP5_LM_H__ */ diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c index 99b2c30b1d48..606e18973ea4 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c @@ -6,7 +6,7 @@ #include "mdp5_kms.h" -int mdp5_pipe_assign(struct drm_atomic_state *s, struct drm_plane *plane, +int mdp5_pipe_assign(struct drm_atomic_commit *s, struct drm_plane *plane, uint32_t caps, uint32_t blkcfg, struct mdp5_hw_pipe **hwpipe, struct mdp5_hw_pipe **r_hwpipe) @@ -119,7 +119,7 @@ int mdp5_pipe_assign(struct drm_atomic_state *s, struct drm_plane *plane, return 0; } -int mdp5_pipe_release(struct drm_atomic_state *s, struct mdp5_hw_pipe *hwpipe) +int mdp5_pipe_release(struct drm_atomic_commit *s, struct mdp5_hw_pipe *hwpipe) { struct msm_drm_private *priv = s->dev->dev_private; struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h index 452138821f60..37485d2fdeba 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h @@ -33,11 +33,11 @@ struct mdp5_hw_pipe_state { struct drm_plane *hwpipe_to_plane[SSPP_MAX]; }; -int mdp5_pipe_assign(struct drm_atomic_state *s, struct drm_plane *plane, +int mdp5_pipe_assign(struct drm_atomic_commit *s, struct drm_plane *plane, uint32_t caps, uint32_t blkcfg, struct mdp5_hw_pipe **hwpipe, struct mdp5_hw_pipe **r_hwpipe); -int mdp5_pipe_release(struct drm_atomic_state *s, struct mdp5_hw_pipe *hwpipe); +int mdp5_pipe_release(struct drm_atomic_commit *s, struct mdp5_hw_pipe *hwpipe); struct mdp5_hw_pipe *mdp5_pipe_init(struct drm_device *dev, enum mdp5_pipe pipe, diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c index c4624a49b32f..841f444a8d68 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c @@ -323,7 +323,7 @@ static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state, } static int mdp5_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); @@ -344,7 +344,7 @@ static int mdp5_plane_atomic_check(struct drm_plane *plane, } static void mdp5_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -363,7 +363,7 @@ static void mdp5_plane_atomic_update(struct drm_plane *plane, } static int mdp5_plane_atomic_async_check(struct drm_plane *plane, - struct drm_atomic_state *state, bool flip) + struct drm_atomic_commit *state, bool flip) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -417,7 +417,7 @@ static int mdp5_plane_atomic_async_check(struct drm_plane *plane, } static void mdp5_plane_atomic_async_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/msm/disp/msm_disp_snapshot.h b/drivers/gpu/drm/msm/disp/msm_disp_snapshot.h index 53bd1dcde15f..38bde9e60e11 100644 --- a/drivers/gpu/drm/msm/disp/msm_disp_snapshot.h +++ b/drivers/gpu/drm/msm/disp/msm_disp_snapshot.h @@ -48,7 +48,7 @@ struct msm_disp_state { struct list_head blocks; - struct drm_atomic_state *atomic_state; + struct drm_atomic_commit *atomic_state; struct timespec64 time; }; diff --git a/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c b/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c index 427d3ee2b833..5e151952dea8 100644 --- a/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c +++ b/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c @@ -152,7 +152,7 @@ void msm_disp_state_free(void *data) struct msm_disp_state_block *block, *tmp; if (disp_state->atomic_state) { - drm_atomic_state_put(disp_state->atomic_state); + drm_atomic_commit_put(disp_state->atomic_state); disp_state->atomic_state = NULL; } diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index d2124d625485..1b3cbf4016ef 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1591,7 +1591,7 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_display, struct drm_device *dev, } void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); struct msm_dp *dp = msm_dp_bridge->msm_dp_display; @@ -1652,7 +1652,7 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, } void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); struct msm_dp *dp = msm_dp_bridge->msm_dp_display; @@ -1664,7 +1664,7 @@ void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, } void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); struct msm_dp *dp = msm_dp_bridge->msm_dp_display; diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index 333fce3d44ed..349175457566 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -144,7 +144,7 @@ static int msm_edp_bridge_atomic_check(struct drm_bridge *drm_bridge, } static void msm_edp_bridge_atomic_enable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state; @@ -173,7 +173,7 @@ static void msm_edp_bridge_atomic_enable(struct drm_bridge *drm_bridge, } static void msm_edp_bridge_atomic_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *atomic_state) + struct drm_atomic_commit *atomic_state) { struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state = NULL, *old_crtc_state = NULL; @@ -217,7 +217,7 @@ static void msm_edp_bridge_atomic_disable(struct drm_bridge *drm_bridge, } static void msm_edp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *atomic_state) + struct drm_atomic_commit *atomic_state) { struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state = NULL; diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_drm.h index 9eb3431dd93a..ec76448e71ae 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_drm.h @@ -26,11 +26,11 @@ int msm_dp_bridge_init(struct msm_dp *msm_dp_display, struct drm_device *dev, bool yuv_supported); void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode); diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c index a9eb6489c520..c4d5e0faf3b3 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c @@ -283,7 +283,7 @@ static void msm_hdmi_set_timings(struct hdmi *hdmi, const struct drm_display_mode *mode); static void msm_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); struct hdmi *hdmi = hdmi_bridge->hdmi; @@ -325,7 +325,7 @@ static void msm_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge, } static void msm_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); struct hdmi *hdmi = hdmi_bridge->hdmi; diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index 87a91148a731..a8babf1dbe0d 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -136,7 +136,7 @@ void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer) kthread_destroy_worker(timer->worker); } -static bool can_do_async(struct drm_atomic_state *state, +static bool can_do_async(struct drm_atomic_commit *state, struct drm_crtc **async_crtc) { struct drm_connector_state *connector_state; @@ -169,7 +169,7 @@ static bool can_do_async(struct drm_atomic_state *state, * can be used with for_each_crtc_mask() iterator, to iterate * effected crtcs without needing to preserve the atomic state. */ -static unsigned get_crtc_mask(struct drm_atomic_state *state) +static unsigned get_crtc_mask(struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state; struct drm_crtc *crtc; @@ -181,7 +181,7 @@ static unsigned get_crtc_mask(struct drm_atomic_state *state) return mask; } -int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) +int msm_atomic_check(struct drm_device *dev, struct drm_atomic_commit *state) { struct msm_drm_private *priv = dev->dev_private; struct msm_kms *kms = priv->kms; @@ -210,7 +210,7 @@ int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) return drm_atomic_helper_check(dev, state); } -void msm_atomic_commit_tail(struct drm_atomic_state *state) +void msm_atomic_commit_tail(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; struct msm_drm_private *priv = dev->dev_private; diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 6d847d593f1a..76ac61df0b35 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -219,9 +219,9 @@ struct msm_pending_timer; int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, struct msm_kms *kms, int crtc_idx); void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); -void msm_atomic_commit_tail(struct drm_atomic_state *state); -int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); -struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); +void msm_atomic_commit_tail(struct drm_atomic_commit *state); +int msm_atomic_check(struct drm_device *dev, struct drm_atomic_commit *state); +struct drm_atomic_commit *msm_atomic_state_alloc(struct drm_device *dev); int msm_crtc_enable_vblank(struct drm_crtc *crtc); void msm_crtc_disable_vblank(struct drm_crtc *crtc); diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index 8a7be7b854de..f25b31e502d2 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -66,13 +66,13 @@ struct msm_kms_funcs { * * Verify if the commit requires a full modeset on one of CRTCs. */ - int (*check_mode_changed)(struct msm_kms *kms, struct drm_atomic_state *state); + int (*check_mode_changed)(struct msm_kms *kms, struct drm_atomic_commit *state); /** * Prepare for atomic commit. This is called after any previous * (async or otherwise) commit has completed. */ - void (*prepare_commit)(struct msm_kms *kms, struct drm_atomic_state *state); + void (*prepare_commit)(struct msm_kms *kms, struct drm_atomic_commit *state); /** * Flush an atomic commit. This is called after the hardware diff --git a/drivers/gpu/drm/mxsfb/lcdif_kms.c b/drivers/gpu/drm/mxsfb/lcdif_kms.c index ef3250a5c54f..ade76c3f4e4e 100644 --- a/drivers/gpu/drm/mxsfb/lcdif_kms.c +++ b/drivers/gpu/drm/mxsfb/lcdif_kms.c @@ -422,7 +422,7 @@ static void lcdif_crtc_mode_set_nofb(struct drm_crtc_state *crtc_state, } static int lcdif_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, @@ -503,7 +503,7 @@ static int lcdif_crtc_atomic_check(struct drm_crtc *crtc, } static void lcdif_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev); struct drm_pending_vblank_event *event; @@ -528,7 +528,7 @@ static void lcdif_crtc_atomic_flush(struct drm_crtc *crtc, } static void lcdif_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev); struct drm_crtc_state *new_cstate = drm_atomic_get_new_crtc_state(state, crtc); @@ -558,7 +558,7 @@ static void lcdif_crtc_atomic_enable(struct drm_crtc *crtc, } static void lcdif_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev); struct drm_device *drm = lcdif->drm; @@ -664,7 +664,7 @@ static const struct drm_crtc_funcs lcdif_crtc_funcs = { */ static int lcdif_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -681,7 +681,7 @@ static int lcdif_plane_atomic_check(struct drm_plane *plane, } static void lcdif_plane_primary_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct lcdif_drm_private *lcdif = to_lcdif_drm_private(plane->dev); struct drm_plane_state *new_pstate = drm_atomic_get_new_plane_state(state, diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c index 8cac0a275b7d..d8ebebc5314b 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c @@ -310,7 +310,7 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb, } static int mxsfb_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -326,7 +326,7 @@ static int mxsfb_crtc_atomic_check(struct drm_crtc *crtc, } static void mxsfb_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_pending_vblank_event *event; @@ -345,7 +345,7 @@ static void mxsfb_crtc_atomic_flush(struct drm_crtc *crtc, } static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); struct drm_plane_state *new_pstate = drm_atomic_get_new_plane_state(state, @@ -399,7 +399,7 @@ static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, } static void mxsfb_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); struct drm_device *drm = mxsfb->drm; @@ -520,7 +520,7 @@ static const struct drm_encoder_funcs mxsfb_encoder_funcs = { */ static int mxsfb_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -537,7 +537,7 @@ static int mxsfb_plane_atomic_check(struct drm_plane *plane, } static void mxsfb_plane_primary_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev); struct drm_plane_state *new_pstate = drm_atomic_get_new_plane_state(state, @@ -550,7 +550,7 @@ static void mxsfb_plane_primary_atomic_update(struct drm_plane *plane, } static void mxsfb_plane_overlay_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_pstate = drm_atomic_get_old_plane_state(state, plane); @@ -613,7 +613,7 @@ static void mxsfb_plane_overlay_atomic_update(struct drm_plane *plane, } static void mxsfb_plane_overlay_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev); diff --git a/drivers/gpu/drm/nouveau/dispnv50/atom.h b/drivers/gpu/drm/nouveau/dispnv50/atom.h index b43c4f9bbcdf..c34a42ea9ac4 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/atom.h +++ b/drivers/gpu/drm/nouveau/dispnv50/atom.h @@ -7,7 +7,7 @@ struct nouveau_encoder; struct nv50_atom { - struct drm_atomic_state state; + struct drm_atomic_commit state; struct list_head outp; bool lock_core; @@ -149,7 +149,7 @@ struct nv50_head_atom { }; static inline struct nv50_head_atom * -nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc) +nv50_head_atom_get(struct drm_atomic_commit *state, struct drm_crtc *crtc) { struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc); @@ -160,7 +160,7 @@ nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc) } static inline struct nv50_head_atom * -nv50_head_atom_get_new(struct drm_atomic_state *state, struct drm_crtc *crtc) +nv50_head_atom_get_new(struct drm_atomic_commit *state, struct drm_crtc *crtc) { struct drm_crtc_state *statec = drm_atomic_get_new_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc.c b/drivers/gpu/drm/nouveau/dispnv50/crc.c index deb6af40ef32..e736318fb0dc 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crc.c @@ -237,7 +237,7 @@ static void nv50_crc_wait_ctx_finished(struct nv50_head *head, head->base.index, ret); } -void nv50_crc_atomic_stop_reporting(struct drm_atomic_state *state) +void nv50_crc_atomic_stop_reporting(struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state; struct drm_crtc *crtc; @@ -269,7 +269,7 @@ void nv50_crc_atomic_stop_reporting(struct drm_atomic_state *state) } } -void nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state *state) +void nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_commit *state) { struct drm_crtc_state *new_crtc_state; struct drm_crtc *crtc; @@ -291,7 +291,7 @@ void nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state *state) } } -void nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_state *state) +void nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_commit *state) { const struct nv50_crc_func *func = nv50_disp(state->dev)->core->func->crc; @@ -316,7 +316,7 @@ void nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_state *state) } } -void nv50_crc_atomic_start_reporting(struct drm_atomic_state *state) +void nv50_crc_atomic_start_reporting(struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state; struct drm_crtc *crtc; @@ -544,7 +544,7 @@ nv50_crc_ctx_fini(struct nv50_crc_notifier_ctx *ctx) int nv50_crc_set_source(struct drm_crtc *crtc, const char *source_str) { struct drm_device *dev = crtc->dev; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_modeset_acquire_ctx ctx; struct nv50_head *head = nv50_head(crtc); struct nv50_crc *crc = &head->crc; @@ -567,7 +567,7 @@ int nv50_crc_set_source(struct drm_crtc *crtc, const char *source_str) ctx_flags |= DRM_MODESET_ACQUIRE_INTERRUPTIBLE; drm_modeset_acquire_init(&ctx, ctx_flags); - state = drm_atomic_state_alloc(dev); + state = drm_atomic_commit_alloc(dev); if (!state) { ret = -ENOMEM; goto out_acquire_fini; @@ -617,13 +617,13 @@ int nv50_crc_set_source(struct drm_crtc *crtc, const char *source_str) for (i = 0; i < ARRAY_SIZE(crc->ctx); i++) nv50_crc_ctx_fini(&crc->ctx[i]); } - drm_atomic_state_put(state); + drm_atomic_commit_put(state); out_acquire_fini: drm_modeset_acquire_fini(&ctx); return ret; deadlock: - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); drm_modeset_backoff(&ctx); goto retry; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc.h b/drivers/gpu/drm/nouveau/dispnv50/crc.h index 75a2009e8193..cefa2dd52f12 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc.h +++ b/drivers/gpu/drm/nouveau/dispnv50/crc.h @@ -84,10 +84,10 @@ int nv50_crc_set_source(struct drm_crtc *, const char *); int nv50_crc_atomic_check_head(struct nv50_head *, struct nv50_head_atom *, struct nv50_head_atom *); void nv50_crc_atomic_check_outp(struct nv50_atom *atom); -void nv50_crc_atomic_stop_reporting(struct drm_atomic_state *); -void nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state *); -void nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_state *); -void nv50_crc_atomic_start_reporting(struct drm_atomic_state *); +void nv50_crc_atomic_stop_reporting(struct drm_atomic_commit *); +void nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_commit *); +void nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_commit *); +void nv50_crc_atomic_start_reporting(struct drm_atomic_commit *); void nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *); void nv50_crc_atomic_clr(struct nv50_head *); @@ -116,13 +116,13 @@ nv50_crc_atomic_check_head(struct nv50_head *head, struct nv50_head_atom *armh) { return 0; } static inline void nv50_crc_atomic_check_outp(struct nv50_atom *atom) {} static inline void -nv50_crc_atomic_stop_reporting(struct drm_atomic_state *state) {} +nv50_crc_atomic_stop_reporting(struct drm_atomic_commit *state) {} static inline void -nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state *state) {} +nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_commit *state) {} static inline void -nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_state *state) {} +nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_commit *state) {} static inline void -nv50_crc_atomic_start_reporting(struct drm_atomic_state *state) {} +nv50_crc_atomic_start_reporting(struct drm_atomic_commit *state) {} static inline void nv50_crc_atomic_set(struct nv50_head *head, struct nv50_head_atom *state) {} static inline void diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 04b6fa3ee2ae..364227f5456f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -428,7 +428,7 @@ nv50_outp_atomic_check(struct drm_encoder *encoder, } struct nouveau_connector * -nv50_outp_get_new_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp) +nv50_outp_get_new_connector(struct drm_atomic_commit *state, struct nouveau_encoder *outp) { struct drm_connector *connector; struct drm_connector_state *connector_state; @@ -444,7 +444,7 @@ nv50_outp_get_new_connector(struct drm_atomic_state *state, struct nouveau_encod } struct nouveau_connector * -nv50_outp_get_old_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp) +nv50_outp_get_old_connector(struct drm_atomic_commit *state, struct nouveau_encoder *outp) { struct drm_connector *connector; struct drm_connector_state *connector_state; @@ -460,7 +460,7 @@ nv50_outp_get_old_connector(struct drm_atomic_state *state, struct nouveau_encod } static struct nouveau_crtc * -nv50_outp_get_new_crtc(const struct drm_atomic_state *state, const struct nouveau_encoder *outp) +nv50_outp_get_new_crtc(const struct drm_atomic_commit *state, const struct nouveau_encoder *outp) { struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; @@ -479,7 +479,7 @@ nv50_outp_get_new_crtc(const struct drm_atomic_state *state, const struct nouvea * DAC *****************************************************************************/ static void -nv50_dac_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) +nv50_dac_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_commit *state) { struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct nv50_core *core = nv50_disp(encoder->dev)->core; @@ -490,7 +490,7 @@ nv50_dac_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *st } static void -nv50_dac_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) +nv50_dac_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_commit *state) { struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); @@ -750,7 +750,7 @@ nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) static void nv50_audio_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc, - struct nouveau_connector *nv_connector, struct drm_atomic_state *state, + struct nouveau_connector *nv_connector, struct drm_atomic_commit *state, struct drm_display_mode *mode) { struct nouveau_drm *drm = nouveau_drm(encoder->dev); @@ -776,7 +776,7 @@ nv50_audio_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc, *****************************************************************************/ static void nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc, - struct nouveau_connector *nv_connector, struct drm_atomic_state *state, + struct nouveau_connector *nv_connector, struct drm_atomic_commit *state, struct drm_display_mode *mode, bool hda) { struct nouveau_drm *drm = nouveau_drm(encoder->dev); @@ -892,7 +892,7 @@ struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder) } static void -nv50_msto_cleanup(struct drm_atomic_state *state, +nv50_msto_cleanup(struct drm_atomic_commit *state, struct drm_dp_mst_topology_state *new_mst_state, struct drm_dp_mst_topology_mgr *mgr, struct nv50_msto *msto) @@ -925,7 +925,7 @@ nv50_msto_cleanup(struct drm_atomic_state *state, } static void -nv50_msto_prepare(struct drm_atomic_state *state, +nv50_msto_prepare(struct drm_atomic_commit *state, struct drm_dp_mst_topology_state *mst_state, struct drm_dp_mst_topology_mgr *mgr, struct nv50_msto *msto) @@ -964,7 +964,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { - struct drm_atomic_state *state = crtc_state->state; + struct drm_atomic_commit *state = crtc_state->state; struct drm_connector *connector = conn_state->connector; struct drm_dp_mst_topology_state *mst_state; struct nv50_mstc *mstc = nv50_mstc(connector); @@ -1024,7 +1024,7 @@ nv50_dp_bpc_to_depth(unsigned int bpc) } static void -nv50_msto_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) +nv50_msto_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_commit *state) { struct nv50_msto *msto = nv50_msto(encoder); struct nv50_head *head = msto->head; @@ -1073,7 +1073,7 @@ nv50_msto_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *st } static void -nv50_msto_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) +nv50_msto_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_commit *state) { struct nv50_msto *msto = nv50_msto(encoder); struct nv50_mstc *mstc = msto->mstc; @@ -1134,7 +1134,7 @@ nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id) static struct drm_encoder * nv50_mstc_atomic_best_encoder(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, connector); @@ -1192,7 +1192,7 @@ nv50_mstc_get_modes(struct drm_connector *connector) static int nv50_mstc_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct nv50_mstc *mstc = nv50_mstc(connector); struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr; @@ -1301,7 +1301,7 @@ nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, } static void -nv50_mstm_cleanup(struct drm_atomic_state *state, +nv50_mstm_cleanup(struct drm_atomic_commit *state, struct drm_dp_mst_topology_state *mst_state, struct nv50_mstm *mstm) { @@ -1330,7 +1330,7 @@ nv50_mstm_cleanup(struct drm_atomic_state *state, } static void -nv50_mstm_prepare(struct drm_atomic_state *state, +nv50_mstm_prepare(struct drm_atomic_commit *state, struct drm_dp_mst_topology_state *mst_state, struct nv50_mstm *mstm) { @@ -1562,7 +1562,7 @@ nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, * fixed time delay from the vbios… */ static void -nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) +nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_commit *state) { struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct nv50_head *head = nv50_head(nv_encoder->crtc); @@ -1741,7 +1741,7 @@ nv50_sor_dp_watermark_sst(struct nouveau_encoder *outp, } static void -nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) +nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_commit *state) { struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); @@ -1967,7 +1967,7 @@ nv50_pior_atomic_check(struct drm_encoder *encoder, } static void -nv50_pior_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) +nv50_pior_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_commit *state) { struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct nv50_core *core = nv50_disp(encoder->dev)->core; @@ -1978,7 +1978,7 @@ nv50_pior_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *s } static void -nv50_pior_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) +nv50_pior_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_commit *state) { struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); @@ -2099,7 +2099,7 @@ nv50_pior_create(struct nouveau_encoder *nv_encoder) *****************************************************************************/ static void -nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) +nv50_disp_atomic_commit_core(struct drm_atomic_commit *state, u32 *interlock) { struct drm_dp_mst_topology_mgr *mgr; struct drm_dp_mst_topology_state *mst_state; @@ -2150,7 +2150,7 @@ nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) } static void -nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) +nv50_disp_atomic_commit_wndw(struct drm_atomic_commit *state, u32 *interlock) { struct drm_plane_state *new_plane_state; struct drm_plane *plane; @@ -2166,7 +2166,7 @@ nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) } static void -nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) +nv50_disp_atomic_commit_tail(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; struct drm_crtc_state *new_crtc_state, *old_crtc_state; @@ -2408,7 +2408,7 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) drm_atomic_helper_commit_hw_done(state); drm_atomic_helper_cleanup_planes(dev, state); drm_atomic_helper_commit_cleanup_done(state); - drm_atomic_state_put(state); + drm_atomic_commit_put(state); /* Drop the RPM ref we got from nv50_disp_atomic_commit() */ pm_runtime_mark_last_busy(dev->dev); @@ -2418,14 +2418,14 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) static void nv50_disp_atomic_commit_work(struct work_struct *work) { - struct drm_atomic_state *state = + struct drm_atomic_commit *state = container_of(work, typeof(*state), commit_work); nv50_disp_atomic_commit_tail(state); } static int nv50_disp_atomic_commit(struct drm_device *dev, - struct drm_atomic_state *state, bool nonblock) + struct drm_atomic_commit *state, bool nonblock) { struct drm_plane_state *new_plane_state; struct drm_plane *plane; @@ -2465,7 +2465,7 @@ nv50_disp_atomic_commit(struct drm_device *dev, nv50_wndw_ntfy_enable(wndw, asyw); } - drm_atomic_state_get(state); + drm_atomic_commit_get(state); /* * Grab another RPM ref for the commit tail, which will release the @@ -2560,7 +2560,7 @@ nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, } static int -nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) +nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_commit *state) { struct nv50_atom *atom = nv50_atom(state); struct nv50_core *core = nv50_disp(dev)->core; @@ -2618,7 +2618,7 @@ nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) } static void -nv50_disp_atomic_state_clear(struct drm_atomic_state *state) +nv50_disp_atomic_state_clear(struct drm_atomic_commit *state) { struct nv50_atom *atom = nv50_atom(state); struct nv50_outp_atom *outp, *outt; @@ -2628,23 +2628,23 @@ nv50_disp_atomic_state_clear(struct drm_atomic_state *state) kfree(outp); } - drm_atomic_state_default_clear(state); + drm_atomic_commit_default_clear(state); } static void -nv50_disp_atomic_state_free(struct drm_atomic_state *state) +nv50_disp_atomic_state_free(struct drm_atomic_commit *state) { struct nv50_atom *atom = nv50_atom(state); - drm_atomic_state_default_release(&atom->state); + drm_atomic_commit_default_release(&atom->state); kfree(atom); } -static struct drm_atomic_state * +static struct drm_atomic_commit * nv50_disp_atomic_state_alloc(struct drm_device *dev) { struct nv50_atom *atom; if (!(atom = kzalloc_obj(*atom)) || - drm_atomic_state_init(dev, &atom->state) < 0) { + drm_atomic_commit_init(dev, &atom->state) < 0) { kfree(atom); return NULL; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c b/drivers/gpu/drm/nouveau/dispnv50/head.c index 4ca7700fb784..1affa0378bd0 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head.c @@ -330,7 +330,7 @@ nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh) } static int -nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) +nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 9ad4973716f7..2635458d52ac 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -441,7 +441,7 @@ nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw, static int nv50_wndw_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index cc239492c7f0..b0b0ad9a0c24 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -1132,7 +1132,7 @@ nouveau_connector_best_encoder(struct drm_connector *connector) } static int -nouveau_connector_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state) +nouveau_connector_atomic_check(struct drm_connector *connector, struct drm_atomic_commit *state) { struct nouveau_connector *nv_conn = nouveau_connector(connector); struct drm_connector_state *conn_state = diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h index 470e0910d484..e711c89723e8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.h +++ b/drivers/gpu/drm/nouveau/nouveau_display.h @@ -34,7 +34,7 @@ struct nouveau_display { struct drm_property *vibrant_hue_property; struct drm_property *color_vibrance_property; - struct drm_atomic_state *suspend; + struct drm_atomic_commit *suspend; const u64 *format_modifiers; }; diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h index dce8e5d9d496..4422c6185d49 100644 --- a/drivers/gpu/drm/nouveau/nouveau_encoder.h +++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h @@ -165,9 +165,9 @@ enum drm_mode_status nv50_dp_mode_valid(struct nouveau_encoder *, unsigned *clock); struct nouveau_connector * -nv50_outp_get_new_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp); +nv50_outp_get_new_connector(struct drm_atomic_commit *state, struct nouveau_encoder *outp); struct nouveau_connector * -nv50_outp_get_old_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp); +nv50_outp_get_old_connector(struct drm_atomic_commit *state, struct nouveau_encoder *outp); int nv50_mstm_detect(struct nouveau_encoder *encoder); void nv50_mstm_remove(struct nv50_mstm *mstm); diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4.c b/drivers/gpu/drm/omapdrm/dss/hdmi4.c index 29b2dfb90b5f..e306247ed8a0 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi4.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi4.c @@ -342,7 +342,7 @@ static void hdmi4_bridge_mode_set(struct drm_bridge *bridge, } static void hdmi4_bridge_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct omap_hdmi *hdmi = drm_bridge_to_hdmi(bridge); struct drm_connector_state *conn_state; @@ -410,7 +410,7 @@ static void hdmi4_bridge_enable(struct drm_bridge *bridge, } static void hdmi4_bridge_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct omap_hdmi *hdmi = drm_bridge_to_hdmi(bridge); unsigned long flags; diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5.c b/drivers/gpu/drm/omapdrm/dss/hdmi5.c index 5636b3dfec1c..ab2d4eb6787f 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi5.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi5.c @@ -340,7 +340,7 @@ static void hdmi5_bridge_mode_set(struct drm_bridge *bridge, } static void hdmi5_bridge_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct omap_hdmi *hdmi = drm_bridge_to_hdmi(bridge); struct drm_connector_state *conn_state; @@ -408,7 +408,7 @@ static void hdmi5_bridge_enable(struct drm_bridge *bridge, } static void hdmi5_bridge_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct omap_hdmi *hdmi = drm_bridge_to_hdmi(bridge); unsigned long flags; diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index ee4c0119d408..c1b41e010a00 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -446,7 +446,7 @@ static void omap_crtc_arm_event(struct drm_crtc *crtc) } static void omap_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct omap_drm_private *priv = crtc->dev->dev_private; struct omap_crtc *omap_crtc = to_omap_crtc(crtc); @@ -472,7 +472,7 @@ static void omap_crtc_atomic_enable(struct drm_crtc *crtc, } static void omap_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct omap_drm_private *priv = crtc->dev->dev_private; struct omap_crtc *omap_crtc = to_omap_crtc(crtc); @@ -577,7 +577,7 @@ static bool omap_crtc_is_manually_updated(struct drm_crtc *crtc) } static int omap_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -609,12 +609,12 @@ static int omap_crtc_atomic_check(struct drm_crtc *crtc, } static void omap_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { } static void omap_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct omap_drm_private *priv = crtc->dev->dev_private; struct omap_crtc *omap_crtc = to_omap_crtc(crtc); diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index 31bf2618046b..92d6a1f9c0a1 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -46,7 +46,7 @@ */ static void omap_atomic_wait_for_completion(struct drm_device *dev, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct drm_crtc_state *new_crtc_state; struct drm_crtc *crtc; @@ -65,7 +65,7 @@ static void omap_atomic_wait_for_completion(struct drm_device *dev, } } -static void omap_atomic_commit_tail(struct drm_atomic_state *old_state) +static void omap_atomic_commit_tail(struct drm_atomic_commit *old_state) { struct drm_device *dev = old_state->dev; struct omap_drm_private *priv = dev->dev_private; @@ -117,7 +117,7 @@ static void omap_atomic_commit_tail(struct drm_atomic_state *old_state) dispc_runtime_put(priv->dispc); } -static int drm_atomic_state_normalized_zpos_cmp(const void *a, const void *b) +static int drm_atomic_commit_normalized_zpos_cmp(const void *a, const void *b) { const struct drm_plane_state *sa = *(struct drm_plane_state **)a; const struct drm_plane_state *sb = *(struct drm_plane_state **)b; @@ -136,7 +136,7 @@ static int drm_atomic_state_normalized_zpos_cmp(const void *a, const void *b) * planes zpos is consistent. */ static int omap_atomic_update_normalize_zpos(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *old_state, *new_state; @@ -174,7 +174,7 @@ static int omap_atomic_update_normalize_zpos(struct drm_device *dev, } sort(states, n, sizeof(*states), - drm_atomic_state_normalized_zpos_cmp, NULL); + drm_atomic_commit_normalized_zpos_cmp, NULL); for (i = 0, inc = 0; i < n; i++) { plane = states[i]->plane; @@ -196,7 +196,7 @@ static int omap_atomic_update_normalize_zpos(struct drm_device *dev, } static int omap_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { int ret; @@ -241,7 +241,7 @@ omap_get_existing_global_state(struct omap_drm_private *priv) * a new duplicated private object state. */ struct omap_global_state *__must_check -omap_get_global_state(struct drm_atomic_state *s) +omap_get_global_state(struct drm_atomic_commit *s) { struct omap_drm_private *priv = s->dev->dev_private; struct drm_private_state *priv_state; diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h index d903568fd8cc..c1f24ce929d9 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.h +++ b/drivers/gpu/drm/omapdrm/omap_drv.h @@ -105,7 +105,7 @@ struct omap_drm_private { void omap_debugfs_init(struct drm_minor *minor); -struct omap_global_state * __must_check omap_get_global_state(struct drm_atomic_state *s); +struct omap_global_state * __must_check omap_get_global_state(struct drm_atomic_commit *s); struct omap_global_state *omap_get_existing_global_state(struct omap_drm_private *priv); diff --git a/drivers/gpu/drm/omapdrm/omap_overlay.c b/drivers/gpu/drm/omapdrm/omap_overlay.c index 77c1b78d0163..d722e3c7db76 100644 --- a/drivers/gpu/drm/omapdrm/omap_overlay.c +++ b/drivers/gpu/drm/omapdrm/omap_overlay.c @@ -66,7 +66,7 @@ omap_plane_find_free_overlay(struct drm_device *dev, struct drm_plane *hwoverlay * This should be called from the plane atomic_check() in order to prepare the * next global overlay_map to be enabled when atomic transaction is valid. */ -int omap_overlay_assign(struct drm_atomic_state *s, struct drm_plane *plane, +int omap_overlay_assign(struct drm_atomic_commit *s, struct drm_plane *plane, u32 caps, u32 fourcc, struct omap_hw_overlay **overlay, struct omap_hw_overlay **r_overlay) { @@ -111,7 +111,7 @@ int omap_overlay_assign(struct drm_atomic_state *s, struct drm_plane *plane, * This should be called from the plane atomic_check() in order to prepare the * next global overlay_map to be enabled when atomic transaction is valid. */ -void omap_overlay_release(struct drm_atomic_state *s, struct omap_hw_overlay *overlay) +void omap_overlay_release(struct drm_atomic_commit *s, struct omap_hw_overlay *overlay) { /* Get the global state of the current atomic transaction */ struct omap_global_state *state = omap_get_global_state(s); diff --git a/drivers/gpu/drm/omapdrm/omap_overlay.h b/drivers/gpu/drm/omapdrm/omap_overlay.h index e36a43f35563..e44332455210 100644 --- a/drivers/gpu/drm/omapdrm/omap_overlay.h +++ b/drivers/gpu/drm/omapdrm/omap_overlay.h @@ -27,9 +27,9 @@ struct omap_hw_overlay { int omap_hwoverlays_init(struct omap_drm_private *priv); void omap_hwoverlays_destroy(struct omap_drm_private *priv); -int omap_overlay_assign(struct drm_atomic_state *s, struct drm_plane *plane, +int omap_overlay_assign(struct drm_atomic_commit *s, struct drm_plane *plane, u32 caps, u32 fourcc, struct omap_hw_overlay **overlay, struct omap_hw_overlay **r_overlay); -void omap_overlay_release(struct drm_atomic_state *s, struct omap_hw_overlay *overlay); +void omap_overlay_release(struct drm_atomic_commit *s, struct omap_hw_overlay *overlay); void omap_overlay_update_state(struct omap_drm_private *priv, struct omap_hw_overlay *overlay); #endif /* __OMAPDRM_OVERLAY_H__ */ diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index 0e09d8f1fe5e..c024cdbbd87a 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -62,7 +62,7 @@ static void omap_plane_cleanup_fb(struct drm_plane *plane, } static void omap_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct omap_drm_private *priv = plane->dev->dev_private; struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, @@ -167,7 +167,7 @@ static void omap_plane_atomic_update(struct drm_plane *plane, } static void omap_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct omap_drm_private *priv = plane->dev->dev_private; struct omap_plane *omap_plane = to_omap_plane(plane); @@ -199,7 +199,7 @@ static void omap_plane_atomic_disable(struct drm_plane *plane, #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) static int omap_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c index 75d47e6b9142..a026bd35ef48 100644 --- a/drivers/gpu/drm/qxl/qxl_display.c +++ b/drivers/gpu/drm/qxl/qxl_display.c @@ -382,7 +382,7 @@ static void qxl_crtc_update_monitors_config(struct drm_crtc *crtc, } static void qxl_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = crtc->dev; struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -473,7 +473,7 @@ static const struct drm_framebuffer_funcs qxl_fb_funcs = { }; static void qxl_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { qxl_crtc_update_monitors_config(crtc, "enable"); @@ -481,7 +481,7 @@ static void qxl_crtc_atomic_enable(struct drm_crtc *crtc, } static void qxl_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { drm_crtc_vblank_off(crtc); @@ -495,7 +495,7 @@ static const struct drm_crtc_helper_funcs qxl_crtc_helper_funcs = { }; static int qxl_primary_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -662,7 +662,7 @@ static void qxl_free_cursor(struct qxl_bo *cursor_bo) } static void qxl_primary_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -695,7 +695,7 @@ static void qxl_primary_atomic_update(struct drm_plane *plane, } static void qxl_primary_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -712,7 +712,7 @@ static void qxl_primary_atomic_disable(struct drm_plane *plane, } static void qxl_cursor_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -729,7 +729,7 @@ static void qxl_cursor_atomic_update(struct drm_plane *plane, } static void qxl_cursor_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c index 22321eb95b7d..703848fac189 100644 --- a/drivers/gpu/drm/radeon/ci_dpm.c +++ b/drivers/gpu/drm/radeon/ci_dpm.c @@ -2461,7 +2461,8 @@ static void ci_register_patching_mc_arb(struct radeon_device *rdev, if (patch && ((rdev->pdev->device == 0x67B0) || - (rdev->pdev->device == 0x67B1))) { + (rdev->pdev->device == 0x67B1)) && + (rdev->pdev->revision == 0)) { if ((memory_clock > 100000) && (memory_clock <= 125000)) { tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff; *dram_timimg2 &= ~0x00ff0000; @@ -3304,7 +3305,8 @@ static int ci_populate_all_memory_levels(struct radeon_device *rdev) pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; if ((dpm_table->mclk_table.count >= 2) && - ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) { + ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1)) && + (rdev->pdev->revision == 0)) { pi->smc_state_table.MemoryLevel[1].MinVddc = pi->smc_state_table.MemoryLevel[0].MinVddc; pi->smc_state_table.MemoryLevel[1].MinVddcPhases = @@ -4493,7 +4495,8 @@ static int ci_register_patching_mc_seq(struct radeon_device *rdev, if (patch && ((rdev->pdev->device == 0x67B0) || - (rdev->pdev->device == 0x67B1))) { + (rdev->pdev->device == 0x67B1)) && + (rdev->pdev->revision == 0)) { for (i = 0; i < table->last; i++) { if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) return -EINVAL; diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 51a3e0fc2f56..a13635443833 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -9063,7 +9063,7 @@ static u32 dce8_available_bandwidth(struct dce8_wm_params *wm) u32 data_return_bandwidth = dce8_data_return_bandwidth(wm); u32 dmif_req_bandwidth = dce8_dmif_request_bandwidth(wm); - return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); + return min3(dram_bandwidth, data_return_bandwidth, dmif_req_bandwidth); } /** diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c index 20fc87409f2e..8ce180e22d1d 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -28,6 +28,7 @@ #include #include +#include #include #include @@ -812,6 +813,7 @@ int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tile int aligned = width; int align_large = (ASIC_IS_AVIVO(rdev)) || tiled; int pitch_mask = 0; + int pitch; switch (cpp) { case 1: @@ -826,9 +828,12 @@ int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tile break; } - aligned += pitch_mask; + if (check_add_overflow(aligned, pitch_mask, &aligned)) + return 0; aligned &= ~pitch_mask; - return aligned * cpp; + if (check_mul_overflow(aligned, cpp, &pitch)) + return 0; + return pitch; } int radeon_mode_dumb_create(struct drm_file *file_priv, @@ -842,8 +847,12 @@ int radeon_mode_dumb_create(struct drm_file *file_priv, args->pitch = radeon_align_pitch(rdev, args->width, DIV_ROUND_UP(args->bpp, 8), 0); + if (!args->pitch) + return -EINVAL; args->size = (u64)args->pitch * args->height; args->size = ALIGN(args->size, PAGE_SIZE); + if (!args->size) + return -EINVAL; r = radeon_gem_object_create(rdev, args->size, 0, RADEON_GEM_DOMAIN_VRAM, 0, diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c index 581ae20c46e4..a5dff072c1ac 100644 --- a/drivers/gpu/drm/radeon/radeon_ring.c +++ b/drivers/gpu/drm/radeon/radeon_ring.c @@ -356,8 +356,10 @@ int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, /* restore the saved ring content */ r = radeon_ring_lock(rdev, ring, size); - if (r) + if (r) { + kvfree(data); return r; + } for (i = 0; i < size; ++i) { radeon_ring_write(ring, data[i]); diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 26197aceb001..4681ff28630a 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -2150,7 +2150,7 @@ static u32 dce6_available_bandwidth(struct dce6_wm_params *wm) u32 data_return_bandwidth = dce6_data_return_bandwidth(wm); u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm); - return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); + return min3(dram_bandwidth, data_return_bandwidth, dmif_req_bandwidth); } static u32 dce6_average_bandwidth(struct dce6_wm_params *wm) diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c index 1a246ebbfc61..6c07c406f725 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c @@ -689,7 +689,7 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc) */ static int rcar_du_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -720,7 +720,7 @@ static int rcar_du_crtc_atomic_check(struct drm_crtc *crtc, } static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc->state); @@ -768,7 +768,7 @@ static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc, } static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -812,7 +812,7 @@ static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc, } static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); @@ -841,7 +841,7 @@ static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc, } static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); struct drm_device *dev = rcrtc->crtc.dev; @@ -1103,7 +1103,7 @@ static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc, struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); struct drm_modeset_acquire_ctx ctx; struct drm_crtc_state *crtc_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; enum vsp1_du_crc_source source; unsigned int index; int ret; @@ -1117,7 +1117,7 @@ static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc, /* Perform an atomic commit to set the CRC source. */ drm_modeset_acquire_init(&ctx, 0); - state = drm_atomic_state_alloc(crtc->dev); + state = drm_atomic_commit_alloc(crtc->dev); if (!state) { ret = -ENOMEM; goto unlock; @@ -1140,12 +1140,12 @@ static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc, } if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); drm_modeset_backoff(&ctx); goto retry; } - drm_atomic_state_put(state); + drm_atomic_commit_put(state); unlock: drm_modeset_drop_locks(&ctx); diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c index 1119c84e5fe9..9228a7ad0dfa 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c @@ -503,7 +503,7 @@ rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv, */ static int rcar_du_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rcar_du_device *rcdu = to_rcar_du_device(dev); int ret; @@ -518,7 +518,7 @@ static int rcar_du_atomic_check(struct drm_device *dev, return rcar_du_atomic_check_planes(dev, state); } -static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state) +static void rcar_du_atomic_commit_tail(struct drm_atomic_commit *old_state) { struct drm_device *dev = old_state->dev; struct rcar_du_device *rcdu = to_rcar_du_device(dev); diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.c index 01840feabdbe..8870766b9e54 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.c +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.c @@ -127,7 +127,7 @@ static int rcar_du_plane_hwalloc(struct rcar_du_plane *plane, } int rcar_du_atomic_check_planes(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rcar_du_device *rcdu = to_rcar_du_device(dev); unsigned int group_freed_planes[RCAR_DU_MAX_GROUPS] = { 0, }; @@ -635,7 +635,7 @@ int __rcar_du_plane_atomic_check(struct drm_plane *plane, } static int rcar_du_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -646,7 +646,7 @@ static int rcar_du_plane_atomic_check(struct drm_plane *plane, } static void rcar_du_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.h b/drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.h index e9e59c5e70d5..49970f098b7b 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.h +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.h @@ -64,7 +64,7 @@ to_rcar_plane_state(struct drm_plane_state *state) } int rcar_du_atomic_check_planes(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); int __rcar_du_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state, diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_vsp.c index a4a49dcd8233..6b413b379a86 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_vsp.c +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_vsp.c @@ -365,7 +365,7 @@ static void rcar_du_vsp_plane_cleanup_fb(struct drm_plane *plane, } static int rcar_du_vsp_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -376,7 +376,7 @@ static int rcar_du_vsp_plane_atomic_check(struct drm_plane *plane, } static void rcar_du_vsp_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c b/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c index 227818e37390..154410745a74 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c @@ -351,7 +351,7 @@ static enum rcar_lvds_mode rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds, } static void rcar_lvds_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_crtc *crtc, struct drm_connector *connector) { @@ -582,7 +582,7 @@ EXPORT_SYMBOL_GPL(rcar_lvds_pclk_disable); */ static void rcar_lvds_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector *connector; struct drm_crtc *crtc; @@ -595,7 +595,7 @@ static void rcar_lvds_atomic_enable(struct drm_bridge *bridge, } static void rcar_lvds_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c index 508977b9e892..aaafee1c060b 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c @@ -846,7 +846,7 @@ static int rcar_mipi_dsi_attach(struct drm_bridge *bridge, } static void rcar_mipi_dsi_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge); @@ -854,7 +854,7 @@ static void rcar_mipi_dsi_atomic_enable(struct drm_bridge *bridge, } static void rcar_mipi_dsi_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge); @@ -862,7 +862,7 @@ static void rcar_mipi_dsi_atomic_disable(struct drm_bridge *bridge, } void rcar_mipi_dsi_pclk_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge); const struct drm_display_mode *mode; diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.h index 528a196e6edd..cfb5d70a6b1f 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.h +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.h @@ -10,16 +10,16 @@ #ifndef __RCAR_MIPI_DSI_H__ #define __RCAR_MIPI_DSI_H__ -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_bridge; #if IS_ENABLED(CONFIG_DRM_RCAR_MIPI_DSI) void rcar_mipi_dsi_pclk_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void rcar_mipi_dsi_pclk_disable(struct drm_bridge *bridge); #else static inline void rcar_mipi_dsi_pclk_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { } diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c index 18e2b981b691..26b95153ce88 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c @@ -249,7 +249,7 @@ static void rzg2l_du_crtc_stop(struct rzg2l_du_crtc *rcrtc) */ static void rzg2l_du_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc); @@ -259,7 +259,7 @@ static void rzg2l_du_crtc_atomic_enable(struct drm_crtc *crtc, } static void rzg2l_du_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc); @@ -275,7 +275,7 @@ static void rzg2l_du_crtc_atomic_disable(struct drm_crtc *crtc, } static void rzg2l_du_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc); struct drm_device *dev = rcrtc->crtc.dev; diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c index eb626c3cc421..bc205c25cd21 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c @@ -213,7 +213,7 @@ static int __rzg2l_du_vsp_plane_atomic_check(struct drm_plane *plane, } static int rzg2l_du_vsp_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -223,7 +223,7 @@ static int rzg2l_du_vsp_plane_atomic_check(struct drm_plane *plane, } static void rzg2l_du_vsp_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c index a9763caa7b0e..a2c864860075 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -1019,7 +1019,7 @@ static int rzg2l_mipi_dsi_attach(struct drm_bridge *bridge, } static void rzg2l_mipi_dsi_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge); const struct drm_display_mode *mode; @@ -1034,7 +1034,7 @@ static void rzg2l_mipi_dsi_atomic_pre_enable(struct drm_bridge *bridge, } static void rzg2l_mipi_dsi_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge); const struct drm_display_mode *mode; @@ -1065,7 +1065,7 @@ static void rzg2l_mipi_dsi_atomic_enable(struct drm_bridge *bridge, } static void rzg2l_mipi_dsi_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge); @@ -1074,7 +1074,7 @@ static void rzg2l_mipi_dsi_atomic_disable(struct drm_bridge *bridge, } static void rzg2l_mipi_dsi_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge); diff --git a/drivers/gpu/drm/renesas/shmobile/shmob_drm_crtc.c b/drivers/gpu/drm/renesas/shmobile/shmob_drm_crtc.c index 815c770147ed..1a2b9b68af6f 100644 --- a/drivers/gpu/drm/renesas/shmobile/shmob_drm_crtc.c +++ b/drivers/gpu/drm/renesas/shmobile/shmob_drm_crtc.c @@ -198,7 +198,7 @@ static inline struct shmob_drm_crtc *to_shmob_crtc(struct drm_crtc *crtc) } static void shmob_drm_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct shmob_drm_crtc *scrtc = to_shmob_crtc(crtc); struct shmob_drm_device *sdev = to_shmob_device(crtc->dev); @@ -256,7 +256,7 @@ static void shmob_drm_crtc_atomic_enable(struct drm_crtc *crtc, } static void shmob_drm_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct shmob_drm_crtc *scrtc = to_shmob_crtc(crtc); struct shmob_drm_device *sdev = to_shmob_device(crtc->dev); @@ -279,7 +279,7 @@ static void shmob_drm_crtc_atomic_disable(struct drm_crtc *crtc, } static void shmob_drm_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_pending_vblank_event *event; struct drm_device *dev = crtc->dev; diff --git a/drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.c b/drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.c index b61fda52d17a..148de34af785 100644 --- a/drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.c +++ b/drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.c @@ -143,7 +143,7 @@ static void shmob_drm_overlay_plane_setup(struct shmob_drm_plane *splane, } static int shmob_drm_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); struct shmob_drm_plane_state *sstate = to_shmob_plane_state(new_plane_state); @@ -192,7 +192,7 @@ static int shmob_drm_plane_atomic_check(struct drm_plane *plane, } static void shmob_drm_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); struct shmob_drm_plane *splane = to_shmob_plane(plane); @@ -207,7 +207,7 @@ static void shmob_drm_plane_atomic_update(struct drm_plane *plane, } static void shmob_drm_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); struct shmob_drm_device *sdev = to_shmob_device(plane->dev); diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index 41ff44eaf44d..06072efd7fca 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -183,7 +183,7 @@ static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder, static struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector *connector; struct drm_connector_state *conn_state; @@ -200,7 +200,7 @@ struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder, } static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rockchip_dp_device *dp = encoder_to_dp(encoder); struct drm_crtc *crtc; @@ -254,7 +254,7 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder, } static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rockchip_dp_device *dp = encoder_to_dp(encoder); struct drm_crtc *crtc; diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c index f39450e12716..190cce9530c8 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c @@ -563,7 +563,7 @@ static void cdn_dp_display_info_update(struct cdn_dp_device *dp, } } -static void cdn_dp_bridge_atomic_enable(struct drm_bridge *bridge, struct drm_atomic_state *state) +static void cdn_dp_bridge_atomic_enable(struct drm_bridge *bridge, struct drm_atomic_commit *state) { struct cdn_dp_device *dp = bridge_to_dp(bridge); struct drm_connector *connector; @@ -630,7 +630,7 @@ static void cdn_dp_bridge_atomic_enable(struct drm_bridge *bridge, struct drm_at mutex_unlock(&dp->lock); } -static void cdn_dp_bridge_atomic_disable(struct drm_bridge *bridge, struct drm_atomic_state *state) +static void cdn_dp_bridge_atomic_disable(struct drm_bridge *bridge, struct drm_atomic_commit *state) { struct cdn_dp_device *dp = bridge_to_dp(bridge); int ret; diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c index 0aea764e29b2..d2e76d36d724 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c @@ -212,7 +212,7 @@ static const struct dw_mipi_dsi2_phy_ops dw_mipi_dsi2_rockchip_phy_ops = { }; static void dw_mipi_dsi2_encoder_atomic_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct dw_mipi_dsi2_rockchip *dsi2 = to_dsi2(encoder); u32 color_depth; diff --git a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c b/drivers/gpu/drm/rockchip/dw_dp-rockchip.c index a9a8bf43aa1d..32bc73a1d5e4 100644 --- a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_dp-rockchip.c @@ -35,7 +35,7 @@ static int dw_dp_encoder_atomic_check(struct drm_encoder *encoder, struct drm_connector_state *conn_state) { struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); - struct drm_atomic_state *state = conn_state->state; + struct drm_atomic_commit *state = conn_state->state; struct drm_display_info *di = &conn_state->connector->display_info; struct drm_bridge *bridge = drm_bridge_chain_get_first_bridge(encoder); struct drm_bridge_state *bridge_state = drm_atomic_get_new_bridge_state(state, bridge); diff --git a/drivers/gpu/drm/rockchip/rk3066_hdmi.c b/drivers/gpu/drm/rockchip/rk3066_hdmi.c index b64cbed26312..1996f8656612 100644 --- a/drivers/gpu/drm/rockchip/rk3066_hdmi.c +++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c @@ -313,7 +313,7 @@ static void rk3066_hdmi_config_phy(struct rk3066_hdmi *hdmi) } static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_bridge *bridge = &hdmi->bridge; struct drm_connector *connector; @@ -394,7 +394,7 @@ static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi, } static void rk3066_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); struct drm_connector_state *conn_state; @@ -424,7 +424,7 @@ static void rk3066_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, } static void rk3066_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 572f4adfd111..0090d8ff0c79 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -728,7 +728,7 @@ static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) } static void vop_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vop *vop = to_vop(crtc); @@ -809,7 +809,7 @@ static bool rockchip_mod_supported(struct drm_plane *plane, } static int vop_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -889,7 +889,7 @@ static int vop_plane_atomic_check(struct drm_plane *plane, } static void vop_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -907,7 +907,7 @@ static void vop_plane_atomic_disable(struct drm_plane *plane, } static void vop_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -1071,7 +1071,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, } static int vop_plane_atomic_async_check(struct drm_plane *plane, - struct drm_atomic_state *state, bool flip) + struct drm_atomic_commit *state, bool flip) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -1105,7 +1105,7 @@ static int vop_plane_atomic_async_check(struct drm_plane *plane, } static void vop_plane_atomic_async_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -1342,7 +1342,7 @@ static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, } static void vop_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -1360,7 +1360,7 @@ static void vop_crtc_atomic_begin(struct drm_crtc *crtc, } static void vop_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -1515,7 +1515,7 @@ static void vop_wait_for_irq_handler(struct vop *vop) } static int vop_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -1562,11 +1562,11 @@ static int vop_crtc_atomic_check(struct drm_crtc *crtc, } static void vop_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); - struct drm_atomic_state *old_state = old_crtc_state->state; + struct drm_atomic_commit *old_state = old_crtc_state->state; struct drm_plane_state *old_plane_state, *new_plane_state; struct vop *vop = to_vop(crtc); struct drm_plane *plane; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 843c7ef979b2..a160077a507f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -923,7 +923,7 @@ static bool vop2_gamma_lut_in_use(struct vop2 *vop2, struct vop2_video_port *vp) } static void vop2_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vop2_video_port *vp = to_vop2_video_port(crtc); struct vop2 *vop2 = vp->vop2; @@ -979,7 +979,7 @@ static void vop2_crtc_atomic_disable(struct drm_crtc *crtc, } static int vop2_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *astate) + struct drm_atomic_commit *astate) { struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane); struct drm_framebuffer *fb = pstate->fb; @@ -1091,7 +1091,7 @@ static int vop2_plane_atomic_check(struct drm_plane *plane, } static void vop2_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_pstate = NULL; struct vop2_win *win = to_vop2_win(plane); @@ -1159,7 +1159,7 @@ static void vop2_plane_setup_color_key(struct drm_plane *plane, u32 color_key) } static void vop2_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *pstate = plane->state; struct drm_crtc *crtc = pstate->crtc; @@ -1622,7 +1622,7 @@ static int us_to_vertical_line(struct drm_display_mode *mode, int us) } static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vop2_video_port *vp = to_vop2_video_port(crtc); struct vop2 *vop2 = vp->vop2; @@ -1814,7 +1814,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, static int vop2_crtc_atomic_check_gamma(struct vop2_video_port *vp, struct drm_crtc *crtc, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_crtc_state *crtc_state) { struct vop2 *vop2 = vp->vop2; @@ -1840,7 +1840,7 @@ static int vop2_crtc_atomic_check_gamma(struct vop2_video_port *vp, } static int vop2_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vop2_video_port *vp = to_vop2_video_port(crtc); struct drm_plane *plane; @@ -1862,7 +1862,7 @@ static int vop2_crtc_atomic_check(struct drm_crtc *crtc, } static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vop2_video_port *vp = to_vop2_video_port(crtc); struct vop2 *vop2 = vp->vop2; @@ -1871,7 +1871,7 @@ static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, } static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); struct vop2_video_port *vp = to_vop2_video_port(crtc); diff --git a/drivers/gpu/drm/sitronix/st7571.c b/drivers/gpu/drm/sitronix/st7571.c index 5fd575d972a2..20954c33eca9 100644 --- a/drivers/gpu/drm/sitronix/st7571.c +++ b/drivers/gpu/drm/sitronix/st7571.c @@ -324,7 +324,7 @@ static const u64 st7571_primary_plane_fmtmods[] = { }; static int st7571_primary_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); struct drm_crtc *new_crtc = new_plane_state->crtc; @@ -340,7 +340,7 @@ static int st7571_primary_plane_helper_atomic_check(struct drm_plane *plane, } static void st7571_primary_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -379,7 +379,7 @@ static void st7571_primary_plane_helper_atomic_update(struct drm_plane *plane, } static void st7571_primary_plane_helper_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = plane->dev; struct st7571_device *st7571 = drm_to_st7571(plane->dev); @@ -437,7 +437,7 @@ static const struct drm_crtc_funcs st7571_crtc_funcs = { */ static void st7571_encoder_atomic_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = encoder->dev; struct st7571_device *st7571 = drm_to_st7571(drm); @@ -452,7 +452,7 @@ static void st7571_encoder_atomic_enable(struct drm_encoder *encoder, } static void st7571_encoder_atomic_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = encoder->dev; struct st7571_device *st7571 = drm_to_st7571(drm); diff --git a/drivers/gpu/drm/sitronix/st7586.c b/drivers/gpu/drm/sitronix/st7586.c index fa58b3d83564..28b2245f6b79 100644 --- a/drivers/gpu/drm/sitronix/st7586.c +++ b/drivers/gpu/drm/sitronix/st7586.c @@ -171,7 +171,7 @@ static const u64 st7586_plane_format_modifiers[] = { }; static void st7586_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = plane->state; struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); @@ -205,7 +205,7 @@ static const struct drm_plane_funcs st7586_plane_funcs = { }; static void st7586_crtc_helper_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct st7586_device *st7586 = to_st7586_device(drm); @@ -276,7 +276,7 @@ static void st7586_crtc_helper_atomic_enable(struct drm_crtc *crtc, } static void st7586_crtc_helper_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct st7586_device *st7586 = to_st7586_device(drm); diff --git a/drivers/gpu/drm/sitronix/st7735r.c b/drivers/gpu/drm/sitronix/st7735r.c index 5a75716ed5ff..bd763871dca0 100644 --- a/drivers/gpu/drm/sitronix/st7735r.c +++ b/drivers/gpu/drm/sitronix/st7735r.c @@ -85,7 +85,7 @@ static const struct drm_plane_funcs st7735r_plane_funcs = { }; static void st7735r_crtc_helper_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct st7735r_device *st7735r = to_st7735r_device(drm); diff --git a/drivers/gpu/drm/sitronix/st7920.c b/drivers/gpu/drm/sitronix/st7920.c index 18fe7a28ed07..d320391801f3 100644 --- a/drivers/gpu/drm/sitronix/st7920.c +++ b/drivers/gpu/drm/sitronix/st7920.c @@ -338,7 +338,7 @@ static int st7920_fb_blit_rect(struct drm_framebuffer *fb, } static int st7920_primary_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = plane->dev; struct st7920_device *st7920 = drm_to_st7920(drm); @@ -387,7 +387,7 @@ static int st7920_primary_plane_atomic_check(struct drm_plane *plane, } static void st7920_primary_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); @@ -429,7 +429,7 @@ static void st7920_primary_plane_atomic_update(struct drm_plane *plane, } static void st7920_primary_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = plane->dev; struct st7920_device *st7920 = drm_to_st7920(drm); @@ -522,7 +522,7 @@ static enum drm_mode_status st7920_crtc_mode_valid(struct drm_crtc *crtc, } static int st7920_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); struct st7920_crtc_state *st7920_state = to_st7920_crtc_state(crtc_state); @@ -540,7 +540,7 @@ static int st7920_crtc_atomic_check(struct drm_crtc *crtc, } static void st7920_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct st7920_device *st7920 = drm_to_st7920(drm); @@ -560,7 +560,7 @@ static void st7920_crtc_atomic_enable(struct drm_crtc *crtc, } static void st7920_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct spi7920_error err = {0}; struct drm_device *drm = crtc->dev; diff --git a/drivers/gpu/drm/solomon/ssd130x.c b/drivers/gpu/drm/solomon/ssd130x.c index c77455b1834d..cae92a3ae8a4 100644 --- a/drivers/gpu/drm/solomon/ssd130x.c +++ b/drivers/gpu/drm/solomon/ssd130x.c @@ -1074,7 +1074,7 @@ static int ssd133x_fb_blit_rect(struct drm_framebuffer *fb, } static int ssd130x_primary_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = plane->dev; struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); @@ -1123,7 +1123,7 @@ static int ssd130x_primary_plane_atomic_check(struct drm_plane *plane, } static int ssd132x_primary_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = plane->dev; struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); @@ -1172,7 +1172,7 @@ static int ssd132x_primary_plane_atomic_check(struct drm_plane *plane, } static int ssd133x_primary_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); struct drm_crtc *crtc = plane_state->crtc; @@ -1195,7 +1195,7 @@ static int ssd133x_primary_plane_atomic_check(struct drm_plane *plane, } static void ssd130x_primary_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); @@ -1236,7 +1236,7 @@ static void ssd130x_primary_plane_atomic_update(struct drm_plane *plane, } static void ssd132x_primary_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); @@ -1277,7 +1277,7 @@ static void ssd132x_primary_plane_atomic_update(struct drm_plane *plane, } static void ssd133x_primary_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); @@ -1316,7 +1316,7 @@ static void ssd133x_primary_plane_atomic_update(struct drm_plane *plane, } static void ssd130x_primary_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = plane->dev; struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); @@ -1340,7 +1340,7 @@ static void ssd130x_primary_plane_atomic_disable(struct drm_plane *plane, } static void ssd132x_primary_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = plane->dev; struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); @@ -1364,7 +1364,7 @@ static void ssd132x_primary_plane_atomic_disable(struct drm_plane *plane, } static void ssd133x_primary_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = plane->dev; struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); @@ -1476,7 +1476,7 @@ static enum drm_mode_status ssd130x_crtc_mode_valid(struct drm_crtc *crtc, } static int ssd130x_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); @@ -1497,7 +1497,7 @@ static int ssd130x_crtc_atomic_check(struct drm_crtc *crtc, } static int ssd132x_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); @@ -1518,7 +1518,7 @@ static int ssd132x_crtc_atomic_check(struct drm_crtc *crtc, } static int ssd133x_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); @@ -1621,7 +1621,7 @@ static const struct drm_crtc_funcs ssd130x_crtc_funcs = { }; static void ssd130x_encoder_atomic_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = encoder->dev; struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); @@ -1647,7 +1647,7 @@ static void ssd130x_encoder_atomic_enable(struct drm_encoder *encoder, } static void ssd132x_encoder_atomic_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = encoder->dev; struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); @@ -1672,7 +1672,7 @@ static void ssd132x_encoder_atomic_enable(struct drm_encoder *encoder, } static void ssd133x_encoder_atomic_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = encoder->dev; struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); @@ -1697,7 +1697,7 @@ static void ssd133x_encoder_atomic_enable(struct drm_encoder *encoder, } static void ssd130x_encoder_atomic_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = encoder->dev; struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); diff --git a/drivers/gpu/drm/sprd/sprd_dpu.c b/drivers/gpu/drm/sprd/sprd_dpu.c index a3447622a33c..66990398b903 100644 --- a/drivers/gpu/drm/sprd/sprd_dpu.c +++ b/drivers/gpu/drm/sprd/sprd_dpu.c @@ -501,7 +501,7 @@ void sprd_dpu_stop(struct sprd_dpu *dpu) } static int sprd_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -526,7 +526,7 @@ static int sprd_plane_atomic_check(struct drm_plane *plane, } static void sprd_plane_atomic_update(struct drm_plane *drm_plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, drm_plane); @@ -537,7 +537,7 @@ static void sprd_plane_atomic_update(struct drm_plane *drm_plane, } static void sprd_plane_atomic_disable(struct drm_plane *drm_plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, drm_plane); @@ -636,7 +636,7 @@ static void sprd_crtc_mode_set_nofb(struct drm_crtc *crtc) } static void sprd_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sprd_dpu *dpu = to_sprd_crtc(crtc); @@ -646,7 +646,7 @@ static void sprd_crtc_atomic_enable(struct drm_crtc *crtc, } static void sprd_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sprd_dpu *dpu = to_sprd_crtc(crtc); struct drm_device *drm = dpu->base.dev; @@ -664,7 +664,7 @@ static void sprd_crtc_atomic_disable(struct drm_crtc *crtc, } static void sprd_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sprd_dpu *dpu = to_sprd_crtc(crtc); diff --git a/drivers/gpu/drm/sti/sti_crtc.c b/drivers/gpu/drm/sti/sti_crtc.c index 3c7154f2d5f3..f0e98653d35a 100644 --- a/drivers/gpu/drm/sti/sti_crtc.c +++ b/drivers/gpu/drm/sti/sti_crtc.c @@ -22,7 +22,7 @@ #include "sti_vtg.h" static void sti_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sti_mixer *mixer = to_sti_mixer(crtc); @@ -34,7 +34,7 @@ static void sti_crtc_atomic_enable(struct drm_crtc *crtc, } static void sti_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sti_mixer *mixer = to_sti_mixer(crtc); @@ -132,7 +132,7 @@ sti_crtc_mode_set_nofb(struct drm_crtc *crtc) } static void sti_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm_dev = crtc->dev; struct sti_mixer *mixer = to_sti_mixer(crtc); diff --git a/drivers/gpu/drm/sti/sti_cursor.c b/drivers/gpu/drm/sti/sti_cursor.c index 4e12a465be7f..d0b89b28e50c 100644 --- a/drivers/gpu/drm/sti/sti_cursor.c +++ b/drivers/gpu/drm/sti/sti_cursor.c @@ -183,7 +183,7 @@ static void sti_cursor_init(struct sti_cursor *cursor) } static int sti_cursor_atomic_check(struct drm_plane *drm_plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, drm_plane); @@ -261,7 +261,7 @@ static int sti_cursor_atomic_check(struct drm_plane *drm_plane, } static void sti_cursor_atomic_update(struct drm_plane *drm_plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, drm_plane); @@ -316,7 +316,7 @@ static void sti_cursor_atomic_update(struct drm_plane *drm_plane, } static void sti_cursor_atomic_disable(struct drm_plane *drm_plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, drm_plane); diff --git a/drivers/gpu/drm/sti/sti_gdp.c b/drivers/gpu/drm/sti/sti_gdp.c index 1e5aa8c30645..9a17b590aa3d 100644 --- a/drivers/gpu/drm/sti/sti_gdp.c +++ b/drivers/gpu/drm/sti/sti_gdp.c @@ -618,7 +618,7 @@ static int sti_gdp_get_dst(struct device *dev, int dst, int src) } static int sti_gdp_atomic_check(struct drm_plane *drm_plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, drm_plane); @@ -705,7 +705,7 @@ static int sti_gdp_atomic_check(struct drm_plane *drm_plane, } static void sti_gdp_atomic_update(struct drm_plane *drm_plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, drm_plane); @@ -873,7 +873,7 @@ static void sti_gdp_atomic_update(struct drm_plane *drm_plane, } static void sti_gdp_atomic_disable(struct drm_plane *drm_plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, drm_plane); diff --git a/drivers/gpu/drm/sti/sti_hqvdp.c b/drivers/gpu/drm/sti/sti_hqvdp.c index 57ef4ba3554e..cf1ed8a33b8e 100644 --- a/drivers/gpu/drm/sti/sti_hqvdp.c +++ b/drivers/gpu/drm/sti/sti_hqvdp.c @@ -1020,7 +1020,7 @@ static void sti_hqvdp_start_xp70(struct sti_hqvdp *hqvdp) } static int sti_hqvdp_atomic_check(struct drm_plane *drm_plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, drm_plane); @@ -1115,7 +1115,7 @@ static int sti_hqvdp_atomic_check(struct drm_plane *drm_plane, } static void sti_hqvdp_atomic_update(struct drm_plane *drm_plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, drm_plane); @@ -1249,7 +1249,7 @@ static void sti_hqvdp_atomic_update(struct drm_plane *drm_plane, } static void sti_hqvdp_atomic_disable(struct drm_plane *drm_plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, drm_plane); diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c index 56d53ac3082d..144b7cda989a 100644 --- a/drivers/gpu/drm/stm/drv.c +++ b/drivers/gpu/drm/stm/drv.c @@ -126,7 +126,7 @@ static __maybe_unused int drv_suspend(struct device *dev) { struct drm_device *ddev = dev_get_drvdata(dev); struct ltdc_device *ldev = ddev->dev_private; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; WARN_ON(ldev->suspend_state); diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index f7e847cfa38f..95fcfa48d8be 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -773,7 +773,7 @@ static void ltdc_crtc_update_clut(struct drm_crtc *crtc) } static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ltdc_device *ldev = crtc_to_ltdc(crtc); struct drm_device *ddev = crtc->dev; @@ -796,7 +796,7 @@ static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, } static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ltdc_device *ldev = crtc_to_ltdc(crtc); struct drm_device *ddev = crtc->dev; @@ -1037,7 +1037,7 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) } static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ltdc_device *ldev = crtc_to_ltdc(crtc); struct drm_device *ddev = crtc->dev; @@ -1236,7 +1236,7 @@ static const struct drm_crtc_funcs ltdc_crtc_with_crc_support_funcs = { */ static int ltdc_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -1263,7 +1263,7 @@ static int ltdc_plane_atomic_check(struct drm_plane *plane, } static void ltdc_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ltdc_device *ldev = plane_to_ltdc(plane); struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, @@ -1509,7 +1509,7 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane, } static void ltdc_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, plane); diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index 17b51a7ce28e..452352e645d7 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -58,7 +58,7 @@ struct ltdc_device { u32 fifo_threshold; /* fifo underrun threshold */ u32 transfer_err; /* transfer error counter */ struct fps_info plane_fpsi[LTDC_MAX_LAYER]; - struct drm_atomic_state *suspend_state; + struct drm_atomic_commit *suspend_state; int crc_skip_count; bool crc_active; }; diff --git a/drivers/gpu/drm/stm/lvds.c b/drivers/gpu/drm/stm/lvds.c index 25e2ba98f36a..50a878688e47 100644 --- a/drivers/gpu/drm/stm/lvds.c +++ b/drivers/gpu/drm/stm/lvds.c @@ -887,7 +887,7 @@ static int lvds_connector_get_modes(struct drm_connector *connector) } static int lvds_connector_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { const struct drm_display_mode *panel_mode; struct drm_connector_state *conn_state; @@ -981,7 +981,7 @@ static int lvds_attach(struct drm_bridge *bridge, struct drm_encoder *encoder, } static void lvds_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct stm_lvds *lvds = bridge_to_stm_lvds(bridge); struct drm_connector_state *conn_state; @@ -1017,7 +1017,7 @@ static void lvds_atomic_enable(struct drm_bridge *bridge, } static void lvds_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct stm_lvds *lvds = bridge_to_stm_lvds(bridge); diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c index bc35dad53b07..03e46a2af646 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.c +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c @@ -72,7 +72,7 @@ static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine) static void sun4i_backend_commit(struct sunxi_engine *engine, struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { DRM_DEBUG_DRIVER("Committing changes\n"); @@ -472,7 +472,7 @@ static int sun4i_backend_atomic_check(struct sunxi_engine *engine, { struct drm_plane_state *plane_states[SUN4I_BACKEND_NUM_LAYERS] = { 0 }; struct sun4i_backend *backend = engine_to_sun4i_backend(engine); - struct drm_atomic_state *state = crtc_state->state; + struct drm_atomic_commit *state = crtc_state->state; struct drm_device *drm = state->dev; struct drm_plane *plane; unsigned int num_planes = 0; diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c b/drivers/gpu/drm/sun4i/sun4i_crtc.c index 18e74047b0f5..c2f7f69baf75 100644 --- a/drivers/gpu/drm/sun4i/sun4i_crtc.c +++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c @@ -46,7 +46,7 @@ static struct drm_encoder *sun4i_crtc_get_encoder(struct drm_crtc *crtc) } static int sun4i_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -61,7 +61,7 @@ static int sun4i_crtc_atomic_check(struct drm_crtc *crtc, } static void sun4i_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -84,7 +84,7 @@ static void sun4i_crtc_atomic_begin(struct drm_crtc *crtc, } static void sun4i_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc); struct drm_pending_vblank_event *event = crtc->state->event; @@ -106,7 +106,7 @@ static void sun4i_crtc_atomic_flush(struct drm_crtc *crtc, } static void sun4i_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc); struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc); @@ -127,7 +127,7 @@ static void sun4i_crtc_atomic_disable(struct drm_crtc *crtc, } static void sun4i_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc); struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc); diff --git a/drivers/gpu/drm/sun4i/sun4i_framebuffer.c b/drivers/gpu/drm/sun4i/sun4i_framebuffer.c index 260136d60ceb..9c8ef927d929 100644 --- a/drivers/gpu/drm/sun4i/sun4i_framebuffer.c +++ b/drivers/gpu/drm/sun4i/sun4i_framebuffer.c @@ -15,7 +15,7 @@ #include "sun4i_framebuffer.h" static int sun4i_de_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { int ret; diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c index dd2a78defdb4..07e2afcb4f95 100644 --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c @@ -76,7 +76,7 @@ static int sun4i_hdmi_write_hdmi_infoframe(struct drm_connector *connector, } static void sun4i_hdmi_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); u32 val; @@ -91,7 +91,7 @@ static void sun4i_hdmi_disable(struct drm_encoder *encoder, } static void sun4i_hdmi_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c index 63cb8c7c3636..d65587d96d9e 100644 --- a/drivers/gpu/drm/sun4i/sun4i_layer.c +++ b/drivers/gpu/drm/sun4i/sun4i_layer.c @@ -61,7 +61,7 @@ static void sun4i_backend_layer_destroy_state(struct drm_plane *plane, } static void sun4i_backend_layer_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -81,7 +81,7 @@ static void sun4i_backend_layer_atomic_disable(struct drm_plane *plane, } static void sun4i_backend_layer_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c index cce4e38789b9..814b77f278f6 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tv.c +++ b/drivers/gpu/drm/sun4i/sun4i_tv.c @@ -261,7 +261,7 @@ sun4i_tv_find_tv_by_mode(unsigned int mode) } static void sun4i_tv_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder); struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc); @@ -276,7 +276,7 @@ static void sun4i_tv_disable(struct drm_encoder *encoder, } static void sun4i_tv_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder); struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc); diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c index 4071ab38b4ae..4e4226295010 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -253,7 +253,7 @@ int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format) static void sun8i_mixer_commit(struct sunxi_engine *engine, struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine); u32 bld_base = sun8i_blender_base(mixer); diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c index 72c92203ae63..00756ab78b4e 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -146,7 +146,7 @@ static void sun8i_ui_layer_update_buffer(struct sun8i_layer *layer, } static int sun8i_ui_layer_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -187,7 +187,7 @@ static int sun8i_ui_layer_atomic_check(struct drm_plane *plane, static void sun8i_ui_layer_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c index cd8d6c2da0c7..09f668c8af24 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -226,7 +226,7 @@ static void sun8i_vi_layer_update_buffer(struct sun8i_layer *layer, } static int sun8i_vi_layer_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -266,7 +266,7 @@ static int sun8i_vi_layer_atomic_check(struct drm_plane *plane, } static void sun8i_vi_layer_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/sun4i/sunxi_engine.h b/drivers/gpu/drm/sun4i/sunxi_engine.h index c9461de06cd0..1711c274a41b 100644 --- a/drivers/gpu/drm/sun4i/sunxi_engine.h +++ b/drivers/gpu/drm/sun4i/sunxi_engine.h @@ -62,7 +62,7 @@ struct sunxi_engine_ops { */ void (*commit)(struct sunxi_engine *engine, struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @layers_init: @@ -153,7 +153,7 @@ struct sunxi_engine { static inline void sunxi_engine_commit(struct sunxi_engine *engine, struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { if (engine->ops && engine->ops->commit) engine->ops->commit(engine, crtc, state); diff --git a/drivers/gpu/drm/sysfb/drm_sysfb_helper.h b/drivers/gpu/drm/sysfb/drm_sysfb_helper.h index b14df5b54bc9..2a2b553366fb 100644 --- a/drivers/gpu/drm/sysfb/drm_sysfb_helper.h +++ b/drivers/gpu/drm/sysfb/drm_sysfb_helper.h @@ -111,11 +111,11 @@ size_t drm_sysfb_build_fourcc_list(struct drm_device *dev, int drm_sysfb_plane_helper_begin_fb_access(struct drm_plane *plane, struct drm_plane_state *plane_state); int drm_sysfb_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *new_state); + struct drm_atomic_commit *new_state); void drm_sysfb_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_sysfb_plane_helper_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); int drm_sysfb_plane_helper_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer *sb); @@ -165,7 +165,7 @@ to_drm_sysfb_crtc_state(struct drm_crtc_state *base) enum drm_mode_status drm_sysfb_crtc_helper_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode); -int drm_sysfb_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state); +int drm_sysfb_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *new_state); #define DRM_SYSFB_CRTC_HELPER_FUNCS \ .mode_valid = drm_sysfb_crtc_helper_mode_valid, \ diff --git a/drivers/gpu/drm/sysfb/drm_sysfb_modeset.c b/drivers/gpu/drm/sysfb/drm_sysfb_modeset.c index 808b1eda871a..d2de29caf89e 100644 --- a/drivers/gpu/drm/sysfb/drm_sysfb_modeset.c +++ b/drivers/gpu/drm/sysfb/drm_sysfb_modeset.c @@ -283,7 +283,7 @@ int drm_sysfb_plane_helper_begin_fb_access(struct drm_plane *plane, EXPORT_SYMBOL(drm_sysfb_plane_helper_begin_fb_access); int drm_sysfb_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *new_state) + struct drm_atomic_commit *new_state) { struct drm_sysfb_device *sysfb = to_drm_sysfb_device(plane->dev); struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(new_state, plane); @@ -326,7 +326,7 @@ int drm_sysfb_plane_helper_atomic_check(struct drm_plane *plane, } EXPORT_SYMBOL(drm_sysfb_plane_helper_atomic_check); -void drm_sysfb_plane_helper_atomic_update(struct drm_plane *plane, struct drm_atomic_state *state) +void drm_sysfb_plane_helper_atomic_update(struct drm_plane *plane, struct drm_atomic_commit *state) { struct drm_device *dev = plane->dev; struct drm_sysfb_device *sysfb = to_drm_sysfb_device(dev); @@ -371,7 +371,7 @@ void drm_sysfb_plane_helper_atomic_update(struct drm_plane *plane, struct drm_at EXPORT_SYMBOL(drm_sysfb_plane_helper_atomic_update); void drm_sysfb_plane_helper_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = plane->dev; struct drm_sysfb_device *sysfb = to_drm_sysfb_device(dev); @@ -486,7 +486,7 @@ enum drm_mode_status drm_sysfb_crtc_helper_mode_valid(struct drm_crtc *crtc, } EXPORT_SYMBOL(drm_sysfb_crtc_helper_mode_valid); -int drm_sysfb_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state) +int drm_sysfb_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *new_state) { struct drm_device *dev = crtc->dev; struct drm_sysfb_device *sysfb = to_drm_sysfb_device(dev); diff --git a/drivers/gpu/drm/sysfb/ofdrm.c b/drivers/gpu/drm/sysfb/ofdrm.c index 8822ebcbc081..819aed466727 100644 --- a/drivers/gpu/drm/sysfb/ofdrm.c +++ b/drivers/gpu/drm/sysfb/ofdrm.c @@ -352,6 +352,7 @@ static void ofdrm_pci_release(void *data) struct pci_dev *pcidev = data; pci_disable_device(pcidev); + pci_dev_put(pcidev); } static int ofdrm_device_init_pci(struct ofdrm_device *odev) @@ -377,6 +378,7 @@ static int ofdrm_device_init_pci(struct ofdrm_device *odev) if (ret) { drm_err(dev, "pci_enable_device(%s) failed: %d\n", dev_name(&pcidev->dev), ret); + pci_dev_put(pcidev); return ret; } ret = devm_add_action_or_reset(&pdev->dev, ofdrm_pci_release, pcidev); @@ -725,7 +727,7 @@ static const struct drm_plane_funcs ofdrm_primary_plane_funcs = { .destroy = drm_plane_cleanup, }; -static void ofdrm_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state) +static void ofdrm_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct ofdrm_device *odev = ofdrm_device_of_dev(crtc->dev); struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/sysfb/vesadrm.c b/drivers/gpu/drm/sysfb/vesadrm.c index 255b90a200b0..dbc317778d54 100644 --- a/drivers/gpu/drm/sysfb/vesadrm.c +++ b/drivers/gpu/drm/sysfb/vesadrm.c @@ -248,7 +248,7 @@ static const u64 vesadrm_primary_plane_format_modifiers[] = { }; static int vesadrm_primary_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *new_state) + struct drm_atomic_commit *new_state) { struct drm_sysfb_device *sysfb = to_drm_sysfb_device(plane->dev); struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(new_state, plane); @@ -317,7 +317,7 @@ static const struct drm_plane_funcs vesadrm_primary_plane_funcs = { }; static void vesadrm_crtc_helper_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = crtc->dev; struct drm_sysfb_device *sysfb = to_drm_sysfb_device(dev); diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 06370b7e0e56..de683644d658 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -616,7 +616,7 @@ static const u64 tegra124_modifiers[] = { }; static int tegra_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -708,7 +708,7 @@ static int tegra_plane_atomic_check(struct drm_plane *plane, } static void tegra_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -725,7 +725,7 @@ static void tegra_plane_atomic_disable(struct drm_plane *plane, } static void tegra_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -864,7 +864,7 @@ static const u32 tegra_cursor_plane_formats[] = { }; static int tegra_cursor_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -1000,7 +1000,7 @@ static void __tegra_cursor_atomic_update(struct drm_plane *plane, } static void tegra_cursor_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -1008,7 +1008,7 @@ static void tegra_cursor_atomic_update(struct drm_plane *plane, } static void tegra_cursor_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -1026,7 +1026,7 @@ static void tegra_cursor_atomic_disable(struct drm_plane *plane, tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); } -static int tegra_cursor_atomic_async_check(struct drm_plane *plane, struct drm_atomic_state *state, +static int tegra_cursor_atomic_async_check(struct drm_plane *plane, struct drm_atomic_commit *state, bool flip) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -1065,7 +1065,7 @@ static int tegra_cursor_atomic_async_check(struct drm_plane *plane, struct drm_a } static void tegra_cursor_atomic_async_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); struct tegra_dc *dc = to_tegra_dc(new_state->crtc); @@ -1998,7 +1998,7 @@ static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) static void tegra_crtc_update_memory_bandwidth(struct drm_crtc *crtc, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, bool prepare_bandwidth_transition) { const struct tegra_plane_state *old_tegra_state, *new_tegra_state; @@ -2094,7 +2094,7 @@ tegra_crtc_update_memory_bandwidth(struct drm_crtc *crtc, } static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tegra_dc *dc = to_tegra_dc(crtc); u32 value; @@ -2158,7 +2158,7 @@ static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, } static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_display_mode *mode = &crtc->state->adjusted_mode; struct tegra_dc_state *crtc_state = to_dc_state(crtc->state); @@ -2289,7 +2289,7 @@ static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, } static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { unsigned long flags; @@ -2310,7 +2310,7 @@ static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, } static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -2390,7 +2390,7 @@ tegra_plane_overlap_mask(struct drm_crtc_state *state, } static int tegra_crtc_calculate_memory_bandwidth(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { ulong overlap_mask[TEGRA_DC_LEGACY_PLANES_NUM] = {}, mask; u32 plane_peak_bw[TEGRA_DC_LEGACY_PLANES_NUM] = {}; @@ -2502,7 +2502,7 @@ static int tegra_crtc_calculate_memory_bandwidth(struct drm_crtc *crtc, } static int tegra_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { int err; @@ -2514,7 +2514,7 @@ static int tegra_crtc_atomic_check(struct drm_crtc *crtc, } void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { /* * Display bandwidth is allowed to go down only once hardware state diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 0559fa6b1bf7..577c2e8e3ab3 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -165,7 +165,7 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc, struct clk *clk, unsigned long pclk, unsigned int div); void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /* from rgb.c */ int tegra_dc_rgb_probe(struct tegra_dc *dc); diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 1dcef4e7d104..dd6c564ff408 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -44,7 +44,7 @@ #define CDMA_GATHER_FETCHES_MAX_NB 16383 static int tegra_atomic_check(struct drm_device *drm, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { int err; @@ -62,7 +62,7 @@ static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = { }; static void tegra_atomic_post_commit(struct drm_device *drm, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct drm_crtc_state *old_crtc_state __maybe_unused; struct drm_crtc *crtc; @@ -72,7 +72,7 @@ static void tegra_atomic_post_commit(struct drm_device *drm, tegra_crtc_atomic_post_commit(crtc, old_state); } -static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state) +static void tegra_atomic_commit_tail(struct drm_atomic_commit *old_state) { struct drm_device *drm = old_state->dev; struct tegra_drm *tegra = drm->dev_private; diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c index 10d993b8d043..bd442bfd4540 100644 --- a/drivers/gpu/drm/tegra/hub.c +++ b/drivers/gpu/drm/tegra/hub.c @@ -424,7 +424,7 @@ static void tegra_dc_remove_shared_plane(struct tegra_dc *dc, } static int tegra_shared_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -482,7 +482,7 @@ static int tegra_shared_plane_atomic_check(struct drm_plane *plane, } static void tegra_shared_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -532,7 +532,7 @@ static inline u32 compute_phase_incr(fixed20_12 in, unsigned int out) } static void tegra_shared_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -847,7 +847,7 @@ static const struct drm_private_state_funcs tegra_display_hub_state_funcs = { static struct tegra_display_hub_state * tegra_display_hub_get_state(struct tegra_display_hub *hub, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_private_state *priv; @@ -859,7 +859,7 @@ tegra_display_hub_get_state(struct tegra_display_hub *hub, } int tegra_display_hub_atomic_check(struct drm_device *drm, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tegra_drm *tegra = drm->dev_private; struct tegra_display_hub_state *hub_state; @@ -925,7 +925,7 @@ static void tegra_display_hub_update(struct tegra_dc *dc) } void tegra_display_hub_atomic_commit(struct drm_device *drm, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tegra_drm *tegra = drm->dev_private; struct tegra_display_hub *hub = tegra->hub; diff --git a/drivers/gpu/drm/tegra/hub.h b/drivers/gpu/drm/tegra/hub.h index a66f18c4facc..9f3a108f6b59 100644 --- a/drivers/gpu/drm/tegra/hub.h +++ b/drivers/gpu/drm/tegra/hub.h @@ -84,9 +84,9 @@ struct drm_plane *tegra_shared_plane_create(struct drm_device *drm, enum drm_plane_type type); int tegra_display_hub_atomic_check(struct drm_device *drm, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void tegra_display_hub_atomic_commit(struct drm_device *drm, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); #define DC_CMD_IHUB_COMMON_MISC_CTL 0x068 #define LATENCY_EVENT (1 << 3) diff --git a/drivers/gpu/drm/tests/Makefile b/drivers/gpu/drm/tests/Makefile index d2e2e3d8349a..3b83e6616fb2 100644 --- a/drivers/gpu/drm/tests/Makefile +++ b/drivers/gpu/drm/tests/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_DRM_KUNIT_TEST_HELPERS) += \ obj-$(CONFIG_DRM_KUNIT_TEST) += \ drm_atomic_test.o \ - drm_atomic_state_test.o \ + drm_atomic_commit_test.o \ drm_bridge_test.o \ drm_cmdline_parser_test.o \ drm_connector_test.o \ diff --git a/drivers/gpu/drm/tests/drm_atomic_state_test.c b/drivers/gpu/drm/tests/drm_atomic_commit_test.c similarity index 98% rename from drivers/gpu/drm/tests/drm_atomic_state_test.c rename to drivers/gpu/drm/tests/drm_atomic_commit_test.c index bc27f65b2823..ff69bade19b8 100644 --- a/drivers/gpu/drm/tests/drm_atomic_state_test.c +++ b/drivers/gpu/drm/tests/drm_atomic_commit_test.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Test cases for the drm_atomic_state helpers + * Test cases for the drm_atomic_commit helpers * * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ @@ -146,7 +146,7 @@ static int set_up_atomic_state(struct kunit *test, { struct drm_device *drm = &priv->drm; struct drm_crtc *crtc = priv->crtc; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_connector_state *conn_state; struct drm_crtc_state *crtc_state; int ret; @@ -196,7 +196,7 @@ static void drm_test_check_connector_changed_modeset(struct kunit *test) struct drm_atomic_test_priv *priv; struct drm_modeset_acquire_ctx ctx; struct drm_connector *old_conn, *new_conn; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_device *drm; struct drm_connector_state *new_conn_state, *old_conn_state; int ret, initial_modeset_count; @@ -278,7 +278,7 @@ static void drm_test_check_valid_clones(struct kunit *test) struct drm_atomic_test_priv *priv; struct drm_modeset_acquire_ctx ctx; struct drm_device *drm; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_crtc_state *crtc_state; priv = drm_atomic_test_init_drm_components(test, false); @@ -303,7 +303,7 @@ static void drm_test_check_valid_clones(struct kunit *test) retry: crtc_state = drm_atomic_get_crtc_state(state, priv->crtc); if (PTR_ERR(crtc_state) == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry; @@ -317,7 +317,7 @@ static void drm_test_check_valid_clones(struct kunit *test) ret = drm_atomic_helper_check_modeset(drm, state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry; diff --git a/drivers/gpu/drm/tests/drm_bridge_test.c b/drivers/gpu/drm/tests/drm_bridge_test.c index dbba06a486f0..64b665580a88 100644 --- a/drivers/gpu/drm/tests/drm_bridge_test.c +++ b/drivers/gpu/drm/tests/drm_bridge_test.c @@ -71,7 +71,7 @@ static const struct drm_bridge_funcs drm_test_bridge_legacy_funcs = { }; static void drm_test_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_bridge_priv *priv = bridge_to_priv(bridge); @@ -79,7 +79,7 @@ static void drm_test_bridge_atomic_enable(struct drm_bridge *bridge, } static void drm_test_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_bridge_priv *priv = bridge_to_priv(bridge); @@ -188,7 +188,7 @@ static void drm_test_drm_bridge_get_current_state_atomic(struct kunit *test) struct drm_bridge_init_priv *priv; struct drm_bridge_state *curr_bridge_state; struct drm_bridge_state *bridge_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_bridge *bridge; struct drm_device *drm; int ret; @@ -209,7 +209,7 @@ static void drm_test_drm_bridge_get_current_state_atomic(struct kunit *test) ret = drm_atomic_commit(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); drm_modeset_backoff(&ctx); goto retry_commit; } diff --git a/drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c b/drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c index a4357efaa983..c9819c3fc635 100644 --- a/drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c +++ b/drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c @@ -179,7 +179,7 @@ static const struct drm_connector_funcs dummy_connector_funcs = { }; static void test_encoder_atomic_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_atomic_helper_connector_hdmi_priv *priv = encoder_to_priv(encoder); @@ -292,7 +292,7 @@ static void drm_test_check_broadcast_rgb_crtc_mode_changed(struct kunit *test) struct drm_connector_state *old_conn_state; struct drm_connector_state *new_conn_state; struct drm_crtc_state *crtc_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_display_mode *preferred; struct drm_connector *conn; struct drm_device *drm; @@ -367,7 +367,7 @@ static void drm_test_check_broadcast_rgb_crtc_mode_not_changed(struct kunit *tes struct drm_connector_state *old_conn_state; struct drm_connector_state *new_conn_state; struct drm_crtc_state *crtc_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_display_mode *preferred; struct drm_connector *conn; struct drm_device *drm; @@ -442,7 +442,7 @@ static void drm_test_check_broadcast_rgb_auto_cea_mode(struct kunit *test) struct drm_atomic_helper_connector_hdmi_priv *priv; struct drm_modeset_acquire_ctx ctx; struct drm_connector_state *conn_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_display_mode *preferred; struct drm_connector *conn; struct drm_device *drm; @@ -509,7 +509,7 @@ static void drm_test_check_broadcast_rgb_auto_cea_mode_vic_1(struct kunit *test) struct drm_atomic_helper_connector_hdmi_priv *priv; struct drm_modeset_acquire_ctx ctx; struct drm_connector_state *conn_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_display_mode *mode; struct drm_connector *conn; struct drm_device *drm; @@ -576,7 +576,7 @@ static void drm_test_check_broadcast_rgb_full_cea_mode(struct kunit *test) struct drm_atomic_helper_connector_hdmi_priv *priv; struct drm_modeset_acquire_ctx ctx; struct drm_connector_state *conn_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_display_mode *preferred; struct drm_connector *conn; struct drm_device *drm; @@ -645,7 +645,7 @@ static void drm_test_check_broadcast_rgb_full_cea_mode_vic_1(struct kunit *test) struct drm_atomic_helper_connector_hdmi_priv *priv; struct drm_modeset_acquire_ctx ctx; struct drm_connector_state *conn_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_display_mode *mode; struct drm_connector *conn; struct drm_device *drm; @@ -714,7 +714,7 @@ static void drm_test_check_broadcast_rgb_limited_cea_mode(struct kunit *test) struct drm_atomic_helper_connector_hdmi_priv *priv; struct drm_modeset_acquire_ctx ctx; struct drm_connector_state *conn_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_display_mode *preferred; struct drm_connector *conn; struct drm_device *drm; @@ -783,7 +783,7 @@ static void drm_test_check_broadcast_rgb_limited_cea_mode_vic_1(struct kunit *te struct drm_atomic_helper_connector_hdmi_priv *priv; struct drm_modeset_acquire_ctx ctx; struct drm_connector_state *conn_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_display_mode *mode; struct drm_connector *conn; struct drm_device *drm; @@ -853,7 +853,7 @@ static void drm_test_check_broadcast_rgb_cea_mode_yuv420(struct kunit *test) enum drm_hdmi_broadcast_rgb broadcast_rgb; struct drm_modeset_acquire_ctx ctx; struct drm_connector_state *conn_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_display_mode *mode; struct drm_connector *conn; struct drm_device *drm; @@ -896,7 +896,7 @@ static void drm_test_check_broadcast_rgb_cea_mode_yuv420(struct kunit *test) retry_conn_state: conn_state = drm_atomic_get_connector_state(state, conn); if (PTR_ERR(conn_state) == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_conn_state; @@ -907,7 +907,7 @@ static void drm_test_check_broadcast_rgb_cea_mode_yuv420(struct kunit *test) ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_conn_state; @@ -955,7 +955,7 @@ static void drm_test_check_output_bpc_crtc_mode_changed(struct kunit *test) struct drm_connector_state *old_conn_state; struct drm_connector_state *new_conn_state; struct drm_crtc_state *crtc_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_display_mode *preferred; struct drm_connector *conn; struct drm_device *drm; @@ -1037,7 +1037,7 @@ static void drm_test_check_output_bpc_crtc_mode_not_changed(struct kunit *test) struct drm_connector_state *old_conn_state; struct drm_connector_state *new_conn_state; struct drm_crtc_state *crtc_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_display_mode *preferred; struct drm_connector *conn; struct drm_device *drm; @@ -1339,7 +1339,7 @@ static void drm_test_check_hdmi_funcs_reject_rate(struct kunit *test) { struct drm_atomic_helper_connector_hdmi_priv *priv; struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_display_mode *preferred; struct drm_crtc_state *crtc_state; struct drm_connector *conn; @@ -1706,7 +1706,7 @@ static void drm_test_check_driver_unsupported_fallback_yuv420(struct kunit *test struct drm_modeset_acquire_ctx ctx; struct drm_connector_state *conn_state; struct drm_crtc_state *crtc_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_display_info *info; struct drm_display_mode *preferred, *yuv420_only_mode; struct drm_connector *conn; @@ -1758,7 +1758,7 @@ static void drm_test_check_driver_unsupported_fallback_yuv420(struct kunit *test retry_crtc_state: crtc_state = drm_atomic_get_crtc_state(state, crtc); if (PTR_ERR(crtc_state) == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_crtc_state; @@ -1770,7 +1770,7 @@ static void drm_test_check_driver_unsupported_fallback_yuv420(struct kunit *test ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_crtc_state; @@ -2142,7 +2142,7 @@ static void drm_test_check_disable_connector(struct kunit *test) struct drm_modeset_acquire_ctx ctx; struct drm_connector_state *conn_state; struct drm_crtc_state *crtc_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_display_mode *preferred; struct drm_connector *conn; struct drm_device *drm; @@ -2531,7 +2531,7 @@ static void drm_test_check_infoframes(struct kunit *test) struct drm_atomic_helper_connector_hdmi_priv *priv; struct drm_modeset_acquire_ctx ctx; struct drm_crtc_state *crtc_state; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_display_mode *preferred; struct drm_connector *conn; struct drm_device *drm; @@ -2573,7 +2573,7 @@ static void drm_test_check_infoframes(struct kunit *test) retry_crtc_state: crtc_state = drm_atomic_get_crtc_state(state, crtc); if (PTR_ERR(crtc_state) == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_crtc_state; @@ -2586,7 +2586,7 @@ static void drm_test_check_infoframes(struct kunit *test) ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_crtc_state; @@ -2595,7 +2595,7 @@ static void drm_test_check_infoframes(struct kunit *test) ret = drm_atomic_commit(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_crtc_state; @@ -2633,7 +2633,7 @@ static void drm_test_check_reject_avi_infoframe(struct kunit *test) { struct drm_atomic_helper_connector_hdmi_priv *priv; struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_crtc_state *crtc_state; struct drm_display_mode *preferred; struct drm_connector *conn; @@ -2678,7 +2678,7 @@ static void drm_test_check_reject_avi_infoframe(struct kunit *test) retry_crtc_state: crtc_state = drm_atomic_get_crtc_state(state, crtc); if (PTR_ERR(crtc_state) == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_crtc_state; @@ -2691,7 +2691,7 @@ static void drm_test_check_reject_avi_infoframe(struct kunit *test) ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_crtc_state; @@ -2700,7 +2700,7 @@ static void drm_test_check_reject_avi_infoframe(struct kunit *test) ret = drm_atomic_commit(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_crtc_state; @@ -2736,7 +2736,7 @@ static void drm_test_check_reject_hdr_infoframe_bpc_8(struct kunit *test) { struct drm_atomic_helper_connector_hdmi_priv *priv; struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_connector_state *new_conn_state; struct drm_crtc_state *crtc_state; struct drm_display_mode *preferred; @@ -2782,7 +2782,7 @@ static void drm_test_check_reject_hdr_infoframe_bpc_8(struct kunit *test) retry_conn_state: new_conn_state = drm_atomic_get_connector_state(state, conn); if (PTR_ERR(new_conn_state) == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_conn_state; @@ -2791,7 +2791,7 @@ static void drm_test_check_reject_hdr_infoframe_bpc_8(struct kunit *test) crtc_state = drm_atomic_get_crtc_state(state, crtc); if (PTR_ERR(crtc_state) == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_conn_state; @@ -2810,7 +2810,7 @@ static void drm_test_check_reject_hdr_infoframe_bpc_8(struct kunit *test) ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_conn_state; @@ -2819,7 +2819,7 @@ static void drm_test_check_reject_hdr_infoframe_bpc_8(struct kunit *test) ret = drm_atomic_commit(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_conn_state; @@ -2847,7 +2847,7 @@ static void drm_test_check_reject_hdr_infoframe_bpc_10(struct kunit *test) { struct drm_atomic_helper_connector_hdmi_priv *priv; struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_connector_state *new_conn_state; struct drm_crtc_state *crtc_state; struct drm_display_mode *preferred; @@ -2896,7 +2896,7 @@ static void drm_test_check_reject_hdr_infoframe_bpc_10(struct kunit *test) retry_conn_state: new_conn_state = drm_atomic_get_connector_state(state, conn); if (PTR_ERR(new_conn_state) == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_conn_state; @@ -2905,7 +2905,7 @@ static void drm_test_check_reject_hdr_infoframe_bpc_10(struct kunit *test) crtc_state = drm_atomic_get_crtc_state(state, crtc); if (PTR_ERR(crtc_state) == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_conn_state; @@ -2933,7 +2933,7 @@ static void drm_test_check_reject_hdr_infoframe_bpc_10(struct kunit *test) ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_conn_state; @@ -2942,7 +2942,7 @@ static void drm_test_check_reject_hdr_infoframe_bpc_10(struct kunit *test) ret = drm_atomic_commit(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_conn_state; @@ -2985,7 +2985,7 @@ static void drm_test_check_reject_audio_infoframe(struct kunit *test) { struct drm_atomic_helper_connector_hdmi_priv *priv; struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_crtc_state *crtc_state; struct drm_display_mode *preferred; struct drm_connector *conn; @@ -3031,7 +3031,7 @@ static void drm_test_check_reject_audio_infoframe(struct kunit *test) retry_crtc_state: crtc_state = drm_atomic_get_crtc_state(state, crtc); if (PTR_ERR(crtc_state) == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_crtc_state; @@ -3044,7 +3044,7 @@ static void drm_test_check_reject_audio_infoframe(struct kunit *test) ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_crtc_state; @@ -3053,7 +3053,7 @@ static void drm_test_check_reject_audio_infoframe(struct kunit *test) ret = drm_atomic_commit(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_crtc_state; @@ -3082,7 +3082,7 @@ static void drm_test_check_reject_audio_infoframe(struct kunit *test) retry_crtc_state_2: crtc_state = drm_atomic_get_crtc_state(state, crtc); if (PTR_ERR(crtc_state) == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_crtc_state_2; @@ -3095,7 +3095,7 @@ static void drm_test_check_reject_audio_infoframe(struct kunit *test) ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_crtc_state_2; @@ -3104,7 +3104,7 @@ static void drm_test_check_reject_audio_infoframe(struct kunit *test) ret = drm_atomic_commit(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_crtc_state_2; diff --git a/drivers/gpu/drm/tests/drm_kunit_helpers.c b/drivers/gpu/drm/tests/drm_kunit_helpers.c index 04edb6079c0d..727766444d63 100644 --- a/drivers/gpu/drm/tests/drm_kunit_helpers.c +++ b/drivers/gpu/drm/tests/drm_kunit_helpers.c @@ -82,11 +82,11 @@ __drm_kunit_helper_alloc_drm_device_with_driver(struct kunit *test, } EXPORT_SYMBOL_GPL(__drm_kunit_helper_alloc_drm_device_with_driver); -static void kunit_action_drm_atomic_state_put(void *ptr) +static void kunit_action_drm_atomic_commit_put(void *ptr) { - struct drm_atomic_state *state = ptr; + struct drm_atomic_commit *state = ptr; - drm_atomic_state_put(state); + drm_atomic_commit_put(state); } /** @@ -98,25 +98,25 @@ static void kunit_action_drm_atomic_state_put(void *ptr) * Allocates a empty atomic state. * * The state is tied to the kunit test context, so we must not call - * drm_atomic_state_put() on it, it will be done so automatically. + * drm_atomic_commit_put() on it, it will be done so automatically. * * Returns: * An ERR_PTR on error, a pointer to the newly allocated state otherwise */ -struct drm_atomic_state * +struct drm_atomic_commit * drm_kunit_helper_atomic_state_alloc(struct kunit *test, struct drm_device *drm, struct drm_modeset_acquire_ctx *ctx) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; int ret; - state = drm_atomic_state_alloc(drm); + state = drm_atomic_commit_alloc(drm); if (!state) return ERR_PTR(-ENOMEM); ret = kunit_add_action_or_reset(test, - kunit_action_drm_atomic_state_put, + kunit_action_drm_atomic_commit_put, state); if (ret) return ERR_PTR(ret); @@ -297,7 +297,7 @@ int drm_kunit_helper_enable_crtc_connector(struct kunit *test, const struct drm_display_mode *mode, struct drm_modeset_acquire_ctx *ctx) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_connector_state *conn_state; struct drm_crtc_state *crtc_state; int ret; diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c index a31c21c5f855..acab9307bdf3 100644 --- a/drivers/gpu/drm/tidss/tidss_crtc.c +++ b/drivers/gpu/drm/tidss/tidss_crtc.c @@ -83,7 +83,7 @@ void tidss_crtc_error_irq(struct drm_crtc *crtc, u64 irqstatus) /* drm_crtc_helper_funcs */ static int tidss_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -123,7 +123,7 @@ static void tidss_crtc_position_planes(struct tidss_device *tidss, struct drm_crtc_state *old_state, bool newmodeset) { - struct drm_atomic_state *ostate = old_state->state; + struct drm_atomic_commit *ostate = old_state->state; struct tidss_crtc *tcrtc = to_tidss_crtc(crtc); struct drm_crtc_state *cstate = crtc->state; int layer; @@ -162,7 +162,7 @@ static void tidss_crtc_position_planes(struct tidss_device *tidss, } static void tidss_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -211,7 +211,7 @@ static void tidss_crtc_atomic_flush(struct drm_crtc *crtc, } static void tidss_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -260,7 +260,7 @@ static void tidss_crtc_atomic_enable(struct drm_crtc *crtc, } static void tidss_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tidss_crtc *tcrtc = to_tidss_crtc(crtc); struct drm_device *ddev = crtc->dev; diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c index b4779c09a1bf..1512ee2574b6 100644 --- a/drivers/gpu/drm/tidss/tidss_kms.c +++ b/drivers/gpu/drm/tidss/tidss_kms.c @@ -19,7 +19,7 @@ #include "tidss_kms.h" #include "tidss_plane.h" -static void tidss_atomic_commit_tail(struct drm_atomic_state *old_state) +static void tidss_atomic_commit_tail(struct drm_atomic_commit *old_state) { struct drm_device *ddev = old_state->dev; struct tidss_device *tidss = to_tidss(ddev); @@ -67,7 +67,7 @@ static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = { }; static int tidss_atomic_check(struct drm_device *ddev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *opstate; struct drm_plane_state *npstate; diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tidss_oldi.c index 17c535bfa057..9c9725aac829 100644 --- a/drivers/gpu/drm/tidss/tidss_oldi.c +++ b/drivers/gpu/drm/tidss/tidss_oldi.c @@ -221,7 +221,7 @@ static int tidss_oldi_config(struct tidss_oldi *oldi) } static void tidss_oldi_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge); struct drm_connector *connector; @@ -258,7 +258,7 @@ static void tidss_oldi_atomic_pre_enable(struct drm_bridge *bridge, } static void tidss_oldi_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge); diff --git a/drivers/gpu/drm/tidss/tidss_plane.c b/drivers/gpu/drm/tidss/tidss_plane.c index aaa02c851c59..1a8b44fb45f8 100644 --- a/drivers/gpu/drm/tidss/tidss_plane.c +++ b/drivers/gpu/drm/tidss/tidss_plane.c @@ -29,7 +29,7 @@ void tidss_plane_error_irq(struct drm_plane *plane, u64 irqstatus) /* drm_plane_helper_funcs */ static int tidss_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -113,7 +113,7 @@ static int tidss_plane_atomic_check(struct drm_plane *plane, } static void tidss_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *ddev = plane->dev; struct tidss_device *tidss = to_tidss(ddev); @@ -133,7 +133,7 @@ static void tidss_plane_atomic_update(struct drm_plane *plane, } static void tidss_plane_atomic_enable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *ddev = plane->dev; struct tidss_device *tidss = to_tidss(ddev); @@ -143,7 +143,7 @@ static void tidss_plane_atomic_enable(struct drm_plane *plane, } static void tidss_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *ddev = plane->dev; struct tidss_device *tidss = to_tidss(ddev); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c index e5fd1e74de91..e07ecb36a27a 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -453,7 +453,7 @@ static void tilcdc_crtc_enable(struct drm_crtc *crtc) } static void tilcdc_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { tilcdc_crtc_enable(crtc); } @@ -510,13 +510,13 @@ static void tilcdc_crtc_disable(struct drm_crtc *crtc) } static void tilcdc_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { tilcdc_crtc_disable(crtc); } static void tilcdc_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { if (!crtc->state->event) return; @@ -632,7 +632,7 @@ static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, } static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c index c877b2be9c2e..e7f675c15c20 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -49,7 +49,7 @@ static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888 }; static int tilcdc_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { int ret; diff --git a/drivers/gpu/drm/tilcdc/tilcdc_plane.c b/drivers/gpu/drm/tilcdc/tilcdc_plane.c index a9982a995690..d2678af5dc22 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_plane.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_plane.c @@ -20,7 +20,7 @@ static const struct drm_plane_funcs tilcdc_plane_funcs = { }; static int tilcdc_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -74,7 +74,7 @@ static int tilcdc_plane_atomic_check(struct drm_plane *plane, } static void tilcdc_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/tiny/appletbdrm.c b/drivers/gpu/drm/tiny/appletbdrm.c index 3bae91d7eefe..cdd35af49892 100644 --- a/drivers/gpu/drm/tiny/appletbdrm.c +++ b/drivers/gpu/drm/tiny/appletbdrm.c @@ -316,7 +316,7 @@ static const u32 appletbdrm_primary_plane_formats[] = { }; static int appletbdrm_primary_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); @@ -353,7 +353,7 @@ static int appletbdrm_primary_plane_helper_atomic_check(struct drm_plane *plane, frames_size + sizeof(struct appletbdrm_fb_request_footer), 16); - appletbdrm_state->request = kzalloc(request_size, GFP_KERNEL); + appletbdrm_state->request = kvzalloc(request_size, GFP_KERNEL); if (!appletbdrm_state->request) return -ENOMEM; @@ -468,7 +468,7 @@ static int appletbdrm_flush_damage(struct appletbdrm_device *adev, } static void appletbdrm_primary_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct appletbdrm_device *adev = drm_to_adev(plane->dev); struct drm_device *drm = plane->dev; @@ -485,7 +485,7 @@ static void appletbdrm_primary_plane_helper_atomic_update(struct drm_plane *plan } static void appletbdrm_primary_plane_helper_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = plane->dev; struct appletbdrm_device *adev = drm_to_adev(dev); @@ -543,7 +543,7 @@ static void appletbdrm_primary_plane_destroy_state(struct drm_plane *plane, { struct appletbdrm_plane_state *appletbdrm_state = to_appletbdrm_plane_state(state); - kfree(appletbdrm_state->request); + kvfree(appletbdrm_state->request); kfree(appletbdrm_state->response); __drm_gem_destroy_shadow_plane_state(&appletbdrm_state->base); diff --git a/drivers/gpu/drm/tiny/bochs.c b/drivers/gpu/drm/tiny/bochs.c index 222e4ae1abbd..376465b79b06 100644 --- a/drivers/gpu/drm/tiny/bochs.c +++ b/drivers/gpu/drm/tiny/bochs.c @@ -419,7 +419,7 @@ static const uint32_t bochs_primary_plane_formats[] = { }; static int bochs_primary_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); struct drm_crtc *new_crtc = new_plane_state->crtc; @@ -442,7 +442,7 @@ static int bochs_primary_plane_helper_atomic_check(struct drm_plane *plane, } static void bochs_primary_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = plane->dev; struct bochs_device *bochs = to_bochs_device(dev); @@ -513,7 +513,7 @@ static void bochs_crtc_helper_mode_set_nofb(struct drm_crtc *crtc) } static int bochs_crtc_helper_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -524,7 +524,7 @@ static int bochs_crtc_helper_atomic_check(struct drm_crtc *crtc, } static void bochs_crtc_helper_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct bochs_device *bochs = to_bochs_device(crtc->dev); @@ -533,7 +533,7 @@ static void bochs_crtc_helper_atomic_enable(struct drm_crtc *crtc, } static void bochs_crtc_helper_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *crtc_state) + struct drm_atomic_commit *crtc_state) { struct bochs_device *bochs = to_bochs_device(crtc->dev); diff --git a/drivers/gpu/drm/tiny/cirrus-qemu.c b/drivers/gpu/drm/tiny/cirrus-qemu.c index 9ba0eab489bb..075221b431d3 100644 --- a/drivers/gpu/drm/tiny/cirrus-qemu.c +++ b/drivers/gpu/drm/tiny/cirrus-qemu.c @@ -296,7 +296,7 @@ static const uint64_t cirrus_primary_plane_format_modifiers[] = { }; static int cirrus_primary_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); struct drm_framebuffer *fb = new_plane_state->fb; @@ -326,7 +326,7 @@ static int cirrus_primary_plane_helper_atomic_check(struct drm_plane *plane, } static void cirrus_primary_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct cirrus_device *cirrus = to_cirrus(plane->dev); struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -374,7 +374,7 @@ static const struct drm_plane_funcs cirrus_primary_plane_funcs = { DRM_GEM_SHADOW_PLANE_FUNCS, }; -static int cirrus_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) +static int cirrus_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); int ret; @@ -390,7 +390,7 @@ static int cirrus_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_ato } static void cirrus_crtc_helper_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct cirrus_device *cirrus = to_cirrus(crtc->dev); struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/tiny/hx8357d.c b/drivers/gpu/drm/tiny/hx8357d.c index 53b152fc6b04..f942a8d09ff2 100644 --- a/drivers/gpu/drm/tiny/hx8357d.c +++ b/drivers/gpu/drm/tiny/hx8357d.c @@ -78,7 +78,7 @@ static const struct drm_plane_funcs hx8357d_plane_funcs = { }; static void hx8357d_crtc_helper_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct hx8357d_device *hx8357d = to_hx8357d_device(drm); diff --git a/drivers/gpu/drm/tiny/ili9163.c b/drivers/gpu/drm/tiny/ili9163.c index 1e581576fc7e..8842424504e3 100644 --- a/drivers/gpu/drm/tiny/ili9163.c +++ b/drivers/gpu/drm/tiny/ili9163.c @@ -67,7 +67,7 @@ static const struct drm_plane_funcs ili9163_plane_funcs = { }; static void ili9163_crtc_helper_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct ili9163_device *ili9163 = to_ili9163_device(drm); diff --git a/drivers/gpu/drm/tiny/ili9225.c b/drivers/gpu/drm/tiny/ili9225.c index 0371527002f9..5bf52a8fd75b 100644 --- a/drivers/gpu/drm/tiny/ili9225.c +++ b/drivers/gpu/drm/tiny/ili9225.c @@ -179,7 +179,7 @@ static const u64 ili9225_plane_format_modifiers[] = { }; static void ili9225_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = plane->dev; struct drm_plane_state *plane_state = plane->state; @@ -214,7 +214,7 @@ static const struct drm_plane_funcs ili9225_plane_funcs = { }; static void ili9225_crtc_helper_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct ili9225_device *ili9225 = to_ili9225_device(drm); @@ -316,7 +316,7 @@ static void ili9225_crtc_helper_atomic_enable(struct drm_crtc *crtc, } static void ili9225_crtc_helper_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct ili9225_device *ili9225 = to_ili9225_device(drm); diff --git a/drivers/gpu/drm/tiny/ili9341.c b/drivers/gpu/drm/tiny/ili9341.c index e623bd8a1827..003381aa22ea 100644 --- a/drivers/gpu/drm/tiny/ili9341.c +++ b/drivers/gpu/drm/tiny/ili9341.c @@ -84,7 +84,7 @@ static const struct drm_plane_funcs ili9341_plane_funcs = { }; static void ili9341_crtc_helper_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct ili9341_device *ili9341 = to_ili9341_device(drm); diff --git a/drivers/gpu/drm/tiny/ili9486.c b/drivers/gpu/drm/tiny/ili9486.c index 030e87a8a3f0..c945a9144315 100644 --- a/drivers/gpu/drm/tiny/ili9486.c +++ b/drivers/gpu/drm/tiny/ili9486.c @@ -126,7 +126,7 @@ static const struct drm_plane_funcs ili9486_plane_funcs = { }; static void ili9486_crtc_helper_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct ili9486_device *ili9486 = to_ili9486_device(drm); diff --git a/drivers/gpu/drm/tiny/mi0283qt.c b/drivers/gpu/drm/tiny/mi0283qt.c index ee597d023390..b0121e89e2dc 100644 --- a/drivers/gpu/drm/tiny/mi0283qt.c +++ b/drivers/gpu/drm/tiny/mi0283qt.c @@ -82,7 +82,7 @@ static const struct drm_plane_funcs mi0283qt_plane_funcs = { }; static void mi0283qt_crtc_helper_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct mi0283qt_device *mi0283qt = to_mi0283qt_device(drm); diff --git a/drivers/gpu/drm/tiny/panel-mipi-dbi.c b/drivers/gpu/drm/tiny/panel-mipi-dbi.c index 581e14528608..60cd65cae41d 100644 --- a/drivers/gpu/drm/tiny/panel-mipi-dbi.c +++ b/drivers/gpu/drm/tiny/panel-mipi-dbi.c @@ -261,7 +261,7 @@ static const struct drm_plane_funcs panel_mipi_dbi_plane_funcs = { }; static void panel_mipi_dbi_crtc_helper_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = crtc->dev; struct panel_mipi_dbi_device *panel_mipi_dbi = to_panel_mipi_dbi_device(drm); diff --git a/drivers/gpu/drm/tiny/pixpaper.c b/drivers/gpu/drm/tiny/pixpaper.c index df3ec42edd57..d02ac26d007c 100644 --- a/drivers/gpu/drm/tiny/pixpaper.c +++ b/drivers/gpu/drm/tiny/pixpaper.c @@ -774,7 +774,7 @@ static u8 pack_pixels_to_byte(__le32 *src_pixels, int i, int j, } static int pixpaper_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -797,7 +797,7 @@ static int pixpaper_plane_helper_atomic_check(struct drm_plane *plane, } static int pixpaper_crtc_helper_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -809,7 +809,7 @@ static int pixpaper_crtc_helper_atomic_check(struct drm_crtc *crtc, } static void pixpaper_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct pixpaper_panel *panel = to_pixpaper_panel(crtc->dev); struct drm_device *drm = &panel->drm; @@ -834,7 +834,7 @@ static void pixpaper_crtc_atomic_enable(struct drm_crtc *crtc, } static void pixpaper_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct pixpaper_panel *panel = to_pixpaper_panel(crtc->dev); struct drm_device *drm = &panel->drm; @@ -858,7 +858,7 @@ static void pixpaper_crtc_atomic_disable(struct drm_crtc *crtc, } static void pixpaper_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/tiny/sharp-memory.c b/drivers/gpu/drm/tiny/sharp-memory.c index cbf69460ebf3..506e6432e70d 100644 --- a/drivers/gpu/drm/tiny/sharp-memory.c +++ b/drivers/gpu/drm/tiny/sharp-memory.c @@ -223,7 +223,7 @@ static void sharp_memory_fb_dirty(struct drm_framebuffer *fb, const struct iosys } static int sharp_memory_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); struct sharp_memory_device *smd; @@ -239,7 +239,7 @@ static int sharp_memory_plane_atomic_check(struct drm_plane *plane, } static void sharp_memory_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); struct drm_plane_state *plane_state = plane->state; @@ -287,7 +287,7 @@ static enum drm_mode_status sharp_memory_crtc_mode_valid(struct drm_crtc *crtc, } static int sharp_memory_crtc_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); int ret; @@ -317,7 +317,7 @@ static int sharp_memory_sw_vcom_signal_thread(void *data) } static void sharp_memory_crtc_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sharp_memory_device *smd = drm_to_sharp_memory_device(crtc->dev); @@ -328,7 +328,7 @@ static void sharp_memory_crtc_enable(struct drm_crtc *crtc, } static void sharp_memory_crtc_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct sharp_memory_device *smd = drm_to_sharp_memory_device(crtc->dev); diff --git a/drivers/gpu/drm/udl/udl_main.c b/drivers/gpu/drm/udl/udl_main.c index 08a0e9480d70..17950fe3a0ec 100644 --- a/drivers/gpu/drm/udl/udl_main.c +++ b/drivers/gpu/drm/udl/udl_main.c @@ -285,13 +285,12 @@ static struct urb *udl_get_urb_locked(struct udl_device *udl, long timeout) return unode->urb; } -#define GET_URB_TIMEOUT HZ struct urb *udl_get_urb(struct udl_device *udl) { struct urb *urb; spin_lock_irq(&udl->urbs.lock); - urb = udl_get_urb_locked(udl, GET_URB_TIMEOUT); + urb = udl_get_urb_locked(udl, HZ * 2); spin_unlock_irq(&udl->urbs.lock); return urb; } diff --git a/drivers/gpu/drm/udl/udl_modeset.c b/drivers/gpu/drm/udl/udl_modeset.c index 231e829bd709..289711035b67 100644 --- a/drivers/gpu/drm/udl/udl_modeset.c +++ b/drivers/gpu/drm/udl/udl_modeset.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -263,7 +264,7 @@ static const uint64_t udl_primary_plane_fmtmods[] = { }; static int udl_primary_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); struct drm_crtc *new_crtc = new_plane_state->crtc; @@ -279,7 +280,7 @@ static int udl_primary_plane_helper_atomic_check(struct drm_plane *plane, } static void udl_primary_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = plane->dev; struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -328,7 +329,7 @@ static const struct drm_plane_funcs udl_primary_plane_funcs = { * CRTC */ -static void udl_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) +static void udl_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct drm_device *dev = crtc->dev; struct udl_device *udl = to_udl(dev); @@ -342,8 +343,10 @@ static void udl_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atom return; urb = udl_get_urb(udl); - if (!urb) + if (!urb) { + drm_err_ratelimited(dev, "get urb failed when enabling crtc\n"); goto out; + } buf = (char *)urb->transfer_buffer; buf = udl_vidreg_lock(buf); @@ -363,7 +366,7 @@ static void udl_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atom drm_dev_exit(idx); } -static void udl_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state) +static void udl_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct drm_device *dev = crtc->dev; struct udl_device *udl = to_udl(dev); diff --git a/drivers/gpu/drm/vboxvideo/vbox_mode.c b/drivers/gpu/drm/vboxvideo/vbox_mode.c index 9c11a6b945ff..8e4e5fc9d3c5 100644 --- a/drivers/gpu/drm/vboxvideo/vbox_mode.c +++ b/drivers/gpu/drm/vboxvideo/vbox_mode.c @@ -219,17 +219,17 @@ static void vbox_crtc_set_base_and_mode(struct drm_crtc *crtc, } static void vbox_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { } static void vbox_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { } static void vbox_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { } @@ -256,7 +256,7 @@ static const struct drm_crtc_funcs vbox_crtc_funcs = { }; static int vbox_primary_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -276,7 +276,7 @@ static int vbox_primary_atomic_check(struct drm_plane *plane, } static void vbox_primary_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -322,7 +322,7 @@ static void vbox_primary_atomic_update(struct drm_plane *plane, } static void vbox_primary_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -335,7 +335,7 @@ static void vbox_primary_atomic_disable(struct drm_plane *plane, } static int vbox_cursor_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -387,7 +387,7 @@ static void copy_cursor_image(u8 *src, u8 *dst, u32 width, u32 height, } static void vbox_cursor_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -438,7 +438,7 @@ static void vbox_cursor_atomic_update(struct drm_plane *plane, } static void vbox_cursor_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); diff --git a/drivers/gpu/drm/vc4/tests/vc4_mock.h b/drivers/gpu/drm/vc4/tests/vc4_mock.h index 002b6218960c..3cc4b4a0feed 100644 --- a/drivers/gpu/drm/vc4/tests/vc4_mock.h +++ b/drivers/gpu/drm/vc4/tests/vc4_mock.h @@ -52,10 +52,10 @@ struct vc4_dev *vc4_mock_device(struct kunit *test); struct vc4_dev *vc5_mock_device(struct kunit *test); int vc4_mock_atomic_add_output(struct kunit *test, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, enum vc4_encoder_type type); int vc4_mock_atomic_del_output(struct kunit *test, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, enum vc4_encoder_type type); #endif // VC4_MOCK_H_ diff --git a/drivers/gpu/drm/vc4/tests/vc4_mock_output.c b/drivers/gpu/drm/vc4/tests/vc4_mock_output.c index 577d9a956369..b53c3635ce67 100644 --- a/drivers/gpu/drm/vc4/tests/vc4_mock_output.c +++ b/drivers/gpu/drm/vc4/tests/vc4_mock_output.c @@ -75,7 +75,7 @@ static const struct drm_display_mode default_mode = { * errors are fatal. */ int vc4_mock_atomic_add_output(struct kunit *test, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, enum vc4_encoder_type type) { struct drm_device *drm = state->dev; @@ -132,7 +132,7 @@ int vc4_mock_atomic_add_output(struct kunit *test, * errors are fatal. */ int vc4_mock_atomic_del_output(struct kunit *test, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, enum vc4_encoder_type type) { struct drm_device *drm = state->dev; diff --git a/drivers/gpu/drm/vc4/tests/vc4_test_pv_muxing.c b/drivers/gpu/drm/vc4/tests/vc4_test_pv_muxing.c index d1f694029169..7a54f46acff9 100644 --- a/drivers/gpu/drm/vc4/tests/vc4_test_pv_muxing.c +++ b/drivers/gpu/drm/vc4/tests/vc4_test_pv_muxing.c @@ -23,7 +23,7 @@ struct pv_muxing_priv { }; static bool check_fifo_conflict(struct kunit *test, - const struct drm_atomic_state *state) + const struct drm_atomic_commit *state) { struct vc4_hvs_state *hvs_state; unsigned int used_fifos = 0; @@ -119,7 +119,7 @@ static bool check_vc5_encoder_constraints(enum vc4_encoder_type type, unsigned i static struct vc4_crtc_state * get_vc4_crtc_state_for_encoder(struct kunit *test, - const struct drm_atomic_state *state, + const struct drm_atomic_commit *state, enum vc4_encoder_type type) { struct drm_device *drm = state->dev; @@ -141,7 +141,7 @@ get_vc4_crtc_state_for_encoder(struct kunit *test, } static bool check_channel_for_encoder(struct kunit *test, - const struct drm_atomic_state *state, + const struct drm_atomic_commit *state, enum vc4_encoder_type type, bool (*check_fn)(enum vc4_encoder_type type, unsigned int channel)) { @@ -677,7 +677,7 @@ static void drm_vc4_test_pv_muxing(struct kunit *test) const struct pv_muxing_param *params = test->param_value; const struct pv_muxing_priv *priv = test->priv; struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_device *drm; struct vc4_dev *vc4; unsigned int i; @@ -696,7 +696,7 @@ static void drm_vc4_test_pv_muxing(struct kunit *test) ret = vc4_mock_atomic_add_output(test, state, enc_type); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry; @@ -706,7 +706,7 @@ static void drm_vc4_test_pv_muxing(struct kunit *test) ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry; @@ -732,7 +732,7 @@ static void drm_vc4_test_pv_muxing_invalid(struct kunit *test) const struct pv_muxing_param *params = test->param_value; const struct pv_muxing_priv *priv = test->priv; struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_device *drm; struct vc4_dev *vc4; unsigned int i; @@ -752,7 +752,7 @@ static void drm_vc4_test_pv_muxing_invalid(struct kunit *test) ret = vc4_mock_atomic_add_output(test, state, enc_type); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry; @@ -762,7 +762,7 @@ static void drm_vc4_test_pv_muxing_invalid(struct kunit *test) ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry; @@ -826,7 +826,7 @@ static struct kunit_suite vc5_pv_muxing_test_suite = { static void drm_test_vc5_pv_muxing_bugs_subsequent_crtc_enable(struct kunit *test) { struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct vc4_crtc_state *new_vc4_crtc_state; struct vc4_hvs_state *new_hvs_state; unsigned int hdmi0_channel; @@ -847,7 +847,7 @@ static void drm_test_vc5_pv_muxing_bugs_subsequent_crtc_enable(struct kunit *tes ret = vc4_mock_atomic_add_output(test, state, VC4_ENCODER_TYPE_HDMI0); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_first; @@ -856,7 +856,7 @@ static void drm_test_vc5_pv_muxing_bugs_subsequent_crtc_enable(struct kunit *tes ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_first; @@ -883,7 +883,7 @@ static void drm_test_vc5_pv_muxing_bugs_subsequent_crtc_enable(struct kunit *tes ret = vc4_mock_atomic_add_output(test, state, VC4_ENCODER_TYPE_HDMI1); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_second; @@ -892,7 +892,7 @@ static void drm_test_vc5_pv_muxing_bugs_subsequent_crtc_enable(struct kunit *tes ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_second; @@ -926,7 +926,7 @@ static void drm_test_vc5_pv_muxing_bugs_subsequent_crtc_enable(struct kunit *tes static void drm_test_vc5_pv_muxing_bugs_stable_fifo(struct kunit *test) { struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct vc4_crtc_state *new_vc4_crtc_state; struct vc4_hvs_state *new_hvs_state; unsigned int old_hdmi0_channel; @@ -947,7 +947,7 @@ static void drm_test_vc5_pv_muxing_bugs_stable_fifo(struct kunit *test) ret = vc4_mock_atomic_add_output(test, state, VC4_ENCODER_TYPE_HDMI0); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_first; @@ -956,7 +956,7 @@ static void drm_test_vc5_pv_muxing_bugs_stable_fifo(struct kunit *test) ret = vc4_mock_atomic_add_output(test, state, VC4_ENCODER_TYPE_HDMI1); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_first; @@ -965,7 +965,7 @@ static void drm_test_vc5_pv_muxing_bugs_stable_fifo(struct kunit *test) ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_first; @@ -1000,7 +1000,7 @@ static void drm_test_vc5_pv_muxing_bugs_stable_fifo(struct kunit *test) ret = vc4_mock_atomic_del_output(test, state, VC4_ENCODER_TYPE_HDMI0); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_second; @@ -1009,7 +1009,7 @@ static void drm_test_vc5_pv_muxing_bugs_stable_fifo(struct kunit *test) ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_second; @@ -1055,7 +1055,7 @@ static void drm_test_vc5_pv_muxing_bugs_subsequent_crtc_enable_too_many_crtc_state(struct kunit *test) { struct drm_modeset_acquire_ctx ctx; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct vc4_crtc_state *new_vc4_crtc_state; struct drm_device *drm; struct vc4_dev *vc4; @@ -1073,7 +1073,7 @@ drm_test_vc5_pv_muxing_bugs_subsequent_crtc_enable_too_many_crtc_state(struct ku ret = vc4_mock_atomic_add_output(test, state, VC4_ENCODER_TYPE_HDMI0); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_first; @@ -1082,7 +1082,7 @@ drm_test_vc5_pv_muxing_bugs_subsequent_crtc_enable_too_many_crtc_state(struct ku ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_first; @@ -1097,7 +1097,7 @@ drm_test_vc5_pv_muxing_bugs_subsequent_crtc_enable_too_many_crtc_state(struct ku ret = vc4_mock_atomic_add_output(test, state, VC4_ENCODER_TYPE_HDMI1); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_second; @@ -1106,7 +1106,7 @@ drm_test_vc5_pv_muxing_bugs_subsequent_crtc_enable_too_many_crtc_state(struct ku ret = drm_atomic_check_only(state); if (ret == -EDEADLK) { - drm_atomic_state_clear(state); + drm_atomic_commit_clear(state); ret = drm_modeset_backoff(&ctx); if (!ret) goto retry_second; diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 4a606986afcc..4572b0b9bae1 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -343,7 +343,7 @@ static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc) } static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = crtc->dev; struct vc4_dev *vc4 = to_vc4_dev(dev); @@ -497,7 +497,7 @@ static void require_hvs_enabled(struct drm_device *dev) static int vc4_crtc_disable(struct drm_crtc *crtc, struct drm_encoder *encoder, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, unsigned int channel) { struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); @@ -622,7 +622,7 @@ void vc4_crtc_send_vblank(struct drm_crtc *crtc) } static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -648,7 +648,7 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, } static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -740,7 +740,7 @@ void vc4_crtc_get_margins(struct drm_crtc_state *state, } int vc4_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index dbcc83b7df00..0f5958c1e6b6 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -375,9 +375,9 @@ struct vc4_hvs_state { #define to_vc4_hvs_state(_state) \ container_of_const(_state, struct vc4_hvs_state, base) -struct vc4_hvs_state *vc4_hvs_get_global_state(struct drm_atomic_state *state); -struct vc4_hvs_state *vc4_hvs_get_old_global_state(const struct drm_atomic_state *state); -struct vc4_hvs_state *vc4_hvs_get_new_global_state(const struct drm_atomic_state *state); +struct vc4_hvs_state *vc4_hvs_get_global_state(struct drm_atomic_commit *state); +struct vc4_hvs_state *vc4_hvs_get_old_global_state(const struct drm_atomic_commit *state); +struct vc4_hvs_state *vc4_hvs_get_new_global_state(const struct drm_atomic_commit *state); struct vc4_plane { struct drm_plane base; @@ -478,12 +478,12 @@ struct vc4_encoder { enum vc4_encoder_type type; u32 clock_select; - void (*pre_crtc_configure)(struct drm_encoder *encoder, struct drm_atomic_state *state); - void (*pre_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_state *state); - void (*post_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_state *state); + void (*pre_crtc_configure)(struct drm_encoder *encoder, struct drm_atomic_commit *state); + void (*pre_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_commit *state); + void (*post_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_commit *state); - void (*post_crtc_disable)(struct drm_encoder *encoder, struct drm_atomic_state *state); - void (*post_crtc_powerdown)(struct drm_encoder *encoder, struct drm_atomic_state *state); + void (*post_crtc_disable)(struct drm_encoder *encoder, struct drm_atomic_commit *state); + void (*post_crtc_powerdown)(struct drm_encoder *encoder, struct drm_atomic_commit *state); }; #define to_vc4_encoder(_encoder) \ @@ -945,7 +945,7 @@ int vc4_page_flip(struct drm_crtc *crtc, uint32_t flags, struct drm_modeset_acquire_ctx *ctx); int vc4_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc); void vc4_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state); @@ -1025,11 +1025,11 @@ struct vc4_hvs *__vc4_hvs_alloc(struct vc4_dev *vc4, void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int output); int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output); u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo); -int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state); -void vc4_hvs_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state); -void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state); -void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state); -void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state); +int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *state); +void vc4_hvs_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_commit *state); +void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_commit *state); +void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_commit *state); +void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_commit *state); void vc4_hvs_dump_state(struct vc4_hvs *hvs); void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel); void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel); diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c index deeeaebc702f..fc76018b044c 100644 --- a/drivers/gpu/drm/vc4/vc4_dsi.c +++ b/drivers/gpu/drm/vc4/vc4_dsi.c @@ -799,7 +799,7 @@ dsi_esc_timing(u32 ns) } static void vc4_dsi_bridge_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); u32 disp0_ctrl; @@ -810,7 +810,7 @@ static void vc4_dsi_bridge_disable(struct drm_bridge *bridge, } static void vc4_dsi_bridge_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); struct device *dev = &dsi->pdev->dev; @@ -872,7 +872,7 @@ static bool vc4_dsi_bridge_mode_fixup(struct drm_bridge *bridge, } static void vc4_dsi_bridge_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); const struct drm_crtc_state *crtc_state; @@ -1141,7 +1141,7 @@ static void vc4_dsi_bridge_pre_enable(struct drm_bridge *bridge, } static void vc4_dsi_bridge_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); bool debug_dump_regs = false; diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index a99f53dadb28..a161d3b00a25 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -455,7 +455,7 @@ static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) } static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *old_state = drm_atomic_get_old_connector_state(state, connector); @@ -877,7 +877,7 @@ static void vc4_hdmi_scrambling_wq(struct work_struct *work) } static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); struct drm_device *drm = vc4_hdmi->connector.dev; @@ -927,7 +927,7 @@ static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, } static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); struct drm_device *drm = vc4_hdmi->connector.dev; @@ -1471,7 +1471,7 @@ static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) } static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); struct drm_device *drm = vc4_hdmi->connector.dev; @@ -1587,7 +1587,7 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, } static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); struct drm_device *drm = vc4_hdmi->connector.dev; @@ -1617,7 +1617,7 @@ static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, } static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); struct drm_connector *connector = &vc4_hdmi->connector; diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c index ee8d0738501b..184d51ea3fa5 100644 --- a/drivers/gpu/drm/vc4/vc4_hvs.c +++ b/drivers/gpu/drm/vc4/vc4_hvs.c @@ -787,7 +787,7 @@ void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan) __vc4_hvs_stop_channel(hvs, chan); } -int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) +int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); @@ -882,7 +882,7 @@ static void vc4_hvs_update_dlist(struct drm_crtc *crtc) } void vc4_hvs_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); @@ -894,7 +894,7 @@ void vc4_hvs_atomic_begin(struct drm_crtc *crtc, } void vc4_hvs_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = crtc->dev; struct vc4_dev *vc4 = to_vc4_dev(dev); @@ -912,7 +912,7 @@ void vc4_hvs_atomic_enable(struct drm_crtc *crtc, } void vc4_hvs_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = crtc->dev; struct vc4_dev *vc4 = to_vc4_dev(dev); @@ -924,7 +924,7 @@ void vc4_hvs_atomic_disable(struct drm_crtc *crtc, } void vc4_hvs_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c index 264b5e80c24d..b17e73bce384 100644 --- a/drivers/gpu/drm/vc4/vc4_kms.c +++ b/drivers/gpu/drm/vc4/vc4_kms.c @@ -44,7 +44,7 @@ struct vc4_load_tracker_state { #define to_vc4_load_tracker_state(_state) \ container_of_const(_state, struct vc4_load_tracker_state, base) -static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state, +static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_commit *state, struct drm_private_obj *manager) { struct drm_device *dev = state->dev; @@ -142,7 +142,7 @@ static u16 vc4_ctm_s31_32_to_s0_9(u64 in) } static void -vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state) +vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_commit *state) { struct vc4_hvs *hvs = vc4->hvs; struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state); @@ -179,7 +179,7 @@ vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state) } struct vc4_hvs_state * -vc4_hvs_get_new_global_state(const struct drm_atomic_state *state) +vc4_hvs_get_new_global_state(const struct drm_atomic_commit *state) { struct vc4_dev *vc4 = to_vc4_dev(state->dev); struct drm_private_state *priv_state; @@ -192,7 +192,7 @@ vc4_hvs_get_new_global_state(const struct drm_atomic_state *state) } struct vc4_hvs_state * -vc4_hvs_get_old_global_state(const struct drm_atomic_state *state) +vc4_hvs_get_old_global_state(const struct drm_atomic_commit *state) { struct vc4_dev *vc4 = to_vc4_dev(state->dev); struct drm_private_state *priv_state; @@ -205,7 +205,7 @@ vc4_hvs_get_old_global_state(const struct drm_atomic_state *state) } struct vc4_hvs_state * -vc4_hvs_get_global_state(struct drm_atomic_state *state) +vc4_hvs_get_global_state(struct drm_atomic_commit *state) { struct vc4_dev *vc4 = to_vc4_dev(state->dev); struct drm_private_state *priv_state; @@ -218,7 +218,7 @@ vc4_hvs_get_global_state(struct drm_atomic_state *state) } static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vc4_hvs *hvs = vc4->hvs; struct drm_crtc_state *crtc_state; @@ -261,7 +261,7 @@ static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4, } static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vc4_hvs *hvs = vc4->hvs; struct drm_crtc_state *crtc_state; @@ -337,7 +337,7 @@ static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4, } static void vc6_hvs_pv_muxing_commit(struct vc4_dev *vc4, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vc4_hvs *hvs = vc4->hvs; struct drm_crtc_state *crtc_state; @@ -384,7 +384,7 @@ static void vc6_hvs_pv_muxing_commit(struct vc4_dev *vc4, } } -static void vc4_atomic_commit_tail(struct drm_atomic_state *state) +static void vc4_atomic_commit_tail(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; struct vc4_dev *vc4 = to_vc4_dev(dev); @@ -508,7 +508,7 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state) } } -static int vc4_atomic_commit_setup(struct drm_atomic_state *state) +static int vc4_atomic_commit_setup(struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state; struct vc4_hvs_state *hvs_state; @@ -587,7 +587,7 @@ static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev, * we don't allow userland to set a CTM that we have no hope of approximating. */ static int -vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) +vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_commit *state) { struct vc4_dev *vc4 = to_vc4_dev(dev); struct vc4_ctm_state *ctm_state = NULL; @@ -653,7 +653,7 @@ vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) return 0; } -static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state) +static int vc4_load_tracker_atomic_check(struct drm_atomic_commit *state) { struct drm_plane_state *old_plane_state, *new_plane_state; struct vc4_dev *vc4 = to_vc4_dev(state->dev); @@ -898,7 +898,7 @@ static int cmp_vc4_crtc_hvs_output(const void *a, const void *b) * single display, and changing the resolution down and then back up. */ static int vc4_pv_muxing_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vc4_hvs_state *hvs_new_state; struct drm_crtc **sorted_crtcs; @@ -1019,7 +1019,7 @@ static int vc4_pv_muxing_atomic_check(struct drm_device *dev, } static int -vc4_core_clock_atomic_check(struct drm_atomic_state *state) +vc4_core_clock_atomic_check(struct drm_atomic_commit *state) { struct vc4_dev *vc4 = to_vc4_dev(state->dev); struct drm_private_state *priv_state; @@ -1091,7 +1091,7 @@ vc4_core_clock_atomic_check(struct drm_atomic_state *state) static int -vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) +vc4_atomic_check(struct drm_device *dev, struct drm_atomic_commit *state) { int ret; diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c index a81bad3519cc..6c433270214d 100644 --- a/drivers/gpu/drm/vc4/vc4_plane.c +++ b/drivers/gpu/drm/vc4/vc4_plane.c @@ -2123,7 +2123,7 @@ static int vc6_plane_mode_set(struct drm_plane *plane, * in the CRTC's flush. */ static int vc4_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vc4_dev *vc4 = to_vc4_dev(plane->dev); struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, @@ -2169,7 +2169,7 @@ static int vc4_plane_atomic_check(struct drm_plane *plane, } static void vc4_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { /* No contents here. Since we don't know where in the CRTC's * dlist we should be stored, our dlist is uploaded to the @@ -2261,7 +2261,7 @@ void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb) } static void vc4_plane_atomic_async_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -2335,7 +2335,7 @@ static void vc4_plane_atomic_async_update(struct drm_plane *plane, } static int vc4_plane_atomic_async_check(struct drm_plane *plane, - struct drm_atomic_state *state, bool flip) + struct drm_atomic_commit *state, bool flip) { struct vc4_dev *vc4 = to_vc4_dev(plane->dev); struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, diff --git a/drivers/gpu/drm/vc4/vc4_txp.c b/drivers/gpu/drm/vc4/vc4_txp.c index 9082902100e4..66b6f2acf862 100644 --- a/drivers/gpu/drm/vc4/vc4_txp.c +++ b/drivers/gpu/drm/vc4/vc4_txp.c @@ -246,7 +246,7 @@ static void vc4_txp_armed(struct drm_crtc_state *state) } static int vc4_txp_connector_atomic_check(struct drm_connector *conn, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *conn_state; struct drm_crtc_state *crtc_state; @@ -285,7 +285,7 @@ static int vc4_txp_connector_atomic_check(struct drm_connector *conn, } static void vc4_txp_connector_atomic_commit(struct drm_connector *conn, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = conn->dev; struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(state, @@ -435,7 +435,7 @@ static const struct drm_crtc_funcs vc4_txp_crtc_funcs = { }; static int vc4_txp_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -451,14 +451,14 @@ static int vc4_txp_atomic_check(struct drm_crtc *crtc, } static void vc4_txp_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { drm_crtc_vblank_on(crtc); vc4_hvs_atomic_enable(crtc, state); } static void vc4_txp_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = crtc->dev; diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c index b0b271d93b27..792b7b39be59 100644 --- a/drivers/gpu/drm/vc4/vc4_vec.c +++ b/drivers/gpu/drm/vc4/vc4_vec.c @@ -538,7 +538,7 @@ static int vc4_vec_connector_init(struct drm_device *dev, struct vc4_vec *vec) } static void vc4_vec_encoder_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = encoder->dev; struct vc4_vec *vec = encoder_to_vc4_vec(encoder); @@ -562,7 +562,7 @@ static void vc4_vec_encoder_disable(struct drm_encoder *encoder, } static void vc4_vec_encoder_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *drm = encoder->dev; struct vc4_vec *vec = encoder_to_vc4_vec(encoder); diff --git a/drivers/gpu/drm/verisilicon/vs_bridge.c b/drivers/gpu/drm/verisilicon/vs_bridge.c index 83c91d5ce397..7a93049368db 100644 --- a/drivers/gpu/drm/verisilicon/vs_bridge.c +++ b/drivers/gpu/drm/verisilicon/vs_bridge.c @@ -174,7 +174,7 @@ static void vs_bridge_enable_common(struct vs_crtc *crtc, } static void vs_bridge_atomic_enable_dpi(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); struct drm_bridge_state *br_state = @@ -192,7 +192,7 @@ static void vs_bridge_atomic_enable_dpi(struct drm_bridge *bridge, } static void vs_bridge_atomic_enable_dp(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); struct drm_bridge_state *br_state = @@ -221,7 +221,7 @@ static void vs_bridge_atomic_enable_dp(struct drm_bridge *bridge, } static void vs_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); struct vs_crtc *crtc = vbridge->crtc; diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisilicon/vs_crtc.c index f49401713000..9080344398ca 100644 --- a/drivers/gpu/drm/verisilicon/vs_crtc.c +++ b/drivers/gpu/drm/verisilicon/vs_crtc.c @@ -21,7 +21,7 @@ #include "vs_plane.h" static void vs_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); struct vs_dc *dc = vcrtc->dc; @@ -33,7 +33,7 @@ static void vs_crtc_atomic_disable(struct drm_crtc *crtc, } static void vs_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); struct vs_dc *dc = vcrtc->dc; diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane.c b/drivers/gpu/drm/verisilicon/vs_primary_plane.c index 3576dd524f5c..1f2be41ae496 100644 --- a/drivers/gpu/drm/verisilicon/vs_primary_plane.c +++ b/drivers/gpu/drm/verisilicon/vs_primary_plane.c @@ -21,7 +21,7 @@ #include "vs_primary_plane_regs.h" static int vs_primary_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -60,7 +60,7 @@ static void vs_primary_plane_commit(struct vs_dc *dc, unsigned int output) } static void vs_primary_plane_atomic_enable(struct drm_plane *plane, - struct drm_atomic_state *atomic_state) + struct drm_atomic_commit *atomic_state) { struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, plane); @@ -79,7 +79,7 @@ static void vs_primary_plane_atomic_enable(struct drm_plane *plane, } static void vs_primary_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *atomic_state) + struct drm_atomic_commit *atomic_state) { struct drm_plane_state *state = drm_atomic_get_old_plane_state(atomic_state, plane); @@ -95,7 +95,7 @@ static void vs_primary_plane_atomic_disable(struct drm_plane *plane, } static void vs_primary_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *atomic_state) + struct drm_atomic_commit *atomic_state) { struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, plane); diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c b/drivers/gpu/drm/virtio/virtgpu_display.c index f1dae9569805..44ffffec550f 100644 --- a/drivers/gpu/drm/virtio/virtgpu_display.c +++ b/drivers/gpu/drm/virtio/virtgpu_display.c @@ -101,13 +101,13 @@ static void virtio_gpu_crtc_mode_set_nofb(struct drm_crtc *crtc) } static void virtio_gpu_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { drm_crtc_vblank_on(crtc); } static void virtio_gpu_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = crtc->dev; struct virtio_gpu_device *vgdev = dev->dev_private; @@ -120,13 +120,13 @@ static void virtio_gpu_crtc_atomic_disable(struct drm_crtc *crtc, } static int virtio_gpu_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { return 0; } static void virtio_gpu_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = crtc->dev; struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/virtio/virtgpu_plane.c b/drivers/gpu/drm/virtio/virtgpu_plane.c index a126d1b25f46..73aa70bd4231 100644 --- a/drivers/gpu/drm/virtio/virtgpu_plane.c +++ b/drivers/gpu/drm/virtio/virtgpu_plane.c @@ -97,7 +97,7 @@ static const struct drm_plane_funcs virtio_gpu_plane_funcs = { }; static int virtio_gpu_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -230,7 +230,7 @@ static void virtio_gpu_resource_flush(struct drm_plane *plane, } static void virtio_gpu_primary_plane_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -423,7 +423,7 @@ static void virtio_gpu_plane_cleanup_fb(struct drm_plane *plane, } static void virtio_gpu_cursor_plane_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); diff --git a/drivers/gpu/drm/vkms/vkms_crtc.c b/drivers/gpu/drm/vkms/vkms_crtc.c index 35ddc553a5e6..079abfba427d 100644 --- a/drivers/gpu/drm/vkms/vkms_crtc.c +++ b/drivers/gpu/drm/vkms/vkms_crtc.c @@ -111,7 +111,7 @@ static const struct drm_crtc_funcs vkms_crtc_funcs = { }; static int vkms_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -157,7 +157,7 @@ static int vkms_crtc_atomic_check(struct drm_crtc *crtc, } static void vkms_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) __acquires(&vkms_output->lock) { struct vkms_output *vkms_output = drm_crtc_to_vkms_output(crtc); @@ -169,7 +169,7 @@ static void vkms_crtc_atomic_begin(struct drm_crtc *crtc, } static void vkms_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) __releases(&vkms_output->lock) { struct vkms_output *vkms_output = drm_crtc_to_vkms_output(crtc); diff --git a/drivers/gpu/drm/vkms/vkms_drv.c b/drivers/gpu/drm/vkms/vkms_drv.c index 95020765c4c2..5a640b531d88 100644 --- a/drivers/gpu/drm/vkms/vkms_drv.c +++ b/drivers/gpu/drm/vkms/vkms_drv.c @@ -62,7 +62,7 @@ MODULE_PARM_DESC(create_default_dev, "Create or not the default VKMS device"); DEFINE_DRM_GEM_FOPS(vkms_driver_fops); -static void vkms_atomic_commit_tail(struct drm_atomic_state *old_state) +static void vkms_atomic_commit_tail(struct drm_atomic_commit *old_state) { struct drm_device *dev = old_state->dev; struct drm_crtc *crtc; @@ -102,7 +102,7 @@ static const struct drm_driver vkms_driver = { .minor = DRIVER_MINOR, }; -static int vkms_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) +static int vkms_atomic_check(struct drm_device *dev, struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; diff --git a/drivers/gpu/drm/vkms/vkms_plane.c b/drivers/gpu/drm/vkms/vkms_plane.c index ca7aee101a95..68cb2a3335e6 100644 --- a/drivers/gpu/drm/vkms/vkms_plane.c +++ b/drivers/gpu/drm/vkms/vkms_plane.c @@ -122,7 +122,7 @@ static const struct drm_plane_funcs vkms_plane_funcs = { }; static void vkms_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -153,7 +153,7 @@ static void vkms_plane_atomic_update(struct drm_plane *plane, } static int vkms_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/vkms/vkms_writeback.c b/drivers/gpu/drm/vkms/vkms_writeback.c index 908b7e602ffb..ecf29a2c0c8e 100644 --- a/drivers/gpu/drm/vkms/vkms_writeback.c +++ b/drivers/gpu/drm/vkms/vkms_writeback.c @@ -32,7 +32,7 @@ static const struct drm_connector_funcs vkms_wb_connector_funcs = { }; static int vkms_wb_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(state, connector); @@ -123,7 +123,7 @@ static void vkms_wb_cleanup_job(struct drm_writeback_connector *connector, } static void vkms_wb_atomic_commit(struct drm_connector *conn, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, conn); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c b/drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c index c46f17ba7236..b010fc7ca68e 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c @@ -690,7 +690,7 @@ int vmw_cursor_plane_prepare_fb(struct drm_plane *plane, * Returns 0 on success */ int vmw_cursor_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -739,7 +739,7 @@ int vmw_cursor_plane_atomic_check(struct drm_plane *plane, void vmw_cursor_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vmw_bo *bo; struct drm_plane_state *new_state = diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.h b/drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.h index 0c2cc0699b0d..d32cf17d013b 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.h +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.h @@ -71,9 +71,9 @@ void vmw_cursor_cmd_dma_snoop(SVGA3dCmdHeader *header, void vmw_cursor_plane_destroy(struct drm_plane *plane); int vmw_cursor_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void vmw_cursor_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); int vmw_cursor_plane_prepare_fb(struct drm_plane *plane, struct drm_plane_state *new_state); void vmw_cursor_plane_cleanup_fb(struct drm_plane *plane, diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h index 57465f69c687..38bea8abab84 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h @@ -507,7 +507,7 @@ struct vmw_private { struct drm_property *hotplug_mode_update_property; struct drm_property *implicit_placement_property; spinlock_t cursor_lock; - struct drm_atomic_state *suspend_state; + struct drm_atomic_commit *suspend_state; /* * Context and surface management. diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c index e7bddf840a79..1b407b61f683 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c @@ -101,7 +101,7 @@ vmw_du_plane_cleanup_fb(struct drm_plane *plane, * Returns 0 on success */ int vmw_du_primary_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -132,7 +132,7 @@ int vmw_du_primary_plane_atomic_check(struct drm_plane *plane, } int vmw_du_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vmw_private *vmw = vmw_priv(crtc->dev); struct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state, @@ -169,7 +169,7 @@ int vmw_du_crtc_atomic_check(struct drm_crtc *crtc, void vmw_du_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { vmw_vkms_crtc_atomic_begin(crtc, state); } @@ -864,7 +864,7 @@ static int vmw_kms_check_display_memory(struct drm_device *dev, * pointer error, in particular -EDEADLK if locking needs to be rerun. */ static struct drm_crtc_state * -vmw_crtc_state_and_lock(struct drm_atomic_state *state, struct drm_crtc *crtc) +vmw_crtc_state_and_lock(struct drm_atomic_commit *state, struct drm_crtc *crtc) { struct drm_crtc_state *crtc_state; @@ -895,7 +895,7 @@ vmw_crtc_state_and_lock(struct drm_atomic_state *state, struct drm_crtc *crtc) * -EDEADLK if modeset locking needs to be rerun. */ static int vmw_kms_check_implicit(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_framebuffer *implicit_fb = NULL; struct drm_crtc *crtc; @@ -933,7 +933,7 @@ static int vmw_kms_check_implicit(struct drm_device *dev, } /** - * vmw_kms_check_topology - Validates topology in drm_atomic_state + * vmw_kms_check_topology - Validates topology in drm_atomic_commit * @dev: DRM device * @state: the driver state object * @@ -941,7 +941,7 @@ static int vmw_kms_check_implicit(struct drm_device *dev, * 0 on success otherwise negative error code */ static int vmw_kms_check_topology(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_crtc_state, *new_crtc_state; struct drm_rect *rects; @@ -1035,7 +1035,7 @@ static int vmw_kms_check_topology(struct drm_device *dev, */ static int vmw_kms_atomic_check_modeset(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; @@ -1133,7 +1133,7 @@ vmw_kms_create_hotplug_mode_update_property(struct vmw_private *dev_priv) } static void -vmw_atomic_commit_tail(struct drm_atomic_state *old_state) +vmw_atomic_commit_tail(struct drm_atomic_commit *old_state) { struct vmw_private *vmw = vmw_priv(old_state->dev); struct drm_crtc *crtc; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h index b5670ece90a9..2224d7d91d1b 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h @@ -408,7 +408,7 @@ void vmw_du_primary_plane_destroy(struct drm_plane *plane); /* Atomic Helpers */ int vmw_du_primary_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void vmw_du_plane_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state); void vmw_du_plane_reset(struct drm_plane *plane); @@ -418,9 +418,9 @@ void vmw_du_plane_destroy_state(struct drm_plane *plane, void vmw_du_plane_unpin_surf(struct vmw_plane_state *vps); int vmw_du_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void vmw_du_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void vmw_du_crtc_reset(struct drm_crtc *crtc); struct drm_crtc_state *vmw_du_crtc_duplicate_state(struct drm_crtc *crtc); void vmw_du_crtc_destroy_state(struct drm_crtc *crtc, diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c index 6f22d5f5c379..af3e32174563 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c @@ -310,7 +310,7 @@ static int vmw_kms_ldu_do_bo_dirty(struct vmw_private *dev_priv, static void vmw_ldu_primary_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c index cfb8ad3ebe43..c83061cf7455 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c @@ -277,7 +277,7 @@ static void vmw_sou_crtc_helper_prepare(struct drm_crtc *crtc) * @state: Unused */ static void vmw_sou_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vmw_private *dev_priv; struct vmw_screen_object_unit *sou; @@ -719,7 +719,7 @@ static int vmw_sou_plane_update_surface(struct vmw_private *dev_priv, static void vmw_sou_primary_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c index 1f5497e2638a..4139837f4caf 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c @@ -414,7 +414,7 @@ static void vmw_stdu_crtc_mode_set_nofb(struct drm_crtc *crtc) } static void vmw_stdu_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vmw_private *dev_priv; struct vmw_screen_target_display_unit *stdu; @@ -879,7 +879,7 @@ vmw_stdu_connector_mode_valid(struct drm_connector *connector, * the same mode but its relative X,Y position in the topology will change. */ static int vmw_stdu_connector_atomic_check(struct drm_connector *conn, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *conn_state; struct vmw_screen_target_display_unit *du; @@ -1399,7 +1399,7 @@ static int vmw_stdu_plane_update_surface(struct vmw_private *dev_priv, */ static void vmw_stdu_primary_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -1460,7 +1460,7 @@ vmw_stdu_primary_plane_atomic_update(struct drm_plane *plane, static void vmw_stdu_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vmw_private *vmw = vmw_priv(crtc->dev); struct vmw_screen_target_display_unit *stdu = vmw_crtc_to_stdu(crtc); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_vkms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_vkms.c index 1f98aa04c9f3..7b8163b5e501 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_vkms.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_vkms.c @@ -307,7 +307,7 @@ vmw_vkms_crtc_cleanup(struct drm_crtc *crtc) void vmw_vkms_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vmw_private *vmw = vmw_priv(crtc->dev); @@ -317,7 +317,7 @@ vmw_vkms_crtc_atomic_begin(struct drm_crtc *crtc, void vmw_vkms_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { unsigned long flags; struct vmw_private *vmw = vmw_priv(crtc->dev); @@ -343,7 +343,7 @@ vmw_vkms_crtc_atomic_flush(struct drm_crtc *crtc, void vmw_vkms_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vmw_private *vmw = vmw_priv(crtc->dev); @@ -353,7 +353,7 @@ vmw_vkms_crtc_atomic_enable(struct drm_crtc *crtc, void vmw_vkms_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct vmw_private *vmw = vmw_priv(crtc->dev); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_vkms.h b/drivers/gpu/drm/vmwgfx/vmwgfx_vkms.h index 40c679f59db2..27bc846313ca 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_vkms.h +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_vkms.h @@ -31,7 +31,7 @@ #include -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_crtc; struct vmw_private; struct vmw_surface; @@ -55,12 +55,12 @@ void vmw_vkms_disable_vblank(struct drm_crtc *crtc); void vmw_vkms_crtc_init(struct drm_crtc *crtc); void vmw_vkms_crtc_cleanup(struct drm_crtc *crtc); void vmw_vkms_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state); -void vmw_vkms_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state); + struct drm_atomic_commit *state); +void vmw_vkms_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_commit *state); void vmw_vkms_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void vmw_vkms_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); const char *const *vmw_vkms_get_crc_sources(struct drm_crtc *crtc, size_t *count); diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 49de1c22a469..09661f079d03 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -88,6 +88,7 @@ xe-y += xe_bb.o \ xe_irq.o \ xe_late_bind_fw.o \ xe_lrc.o \ + xe_mem_pool.o \ xe_migrate.o \ xe_mmio.o \ xe_mmio_gem.o \ @@ -112,6 +113,7 @@ xe-y += xe_bb.o \ xe_pxp_submit.o \ xe_query.o \ xe_range_fence.o \ + xe_ras.o \ xe_reg_sr.o \ xe_reg_whitelist.o \ xe_ring_ops.o \ @@ -123,6 +125,9 @@ xe-y += xe_bb.o \ xe_step.o \ xe_survivability_mode.o \ xe_sync.o \ + xe_sysctrl.o \ + xe_sysctrl_event.o \ + xe_sysctrl_mailbox.o \ xe_tile.o \ xe_tile_sysfs.o \ xe_tlb_inval.o \ @@ -211,7 +216,6 @@ $(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE # Display code specific to xe xe-$(CONFIG_DRM_XE_DISPLAY) += \ - display/intel_fbdev_fb.o \ display/xe_display.o \ display/xe_display_bo.o \ display/xe_display_pcode.o \ @@ -261,6 +265,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-display/intel_display_power.o \ i915-display/intel_display_power_map.o \ i915-display/intel_display_power_well.o \ + i915-display/intel_display_reset.o \ i915-display/intel_display_rpm.o \ i915-display/intel_display_rps.o \ i915-display/intel_display_trace.o \ @@ -304,6 +309,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-display/intel_link_bw.o \ i915-display/intel_lspcon.o \ i915-display/intel_lt_phy.o \ + i915-display/intel_mchbar.o \ i915-display/intel_modeset_lock.o \ i915-display/intel_modeset_setup.o \ i915-display/intel_modeset_verify.o \ @@ -330,7 +336,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-display/skl_prefill.o \ i915-display/skl_scaler.o \ i915-display/skl_universal_plane.o \ - i915-display/skl_watermark.o + i915-display/skl_watermark.o \ + i915-display/vlv_sideband.o ifeq ($(CONFIG_ACPI),y) xe-$(CONFIG_DRM_XE_DISPLAY) += \ diff --git a/drivers/gpu/drm/xe/abi/guc_klvs_abi.h b/drivers/gpu/drm/xe/abi/guc_klvs_abi.h index e33bd622ab44..644f5a4226d7 100644 --- a/drivers/gpu/drm/xe/abi/guc_klvs_abi.h +++ b/drivers/gpu/drm/xe/abi/guc_klvs_abi.h @@ -192,6 +192,13 @@ enum { * `GuC KLV`_ keys available for use with PF2GUC_UPDATE_VGT_POLICY. * * _`GUC_KLV_VGT_POLICY_SCHED_IF_IDLE` : 0x8001 + * [From 70.12.0] + * This config allows to update scheduling priority of PF and all VFs at once. + * Setting this policy to 0 updates all VFs scheduling priorities to LOW, and + * setting this policy to 1 updates all VFs scheduling priorities to NORMAL. + * Those changes will take effect on the next VF-Switch event. + * + * [Before 70.12.0] * This config sets whether strict scheduling is enabled whereby any VF * that doesn’t have work to submit is still allocated a fixed execution * time-slice to ensure active VFs execution is always consistent even @@ -496,6 +503,7 @@ enum xe_guc_klv_ids { GUC_WA_KLV_WAKE_POWER_DOMAINS_FOR_OUTBOUND_MMIO = 0x900a, GUC_WA_KLV_RESET_BB_STACK_PTR_ON_VF_SWITCH = 0x900b, GUC_WA_KLV_RESTORE_UNSAVED_MEDIA_CONTROL_REG = 0x900c, + GUC_WA_KLV_CLR_CS_INDIRECT_RING_STATE_IF_IDLE_AT_CTX_REG = 0x900e, }; #endif diff --git a/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h b/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h new file mode 100644 index 000000000000..4cbde267ac44 --- /dev/null +++ b/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ + +#ifndef _XE_SYSCTRL_ABI_H_ +#define _XE_SYSCTRL_ABI_H_ + +#include + +/** + * DOC: System Controller ABI + * + * This header defines the Application Binary Interface (ABI) used by + * drm/xe to communicate with System Controller firmware on Intel Xe3p + * discrete GPU platforms. + * + * System Controller (sysctrl) is a firmware-managed entity on Intel + * dGPUs responsible for certain low-level platform management + * functions. + * + * Communication protocol: + * + * Communication uses a mailbox interface with messages composed of: + * + * - Application message header (struct xe_sysctrl_app_msg_hdr) + * containing group_id, command, and version + * - Variable-length, command-specific payload + * + * Message header format: + * + * The 32-bit application message header is packed as: + * + * - Bits [7:0] : Group ID identifying command group + * - Bits [15:8] : Command identifier within group + * - Bits [23:16] : Command version for interface compatibility + * - Bits [31:24] : Reserved, must be zero + * + * This header defines firmware ABI message formats and constants shared + * between driver and System Controller firmware. + */ + +/** + * struct xe_sysctrl_app_msg_hdr - Application layer message header + * @data: 32-bit header data + * + * Header structure for application-level messages. + */ +struct xe_sysctrl_app_msg_hdr { + u32 data; +} __packed; + +#define SYSCTRL_HDR_GROUP_ID_MASK GENMASK(7, 0) +#define SYSCTRL_HDR_COMMAND_MASK GENMASK(14, 8) +#define SYSCTRL_HDR_COMMAND_MAX 0x7f +#define SYSCTRL_HDR_IS_RESPONSE BIT(15) +#define SYSCTRL_HDR_RESERVED_MASK GENMASK(23, 16) +#define SYSCTRL_HDR_RESULT_MASK GENMASK(31, 24) + +#define APP_HDR_GROUP_ID_MASK GENMASK(7, 0) +#define APP_HDR_COMMAND_MASK GENMASK(15, 8) +#define APP_HDR_VERSION_MASK GENMASK(23, 16) +#define APP_HDR_RESERVED_MASK GENMASK(31, 24) + +#endif diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h index ce986f0e8f38..552975a30ba2 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h @@ -3,4 +3,12 @@ * Copyright © 2023 Intel Corporation */ -#include "../../i915/intel_clock_gating.h" +#ifndef __INTEL_CLOCK_GATING_H__ +#define __INTEL_CLOCK_GATING_H__ + +struct drm_device; + +static inline void intel_clock_gating_init(struct drm_device *drm) {} +static inline void intel_clock_gating_hooks_init(struct drm_device *drm) {} + +#endif /* __INTEL_CLOCK_GATING_H__ */ diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h deleted file mode 100644 index 55b316985340..000000000000 --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2023 Intel Corporation - */ - -#include "../../i915/intel_mchbar_regs.h" diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h deleted file mode 100644 index 8c15867fd613..000000000000 --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2023 Intel Corporation - */ - -#include "../../i915/intel_pci_config.h" diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_step.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_step.h deleted file mode 100644 index 0eabe2866f5f..000000000000 --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_step.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2023 Intel Corporation - */ - -#ifndef __INTEL_STEP_H__ -#define __INTEL_STEP_H__ - -#include "xe_step_types.h" - -#define intel_step xe_step - -#endif /* __INTEL_STEP_H__ */ diff --git a/drivers/gpu/drm/xe/compat-i915-headers/vlv_iosf_sb.h b/drivers/gpu/drm/xe/compat-i915-headers/vlv_iosf_sb.h deleted file mode 100644 index 69e1935e9cdf..000000000000 --- a/drivers/gpu/drm/xe/compat-i915-headers/vlv_iosf_sb.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2013-2021 Intel Corporation - */ - -#ifndef _VLV_IOSF_SB_H_ -#define _VLV_IOSF_SB_H_ - -#include - -#include "vlv_iosf_sb_reg.h" - -struct drm_device; - -enum vlv_iosf_sb_unit { - VLV_IOSF_SB_BUNIT, - VLV_IOSF_SB_CCK, - VLV_IOSF_SB_CCU, - VLV_IOSF_SB_DPIO, - VLV_IOSF_SB_DPIO_2, - VLV_IOSF_SB_FLISDSI, - VLV_IOSF_SB_GPIO, - VLV_IOSF_SB_NC, - VLV_IOSF_SB_PUNIT, -}; - -static inline void vlv_iosf_sb_get(struct drm_device *drm, unsigned long ports) -{ -} -static inline u32 vlv_iosf_sb_read(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr) -{ - return 0; -} -static inline int vlv_iosf_sb_write(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr, u32 val) -{ - return 0; -} -static inline void vlv_iosf_sb_put(struct drm_device *drm, unsigned long ports) -{ -} - -#endif /* _VLV_IOSF_SB_H_ */ diff --git a/drivers/gpu/drm/xe/compat-i915-headers/vlv_iosf_sb_reg.h b/drivers/gpu/drm/xe/compat-i915-headers/vlv_iosf_sb_reg.h deleted file mode 100644 index cb7fa8e794a6..000000000000 --- a/drivers/gpu/drm/xe/compat-i915-headers/vlv_iosf_sb_reg.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2023 Intel Corporation - */ - -#include "../../i915/vlv_iosf_sb_reg.h" diff --git a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c deleted file mode 100644 index d7030e4d814c..000000000000 --- a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c +++ /dev/null @@ -1,120 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2023 Intel Corporation - */ - -#include - -#include "intel_fbdev_fb.h" -#include "xe_bo.h" -#include "xe_ttm_stolen_mgr.h" -#include "xe_wa.h" - -#include - -/* - * FIXME: There shouldn't be any reason to have XE_PAGE_SIZE stride - * alignment. The same 64 as i915 uses should be fine, and we shouldn't need to - * have driver specific values. However, dropping the stride alignment to 64 - * leads to underflowing the bo pin count in the atomic cleanup work. - */ -u32 intel_fbdev_fb_pitch_align(u32 stride) -{ - return ALIGN(stride, XE_PAGE_SIZE); -} - -bool intel_fbdev_fb_prefer_stolen(struct drm_device *drm, unsigned int size) -{ - struct xe_device *xe = to_xe_device(drm); - struct ttm_resource_manager *stolen; - - stolen = ttm_manager_type(&xe->ttm, XE_PL_STOLEN); - if (!stolen) - return false; - - if (IS_DGFX(xe)) - return false; - - if (XE_DEVICE_WA(xe, 22019338487_display)) - return false; - - /* - * If the FB is too big, just don't use it since fbdev is not very - * important and we should probably use that space with FBC or other - * features. - */ - return stolen->size >= size * 2; -} - -struct drm_gem_object *intel_fbdev_fb_bo_create(struct drm_device *drm, int size) -{ - struct xe_device *xe = to_xe_device(drm); - struct xe_bo *obj; - - obj = ERR_PTR(-ENODEV); - - if (intel_fbdev_fb_prefer_stolen(drm, size)) { - obj = xe_bo_create_pin_map_novm(xe, xe_device_get_root_tile(xe), - size, - ttm_bo_type_kernel, - XE_BO_FLAG_FORCE_WC | - XE_BO_FLAG_STOLEN | - XE_BO_FLAG_GGTT, - false); - if (!IS_ERR(obj)) - drm_info(&xe->drm, "Allocated fbdev into stolen\n"); - else - drm_info(&xe->drm, "Allocated fbdev into stolen failed: %li\n", PTR_ERR(obj)); - } else { - drm_info(&xe->drm, "Allocating fbdev: Stolen memory not preferred.\n"); - } - - if (IS_ERR(obj)) { - obj = xe_bo_create_pin_map_novm(xe, xe_device_get_root_tile(xe), size, - ttm_bo_type_kernel, - XE_BO_FLAG_FORCE_WC | - XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) | - XE_BO_FLAG_GGTT, - false); - } - - if (IS_ERR(obj)) { - drm_err(&xe->drm, "failed to allocate framebuffer (%pe)\n", obj); - return ERR_PTR(-ENOMEM); - } - - return &obj->ttm.base; -} - -void intel_fbdev_fb_bo_destroy(struct drm_gem_object *obj) -{ - xe_bo_unpin_map_no_vm(gem_to_xe_bo(obj)); -} - -int intel_fbdev_fb_fill_info(struct drm_device *drm, struct fb_info *info, - struct drm_gem_object *_obj, struct i915_vma *vma) -{ - struct xe_bo *obj = gem_to_xe_bo(_obj); - struct pci_dev *pdev = to_pci_dev(drm->dev); - - if (!(obj->flags & XE_BO_FLAG_SYSTEM)) { - if (obj->flags & XE_BO_FLAG_STOLEN) - info->fix.smem_start = xe_ttm_stolen_io_offset(obj, 0); - else - info->fix.smem_start = - pci_resource_start(pdev, 2) + - xe_bo_addr(obj, 0, XE_PAGE_SIZE); - - info->fix.smem_len = obj->ttm.base.size; - } else { - /* XXX: Pure fiction, as the BO may not be physically accessible.. */ - info->fix.smem_start = 0; - info->fix.smem_len = obj->ttm.base.size; - } - XE_WARN_ON(iosys_map_is_null(&obj->vmap)); - - info->screen_base = obj->vmap.vaddr_iomem; - info->screen_size = obj->ttm.base.size; - - return 0; -} diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c index 00dfa68af29a..0747044f7c2a 100644 --- a/drivers/gpu/drm/xe/display/xe_display.c +++ b/drivers/gpu/drm/xe/display/xe_display.c @@ -520,9 +520,10 @@ void xe_display_pm_runtime_resume(struct xe_device *xe) static void display_device_remove(struct drm_device *dev, void *arg) { - struct intel_display *display = arg; + struct xe_device *xe = arg; - intel_display_device_remove(display); + intel_display_device_remove(xe->display); + xe->display = NULL; } static bool irq_enabled(struct drm_device *drm) @@ -587,12 +588,12 @@ int xe_display_probe(struct xe_device *xe) if (IS_ERR(display)) return PTR_ERR(display); - err = drmm_add_action_or_reset(&xe->drm, display_device_remove, display); + xe->display = display; + + err = drmm_add_action_or_reset(&xe->drm, display_device_remove, xe); if (err) return err; - xe->display = display; - if (intel_display_device_present(display)) return 0; diff --git a/drivers/gpu/drm/xe/display/xe_display_bo.c b/drivers/gpu/drm/xe/display/xe_display_bo.c index 1d81b9908265..dc0d78ff2d79 100644 --- a/drivers/gpu/drm/xe/display/xe_display_bo.c +++ b/drivers/gpu/drm/xe/display/xe_display_bo.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: MIT /* Copyright © 2024 Intel Corporation */ +#include + #include #include @@ -8,6 +10,10 @@ #include "xe_bo.h" #include "xe_display_bo.h" #include "xe_pxp.h" +#include "xe_ttm_stolen_mgr.h" +#include "xe_wa.h" + +#include static bool xe_display_bo_is_protected(struct drm_gem_object *obj) { @@ -101,6 +107,114 @@ xe_display_bo_framebuffer_lookup(struct drm_device *drm, return gem; } +#if IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION) +/* + * FIXME: There shouldn't be any reason to have XE_PAGE_SIZE stride + * alignment. The same 64 as i915 uses should be fine, and we shouldn't need to + * have driver specific values. However, dropping the stride alignment to 64 + * leads to underflowing the bo pin count in the atomic cleanup work. + */ +static u32 xe_display_bo_fbdev_pitch_align(u32 stride) +{ + return ALIGN(stride, XE_PAGE_SIZE); +} + +bool xe_display_bo_fbdev_prefer_stolen(struct xe_device *xe, unsigned int size) +{ + struct ttm_resource_manager *stolen; + + stolen = ttm_manager_type(&xe->ttm, XE_PL_STOLEN); + if (!stolen) + return false; + + if (IS_DGFX(xe)) + return false; + + if (XE_DEVICE_WA(xe, 22019338487_display)) + return false; + + /* + * If the FB is too big, just don't use it since fbdev is not very + * important and we should probably use that space with FBC or other + * features. + */ + return stolen->size >= size * 2; +} + +static struct drm_gem_object *xe_display_bo_fbdev_create(struct drm_device *drm, int size) +{ + struct xe_device *xe = to_xe_device(drm); + struct xe_bo *obj; + + obj = ERR_PTR(-ENODEV); + + if (xe_display_bo_fbdev_prefer_stolen(xe, size)) { + obj = xe_bo_create_pin_map_novm(xe, xe_device_get_root_tile(xe), + size, + ttm_bo_type_kernel, + XE_BO_FLAG_FORCE_WC | + XE_BO_FLAG_STOLEN | + XE_BO_FLAG_GGTT, + false); + if (!IS_ERR(obj)) + drm_info(&xe->drm, "Allocated fbdev into stolen\n"); + else + drm_info(&xe->drm, "Allocated fbdev into stolen failed: %li\n", PTR_ERR(obj)); + } else { + drm_info(&xe->drm, "Allocating fbdev: Stolen memory not preferred.\n"); + } + + if (IS_ERR(obj)) { + obj = xe_bo_create_pin_map_novm(xe, xe_device_get_root_tile(xe), size, + ttm_bo_type_kernel, + XE_BO_FLAG_FORCE_WC | + XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) | + XE_BO_FLAG_GGTT, + false); + } + + if (IS_ERR(obj)) { + drm_err(&xe->drm, "failed to allocate framebuffer (%pe)\n", obj); + return ERR_PTR(-ENOMEM); + } + + return &obj->ttm.base; +} + +static void xe_display_bo_fbdev_destroy(struct drm_gem_object *obj) +{ + xe_bo_unpin_map_no_vm(gem_to_xe_bo(obj)); +} + +static int xe_display_bo_fbdev_fill_info(struct drm_gem_object *_obj, struct fb_info *info, + struct i915_vma *vma) +{ + struct xe_bo *obj = gem_to_xe_bo(_obj); + struct pci_dev *pdev = to_pci_dev(_obj->dev->dev); + + if (!(obj->flags & XE_BO_FLAG_SYSTEM)) { + if (obj->flags & XE_BO_FLAG_STOLEN) + info->fix.smem_start = xe_ttm_stolen_io_offset(obj, 0); + else + info->fix.smem_start = + pci_resource_start(pdev, 2) + + xe_bo_addr(obj, 0, XE_PAGE_SIZE); + + info->fix.smem_len = obj->ttm.base.size; + } else { + /* XXX: Pure fiction, as the BO may not be physically accessible.. */ + info->fix.smem_start = 0; + info->fix.smem_len = obj->ttm.base.size; + } + XE_WARN_ON(iosys_map_is_null(&obj->vmap)); + + info->screen_base = obj->vmap.vaddr_iomem; + info->screen_size = obj->ttm.base.size; + + return 0; +} +#endif + const struct intel_display_bo_interface xe_display_bo_interface = { .is_protected = xe_display_bo_is_protected, .key_check = xe_pxp_obj_key_check, @@ -109,4 +223,10 @@ const struct intel_display_bo_interface xe_display_bo_interface = { .framebuffer_init = xe_display_bo_framebuffer_init, .framebuffer_fini = xe_display_bo_framebuffer_fini, .framebuffer_lookup = xe_display_bo_framebuffer_lookup, +#if IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION) + .fbdev_create = xe_display_bo_fbdev_create, + .fbdev_destroy = xe_display_bo_fbdev_destroy, + .fbdev_fill_info = xe_display_bo_fbdev_fill_info, + .fbdev_pitch_align = xe_display_bo_fbdev_pitch_align, +#endif }; diff --git a/drivers/gpu/drm/xe/display/xe_display_bo.h b/drivers/gpu/drm/xe/display/xe_display_bo.h index 6879c104b0b1..c72056884ff4 100644 --- a/drivers/gpu/drm/xe/display/xe_display_bo.h +++ b/drivers/gpu/drm/xe/display/xe_display_bo.h @@ -4,6 +4,12 @@ #ifndef __XE_DISPLAY_BO_H__ #define __XE_DISPLAY_BO_H__ +#include + +struct xe_device; + +bool xe_display_bo_fbdev_prefer_stolen(struct xe_device *xe, unsigned int size); + extern const struct intel_display_bo_interface xe_display_bo_interface; #endif diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index e45a1e7a4670..948446346c53 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -14,6 +14,7 @@ #include "xe_device.h" #include "xe_display_vma.h" #include "xe_ggtt.h" +#include "xe_pat.h" #include "xe_pm.h" #include "xe_vram_types.h" @@ -24,7 +25,7 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_ struct xe_device *xe = xe_bo_device(bo); struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt; u32 column, row; - u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]); + u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe_cache_pat_idx(xe, XE_CACHE_NONE)); /* TODO: Maybe rewrite so we can traverse the bo addresses sequentially, * by writing dpt/ggtt in a different order? @@ -64,7 +65,7 @@ write_dpt_remapped_linear(struct xe_bo *bo, struct iosys_map *map, struct xe_device *xe = xe_bo_device(bo); struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt; const u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, - xe->pat.idx[XE_CACHE_NONE]); + xe_cache_pat_idx(xe, XE_CACHE_NONE)); unsigned int offset = plane->offset * XE_PAGE_SIZE; unsigned int size = plane->size; @@ -87,7 +88,7 @@ write_dpt_remapped_tiled(struct xe_bo *bo, struct iosys_map *map, struct xe_device *xe = xe_bo_device(bo); struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt; const u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, - xe->pat.idx[XE_CACHE_NONE]); + xe_cache_pat_idx(xe, XE_CACHE_NONE)); unsigned int offset, column, row; for (row = 0; row < plane->height; row++) { @@ -139,22 +140,21 @@ write_dpt_remapped(struct xe_bo *bo, } } -static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb, - const struct i915_gtt_view *view, - struct i915_vma *vma, - unsigned int alignment) +static int __xe_pin_fb_vma_dpt(struct drm_gem_object *obj, + const struct intel_fb_pin_params *pin_params, + struct i915_vma *vma) { - struct xe_device *xe = to_xe_device(fb->base.dev); + struct xe_device *xe = to_xe_device(obj->dev); struct xe_tile *tile0 = xe_device_get_root_tile(xe); struct xe_ggtt *ggtt = tile0->mem.ggtt; - struct drm_gem_object *obj = intel_fb_bo(&fb->base); + const struct i915_gtt_view *view = pin_params->view; struct xe_bo *bo = gem_to_xe_bo(obj), *dpt; u32 dpt_size, size = bo->ttm.base.size; if (view->type == I915_GTT_VIEW_NORMAL) dpt_size = ALIGN(size / XE_PAGE_SIZE * 8, XE_PAGE_SIZE); else if (view->type == I915_GTT_VIEW_REMAPPED) - dpt_size = ALIGN(intel_remapped_info_size(&fb->remapped_view.gtt.remapped) * 8, + dpt_size = ALIGN(intel_remapped_info_size(&view->remapped) * 8, XE_PAGE_SIZE); else /* display uses 4K tiles instead of bytes here, convert to entries.. */ @@ -168,7 +168,7 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb, XE_BO_FLAG_VRAM0 | XE_BO_FLAG_GGTT | XE_BO_FLAG_PAGETABLE, - alignment, false); + pin_params->alignment, false); else dpt = xe_bo_create_pin_map_at_novm(xe, tile0, dpt_size, ~0ull, @@ -176,7 +176,7 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb, XE_BO_FLAG_STOLEN | XE_BO_FLAG_GGTT | XE_BO_FLAG_PAGETABLE, - alignment, false); + pin_params->alignment, false); if (IS_ERR(dpt)) dpt = xe_bo_create_pin_map_at_novm(xe, tile0, dpt_size, ~0ull, @@ -185,12 +185,12 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb, XE_BO_FLAG_GGTT | XE_BO_FLAG_PAGETABLE | XE_BO_FLAG_FORCE_WC, - alignment, false); + pin_params->alignment, false); if (IS_ERR(dpt)) return PTR_ERR(dpt); if (view->type == I915_GTT_VIEW_NORMAL) { - u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]); + u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe_cache_pat_idx(xe, XE_CACHE_NONE)); u32 x; for (x = 0; x < size / XE_PAGE_SIZE; x++) { @@ -268,14 +268,13 @@ static void write_ggtt_rotated_node(struct xe_ggtt *ggtt, struct xe_ggtt_node *n rot_info->plane[i].dst_stride); } -static int __xe_pin_fb_vma_ggtt(const struct intel_framebuffer *fb, - const struct i915_gtt_view *view, - struct i915_vma *vma, - unsigned int alignment) +static int __xe_pin_fb_vma_ggtt(struct drm_gem_object *obj, + const struct intel_fb_pin_params *pin_params, + struct i915_vma *vma) { - struct drm_gem_object *obj = intel_fb_bo(&fb->base); + const struct i915_gtt_view *view = pin_params->view; struct xe_bo *bo = gem_to_xe_bo(obj); - struct xe_device *xe = to_xe_device(fb->base.dev); + struct xe_device *xe = to_xe_device(obj->dev); struct xe_tile *tile0 = xe_device_get_root_tile(xe); struct xe_ggtt *ggtt = tile0->mem.ggtt; u64 pte, size; @@ -306,7 +305,7 @@ static int __xe_pin_fb_vma_ggtt(const struct intel_framebuffer *fb, /* display uses tiles instead of bytes here, so convert it back.. */ size = intel_rotation_info_size(&view->rotated) * XE_PAGE_SIZE; - pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]); + pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe_cache_pat_idx(xe, XE_CACHE_NONE)); vma->node = xe_ggtt_insert_node_transform(ggtt, bo, pte, ALIGN(size, align), align, view->type == I915_GTT_VIEW_NORMAL ? @@ -318,14 +317,11 @@ static int __xe_pin_fb_vma_ggtt(const struct intel_framebuffer *fb, return ret; } -static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb, - const struct i915_gtt_view *view, - unsigned int alignment) +static struct i915_vma *__xe_pin_fb_vma(struct drm_gem_object *obj, bool is_dpt, + const struct intel_fb_pin_params *pin_params) { - struct drm_device *dev = fb->base.dev; - struct xe_device *xe = to_xe_device(dev); + struct xe_device *xe = to_xe_device(obj->dev); struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); - struct drm_gem_object *obj = intel_fb_bo(&fb->base); struct xe_bo *bo = gem_to_xe_bo(obj); struct xe_validation_ctx ctx; struct drm_exec exec; @@ -336,7 +332,7 @@ static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb, refcount_set(&vma->ref, 1); if (IS_DGFX(to_xe_device(bo->ttm.base.dev)) && - intel_fb_rc_ccs_cc_plane(&fb->base) >= 0 && + pin_params->needs_cpu_lmem_access && !(bo->flags & XE_BO_FLAG_NEEDS_CPU_ACCESS)) { struct xe_vram_region *vram = xe_device_get_root_tile(xe)->mem.vram; @@ -376,10 +372,10 @@ static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb, goto err; vma->bo = bo; - if (intel_fb_uses_dpt(&fb->base)) - ret = __xe_pin_fb_vma_dpt(fb, view, vma, alignment); + if (is_dpt) + ret = __xe_pin_fb_vma_dpt(obj, pin_params, vma); else - ret = __xe_pin_fb_vma_ggtt(fb, view, vma, alignment); + ret = __xe_pin_fb_vma_ggtt(obj, pin_params, vma); if (ret) goto err_unpin; @@ -413,20 +409,17 @@ static void __xe_unpin_fb_vma(struct i915_vma *vma) } struct i915_vma * -intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, - const struct i915_gtt_view *view, - unsigned int alignment, - unsigned int phys_alignment, - unsigned int vtd_guard, - bool uses_fence, - unsigned long *out_flags) +intel_fb_pin_to_ggtt(struct drm_gem_object *obj, + const struct intel_fb_pin_params *pin_params, + int *out_fence_id) { - *out_flags = 0; + if (out_fence_id) + *out_fence_id = -1; - return __xe_pin_fb_vma(to_intel_framebuffer(fb), view, alignment); + return __xe_pin_fb_vma(obj, false, pin_params); } -void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags) +void intel_fb_unpin_vma(struct i915_vma *vma, int fence_id) { __xe_unpin_fb_vma(vma); } @@ -473,9 +466,12 @@ int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, struct drm_gem_object *obj = intel_fb_bo(fb); struct xe_bo *bo = gem_to_xe_bo(obj); struct i915_vma *vma; - struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); - unsigned int alignment = plane->min_alignment(plane, fb, 0); + struct intel_fb_pin_params pin_params = { + .view = &new_plane_state->view.gtt, + .alignment = plane->min_alignment(plane, fb, 0), + .needs_cpu_lmem_access = intel_fb_needs_cpu_access(fb), + }; if (reuse_vma(new_plane_state, old_plane_state)) return 0; @@ -483,7 +479,7 @@ int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, /* We reject creating !SCANOUT fb's, so this is weird.. */ drm_WARN_ON(bo->ttm.base.dev, !(bo->flags & XE_BO_FLAG_FORCE_WC)); - vma = __xe_pin_fb_vma(intel_fb, &new_plane_state->view.gtt, alignment); + vma = __xe_pin_fb_vma(obj, intel_fb_uses_dpt(fb), &pin_params); if (IS_ERR(vma)) return PTR_ERR(vma); diff --git a/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c b/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c index 29c72aa4b0d2..33494b86205d 100644 --- a/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c +++ b/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c @@ -37,9 +37,17 @@ static bool intel_hdcp_gsc_check_status(struct drm_device *drm) struct xe_device *xe = to_xe_device(drm); struct xe_tile *tile = xe_device_get_root_tile(xe); struct xe_gt *gt = tile->media_gt; - struct xe_gsc *gsc = >->uc.gsc; + struct xe_gsc *gsc; - if (!gsc || !xe_uc_fw_is_available(&gsc->fw)) { + if (!gt) { + drm_dbg_kms(&xe->drm, + "not checking GSC status for HDCP2.x: media GT not present or disabled\n"); + return false; + } + + gsc = >->uc.gsc; + + if (!xe_uc_fw_is_available(&gsc->fw)) { drm_dbg_kms(&xe->drm, "GSC Components not ready for HDCP2.x\n"); return false; diff --git a/drivers/gpu/drm/xe/display/xe_initial_plane.c b/drivers/gpu/drm/xe/display/xe_initial_plane.c index 8bcae552dddc..8e3c0c4b81fe 100644 --- a/drivers/gpu/drm/xe/display/xe_initial_plane.c +++ b/drivers/gpu/drm/xe/display/xe_initial_plane.c @@ -7,34 +7,16 @@ #include "regs/xe_gtt_defs.h" -#include "intel_crtc.h" -#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_pin.h" -#include "intel_fbdev_fb.h" #include "xe_bo.h" +#include "xe_display_bo.h" #include "xe_display_vma.h" #include "xe_ggtt.h" #include "xe_mmio.h" #include "xe_vram_types.h" -/* Early xe has no irq */ -static void xe_initial_plane_vblank_wait(struct drm_crtc *_crtc) -{ - struct intel_crtc *crtc = to_intel_crtc(_crtc); - struct xe_device *xe = to_xe_device(crtc->base.dev); - struct xe_reg pipe_frmtmstmp = XE_REG(i915_mmio_reg_offset(PIPE_FRMTMSTMP(crtc->pipe))); - u32 timestamp; - int ret; - - timestamp = xe_mmio_read32(xe_root_tile_mmio(xe), pipe_frmtmstmp); - - ret = xe_mmio_wait32_not(xe_root_tile_mmio(xe), pipe_frmtmstmp, ~0U, timestamp, 40000U, ×tamp, false); - if (ret < 0) - drm_warn(&xe->drm, "waiting for early vblank failed with %i\n", ret); -} - static struct xe_bo * initial_plane_bo(struct xe_device *xe, struct intel_initial_plane_config *plane_config) @@ -86,7 +68,8 @@ initial_plane_bo(struct xe_device *xe, flags |= XE_BO_FLAG_STOLEN; if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) && - !intel_fbdev_fb_prefer_stolen(&xe->drm, plane_config->size)) { + IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION) && + !xe_display_bo_fbdev_prefer_stolen(xe, plane_config->size)) { drm_info(&xe->drm, "Initial FB size exceeds half of stolen, discarding\n"); return NULL; } @@ -114,7 +97,7 @@ xe_alloc_initial_plane_obj(struct drm_device *drm, { struct xe_device *xe = to_xe_device(drm); struct drm_mode_fb_cmd2 mode_cmd = { 0 }; - struct drm_framebuffer *fb = &plane_config->fb->base; + struct drm_framebuffer *fb = plane_config->fb; struct xe_bo *bo; mode_cmd.pixel_format = fb->format->format; @@ -151,9 +134,11 @@ xe_initial_plane_setup(struct drm_plane_state *_plane_state, { struct intel_plane_state *plane_state = to_intel_plane_state(_plane_state); struct i915_vma *vma; + struct intel_fb_pin_params pin_params = { + .view = &plane_state->view.gtt, + }; - vma = intel_fb_pin_to_ggtt(fb, &plane_state->view.gtt, - 0, 0, 0, false, &plane_state->flags); + vma = intel_fb_pin_to_ggtt(intel_fb_bo(fb), &pin_params, NULL); if (IS_ERR(vma)) return PTR_ERR(vma); @@ -171,7 +156,6 @@ static void xe_plane_config_fini(struct intel_initial_plane_config *plane_config } const struct intel_display_initial_plane_interface xe_display_initial_plane_interface = { - .vblank_wait = xe_initial_plane_vblank_wait, .alloc_obj = xe_alloc_initial_plane_obj, .setup = xe_initial_plane_setup, .config_fini = xe_plane_config_fini, diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h index 1b4a7e9a703d..c4c879a9e555 100644 --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h @@ -165,9 +165,9 @@ #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3) #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0) -#define RING_MODE(base) XE_REG((base) + 0x29c) -#define GFX_DISABLE_LEGACY_MODE REG_BIT(3) +#define GFX_MODE(base) XE_REG((base) + 0x29c, XE_REG_OPTION_MASKED) #define GFX_MSIX_INTERRUPT_ENABLE REG_BIT(13) +#define GFX_DISABLE_LEGACY_MODE REG_BIT(3) #define RING_CSMQDEBUG(base) XE_REG((base) + 0x2b0) @@ -176,7 +176,6 @@ #define RING_TIMESTAMP_UDW(base) XE_REG((base) + 0x358 + 4) #define RING_VALID_MASK 0x00000001 #define RING_VALID 0x00000001 -#define STOP_RING REG_BIT(8) #define RING_CTX_TIMESTAMP(base) XE_REG((base) + 0x3a8) #define RING_CTX_TIMESTAMP_UDW(base) XE_REG((base) + 0x3ac) diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 4ebaa0888a43..16c87ce3f614 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -528,6 +528,7 @@ #define ROW_CHICKEN3 XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED) #define XE2_EUPEND_CHK_FLUSH_DIS REG_BIT(14) +#define DIS_EU_GRF_POISON_TO_LSC REG_BIT(13) #define DIS_FIX_EOT1_FLUSH REG_BIT(9) #define TDL_TSL_CHICKEN XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED) @@ -535,6 +536,9 @@ #define SLM_WMTP_RESTORE REG_BIT(11) #define RES_CHK_SPR_DIS REG_BIT(6) +#define TDL_TSL_CHICKEN2 XE_REG_MCR(0xe4cc, XE_REG_OPTION_MASKED) +#define TILEY_LOCALID REG_BIT(2) + #define ROW_CHICKEN XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED) #define UGM_BACKUP_MODE REG_BIT(13) #define MDQ_ARBITRATION_MODE REG_BIT(12) @@ -560,6 +564,7 @@ #define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3) #define TDL_CHICKEN XE_REG_MCR(0xe5f4, XE_REG_OPTION_MASKED) +#define BIT_APQ_OPT_DIS REG_BIT(14) #define QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE REG_BIT(12) #define EUSTALL_PERF_SAMPLING_DISABLE REG_BIT(5) @@ -583,7 +588,7 @@ #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32) #define LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE REG_BIT(35 - 32) -#define ROW_CHICKEN5 XE_REG_MCR(0xe7f0) +#define ROW_CHICKEN5 XE_REG_MCR(0xe7f0, XE_REG_OPTION_MASKED) #define CPSS_AWARE_DIS REG_BIT(3) #define SARB_CHICKEN1 XE_REG_MCR(0xe90c) diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h index 9d74f454d3ff..1d6b976c4de0 100644 --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h @@ -22,6 +22,7 @@ #define DISPLAY_IRQ REG_BIT(16) #define SOC_H2DMEMINT_IRQ REG_BIT(13) #define I2C_IRQ REG_BIT(12) +#define SYSCTRL_IRQ REG_BIT(11) #define GT_DW_IRQ(x) REG_BIT(x) /* diff --git a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h index 4b3c46eb858f..c63b409d7a82 100644 --- a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h @@ -27,4 +27,7 @@ #define TEMP_SIGN_MASK REG_BIT(31) #define BMG_PACKAGE_TEMPERATURE XE_REG(0x138434) +#define CRI_PACKAGE_ENERGY_STATUS XE_REG(0x138120) +#define CRI_PLATFORM_ENERGY_STATUS XE_REG(0x138458) + #endif /* _XE_PCODE_REGS_H_ */ diff --git a/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h new file mode 100644 index 000000000000..59f3f3ec59a6 --- /dev/null +++ b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ + +#ifndef _XE_SYSCTRL_REGS_H_ +#define _XE_SYSCTRL_REGS_H_ + +#include "xe_regs.h" + +#define SYSCTRL_BASE_OFFSET 0xdb000 +#define SYSCTRL_BASE (SOC_BASE + SYSCTRL_BASE_OFFSET) +#define SYSCTRL_MAILBOX_INDEX 0x03 +#define SYSCTRL_BAR_LENGTH 0x1000 + +#define SYSCTRL_MB_CTRL XE_REG(0x10) +#define SYSCTRL_MB_CTRL_RUN_BUSY REG_BIT(31) +#define SYSCTRL_MB_CTRL_IRQ REG_BIT(30) +#define SYSCTRL_MB_CTRL_RUN_BUSY_OUT REG_BIT(29) +#define SYSCTRL_MB_CTRL_PARAM3_MASK REG_GENMASK(28, 24) +#define SYSCTRL_MB_CTRL_PARAM2_MASK REG_GENMASK(23, 16) +#define SYSCTRL_MB_CTRL_PARAM1_MASK REG_GENMASK(15, 8) +#define SYSCTRL_MB_CTRL_COMMAND_MASK REG_GENMASK(7, 0) +#define SYSCTRL_MB_CTRL_CMD REG_FIELD_PREP(SYSCTRL_MB_CTRL_COMMAND_MASK, 5) + +#define SYSCTRL_MB_DATA0 XE_REG(0x14) +#define SYSCTRL_MB_DATA1 XE_REG(0x18) +#define SYSCTRL_MB_DATA2 XE_REG(0x1c) +#define SYSCTRL_MB_DATA3 XE_REG(0x20) + +#define SYSCTRL_FRAME_PHASE REG_BIT(24) +#define SYSCTRL_FRAME_CURRENT_MASK REG_GENMASK(21, 16) +#define SYSCTRL_FRAME_TOTAL_MASK REG_GENMASK(13, 8) +#define SYSCTRL_FRAME_COMMAND_MASK REG_GENMASK(7, 0) + +#endif diff --git a/drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c b/drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c index efa8963ec248..e6eaa94d4d30 100644 --- a/drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c +++ b/drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c @@ -13,11 +13,28 @@ #define TEST_MAX_VFS 63 #define TEST_VRAM 0x7a800000ull /* random size that works on 32-bit */ +static bool xe_device_is_admin_only_stub_enable(const struct xe_device *xe) +{ + return true; +} + +static bool xe_device_is_admin_only_stub_disable(const struct xe_device *xe) +{ + return false; +} + static void pf_set_admin_mode(struct xe_device *xe, bool enable) { - /* should match logic of xe_sriov_pf_admin_only() */ - xe->sriov.pf.admin_only = enable; + typeof(xe_device_is_admin_only) *stub = enable ? + xe_device_is_admin_only_stub_enable : + xe_device_is_admin_only_stub_disable; + + kunit_activate_static_stub(kunit_get_current_test(), + xe_device_is_admin_only, + *stub); + KUNIT_EXPECT_EQ(kunit_get_current_test(), enable, xe_sriov_pf_admin_only(xe)); + KUNIT_EXPECT_EQ(kunit_get_current_test(), enable, xe_device_is_admin_only(xe)); } static void pf_set_usable_vram(struct xe_device *xe, u64 usable) diff --git a/drivers/gpu/drm/xe/tests/xe_migrate.c b/drivers/gpu/drm/xe/tests/xe_migrate.c index 34e2f0f4631f..50a97705e0ac 100644 --- a/drivers/gpu/drm/xe/tests/xe_migrate.c +++ b/drivers/gpu/drm/xe/tests/xe_migrate.c @@ -9,6 +9,7 @@ #include "tests/xe_kunit_helpers.h" #include "tests/xe_pci_test.h" +#include "xe_pat.h" #include "xe_pci.h" #include "xe_pm.h" @@ -246,7 +247,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test, /* First part of the test, are we updating our pagetable bo with a new entry? */ xe_map_wr(xe, &bo->vmap, XE_PAGE_SIZE * (NUM_KERNEL_PDE - 1), u64, 0xdeaddeadbeefbeef); - expected = m->q->vm->pt_ops->pte_encode_bo(pt, 0, xe->pat.idx[XE_CACHE_WB], 0); + expected = m->q->vm->pt_ops->pte_encode_bo(pt, 0, xe_cache_pat_idx(xe, XE_CACHE_WB), 0); if (m->q->vm->flags & XE_VM_FLAG_64K) expected |= XE_PTE_PS64; if (xe_bo_is_vram(pt)) diff --git a/drivers/gpu/drm/xe/tests/xe_pci.c b/drivers/gpu/drm/xe/tests/xe_pci.c index f3179b31f13e..860409c579f8 100644 --- a/drivers/gpu/drm/xe/tests/xe_pci.c +++ b/drivers/gpu/drm/xe/tests/xe_pci.c @@ -131,12 +131,12 @@ static const char *subplatform_prefix(enum xe_subplatform s) return s == XE_SUBPLATFORM_NONE ? "" : " "; } -static const char *step_prefix(enum xe_step step) +static const char *step_prefix(enum intel_step step) { return step == STEP_NONE ? "" : " "; } -static const char *step_name(enum xe_step step) +static const char *step_name(enum intel_step step) { return step == STEP_NONE ? "" : xe_step_name(step); } diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c index a7c2dc7f224c..5ce60d161e09 100644 --- a/drivers/gpu/drm/xe/xe_bo.c +++ b/drivers/gpu/drm/xe/xe_bo.c @@ -173,19 +173,6 @@ mem_type_to_migrate(struct xe_device *xe, u32 mem_type) return tile->migrate; } -static struct xe_vram_region *res_to_mem_region(struct ttm_resource *res) -{ - struct xe_device *xe = ttm_to_xe_device(res->bo->bdev); - struct ttm_resource_manager *mgr; - struct xe_ttm_vram_mgr *vram_mgr; - - xe_assert(xe, resource_is_vram(res)); - mgr = ttm_manager_type(&xe->ttm, res->mem_type); - vram_mgr = to_xe_ttm_vram_mgr(mgr); - - return container_of(vram_mgr, struct xe_vram_region, ttm); -} - static void try_add_system(struct xe_device *xe, struct xe_bo *bo, u32 bo_flags, u32 *c) { @@ -635,7 +622,7 @@ static int xe_ttm_io_mem_reserve(struct ttm_device *bdev, return 0; case XE_PL_VRAM0: case XE_PL_VRAM1: { - struct xe_vram_region *vram = res_to_mem_region(mem); + struct xe_vram_region *vram = xe_map_resource_to_region(mem); if (!xe_ttm_resource_visible(mem)) return -EINVAL; @@ -1642,7 +1629,7 @@ static unsigned long xe_ttm_io_mem_pfn(struct ttm_buffer_object *ttm_bo, if (ttm_bo->resource->mem_type == XE_PL_STOLEN) return xe_ttm_stolen_io_offset(bo, page_offset << PAGE_SHIFT) >> PAGE_SHIFT; - vram = res_to_mem_region(ttm_bo->resource); + vram = xe_map_resource_to_region(ttm_bo->resource); xe_res_first(ttm_bo->resource, (u64)page_offset << PAGE_SHIFT, 0, &cursor); return (vram->io_start + cursor.start) >> PAGE_SHIFT; } @@ -1782,7 +1769,7 @@ static int xe_ttm_access_memory(struct ttm_buffer_object *ttm_bo, goto out; } - vram = res_to_mem_region(ttm_bo->resource); + vram = xe_map_resource_to_region(ttm_bo->resource); xe_res_first(ttm_bo->resource, offset & PAGE_MASK, xe_bo_size(bo) - (offset & PAGE_MASK), &cursor); @@ -2322,8 +2309,10 @@ struct xe_bo *xe_bo_init_locked(struct xe_device *xe, struct xe_bo *bo, } /* XE_BO_FLAG_GGTTx requires XE_BO_FLAG_GGTT also be set */ - if ((flags & XE_BO_FLAG_GGTT_ALL) && !(flags & XE_BO_FLAG_GGTT)) + if ((flags & XE_BO_FLAG_GGTT_ALL) && !(flags & XE_BO_FLAG_GGTT)) { + xe_bo_free(bo); return ERR_PTR(-EINVAL); + } if (flags & (XE_BO_FLAG_VRAM_MASK | XE_BO_FLAG_STOLEN) && !(flags & XE_BO_FLAG_IGNORE_MIN_PAGE_SIZE) && @@ -2342,8 +2331,10 @@ struct xe_bo *xe_bo_init_locked(struct xe_device *xe, struct xe_bo *bo, alignment = SZ_4K >> PAGE_SHIFT; } - if (type == ttm_bo_type_device && aligned_size != size) + if (type == ttm_bo_type_device && aligned_size != size) { + xe_bo_free(bo); return ERR_PTR(-EINVAL); + } if (!bo) { bo = xe_bo_alloc(); @@ -2923,7 +2914,7 @@ uint64_t vram_region_gpu_offset(struct ttm_resource *res) case XE_PL_SYSTEM: return 0; default: - return res_to_mem_region(res)->dpa_base; + return xe_map_resource_to_region(res)->dpa_base; } return 0; } diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h index ff8317bfc1ae..9c199badd9b2 100644 --- a/drivers/gpu/drm/xe/xe_bo_types.h +++ b/drivers/gpu/drm/xe/xe_bo_types.h @@ -18,6 +18,7 @@ #include "xe_ggtt_types.h" struct xe_device; +struct xe_mem_pool_node; struct xe_vm; #define XE_BO_MAX_PLACEMENTS 3 @@ -66,7 +67,7 @@ struct xe_bo { /** @attr: User controlled attributes for bo */ struct { /** - * @atomic_access: type of atomic access bo needs + * @attr.atomic_access: type of atomic access bo needs * protected by bo dma-resv lock */ u32 atomic_access; @@ -88,7 +89,7 @@ struct xe_bo { bool ccs_cleared; /** @bb_ccs: BB instructions of CCS read/write. Valid only for VF */ - struct xe_bb *bb_ccs[XE_SRIOV_VF_CCS_CTX_COUNT]; + struct xe_mem_pool_node *bb_ccs[XE_SRIOV_VF_CCS_CTX_COUNT]; /** * @cpu_caching: CPU caching mode. Currently only used for userspace diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c index ad2d8f179eb6..22b471303984 100644 --- a/drivers/gpu/drm/xe/xe_debugfs.c +++ b/drivers/gpu/drm/xe/xe_debugfs.c @@ -15,9 +15,11 @@ #include "xe_bo.h" #include "xe_device.h" #include "xe_force_wake.h" +#include "xe_gt.h" #include "xe_gt_debugfs.h" #include "xe_gt_printk.h" #include "xe_guc_ads.h" +#include "xe_hw_engine.h" #include "xe_mmio.h" #include "xe_pm.h" #include "xe_psmi.h" @@ -61,6 +63,37 @@ static struct xe_device *node_to_xe(struct drm_info_node *node) return to_xe_device(node->minor->dev); } +static void print_engine_class_mask(struct drm_printer *p, u16 mask) +{ + if (!mask) { + drm_printf(p, " none\n"); + return; + } + + for (enum xe_engine_class ec = 0; ec < XE_ENGINE_CLASS_MAX; ec++) { + if (mask & BIT(ec)) + drm_printf(p, " %s", xe_hw_engine_class_to_str(ec)); + } + drm_printf(p, "\n"); +} + +static void print_engine_mask(struct drm_printer *p, struct xe_gt *gt, u64 mask) +{ + struct xe_hw_engine *hwe; + enum xe_hw_engine_id id; + + if (!mask) { + drm_printf(p, " none\n"); + return; + } + + for_each_hw_engine(hwe, gt, id) { + if (mask & BIT_ULL(id)) + drm_printf(p, " %s", hwe->name); + } + drm_printf(p, "\n"); +} + static int info(struct seq_file *m, void *data) { struct xe_device *xe = node_to_xe(m->private); @@ -88,13 +121,15 @@ static int info(struct seq_file *m, void *data) drm_printf(&p, "has_flat_ccs %s\n", str_yes_no(xe->info.has_flat_ccs)); drm_printf(&p, "has_usm %s\n", str_yes_no(xe->info.has_usm)); drm_printf(&p, "skip_guc_pc %s\n", str_yes_no(xe->info.skip_guc_pc)); + drm_printf(&p, "multi_lrc_engine_classes"); + print_engine_class_mask(&p, xe->info.multi_lrc_mask); for_each_gt(gt, xe, id) { drm_printf(&p, "gt%d force wake %d\n", id, xe_force_wake_ref(gt_to_fw(gt), XE_FW_GT)); - drm_printf(&p, "gt%d engine_mask 0x%llx\n", id, - gt->info.engine_mask); - drm_printf(&p, "gt%d multi_queue_engine_class_mask 0x%x\n", id, - gt->info.multi_queue_engine_class_mask); + drm_printf(&p, "gt%d engines", id); + print_engine_mask(&p, gt, gt->info.engine_mask); + drm_printf(&p, "gt%d multi_queue_engine_classes", id); + print_engine_class_mask(&p, gt->info.multi_queue_engine_class_mask); } return 0; diff --git a/drivers/gpu/drm/xe/xe_dep_scheduler.h b/drivers/gpu/drm/xe/xe_dep_scheduler.h index 853961eec64b..f314fb5d80f5 100644 --- a/drivers/gpu/drm/xe/xe_dep_scheduler.h +++ b/drivers/gpu/drm/xe/xe_dep_scheduler.h @@ -3,6 +3,9 @@ * Copyright © 2025 Intel Corporation */ +#ifndef _XE_DEP_SCHEDULER_H_ +#define _XE_DEP_SCHEDULER_H_ + #include struct drm_sched_entity; @@ -19,3 +22,5 @@ void xe_dep_scheduler_fini(struct xe_dep_scheduler *dep_scheduler); struct drm_sched_entity * xe_dep_scheduler_entity(struct xe_dep_scheduler *dep_scheduler); + +#endif diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c index 558a1a9841a0..5f2b90b18f97 100644 --- a/drivers/gpu/drm/xe/xe_devcoredump.c +++ b/drivers/gpu/drm/xe/xe_devcoredump.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include @@ -101,7 +101,7 @@ static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count, drm_puts(&p, "**** Xe Device Coredump ****\n"); drm_printf(&p, "Reason: %s\n", ss->reason); - drm_puts(&p, "kernel: " UTS_RELEASE "\n"); + drm_printf(&p, "kernel: %s\n", init_utsname()->release); drm_puts(&p, "module: " KBUILD_MODNAME "\n"); ts = ktime_to_timespec64(ss->snapshot_time); @@ -149,7 +149,8 @@ static void xe_devcoredump_snapshot_free(struct xe_devcoredump_snapshot *ss) xe_guc_ct_snapshot_free(ss->guc.ct); ss->guc.ct = NULL; - xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc); + if (!IS_ERR_OR_NULL(ss->gt)) + xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc); ss->matched_node = NULL; xe_guc_exec_queue_snapshot_free(ss->ge); @@ -254,7 +255,8 @@ static void xe_devcoredump_free(void *data) if (!data || !coredump_to_xe(coredump)) return; - cancel_work_sync(&coredump->snapshot.work); + if (coredump->captured) + cancel_work_sync(&coredump->snapshot.work); mutex_lock(&coredump->lock); diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index ffea4a453c01..4b45b617a039 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "display/xe_display.h" @@ -25,6 +26,7 @@ #include "regs/xe_regs.h" #include "xe_bo.h" #include "xe_bo_evict.h" +#include "xe_configfs.h" #include "xe_debugfs.h" #include "xe_defaults.h" #include "xe_devcoredump.h" @@ -65,6 +67,7 @@ #include "xe_survivability_mode.h" #include "xe_sriov.h" #include "xe_svm.h" +#include "xe_sysctrl.h" #include "xe_tile.h" #include "xe_ttm_stolen_mgr.h" #include "xe_ttm_sys_mgr.h" @@ -389,7 +392,7 @@ bool xe_is_xe_file(const struct file *file) return file->f_op == &xe_driver_fops; } -static struct drm_driver driver = { +static struct drm_driver regular_driver = { .driver_features = DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | @@ -414,6 +417,40 @@ static struct drm_driver driver = { .patchlevel = DRIVER_PATCHLEVEL, }; +#ifdef CONFIG_PCI_IOV +static const struct drm_ioctl_desc xe_ioctls_admin_only[] = { + DRM_IOCTL_DEF_DRV(XE_DEVICE_QUERY, xe_query_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(XE_OBSERVATION, xe_observation_ioctl, DRM_RENDER_ALLOW), +}; + +static struct drm_driver admin_only_driver = { + .driver_features = + DRIVER_GEM | DRIVER_RENDER | DRIVER_GEM_GPUVA, + .open = xe_file_open, + .postclose = xe_file_close, + .ioctls = xe_ioctls_admin_only, + .num_ioctls = ARRAY_SIZE(xe_ioctls_admin_only), + .fops = &xe_driver_fops, + .name = DRIVER_NAME, + .desc = DRIVER_DESC, + .major = DRIVER_MAJOR, + .minor = DRIVER_MINOR, + .patchlevel = DRIVER_PATCHLEVEL, +}; + +/** + * xe_device_is_admin_only() - Check whether device is admin only or not. + * @xe: the &xe_device to check + * + * Return: true if the device is admin only, false otherwise. + */ +bool xe_device_is_admin_only(const struct xe_device *xe) +{ + KUNIT_STATIC_STUB_REDIRECT(xe_device_is_admin_only, xe); + return xe->drm.driver == &admin_only_driver; +} +#endif + static void xe_device_destroy(struct drm_device *dev, void *dummy) { struct xe_device *xe = to_xe_device(dev); @@ -438,16 +475,26 @@ static void xe_device_destroy(struct drm_device *dev, void *dummy) struct xe_device *xe_device_create(struct pci_dev *pdev, const struct pci_device_id *ent) { + struct drm_driver *driver = ®ular_driver; struct xe_device *xe; int err; - xe_display_driver_set_hooks(&driver); +#ifdef CONFIG_PCI_IOV + /* + * Since XE device is not initialized yet, read from configfs + * directly to decide whether we are in admin-only PF mode or not. + */ + if (xe_configfs_admin_only_pf(pdev)) + driver = &admin_only_driver; +#endif - err = aperture_remove_conflicting_pci_devices(pdev, driver.name); + xe_display_driver_set_hooks(driver); + + err = aperture_remove_conflicting_pci_devices(pdev, driver->name); if (err) return ERR_PTR(err); - xe = devm_drm_dev_alloc(&pdev->dev, &driver, struct xe_device, drm); + xe = devm_drm_dev_alloc(&pdev->dev, driver, struct xe_device, drm); if (IS_ERR(xe)) return xe; @@ -707,6 +754,11 @@ int xe_device_probe_early(struct xe_device *xe) xe_sriov_probe_early(xe); + if (xe_device_is_admin_only(xe) && !IS_SRIOV_PF(xe)) { + xe_err(xe, "Can't run Admin-only mode without SR-IOV PF mode!\n"); + return -ENODEV; + } + if (IS_SRIOV_VF(xe)) vf_update_device_info(xe); @@ -992,6 +1044,10 @@ int xe_device_probe(struct xe_device *xe) if (err) goto err_unregister_display; + err = xe_sysctrl_init(xe); + if (err) + goto err_unregister_display; + err = xe_device_sysfs_init(xe); if (err) goto err_unregister_display; diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h index e4b9de8d8e95..355d69dc8f54 100644 --- a/drivers/gpu/drm/xe/xe_device.h +++ b/drivers/gpu/drm/xe/xe_device.h @@ -146,37 +146,37 @@ static inline struct xe_force_wake *gt_to_fw(struct xe_gt *gt) void xe_device_assert_mem_access(struct xe_device *xe); -static inline bool xe_device_has_flat_ccs(struct xe_device *xe) +static inline bool xe_device_has_flat_ccs(const struct xe_device *xe) { return xe->info.has_flat_ccs; } -static inline bool xe_device_has_sriov(struct xe_device *xe) +static inline bool xe_device_has_sriov(const struct xe_device *xe) { return xe->info.has_sriov; } -static inline bool xe_device_has_msix(struct xe_device *xe) +static inline bool xe_device_has_msix(const struct xe_device *xe) { return xe->irq.msix.nvec > 0; } -static inline bool xe_device_has_memirq(struct xe_device *xe) +static inline bool xe_device_has_memirq(const struct xe_device *xe) { return GRAPHICS_VERx100(xe) >= 1250; } -static inline bool xe_device_uses_memirq(struct xe_device *xe) +static inline bool xe_device_uses_memirq(const struct xe_device *xe) { return xe_device_has_memirq(xe) && (IS_SRIOV_VF(xe) || xe_device_has_msix(xe)); } -static inline bool xe_device_has_lmtt(struct xe_device *xe) +static inline bool xe_device_has_lmtt(const struct xe_device *xe) { return IS_DGFX(xe); } -static inline bool xe_device_has_mert(struct xe_device *xe) +static inline bool xe_device_has_mert(const struct xe_device *xe) { return xe->info.has_mert; } @@ -211,6 +211,15 @@ bool xe_is_xe_file(const struct file *file); struct xe_vm *xe_device_asid_to_vm(struct xe_device *xe, u32 asid); +#ifdef CONFIG_PCI_IOV +bool xe_device_is_admin_only(const struct xe_device *xe); +#else +static inline bool xe_device_is_admin_only(const struct xe_device *xe) +{ + return false; +} +#endif + /* * Occasionally it is seen that the G2H worker starts running after a delay of more than * a second even after being queued and activated by the Linux workqueue subsystem. This diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index 615218d775b1..89437de3001a 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -27,6 +27,7 @@ #include "xe_sriov_vf_ccs_types.h" #include "xe_step_types.h" #include "xe_survivability_mode_types.h" +#include "xe_sysctrl_types.h" #include "xe_tile_types.h" #include "xe_validation.h" @@ -196,6 +197,8 @@ struct xe_device { u8 has_soc_remapper_telem:1; /** @info.has_sriov: Supports SR-IOV */ u8 has_sriov:1; + /** @info.has_sysctrl: Supports System Controller */ + u8 has_sysctrl:1; /** @info.has_usm: Device has unified shared memory support */ u8 has_usm:1; /** @info.has_64bit_timestamp: Device supports 64-bit timestamps */ @@ -215,8 +218,6 @@ struct xe_device { u8 probe_display:1; /** @info.skip_guc_pc: Skip GuC based PM feature init */ u8 skip_guc_pc:1; - /** @info.skip_mtcfg: skip Multi-Tile configuration from MTCFG register */ - u8 skip_mtcfg:1; /** @info.skip_pcode: skip access to PCODE uC */ u8 skip_pcode:1; /** @info.needs_shared_vf_gt_wq: needs shared GT WQ on VF */ @@ -273,7 +274,7 @@ struct xe_device { struct xe_vram_region *vram; /** @mem.sys_mgr: system TTM manager */ struct ttm_resource_manager sys_mgr; - /** @mem.sys_mgr: system memory shrinker. */ + /** @mem.shrinker: system memory shrinker. */ struct xe_shrinker *shrinker; } mem; @@ -295,7 +296,7 @@ struct xe_device { /** @usm: unified memory state */ struct { - /** @usm.asid: convert a ASID to VM */ + /** @usm.asid_to_vm: convert an ASID to VM */ struct xarray asid_to_vm; /** @usm.next_asid: next ASID, used to cyclical alloc asids */ u32 next_asid; @@ -312,7 +313,7 @@ struct xe_device { /** @usm.pf_queue: Page fault queues */ struct xe_pagefault_queue pf_queue[XE_PAGEFAULT_QUEUE_COUNT]; #if IS_ENABLED(CONFIG_DRM_XE_PAGEMAP) - /** @usm.pagemap_shrinker: Shrinker for unused pagemaps */ + /** @usm.dpagemap_shrinker: Shrinker for unused pagemaps */ struct drm_pagemap_shrinker *dpagemap_shrinker; #endif } usm; @@ -334,7 +335,7 @@ struct xe_device { struct list_head kernel_bo_present; /** @pinned.late.evicted: pinned BO that have been evicted */ struct list_head evicted; - /** @pinned.external: pinned external and dma-buf. */ + /** @pinned.late.external: pinned external and dma-buf. */ struct list_head external; } late; } pinned; @@ -369,7 +370,7 @@ struct xe_device { struct { /** * @mem_access.vram_userfault.lock: Protects access to - * @vram_usefault.list Using mutex instead of spinlock + * @mem_access.vram_userfault.list Using mutex instead of spinlock * as lock is applied to entire list operation which * may sleep */ @@ -400,7 +401,7 @@ struct xe_device { const struct xe_pat_table_entry *pat_primary_pta; /** @pat.pat_media_pta: media GT PAT entry for page table accesses */ const struct xe_pat_table_entry *pat_media_pta; - u32 idx[__XE_CACHE_LEVEL_COUNT]; + u16 idx[__XE_CACHE_LEVEL_COUNT]; } pat; /** @d3cold: Encapsulate d3cold related stuff */ @@ -508,6 +509,9 @@ struct xe_device { /** @i2c: I2C host controller */ struct xe_i2c *i2c; + /** @sc: System Controller */ + struct xe_sysctrl sc; + /** @atomic_svm_timeslice_ms: Atomic SVM fault timeslice MS */ u32 atomic_svm_timeslice_ms; @@ -578,7 +582,7 @@ struct xe_file { /** @vm: VM state for file */ struct { - /** @vm.xe: xarray to store VMs */ + /** @vm.xa: xarray to store VMs */ struct xarray xa; /** * @vm.lock: Protects VM lookup + reference and removal from diff --git a/drivers/gpu/drm/xe/xe_device_wa_oob.rules b/drivers/gpu/drm/xe/xe_device_wa_oob.rules index d129cddb6ead..92371c490529 100644 --- a/drivers/gpu/drm/xe/xe_device_wa_oob.rules +++ b/drivers/gpu/drm/xe/xe_device_wa_oob.rules @@ -4,3 +4,4 @@ 22019338487_display PLATFORM(LUNARLAKE) 14022085890 SUBPLATFORM(BATTLEMAGE, G21) 14026539277 PLATFORM(NOVALAKE_P), PLATFORM_STEP(A0, B0) +14026633728 PLATFORM(CRESCENTISLAND) diff --git a/drivers/gpu/drm/xe/xe_dma_buf.c b/drivers/gpu/drm/xe/xe_dma_buf.c index 7f9602b3363d..b9828da15897 100644 --- a/drivers/gpu/drm/xe/xe_dma_buf.c +++ b/drivers/gpu/drm/xe/xe_dma_buf.c @@ -258,6 +258,13 @@ struct dma_buf *xe_gem_prime_export(struct drm_gem_object *obj, int flags) return ERR_PTR(ret); } +/* + * Takes ownership of @storage: on success it is transferred to the returned + * drm_gem_object; on failure it is freed before returning the error. + * This matches the contract of xe_bo_init_locked() which frees @storage on + * its error paths, so callers need not (and must not) free @storage after + * this call. + */ static struct drm_gem_object * xe_dma_buf_init_obj(struct drm_device *dev, struct xe_bo *storage, struct dma_buf *dma_buf) @@ -271,8 +278,10 @@ xe_dma_buf_init_obj(struct drm_device *dev, struct xe_bo *storage, int ret = 0; dummy_obj = drm_gpuvm_resv_object_alloc(&xe->drm); - if (!dummy_obj) + if (!dummy_obj) { + xe_bo_free(storage); return ERR_PTR(-ENOMEM); + } dummy_obj->resv = resv; xe_validation_guard(&ctx, &xe->val, &exec, (struct xe_val_flags) {}, ret) { @@ -281,6 +290,7 @@ xe_dma_buf_init_obj(struct drm_device *dev, struct xe_bo *storage, if (ret) break; + /* xe_bo_init_locked() frees storage on error */ bo = xe_bo_init_locked(xe, storage, NULL, resv, NULL, dma_buf->size, 0, /* Will require 1way or 2way for vm_bind */ ttm_bo_type_sg, XE_BO_FLAG_SYSTEM, &exec); @@ -368,12 +378,15 @@ struct drm_gem_object *xe_gem_prime_import(struct drm_device *dev, goto out_err; } - /* Errors here will take care of freeing the bo. */ + /* + * xe_dma_buf_init_obj() takes ownership of bo on both success + * and failure, so we must not touch bo after this call. + */ obj = xe_dma_buf_init_obj(dev, bo, dma_buf); - if (IS_ERR(obj)) + if (IS_ERR(obj)) { + dma_buf_detach(dma_buf, attach); return obj; - - + } get_dma_buf(dma_buf); obj->import_attach = attach; return obj; diff --git a/drivers/gpu/drm/xe/xe_drm_ras.c b/drivers/gpu/drm/xe/xe_drm_ras.c index e07dc23a155e..c21c8b428de6 100644 --- a/drivers/gpu/drm/xe/xe_drm_ras.c +++ b/drivers/gpu/drm/xe/xe_drm_ras.c @@ -27,6 +27,16 @@ static int hw_query_error_counter(struct xe_drm_ras_counter *info, return 0; } +static int hw_clear_error_counter(struct xe_drm_ras_counter *info, u32 error_id) +{ + if (!info || !info[error_id].name) + return -ENOENT; + + atomic_set(&info[error_id].counter, 0); + + return 0; +} + static int query_uncorrectable_error_counter(struct drm_ras_node *ep, u32 error_id, const char **name, u32 *val) { @@ -37,6 +47,15 @@ static int query_uncorrectable_error_counter(struct drm_ras_node *ep, u32 error_ return hw_query_error_counter(info, error_id, name, val); } +static int clear_uncorrectable_error_counter(struct drm_ras_node *node, u32 error_id) +{ + struct xe_device *xe = node->priv; + struct xe_drm_ras *ras = &xe->ras; + struct xe_drm_ras_counter *info = ras->info[DRM_XE_RAS_ERR_SEV_UNCORRECTABLE]; + + return hw_clear_error_counter(info, error_id); +} + static int query_correctable_error_counter(struct drm_ras_node *ep, u32 error_id, const char **name, u32 *val) { @@ -47,6 +66,15 @@ static int query_correctable_error_counter(struct drm_ras_node *ep, u32 error_id return hw_query_error_counter(info, error_id, name, val); } +static int clear_correctable_error_counter(struct drm_ras_node *node, u32 error_id) +{ + struct xe_device *xe = node->priv; + struct xe_drm_ras *ras = &xe->ras; + struct xe_drm_ras_counter *info = ras->info[DRM_XE_RAS_ERR_SEV_CORRECTABLE]; + + return hw_clear_error_counter(info, error_id); +} + static struct xe_drm_ras_counter *allocate_and_copy_counters(struct xe_device *xe) { struct xe_drm_ras_counter *counter; @@ -92,10 +120,13 @@ static int assign_node_params(struct xe_device *xe, struct drm_ras_node *node, if (IS_ERR(ras->info[severity])) return PTR_ERR(ras->info[severity]); - if (severity == DRM_XE_RAS_ERR_SEV_CORRECTABLE) + if (severity == DRM_XE_RAS_ERR_SEV_CORRECTABLE) { node->query_error_counter = query_correctable_error_counter; - else + node->clear_error_counter = clear_correctable_error_counter; + } else { node->query_error_counter = query_uncorrectable_error_counter; + node->clear_error_counter = clear_uncorrectable_error_counter; + } return 0; } diff --git a/drivers/gpu/drm/xe/xe_drm_ras.h b/drivers/gpu/drm/xe/xe_drm_ras.h index 5cc8f0124411..365c70e93e82 100644 --- a/drivers/gpu/drm/xe/xe_drm_ras.h +++ b/drivers/gpu/drm/xe/xe_drm_ras.h @@ -2,8 +2,8 @@ /* * Copyright © 2026 Intel Corporation */ -#ifndef XE_DRM_RAS_H_ -#define XE_DRM_RAS_H_ +#ifndef _XE_DRM_RAS_H_ +#define _XE_DRM_RAS_H_ struct xe_device; diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c index c34408cfd292..dddcdd0bb7a3 100644 --- a/drivers/gpu/drm/xe/xe_eu_stall.c +++ b/drivers/gpu/drm/xe/xe_eu_stall.c @@ -869,14 +869,14 @@ static int xe_eu_stall_stream_close(struct inode *inode, struct file *file) struct xe_eu_stall_data_stream *stream = file->private_data; struct xe_gt *gt = stream->gt; - drm_dev_put(>->tile->xe->drm); - mutex_lock(>->eu_stall->stream_lock); xe_eu_stall_disable_locked(stream); xe_eu_stall_data_buf_destroy(stream); xe_eu_stall_stream_free(stream); mutex_unlock(>->eu_stall->stream_lock); + drm_dev_put(>->tile->xe->drm); + return 0; } diff --git a/drivers/gpu/drm/xe/xe_eu_stall.h b/drivers/gpu/drm/xe/xe_eu_stall.h index d1c76e503799..842bef9f6872 100644 --- a/drivers/gpu/drm/xe/xe_eu_stall.h +++ b/drivers/gpu/drm/xe/xe_eu_stall.h @@ -3,8 +3,8 @@ * Copyright © 2025 Intel Corporation */ -#ifndef __XE_EU_STALL_H__ -#define __XE_EU_STALL_H__ +#ifndef _XE_EU_STALL_H_ +#define _XE_EU_STALL_H_ #include "xe_gt_types.h" #include "xe_sriov.h" diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c index b287d0e0e60a..071b8c41df43 100644 --- a/drivers/gpu/drm/xe/xe_exec_queue.c +++ b/drivers/gpu/drm/xe/xe_exec_queue.c @@ -1405,7 +1405,7 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data, if (q->vm && q->hwe->hw_engine_group) { err = xe_hw_engine_group_add_exec_queue(q->hwe->hw_engine_group, q); if (err) - goto put_exec_queue; + goto kill_exec_queue; } } @@ -1416,12 +1416,15 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data, /* user id alloc must always be last in ioctl to prevent UAF */ err = xa_alloc(&xef->exec_queue.xa, &id, q, xa_limit_32b, GFP_KERNEL); if (err) - goto kill_exec_queue; + goto del_hw_engine_group; args->exec_queue_id = id; return 0; +del_hw_engine_group: + if (q->vm && q->hwe && q->hwe->hw_engine_group) + xe_hw_engine_group_del_exec_queue(q->hwe->hw_engine_group, q); kill_exec_queue: xe_exec_queue_kill(q); delete_queue_group: @@ -1760,7 +1763,7 @@ void xe_exec_queue_tlb_inval_last_fence_put(struct xe_exec_queue *q, void xe_exec_queue_tlb_inval_last_fence_put_unlocked(struct xe_exec_queue *q, unsigned int type) { - xe_assert(q->vm->xe, type == XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT || + xe_assert(gt_to_xe(q->gt), type == XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT || type == XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT); dma_fence_put(q->tlb_inval[type].last_fence); diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h index 8ce78e0b1d50..2f5ccf294675 100644 --- a/drivers/gpu/drm/xe/xe_exec_queue_types.h +++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h @@ -214,7 +214,7 @@ struct xe_exec_queue { */ struct xe_dep_scheduler *dep_scheduler; /** - * @last_fence: last fence for tlb invalidation, protected by + * @tlb_inval.last_fence: last fence for tlb invalidation, protected by * vm->lock in write mode */ struct dma_fence *last_fence; diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c index 1f8d358e60fd..9fb99c038ea8 100644 --- a/drivers/gpu/drm/xe/xe_execlist.c +++ b/drivers/gpu/drm/xe/xe_execlist.c @@ -47,7 +47,6 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc, struct xe_mmio *mmio = >->mmio; struct xe_device *xe = gt_to_xe(gt); u64 lrc_desc; - u32 ring_mode = REG_MASKED_FIELD_ENABLE(GFX_DISABLE_LEGACY_MODE); lrc_desc = xe_lrc_descriptor(lrc); @@ -59,10 +58,6 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc, lrc_desc |= FIELD_PREP(SW_CTX_ID, ctx_id); } - if (hwe->class == XE_ENGINE_CLASS_COMPUTE) - xe_mmio_write32(mmio, RCU_MODE, - REG_MASKED_FIELD_ENABLE(RCU_MODE_CCS_ENABLE)); - xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail); lrc->ring.old_tail = lrc->ring.tail; @@ -82,10 +77,6 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc, xe_bo_ggtt_addr(hwe->hwsp)); xe_mmio_read32(mmio, RING_HWS_PGA(hwe->mmio_base)); - if (xe_device_has_msix(gt_to_xe(hwe->gt))) - ring_mode |= REG_MASKED_FIELD_ENABLE(GFX_MSIX_INTERRUPT_ENABLE); - xe_mmio_write32(mmio, RING_MODE(hwe->mmio_base), ring_mode); - xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base), lower_32_bits(lrc_desc)); xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base), diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c index a848d1a41b9b..a351c578b170 100644 --- a/drivers/gpu/drm/xe/xe_ggtt.c +++ b/drivers/gpu/drm/xe/xe_ggtt.c @@ -24,6 +24,7 @@ #include "xe_gt_types.h" #include "xe_map.h" #include "xe_mmio.h" +#include "xe_pat.h" #include "xe_pm.h" #include "xe_res_cursor.h" #include "xe_sriov.h" @@ -115,7 +116,6 @@ struct xe_ggtt { /** @size: Total usable size of this GGTT */ u64 size; -#define XE_GGTT_FLAGS_64K BIT(0) /** * @flags: Flags for this GGTT * Acceptable flags: @@ -259,7 +259,7 @@ static u64 xe_ggtt_get_pte(struct xe_ggtt *ggtt, u64 addr) static void xe_ggtt_clear(struct xe_ggtt *ggtt, u64 start, u64 size) { - u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[XE_CACHE_WB]; + u16 pat_index = xe_cache_pat_idx(tile_to_xe(ggtt->tile), XE_CACHE_WB); u64 end = start + size - 1; u64 scratch_pte; @@ -724,7 +724,7 @@ static void xe_ggtt_map_bo(struct xe_ggtt *ggtt, struct xe_ggtt_node *node, void xe_ggtt_map_bo_unlocked(struct xe_ggtt *ggtt, struct xe_bo *bo) { u16 cache_mode = bo->flags & XE_BO_FLAG_NEEDS_UC ? XE_CACHE_NONE : XE_CACHE_WB; - u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[cache_mode]; + u16 pat_index = xe_cache_pat_idx(tile_to_xe(ggtt->tile), cache_mode); u64 pte; mutex_lock(&ggtt->lock); @@ -841,7 +841,7 @@ static int __xe_ggtt_insert_bo_at(struct xe_ggtt *ggtt, struct xe_bo *bo, bo->ggtt_node[tile_id] = NULL; } else { u16 cache_mode = bo->flags & XE_BO_FLAG_NEEDS_UC ? XE_CACHE_NONE : XE_CACHE_WB; - u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[cache_mode]; + u16 pat_index = xe_cache_pat_idx(tile_to_xe(ggtt->tile), cache_mode); u64 pte = ggtt->pt_ops->pte_encode_flags(bo, pat_index); xe_ggtt_map_bo(ggtt, bo->ggtt_node[tile_id], bo, pte); diff --git a/drivers/gpu/drm/xe/xe_gsc.c b/drivers/gpu/drm/xe/xe_gsc.c index e5c234f3d795..0d13e357fb43 100644 --- a/drivers/gpu/drm/xe/xe_gsc.c +++ b/drivers/gpu/drm/xe/xe_gsc.c @@ -166,7 +166,7 @@ static int query_compatibility_version(struct xe_gsc *gsc) &rd_offset); if (err) { xe_gt_err(gt, "HuC: invalid GSC reply for version query (err=%d)\n", err); - return err; + goto out_bo; } compat->major = version_query_rd(xe, &bo->vmap, rd_offset, proj_major); diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index 8a31c963c372..cdc678d1ae1f 100644 --- a/drivers/gpu/drm/xe/xe_gt.c +++ b/drivers/gpu/drm/xe/xe_gt.c @@ -993,7 +993,6 @@ void xe_gt_reset_async(struct xe_gt *gt) void xe_gt_suspend_prepare(struct xe_gt *gt) { - CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); xe_uc_suspend_prepare(>->uc); } diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c index 7c6f039c880d..df281688c617 100644 --- a/drivers/gpu/drm/xe/xe_gt_mcr.c +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c @@ -216,9 +216,7 @@ static const struct xe_mmio_range xe2lpg_sqidi_psmi_steering_table[] = { static const struct xe_mmio_range xe2lpg_instance0_steering_table[] = { { 0x004000, 0x004AFF }, /* GAM, rsvd, GAMWKR */ { 0x008700, 0x00887F }, /* SQIDI, MEMPIPE */ - { 0x00B000, 0x00B3FF }, /* NODE, L3BANK */ { 0x00C800, 0x00CFFF }, /* GAM */ - { 0x00D880, 0x00D8FF }, /* NODE */ { 0x00DD00, 0x00DDFF }, /* MEMPIPE */ { 0x00E900, 0x00E97F }, /* MEMPIPE */ { 0x00F000, 0x00FFFF }, /* GAM, GAMWKR */ @@ -267,7 +265,7 @@ static const struct xe_mmio_range xe3p_xpc_gam_grp1_steering_table[] = { {}, }; -static const struct xe_mmio_range xe3p_xpc_node_steering_table[] = { +static const struct xe_mmio_range xe2_node_steering_table[] = { { 0x00B000, 0x00B0FF }, { 0x00D880, 0x00D8FF }, {}, @@ -298,7 +296,7 @@ static void init_steering_l3bank(struct xe_gt *gt) struct xe_device *xe = gt_to_xe(gt); struct xe_mmio *mmio = >->mmio; - if (GRAPHICS_VER(xe) >= 35) { + if (GRAPHICS_VER(xe) >= 20) { unsigned int first_bank = xe_l3_bank_mask_ffs(gt->fuse_topo.l3_bank_mask); const int banks_per_node = 4; unsigned int node = first_bank / banks_per_node; @@ -430,19 +428,6 @@ void xe_gt_mcr_get_dss_steering(const struct xe_gt *gt, unsigned int dss, u16 *g *instance = dss % gt->steering_dss_per_grp; } -/** - * xe_gt_mcr_steering_info_to_dss_id - Get DSS ID from group/instance steering - * @gt: GT structure - * @group: steering group ID - * @instance: steering instance ID - * - * Return: the converted DSS id. - */ -u32 xe_gt_mcr_steering_info_to_dss_id(struct xe_gt *gt, u16 group, u16 instance) -{ - return group * dss_per_group(gt) + instance; -} - static void init_steering_dss(struct xe_gt *gt) { gt->steering_dss_per_grp = dss_per_group(gt); @@ -536,7 +521,7 @@ void xe_gt_mcr_init_early(struct xe_gt *gt) gt->steering[GAM1].ranges = xe3p_xpc_gam_grp1_steering_table; gt->steering[INSTANCE0].ranges = xe3p_xpc_instance0_steering_table; gt->steering[L3BANK].ranges = xelpg_l3bank_steering_table; - gt->steering[NODE].ranges = xe3p_xpc_node_steering_table; + gt->steering[NODE].ranges = xe2_node_steering_table; } else if (GRAPHICS_VERx100(xe) >= 3510) { gt->steering[DSS].ranges = xe2lpg_dss_steering_table; gt->steering[INSTANCE0].ranges = xe3p_lpg_instance0_steering_table; @@ -544,6 +529,8 @@ void xe_gt_mcr_init_early(struct xe_gt *gt) gt->steering[DSS].ranges = xe2lpg_dss_steering_table; gt->steering[SQIDI_PSMI].ranges = xe2lpg_sqidi_psmi_steering_table; gt->steering[INSTANCE0].ranges = xe2lpg_instance0_steering_table; + gt->steering[L3BANK].ranges = xelpg_l3bank_steering_table; + gt->steering[NODE].ranges = xe2_node_steering_table; } else if (GRAPHICS_VERx100(xe) >= 1270) { gt->steering[INSTANCE0].ranges = xelpg_instance0_steering_table; gt->steering[L3BANK].ranges = xelpg_l3bank_steering_table; diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.h b/drivers/gpu/drm/xe/xe_gt_mcr.h index 283a1c9770e2..2be9419b8acc 100644 --- a/drivers/gpu/drm/xe/xe_gt_mcr.h +++ b/drivers/gpu/drm/xe/xe_gt_mcr.h @@ -33,7 +33,6 @@ bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt, void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p); void xe_gt_mcr_get_dss_steering(const struct xe_gt *gt, unsigned int dss, u16 *group, u16 *instance); -u32 xe_gt_mcr_steering_info_to_dss_id(struct xe_gt *gt, u16 group, u16 instance); /* * Loop over each DSS and determine the group and instance IDs that diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf.c index fb5c9101e275..7868056841b3 100644 --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf.c +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf.c @@ -219,6 +219,7 @@ static void pf_restart(struct xe_gt *gt) xe_gt_assert(gt, !xe_pm_runtime_suspended(xe)); + xe_gt_sriov_pf_policy_restart(gt); xe_gt_sriov_pf_config_restart(gt); xe_gt_sriov_pf_control_restart(gt); diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c index 2f376b5fb088..2c9b85b84b1b 100644 --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c @@ -285,6 +285,13 @@ static u32 encode_config_ggtt(u32 *cfg, const struct xe_gt_sriov_config *config, return encode_ggtt(cfg, xe_ggtt_node_addr(node), xe_ggtt_node_size(node), details); } +static bool custom_sched_priority(struct xe_gt *gt, u32 priority) +{ + return xe_gt_sriov_pf_policy_get_sched_if_idle_locked(gt) ? + priority != GUC_SCHED_PRIORITY_NORMAL : + priority != GUC_SCHED_PRIORITY_LOW; +} + static u32 encode_config_sched(struct xe_gt *gt, u32 *cfg, u32 n, const struct xe_gt_sriov_config *config) { @@ -313,6 +320,11 @@ static u32 encode_config_sched(struct xe_gt *gt, u32 *cfg, u32 n, cfg[n++] = config->preempt_timeout[0]; } + if (custom_sched_priority(gt, config->sched_priority)) { + cfg[n++] = PREP_GUC_KLV_TAG(VF_CFG_SCHED_PRIORITY); + cfg[n++] = config->sched_priority; + } + return n; } @@ -1922,29 +1934,45 @@ static u64 pf_profile_fair_lmem(struct xe_gt *gt, unsigned int num_vfs) return ALIGN_DOWN(fair, alignment); } -static void __pf_show_provisioning_lmem(struct xe_gt *gt, unsigned int first_vf, - unsigned int num_vfs, bool provisioned) +static void __pf_show_provisioned(struct xe_gt *gt, unsigned int first_vf, + unsigned int num_vfs, bool provisioned, + u32 (*get32)(struct xe_gt *, unsigned int), + u64 (*get64)(struct xe_gt *, unsigned int), + const char *what) { unsigned int allvfs = 1 + xe_gt_sriov_pf_get_totalvfs(gt); /* PF plus VFs */ unsigned long *bitmap __free(bitmap) = bitmap_zalloc(allvfs, GFP_KERNEL); unsigned int weight; unsigned int n; + bool pf; + + xe_gt_assert(gt, get32 || get64); if (!bitmap) return; for (n = first_vf; n < first_vf + num_vfs; n++) { - if (!!pf_get_vf_config_lmem(gt, VFID(n)) == provisioned) + if ((get32 && (!!get32(gt, VFID(n)) == provisioned)) || + (get64 && (!!get64(gt, VFID(n)) == provisioned))) bitmap_set(bitmap, n, 1); } + pf = test_and_clear_bit(0, bitmap); weight = bitmap_weight(bitmap, allvfs); - if (!weight) + if (!pf && !weight) return; - xe_gt_sriov_info(gt, "VF%s%*pbl %s provisioned with VRAM\n", - weight > 1 ? "s " : "", allvfs, bitmap, - provisioned ? "already" : "not"); + xe_gt_sriov_info(gt, "%s%s%s%s%*pbl %s provisioned with %s\n", + pf ? "PF" : "", pf && weight ? " and " : "", + weight ? "VF" : "", weight > 1 ? "s " : "", + allvfs, bitmap, provisioned ? "already" : "not", what); +} + +static void __pf_show_provisioning_lmem(struct xe_gt *gt, unsigned int first_vf, + unsigned int num_vfs, bool provisioned) +{ + __pf_show_provisioned(gt, first_vf, num_vfs, provisioned, + NULL, pf_get_vf_config_lmem, "VRAM"); } static void pf_show_all_provisioned_lmem(struct xe_gt *gt) @@ -2078,6 +2106,17 @@ static u32 pf_get_exec_quantum(struct xe_gt *gt, unsigned int vfid) return config->exec_quantum[0]; } +static bool pf_non_default_exec_quantum(struct xe_gt *gt, unsigned int vfid) +{ + struct xe_gt_sriov_config *config = pf_pick_vf_config(gt, vfid); + int i; + + for (i = 0; i < ARRAY_SIZE(config->exec_quantum); i++) + if (config->exec_quantum[i]) + return true; + return false; +} + /** * xe_gt_sriov_pf_config_set_exec_quantum_locked() - Configure PF/VF execution quantum. * @gt: the &xe_gt @@ -2154,6 +2193,25 @@ u32 xe_gt_sriov_pf_config_get_exec_quantum(struct xe_gt *gt, unsigned int vfid) return pf_get_exec_quantum(gt, vfid); } +static int pf_bulk_set_exec_quantum(struct xe_gt *gt, u32 exec_quantum, + unsigned int first_vf, unsigned int num_vfs) +{ + unsigned int n; + int err = 0; + + lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt)); + + for (n = first_vf; n < first_vf + num_vfs; n++) { + err = pf_provision_exec_quantum(gt, VFID(n), exec_quantum); + if (err) + break; + } + + return pf_config_bulk_set_u32_done(gt, first_vf, num_vfs, exec_quantum, + pf_get_exec_quantum, "execution quantum", + exec_quantum_unit, n, err); +} + /** * xe_gt_sriov_pf_config_bulk_set_exec_quantum_locked() - Configure EQ for PF and VFs. * @gt: the &xe_gt to configure @@ -2166,20 +2224,8 @@ u32 xe_gt_sriov_pf_config_get_exec_quantum(struct xe_gt *gt, unsigned int vfid) int xe_gt_sriov_pf_config_bulk_set_exec_quantum_locked(struct xe_gt *gt, u32 exec_quantum) { unsigned int totalvfs = xe_gt_sriov_pf_get_totalvfs(gt); - unsigned int n; - int err = 0; - lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt)); - - for (n = 0; n <= totalvfs; n++) { - err = pf_provision_exec_quantum(gt, VFID(n), exec_quantum); - if (err) - break; - } - - return pf_config_bulk_set_u32_done(gt, 0, 1 + totalvfs, exec_quantum, - pf_get_exec_quantum, "execution quantum", - exec_quantum_unit, n, err); + return pf_bulk_set_exec_quantum(gt, exec_quantum, PFID, 1 + totalvfs); } static int pf_provision_groups_exec_quantums(struct xe_gt *gt, unsigned int vfid, @@ -2293,6 +2339,17 @@ static u32 pf_get_preempt_timeout(struct xe_gt *gt, unsigned int vfid) return config->preempt_timeout[0]; } +static bool pf_non_default_preempt_timeout(struct xe_gt *gt, unsigned int vfid) +{ + struct xe_gt_sriov_config *config = pf_pick_vf_config(gt, vfid); + int i; + + for (i = 0; i < ARRAY_SIZE(config->preempt_timeout); i++) + if (config->preempt_timeout[i]) + return true; + return false; +} + /** * xe_gt_sriov_pf_config_set_preempt_timeout_locked() - Configure PF/VF preemption timeout. * @gt: the &xe_gt @@ -2368,6 +2425,25 @@ u32 xe_gt_sriov_pf_config_get_preempt_timeout(struct xe_gt *gt, unsigned int vfi return pf_get_preempt_timeout(gt, vfid); } +static int pf_bulk_set_preempt_timeout(struct xe_gt *gt, u32 preempt_timeout, + unsigned int first_vf, unsigned int num_vfs) +{ + unsigned int n; + int err = 0; + + lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt)); + + for (n = first_vf; n < first_vf + num_vfs; n++) { + err = pf_provision_preempt_timeout(gt, VFID(n), preempt_timeout); + if (err) + break; + } + + return pf_config_bulk_set_u32_done(gt, first_vf, num_vfs, preempt_timeout, + pf_get_preempt_timeout, "preemption timeout", + preempt_timeout_unit, n, err); +} + /** * xe_gt_sriov_pf_config_bulk_set_preempt_timeout_locked() - Configure PT for PF and VFs. * @gt: the &xe_gt to configure @@ -2380,20 +2456,8 @@ u32 xe_gt_sriov_pf_config_get_preempt_timeout(struct xe_gt *gt, unsigned int vfi int xe_gt_sriov_pf_config_bulk_set_preempt_timeout_locked(struct xe_gt *gt, u32 preempt_timeout) { unsigned int totalvfs = xe_gt_sriov_pf_get_totalvfs(gt); - unsigned int n; - int err = 0; - lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt)); - - for (n = 0; n <= totalvfs; n++) { - err = pf_provision_preempt_timeout(gt, VFID(n), preempt_timeout); - if (err) - break; - } - - return pf_config_bulk_set_u32_done(gt, 0, 1 + totalvfs, preempt_timeout, - pf_get_preempt_timeout, "preemption timeout", - preempt_timeout_unit, n, err); + return pf_bulk_set_preempt_timeout(gt, preempt_timeout, PFID, 1 + totalvfs); } static int pf_provision_groups_preempt_timeouts(struct xe_gt *gt, unsigned int vfid, @@ -2500,7 +2564,7 @@ static int pf_provision_sched_priority(struct xe_gt *gt, unsigned int vfid, u32 return 0; } -static int pf_get_sched_priority(struct xe_gt *gt, unsigned int vfid) +static u32 pf_get_sched_priority(struct xe_gt *gt, unsigned int vfid) { struct xe_gt_sriov_config *config = pf_pick_vf_config(gt, vfid); @@ -2550,6 +2614,35 @@ u32 xe_gt_sriov_pf_config_get_sched_priority(struct xe_gt *gt, unsigned int vfid return priority; } +/** + * xe_gt_sriov_pf_config_force_sched_priority_locked() - Force update scheduling priority. + * @gt: the &xe_gt + * @priority: new scheduling priority to set + * + * This function allows to update cached values of the scheduling priorities of all + * VFs (and PF) as result of applying the `GUC_KLV_VGT_POLICY_SCHED_IF_IDLE`_ policy. + * + * This function can only be called on PF. + */ +void xe_gt_sriov_pf_config_force_sched_priority_locked(struct xe_gt *gt, u32 priority) +{ + unsigned int total_vfs = xe_gt_sriov_pf_get_totalvfs(gt); + struct xe_gt_sriov_config *config; + unsigned int n; + + xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); + lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt)); + + for (n = 0; n <= total_vfs; n++) { + config = pf_pick_vf_config(gt, VFID(n)); + config->sched_priority = priority; + } + + pf_config_bulk_set_u32_done(gt, PFID, 1 + total_vfs, priority, + pf_get_sched_priority, "scheduling priority", + sched_priority_unit, n, 0); +} + static void pf_reset_config_sched(struct xe_gt *gt, struct xe_gt_sriov_config *config) { int i; @@ -2562,6 +2655,104 @@ static void pf_reset_config_sched(struct xe_gt *gt, struct xe_gt_sriov_config *c } } +static bool pf_non_default_sched(struct xe_gt *gt, unsigned int vfid) +{ + return pf_non_default_exec_quantum(gt, vfid) || + pf_non_default_preempt_timeout(gt, vfid) || + custom_sched_priority(gt, pf_get_sched_priority(gt, vfid)); +} + +static void __pf_show_provisioned_sched(struct xe_gt *gt, unsigned int first_vf, + unsigned int num_vfs, bool provisioned) +{ + __pf_show_provisioned(gt, first_vf, num_vfs, provisioned, + pf_get_exec_quantum, NULL, "EQ"); + __pf_show_provisioned(gt, first_vf, num_vfs, provisioned, + pf_get_preempt_timeout, NULL, "PT"); + + /* we only care about non-default priorities */ + if (provisioned) + __pf_show_provisioned(gt, first_vf, num_vfs, true, + pf_get_sched_priority, NULL, "PRIORITY"); +} + +static void pf_show_all_provisioned_sched(struct xe_gt *gt) +{ + __pf_show_provisioned_sched(gt, PFID, 1 + xe_gt_sriov_pf_get_totalvfs(gt), true); +} + +static void pf_show_unprovisioned_sched(struct xe_gt *gt, unsigned int num_vfs) +{ + __pf_show_provisioned_sched(gt, PFID, 1 + num_vfs, false); +} + +static bool pf_needs_provision_sched(struct xe_gt *gt, unsigned int num_vfs) +{ + unsigned int vfid; + + for (vfid = PFID; vfid <= PFID + num_vfs; vfid++) { + if (pf_non_default_sched(gt, vfid)) { + pf_show_all_provisioned_sched(gt); + pf_show_unprovisioned_sched(gt, num_vfs); + return false; + } + } + + if (xe_gt_sriov_pf_policy_get_sched_if_idle_locked(gt)) { + pf_show_all_provisioned_sched(gt); + pf_show_unprovisioned_sched(gt, num_vfs); + return false; + } + + pf_show_all_provisioned_sched(gt); + return true; +} + +/* With 16ms EQ/PT GuC should be able to handle up to 63 VFs within 2s */ +#define XE_FAIR_EXEC_QUANTUM_MS 16 +#define XE_FAIR_PREEMPT_TIMEOUT_US 16000 +#define XE_FAIR_SCHED_PRIORITY GUC_SCHED_PRIORITY_LOW +#define XE_ADMIN_PF_SCHED_PRIORITY GUC_SCHED_PRIORITY_HIGH + +/** + * xe_gt_sriov_pf_config_set_fair_sched() - Provision PF and VFs with fair scheduling. + * @gt: the &xe_gt + * @num_vfs: number of VFs to provision (can't be 0) + * + * This function can only be called on PF. + * + * Return: 0 on success or a negative error code on failure. + */ +int xe_gt_sriov_pf_config_set_fair_sched(struct xe_gt *gt, unsigned int num_vfs) +{ + int result = 0; + int err; + + xe_gt_assert(gt, num_vfs); + xe_gt_assert(gt, XE_FAIR_EXEC_QUANTUM_MS); + xe_gt_assert(gt, XE_FAIR_PREEMPT_TIMEOUT_US); + + guard(mutex)(xe_gt_sriov_pf_master_mutex(gt)); + + if (!pf_needs_provision_sched(gt, num_vfs)) + return 0; + + err = pf_bulk_set_exec_quantum(gt, XE_FAIR_EXEC_QUANTUM_MS, PFID, 1 + num_vfs); + result = result ?: err; + err = pf_bulk_set_preempt_timeout(gt, XE_FAIR_PREEMPT_TIMEOUT_US, PFID, 1 + num_vfs); + result = result ?: err; + + xe_gt_assert(gt, XE_FAIR_SCHED_PRIORITY == GUC_SCHED_PRIORITY_LOW); + xe_gt_assert(gt, !xe_gt_sriov_pf_policy_get_sched_if_idle_locked(gt)); + + if (xe_sriov_pf_admin_only(gt_to_xe(gt))) { + err = pf_provision_sched_priority(gt, PFID, XE_ADMIN_PF_SCHED_PRIORITY); + result = result ?: err; + } + + return result; +} + static int pf_provision_threshold(struct xe_gt *gt, unsigned int vfid, enum xe_guc_klv_threshold_index index, u32 value) { @@ -2838,6 +3029,9 @@ static int pf_validate_vf_config(struct xe_gt *gt, unsigned int vfid) valid_all = valid_all && valid_lmem; } + /* also check optional EQ/PT/PRIO */ + valid_any = valid_any || pf_non_default_sched(gt, vfid); + return valid_all ? 0 : valid_any ? -ENOKEY : -ENODATA; } diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.h b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.h index 4a004ecd6140..2ec62c12ad5c 100644 --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.h +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.h @@ -71,12 +71,14 @@ int xe_gt_sriov_pf_config_set_groups_preempt_timeouts(struct xe_gt *gt, unsigned u32 xe_gt_sriov_pf_config_get_sched_priority(struct xe_gt *gt, unsigned int vfid); int xe_gt_sriov_pf_config_set_sched_priority(struct xe_gt *gt, unsigned int vfid, u32 priority); +void xe_gt_sriov_pf_config_force_sched_priority_locked(struct xe_gt *gt, u32 priority); u32 xe_gt_sriov_pf_config_get_threshold(struct xe_gt *gt, unsigned int vfid, enum xe_guc_klv_threshold_index index); int xe_gt_sriov_pf_config_set_threshold(struct xe_gt *gt, unsigned int vfid, enum xe_guc_klv_threshold_index index, u32 value); +int xe_gt_sriov_pf_config_set_fair_sched(struct xe_gt *gt, unsigned int num_vfs); int xe_gt_sriov_pf_config_set_fair(struct xe_gt *gt, unsigned int vfid, unsigned int num_vfs); int xe_gt_sriov_pf_config_sanitize(struct xe_gt *gt, unsigned int vfid, long timeout); int xe_gt_sriov_pf_config_release(struct xe_gt *gt, unsigned int vfid, bool force); diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c index 848e24926ecd..e8458d63742d 100644 --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c @@ -8,6 +8,7 @@ #include "abi/guc_actions_sriov_abi.h" #include "xe_gt.h" +#include "xe_gt_sriov_pf_config.h" #include "xe_gt_sriov_pf_helpers.h" #include "xe_gt_sriov_pf_policy.h" #include "xe_gt_sriov_printk.h" @@ -16,7 +17,6 @@ #include "xe_guc_ct.h" #include "xe_guc_klv_helpers.h" #include "xe_guc_submit.h" -#include "xe_pm.h" /* * Return: number of KLVs that were successfully parsed and saved, @@ -67,6 +67,15 @@ static int pf_push_policy_buf_klvs(struct xe_gt *gt, u32 num_klvs, return err; } + if (IS_ENABLED(CONFIG_DRM_XE_DEBUG_SRIOV)) { + struct drm_printer p = xe_gt_dbg_printer(gt); + void *klvs = xe_guc_buf_cpu_ptr(buf); + + xe_gt_sriov_dbg(gt, "pushed policy update with %u KLV%s:\n", + num_klvs, str_plural(num_klvs)); + xe_guc_klv_print(klvs, num_dwords, &p); + } + return 0; } @@ -153,33 +162,14 @@ static int pf_update_policy_u32(struct xe_gt *gt, u16 key, u32 *policy, u32 valu return 0; } -static void pf_bulk_reset_sched_priority(struct xe_gt *gt, u32 priority) -{ - unsigned int total_vfs = 1 + xe_gt_sriov_pf_get_totalvfs(gt); - unsigned int n; - - xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); - lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt)); - - for (n = 0; n < total_vfs; n++) - gt->sriov.pf.vfs[n].config.sched_priority = priority; -} - static int pf_provision_sched_if_idle(struct xe_gt *gt, bool enable) { - int err; - xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt)); - err = pf_update_policy_bool(gt, GUC_KLV_VGT_POLICY_SCHED_IF_IDLE_KEY, - >->sriov.pf.policy.guc.sched_if_idle, - enable); - - if (!err) - pf_bulk_reset_sched_priority(gt, enable ? GUC_SCHED_PRIORITY_NORMAL : - GUC_SCHED_PRIORITY_LOW); - return err; + return pf_update_policy_bool(gt, GUC_KLV_VGT_POLICY_SCHED_IF_IDLE_KEY, + >->sriov.pf.policy.guc.sched_if_idle, + enable); } static int pf_reprovision_sched_if_idle(struct xe_gt *gt) @@ -187,6 +177,9 @@ static int pf_reprovision_sched_if_idle(struct xe_gt *gt) xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt)); + if (!gt->sriov.pf.policy.guc.sched_if_idle) + return 0; + return pf_provision_sched_if_idle(gt, gt->sriov.pf.policy.guc.sched_if_idle); } @@ -199,7 +192,39 @@ static void pf_sanitize_sched_if_idle(struct xe_gt *gt) } /** - * xe_gt_sriov_pf_policy_set_sched_if_idle - Control the 'sched_if_idle' policy. + * xe_gt_sriov_pf_policy_set_sched_if_idle_locked() - Control the 'sched_if_idle' policy. + * @gt: the &xe_gt where to apply the policy + * @enable: the value of the 'sched_if_idle' policy + * + * This function can only be called on PF. + * + * Return: 0 on success or a negative error code on failure. + */ +int xe_gt_sriov_pf_policy_set_sched_if_idle_locked(struct xe_gt *gt, bool enable) +{ + u32 priority; + int err; + + lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt)); + + err = pf_provision_sched_if_idle(gt, enable); + if (err) + return err; + + /* + * As of GuC 70.12 a change of this policy impacts individual configs + * of all VFs. See `GUC_KLV_VGT_POLICY_SCHED_IF_IDLE`_ for details. + */ + xe_gt_assert(gt, GUC_FIRMWARE_VER_AT_LEAST(>->uc.guc, 70, 12)); + + priority = enable ? GUC_SCHED_PRIORITY_NORMAL : GUC_SCHED_PRIORITY_LOW; + xe_gt_sriov_pf_config_force_sched_priority_locked(gt, priority); + + return 0; +} + +/** + * xe_gt_sriov_pf_policy_set_sched_if_idle() - Control the 'sched_if_idle' policy. * @gt: the &xe_gt where to apply the policy * @enable: the value of the 'sched_if_idle' policy * @@ -209,13 +234,26 @@ static void pf_sanitize_sched_if_idle(struct xe_gt *gt) */ int xe_gt_sriov_pf_policy_set_sched_if_idle(struct xe_gt *gt, bool enable) { - int err; + xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); + guard(mutex)(xe_gt_sriov_pf_master_mutex(gt)); - mutex_lock(xe_gt_sriov_pf_master_mutex(gt)); - err = pf_provision_sched_if_idle(gt, enable); - mutex_unlock(xe_gt_sriov_pf_master_mutex(gt)); + return xe_gt_sriov_pf_policy_set_sched_if_idle_locked(gt, enable); +} - return err; +/** + * xe_gt_sriov_pf_policy_get_sched_if_idle_locked() - Retrieve value of 'sched_if_idle' policy. + * @gt: the &xe_gt where to read the policy from + * + * This function can only be called on PF. + * + * Return: last value of 'sched_if_idle' policy applied. + */ +bool xe_gt_sriov_pf_policy_get_sched_if_idle_locked(struct xe_gt *gt) +{ + xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); + lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt)); + + return gt->sriov.pf.policy.guc.sched_if_idle; } /** @@ -228,15 +266,10 @@ int xe_gt_sriov_pf_policy_set_sched_if_idle(struct xe_gt *gt, bool enable) */ bool xe_gt_sriov_pf_policy_get_sched_if_idle(struct xe_gt *gt) { - bool enable; - xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); + guard(mutex)(xe_gt_sriov_pf_master_mutex(gt)); - mutex_lock(xe_gt_sriov_pf_master_mutex(gt)); - enable = gt->sriov.pf.policy.guc.sched_if_idle; - mutex_unlock(xe_gt_sriov_pf_master_mutex(gt)); - - return enable; + return xe_gt_sriov_pf_policy_get_sched_if_idle_locked(gt); } static int pf_provision_reset_engine(struct xe_gt *gt, bool enable) @@ -253,6 +286,9 @@ static int pf_reprovision_reset_engine(struct xe_gt *gt) xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt)); + if (!gt->sriov.pf.policy.guc.reset_engine) + return 0; + return pf_provision_reset_engine(gt, gt->sriov.pf.policy.guc.reset_engine); } @@ -319,6 +355,9 @@ static int pf_reprovision_sample_period(struct xe_gt *gt) xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt)); + if (!gt->sriov.pf.policy.guc.sample_period) + return 0; + return pf_provision_sample_period(gt, gt->sriov.pf.policy.guc.sample_period); } @@ -689,30 +728,23 @@ void xe_gt_sriov_pf_policy_sanitize(struct xe_gt *gt) } /** - * xe_gt_sriov_pf_policy_reprovision - Reprovision (and optionally reset) policy settings. + * xe_gt_sriov_pf_policy_restart() - Reprovision policy settings. * @gt: the &xe_gt - * @reset: if true will reprovision using default values instead of latest * * This function can only be called on PF. * * Return: 0 on success or a negative error code on failure. */ -int xe_gt_sriov_pf_policy_reprovision(struct xe_gt *gt, bool reset) +int xe_gt_sriov_pf_policy_restart(struct xe_gt *gt) { int err = 0; - xe_pm_runtime_get_noresume(gt_to_xe(gt)); + guard(mutex)(xe_gt_sriov_pf_master_mutex(gt)); - mutex_lock(xe_gt_sriov_pf_master_mutex(gt)); - if (reset) - pf_sanitize_guc_policies(gt); err |= pf_reprovision_sched_if_idle(gt); err |= pf_reprovision_reset_engine(gt); err |= pf_reprovision_sample_period(gt); err |= pf_reprovision_sched_groups(gt); - mutex_unlock(xe_gt_sriov_pf_master_mutex(gt)); - - xe_pm_runtime_put(gt_to_xe(gt)); return err ? -ENXIO : 0; } diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.h b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.h index bd73aa58f9ca..d667d66897b1 100644 --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.h +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.h @@ -14,7 +14,9 @@ struct drm_printer; struct xe_gt; int xe_gt_sriov_pf_policy_set_sched_if_idle(struct xe_gt *gt, bool enable); +int xe_gt_sriov_pf_policy_set_sched_if_idle_locked(struct xe_gt *gt, bool enable); bool xe_gt_sriov_pf_policy_get_sched_if_idle(struct xe_gt *gt); +bool xe_gt_sriov_pf_policy_get_sched_if_idle_locked(struct xe_gt *gt); int xe_gt_sriov_pf_policy_set_reset_engine(struct xe_gt *gt, bool enable); bool xe_gt_sriov_pf_policy_get_reset_engine(struct xe_gt *gt); int xe_gt_sriov_pf_policy_set_sample_period(struct xe_gt *gt, u32 value); @@ -29,7 +31,7 @@ bool xe_gt_sriov_pf_policy_sched_groups_enabled(struct xe_gt *gt); void xe_gt_sriov_pf_policy_init(struct xe_gt *gt); void xe_gt_sriov_pf_policy_sanitize(struct xe_gt *gt); -int xe_gt_sriov_pf_policy_reprovision(struct xe_gt *gt, bool reset); +int xe_gt_sriov_pf_policy_restart(struct xe_gt *gt); int xe_gt_sriov_pf_policy_print(struct xe_gt *gt, struct drm_printer *p); #endif diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_types.h b/drivers/gpu/drm/xe/xe_gt_sriov_pf_types.h index 667b8310478d..6296483c44ec 100644 --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_types.h +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_types.h @@ -49,7 +49,6 @@ struct xe_gt_sriov_pf_workers { * @service: service data. * @control: control data. * @policy: policy data. - * @migration: migration data. * @spare: PF-only provisioning configuration. * @vfs: metadata for all VFs. */ diff --git a/drivers/gpu/drm/xe/xe_gt_stats.c b/drivers/gpu/drm/xe/xe_gt_stats.c index 59b3b23a54c8..789397514f3e 100644 --- a/drivers/gpu/drm/xe/xe_gt_stats.c +++ b/drivers/gpu/drm/xe/xe_gt_stats.c @@ -9,6 +9,47 @@ #include "xe_device.h" #include "xe_gt_stats.h" +/** + * DOC: Xe GT Statistics + * + * Overview + * ======== + * + * The Xe driver exposes per-GT statistics through the debugfs filesystem at:: + * + * /sys/kernel/debug/dri//gt/stats + * + * This interface requires the kernel to be built with ``CONFIG_DEBUG_FS=y``. + * + * Reading statistics + * ================== + * + * Reading the file prints all available statistics, one per line, in + * ``name: value`` format:: + * + * $ cat /sys/kernel/debug/dri/0/gt0/stats + * svm_pagefault_count: 0 + * tlb_inval_count: 1234 + * ... + * + * All values are 64-bit unsigned integers aggregated across all CPUs. + * Counters accumulate since the driver was loaded or since the last explicit + * reset. Timing counters use microseconds as their unit; data volume counters + * use KiB. + * + * Resetting statistics + * ==================== + * + * Writing a boolean true value to the file resets all counters to zero:: + * + * echo 1 > /sys/kernel/debug/dri/0/gt0/stats + * + * Any value accepted by ``kstrtobool()`` (e.g. ``1``, ``y``, ``yes``, + * ``on``) triggers the reset. Resetting while the GPU is active may yield + * unpredictable intermediate values; it is recommended to reset only when + * the GPU is idle. + */ + static void xe_gt_stats_fini(struct drm_device *drm, void *arg) { struct xe_gt *gt = arg; diff --git a/drivers/gpu/drm/xe/xe_gt_stats_types.h b/drivers/gpu/drm/xe/xe_gt_stats_types.h index 081c787ddcb6..425491bed6c4 100644 --- a/drivers/gpu/drm/xe/xe_gt_stats_types.h +++ b/drivers/gpu/drm/xe/xe_gt_stats_types.h @@ -8,6 +8,124 @@ #include +/** + * enum xe_gt_stats_id - GT statistics identifiers + * @XE_GT_STATS_ID_SVM_PAGEFAULT_COUNT: Total SVM page faults handled. + * @XE_GT_STATS_ID_TLB_INVAL: Total GPU Translation Lookaside Buffer (TLB) + * invalidations issued. + * @XE_GT_STATS_ID_SVM_TLB_INVAL_COUNT: TLB invalidations issued during SVM + * page-fault handling. + * @XE_GT_STATS_ID_SVM_TLB_INVAL_US: Cumulative time (µs) waiting for TLB + * invalidations during SVM page-fault handling. + * + * @XE_GT_STATS_ID_VMA_PAGEFAULT_COUNT: Buffer-object (non-SVM) page faults + * handled. + * @XE_GT_STATS_ID_VMA_PAGEFAULT_KB: Size (KiB) of VMAs involved in + * buffer-object page fault handling. + * @XE_GT_STATS_ID_INVALID_PREFETCH_PAGEFAULT_COUNT: GPU prefetch faults for + * addresses with no valid backing. + * + * @XE_GT_STATS_ID_SVM_4K_PAGEFAULT_COUNT: SVM page faults resolved by + * mapping 4K pages. + * @XE_GT_STATS_ID_SVM_64K_PAGEFAULT_COUNT: SVM page faults resolved by + * mapping 64K pages. + * @XE_GT_STATS_ID_SVM_2M_PAGEFAULT_COUNT: SVM page faults resolved by + * mapping 2M pages. + * @XE_GT_STATS_ID_SVM_4K_VALID_PAGEFAULT_COUNT: Valid SVM page faults + * at 4K page size, where the GPU mapping was already valid — resolved without + * creating new mappings. + * @XE_GT_STATS_ID_SVM_64K_VALID_PAGEFAULT_COUNT: Valid SVM page faults at 64K + * page size. + * @XE_GT_STATS_ID_SVM_2M_VALID_PAGEFAULT_COUNT: Valid SVM page faults at 2M + * page size. + * @XE_GT_STATS_ID_SVM_4K_PAGEFAULT_US: Cumulative time (µs) handling 4K SVM + * page faults. + * @XE_GT_STATS_ID_SVM_64K_PAGEFAULT_US: Cumulative time (µs) handling 64K + * SVM page faults. + * @XE_GT_STATS_ID_SVM_2M_PAGEFAULT_US: Cumulative time (µs) handling 2M SVM + * page faults. + * + * @XE_GT_STATS_ID_SVM_4K_MIGRATE_COUNT: 4K pages moved from CPU to device + * memory. + * @XE_GT_STATS_ID_SVM_64K_MIGRATE_COUNT: 64K pages moved from CPU to device + * memory. + * @XE_GT_STATS_ID_SVM_2M_MIGRATE_COUNT: 2M pages moved from CPU to device + * memory. + * @XE_GT_STATS_ID_SVM_4K_MIGRATE_US: Cumulative time (µs) moving 4K pages + * from CPU to device memory. + * @XE_GT_STATS_ID_SVM_64K_MIGRATE_US: Cumulative time (µs) moving 64K pages + * from CPU to device memory. + * @XE_GT_STATS_ID_SVM_2M_MIGRATE_US: Cumulative time (µs) moving 2M pages + * from CPU to device memory. + * + * @XE_GT_STATS_ID_SVM_DEVICE_COPY_US: Cumulative time (µs) for memory copies to + * device, across all page sizes. + * @XE_GT_STATS_ID_SVM_4K_DEVICE_COPY_US: Cumulative time (µs) for memory copies + * of 4K pages to device. + * @XE_GT_STATS_ID_SVM_64K_DEVICE_COPY_US: Cumulative time (µs) for memory + * copies of 64K pages to device. + * @XE_GT_STATS_ID_SVM_2M_DEVICE_COPY_US: Cumulative time (µs) for memory copies + * of 2M pages to device. + * @XE_GT_STATS_ID_SVM_CPU_COPY_US: Cumulative time (µs) for memory copies to + * CPU, across all page sizes. + * @XE_GT_STATS_ID_SVM_4K_CPU_COPY_US: Cumulative time (µs) for memory copies of + * 4K pages to CPU. + * @XE_GT_STATS_ID_SVM_64K_CPU_COPY_US: Cumulative time (µs) for memory copies + * of 64K pages to CPU. + * @XE_GT_STATS_ID_SVM_2M_CPU_COPY_US: Cumulative time (µs) for memory copies of + * 2M pages to CPU. + * @XE_GT_STATS_ID_SVM_DEVICE_COPY_KB: Data (KiB) copied to device across all + * page sizes. + * @XE_GT_STATS_ID_SVM_4K_DEVICE_COPY_KB: Data (KiB) copied to device for 4K + * pages. + * @XE_GT_STATS_ID_SVM_64K_DEVICE_COPY_KB: Data (KiB) copied to device for + * 64K pages. + * @XE_GT_STATS_ID_SVM_2M_DEVICE_COPY_KB: Data (KiB) copied to device for 2M + * pages. + * @XE_GT_STATS_ID_SVM_CPU_COPY_KB: Data (KiB) copied to CPU across all page + * sizes. + * @XE_GT_STATS_ID_SVM_4K_CPU_COPY_KB: Data (KiB) copied to CPU for 4K pages. + * @XE_GT_STATS_ID_SVM_64K_CPU_COPY_KB: Data (KiB) copied to CPU for 64K pages. + * @XE_GT_STATS_ID_SVM_2M_CPU_COPY_KB: Data (KiB) copied to CPU for 2M pages. + * + * @XE_GT_STATS_ID_SVM_4K_GET_PAGES_US: Cumulative time (µs) getting CPU + * memory pages for GPU access at 4K page size. + * @XE_GT_STATS_ID_SVM_64K_GET_PAGES_US: Cumulative time (µs) getting CPU + * memory pages for GPU access at 64K page size. + * @XE_GT_STATS_ID_SVM_2M_GET_PAGES_US: Cumulative time (µs) getting CPU + * memory pages for GPU access at 2M page size. + * @XE_GT_STATS_ID_SVM_4K_BIND_US: Cumulative time (µs) binding 4K pages + * into the GPU page table. + * @XE_GT_STATS_ID_SVM_64K_BIND_US: Cumulative time (µs) binding 64K pages + * into the GPU page table. + * @XE_GT_STATS_ID_SVM_2M_BIND_US: Cumulative time (µs) binding 2M pages + * into the GPU page table. + * + * @XE_GT_STATS_ID_HW_ENGINE_GROUP_SUSPEND_LR_QUEUE_COUNT: Times the + * scheduler preempted a long-running (LR) GPU exec queue. + * @XE_GT_STATS_ID_HW_ENGINE_GROUP_SKIP_LR_QUEUE_COUNT: Times the scheduler + * skipped suspend because the system was idle. + * @XE_GT_STATS_ID_HW_ENGINE_GROUP_WAIT_DMA_QUEUE_COUNT: Times the driver + * stalled waiting for prior GPU work to complete before scheduling more. + * @XE_GT_STATS_ID_HW_ENGINE_GROUP_SUSPEND_LR_QUEUE_US: Cumulative time + * (µs) spent preempting long-running (LR) GPU exec queues. + * @XE_GT_STATS_ID_HW_ENGINE_GROUP_WAIT_DMA_QUEUE_US: Cumulative time (µs) + * stalled waiting for prior GPU work to complete. + * + * @XE_GT_STATS_ID_PRL_4K_ENTRY_COUNT: 4K-page entries from the page reclaim + * list that were processed. + * @XE_GT_STATS_ID_PRL_64K_ENTRY_COUNT: 64K-page entries from the page reclaim + * list that were processed. + * @XE_GT_STATS_ID_PRL_2M_ENTRY_COUNT: 2M-page entries from the page reclaim + * list that were processed. + * @XE_GT_STATS_ID_PRL_ISSUED_COUNT: Times a page reclamation was issued. + * @XE_GT_STATS_ID_PRL_ABORTED_COUNT: Times the page reclaim process was + * aborted. + * + * @__XE_GT_STATS_NUM_IDS: Number of valid IDs; not a real counter. + * + * See Documentation/gpu/xe/xe_gt_stats.rst. + */ enum xe_gt_stats_id { XE_GT_STATS_ID_SVM_PAGEFAULT_COUNT, XE_GT_STATS_ID_TLB_INVAL, diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h index 8b55cf25a75f..7351aadd238e 100644 --- a/drivers/gpu/drm/xe/xe_gt_types.h +++ b/drivers/gpu/drm/xe/xe_gt_types.h @@ -136,7 +136,7 @@ struct xe_gt { /** @info.gmdid: raw GMD_ID value from hardware */ u32 gmdid; /** - * @multi_queue_engine_class_mask: Bitmask of engine classes with + * @info.multi_queue_engine_class_mask: Bitmask of engine classes with * multi queue support enabled. */ u16 multi_queue_engine_class_mask; @@ -355,7 +355,7 @@ struct xe_gt { /** @user_engines: engines present in GT and available to userspace */ struct { /** - * @user_engines.mask: like @info->engine_mask, but take in + * @user_engines.mask: like @info.engine_mask, but take in * consideration only engines available to userspace */ u64 mask; diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c index ccebb437e37f..e468b638271b 100644 --- a/drivers/gpu/drm/xe/xe_guc.c +++ b/drivers/gpu/drm/xe/xe_guc.c @@ -780,6 +780,14 @@ int xe_guc_init(struct xe_guc *guc) if (GUC_SUBMIT_VER(guc) < MAKE_GUC_VER(1, 14, 0)) xe->info.has_page_reclaim_hw_assist = false; + /* Disable indirect_ring_state if missing GuC 70.53+ WA 14025515070. */ + if (gt->info.has_indirect_ring_state && + XE_GT_WA(gt, 14025515070) && + GUC_SUBMIT_VER(guc) < MAKE_GUC_VER(1, 26, 0)) { + gt->info.has_indirect_ring_state = 0; + xe_gt_notice(gt, "indirect ring state requires WA in GuC submit ver 1.26+\n"); + } + if (IS_SRIOV_VF(xe)) { ret = devm_add_action_or_reset(xe->drm.dev, vf_guc_fini_hw, guc); if (ret) @@ -1693,13 +1701,8 @@ void xe_guc_reset_wait(struct xe_guc *guc) void xe_guc_stop_prepare(struct xe_guc *guc) { - if (!IS_SRIOV_VF(guc_to_xe(guc))) { - int err; - - err = xe_guc_pc_stop(&guc->pc); - xe_gt_WARN(guc_to_gt(guc), err, "Failed to stop GuC PC: %pe\n", - ERR_PTR(err)); - } + if (!IS_SRIOV_VF(guc_to_xe(guc))) + xe_guc_pc_stop(&guc->pc); } void xe_guc_stop(struct xe_guc *guc) diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c index 81b5f01b1f65..ce651da6f318 100644 --- a/drivers/gpu/drm/xe/xe_guc_ads.c +++ b/drivers/gpu/drm/xe/xe_guc_ads.c @@ -360,6 +360,9 @@ static void guc_waklv_init(struct xe_guc_ads *ads) if (XE_GT_WA(gt, 14020001231)) guc_waklv_enable(ads, NULL, 0, &offset, &remain, GUC_WORKAROUND_KLV_DISABLE_PSMI_INTERRUPTS_AT_C6_ENTRY_RESTORE_AT_EXIT); + if (XE_GT_WA(gt, 14025515070) && GUC_FIRMWARE_VER_AT_LEAST(>->uc.guc, 70, 53)) + guc_waklv_enable(ads, NULL, 0, &offset, &remain, + GUC_WA_KLV_CLR_CS_INDIRECT_RING_STATE_IF_IDLE_AT_CTX_REG); size = guc_ads_waklv_size(ads) - remain; if (!size) @@ -742,10 +745,8 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads, struct xe_reg reg; bool skip; } *e, extra_regs[] = { - { .reg = RING_MODE(hwe->mmio_base), }, { .reg = RING_HWS_PGA(hwe->mmio_base), }, { .reg = RING_IMR(hwe->mmio_base), }, - { .reg = RCU_MODE, .skip = hwe != hwe_rcs_reset_domain }, { .reg = CCS_MODE, .skip = hwe != hwe_rcs_reset_domain || !xe_gt_ccs_mode_enabled(hwe->gt) }, }; diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c index 2f5816c78fba..bc49e40165a3 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture.c +++ b/drivers/gpu/drm/xe/xe_guc_capture.c @@ -111,7 +111,7 @@ struct __guc_capture_parsed_output { { RING_TAIL(0), REG_32BIT, 0, 0, 0, "RING_TAIL"}, \ { RING_CTL(0), REG_32BIT, 0, 0, 0, "RING_CTL"}, \ { RING_MI_MODE(0), REG_32BIT, 0, 0, 0, "RING_MI_MODE"}, \ - { RING_MODE(0), REG_32BIT, 0, 0, 0, "RING_MODE"}, \ + { GFX_MODE(0), REG_32BIT, 0, 0, 0, "GFX_MODE"}, \ { RING_ESR(0), REG_32BIT, 0, 0, 0, "RING_ESR"}, \ { RING_EMR(0), REG_32BIT, 0, 0, 0, "RING_EMR"}, \ { RING_EIR(0), REG_32BIT, 0, 0, 0, "RING_EIR"}, \ diff --git a/drivers/gpu/drm/xe/xe_guc_capture.h b/drivers/gpu/drm/xe/xe_guc_capture.h index 34d6fdc64f56..dca97d52b192 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture.h +++ b/drivers/gpu/drm/xe/xe_guc_capture.h @@ -3,8 +3,8 @@ * Copyright © 2021-2024 Intel Corporation */ -#ifndef _XE_GUC_CAPTURE_H -#define _XE_GUC_CAPTURE_H +#ifndef _XE_GUC_CAPTURE_H_ +#define _XE_GUC_CAPTURE_H_ #include #include "abi/guc_capture_abi.h" diff --git a/drivers/gpu/drm/xe/xe_guc_capture_types.h b/drivers/gpu/drm/xe/xe_guc_capture_types.h index 6cb439115597..058a3f2eadce 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture_types.h +++ b/drivers/gpu/drm/xe/xe_guc_capture_types.h @@ -3,8 +3,8 @@ * Copyright © 2021-2024 Intel Corporation */ -#ifndef _XE_GUC_CAPTURE_TYPES_H -#define _XE_GUC_CAPTURE_TYPES_H +#ifndef _XE_GUC_CAPTURE_TYPES_H_ +#define _XE_GUC_CAPTURE_TYPES_H_ #include #include "regs/xe_reg_defs.h" @@ -32,7 +32,7 @@ struct __guc_mmio_reg_descr { /** * @data_type: data type of the register * Could be 32 bit, low or hi dword of a 64 bit, see enum - * register_data_type + * capture_register_data_type */ enum capture_register_data_type data_type; /** @flags: Flags for the register */ diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c index a11cff7a20be..21e0dad9a481 100644 --- a/drivers/gpu/drm/xe/xe_guc_ct.c +++ b/drivers/gpu/drm/xe/xe_guc_ct.c @@ -186,13 +186,16 @@ static void fast_req_track(struct xe_guc_ct *ct, u16 fence, u16 action) { } struct g2h_fence { u32 *response_buffer; u32 seqno; + /* fields below this point are setup based on the response */ u32 response_data; u16 response_len; u16 error; u16 hint; u16 reason; + u32 counter; bool cancel; bool retry; + bool wait; bool fail; bool done; }; @@ -204,6 +207,11 @@ static void g2h_fence_init(struct g2h_fence *g2h_fence, u32 *response_buffer) g2h_fence->seqno = ~0x0; } +static void g2h_fence_reinit(struct g2h_fence *g2h_fence) +{ + memset_after(g2h_fence, 0, seqno); +} + static void g2h_fence_cancel(struct g2h_fence *g2h_fence) { g2h_fence->cancel = true; @@ -1331,6 +1339,7 @@ static int guc_ct_send_recv(struct xe_guc_ct *ct, const u32 *action, u32 len, /* READ_ONCEs pairs with WRITE_ONCEs in parse_g2h_response * and g2h_fence_cancel. */ +wait_again: ret = wait_event_timeout(ct->g2h_fence_wq, READ_ONCE(g2h_fence.done), HZ); if (!ret) { LNL_FLUSH_WORK(&ct->g2h_worker); @@ -1356,6 +1365,14 @@ static int guc_ct_send_recv(struct xe_guc_ct *ct, const u32 *action, u32 len, return -ETIME; } + if (g2h_fence.wait) { + xe_gt_dbg(gt, "H2G action %#x busy: counter %u\n", + action[0], g2h_fence.counter); + /* we can't leave any response data if we want to wait again */ + g2h_fence_reinit(&g2h_fence); + mutex_unlock(&ct->lock); + goto wait_again; + } if (g2h_fence.retry) { xe_gt_dbg(gt, "H2G action %#x retrying: reason %#x\n", action[0], g2h_fence.reason); @@ -1508,7 +1525,12 @@ static int parse_g2h_response(struct xe_guc_ct *ct, u32 *msg, u32 len) return -EPROTO; } - g2h_fence = xa_erase(&ct->fence_lookup, fence); + /* don't erase as we still expect a final response with the same fence */ + if (type == GUC_HXG_TYPE_NO_RESPONSE_BUSY) + g2h_fence = xa_load(&ct->fence_lookup, fence); + else + g2h_fence = xa_erase(&ct->fence_lookup, fence); + if (unlikely(!g2h_fence)) { /* Don't tear down channel, as send could've timed out */ /* CT_DEAD(ct, NULL, PARSE_G2H_UNKNOWN); */ @@ -1519,6 +1541,12 @@ static int parse_g2h_response(struct xe_guc_ct *ct, u32 *msg, u32 len) xe_gt_assert(gt, fence == g2h_fence->seqno); + /* + * reinit as we might have already process this g2h_fence before + * if we received a NO_RESPONSE_BUSY reply + */ + g2h_fence_reinit(g2h_fence); + if (type == GUC_HXG_TYPE_RESPONSE_FAILURE) { g2h_fence->fail = true; g2h_fence->error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, hxg[0]); @@ -1526,6 +1554,9 @@ static int parse_g2h_response(struct xe_guc_ct *ct, u32 *msg, u32 len) } else if (type == GUC_HXG_TYPE_NO_RESPONSE_RETRY) { g2h_fence->retry = true; g2h_fence->reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, hxg[0]); + } else if (type == GUC_HXG_TYPE_NO_RESPONSE_BUSY) { + g2h_fence->wait = true; + g2h_fence->counter = FIELD_GET(GUC_HXG_BUSY_MSG_0_COUNTER, hxg[0]); } else if (g2h_fence->response_buffer) { g2h_fence->response_len = hxg_len; memcpy(g2h_fence->response_buffer, hxg, hxg_len * sizeof(u32)); @@ -1533,7 +1564,9 @@ static int parse_g2h_response(struct xe_guc_ct *ct, u32 *msg, u32 len) g2h_fence->response_data = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, hxg[0]); } - g2h_release_space(ct, GUC_CTB_HXG_MSG_MAX_LEN); + /* don't release any space if it was an intermediate message */ + if (!g2h_fence->wait) + g2h_release_space(ct, GUC_CTB_HXG_MSG_MAX_LEN); /* WRITE_ONCE pairs with READ_ONCEs in guc_ct_send_recv. */ WRITE_ONCE(g2h_fence->done, true); @@ -1570,6 +1603,7 @@ static int parse_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len) case GUC_HXG_TYPE_RESPONSE_SUCCESS: case GUC_HXG_TYPE_RESPONSE_FAILURE: case GUC_HXG_TYPE_NO_RESPONSE_RETRY: + case GUC_HXG_TYPE_NO_RESPONSE_BUSY: ret = parse_g2h_response(ct, msg, len); break; default: diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h b/drivers/gpu/drm/xe/xe_guc_ct_types.h index 5da1ce5dc372..f88e588af0d3 100644 --- a/drivers/gpu/drm/xe/xe_guc_ct_types.h +++ b/drivers/gpu/drm/xe/xe_guc_ct_types.h @@ -102,9 +102,9 @@ struct xe_dead_ct { bool reported; /** @worker: worker thread to get out of interrupt context before dumping */ struct work_struct worker; - /** snapshot_ct: copy of CT state and CTB content at point of error */ + /** @snapshot_ct: copy of CT state and CTB content at point of error */ struct xe_guc_ct_snapshot *snapshot_ct; - /** snapshot_log: copy of GuC log at point of error */ + /** @snapshot_log: copy of GuC log at point of error */ struct xe_guc_log_snapshot *snapshot_log; }; @@ -134,9 +134,9 @@ struct xe_guc_ct { spinlock_t fast_lock; /** @ctbs: buffers for sending and receiving commands */ struct { - /** @ctbs.send: Host to GuC (H2G, send) channel */ + /** @ctbs.h2g: Host to GuC (H2G, send) channel */ struct guc_ctb h2g; - /** @ctbs.recv: GuC to Host (G2H, receive) channel */ + /** @ctbs.g2h: GuC to Host (G2H, receive) channel */ struct guc_ctb g2h; } ctbs; /** @g2h_outstanding: number of outstanding G2H */ diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h index b73fae063fac..3fbda4798cff 100644 --- a/drivers/gpu/drm/xe/xe_guc_fwif.h +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h @@ -3,8 +3,8 @@ * Copyright © 2022 Intel Corporation */ -#ifndef _XE_GUC_FWIF_H -#define _XE_GUC_FWIF_H +#ifndef _XE_GUC_FWIF_H_ +#define _XE_GUC_FWIF_H_ #include diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c index bb8c4e793492..59f2fa79ad42 100644 --- a/drivers/gpu/drm/xe/xe_guc_pc.c +++ b/drivers/gpu/drm/xe/xe_guc_pc.c @@ -890,9 +890,26 @@ void xe_guc_pc_init_early(struct xe_guc_pc *pc) pc_init_fused_rp_values(pc); } +static bool pc_needs_min_freq_change(struct xe_guc_pc *pc) +{ + struct xe_device *xe = pc_to_xe(pc); + struct xe_gt *gt = pc_to_gt(pc); + + if (XE_DEVICE_WA(xe, 14022085890)) + return true; + + if (xe_gt_is_media_type(gt)) + return false; + + if (xe->info.platform == XE_BATTLEMAGE || + xe->info.platform == XE_CRESCENTISLAND) + return true; + + return false; +} + static int pc_adjust_freq_bounds(struct xe_guc_pc *pc) { - struct xe_tile *tile = gt_to_tile(pc_to_gt(pc)); int ret; lockdep_assert_held(&pc->freq_lock); @@ -919,7 +936,18 @@ static int pc_adjust_freq_bounds(struct xe_guc_pc *pc) if (pc_get_min_freq(pc) > pc->rp0_freq) ret = pc_set_min_freq(pc, pc->rp0_freq); - if (XE_DEVICE_WA(tile_to_xe(tile), 14022085890)) + /* + * Setting GT RP min frequency to 1.2GHz by default for + * GT0(Graphics) Tile of BMG and CRI. + * + * While BMG G21 WA will apply min frequency for + * both GT0(Graphics) and GT1(Media) Tile. + * + * This is an active frequency, so if the device is idle + * we aren't expecting high power output across board + * + */ + if (pc_needs_min_freq_change(pc)) ret = pc_set_min_freq(pc, max(BMG_MIN_FREQ, pc_get_min_freq(pc))); out: @@ -1288,18 +1316,16 @@ int xe_guc_pc_start(struct xe_guc_pc *pc) * xe_guc_pc_stop - Stop GuC's Power Conservation component * @pc: Xe_GuC_PC instance */ -int xe_guc_pc_stop(struct xe_guc_pc *pc) +void xe_guc_pc_stop(struct xe_guc_pc *pc) { struct xe_device *xe = pc_to_xe(pc); if (xe->info.skip_guc_pc) - return 0; + return; mutex_lock(&pc->freq_lock); pc->freq_ready = false; mutex_unlock(&pc->freq_lock); - - return 0; } /** @@ -1314,10 +1340,10 @@ static void xe_guc_pc_fini_hw(void *arg) if (xe_device_wedged(xe)) return; - CLASS(xe_force_wake, fw_ref)(gt_to_fw(pc_to_gt(pc)), XE_FW_GT); - XE_WARN_ON(xe_guc_pc_stop(pc)); + xe_guc_pc_stop(pc); /* Bind requested freq to mert_freq_cap before unload */ + CLASS(xe_force_wake, fw_ref)(gt_to_fw(pc_to_gt(pc)), XE_FW_GT); pc_set_cur_freq(pc, min(pc_max_freq_cap(pc), xe_guc_pc_get_rpe_freq(pc))); } diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h b/drivers/gpu/drm/xe/xe_guc_pc.h index 0678a4e787b3..1025a2b15f5f 100644 --- a/drivers/gpu/drm/xe/xe_guc_pc.h +++ b/drivers/gpu/drm/xe/xe_guc_pc.h @@ -13,7 +13,7 @@ struct drm_printer; int xe_guc_pc_init(struct xe_guc_pc *pc); int xe_guc_pc_start(struct xe_guc_pc *pc); -int xe_guc_pc_stop(struct xe_guc_pc *pc); +void xe_guc_pc_stop(struct xe_guc_pc *pc); void xe_guc_pc_print(struct xe_guc_pc *pc, struct drm_printer *p); int xe_guc_pc_action_set_param(struct xe_guc_pc *pc, u8 id, u32 value); int xe_guc_pc_action_unset_param(struct xe_guc_pc *pc, u8 id); diff --git a/drivers/gpu/drm/xe/xe_guc_relay_types.h b/drivers/gpu/drm/xe/xe_guc_relay_types.h index 20eee10856b2..b99a6686416b 100644 --- a/drivers/gpu/drm/xe/xe_guc_relay_types.h +++ b/drivers/gpu/drm/xe/xe_guc_relay_types.h @@ -15,7 +15,7 @@ * struct xe_guc_relay - Data used by the VF-PF Relay Communication over GuC. */ struct xe_guc_relay { - /**@lock: protects all internal data. */ + /** @lock: protects all internal data. */ spinlock_t lock; /** @worker: dispatches incoming action messages. */ diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c index a145234f662b..b1222b42174c 100644 --- a/drivers/gpu/drm/xe/xe_guc_submit.c +++ b/drivers/gpu/drm/xe/xe_guc_submit.c @@ -259,24 +259,12 @@ static void guc_submit_sw_fini(struct drm_device *drm, void *arg) } static void guc_submit_fini(void *arg) -{ - struct xe_guc *guc = arg; - - /* Forcefully kill any remaining exec queues */ - xe_guc_ct_stop(&guc->ct); - guc_submit_reset_prepare(guc); - xe_guc_softreset(guc); - xe_guc_submit_stop(guc); - xe_uc_fw_sanitize(&guc->fw); - xe_guc_submit_pause_abort(guc); -} - -static void guc_submit_wedged_fini(void *arg) { struct xe_guc *guc = arg; struct xe_exec_queue *q; unsigned long index; + /* Drop any wedged queue refs */ mutex_lock(&guc->submission_state.lock); xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) { if (exec_queue_wedged(q)) { @@ -286,6 +274,14 @@ static void guc_submit_wedged_fini(void *arg) } } mutex_unlock(&guc->submission_state.lock); + + /* Forcefully kill any remaining exec queues */ + xe_guc_ct_stop(&guc->ct); + guc_submit_reset_prepare(guc); + xe_guc_softreset(guc); + xe_guc_submit_stop(guc); + xe_uc_fw_sanitize(&guc->fw); + xe_guc_submit_pause_abort(guc); } static const struct xe_exec_queue_ops guc_exec_queue_ops; @@ -1320,10 +1316,8 @@ static void disable_scheduling_deregister(struct xe_guc *guc, void xe_guc_submit_wedge(struct xe_guc *guc) { struct xe_device *xe = guc_to_xe(guc); - struct xe_gt *gt = guc_to_gt(guc); struct xe_exec_queue *q; unsigned long index; - int err; xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode); @@ -1335,15 +1329,6 @@ void xe_guc_submit_wedge(struct xe_guc *guc) return; if (xe->wedged.mode == XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET) { - err = devm_add_action_or_reset(guc_to_xe(guc)->drm.dev, - guc_submit_wedged_fini, guc); - if (err) { - xe_gt_err(gt, "Failed to register clean-up on wedged.mode=%s; " - "Although device is wedged.\n", - xe_wedged_mode_to_string(XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET)); - return; - } - mutex_lock(&guc->submission_state.lock); xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) if (xe_exec_queue_get_unless_zero(q)) @@ -2983,9 +2968,10 @@ int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) if (unlikely(!q)) return -EPROTO; - xe_gt_info(gt, "Engine reset: engine_class=%s, logical_mask: 0x%x, guc_id=%d, state=0x%0x", - xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id, - atomic_read(&q->guc->state)); + if (!exec_queue_killed(q)) + xe_gt_info(gt, "Engine reset: engine_class=%s, logical_mask: 0x%x, guc_id=%d, state=0x%0x", + xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id, + atomic_read(&q->guc->state)); trace_xe_exec_queue_reset(q); diff --git a/drivers/gpu/drm/xe/xe_guc_submit_types.h b/drivers/gpu/drm/xe/xe_guc_submit_types.h index 5ccc5f959bb3..7824f61b1290 100644 --- a/drivers/gpu/drm/xe/xe_guc_submit_types.h +++ b/drivers/gpu/drm/xe/xe_guc_submit_types.h @@ -138,7 +138,7 @@ struct xe_guc_submit_exec_queue_snapshot { u32 primary; /** @multi_queue.pos: Position of the exec queue within the multi queue group */ u8 pos; - /** @valid: The exec queue is part of a multi queue group */ + /** @multi_queue.valid: The exec queue is part of a multi queue group */ bool valid; } multi_queue; }; diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c index 6dd05fac6595..0f0e08bcc182 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.c +++ b/drivers/gpu/drm/xe/xe_hw_engine.c @@ -67,7 +67,7 @@ static const struct engine_info engine_infos[] = { .class = XE_ENGINE_CLASS_COPY, .instance = 0, .irq_offset = ilog2(INTR_BCS(0)), - .domain = XE_FW_RENDER, + .domain = XE_FW_GT, .mmio_base = BLT_RING_BASE, }, [XE_HW_ENGINE_BCS1] = { @@ -75,7 +75,7 @@ static const struct engine_info engine_infos[] = { .class = XE_ENGINE_CLASS_COPY, .instance = 1, .irq_offset = ilog2(INTR_BCS(1)), - .domain = XE_FW_RENDER, + .domain = XE_FW_GT, .mmio_base = XEHPC_BCS1_RING_BASE, }, [XE_HW_ENGINE_BCS2] = { @@ -83,7 +83,7 @@ static const struct engine_info engine_infos[] = { .class = XE_ENGINE_CLASS_COPY, .instance = 2, .irq_offset = ilog2(INTR_BCS(2)), - .domain = XE_FW_RENDER, + .domain = XE_FW_GT, .mmio_base = XEHPC_BCS2_RING_BASE, }, [XE_HW_ENGINE_BCS3] = { @@ -91,7 +91,7 @@ static const struct engine_info engine_infos[] = { .class = XE_ENGINE_CLASS_COPY, .instance = 3, .irq_offset = ilog2(INTR_BCS(3)), - .domain = XE_FW_RENDER, + .domain = XE_FW_GT, .mmio_base = XEHPC_BCS3_RING_BASE, }, [XE_HW_ENGINE_BCS4] = { @@ -99,7 +99,7 @@ static const struct engine_info engine_infos[] = { .class = XE_ENGINE_CLASS_COPY, .instance = 4, .irq_offset = ilog2(INTR_BCS(4)), - .domain = XE_FW_RENDER, + .domain = XE_FW_GT, .mmio_base = XEHPC_BCS4_RING_BASE, }, [XE_HW_ENGINE_BCS5] = { @@ -107,7 +107,7 @@ static const struct engine_info engine_infos[] = { .class = XE_ENGINE_CLASS_COPY, .instance = 5, .irq_offset = ilog2(INTR_BCS(5)), - .domain = XE_FW_RENDER, + .domain = XE_FW_GT, .mmio_base = XEHPC_BCS5_RING_BASE, }, [XE_HW_ENGINE_BCS6] = { @@ -115,7 +115,7 @@ static const struct engine_info engine_infos[] = { .class = XE_ENGINE_CLASS_COPY, .instance = 6, .irq_offset = ilog2(INTR_BCS(6)), - .domain = XE_FW_RENDER, + .domain = XE_FW_GT, .mmio_base = XEHPC_BCS6_RING_BASE, }, [XE_HW_ENGINE_BCS7] = { @@ -123,7 +123,7 @@ static const struct engine_info engine_infos[] = { .class = XE_ENGINE_CLASS_COPY, .irq_offset = ilog2(INTR_BCS(7)), .instance = 7, - .domain = XE_FW_RENDER, + .domain = XE_FW_GT, .mmio_base = XEHPC_BCS7_RING_BASE, }, [XE_HW_ENGINE_BCS8] = { @@ -131,7 +131,7 @@ static const struct engine_info engine_infos[] = { .class = XE_ENGINE_CLASS_COPY, .instance = 8, .irq_offset = ilog2(INTR_BCS8), - .domain = XE_FW_RENDER, + .domain = XE_FW_GT, .mmio_base = XEHPC_BCS8_RING_BASE, }, @@ -282,27 +282,6 @@ static void hw_engine_fini(void *arg) hwe->gt = NULL; } -/** - * xe_hw_engine_mmio_write32() - Write engine register - * @hwe: engine - * @reg: register to write into - * @val: desired 32-bit value to write - * - * This function will write val into an engine specific register. - * Forcewake must be held by the caller. - * - */ -void xe_hw_engine_mmio_write32(struct xe_hw_engine *hwe, - struct xe_reg reg, u32 val) -{ - xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base)); - xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain); - - reg.addr += hwe->mmio_base; - - xe_mmio_write32(&hwe->gt->mmio, reg, val); -} - /** * xe_hw_engine_mmio_read32() - Read engine register * @hwe: engine @@ -325,24 +304,8 @@ u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg) void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe) { - u32 ccs_mask = - xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE); - u32 ring_mode = REG_MASKED_FIELD_ENABLE(GFX_DISABLE_LEGACY_MODE); - - if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask) - xe_mmio_write32(&hwe->gt->mmio, RCU_MODE, - REG_MASKED_FIELD_ENABLE(RCU_MODE_CCS_ENABLE)); - - xe_hw_engine_mmio_write32(hwe, RING_HWSTAM(0), ~0x0); - xe_hw_engine_mmio_write32(hwe, RING_HWS_PGA(0), - xe_bo_ggtt_addr(hwe->hwsp)); - - if (xe_device_has_msix(gt_to_xe(hwe->gt))) - ring_mode |= REG_MASKED_FIELD_ENABLE(GFX_MSIX_INTERRUPT_ENABLE); - xe_hw_engine_mmio_write32(hwe, RING_MODE(0), ring_mode); - xe_hw_engine_mmio_write32(hwe, RING_MI_MODE(0), - REG_MASKED_FIELD_DISABLE(STOP_RING)); - xe_hw_engine_mmio_read32(hwe, RING_MI_MODE(0)); + xe_mmio_write32(&hwe->gt->mmio, RING_HWS_PGA(hwe->mmio_base), + xe_bo_ggtt_addr(hwe->hwsp)); } static bool xe_hw_engine_match_fixed_cslice_mode(const struct xe_device *xe, @@ -390,7 +353,7 @@ xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe) * BLIT_CCTL registers are needed to be programmed to un-cached. */ { XE_RTP_NAME("BLIT_CCTL_default_MOCS"), - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED), + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274), ENGINE_CLASS(COPY)), XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0), BLIT_CCTL_DST_MOCS_MASK | @@ -436,13 +399,23 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe) struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); const struct xe_rtp_entry_sr engine_entries[] = { { XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"), - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED)), + XE_RTP_RULES(FUNC(xe_rtp_match_always)), XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0), CMD_CCTL_WRITE_OVERRIDE_MASK | CMD_CCTL_READ_OVERRIDE_MASK, ring_cmd_cctl_val, XE_RTP_ACTION_FLAG(ENGINE_BASE))) }, + { XE_RTP_NAME("Disable HW status page updates for interrupts"), + XE_RTP_RULES(FUNC(xe_rtp_match_always)), + XE_RTP_ACTIONS(SET(RING_HWSTAM(0), ~0x0, + XE_RTP_ACTION_FLAG(ENGINE_BASE))) + }, + { XE_RTP_NAME("Disable engine 'legacy' mode"), + XE_RTP_RULES(FUNC(xe_rtp_match_always)), + XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_DISABLE_LEGACY_MODE, + XE_RTP_ACTION_FLAG(ENGINE_BASE))) + }, /* * To allow the GSC engine to go idle on MTL we need to enable * idle messaging and set the hysteresis value (we use 0xA=5us @@ -465,12 +438,22 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe) XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ, XE_RTP_ACTION_FLAG(ENGINE_BASE))) }, + { XE_RTP_NAME("Enable CCS Engine(s)"), + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, XE_RTP_END_VERSION_UNDEFINED), + FUNC(xe_rtp_match_first_render_or_compute)), + XE_RTP_ACTIONS(SET(RCU_MODE, RCU_MODE_CCS_ENABLE)) + }, /* Use Fixed slice CCS mode */ { XE_RTP_NAME("RCU_MODE_FIXED_SLICE_CCS_MODE"), XE_RTP_RULES(FUNC(xe_hw_engine_match_fixed_cslice_mode)), XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE)) }, + { XE_RTP_NAME("Enable MSI-X interrupt support"), + XE_RTP_RULES(FUNC(xe_rtp_match_has_msix)), + XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE, + XE_RTP_ACTION_FLAG(ENGINE_BASE))) + }, }; xe_rtp_process_to_sr(&ctx, engine_entries, ARRAY_SIZE(engine_entries), @@ -1026,6 +1009,9 @@ bool xe_hw_engine_is_reserved(struct xe_hw_engine *hwe) struct xe_gt *gt = hwe->gt; struct xe_device *xe = gt_to_xe(gt); + if (xe_device_is_admin_only(xe)) + return true; + if (hwe->class == XE_ENGINE_CLASS_OTHER) return true; diff --git a/drivers/gpu/drm/xe/xe_hw_engine.h b/drivers/gpu/drm/xe/xe_hw_engine.h index 6b5f9fa2a594..ee9218773b51 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.h +++ b/drivers/gpu/drm/xe/xe_hw_engine.h @@ -76,7 +76,6 @@ const char *xe_hw_engine_class_to_str(enum xe_engine_class class); u64 xe_hw_engine_read_timestamp(struct xe_hw_engine *hwe); enum xe_force_wake_domains xe_hw_engine_to_fw_domain(struct xe_hw_engine *hwe); -void xe_hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg, u32 val); u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg); #endif diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h index e4191a7a2c31..0f87128c6529 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine_types.h +++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h @@ -79,7 +79,7 @@ struct xe_hw_engine_class_intf { * @defaults: default scheduling properties */ struct { - /** @sched_props.set_job_timeout: Set job timeout in ms for engine */ + /** @sched_props.job_timeout_ms: Set job timeout in ms for engine */ u32 job_timeout_ms; /** @sched_props.job_timeout_min: Min job timeout in ms for engine */ u32 job_timeout_min; diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h index d86e28c5180c..5e3a11424108 100644 --- a/drivers/gpu/drm/xe/xe_hw_error.h +++ b/drivers/gpu/drm/xe/xe_hw_error.h @@ -2,8 +2,8 @@ /* * Copyright © 2025 Intel Corporation */ -#ifndef XE_HW_ERROR_H_ -#define XE_HW_ERROR_H_ +#ifndef _XE_HW_ERROR_H_ +#define _XE_HW_ERROR_H_ #include diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c index 92e423a339f1..de3f2aeffc3f 100644 --- a/drivers/gpu/drm/xe/xe_hwmon.c +++ b/drivers/gpu/drm/xe/xe_hwmon.c @@ -180,6 +180,18 @@ struct xe_hwmon { struct xe_hwmon_thermal_info temp; }; +static inline int prepare_power_limit_param2(const struct xe_hwmon *hwmon) +{ + if (hwmon->boot_power_limit_read) { + if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) + return READ_PL_ACCEPTED; + else + return READ_PL_FROM_PCODE; + } else { + return READ_PL_FROM_FW; + } +} + static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 attr, int channel, u32 *uval) { @@ -191,9 +203,7 @@ static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 att (channel == CHANNEL_CARD) ? READ_PSYSGPU_POWER_LIMIT : READ_PACKAGE_POWER_LIMIT, - hwmon->boot_power_limit_read ? - READ_PL_FROM_PCODE : READ_PL_FROM_FW), - &val0, &val1); + prepare_power_limit_param2(hwmon)), &val0, &val1); if (ret) { drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", @@ -226,10 +236,7 @@ static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr (channel == CHANNEL_CARD) ? READ_PSYSGPU_POWER_LIMIT : READ_PACKAGE_POWER_LIMIT, - hwmon->boot_power_limit_read ? - READ_PL_FROM_PCODE : READ_PL_FROM_FW), - &val0, &val1); - + prepare_power_limit_param2(hwmon)), &val0, &val1); if (ret) drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", channel, val0, val1, ret); @@ -296,7 +303,12 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg return GT_PERF_STATUS; break; case REG_PKG_ENERGY_STATUS: - if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) { + if (xe->info.platform == XE_CRESCENTISLAND) { + if (channel == CHANNEL_CARD) + return CRI_PLATFORM_ENERGY_STATUS; + else if (channel == CHANNEL_PKG) + return CRI_PACKAGE_ENERGY_STATUS; + } else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) { return PVC_GT0_PLATFORM_ENERGY_STATUS; } else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) { return PCU_CR_PACKAGE_ENERGY_STATUS; diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c index 7560a45f7f64..9e49e2241da4 100644 --- a/drivers/gpu/drm/xe/xe_irq.c +++ b/drivers/gpu/drm/xe/xe_irq.c @@ -24,6 +24,7 @@ #include "xe_mmio.h" #include "xe_pxp.h" #include "xe_sriov.h" +#include "xe_sysctrl.h" #include "xe_tile.h" /* @@ -525,6 +526,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg) xe_heci_csc_irq_handler(xe, master_ctl); xe_display_irq_handler(xe, master_ctl); xe_i2c_irq_handler(xe, master_ctl); + xe_sysctrl_irq_handler(xe, master_ctl); xe_mert_irq_handler(xe, master_ctl); gu_misc_iir = gu_misc_irq_ack(xe, master_ctl); } diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c index 9d12a0d2f0b5..9db914584347 100644 --- a/drivers/gpu/drm/xe/xe_lrc.c +++ b/drivers/gpu/drm/xe/xe_lrc.c @@ -682,25 +682,6 @@ static void set_memory_based_intr(u32 *regs, struct xe_hw_engine *hwe) } } -static int lrc_ring_mi_mode(struct xe_hw_engine *hwe) -{ - struct xe_device *xe = gt_to_xe(hwe->gt); - - if (GRAPHICS_VERx100(xe) >= 1250) - return 0x70; - else - return 0x60; -} - -static void reset_stop_ring(u32 *regs, struct xe_hw_engine *hwe) -{ - int x; - - x = lrc_ring_mi_mode(hwe); - regs[x + 1] &= ~STOP_RING; - regs[x + 1] |= STOP_RING << 16; -} - static inline bool xe_lrc_has_indirect_ring_state(struct xe_lrc *lrc) { return lrc->flags & XE_LRC_FLAG_INDIRECT_RING_STATE; @@ -980,7 +961,6 @@ static void *empty_lrc_data(struct xe_hw_engine *hwe) set_offsets(regs, reg_offsets(gt_to_xe(gt), hwe->class), hwe); set_context_control(regs, hwe); set_memory_based_intr(regs, hwe); - reset_stop_ring(regs, hwe); if (xe_gt_has_indirect_ring_state(gt)) { regs = data + xe_gt_lrc_size(gt, hwe->class) - LRC_INDIRECT_RING_STATE_SIZE; @@ -1214,7 +1194,7 @@ static ssize_t setup_invalidate_state_cache_wa(struct xe_lrc *lrc, if (xe_gt_WARN_ON(lrc->gt, max_len < 3)) return -ENOSPC; - *cmd++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1); + *cmd++ = MI_LOAD_REGISTER_IMM | MI_LRI_LRM_CS_MMIO | MI_LRI_NUM_REGS(1); *cmd++ = CS_DEBUG_MODE2(0).addr; *cmd++ = REG_MASKED_FIELD_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE); diff --git a/drivers/gpu/drm/xe/xe_mem_pool.c b/drivers/gpu/drm/xe/xe_mem_pool.c new file mode 100644 index 000000000000..d5e24d6aa88d --- /dev/null +++ b/drivers/gpu/drm/xe/xe_mem_pool.c @@ -0,0 +1,403 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2026 Intel Corporation + */ + +#include + +#include + +#include "instructions/xe_mi_commands.h" +#include "xe_bo.h" +#include "xe_device_types.h" +#include "xe_map.h" +#include "xe_mem_pool.h" +#include "xe_mem_pool_types.h" +#include "xe_tile_printk.h" + +/** + * struct xe_mem_pool - DRM MM pool for sub-allocating memory from a BO on an + * XE tile. + * + * The XE memory pool is a DRM MM manager that provides sub-allocation of memory + * from a backing buffer object (BO) on a specific XE tile. It is designed to + * manage memory for GPU workloads, allowing for efficient allocation and + * deallocation of memory regions within the BO. + * + * The memory pool maintains a primary BO that is pinned in the GGTT and mapped + * into the CPU address space for direct access. Optionally, it can also maintain + * a shadow BO that can be used for atomic updates to the primary BO's contents. + * + * The API provided by the memory pool allows clients to allocate and free memory + * regions, retrieve GPU and CPU addresses, and synchronize data between the + * primary and shadow BOs as needed. + */ +struct xe_mem_pool { + /** @base: Range allocator over [0, @size) in bytes */ + struct drm_mm base; + /** @bo: Active pool BO (GGTT-pinned, CPU-mapped). */ + struct xe_bo *bo; + /** @shadow: Shadow BO for atomic command updates. */ + struct xe_bo *shadow; + /** @swap_guard: Timeline guard updating @bo and @shadow */ + struct mutex swap_guard; + /** @cpu_addr: CPU virtual address of the active BO. */ + void *cpu_addr; + /** @is_iomem: Indicates if the BO mapping is I/O memory. */ + bool is_iomem; +}; + +static struct xe_mem_pool *node_to_pool(struct xe_mem_pool_node *node) +{ + return container_of(node->sa_node.mm, struct xe_mem_pool, base); +} + +static struct xe_tile *pool_to_tile(struct xe_mem_pool *pool) +{ + return pool->bo->tile; +} + +static void fini_pool_action(struct drm_device *drm, void *arg) +{ + struct xe_mem_pool *pool = arg; + + if (pool->is_iomem) + kvfree(pool->cpu_addr); + + drm_mm_takedown(&pool->base); +} + +static int pool_shadow_init(struct xe_mem_pool *pool) +{ + struct xe_tile *tile = pool->bo->tile; + struct xe_device *xe = tile_to_xe(tile); + struct xe_bo *shadow; + int ret; + + xe_assert(xe, !pool->shadow); + + ret = drmm_mutex_init(&xe->drm, &pool->swap_guard); + if (ret) + return ret; + + if (IS_ENABLED(CONFIG_PROVE_LOCKING)) { + fs_reclaim_acquire(GFP_KERNEL); + might_lock(&pool->swap_guard); + fs_reclaim_release(GFP_KERNEL); + } + shadow = xe_managed_bo_create_pin_map(xe, tile, + xe_bo_size(pool->bo), + XE_BO_FLAG_VRAM_IF_DGFX(tile) | + XE_BO_FLAG_GGTT | + XE_BO_FLAG_GGTT_INVALIDATE | + XE_BO_FLAG_PINNED_NORESTORE); + if (IS_ERR(shadow)) + return PTR_ERR(shadow); + + pool->shadow = shadow; + + return 0; +} + +/** + * xe_mem_pool_init() - Initialize memory pool. + * @tile: the &xe_tile where allocate. + * @size: number of bytes to allocate. + * @guard: the size of the guard region at the end of the BO that is not + * sub-allocated, in bytes. + * @flags: flags to use to create shadow pool. + * + * Initializes a memory pool for sub-allocating memory from a backing BO on the + * specified XE tile. The backing BO is pinned in the GGTT and mapped into + * the CPU address space for direct access. Optionally, a shadow BO can also be + * initialized for atomic updates to the primary BO's contents. + * + * Returns: a pointer to the &xe_mem_pool, or an error pointer on failure. + */ +struct xe_mem_pool *xe_mem_pool_init(struct xe_tile *tile, u32 size, + u32 guard, int flags) +{ + struct xe_device *xe = tile_to_xe(tile); + struct xe_mem_pool *pool; + struct xe_bo *bo; + u32 managed_size; + int ret; + + xe_tile_assert(tile, size > guard); + managed_size = size - guard; + + pool = drmm_kzalloc(&xe->drm, sizeof(*pool), GFP_KERNEL); + if (!pool) + return ERR_PTR(-ENOMEM); + + bo = xe_managed_bo_create_pin_map(xe, tile, size, + XE_BO_FLAG_VRAM_IF_DGFX(tile) | + XE_BO_FLAG_GGTT | + XE_BO_FLAG_GGTT_INVALIDATE | + XE_BO_FLAG_PINNED_NORESTORE); + if (IS_ERR(bo)) { + xe_tile_err(tile, "Failed to prepare %uKiB BO for mem pool (%pe)\n", + size / SZ_1K, bo); + return ERR_CAST(bo); + } + pool->bo = bo; + pool->is_iomem = bo->vmap.is_iomem; + + if (pool->is_iomem) { + pool->cpu_addr = kvzalloc(size, GFP_KERNEL); + if (!pool->cpu_addr) + return ERR_PTR(-ENOMEM); + } else { + pool->cpu_addr = bo->vmap.vaddr; + } + + if (flags & XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY) { + ret = pool_shadow_init(pool); + + if (ret) + goto out_err; + } + + drm_mm_init(&pool->base, 0, managed_size); + ret = drmm_add_action_or_reset(&xe->drm, fini_pool_action, pool); + if (ret) + return ERR_PTR(ret); + + return pool; + +out_err: + if (flags & XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY) + xe_tile_err(tile, + "Failed to initialize shadow BO for mem pool (%d)\n", ret); + if (bo->vmap.is_iomem) + kvfree(pool->cpu_addr); + return ERR_PTR(ret); +} + +/** + * xe_mem_pool_sync() - Copy the entire contents of the main pool to shadow pool. + * @pool: the memory pool containing the primary and shadow BOs. + * + * Copies the entire contents of the primary pool to the shadow pool. This must + * be done after xe_mem_pool_init() with the XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY + * flag to ensure that the shadow pool has the same initial contents as the primary + * pool. After this initial synchronization, clients can choose to synchronize the + * shadow pool with the primary pool on a node basis using + * xe_mem_pool_sync_shadow_locked() as needed. + * + * Return: None. + */ +void xe_mem_pool_sync(struct xe_mem_pool *pool) +{ + struct xe_tile *tile = pool_to_tile(pool); + struct xe_device *xe = tile_to_xe(tile); + + xe_tile_assert(tile, pool->shadow); + + xe_map_memcpy_to(xe, &pool->shadow->vmap, 0, + pool->cpu_addr, xe_bo_size(pool->bo)); +} + +/** + * xe_mem_pool_swap_shadow_locked() - Swap the primary BO with the shadow BO. + * @pool: the memory pool containing the primary and shadow BOs. + * + * Swaps the primary buffer object with the shadow buffer object in the mem + * pool. This allows for atomic updates to the contents of the primary BO + * by first writing to the shadow BO and then swapping it with the primary BO. + * Swap_guard must be held to ensure synchronization with any concurrent swap + * operations. + * + * Return: None. + */ +void xe_mem_pool_swap_shadow_locked(struct xe_mem_pool *pool) +{ + struct xe_tile *tile = pool_to_tile(pool); + + xe_tile_assert(tile, pool->shadow); + lockdep_assert_held(&pool->swap_guard); + + swap(pool->bo, pool->shadow); + if (!pool->bo->vmap.is_iomem) + pool->cpu_addr = pool->bo->vmap.vaddr; +} + +/** + * xe_mem_pool_sync_shadow_locked() - Copy node from primary pool to shadow pool. + * @node: the node allocated in the memory pool. + * + * Copies the specified batch buffer from the primary pool to the shadow pool. + * Swap_guard must be held to ensure synchronization with any concurrent swap + * operations. + * + * Return: None. + */ +void xe_mem_pool_sync_shadow_locked(struct xe_mem_pool_node *node) +{ + struct xe_mem_pool *pool = node_to_pool(node); + struct xe_tile *tile = pool_to_tile(pool); + struct xe_device *xe = tile_to_xe(tile); + struct drm_mm_node *sa_node = &node->sa_node; + + xe_tile_assert(tile, pool->shadow); + lockdep_assert_held(&pool->swap_guard); + + xe_map_memcpy_to(xe, &pool->shadow->vmap, + sa_node->start, + pool->cpu_addr + sa_node->start, + sa_node->size); +} + +/** + * xe_mem_pool_gpu_addr() - Retrieve GPU address of memory pool. + * @pool: the memory pool + * + * Returns: GGTT address of the memory pool. + */ +u64 xe_mem_pool_gpu_addr(struct xe_mem_pool *pool) +{ + return xe_bo_ggtt_addr(pool->bo); +} + +/** + * xe_mem_pool_cpu_addr() - Retrieve CPU address of manager pool. + * @pool: the memory pool + * + * Returns: CPU virtual address of memory pool. + */ +void *xe_mem_pool_cpu_addr(struct xe_mem_pool *pool) +{ + return pool->cpu_addr; +} + +/** + * xe_mem_pool_bo_swap_guard() - Retrieve the mutex used to guard swap + * operations on a memory pool. + * @pool: the memory pool + * + * Returns: Swap guard mutex or NULL if shadow pool is not created. + */ +struct mutex *xe_mem_pool_bo_swap_guard(struct xe_mem_pool *pool) +{ + if (!pool->shadow) + return NULL; + + return &pool->swap_guard; +} + +/** + * xe_mem_pool_bo_flush_write() - Copy the data from the sub-allocation + * to the GPU memory. + * @node: the node allocated in the memory pool to flush. + */ +void xe_mem_pool_bo_flush_write(struct xe_mem_pool_node *node) +{ + struct xe_mem_pool *pool = node_to_pool(node); + struct xe_tile *tile = pool_to_tile(pool); + struct xe_device *xe = tile_to_xe(tile); + struct drm_mm_node *sa_node = &node->sa_node; + + if (!pool->bo->vmap.is_iomem) + return; + + xe_map_memcpy_to(xe, &pool->bo->vmap, sa_node->start, + pool->cpu_addr + sa_node->start, + sa_node->size); +} + +/** + * xe_mem_pool_bo_sync_read() - Copy the data from GPU memory to the + * sub-allocation. + * @node: the node allocated in the memory pool to read back. + */ +void xe_mem_pool_bo_sync_read(struct xe_mem_pool_node *node) +{ + struct xe_mem_pool *pool = node_to_pool(node); + struct xe_tile *tile = pool_to_tile(pool); + struct xe_device *xe = tile_to_xe(tile); + struct drm_mm_node *sa_node = &node->sa_node; + + if (!pool->bo->vmap.is_iomem) + return; + + xe_map_memcpy_from(xe, pool->cpu_addr + sa_node->start, + &pool->bo->vmap, sa_node->start, sa_node->size); +} + +/** + * xe_mem_pool_alloc_node() - Allocate a new node for use with xe_mem_pool. + * + * Returns: node structure or an ERR_PTR(-ENOMEM). + */ +struct xe_mem_pool_node *xe_mem_pool_alloc_node(void) +{ + struct xe_mem_pool_node *node = kzalloc_obj(*node); + + if (!node) + return ERR_PTR(-ENOMEM); + + return node; +} + +/** + * xe_mem_pool_insert_node() - Insert a node into the memory pool. + * @pool: the memory pool to insert into + * @node: the node to insert + * @size: the size of the node to be allocated in bytes. + * + * Inserts a node into the specified memory pool using drm_mm for + * allocation. + * + * Returns: 0 on success or a negative error code on failure. + */ +int xe_mem_pool_insert_node(struct xe_mem_pool *pool, + struct xe_mem_pool_node *node, u32 size) +{ + if (!pool) + return -EINVAL; + + return drm_mm_insert_node(&pool->base, &node->sa_node, size); +} + +/** + * xe_mem_pool_free_node() - Free a node allocated from the memory pool. + * @node: the node to free + * + * Returns: None. + */ +void xe_mem_pool_free_node(struct xe_mem_pool_node *node) +{ + if (!node) + return; + + drm_mm_remove_node(&node->sa_node); + kfree(node); +} + +/** + * xe_mem_pool_node_cpu_addr() - Retrieve CPU address of the node. + * @node: the node allocated in the memory pool + * + * Returns: CPU virtual address of the node. + */ +void *xe_mem_pool_node_cpu_addr(struct xe_mem_pool_node *node) +{ + struct xe_mem_pool *pool = node_to_pool(node); + + return xe_mem_pool_cpu_addr(pool) + node->sa_node.start; +} + +/** + * xe_mem_pool_dump() - Dump the state of the DRM MM manager for debugging. + * @pool: the memory pool info be dumped. + * @p: The DRM printer to use for output. + * + * Only the drm managed region is dumped, not the state of the BOs or any other + * pool information. + * + * Returns: None. + */ +void xe_mem_pool_dump(struct xe_mem_pool *pool, struct drm_printer *p) +{ + drm_mm_print(&pool->base, p); +} diff --git a/drivers/gpu/drm/xe/xe_mem_pool.h b/drivers/gpu/drm/xe/xe_mem_pool.h new file mode 100644 index 000000000000..89cd2555fe91 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_mem_pool.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ +#ifndef _XE_MEM_POOL_H_ +#define _XE_MEM_POOL_H_ + +#include +#include + +#include +#include "xe_mem_pool_types.h" + +struct drm_printer; +struct xe_mem_pool; +struct xe_tile; + +struct xe_mem_pool *xe_mem_pool_init(struct xe_tile *tile, u32 size, + u32 guard, int flags); +void xe_mem_pool_sync(struct xe_mem_pool *pool); +void xe_mem_pool_swap_shadow_locked(struct xe_mem_pool *pool); +void xe_mem_pool_sync_shadow_locked(struct xe_mem_pool_node *node); +u64 xe_mem_pool_gpu_addr(struct xe_mem_pool *pool); +void *xe_mem_pool_cpu_addr(struct xe_mem_pool *pool); +struct mutex *xe_mem_pool_bo_swap_guard(struct xe_mem_pool *pool); +void xe_mem_pool_bo_flush_write(struct xe_mem_pool_node *node); +void xe_mem_pool_bo_sync_read(struct xe_mem_pool_node *node); +struct xe_mem_pool_node *xe_mem_pool_alloc_node(void); +int xe_mem_pool_insert_node(struct xe_mem_pool *pool, + struct xe_mem_pool_node *node, u32 size); +void xe_mem_pool_free_node(struct xe_mem_pool_node *node); +void *xe_mem_pool_node_cpu_addr(struct xe_mem_pool_node *node); +void xe_mem_pool_dump(struct xe_mem_pool *pool, struct drm_printer *p); + +#endif diff --git a/drivers/gpu/drm/xe/xe_mem_pool_types.h b/drivers/gpu/drm/xe/xe_mem_pool_types.h new file mode 100644 index 000000000000..d5e926c93351 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_mem_pool_types.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ + +#ifndef _XE_MEM_POOL_TYPES_H_ +#define _XE_MEM_POOL_TYPES_H_ + +#include + +#define XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY BIT(0) + +/** + * struct xe_mem_pool_node - Sub-range allocations from mem pool. + */ +struct xe_mem_pool_node { + /** @sa_node: drm_mm_node for this allocation. */ + struct drm_mm_node sa_node; +}; + +#endif diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c index fc918b4fba54..a87fbc1e9fb1 100644 --- a/drivers/gpu/drm/xe/xe_migrate.c +++ b/drivers/gpu/drm/xe/xe_migrate.c @@ -29,7 +29,9 @@ #include "xe_hw_engine.h" #include "xe_lrc.h" #include "xe_map.h" +#include "xe_mem_pool.h" #include "xe_mocs.h" +#include "xe_pat.h" #include "xe_printk.h" #include "xe_pt.h" #include "xe_res_cursor.h" @@ -216,7 +218,7 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m, struct xe_vm *vm, u32 *ofs) { struct xe_device *xe = tile_to_xe(tile); - u16 pat_index = xe->pat.idx[XE_CACHE_WB]; + u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB); u8 id = tile->id; u32 num_entries = NUM_PT_SLOTS, num_level = vm->pt_root[id]->level; #define VRAM_IDENTITY_MAP_COUNT 2 @@ -336,7 +338,7 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m, * if flat ccs is enabled. */ if (GRAPHICS_VER(xe) >= 20 && xe_device_has_flat_ccs(xe)) { - u16 comp_pat_index = xe->pat.idx[XE_CACHE_NONE_COMPRESSION]; + u16 comp_pat_index = xe_cache_pat_idx(xe, XE_CACHE_NONE_COMPRESSION); u64 vram_offset = IDENTITY_OFFSET + DIV_ROUND_UP_ULL(actual_phy_size, SZ_1G); u64 pt31_ofs = xe_bo_size(bo) - XE_PAGE_SIZE; @@ -636,10 +638,10 @@ static void emit_pte(struct xe_migrate *m, /* Indirect access needs compression enabled uncached PAT index */ if (GRAPHICS_VERx100(xe) >= 2000) - pat_index = is_comp_pte ? xe->pat.idx[XE_CACHE_NONE_COMPRESSION] : - xe->pat.idx[XE_CACHE_WB]; + pat_index = is_comp_pte ? xe_cache_pat_idx(xe, XE_CACHE_NONE_COMPRESSION) : + xe_cache_pat_idx(xe, XE_CACHE_WB); else - pat_index = xe->pat.idx[XE_CACHE_WB]; + pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB); ptes = DIV_ROUND_UP(size, XE_PAGE_SIZE); @@ -1166,11 +1168,12 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q, u32 batch_size, batch_size_allocated; struct xe_device *xe = gt_to_xe(gt); struct xe_res_cursor src_it, ccs_it; + struct xe_mem_pool *bb_pool; struct xe_sriov_vf_ccs_ctx *ctx; - struct xe_sa_manager *bb_pool; u64 size = xe_bo_size(src_bo); - struct xe_bb *bb = NULL; + struct xe_mem_pool_node *bb; u64 src_L0, src_L0_ofs; + struct xe_bb xe_bb_tmp; u32 src_L0_pt; int err; @@ -1208,18 +1211,18 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q, size -= src_L0; } - bb = xe_bb_alloc(gt); + bb = xe_mem_pool_alloc_node(); if (IS_ERR(bb)) return PTR_ERR(bb); bb_pool = ctx->mem.ccs_bb_pool; - scoped_guard(mutex, xe_sa_bo_swap_guard(bb_pool)) { - xe_sa_bo_swap_shadow(bb_pool); + scoped_guard(mutex, xe_mem_pool_bo_swap_guard(bb_pool)) { + xe_mem_pool_swap_shadow_locked(bb_pool); - err = xe_bb_init(bb, bb_pool, batch_size); + err = xe_mem_pool_insert_node(bb_pool, bb, batch_size * sizeof(u32)); if (err) { xe_gt_err(gt, "BB allocation failed.\n"); - xe_bb_free(bb, NULL); + kfree(bb); return err; } @@ -1227,6 +1230,7 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q, size = xe_bo_size(src_bo); batch_size = 0; + xe_bb_tmp = (struct xe_bb){ .cs = xe_mem_pool_node_cpu_addr(bb), .len = 0 }; /* * Emit PTE and copy commands here. * The CCS copy command can only support limited size. If the size to be @@ -1255,24 +1259,27 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q, xe_assert(xe, IS_ALIGNED(ccs_it.start, PAGE_SIZE)); batch_size += EMIT_COPY_CCS_DW; - emit_pte(m, bb, src_L0_pt, false, true, &src_it, src_L0, src); + emit_pte(m, &xe_bb_tmp, src_L0_pt, false, true, &src_it, src_L0, src); - emit_pte(m, bb, ccs_pt, false, false, &ccs_it, ccs_size, src); + emit_pte(m, &xe_bb_tmp, ccs_pt, false, false, &ccs_it, ccs_size, src); - bb->len = emit_flush_invalidate(bb->cs, bb->len, flush_flags); - flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs, src_is_pltt, + xe_bb_tmp.len = emit_flush_invalidate(xe_bb_tmp.cs, xe_bb_tmp.len, + flush_flags); + flush_flags = xe_migrate_ccs_copy(m, &xe_bb_tmp, src_L0_ofs, src_is_pltt, src_L0_ofs, dst_is_pltt, src_L0, ccs_ofs, true); - bb->len = emit_flush_invalidate(bb->cs, bb->len, flush_flags); + xe_bb_tmp.len = emit_flush_invalidate(xe_bb_tmp.cs, xe_bb_tmp.len, + flush_flags); size -= src_L0; } - xe_assert(xe, (batch_size_allocated == bb->len)); + xe_assert(xe, (batch_size_allocated == xe_bb_tmp.len)); + xe_assert(xe, bb->sa_node.size == xe_bb_tmp.len * sizeof(u32)); src_bo->bb_ccs[read_write] = bb; xe_sriov_vf_ccs_rw_update_bb_addr(ctx); - xe_sa_bo_sync_shadow(bb->bo); + xe_mem_pool_sync_shadow_locked(bb); } return 0; @@ -1297,10 +1304,10 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q, void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo, enum xe_sriov_vf_ccs_rw_ctxs read_write) { - struct xe_bb *bb = src_bo->bb_ccs[read_write]; + struct xe_mem_pool_node *bb = src_bo->bb_ccs[read_write]; struct xe_device *xe = xe_bo_device(src_bo); + struct xe_mem_pool *bb_pool; struct xe_sriov_vf_ccs_ctx *ctx; - struct xe_sa_manager *bb_pool; u32 *cs; xe_assert(xe, IS_SRIOV_VF(xe)); @@ -1308,17 +1315,17 @@ void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo, ctx = &xe->sriov.vf.ccs.contexts[read_write]; bb_pool = ctx->mem.ccs_bb_pool; - guard(mutex) (xe_sa_bo_swap_guard(bb_pool)); - xe_sa_bo_swap_shadow(bb_pool); + scoped_guard(mutex, xe_mem_pool_bo_swap_guard(bb_pool)) { + xe_mem_pool_swap_shadow_locked(bb_pool); - cs = xe_sa_bo_cpu_addr(bb->bo); - memset(cs, MI_NOOP, bb->len * sizeof(u32)); - xe_sriov_vf_ccs_rw_update_bb_addr(ctx); + cs = xe_mem_pool_node_cpu_addr(bb); + memset(cs, MI_NOOP, bb->sa_node.size); + xe_sriov_vf_ccs_rw_update_bb_addr(ctx); - xe_sa_bo_sync_shadow(bb->bo); - - xe_bb_free(bb, NULL); - src_bo->bb_ccs[read_write] = NULL; + xe_mem_pool_sync_shadow_locked(bb); + xe_mem_pool_free_node(bb); + src_bo->bb_ccs[read_write] = NULL; + } } /** @@ -1870,7 +1877,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m, /* For sysmem PTE's, need to map them in our hole.. */ if (!IS_DGFX(xe)) { - u16 pat_index = xe->pat.idx[XE_CACHE_WB]; + u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB); u32 ptes, ofs; ppgtt_ofs = NUM_KERNEL_PDE - 1; @@ -2092,7 +2099,7 @@ static void build_pt_update_batch_sram(struct xe_migrate *m, struct drm_pagemap_addr *sram_addr, u32 size, int level) { - u16 pat_index = tile_to_xe(m->tile)->pat.idx[XE_CACHE_WB]; + u16 pat_index = xe_cache_pat_idx(tile_to_xe(m->tile), XE_CACHE_WB); u64 gpu_page_size = 0x1ull << xe_pt_shift(level); u32 ptes; int i = 0; diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h index 169279d9d8c2..965c45889c72 100644 --- a/drivers/gpu/drm/xe/xe_migrate.h +++ b/drivers/gpu/drm/xe/xe_migrate.h @@ -3,8 +3,8 @@ * Copyright © 2020 Intel Corporation */ -#ifndef _XE_MIGRATE_ -#define _XE_MIGRATE_ +#ifndef _XE_MIGRATE_H_ +#define _XE_MIGRATE_H_ #include diff --git a/drivers/gpu/drm/xe/xe_nvm.h b/drivers/gpu/drm/xe/xe_nvm.h index fd3467ad35a4..b14722103f81 100644 --- a/drivers/gpu/drm/xe/xe_nvm.h +++ b/drivers/gpu/drm/xe/xe_nvm.h @@ -3,8 +3,8 @@ * Copyright(c) 2019-2025 Intel Corporation. All rights reserved. */ -#ifndef __XE_NVM_H__ -#define __XE_NVM_H__ +#ifndef _XE_NVM_H_ +#define _XE_NVM_H_ struct xe_device; diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c index 6337e671c97a..5de5bf19240a 100644 --- a/drivers/gpu/drm/xe/xe_oa.c +++ b/drivers/gpu/drm/xe/xe_oa.c @@ -9,11 +9,13 @@ #include #include +#include #include #include #include #include +#include #include "abi/guc_actions_slpc_abi.h" #include "instructions/xe_mi_commands.h" @@ -213,32 +215,45 @@ static u32 xe_oa_hw_tail_read(struct xe_oa_stream *stream) #define oa_report_header_64bit(__s) \ ((__s)->oa_buffer.format->header == HDR_64_BIT) -static u64 oa_report_id(struct xe_oa_stream *stream, void *report) +static u64 oa_report_id(struct xe_oa_stream *stream, u32 report_offset) { - return oa_report_header_64bit(stream) ? *(u64 *)report : *(u32 *)report; -} + struct iosys_map *map = &stream->oa_buffer.bo->vmap; -static void oa_report_id_clear(struct xe_oa_stream *stream, u32 *report) -{ - if (oa_report_header_64bit(stream)) - *(u64 *)report = 0; - else - *report = 0; -} - -static u64 oa_timestamp(struct xe_oa_stream *stream, void *report) -{ return oa_report_header_64bit(stream) ? - *((u64 *)report + 1) : - *((u32 *)report + 1); + xe_map_rd(stream->oa->xe, map, report_offset, u64) : + xe_map_rd(stream->oa->xe, map, report_offset, u32); } -static void oa_timestamp_clear(struct xe_oa_stream *stream, u32 *report) +static void oa_report_id_clear(struct xe_oa_stream *stream, u32 report_offset) { - if (oa_report_header_64bit(stream)) - *(u64 *)&report[2] = 0; - else - report[1] = 0; + struct iosys_map *map = &stream->oa_buffer.bo->vmap; + + oa_report_header_64bit(stream) ? + xe_map_wr(stream->oa->xe, map, report_offset, u64, 0) : + xe_map_wr(stream->oa->xe, map, report_offset, u32, 0); +} + +static u64 oa_timestamp(struct xe_oa_stream *stream, u32 report_offset) +{ + struct iosys_map *map = &stream->oa_buffer.bo->vmap; + + return oa_report_header_64bit(stream) ? + xe_map_rd(stream->oa->xe, map, report_offset + 8, u64) : + xe_map_rd(stream->oa->xe, map, report_offset + 4, u32); +} + +static void oa_timestamp_clear(struct xe_oa_stream *stream, u32 report_offset) +{ + struct iosys_map *map = &stream->oa_buffer.bo->vmap; + + oa_report_header_64bit(stream) ? + xe_map_wr(stream->oa->xe, map, report_offset + 8, u64, 0) : + xe_map_wr(stream->oa->xe, map, report_offset + 4, u32, 0); +} + +static bool mert_wa_14026633728(struct xe_oa_stream *s) +{ + return s->oa_unit->type == DRM_XE_OA_UNIT_TYPE_MERT && XE_DEVICE_WA(s->oa->xe, 14026633728); } static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream) @@ -275,9 +290,7 @@ static bool xe_oa_buffer_check_unlocked(struct xe_oa_stream *stream) * they were written. If not : (╯°□°）╯︵ ┻━┻ */ while (xe_oa_circ_diff(stream, tail, stream->oa_buffer.tail) >= report_size) { - void *report = stream->oa_buffer.vaddr + tail; - - if (oa_report_id(stream, report) || oa_timestamp(stream, report)) + if (oa_report_id(stream, tail) || oa_timestamp(stream, tail)) break; tail = xe_oa_circ_diff(stream, tail, report_size); @@ -311,30 +324,37 @@ static enum hrtimer_restart xe_oa_poll_check_timer_cb(struct hrtimer *hrtimer) return HRTIMER_RESTART; } +static unsigned long +xe_oa_copy_to_user(struct xe_oa_stream *stream, void __user *dst, u32 report_offset, u32 len) +{ + xe_assert(stream->oa->xe, len <= stream->oa_buffer.format->size); + + xe_map_memcpy_from(stream->oa->xe, stream->oa_buffer.bounce, + &stream->oa_buffer.bo->vmap, report_offset, len); + return copy_to_user(dst, stream->oa_buffer.bounce, len); +} + static int xe_oa_append_report(struct xe_oa_stream *stream, char __user *buf, - size_t count, size_t *offset, const u8 *report) + size_t count, size_t *offset, u32 report_offset) { int report_size = stream->oa_buffer.format->size; int report_size_partial; - u8 *oa_buf_end; if ((count - *offset) < report_size) return -ENOSPC; buf += *offset; - oa_buf_end = stream->oa_buffer.vaddr + stream->oa_buffer.circ_size; - report_size_partial = oa_buf_end - report; + report_size_partial = stream->oa_buffer.circ_size - report_offset; if (report_size_partial < report_size) { - if (copy_to_user(buf, report, report_size_partial)) + if (xe_oa_copy_to_user(stream, buf, report_offset, report_size_partial)) return -EFAULT; buf += report_size_partial; - if (copy_to_user(buf, stream->oa_buffer.vaddr, - report_size - report_size_partial)) + if (xe_oa_copy_to_user(stream, buf, 0, report_size - report_size_partial)) return -EFAULT; - } else if (copy_to_user(buf, report, report_size)) { + } else if (xe_oa_copy_to_user(stream, buf, report_offset, report_size)) { return -EFAULT; } @@ -347,7 +367,6 @@ static int xe_oa_append_reports(struct xe_oa_stream *stream, char __user *buf, size_t count, size_t *offset) { int report_size = stream->oa_buffer.format->size; - u8 *oa_buf_base = stream->oa_buffer.vaddr; u32 gtt_offset = xe_bo_ggtt_addr(stream->oa_buffer.bo); size_t start_offset = *offset; unsigned long flags; @@ -364,26 +383,24 @@ static int xe_oa_append_reports(struct xe_oa_stream *stream, char __user *buf, for (; xe_oa_circ_diff(stream, tail, head); head = xe_oa_circ_incr(stream, head, report_size)) { - u8 *report = oa_buf_base + head; - - ret = xe_oa_append_report(stream, buf, count, offset, report); + ret = xe_oa_append_report(stream, buf, count, offset, head); if (ret) break; if (!(stream->oa_buffer.circ_size % report_size)) { /* Clear out report id and timestamp to detect unlanded reports */ - oa_report_id_clear(stream, (void *)report); - oa_timestamp_clear(stream, (void *)report); + oa_report_id_clear(stream, head); + oa_timestamp_clear(stream, head); } else { - u8 *oa_buf_end = stream->oa_buffer.vaddr + stream->oa_buffer.circ_size; - u32 part = oa_buf_end - report; + struct iosys_map *map = &stream->oa_buffer.bo->vmap; + u32 part = stream->oa_buffer.circ_size - head; /* Zero out the entire report */ if (report_size <= part) { - memset(report, 0, report_size); + xe_map_memset(stream->oa->xe, map, head, 0, report_size); } else { - memset(report, 0, part); - memset(oa_buf_base, 0, report_size - part); + xe_map_memset(stream->oa->xe, map, head, 0, part); + xe_map_memset(stream->oa->xe, map, 0, 0, report_size - part); } } } @@ -436,7 +453,8 @@ static void xe_oa_init_oa_buffer(struct xe_oa_stream *stream) spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags); /* Zero out the OA buffer since we rely on zero report id and timestamp fields */ - memset(stream->oa_buffer.vaddr, 0, xe_bo_size(stream->oa_buffer.bo)); + xe_map_memset(stream->oa->xe, &stream->oa_buffer.bo->vmap, 0, 0, + xe_bo_size(stream->oa_buffer.bo)); } static u32 __format_to_oactrl(const struct xe_oa_format *format, int counter_sel_mask) @@ -699,6 +717,7 @@ static int num_lri_dwords(int num_regs) static void xe_oa_free_oa_buffer(struct xe_oa_stream *stream) { xe_bo_unpin_map_no_vm(stream->oa_buffer.bo); + kfree(stream->oa_buffer.bounce); } static void xe_oa_free_configs(struct xe_oa_stream *stream) @@ -880,18 +899,25 @@ static void xe_oa_stream_destroy(struct xe_oa_stream *stream) static int xe_oa_alloc_oa_buffer(struct xe_oa_stream *stream, size_t size) { + u32 vram = mert_wa_14026633728(stream) ? + XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(stream->oa->xe)) : + XE_BO_FLAG_SYSTEM; struct xe_bo *bo; bo = xe_bo_create_pin_map_novm(stream->oa->xe, stream->gt->tile, size, ttm_bo_type_kernel, - XE_BO_FLAG_SYSTEM | XE_BO_FLAG_GGTT, false); + vram | XE_BO_FLAG_GGTT, false); if (IS_ERR(bo)) return PTR_ERR(bo); stream->oa_buffer.bo = bo; - /* mmap implementation requires OA buffer to be in system memory */ - xe_assert(stream->oa->xe, bo->vmap.is_iomem == 0); - stream->oa_buffer.vaddr = bo->vmap.vaddr; + + stream->oa_buffer.bounce = kmalloc(stream->oa_buffer.format->size, GFP_KERNEL); + if (!stream->oa_buffer.bounce) { + xe_bo_unpin_map_no_vm(stream->oa_buffer.bo); + return -ENOMEM; + } + return 0; } @@ -1673,8 +1699,6 @@ static int xe_oa_mmap(struct file *file, struct vm_area_struct *vma) { struct xe_oa_stream *stream = file->private_data; struct xe_bo *bo = stream->oa_buffer.bo; - unsigned long start = vma->vm_start; - int i, ret; if (xe_observation_paranoid && !perfmon_capable()) { drm_dbg(&stream->oa->xe->drm, "Insufficient privilege to map OA buffer\n"); @@ -1682,7 +1706,7 @@ static int xe_oa_mmap(struct file *file, struct vm_area_struct *vma) } /* Can mmap the entire OA buffer or nothing (no partial OA buffer mmaps) */ - if (vma->vm_end - vma->vm_start != xe_bo_size(stream->oa_buffer.bo)) { + if (vma->vm_end - vma->vm_start != xe_bo_size(bo)) { drm_dbg(&stream->oa->xe->drm, "Wrong mmap size, must be OA buffer size\n"); return -EINVAL; } @@ -1698,17 +1722,7 @@ static int xe_oa_mmap(struct file *file, struct vm_area_struct *vma) vm_flags_mod(vma, VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | VM_DONTCOPY, VM_MAYWRITE | VM_MAYEXEC); - xe_assert(stream->oa->xe, bo->ttm.ttm->num_pages == vma_pages(vma)); - for (i = 0; i < bo->ttm.ttm->num_pages; i++) { - ret = remap_pfn_range(vma, start, page_to_pfn(bo->ttm.ttm->pages[i]), - PAGE_SIZE, vma->vm_page_prot); - if (ret) - break; - - start += PAGE_SIZE; - } - - return ret; + return drm_gem_mmap_obj(&bo->ttm.base, xe_bo_size(bo), vma); } static const struct file_operations xe_oa_fops = { diff --git a/drivers/gpu/drm/xe/xe_oa_types.h b/drivers/gpu/drm/xe/xe_oa_types.h index b03ffd513483..3d9ec8490899 100644 --- a/drivers/gpu/drm/xe/xe_oa_types.h +++ b/drivers/gpu/drm/xe/xe_oa_types.h @@ -67,7 +67,7 @@ struct xe_oa_format { u32 counter_select; /** @size: record size as written by HW (multiple of 64 byte cachelines) */ int size; - /** @type: of enum @drm_xe_oa_format_type */ + /** @type: of enum drm_xe_oa_format_type */ int type; /** @header: 32 or 64 bit report headers */ enum xe_oa_report_header header; @@ -154,16 +154,18 @@ struct xe_oa { u16 oa_unit_ids; }; -/** @xe_oa_buffer: State of the stream OA buffer */ +/** + * struct xe_oa_buffer - State of the stream OA buffer + */ struct xe_oa_buffer { /** @format: data format */ const struct xe_oa_format *format; - /** @format: xe_bo backing the OA buffer */ + /** @bo: xe_bo backing the OA buffer */ struct xe_bo *bo; - /** @vaddr: mapped vaddr of the OA buffer */ - u8 *vaddr; + /** @bounce: bounce buffer used with xe_map layer */ + void *bounce; /** @ptr_lock: Lock protecting reads/writes to head/tail pointers */ spinlock_t ptr_lock; diff --git a/drivers/gpu/drm/xe/xe_pagefault_types.h b/drivers/gpu/drm/xe/xe_pagefault_types.h index b3289219b1be..c4ee625b93dd 100644 --- a/drivers/gpu/drm/xe/xe_pagefault_types.h +++ b/drivers/gpu/drm/xe/xe_pagefault_types.h @@ -86,7 +86,7 @@ struct xe_pagefault { u8 engine_class; /** @consumer.engine_instance: engine instance */ u8 engine_instance; - /** consumer.reserved: reserved bits for future expansion */ + /** @consumer.reserved: reserved bits for future expansion */ u64 reserved; } consumer; /** @@ -112,7 +112,7 @@ struct xe_pagefault { }; /** - * struct xe_pagefault_queue: Xe pagefault queue (consumer) + * struct xe_pagefault_queue - Xe pagefault queue (consumer) * * Used to capture all device page faults for deferred processing. Size this * queue to absorb the device’s worst-case number of outstanding faults. diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c index 356f53bdb83c..fad5b5a5ed4a 100644 --- a/drivers/gpu/drm/xe/xe_pat.c +++ b/drivers/gpu/drm/xe/xe_pat.c @@ -531,6 +531,14 @@ static int xe2_dump(struct xe_gt *gt, struct drm_printer *p) drm_printf(p, "Page Table Access:\n"); xe->pat.ops->entry_dump(p, "PTA_MODE", pat, false); + if (xe_gt_is_media_type(gt)) + pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_ATS)); + else + pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_ATS)); + + drm_printf(p, "PCIe ATS/PASID:\n"); + xe->pat.ops->entry_dump(p, "PAT_ATS ", pat, false); + return 0; } @@ -551,6 +559,7 @@ static const struct xe_pat_ops xe3p_xpc_pat_ops = { void xe_pat_init_early(struct xe_device *xe) { xe->pat.idx[XE_CACHE_WB_COMPRESSION] = XE_PAT_INVALID_IDX; + xe->pat.idx[XE_CACHE_NONE_COMPRESSION] = XE_PAT_INVALID_IDX; if (GRAPHICS_VERx100(xe) == 3511) { xe->pat.ops = &xe3p_xpc_pat_ops; xe->pat.table = xe3p_xpc_pat_table; diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h index a1e287c08f57..7060f66e1d63 100644 --- a/drivers/gpu/drm/xe/xe_pat.h +++ b/drivers/gpu/drm/xe/xe_pat.h @@ -82,4 +82,12 @@ bool xe_pat_index_get_comp_en(struct xe_device *xe, u16 pat_index); */ u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index); +#define xe_cache_pat_idx(xe, cache_mode) ({ \ + const struct xe_device *__xedev = (xe); \ + enum xe_cache_level __mode = (cache_mode); \ + xe_assert(__xedev, __mode < __XE_CACHE_LEVEL_COUNT); \ + xe_assert(__xedev, __xedev->pat.idx[__mode] != XE_PAT_INVALID_IDX); \ + __xedev->pat.idx[__mode]; \ +}) + #endif diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 01673d2b2464..41435f84aeb2 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -118,6 +118,7 @@ static const struct xe_graphics_desc graphics_xe2 = { static const struct xe_graphics_desc graphics_xe3p_lpg = { XE2_GFX_FEATURES, + .has_indirect_ring_state = 1, .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | BIT(XE_ENGINE_CLASS_COMPUTE), .num_geometry_xecore_fuse_regs = 3, .num_compute_xecore_fuse_regs = 3, @@ -465,6 +466,7 @@ static const struct xe_device_desc cri_desc = { .has_soc_remapper_sysctrl = true, .has_soc_remapper_telem = true, .has_sriov = true, + .has_sysctrl = true, .max_gt_per_tile = 2, MULTI_LRC_MASK, .require_force_probe = true, @@ -763,8 +765,8 @@ static int xe_info_init_early(struct xe_device *xe, xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem; xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) && desc->has_sriov; + xe->info.has_sysctrl = desc->has_sysctrl; xe->info.skip_guc_pc = desc->skip_guc_pc; - xe->info.skip_mtcfg = desc->skip_mtcfg; xe->info.skip_pcode = desc->skip_pcode; xe->info.needs_scratch = desc->needs_scratch; xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq; @@ -806,9 +808,6 @@ static void xe_info_probe_tile_count(struct xe_device *xe) if (xe->info.tile_count == 1) return; - if (xe->info.skip_mtcfg) - return; - mmio = xe_root_tile_mmio(xe); /* @@ -959,6 +958,12 @@ static int xe_info_init(struct xe_device *xe, xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp; xe->info.has_mem_copy_instr = GRAPHICS_VER(xe) >= 20; + if (IS_SRIOV_VF(xe)) { + xe->info.has_sysctrl = 0; + xe->info.has_soc_remapper_sysctrl = 0; + xe->info.has_soc_remapper_telem = 0; + } + xe_info_probe_tile_count(xe); for_each_remote_tile(tile, xe, id) { diff --git a/drivers/gpu/drm/xe/xe_pci_sriov.c b/drivers/gpu/drm/xe/xe_pci_sriov.c index 3fd22034f03e..35e6b53e18ce 100644 --- a/drivers/gpu/drm/xe/xe_pci_sriov.c +++ b/drivers/gpu/drm/xe/xe_pci_sriov.c @@ -191,6 +191,8 @@ static int pf_disable_vfs(struct xe_device *xe) pci_disable_sriov(pdev); + xe_sriov_pf_reprovision_default(xe); + pf_reset_vfs(xe, num_vfs); xe_sriov_pf_unprovision_vfs(xe, num_vfs); diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h index 8eee4fb1c57c..5b85e2c24b7b 100644 --- a/drivers/gpu/drm/xe/xe_pci_types.h +++ b/drivers/gpu/drm/xe/xe_pci_types.h @@ -57,9 +57,9 @@ struct xe_device_desc { u8 has_soc_remapper_sysctrl:1; u8 has_soc_remapper_telem:1; u8 has_sriov:1; + u8 has_sysctrl:1; u8 needs_scratch:1; u8 skip_guc_pc:1; - u8 skip_mtcfg:1; u8 skip_pcode:1; u8 needs_shared_vf_gt_wq:1; }; diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h index 85cc7478b787..94575c476e3d 100644 --- a/drivers/gpu/drm/xe/xe_pcode_api.h +++ b/drivers/gpu/drm/xe/xe_pcode_api.h @@ -3,6 +3,9 @@ * Copyright © 2022 Intel Corporation */ +#ifndef _XE_PCODE_API_H_ +#define _XE_PCODE_API_H_ + /* Internal to xe_pcode */ #include "regs/xe_reg_defs.h" @@ -47,8 +50,9 @@ #define WRITE_PSYSGPU_POWER_LIMIT 0x7 #define READ_PACKAGE_POWER_LIMIT 0x8 #define WRITE_PACKAGE_POWER_LIMIT 0x9 -#define READ_PL_FROM_FW 0x1 #define READ_PL_FROM_PCODE 0x0 +#define READ_PL_FROM_FW 0x1 +#define READ_PL_ACCEPTED 0x2 #define PCODE_THERMAL_INFO 0x25 #define READ_THERMAL_LIMITS 0x0 @@ -101,3 +105,5 @@ #define BMG_PCIE_CAP XE_REG(0x138340) #define LINK_DOWNGRADE REG_GENMASK(1, 0) #define DOWNGRADE_CAPABLE 2 + +#endif diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c index 01185f10a883..d4672eb07476 100644 --- a/drivers/gpu/drm/xe/xe_pm.c +++ b/drivers/gpu/drm/xe/xe_pm.c @@ -26,6 +26,7 @@ #include "xe_pcode.h" #include "xe_pxp.h" #include "xe_sriov_vf_ccs.h" +#include "xe_sysctrl.h" #include "xe_trace.h" #include "xe_vm.h" #include "xe_wa.h" @@ -259,6 +260,8 @@ int xe_pm_resume(struct xe_device *xe) xe_i2c_pm_resume(xe, true); + xe_sysctrl_pm_resume(xe); + xe_irq_resume(xe); for_each_gt(gt, xe, id) { @@ -670,6 +673,9 @@ int xe_pm_runtime_resume(struct xe_device *xe) xe_i2c_pm_resume(xe, xe->d3cold.allowed); + if (xe->d3cold.allowed) + xe_sysctrl_pm_resume(xe); + xe_irq_resume(xe); for_each_gt(gt, xe, id) { diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c index 8e5f4f0dea3f..2669ff5ee747 100644 --- a/drivers/gpu/drm/xe/xe_pt.c +++ b/drivers/gpu/drm/xe/xe_pt.c @@ -14,6 +14,7 @@ #include "xe_gt_stats.h" #include "xe_migrate.h" #include "xe_page_reclaim.h" +#include "xe_pat.h" #include "xe_pt_types.h" #include "xe_pt_walk.h" #include "xe_res_cursor.h" @@ -62,7 +63,7 @@ static u64 __xe_pt_empty_pte(struct xe_tile *tile, struct xe_vm *vm, unsigned int level) { struct xe_device *xe = tile_to_xe(tile); - u16 pat_index = xe->pat.idx[XE_CACHE_WB]; + u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB); u8 id = tile->id; if (!xe_vm_has_scratch(vm)) diff --git a/drivers/gpu/drm/xe/xe_pt_types.h b/drivers/gpu/drm/xe/xe_pt_types.h index 84b51d3762a4..a7d1bb708b69 100644 --- a/drivers/gpu/drm/xe/xe_pt_types.h +++ b/drivers/gpu/drm/xe/xe_pt_types.h @@ -34,7 +34,7 @@ struct xe_pt { bool rebind; bool is_compact; #if IS_ENABLED(CONFIG_DRM_XE_DEBUG_VM) - /** addr: Virtual address start address of the PT. */ + /** @addr: Virtual address start address of the PT. */ u64 addr; #endif }; diff --git a/drivers/gpu/drm/xe/xe_pt_walk.h b/drivers/gpu/drm/xe/xe_pt_walk.h index 5c02c244f7de..e91995fa703b 100644 --- a/drivers/gpu/drm/xe/xe_pt_walk.h +++ b/drivers/gpu/drm/xe/xe_pt_walk.h @@ -2,8 +2,8 @@ /* * Copyright © 2022 Intel Corporation */ -#ifndef __XE_PT_WALK__ -#define __XE_PT_WALK__ +#ifndef _XE_PT_WALK_H_ +#define _XE_PT_WALK_H_ #include #include @@ -34,7 +34,7 @@ struct xe_pt_walk { * changed during the walk. */ const u64 *shifts; - /** @max_level: Highest populated level in @sizes */ + /** @max_level: Highest populated level in @shifts */ unsigned int max_level; /** * @shared_pt_mode: Whether to skip all entries that are private @@ -49,7 +49,7 @@ struct xe_pt_walk { /** * typedef xe_pt_entry_fn - gpu page-table-walk callback-function - * @parent: The parent page.table. + * @parent: The parent page table. * @offset: The offset (number of entries) into the page table. * @level: The level of @parent. * @addr: The virtual address. @@ -111,14 +111,14 @@ static inline bool xe_pt_covers(u64 addr, u64 end, unsigned int level, } /** - * xe_pt_num_entries: Number of page-table entries of a given range at this + * xe_pt_num_entries - Number of page-table entries of a given range at this * level * @addr: Start address. * @end: End address. * @level: Page table level. * @walk: Walk info. * - * Return: The number of page table entries at this level between @start and + * Return: The number of page table entries at this level between @addr and * @end. */ static inline pgoff_t @@ -132,7 +132,7 @@ xe_pt_num_entries(u64 addr, u64 end, unsigned int level, } /** - * xe_pt_offset: Offset of the page-table entry for a given address. + * xe_pt_offset - Offset of the page-table entry for a given address. * @addr: The address. * @level: Page table level. * @walk: Walk info. diff --git a/drivers/gpu/drm/xe/xe_pxp.c b/drivers/gpu/drm/xe/xe_pxp.c index 7244090b0782..968b7e70b3f9 100644 --- a/drivers/gpu/drm/xe/xe_pxp.c +++ b/drivers/gpu/drm/xe/xe_pxp.c @@ -13,10 +13,12 @@ #include "xe_device_types.h" #include "xe_exec_queue.h" #include "xe_force_wake.h" +#include "xe_guc_exec_queue_types.h" #include "xe_guc_submit.h" #include "xe_gsc_proxy.h" #include "xe_gt_types.h" #include "xe_huc.h" +#include "xe_hw_engine.h" #include "xe_mmio.h" #include "xe_pm.h" #include "xe_pxp_submit.h" @@ -740,6 +742,10 @@ static void pxp_invalidate_queues(struct xe_pxp *pxp) spin_unlock_irq(&pxp->queues.lock); list_for_each_entry_safe(q, tmp, &to_clean, pxp.link) { + drm_dbg(&pxp->xe->drm, + "Killing queue due to PXP termination: eclass=%s, guc_id=%d\n", + xe_hw_engine_class_to_str(q->class), q->guc->id); + xe_exec_queue_kill(q); /* diff --git a/drivers/gpu/drm/xe/xe_pxp.h b/drivers/gpu/drm/xe/xe_pxp.h index 71a23280b900..4fb6e0afffd2 100644 --- a/drivers/gpu/drm/xe/xe_pxp.h +++ b/drivers/gpu/drm/xe/xe_pxp.h @@ -3,8 +3,8 @@ * Copyright(c) 2024, Intel Corporation. All rights reserved. */ -#ifndef __XE_PXP_H__ -#define __XE_PXP_H__ +#ifndef _XE_PXP_H_ +#define _XE_PXP_H_ #include @@ -32,4 +32,4 @@ int xe_pxp_key_assign(struct xe_pxp *pxp, struct xe_bo *bo); int xe_pxp_bo_key_check(struct xe_pxp *pxp, struct xe_bo *bo); int xe_pxp_obj_key_check(struct drm_gem_object *obj); -#endif /* __XE_PXP_H__ */ +#endif /* _XE_PXP_H_ */ diff --git a/drivers/gpu/drm/xe/xe_pxp_debugfs.h b/drivers/gpu/drm/xe/xe_pxp_debugfs.h index 988466aad50b..2997de0c90b2 100644 --- a/drivers/gpu/drm/xe/xe_pxp_debugfs.h +++ b/drivers/gpu/drm/xe/xe_pxp_debugfs.h @@ -3,11 +3,11 @@ * Copyright © 2024 Intel Corporation */ -#ifndef __XE_PXP_DEBUGFS_H__ -#define __XE_PXP_DEBUGFS_H__ +#ifndef _XE_PXP_DEBUGFS_H_ +#define _XE_PXP_DEBUGFS_H_ struct xe_pxp; void xe_pxp_debugfs_register(struct xe_pxp *pxp); -#endif /* __XE_PXP_DEBUGFS_H__ */ +#endif /* _XE_PXP_DEBUGFS_H_ */ diff --git a/drivers/gpu/drm/xe/xe_pxp_submit.h b/drivers/gpu/drm/xe/xe_pxp_submit.h index c9efda02f4b0..dbbbe6b92bb2 100644 --- a/drivers/gpu/drm/xe/xe_pxp_submit.h +++ b/drivers/gpu/drm/xe/xe_pxp_submit.h @@ -3,8 +3,8 @@ * Copyright(c) 2024, Intel Corporation. All rights reserved. */ -#ifndef __XE_PXP_SUBMIT_H__ -#define __XE_PXP_SUBMIT_H__ +#ifndef _XE_PXP_SUBMIT_H_ +#define _XE_PXP_SUBMIT_H_ #include @@ -19,4 +19,4 @@ int xe_pxp_submit_session_termination(struct xe_pxp *pxp, u32 id); int xe_pxp_submit_session_invalidation(struct xe_pxp_gsc_client_resources *gsc_res, u32 id); -#endif /* __XE_PXP_SUBMIT_H__ */ +#endif /* _XE_PXP_SUBMIT_H_ */ diff --git a/drivers/gpu/drm/xe/xe_pxp_types.h b/drivers/gpu/drm/xe/xe_pxp_types.h index 53e9d48d10fb..ec86306e16f4 100644 --- a/drivers/gpu/drm/xe/xe_pxp_types.h +++ b/drivers/gpu/drm/xe/xe_pxp_types.h @@ -3,8 +3,8 @@ * Copyright(c) 2024, Intel Corporation. All rights reserved. */ -#ifndef __XE_PXP_TYPES_H__ -#define __XE_PXP_TYPES_H__ +#ifndef _XE_PXP_TYPES_H_ +#define _XE_PXP_TYPES_H_ #include #include @@ -132,4 +132,4 @@ struct xe_pxp { u32 last_suspend_key_instance; }; -#endif /* __XE_PXP_TYPES_H__ */ +#endif /* _XE_PXP_TYPES_H_ */ diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c index d84d6a422c45..8c7d54498f38 100644 --- a/drivers/gpu/drm/xe/xe_query.c +++ b/drivers/gpu/drm/xe/xe_query.c @@ -231,6 +231,9 @@ static size_t calc_mem_regions_size(struct xe_device *xe) u32 num_managers = 1; int i; + if (xe_device_is_admin_only(xe)) + return sizeof(struct drm_xe_query_mem_regions); + for (i = XE_PL_VRAM0; i <= XE_PL_VRAM1; ++i) if (ttm_manager_type(&xe->ttm, i)) num_managers++; @@ -259,6 +262,9 @@ static int query_mem_regions(struct xe_device *xe, if (XE_IOCTL_DBG(xe, !mem_regions)) return -ENOMEM; + if (xe_device_is_admin_only(xe)) + goto user_copy; + man = ttm_manager_type(&xe->ttm, XE_PL_TT); mem_regions->mem_regions[0].mem_class = DRM_XE_MEM_REGION_CLASS_SYSMEM; /* @@ -297,6 +303,7 @@ static int query_mem_regions(struct xe_device *xe, } } +user_copy: if (!copy_to_user(query_ptr, mem_regions, size)) ret = 0; else diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c new file mode 100644 index 000000000000..4cb16b419b0c --- /dev/null +++ b/drivers/gpu/drm/xe/xe_ras.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2026 Intel Corporation + */ + +#include "xe_device.h" +#include "xe_printk.h" +#include "xe_ras.h" +#include "xe_ras_types.h" +#include "xe_sysctrl.h" +#include "xe_sysctrl_event_types.h" + +/* Severity of detected errors */ +enum xe_ras_severity { + XE_RAS_SEV_NOT_SUPPORTED = 0, + XE_RAS_SEV_CORRECTABLE, + XE_RAS_SEV_UNCORRECTABLE, + XE_RAS_SEV_INFORMATIONAL, + XE_RAS_SEV_MAX +}; + +/* Major IP blocks/components where errors can originate */ +enum xe_ras_component { + XE_RAS_COMP_NOT_SUPPORTED = 0, + XE_RAS_COMP_DEVICE_MEMORY, + XE_RAS_COMP_CORE_COMPUTE, + XE_RAS_COMP_RESERVED, + XE_RAS_COMP_PCIE, + XE_RAS_COMP_FABRIC, + XE_RAS_COMP_SOC_INTERNAL, + XE_RAS_COMP_MAX +}; + +static const char *const xe_ras_severities[] = { + [XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported", + [XE_RAS_SEV_CORRECTABLE] = "Correctable Error", + [XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable Error", + [XE_RAS_SEV_INFORMATIONAL] = "Informational Error", +}; +static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX); + +static const char *const xe_ras_components[] = { + [XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported", + [XE_RAS_COMP_DEVICE_MEMORY] = "Device Memory", + [XE_RAS_COMP_CORE_COMPUTE] = "Core Compute", + [XE_RAS_COMP_RESERVED] = "Reserved", + [XE_RAS_COMP_PCIE] = "PCIe", + [XE_RAS_COMP_FABRIC] = "Fabric", + [XE_RAS_COMP_SOC_INTERNAL] = "SoC Internal", +}; +static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX); + +static inline const char *sev_to_str(u8 severity) +{ + if (severity >= XE_RAS_SEV_MAX) + severity = XE_RAS_SEV_NOT_SUPPORTED; + + return xe_ras_severities[severity]; +} + +static inline const char *comp_to_str(u8 component) +{ + if (component >= XE_RAS_COMP_MAX) + component = XE_RAS_COMP_NOT_SUPPORTED; + + return xe_ras_components[component]; +} + +void xe_ras_counter_threshold_crossed(struct xe_device *xe, + struct xe_sysctrl_event_response *response) +{ + struct xe_ras_threshold_crossed *pending = (void *)&response->data; + struct xe_ras_error_class *errors = pending->counters; + u32 id, ncounters = pending->ncounters; + + BUILD_BUG_ON(sizeof(response->data) < sizeof(*pending)); + xe_device_assert_mem_access(xe); + + if (!ncounters || ncounters > XE_RAS_NUM_COUNTERS) + xe_err(xe, "sysctrl: unexpected counter threshold crossed %u\n", ncounters); + else + xe_warn(xe, "[RAS]: counter threshold crossed, %u new errors\n", ncounters); + + for (id = 0; id < ncounters && id < XE_RAS_NUM_COUNTERS; id++) { + u8 severity, component; + + severity = errors[id].common.severity; + component = errors[id].common.component; + + xe_warn(xe, "[RAS]: %s %s detected\n", + comp_to_str(component), sev_to_str(severity)); + } +} diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h new file mode 100644 index 000000000000..ea90593b62dc --- /dev/null +++ b/drivers/gpu/drm/xe/xe_ras.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ + +#ifndef _XE_RAS_H_ +#define _XE_RAS_H_ + +struct xe_device; +struct xe_sysctrl_event_response; + +void xe_ras_counter_threshold_crossed(struct xe_device *xe, + struct xe_sysctrl_event_response *response); + +#endif diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h new file mode 100644 index 000000000000..4e63c67f806a --- /dev/null +++ b/drivers/gpu/drm/xe/xe_ras_types.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ + +#ifndef _XE_RAS_TYPES_H_ +#define _XE_RAS_TYPES_H_ + +#include + +#define XE_RAS_NUM_COUNTERS 16 + +/** + * struct xe_ras_error_common - Error fields that are common across all products + */ +struct xe_ras_error_common { + /** @severity: Error severity */ + u8 severity; + /** @component: IP block where error originated */ + u8 component; +} __packed; + +/** + * struct xe_ras_error_unit - Error unit information + */ +struct xe_ras_error_unit { + /** @tile: Tile identifier */ + u8 tile; + /** @instance: Instance identifier specific to IP */ + u32 instance; +} __packed; + +/** + * struct xe_ras_error_cause - Error cause information + */ +struct xe_ras_error_cause { + /** @cause: Cause/checker */ + u32 cause; + /** @reserved: For future use */ + u8 reserved; +} __packed; + +/** + * struct xe_ras_error_product - Error fields that are specific to the product + */ +struct xe_ras_error_product { + /** @unit: Unit within IP block */ + struct xe_ras_error_unit unit; + /** @cause: Cause/checker */ + struct xe_ras_error_cause cause; +} __packed; + +/** + * struct xe_ras_error_class - Combines common and product-specific parts + */ +struct xe_ras_error_class { + /** @common: Common error type and component */ + struct xe_ras_error_common common; + /** @product: Product-specific unit and cause */ + struct xe_ras_error_product product; +} __packed; + +/** + * struct xe_ras_threshold_crossed - Data for threshold crossed event + */ +struct xe_ras_threshold_crossed { + /** @ncounters: Number of error counters that crossed thresholds */ + u32 ncounters; + /** @counters: Array of error counters that crossed threshold */ + struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS]; +} __packed; + +#endif diff --git a/drivers/gpu/drm/xe/xe_reg_sr.h b/drivers/gpu/drm/xe/xe_reg_sr.h index 1ec6e8ecf278..d26cf4713383 100644 --- a/drivers/gpu/drm/xe/xe_reg_sr.h +++ b/drivers/gpu/drm/xe/xe_reg_sr.h @@ -3,8 +3,8 @@ * Copyright © 2022 Intel Corporation */ -#ifndef _XE_REG_SR_ -#define _XE_REG_SR_ +#ifndef _XE_REG_SR_H_ +#define _XE_REG_SR_H_ /* * Reg save/restore bookkeeping diff --git a/drivers/gpu/drm/xe/xe_reg_sr_types.h b/drivers/gpu/drm/xe/xe_reg_sr_types.h index ebe11f237fa2..0a6695db2967 100644 --- a/drivers/gpu/drm/xe/xe_reg_sr_types.h +++ b/drivers/gpu/drm/xe/xe_reg_sr_types.h @@ -3,8 +3,8 @@ * Copyright © 2022 Intel Corporation */ -#ifndef _XE_REG_SR_TYPES_ -#define _XE_REG_SR_TYPES_ +#ifndef _XE_REG_SR_TYPES_H_ +#define _XE_REG_SR_TYPES_H_ #include #include diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c index 80577e4b7437..8cc313182968 100644 --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c @@ -226,7 +226,7 @@ void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent, } range_start = reg & REG_GENMASK(25, range_bit); - range_end = range_start | REG_GENMASK(range_bit, 0); + range_end = range_start | REG_GENMASK(range_bit - 1, 0); switch (val & RING_FORCE_TO_NONPRIV_ACCESS_MASK) { case RING_FORCE_TO_NONPRIV_ACCESS_RW: diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.h b/drivers/gpu/drm/xe/xe_reg_whitelist.h index 69b121d377da..3b64b42fe96e 100644 --- a/drivers/gpu/drm/xe/xe_reg_whitelist.h +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.h @@ -3,8 +3,8 @@ * Copyright © 2023 Intel Corporation */ -#ifndef _XE_REG_WHITELIST_ -#define _XE_REG_WHITELIST_ +#ifndef _XE_REG_WHITELIST_H_ +#define _XE_REG_WHITELIST_H_ #include diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c index 991f218f1cc3..1a4dcbbbc176 100644 --- a/drivers/gpu/drm/xe/xe_rtp.c +++ b/drivers/gpu/drm/xe/xe_rtp.c @@ -10,6 +10,7 @@ #include #include "xe_configfs.h" +#include "xe_device.h" #include "xe_gt.h" #include "xe_gt_topology.h" #include "xe_reg_sr.h" @@ -352,6 +353,13 @@ void xe_rtp_process(struct xe_rtp_process_ctx *ctx, } EXPORT_SYMBOL_IF_KUNIT(xe_rtp_process); +bool xe_rtp_match_always(const struct xe_device *xe, + const struct xe_gt *gt, + const struct xe_hw_engine *hwe) +{ + return true; +} + bool xe_rtp_match_even_instance(const struct xe_device *xe, const struct xe_gt *gt, const struct xe_hw_engine *hwe) @@ -397,3 +405,10 @@ bool xe_rtp_match_has_flat_ccs(const struct xe_device *xe, { return xe->info.has_flat_ccs; } + +bool xe_rtp_match_has_msix(const struct xe_device *xe, + const struct xe_gt *gt, + const struct xe_hw_engine *hwe) +{ + return xe_device_has_msix(xe); +} diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h index 7d6daa7eb1e4..562082b18d7b 100644 --- a/drivers/gpu/drm/xe/xe_rtp.h +++ b/drivers/gpu/drm/xe/xe_rtp.h @@ -3,8 +3,8 @@ * Copyright © 2022 Intel Corporation */ -#ifndef _XE_RTP_ -#define _XE_RTP_ +#ifndef _XE_RTP_H_ +#define _XE_RTP_H_ #include #include @@ -459,6 +459,18 @@ void xe_rtp_process(struct xe_rtp_process_ctx *ctx, /* Match functions to be used with XE_RTP_MATCH_FUNC */ +/** + * xe_rtp_match_always - Match RTP entry unconditionally + * @xe: Device structure + * @gt: GT structure + * @hwe: Engine instance + * + * Returns: true, regardless of inputs + */ +bool xe_rtp_match_always(const struct xe_device *xe, + const struct xe_gt *gt, + const struct xe_hw_engine *hwe); + /** * xe_rtp_match_even_instance - Match if engine instance is even * @xe: Device structure @@ -524,4 +536,16 @@ bool xe_rtp_match_has_flat_ccs(const struct xe_device *xe, const struct xe_gt *gt, const struct xe_hw_engine *hwe); +/** + * xe_rtp_match_has_msix - Match when platform has MSI-X + * @xe: Device structure + * @gt: GT structure + * @hwe: Engine instance + * + * Returns: true if platform has MSI-X interrupt support + */ +bool xe_rtp_match_has_msix(const struct xe_device *xe, + const struct xe_gt *gt, + const struct xe_hw_engine *hwe); + #endif diff --git a/drivers/gpu/drm/xe/xe_rtp_helpers.h b/drivers/gpu/drm/xe/xe_rtp_helpers.h index a33b0ae98bbc..ffa8b2f8828d 100644 --- a/drivers/gpu/drm/xe/xe_rtp_helpers.h +++ b/drivers/gpu/drm/xe/xe_rtp_helpers.h @@ -3,8 +3,8 @@ * Copyright © 2023 Intel Corporation */ -#ifndef _XE_RTP_HELPERS_ -#define _XE_RTP_HELPERS_ +#ifndef _XE_RTP_HELPERS_H_ +#define _XE_RTP_HELPERS_H_ #ifndef _XE_RTP_INCLUDE_PRIVATE_HELPERS #error "This header is supposed to be included by xe_rtp.h only" @@ -66,6 +66,8 @@ #define XE_RTP_PASTE_10(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_9(prefix_, sep_, _XE_TUPLE_TAIL args_) #define XE_RTP_PASTE_11(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_10(prefix_, sep_, _XE_TUPLE_TAIL args_) #define XE_RTP_PASTE_12(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_11(prefix_, sep_, _XE_TUPLE_TAIL args_) +#define XE_RTP_PASTE_13(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_12(prefix_, sep_, _XE_TUPLE_TAIL args_) +#define XE_RTP_PASTE_14(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_13(prefix_, sep_, _XE_TUPLE_TAIL args_) /* * XE_RTP_DROP_CAST - Drop cast to convert a compound statement to a initializer diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h index 166251615be1..0265c16d2762 100644 --- a/drivers/gpu/drm/xe/xe_rtp_types.h +++ b/drivers/gpu/drm/xe/xe_rtp_types.h @@ -3,8 +3,8 @@ * Copyright © 2022 Intel Corporation */ -#ifndef _XE_RTP_TYPES_ -#define _XE_RTP_TYPES_ +#ifndef _XE_RTP_TYPES_H_ +#define _XE_RTP_TYPES_H_ #include diff --git a/drivers/gpu/drm/xe/xe_sriov_pf.c b/drivers/gpu/drm/xe/xe_sriov_pf.c index 47a6e0fd66e0..33bd754d138f 100644 --- a/drivers/gpu/drm/xe/xe_sriov_pf.c +++ b/drivers/gpu/drm/xe/xe_sriov_pf.c @@ -20,11 +20,6 @@ #include "xe_sriov_pf_sysfs.h" #include "xe_sriov_printk.h" -static bool wanted_admin_only(struct xe_device *xe) -{ - return xe_configfs_admin_only_pf(to_pci_dev(xe->drm.dev)); -} - static unsigned int wanted_max_vfs(struct xe_device *xe) { return xe_configfs_get_max_vfs(to_pci_dev(xe->drm.dev)); @@ -79,7 +74,6 @@ bool xe_sriov_pf_readiness(struct xe_device *xe) pf_reduce_totalvfs(xe, newlimit); - xe->sriov.pf.admin_only = wanted_admin_only(xe); xe->sriov.pf.device_total_vfs = totalvfs; xe->sriov.pf.driver_max_vfs = newlimit; diff --git a/drivers/gpu/drm/xe/xe_sriov_pf_helpers.h b/drivers/gpu/drm/xe/xe_sriov_pf_helpers.h index 0fcc6cec4afc..19f6f8331c8d 100644 --- a/drivers/gpu/drm/xe/xe_sriov_pf_helpers.h +++ b/drivers/gpu/drm/xe/xe_sriov_pf_helpers.h @@ -7,6 +7,7 @@ #define _XE_SRIOV_PF_HELPERS_H_ #include "xe_assert.h" +#include "xe_device.h" #include "xe_device_types.h" #include "xe_sriov.h" #include "xe_sriov_types.h" @@ -57,7 +58,7 @@ static inline unsigned int xe_sriov_pf_num_vfs(const struct xe_device *xe) static inline bool xe_sriov_pf_admin_only(const struct xe_device *xe) { xe_assert(xe, IS_SRIOV_PF(xe)); - return xe->sriov.pf.admin_only; + return xe_device_is_admin_only(xe); } static inline struct mutex *xe_sriov_pf_master_mutex(struct xe_device *xe) diff --git a/drivers/gpu/drm/xe/xe_sriov_pf_provision.c b/drivers/gpu/drm/xe/xe_sriov_pf_provision.c index abe3677d33ed..0ec7ea83f12a 100644 --- a/drivers/gpu/drm/xe/xe_sriov_pf_provision.c +++ b/drivers/gpu/drm/xe/xe_sriov_pf_provision.c @@ -41,6 +41,8 @@ static int pf_provision_vfs(struct xe_device *xe, unsigned int num_vfs) int err; for_each_gt(gt, xe, id) { + err = xe_gt_sriov_pf_config_set_fair_sched(gt, num_vfs); + result = result ?: err; err = xe_gt_sriov_pf_config_set_fair(gt, VFID(1), num_vfs); result = result ?: err; } @@ -103,6 +105,45 @@ int xe_sriov_pf_unprovision_vfs(struct xe_device *xe, unsigned int num_vfs) return 0; } +static int pf_reprovision_default(struct xe_device *xe) +{ + struct xe_gt *gt; + unsigned int id; + int result = 0; + int err; + + guard(mutex)(xe_sriov_pf_master_mutex(xe)); + + for_each_gt(gt, xe, id) { + err = xe_gt_sriov_pf_policy_set_sched_if_idle_locked(gt, false); + result = result ?: err; + err = xe_gt_sriov_pf_config_set_exec_quantum_locked(gt, PFID, 0); + result = result ?: err; + err = xe_gt_sriov_pf_config_set_preempt_timeout_locked(gt, PFID, 0); + result = result ?: err; + } + + return result; +} + +/** + * xe_sriov_pf_reprovision_default() - Reprovision default PF in auto-mode. + * @xe: the PF &xe_device + * + * This function can only be called on PF. + * + * Return: 0 on success or a negative error code on failure. + */ +int xe_sriov_pf_reprovision_default(struct xe_device *xe) +{ + xe_assert(xe, IS_SRIOV_PF(xe)); + + if (!pf_auto_provisioning_mode(xe)) + return 0; + + return pf_reprovision_default(xe); +} + /** * xe_sriov_pf_provision_set_mode() - Change VFs provision mode. * @xe: the PF &xe_device diff --git a/drivers/gpu/drm/xe/xe_sriov_pf_provision.h b/drivers/gpu/drm/xe/xe_sriov_pf_provision.h index f26f49539697..b15e4d7ad940 100644 --- a/drivers/gpu/drm/xe/xe_sriov_pf_provision.h +++ b/drivers/gpu/drm/xe/xe_sriov_pf_provision.h @@ -30,6 +30,7 @@ int xe_sriov_pf_provision_query_vf_vram(struct xe_device *xe, unsigned int vfid, int xe_sriov_pf_provision_vfs(struct xe_device *xe, unsigned int num_vfs); int xe_sriov_pf_unprovision_vfs(struct xe_device *xe, unsigned int num_vfs); +int xe_sriov_pf_reprovision_default(struct xe_device *xe); int xe_sriov_pf_provision_set_mode(struct xe_device *xe, enum xe_sriov_provisioning_mode mode); diff --git a/drivers/gpu/drm/xe/xe_sriov_pf_types.h b/drivers/gpu/drm/xe/xe_sriov_pf_types.h index 080cf10512f4..b0253e1ae5da 100644 --- a/drivers/gpu/drm/xe/xe_sriov_pf_types.h +++ b/drivers/gpu/drm/xe/xe_sriov_pf_types.h @@ -36,9 +36,6 @@ struct xe_sriov_metadata { * @XE_SRIOV_MODE_PF mode. */ struct xe_device_pf { - /** @admin_only: PF functionality focused on VFs management only. */ - bool admin_only; - /** @device_total_vfs: Maximum number of VFs supported by the device. */ u16 device_total_vfs; diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c index db023fb66a27..09b99fb2608b 100644 --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c @@ -14,9 +14,9 @@ #include "xe_guc.h" #include "xe_guc_submit.h" #include "xe_lrc.h" +#include "xe_mem_pool.h" #include "xe_migrate.h" #include "xe_pm.h" -#include "xe_sa.h" #include "xe_sriov_printk.h" #include "xe_sriov_vf.h" #include "xe_sriov_vf_ccs.h" @@ -141,43 +141,47 @@ static u64 get_ccs_bb_pool_size(struct xe_device *xe) static int alloc_bb_pool(struct xe_tile *tile, struct xe_sriov_vf_ccs_ctx *ctx) { + struct xe_mem_pool *pool; struct xe_device *xe = tile_to_xe(tile); - struct xe_sa_manager *sa_manager; + u32 *pool_cpu_addr, *last_dw_addr; u64 bb_pool_size; - int offset, err; + int err; bb_pool_size = get_ccs_bb_pool_size(xe); xe_sriov_info(xe, "Allocating %s CCS BB pool size = %lldMB\n", ctx->ctx_id ? "Restore" : "Save", bb_pool_size / SZ_1M); - sa_manager = __xe_sa_bo_manager_init(tile, bb_pool_size, SZ_4K, SZ_16, - XE_SA_BO_MANAGER_FLAG_SHADOW); - - if (IS_ERR(sa_manager)) { - xe_sriov_err(xe, "Suballocator init failed with error: %pe\n", - sa_manager); - err = PTR_ERR(sa_manager); + pool = xe_mem_pool_init(tile, bb_pool_size, sizeof(u32), + XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY); + if (IS_ERR(pool)) { + xe_sriov_err(xe, "xe_mem_pool_init failed with error: %pe\n", + pool); + err = PTR_ERR(pool); return err; } - offset = 0; - xe_map_memset(xe, &sa_manager->bo->vmap, offset, MI_NOOP, - bb_pool_size); - xe_map_memset(xe, &sa_manager->shadow->vmap, offset, MI_NOOP, - bb_pool_size); + pool_cpu_addr = xe_mem_pool_cpu_addr(pool); + memset(pool_cpu_addr, 0, bb_pool_size); - offset = bb_pool_size - sizeof(u32); - xe_map_wr(xe, &sa_manager->bo->vmap, offset, u32, MI_BATCH_BUFFER_END); - xe_map_wr(xe, &sa_manager->shadow->vmap, offset, u32, MI_BATCH_BUFFER_END); + last_dw_addr = pool_cpu_addr + (bb_pool_size / sizeof(u32)) - 1; + *last_dw_addr = MI_BATCH_BUFFER_END; - ctx->mem.ccs_bb_pool = sa_manager; + /** + * Sync the main copy and shadow copy so that the shadow copy is + * replica of main copy. We sync only BBs after init part. So, we + * need to make sure the main pool and shadow copy are in sync after + * this point. This is needed as GuC may read the BB commands from + * shadow copy. + */ + xe_mem_pool_sync(pool); + ctx->mem.ccs_bb_pool = pool; return 0; } static void ccs_rw_update_ring(struct xe_sriov_vf_ccs_ctx *ctx) { - u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool); + u64 addr = xe_mem_pool_gpu_addr(ctx->mem.ccs_bb_pool); struct xe_lrc *lrc = xe_exec_queue_lrc(ctx->mig_q); u32 dw[10], i = 0; @@ -388,7 +392,7 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) #define XE_SRIOV_VF_CCS_RW_BB_ADDR_OFFSET (2 * sizeof(u32)) void xe_sriov_vf_ccs_rw_update_bb_addr(struct xe_sriov_vf_ccs_ctx *ctx) { - u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool); + u64 addr = xe_mem_pool_gpu_addr(ctx->mem.ccs_bb_pool); struct xe_lrc *lrc = xe_exec_queue_lrc(ctx->mig_q); struct xe_device *xe = gt_to_xe(ctx->mig_q->gt); @@ -412,8 +416,8 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo) struct xe_device *xe = xe_bo_device(bo); enum xe_sriov_vf_ccs_rw_ctxs ctx_id; struct xe_sriov_vf_ccs_ctx *ctx; + struct xe_mem_pool_node *bb; struct xe_tile *tile; - struct xe_bb *bb; int err = 0; xe_assert(xe, IS_VF_CCS_READY(xe)); @@ -445,7 +449,7 @@ int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo) { struct xe_device *xe = xe_bo_device(bo); enum xe_sriov_vf_ccs_rw_ctxs ctx_id; - struct xe_bb *bb; + struct xe_mem_pool_node *bb; xe_assert(xe, IS_VF_CCS_READY(xe)); @@ -471,8 +475,8 @@ int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo) */ void xe_sriov_vf_ccs_print(struct xe_device *xe, struct drm_printer *p) { - struct xe_sa_manager *bb_pool; enum xe_sriov_vf_ccs_rw_ctxs ctx_id; + struct xe_mem_pool *bb_pool; if (!IS_VF_CCS_READY(xe)) return; @@ -485,7 +489,7 @@ void xe_sriov_vf_ccs_print(struct xe_device *xe, struct drm_printer *p) drm_printf(p, "ccs %s bb suballoc info\n", ctx_id ? "write" : "read"); drm_printf(p, "-------------------------\n"); - drm_suballoc_dump_debug_info(&bb_pool->base, p, xe_sa_manager_gpu_addr(bb_pool)); + xe_mem_pool_dump(bb_pool, p); drm_puts(p, "\n"); } } diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h index 22c499943d2a..6fc8f97ef3f4 100644 --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h @@ -17,9 +17,6 @@ enum xe_sriov_vf_ccs_rw_ctxs { XE_SRIOV_VF_CCS_CTX_COUNT }; -struct xe_migrate; -struct xe_sa_manager; - /** * struct xe_sriov_vf_ccs_ctx - VF CCS migration context data. */ @@ -33,7 +30,7 @@ struct xe_sriov_vf_ccs_ctx { /** @mem: memory data */ struct { /** @mem.ccs_bb_pool: Pool from which batch buffers are allocated. */ - struct xe_sa_manager *ccs_bb_pool; + struct xe_mem_pool *ccs_bb_pool; } mem; }; diff --git a/drivers/gpu/drm/xe/xe_step.c b/drivers/gpu/drm/xe/xe_step.c index d0f888c31831..fb9c31613ca7 100644 --- a/drivers/gpu/drm/xe/xe_step.c +++ b/drivers/gpu/drm/xe/xe_step.c @@ -278,7 +278,7 @@ void xe_step_gmdid_get(struct xe_device *xe, case STEP_##name: \ return #name; -const char *xe_step_name(enum xe_step step) +const char *xe_step_name(enum intel_step step) { switch (step) { STEP_NAME_LIST(STEP_NAME_CASE); diff --git a/drivers/gpu/drm/xe/xe_step.h b/drivers/gpu/drm/xe/xe_step.h index 41f1c95c46e5..ea36b22cc297 100644 --- a/drivers/gpu/drm/xe/xe_step.h +++ b/drivers/gpu/drm/xe/xe_step.h @@ -18,8 +18,8 @@ void xe_step_pre_gmdid_get(struct xe_device *xe); void xe_step_gmdid_get(struct xe_device *xe, u32 graphics_gmdid_revid, u32 media_gmdid_revid); -static inline u32 xe_step_to_gmdid(enum xe_step step) { return step - STEP_A0; } +static inline u32 xe_step_to_gmdid(enum intel_step step) { return step - STEP_A0; } -const char *xe_step_name(enum xe_step step); +const char *xe_step_name(enum intel_step step); #endif diff --git a/drivers/gpu/drm/xe/xe_step_types.h b/drivers/gpu/drm/xe/xe_step_types.h index 43ca73850739..f60572b93523 100644 --- a/drivers/gpu/drm/xe/xe_step_types.h +++ b/drivers/gpu/drm/xe/xe_step_types.h @@ -8,6 +8,8 @@ #include +#include + struct xe_step_info { u8 platform; u8 graphics; @@ -15,63 +17,4 @@ struct xe_step_info { u8 basedie; }; -#define STEP_ENUM_VAL(name) STEP_##name, - -/* - * Always define four minor steppings 0-3 for each stepping to match GMD ID - * spacing of values. See xe_step_gmdid_get(). - */ -#define STEP_NAME_LIST(func) \ - func(A0) \ - func(A1) \ - func(A2) \ - func(A3) \ - func(B0) \ - func(B1) \ - func(B2) \ - func(B3) \ - func(C0) \ - func(C1) \ - func(C2) \ - func(C3) \ - func(D0) \ - func(D1) \ - func(D2) \ - func(D3) \ - func(E0) \ - func(E1) \ - func(E2) \ - func(E3) \ - func(F0) \ - func(F1) \ - func(F2) \ - func(F3) \ - func(G0) \ - func(G1) \ - func(G2) \ - func(G3) \ - func(H0) \ - func(H1) \ - func(H2) \ - func(H3) \ - func(I0) \ - func(I1) \ - func(I2) \ - func(I3) \ - func(J0) \ - func(J1) \ - func(J2) \ - func(J3) - -/* - * Symbolic steppings that do not match the hardware. These are valid both as gt - * and display steppings as symbolic names. - */ -enum xe_step { - STEP_NONE = 0, - STEP_NAME_LIST(STEP_ENUM_VAL) - STEP_FUTURE, - STEP_FOREVER, -}; - #endif diff --git a/drivers/gpu/drm/xe/xe_svm.c b/drivers/gpu/drm/xe/xe_svm.c index b54587b77b2f..e1651e70c8f0 100644 --- a/drivers/gpu/drm/xe/xe_svm.c +++ b/drivers/gpu/drm/xe/xe_svm.c @@ -786,12 +786,12 @@ static int xe_svm_populate_devmem_pfn(struct drm_pagemap_devmem *devmem_allocati struct xe_bo *bo = to_xe_bo(devmem_allocation); struct ttm_resource *res = bo->ttm.resource; struct list_head *blocks = &to_xe_ttm_vram_mgr_resource(res)->blocks; + struct xe_vram_region *vr = xe_map_resource_to_region(res); + struct gpu_buddy *buddy = vram_to_buddy(vr); struct gpu_buddy_block *block; int j = 0; list_for_each_entry(block, blocks, link) { - struct xe_vram_region *vr = block->private; - struct gpu_buddy *buddy = vram_to_buddy(vr); u64 block_pfn = block_offset_to_pfn(devmem_allocation->dpagemap, gpu_buddy_block_offset(block)); int i; @@ -1060,9 +1060,7 @@ static int xe_drm_pagemap_populate_mm(struct drm_pagemap *dpagemap, struct dma_fence *pre_migrate_fence = NULL; struct xe_device *xe = vr->xe; struct device *dev = xe->drm.dev; - struct gpu_buddy_block *block; struct xe_validation_ctx vctx; - struct list_head *blocks; struct drm_exec exec; struct xe_bo *bo; int err = 0, idx; @@ -1099,10 +1097,6 @@ static int xe_drm_pagemap_populate_mm(struct drm_pagemap *dpagemap, &dpagemap_devmem_ops, dpagemap, end - start, pre_migrate_fence); - blocks = &to_xe_ttm_vram_mgr_resource(bo->ttm.resource)->blocks; - list_for_each_entry(block, blocks, link) - block->private = vr; - xe_bo_get(bo); /* Ensure the device has a pm ref while there are device pages active. */ diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c new file mode 100644 index 000000000000..1db20be8158b --- /dev/null +++ b/drivers/gpu/drm/xe/xe_sysctrl.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2026 Intel Corporation + */ + +#include +#include + +#include + +#include "regs/xe_irq_regs.h" +#include "regs/xe_sysctrl_regs.h" +#include "xe_device.h" +#include "xe_mmio.h" +#include "xe_pm.h" +#include "xe_soc_remapper.h" +#include "xe_sysctrl.h" +#include "xe_sysctrl_mailbox.h" +#include "xe_sysctrl_types.h" + +/** + * DOC: System Controller (sysctrl) + * + * System Controller (sysctrl) is a firmware-managed entity on Intel dGPUs + * responsible for selected low-level platform management functions. + * Communication between driver and System Controller is performed + * via a mailbox interface, enabling command and response exchange. + * + * This module provides initialization and support code for interacting + * with System Controller through the mailbox interface. + */ +static void sysctrl_fini(void *arg) +{ + struct xe_device *xe = arg; + struct xe_sysctrl *sc = &xe->sc; + + disable_work_sync(&sc->work); + xe->soc_remapper.set_sysctrl_region(xe, 0); +} + +static void xe_sysctrl_work(struct work_struct *work) +{ + struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work); + struct xe_device *xe = sc_to_xe(sc); + + guard(xe_pm_runtime)(xe); + xe_sysctrl_event(sc); +} + +/** + * xe_sysctrl_init() - Initialize System Controller subsystem + * @xe: xe device instance + * + * Entry point for System Controller initialization, called from xe_device_probe. + * This function checks platform support and initializes the system controller. + * + * Return: 0 on success, error code on failure + */ +int xe_sysctrl_init(struct xe_device *xe) +{ + struct xe_tile *tile = xe_device_get_root_tile(xe); + struct xe_sysctrl *sc = &xe->sc; + int ret; + + if (!xe->info.has_soc_remapper_sysctrl) + return 0; + + if (!xe->info.has_sysctrl) + return 0; + + sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL); + if (!sc->mmio) + return -ENOMEM; + + xe_mmio_init(sc->mmio, tile, tile->mmio.regs, tile->mmio.regs_size); + sc->mmio->adj_offset = SYSCTRL_BASE; + sc->mmio->adj_limit = U32_MAX; + + ret = devm_mutex_init(xe->drm.dev, &sc->cmd_lock); + if (ret) + return ret; + + ret = devm_mutex_init(xe->drm.dev, &sc->event_lock); + if (ret) + return ret; + + xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX); + xe_sysctrl_mailbox_init(sc); + INIT_WORK(&sc->work, xe_sysctrl_work); + + return devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe); +} + +/** + * xe_sysctrl_irq_handler() - Handler for System Controller interrupts + * @xe: xe device instance + * @master_ctl: interrupt register + * + * Handle interrupts generated by System Controller. + */ +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl) +{ + struct xe_sysctrl *sc = &xe->sc; + + if (!xe->info.has_sysctrl || !sc->work.func) + return; + + if (master_ctl & SYSCTRL_IRQ) + schedule_work(&sc->work); +} + +/** + * xe_sysctrl_pm_resume() - System Controller resume handler + * @xe: xe device instance + * + * Invoked during system resume (S3/S4 to S0) and runtime resume from D3cold. + * Restores SoC remapper configuration and reinitializes mailbox interface. + */ +void xe_sysctrl_pm_resume(struct xe_device *xe) +{ + struct xe_sysctrl *sc = &xe->sc; + + if (!xe->info.has_soc_remapper_sysctrl) + return; + + if (!xe->info.has_sysctrl) + return; + + xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX); + + xe_sysctrl_mailbox_init(sc); +} diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h new file mode 100644 index 000000000000..090dffb6d55f --- /dev/null +++ b/drivers/gpu/drm/xe/xe_sysctrl.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ + +#ifndef _XE_SYSCTRL_H_ +#define _XE_SYSCTRL_H_ + +#include + +#include "xe_device_types.h" +#include "xe_sysctrl_types.h" + +static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc) +{ + return container_of(sc, struct xe_device, sc); +} + +void xe_sysctrl_event(struct xe_sysctrl *sc); +int xe_sysctrl_init(struct xe_device *xe); +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl); +void xe_sysctrl_pm_resume(struct xe_device *xe); + +#endif diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c new file mode 100644 index 000000000000..b4d17329af6c --- /dev/null +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2026 Intel Corporation + */ + +#include "xe_device.h" +#include "xe_irq.h" +#include "xe_printk.h" +#include "xe_ras.h" +#include "xe_sysctrl.h" +#include "xe_sysctrl_event_types.h" +#include "xe_sysctrl_mailbox.h" +#include "xe_sysctrl_mailbox_types.h" + +static void get_pending_event(struct xe_sysctrl *sc, struct xe_sysctrl_mailbox_command *command) +{ + struct xe_sysctrl_event_response *response = command->data_out; + struct xe_device *xe = sc_to_xe(sc); + u32 count = XE_SYSCTRL_EVENT_FLOOD; + size_t len; + int ret; + + do { + memset(response, 0, sizeof(*response)); + + ret = xe_sysctrl_send_command(sc, command, &len); + if (ret) { + xe_err(xe, "sysctrl: failed to get pending event %d\n", ret); + return; + } + + if (len != sizeof(*response)) { + xe_err(xe, "sysctrl: unexpected event response length %zu (expected %zu)\n", + len, sizeof(*response)); + return; + } + + if (response->event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) + xe_ras_counter_threshold_crossed(xe, response); + else + xe_warn(xe, "sysctrl: unexpected event %#x\n", response->event); + + if (!--count) { + xe_err(xe, "sysctrl: event flooding\n"); + return; + } + + xe_dbg(xe, "sysctrl: %u events pending\n", response->count); + } while (response->count); +} + +static void event_request_prepare(struct xe_device *xe, struct xe_sysctrl_app_msg_hdr *header, + struct xe_sysctrl_event_request *request) +{ + struct pci_dev *pdev = to_pci_dev(xe->drm.dev); + + header->data = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) | + REG_FIELD_PREP(APP_HDR_COMMAND_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT); + + request->vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0; + request->fn = PCI_FUNC(pdev->devfn); +} + +/** + * xe_sysctrl_event() - Handler for System Controller events + * @sc: System Controller instance + * + * Handle events generated by System Controller. + */ +void xe_sysctrl_event(struct xe_sysctrl *sc) +{ + struct xe_sysctrl_mailbox_command command = {}; + struct xe_sysctrl_event_response response = {}; + struct xe_sysctrl_event_request request = {}; + struct xe_sysctrl_app_msg_hdr header = {}; + + xe_device_assert_mem_access(sc_to_xe(sc)); + event_request_prepare(sc_to_xe(sc), &header, &request); + + command.header = header; + command.data_in = &request; + command.data_in_len = sizeof(request); + command.data_out = &response; + command.data_out_len = sizeof(response); + + guard(mutex)(&sc->event_lock); + get_pending_event(sc, &command); +} diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h new file mode 100644 index 000000000000..c16c66b9fa7f --- /dev/null +++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ + +#ifndef _XE_SYSCTRL_EVENT_TYPES_H_ +#define _XE_SYSCTRL_EVENT_TYPES_H_ + +#include + +#define XE_SYSCTRL_EVENT_DATA_LEN 59 + +/* Modify as needed */ +#define XE_SYSCTRL_EVENT_FLOOD 16 + +/** + * enum xe_sysctrl_event - Events reported by System Controller + * + * @XE_SYSCTRL_EVENT_THRESHOLD_CROSSED: Error counter threshold crossed + */ +enum xe_sysctrl_event { + XE_SYSCTRL_EVENT_THRESHOLD_CROSSED = 0x01, +}; + +/** + * struct xe_sysctrl_event_request - Request structure for pending event + */ +struct xe_sysctrl_event_request { + /** @vector: MSI-X vector that was triggered */ + u32 vector; + /** @fn: Function index (0-7) of PCIe device */ + u32 fn:8; + /** @reserved: Reserved for future use */ + u32 reserved:24; + /** @reserved1: Reserved for future use */ + u32 reserved1[2]; +} __packed; + +/** + * struct xe_sysctrl_event_response - Response structure for pending event + */ +struct xe_sysctrl_event_response { + /** @count: Pending event count after this response */ + u32 count; + /** @event: Pending event type */ + u32 event; + /** @timestamp: Timestamp of most recent event */ + u64 timestamp; + /** @extended: Event has extended payload */ + u32 extended:1; + /** @reserved: Reserved for future use */ + u32 reserved:31; + /** @data: Generic event data */ + u32 data[XE_SYSCTRL_EVENT_DATA_LEN]; +} __packed; + +#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */ diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c new file mode 100644 index 000000000000..3caa9f15875f --- /dev/null +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2026 Intel Corporation + */ + +#include +#include +#include +#include +#include + +#include "regs/xe_sysctrl_regs.h" +#include "xe_device.h" +#include "xe_mmio.h" +#include "xe_pm.h" +#include "xe_printk.h" +#include "xe_sysctrl.h" +#include "xe_sysctrl_mailbox.h" +#include "xe_sysctrl_mailbox_types.h" + +struct xe_sysctrl_mailbox_msg_hdr { + __le32 data; +} __packed; + +#define XE_SYSCTRL_HDR_GROUP_ID(hdr) \ + FIELD_GET(SYSCTRL_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data)) + +#define XE_SYSCTRL_HDR_COMMAND(hdr) \ + FIELD_GET(SYSCTRL_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data)) + +#define XE_SYSCTRL_HDR_IS_RESPONSE(hdr) \ + FIELD_GET(SYSCTRL_HDR_IS_RESPONSE, le32_to_cpu((hdr)->data)) + +#define XE_SYSCTRL_HDR_RESULT(hdr) \ + FIELD_GET(SYSCTRL_HDR_RESULT_MASK, le32_to_cpu((hdr)->data)) + +static bool sysctrl_wait_bit_clear(struct xe_sysctrl *sc, u32 bit_mask, + unsigned int timeout_ms) +{ + int ret; + + ret = xe_mmio_wait32_not(sc->mmio, SYSCTRL_MB_CTRL, bit_mask, bit_mask, + timeout_ms * 1000, NULL, false); + + return ret == 0; +} + +static bool sysctrl_wait_bit_set(struct xe_sysctrl *sc, u32 bit_mask, + unsigned int timeout_ms) +{ + int ret; + + ret = xe_mmio_wait32(sc->mmio, SYSCTRL_MB_CTRL, bit_mask, bit_mask, + timeout_ms * 1000, NULL, false); + + return ret == 0; +} + +static int sysctrl_write_frame(struct xe_sysctrl *sc, const void *frame, + size_t len) +{ + static const struct xe_reg regs[] = { + SYSCTRL_MB_DATA0, SYSCTRL_MB_DATA1, SYSCTRL_MB_DATA2, SYSCTRL_MB_DATA3 + }; + struct xe_device *xe = sc_to_xe(sc); + u32 val[XE_SYSCTRL_MB_FRAME_SIZE / sizeof(u32)] = {0}; + u32 dw = DIV_ROUND_UP(len, sizeof(u32)); + u32 i; + + xe_assert(xe, len > 0 && len <= XE_SYSCTRL_MB_FRAME_SIZE); + + memcpy(val, frame, len); + + for (i = 0; i < dw; i++) + xe_mmio_write32(sc->mmio, regs[i], val[i]); + + return 0; +} + +static int sysctrl_read_frame(struct xe_sysctrl *sc, void *frame, + size_t len) +{ + static const struct xe_reg regs[] = { + SYSCTRL_MB_DATA0, SYSCTRL_MB_DATA1, SYSCTRL_MB_DATA2, SYSCTRL_MB_DATA3 + }; + struct xe_device *xe = sc_to_xe(sc); + u32 val[XE_SYSCTRL_MB_FRAME_SIZE / sizeof(u32)] = {0}; + u32 dw = DIV_ROUND_UP(len, sizeof(u32)); + u32 i; + + xe_assert(xe, len > 0 && len <= XE_SYSCTRL_MB_FRAME_SIZE); + + for (i = 0; i < dw; i++) + val[i] = xe_mmio_read32(sc->mmio, regs[i]); + + memcpy(frame, val, len); + + return 0; +} + +static void sysctrl_clear_response(struct xe_sysctrl *sc) +{ + xe_mmio_rmw32(sc->mmio, SYSCTRL_MB_CTRL, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, 0); +} + +static int sysctrl_prepare_command(struct xe_device *xe, + u8 group_id, u8 command, + const void *data_in, size_t data_in_len, + u8 **mbox_cmd, size_t *cmd_size) +{ + struct xe_sysctrl_mailbox_msg_hdr *hdr; + size_t size; + u8 *buffer; + + xe_assert(xe, command <= SYSCTRL_HDR_COMMAND_MAX); + + if (data_in_len > XE_SYSCTRL_MB_MAX_MESSAGE_SIZE - sizeof(*hdr)) { + xe_err(xe, "sysctrl: Input data too large: %zu bytes\n", data_in_len); + return -EINVAL; + } + + size = sizeof(*hdr) + data_in_len; + + buffer = kmalloc(size, GFP_KERNEL); + if (!buffer) + return -ENOMEM; + + hdr = (struct xe_sysctrl_mailbox_msg_hdr *)buffer; + hdr->data = cpu_to_le32(FIELD_PREP(SYSCTRL_HDR_GROUP_ID_MASK, group_id) | + FIELD_PREP(SYSCTRL_HDR_COMMAND_MASK, command)); + + if (data_in && data_in_len) + memcpy(buffer + sizeof(*hdr), data_in, data_in_len); + + *mbox_cmd = buffer; + *cmd_size = size; + + return 0; +} + +static int sysctrl_send_frames(struct xe_sysctrl *sc, + const u8 *mbox_cmd, + size_t cmd_size, unsigned int timeout_ms) +{ + struct xe_device *xe = sc_to_xe(sc); + u32 ctrl_reg, total_frames, frame; + size_t bytes_sent, frame_size; + + total_frames = DIV_ROUND_UP(cmd_size, XE_SYSCTRL_MB_FRAME_SIZE); + + if (!sysctrl_wait_bit_clear(sc, SYSCTRL_MB_CTRL_RUN_BUSY, timeout_ms)) { + xe_err(xe, "sysctrl: Mailbox busy\n"); + return -EBUSY; + } + + sc->phase_bit ^= 1; + bytes_sent = 0; + + for (frame = 0; frame < total_frames; frame++) { + frame_size = min_t(size_t, cmd_size - bytes_sent, XE_SYSCTRL_MB_FRAME_SIZE); + + if (sysctrl_write_frame(sc, mbox_cmd + bytes_sent, frame_size)) { + xe_err(xe, "sysctrl: Failed to write frame %u\n", frame); + sc->phase_bit = 0; + return -EIO; + } + + ctrl_reg = SYSCTRL_MB_CTRL_RUN_BUSY | + REG_FIELD_PREP(SYSCTRL_FRAME_CURRENT_MASK, frame) | + REG_FIELD_PREP(SYSCTRL_FRAME_TOTAL_MASK, total_frames - 1) | + SYSCTRL_MB_CTRL_CMD | + (sc->phase_bit ? SYSCTRL_FRAME_PHASE : 0); + + xe_mmio_write32(sc->mmio, SYSCTRL_MB_CTRL, ctrl_reg); + + if (!sysctrl_wait_bit_clear(sc, SYSCTRL_MB_CTRL_RUN_BUSY, timeout_ms)) { + xe_err(xe, "sysctrl: Frame %u acknowledgment timeout\n", frame); + sc->phase_bit = 0; + return -ETIMEDOUT; + } + + bytes_sent += frame_size; + } + + return 0; +} + +static int sysctrl_process_frame(struct xe_sysctrl *sc, void *out, + size_t frame_size, unsigned int timeout_ms, + bool *done) +{ + u32 curr_frame, total_frames, ctrl_reg; + struct xe_device *xe = sc_to_xe(sc); + int ret; + + if (!sysctrl_wait_bit_set(sc, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) { + xe_err(xe, "sysctrl: Response frame timeout\n"); + return -ETIMEDOUT; + } + + ctrl_reg = xe_mmio_read32(sc->mmio, SYSCTRL_MB_CTRL); + total_frames = FIELD_GET(SYSCTRL_FRAME_TOTAL_MASK, ctrl_reg); + curr_frame = FIELD_GET(SYSCTRL_FRAME_CURRENT_MASK, ctrl_reg); + + ret = sysctrl_read_frame(sc, out, frame_size); + if (ret) + return ret; + + sysctrl_clear_response(sc); + + if (curr_frame == total_frames) + *done = true; + + return 0; +} + +static int sysctrl_receive_frames(struct xe_sysctrl *sc, + const struct xe_sysctrl_mailbox_msg_hdr *req, + void *data_out, size_t data_out_len, + size_t *rdata_len, unsigned int timeout_ms) +{ + struct xe_sysctrl_mailbox_msg_hdr *hdr; + struct xe_device *xe = sc_to_xe(sc); + size_t remain = sizeof(*hdr) + data_out_len; + u8 *buffer __free(kfree) = kzalloc(remain, GFP_KERNEL); + size_t frame_size; + bool done = false; + int ret = 0; + u8 *out; + + if (!buffer) + return -ENOMEM; + + out = buffer; + while (!done && remain) { + frame_size = min_t(size_t, remain, XE_SYSCTRL_MB_FRAME_SIZE); + + ret = sysctrl_process_frame(sc, out, frame_size, timeout_ms, + &done); + if (ret) + return ret; + + remain -= frame_size; + out += frame_size; + } + + hdr = (struct xe_sysctrl_mailbox_msg_hdr *)buffer; + + if (!XE_SYSCTRL_HDR_IS_RESPONSE(hdr) || + XE_SYSCTRL_HDR_GROUP_ID(hdr) != XE_SYSCTRL_HDR_GROUP_ID(req) || + XE_SYSCTRL_HDR_COMMAND(hdr) != XE_SYSCTRL_HDR_COMMAND(req)) { + xe_err(xe, "sysctrl: Response header mismatch\n"); + return -EPROTO; + } + + if (XE_SYSCTRL_HDR_RESULT(hdr) != 0) { + xe_err(xe, "sysctrl: Firmware error: 0x%02lx\n", + XE_SYSCTRL_HDR_RESULT(hdr)); + return -EIO; + } + + memcpy(data_out, hdr + 1, data_out_len); + *rdata_len = out - buffer - sizeof(*hdr); + + return 0; +} + +static int sysctrl_send_command(struct xe_sysctrl *sc, + const u8 *mbox_cmd, size_t cmd_size, + void *data_out, size_t data_out_len, + size_t *rdata_len, unsigned int timeout_ms) +{ + const struct xe_sysctrl_mailbox_msg_hdr *hdr; + size_t received; + int ret; + + ret = sysctrl_send_frames(sc, mbox_cmd, cmd_size, timeout_ms); + if (ret) + return ret; + + if (!data_out || !rdata_len) + return 0; + + hdr = (const struct xe_sysctrl_mailbox_msg_hdr *)mbox_cmd; + + ret = sysctrl_receive_frames(sc, hdr, data_out, data_out_len, + &received, timeout_ms); + if (ret) + return ret; + + *rdata_len = received; + + return 0; +} + +/** + * xe_sysctrl_mailbox_init - Initialize System Controller mailbox interface + * @sc: System controller structure + * + * Initialize system controller mailbox interface for communication. + */ +void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc) +{ + u32 ctrl_reg; + + ctrl_reg = xe_mmio_read32(sc->mmio, SYSCTRL_MB_CTRL); + sc->phase_bit = (ctrl_reg & SYSCTRL_FRAME_PHASE) ? 1 : 0; +} + +/** + * xe_sysctrl_send_command() - Send mailbox command to System Controller + * @sc: System Controller instance + * @cmd: Command descriptor containing request header and payload buffers + * @rdata_len: Pointer to store actual response data length + * + * Sends a mailbox command to System Controller firmware using + * System Controller mailbox and waits for a response. + * + * Request payload is provided via @cmd->data_in and @cmd->data_in_len. + * If a response is expected, @cmd->data_out must point to a buffer of + * size @cmd->data_out_len supplied by caller. + * + * On success, @rdata_len is updated with number of valid response bytes + * returned by firmware, bounded by @cmd->data_out_len. + * + * Return: 0 on success, or negative errno on failure. + */ +int xe_sysctrl_send_command(struct xe_sysctrl *sc, + struct xe_sysctrl_mailbox_command *cmd, + size_t *rdata_len) +{ + struct xe_device *xe = sc_to_xe(sc); + u8 group_id, command_code; + u8 *mbox_cmd = NULL; + size_t cmd_size = 0; + int ret; + + guard(xe_pm_runtime_noresume)(xe); + + if (!xe->info.has_sysctrl) + return -ENODEV; + + xe_assert(xe, cmd->data_in || cmd->data_out); + xe_assert(xe, !cmd->data_in || cmd->data_in_len); + xe_assert(xe, !cmd->data_out || cmd->data_out_len); + + group_id = XE_SYSCTRL_APP_HDR_GROUP_ID(&cmd->header); + command_code = XE_SYSCTRL_APP_HDR_COMMAND(&cmd->header); + + might_sleep(); + + ret = sysctrl_prepare_command(xe, group_id, command_code, + cmd->data_in, cmd->data_in_len, + &mbox_cmd, &cmd_size); + if (ret) { + xe_err(xe, "sysctrl: Failed to prepare command: %pe\n", ERR_PTR(ret)); + return ret; + } + + guard(mutex)(&sc->cmd_lock); + + ret = sysctrl_send_command(sc, mbox_cmd, cmd_size, + cmd->data_out, cmd->data_out_len, rdata_len, + XE_SYSCTRL_MB_DEFAULT_TIMEOUT_MS); + if (ret) + xe_err(xe, "sysctrl: Mailbox command failed: %pe\n", ERR_PTR(ret)); + + kfree(mbox_cmd); + + return ret; +} diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h new file mode 100644 index 000000000000..f67e9234de48 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ + +#ifndef _XE_SYSCTRL_MAILBOX_H_ +#define _XE_SYSCTRL_MAILBOX_H_ + +#include +#include + +#include "abi/xe_sysctrl_abi.h" + +struct xe_sysctrl; +struct xe_sysctrl_mailbox_command; + +#define XE_SYSCTRL_APP_HDR_GROUP_ID(hdr) \ + FIELD_GET(APP_HDR_GROUP_ID_MASK, (hdr)->data) + +#define XE_SYSCTRL_APP_HDR_COMMAND(hdr) \ + FIELD_GET(APP_HDR_COMMAND_MASK, (hdr)->data) + +#define XE_SYSCTRL_APP_HDR_VERSION(hdr) \ + FIELD_GET(APP_HDR_VERSION_MASK, (hdr)->data) + +void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc); +int xe_sysctrl_send_command(struct xe_sysctrl *sc, + struct xe_sysctrl_mailbox_command *cmd, + size_t *rdata_len); + +#endif diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h new file mode 100644 index 000000000000..84d7c647e743 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ + +#ifndef _XE_SYSCTRL_MAILBOX_TYPES_H_ +#define _XE_SYSCTRL_MAILBOX_TYPES_H_ + +#include + +#include "abi/xe_sysctrl_abi.h" + +/** + * enum xe_sysctrl_group - System Controller command groups + * + * @XE_SYSCTRL_GROUP_GFSP: GFSP group + */ +enum xe_sysctrl_group { + XE_SYSCTRL_GROUP_GFSP = 0x01, +}; + +/** + * enum xe_sysctrl_gfsp_cmd - Commands supported by GFSP group + * + * @XE_SYSCTRL_CMD_GET_PENDING_EVENT: Retrieve pending event + */ +enum xe_sysctrl_gfsp_cmd { + XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07, +}; + +/** + * struct xe_sysctrl_mailbox_command - System Controller mailbox command + */ +struct xe_sysctrl_mailbox_command { + /** @header: Application message header containing command information */ + struct xe_sysctrl_app_msg_hdr header; + + /** @data_in: Pointer to input payload data (can be NULL if no input data) */ + void *data_in; + + /** @data_in_len: Size of input payload in bytes (0 if no input data) */ + size_t data_in_len; + + /** @data_out: Pointer to output buffer for response data (can be NULL if no response) */ + void *data_out; + + /** @data_out_len: Size of output buffer in bytes (0 if no response expected) */ + size_t data_out_len; +}; + +#define XE_SYSCTRL_MB_FRAME_SIZE 16 +#define XE_SYSCTRL_MB_MAX_FRAMES 64 +#define XE_SYSCTRL_MB_MAX_MESSAGE_SIZE \ + (XE_SYSCTRL_MB_FRAME_SIZE * XE_SYSCTRL_MB_MAX_FRAMES) + +#define XE_SYSCTRL_MB_DEFAULT_TIMEOUT_MS 500 + +#endif diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h new file mode 100644 index 000000000000..66ba24f43017 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ + +#ifndef _XE_SYSCTRL_TYPES_H_ +#define _XE_SYSCTRL_TYPES_H_ + +#include +#include +#include + +struct xe_mmio; + +/** + * struct xe_sysctrl - System Controller driver context + * + * This structure maintains the runtime state for System Controller + * communication. All fields are initialized during xe_sysctrl_init() + * and protected appropriately for concurrent access. + */ +struct xe_sysctrl { + /** @mmio: MMIO region for system control registers */ + struct xe_mmio *mmio; + + /** @cmd_lock: Mutex protecting mailbox command operations */ + struct mutex cmd_lock; + + /** @phase_bit: Message boundary phase toggle bit (0 or 1) */ + bool phase_bit; + + /** @work: Pending events worker */ + struct work_struct work; + + /** @event_lock: Mutex protecting pending events */ + struct mutex event_lock; +}; + +#endif diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.c b/drivers/gpu/drm/xe/xe_tlb_inval.c index 10dcd4abb00f..bbd21d393062 100644 --- a/drivers/gpu/drm/xe/xe_tlb_inval.c +++ b/drivers/gpu/drm/xe/xe_tlb_inval.c @@ -529,7 +529,7 @@ int xe_tlb_inval_range_tilemask_submit(struct xe_device *xe, u32 asid, struct xe_tile *tile; u32 fence_id = 0; u8 id; - int err; + int err = 0; batch->num_fences = 0; if (!tile_mask) diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c index 5fd0d5506a7e..6ba47996bc7c 100644 --- a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c +++ b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c @@ -292,8 +292,6 @@ static void xe_ttm_vram_mgr_fini(struct drm_device *dev, void *arg) ttm_resource_manager_cleanup(&mgr->manager); ttm_set_driver_manager(&xe->ttm, mgr->mem_type, NULL); - - mutex_destroy(&mgr->lock); } int __xe_ttm_vram_mgr_init(struct xe_device *xe, struct xe_ttm_vram_mgr *mgr, @@ -312,7 +310,9 @@ int __xe_ttm_vram_mgr_init(struct xe_device *xe, struct xe_ttm_vram_mgr *mgr, man->func = &xe_ttm_vram_mgr_func; mgr->mem_type = mem_type; - mutex_init(&mgr->lock); + err = drmm_mutex_init(&xe->drm, &mgr->lock); + if (err) + return err; mgr->default_page_size = default_page_size; mgr->visible_size = io_size; mgr->visible_avail = io_size; diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c index f8de6a4bf189..ce39b77a084a 100644 --- a/drivers/gpu/drm/xe/xe_tuning.c +++ b/drivers/gpu/drm/xe/xe_tuning.c @@ -43,7 +43,7 @@ static const struct xe_rtp_entry_sr gt_tunings[] = { REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f))) }, { XE_RTP_NAME("Tuning: Compression Overfetch"), - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3499), FUNC(xe_rtp_match_has_flat_ccs)), XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX), SET(CCCHKNREG1, L3CMPCTRL)) @@ -97,7 +97,7 @@ static const struct xe_rtp_entry_sr gt_tunings[] = { { XE_RTP_NAME("Tuning: Set STLB Bank Hash Mode to 4KB"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, XE_RTP_END_VERSION_UNDEFINED), IS_INTEGRATED), - XE_RTP_ACTIONS(FIELD_SET(XEHP_GAMSTLB_CTRL, BANK_HASH_MODE, + XE_RTP_ACTIONS(FIELD_SET(GAMSTLB_CTRL, BANK_HASH_MODE, BANK_HASH_4KB_MODE)) }, }; @@ -124,6 +124,11 @@ static const struct xe_rtp_entry_sr engine_tunings[] = { GHWSP_CSB_REPORT_DIS, XE_RTP_ACTION_FLAG(ENGINE_BASE))) }, + { XE_RTP_NAME("Tuning: TileY 2x2 Walk"), + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, XE_RTP_END_VERSION_UNDEFINED), + FUNC(xe_rtp_match_first_render_or_compute)), + XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN2, TILEY_LOCALID)) + }, }; static const struct xe_rtp_entry_sr lrc_tunings[] = { diff --git a/drivers/gpu/drm/xe/xe_tuning.h b/drivers/gpu/drm/xe/xe_tuning.h index c1cc5927fda7..d18e187debf6 100644 --- a/drivers/gpu/drm/xe/xe_tuning.h +++ b/drivers/gpu/drm/xe/xe_tuning.h @@ -3,8 +3,8 @@ * Copyright © 2022 Intel Corporation */ -#ifndef _XE_TUNING_ -#define _XE_TUNING_ +#ifndef _XE_TUNING_H_ +#define _XE_TUNING_H_ struct drm_printer; struct xe_gt; diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c index 9cebb2490245..df2aa196f6f9 100644 --- a/drivers/gpu/drm/xe/xe_uc_fw.c +++ b/drivers/gpu/drm/xe/xe_uc_fw.c @@ -214,6 +214,17 @@ static struct xe_device *uc_fw_to_xe(struct xe_uc_fw *uc_fw) return gt_to_xe(uc_fw_to_gt(uc_fw)); } +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_GUC) +void xe_uc_fw_change_status(struct xe_uc_fw *uc_fw, enum xe_uc_fw_status status) +{ + xe_gt_dbg(uc_fw_to_gt(uc_fw), "%s %s->%s\n", + xe_uc_fw_type_repr(uc_fw->type), + xe_uc_fw_status_repr(uc_fw->status), + xe_uc_fw_status_repr(status)); + uc_fw->__status = status; +} +#endif + static void uc_fw_auto_select(struct xe_device *xe, struct xe_uc_fw *uc_fw) { diff --git a/drivers/gpu/drm/xe/xe_uc_fw.h b/drivers/gpu/drm/xe/xe_uc_fw.h index 6195e353f269..bb281b72a677 100644 --- a/drivers/gpu/drm/xe/xe_uc_fw.h +++ b/drivers/gpu/drm/xe/xe_uc_fw.h @@ -25,11 +25,15 @@ static inline u32 xe_uc_fw_rsa_offset(struct xe_uc_fw *uc_fw) return sizeof(struct uc_css_header) + uc_fw->ucode_size + uc_fw->css_offset; } +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_GUC) +void xe_uc_fw_change_status(struct xe_uc_fw *uc_fw, enum xe_uc_fw_status status); +#else static inline void xe_uc_fw_change_status(struct xe_uc_fw *uc_fw, enum xe_uc_fw_status status) { uc_fw->__status = status; } +#endif static inline const char *xe_uc_fw_status_repr(enum xe_uc_fw_status status) diff --git a/drivers/gpu/drm/xe/xe_uc_fw_abi.h b/drivers/gpu/drm/xe/xe_uc_fw_abi.h index 3c9a63d13032..74b888904fdc 100644 --- a/drivers/gpu/drm/xe/xe_uc_fw_abi.h +++ b/drivers/gpu/drm/xe/xe_uc_fw_abi.h @@ -3,8 +3,8 @@ * Copyright © 2022 Intel Corporation */ -#ifndef _XE_UC_FW_ABI_H -#define _XE_UC_FW_ABI_H +#ifndef _XE_UC_FW_ABI_H_ +#define _XE_UC_FW_ABI_H_ #include #include diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c index 62a87a051be7..43a578d9c067 100644 --- a/drivers/gpu/drm/xe/xe_vm.c +++ b/drivers/gpu/drm/xe/xe_vm.c @@ -634,9 +634,9 @@ void xe_vm_add_fault_entry_pf(struct xe_vm *vm, struct xe_pagefault *pf) e->address_precision = SZ_4K; e->access_type = pf->consumer.access_type; e->fault_type = FIELD_GET(XE_PAGEFAULT_TYPE_MASK, - pf->consumer.fault_type_level), + pf->consumer.fault_type_level); e->fault_level = FIELD_GET(XE_PAGEFAULT_LEVEL_MASK, - pf->consumer.fault_type_level), + pf->consumer.fault_type_level); list_add_tail(&e->list, &vm->faults.list); vm->faults.len++; @@ -1399,9 +1399,9 @@ static u16 pde_pat_index(struct xe_bo *bo) * something which is always safe). */ if (!xe_bo_is_vram(bo) && bo->ttm.ttm->caching == ttm_cached) - pat_index = xe->pat.idx[XE_CACHE_WB]; + pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB); else - pat_index = xe->pat.idx[XE_CACHE_NONE]; + pat_index = xe_cache_pat_idx(xe, XE_CACHE_NONE); xe_assert(xe, pat_index <= 3); @@ -3658,6 +3658,8 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm, op == DRM_XE_VM_BIND_OP_MAP_USERPTR) || XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE && op == DRM_XE_VM_BIND_OP_MAP_USERPTR) || + XE_IOCTL_DBG(xe, !IS_DGFX(xe) && coh_mode == XE_COH_NONE && + is_cpu_addr_mirror) || XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) && (op == DRM_XE_VM_BIND_OP_MAP_USERPTR || is_cpu_addr_mirror) && @@ -4156,7 +4158,8 @@ int xe_vm_get_property_ioctl(struct drm_device *drm, void *data, int ret = 0; if (XE_IOCTL_DBG(xe, (args->reserved[0] || args->reserved[1] || - args->reserved[2]))) + args->reserved[2] || args->extensions || + args->pad))) return -EINVAL; vm = xe_vm_lookup(xef, args->vm_id); @@ -4203,7 +4206,7 @@ struct dma_fence *xe_vm_bind_kernel_bo(struct xe_vm *vm, struct xe_bo *bo, ops = vm_bind_ioctl_ops_create(vm, &vops, bo, 0, addr, xe_bo_size(bo), DRM_XE_VM_BIND_OP_MAP, 0, 0, - vm->xe->pat.idx[cache_lvl]); + xe_cache_pat_idx(vm->xe, cache_lvl)); if (IS_ERR(ops)) { err = PTR_ERR(ops); goto release_vm_lock; @@ -4406,7 +4409,7 @@ struct xe_vm_snapshot { #define XE_VM_SNAP_FLAG_IS_NULL BIT(2) unsigned long flags; int uapi_mem_region; - int pat_index; + u16 pat_index; int cpu_caching; struct xe_bo *bo; void *data; diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c index 66f00d3f5c07..c78906dea82b 100644 --- a/drivers/gpu/drm/xe/xe_vm_madvise.c +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c @@ -621,6 +621,45 @@ static int xe_madvise_purgeable_retained_to_user(const struct xe_madvise_details return 0; } +static bool check_pat_args_are_sane(struct xe_device *xe, + struct xe_vmas_in_madvise_range *madvise_range, + u16 pat_index) +{ + u16 coh_mode = xe_pat_index_get_coh_mode(xe, pat_index); + int i; + + /* + * Using coh_none with CPU cached buffers is not allowed on iGPU. + * On iGPU the GPU shares the LLC with the CPU, so with coh_none + * the GPU bypasses CPU caches and reads directly from DRAM, + * potentially seeing stale sensitive data from previously freed + * pages. On dGPU this restriction does not apply, because the + * platform does not provide a non-coherent system memory access + * path that would violate the DMA coherency contract. + */ + if (coh_mode != XE_COH_NONE || IS_DGFX(xe)) + return true; + + for (i = 0; i < madvise_range->num_vmas; i++) { + struct xe_vma *vma = madvise_range->vmas[i]; + struct xe_bo *bo = xe_vma_bo(vma); + + if (bo) { + /* BO with WB caching + COH_NONE is not allowed */ + if (XE_IOCTL_DBG(xe, bo->cpu_caching == DRM_XE_GEM_CPU_CACHING_WB)) + return false; + /* Imported dma-buf without caching info, assume cached */ + if (XE_IOCTL_DBG(xe, !bo->cpu_caching)) + return false; + } else if (XE_IOCTL_DBG(xe, xe_vma_is_cpu_addr_mirror(vma) || + xe_vma_is_userptr(vma))) + /* System memory (userptr/SVM) is always CPU cached */ + return false; + } + + return true; +} + static bool check_bo_args_are_sane(struct xe_vm *vm, struct xe_vma **vmas, int num_vmas, u32 atomic_val) { @@ -750,6 +789,14 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil } } + if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) { + if (!check_pat_args_are_sane(xe, &madvise_range, + args->pat_index.val)) { + err = -EINVAL; + goto free_vmas; + } + } + if (madvise_range.has_bo_vmas) { if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) { if (!check_bo_args_are_sane(vm, madvise_range.vmas, diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h index a94827d7fbec..635ed29b9a69 100644 --- a/drivers/gpu/drm/xe/xe_vm_types.h +++ b/drivers/gpu/drm/xe/xe_vm_types.h @@ -412,10 +412,11 @@ struct xe_vm { struct xe_vma_op_map { /** @vma: VMA to map */ struct xe_vma *vma; + /** @vma_flags: VMA flags for this operation */ unsigned int vma_flags; /** @immediate: Immediate bind */ bool immediate; - /** @read_only: Read only */ + /** @invalidate_on_bind: Invalidate on bind */ bool invalidate_on_bind; /** @request_decompress: schedule decompression for GPU map */ bool request_decompress; diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c index 0538dcb8b18c..23eb7edbdd57 100644 --- a/drivers/gpu/drm/xe/xe_vram.c +++ b/drivers/gpu/drm/xe/xe_vram.c @@ -13,6 +13,7 @@ #include "regs/xe_gt_regs.h" #include "regs/xe_regs.h" #include "xe_assert.h" +#include "xe_bo.h" #include "xe_device.h" #include "xe_force_wake.h" #include "xe_gt_mcr.h" @@ -249,6 +250,27 @@ static int vram_region_init(struct xe_device *xe, struct xe_vram_region *vram, return 0; } +/** + * xe_map_resource_to_region - Map ttm resource to vram memory region + * @res: The ttm resource + * + * Get vram memory region using vram memory manager managing this resource + * + * Returns: pointer to xe_vram_region + */ +struct xe_vram_region *xe_map_resource_to_region(struct ttm_resource *res) +{ + struct xe_device *xe = ttm_to_xe_device(res->bo->bdev); + struct ttm_resource_manager *mgr; + struct xe_ttm_vram_mgr *vram_mgr; + + xe_assert(xe, mem_type_is_vram(res->mem_type)); + mgr = ttm_manager_type(&xe->ttm, res->mem_type); + vram_mgr = to_xe_ttm_vram_mgr(mgr); + + return container_of(vram_mgr, struct xe_vram_region, ttm); +} + /** * xe_vram_probe() - Probe VRAM configuration * @xe: the &xe_device diff --git a/drivers/gpu/drm/xe/xe_vram.h b/drivers/gpu/drm/xe/xe_vram.h index 72860f714fc6..dd1c8bf17922 100644 --- a/drivers/gpu/drm/xe/xe_vram.h +++ b/drivers/gpu/drm/xe/xe_vram.h @@ -10,7 +10,9 @@ struct xe_device; struct xe_vram_region; +struct ttm_resource; +struct xe_vram_region *xe_map_resource_to_region(struct ttm_resource *res); int xe_vram_probe(struct xe_device *xe); struct xe_vram_region *xe_vram_region_alloc(struct xe_device *xe, u8 id, u32 placement); diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index 546296f0220b..49f5e3e4c7cc 100644 --- a/drivers/gpu/drm/xe/xe_wa.c +++ b/drivers/gpu/drm/xe/xe_wa.c @@ -601,6 +601,19 @@ static const struct xe_rtp_entry_sr engine_was[] = { FUNC(xe_rtp_match_first_render_or_compute)), XE_RTP_ACTIONS(SET(ROW_CHICKEN5, CPSS_AWARE_DIS)) }, + + /* Xe3p_XPC */ + + { XE_RTP_NAME("14026999295"), + XE_RTP_RULES(GRAPHICS_VERSION(3511), + FUNC(xe_rtp_match_first_render_or_compute)), + XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_EU_GRF_POISON_TO_LSC)) + }, + { XE_RTP_NAME("18044193044"), + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0), + FUNC(xe_rtp_match_first_render_or_compute)), + XE_RTP_ACTIONS(SET(TDL_CHICKEN, BIT_APQ_OPT_DIS)) + }, }; static const struct xe_rtp_entry_sr lrc_was[] = { @@ -743,14 +756,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = { XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) }, - { XE_RTP_NAME("14019988906"), - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) - }, - { XE_RTP_NAME("14019877138"), - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) - }, { XE_RTP_NAME("14021490052"), XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), XE_RTP_ACTIONS(SET(FF_MODE, diff --git a/drivers/gpu/drm/xe/xe_wa.h b/drivers/gpu/drm/xe/xe_wa.h index 8fd6a5af0910..a5f7d33c1b32 100644 --- a/drivers/gpu/drm/xe/xe_wa.h +++ b/drivers/gpu/drm/xe/xe_wa.h @@ -3,8 +3,8 @@ * Copyright © 2022 Intel Corporation */ -#ifndef _XE_WA_ -#define _XE_WA_ +#ifndef _XE_WA_H_ +#define _XE_WA_H_ #include "xe_assert.h" diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules index 80b54b195f20..f8a185103b80 100644 --- a/drivers/gpu/drm/xe/xe_wa_oob.rules +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules @@ -51,6 +51,13 @@ MEDIA_VERSION_RANGE(2000, 3002), FUNC(xe_rtp_match_psmi_enabled) 16023683509 MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled) MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), FUNC(xe_rtp_match_psmi_enabled) +14025515070 GRAPHICS_VERSION(2004) + MEDIA_VERSION_RANGE(1301, 3000) + MEDIA_VERSION(3002) + GRAPHICS_VERSION_RANGE(3000, 3001) + GRAPHICS_VERSION_RANGE(3003, 3005) + MEDIA_VERSION(3500) + GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0) 15015404425_disable PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER) 16026007364 MEDIA_VERSION(3000) diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c index 379180fb3004..05bd31fe675b 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -1437,7 +1437,7 @@ zynqmp_dp_disp_connected_live_layer(struct zynqmp_dp *dp) } static void zynqmp_dp_disp_enable(struct zynqmp_dp *dp, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct zynqmp_disp_layer *layer; struct drm_bridge_state *bridge_state; @@ -1549,7 +1549,7 @@ zynqmp_dp_bridge_mode_valid(struct drm_bridge *bridge, } static void zynqmp_dp_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct zynqmp_dp *dp = bridge_to_dp(bridge); const struct drm_crtc_state *crtc_state; @@ -1626,7 +1626,7 @@ static void zynqmp_dp_bridge_atomic_enable(struct drm_bridge *bridge, } static void zynqmp_dp_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_bridge_state *old_bridge_state = drm_atomic_get_old_bridge_state(state, bridge); diff --git a/drivers/gpu/drm/xlnx/zynqmp_kms.c b/drivers/gpu/drm/xlnx/zynqmp_kms.c index a341ca492253..d5f922450565 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_kms.c +++ b/drivers/gpu/drm/xlnx/zynqmp_kms.c @@ -53,7 +53,7 @@ static inline struct zynqmp_dpsub *to_zynqmp_dpsub(struct drm_device *drm) */ static int zynqmp_dpsub_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -74,7 +74,7 @@ static int zynqmp_dpsub_plane_atomic_check(struct drm_plane *plane, } static void zynqmp_dpsub_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -92,7 +92,7 @@ static void zynqmp_dpsub_plane_atomic_disable(struct drm_plane *plane, } static void zynqmp_dpsub_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); @@ -193,7 +193,7 @@ static inline struct zynqmp_dpsub *crtc_to_dpsub(struct drm_crtc *crtc) } static void zynqmp_dpsub_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct zynqmp_dpsub *dpsub = crtc_to_dpsub(crtc); struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; @@ -219,7 +219,7 @@ static void zynqmp_dpsub_crtc_atomic_enable(struct drm_crtc *crtc, } static void zynqmp_dpsub_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct zynqmp_dpsub *dpsub = crtc_to_dpsub(crtc); struct drm_plane_state *old_plane_state; @@ -249,19 +249,19 @@ static void zynqmp_dpsub_crtc_atomic_disable(struct drm_crtc *crtc, } static int zynqmp_dpsub_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { return drm_atomic_add_affected_planes(state, crtc); } static void zynqmp_dpsub_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { drm_crtc_vblank_on(crtc); } static void zynqmp_dpsub_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { if (crtc->state->event) { struct drm_pending_vblank_event *event; diff --git a/drivers/mailbox/cix-mailbox.c b/drivers/mailbox/cix-mailbox.c index 443620e8ae37..43c76cdab24a 100644 --- a/drivers/mailbox/cix-mailbox.c +++ b/drivers/mailbox/cix-mailbox.c @@ -12,8 +12,6 @@ #include #include -#include "mailbox.h" - /* * The maximum transmission size is 32 words or 128 bytes. */ @@ -405,7 +403,7 @@ static int cix_mbox_startup(struct mbox_chan *chan) int index = cp->index, ret; u32 val; - ret = request_irq(priv->irq, cix_mbox_isr, 0, + ret = request_irq(priv->irq, cix_mbox_isr, IRQF_NO_SUSPEND, dev_name(priv->dev), chan); if (ret) { dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq); @@ -415,7 +413,7 @@ static int cix_mbox_startup(struct mbox_chan *chan) switch (cp->type) { case CIX_MBOX_TYPE_DB: /* Overwrite txdone_method for DB channel */ - chan->txdone_method = TXDONE_BY_ACK; + chan->txdone_method = MBOX_TXDONE_BY_ACK; fallthrough; case CIX_MBOX_TYPE_REG: if (priv->dir == CIX_MBOX_TX) { diff --git a/drivers/mailbox/exynos-mailbox.c b/drivers/mailbox/exynos-mailbox.c index 5f2d3b81c1db..d2355b128ba4 100644 --- a/drivers/mailbox/exynos-mailbox.c +++ b/drivers/mailbox/exynos-mailbox.c @@ -99,7 +99,6 @@ static int exynos_mbox_probe(struct platform_device *pdev) struct mbox_controller *mbox; struct mbox_chan *chans; struct clk *pclk; - int i; exynos_mbox = devm_kzalloc(dev, sizeof(*exynos_mbox), GFP_KERNEL); if (!exynos_mbox) @@ -129,9 +128,6 @@ static int exynos_mbox_probe(struct platform_device *pdev) mbox->ops = &exynos_mbox_chan_ops; mbox->of_xlate = exynos_mbox_of_xlate; - for (i = 0; i < EXYNOS_MBOX_CHAN_COUNT; i++) - chans[i].mbox = mbox; - exynos_mbox->mbox = mbox; platform_set_drvdata(pdev, exynos_mbox); diff --git a/drivers/mailbox/hi3660-mailbox.c b/drivers/mailbox/hi3660-mailbox.c index 17c29e960fbf..9b727a2b54a5 100644 --- a/drivers/mailbox/hi3660-mailbox.c +++ b/drivers/mailbox/hi3660-mailbox.c @@ -15,8 +15,6 @@ #include #include -#include "mailbox.h" - #define MBOX_CHAN_MAX 32 #define MBOX_RX 0x0 diff --git a/drivers/mailbox/hi6220-mailbox.c b/drivers/mailbox/hi6220-mailbox.c index f77741ce42e7..69d15b6283e9 100644 --- a/drivers/mailbox/hi6220-mailbox.c +++ b/drivers/mailbox/hi6220-mailbox.c @@ -79,12 +79,12 @@ struct hi6220_mbox { /* region for mailbox */ void __iomem *base; - unsigned int chan_num; - struct hi6220_mbox_chan *mchan; - void *irq_map_chan[MBOX_CHAN_MAX]; struct mbox_chan *chan; struct mbox_controller controller; + + unsigned int chan_num; + struct hi6220_mbox_chan mchan[] __counted_by(chan_num); }; static void mbox_set_state(struct hi6220_mbox *mbox, @@ -267,16 +267,12 @@ static int hi6220_mbox_probe(struct platform_device *pdev) struct hi6220_mbox *mbox; int i, err; - mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + mbox = devm_kzalloc(dev, struct_size(mbox, mchan, MBOX_CHAN_MAX), GFP_KERNEL); if (!mbox) return -ENOMEM; - mbox->dev = dev; mbox->chan_num = MBOX_CHAN_MAX; - mbox->mchan = devm_kcalloc(dev, - mbox->chan_num, sizeof(*mbox->mchan), GFP_KERNEL); - if (!mbox->mchan) - return -ENOMEM; + mbox->dev = dev; mbox->chan = devm_kcalloc(dev, mbox->chan_num, sizeof(*mbox->chan), GFP_KERNEL); diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index 003f9236c35e..246a9a9e3952 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -23,8 +23,6 @@ #include #include -#include "mailbox.h" - #define IMX_MU_CHANS 24 /* TX0/RX0/RXDB[0-3] */ #define IMX_MU_SCU_CHANS 6 @@ -734,7 +732,7 @@ static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox, p_chan = &mbox->chans[chan]; if (type == IMX_MU_TYPE_TXDB_V2) - p_chan->txdone_method = TXDONE_BY_ACK; + p_chan->txdone_method = MBOX_TXDONE_BY_ACK; return p_chan; } diff --git a/drivers/mailbox/mailbox-sti.c b/drivers/mailbox/mailbox-sti.c index b4b5bdd503cf..b6c9ecbbc8ec 100644 --- a/drivers/mailbox/mailbox-sti.c +++ b/drivers/mailbox/mailbox-sti.c @@ -21,8 +21,6 @@ #include #include -#include "mailbox.h" - #define STI_MBOX_INST_MAX 4 /* RAM saving: Max supported instances */ #define STI_MBOX_CHAN_MAX 20 /* RAM saving: Max supported channels */ diff --git a/drivers/mailbox/mailbox-test.c b/drivers/mailbox/mailbox-test.c index 3a28ab5c42e5..7b6ef033e77a 100644 --- a/drivers/mailbox/mailbox-test.c +++ b/drivers/mailbox/mailbox-test.c @@ -28,8 +28,6 @@ #define MBOX_HEXDUMP_MAX_LEN (MBOX_HEXDUMP_LINE_LEN * \ (MBOX_MAX_MSG_LEN / MBOX_BYTES_PER_LINE)) -static bool mbox_data_ready; - struct mbox_test_device { struct device *dev; void __iomem *tx_mmio; @@ -42,6 +40,7 @@ struct mbox_test_device { spinlock_t lock; struct mutex mutex; wait_queue_head_t waitq; + bool data_ready; struct fasync_struct *async_queue; struct dentry *root_debugfs_dir; }; @@ -162,7 +161,7 @@ static bool mbox_test_message_data_ready(struct mbox_test_device *tdev) unsigned long flags; spin_lock_irqsave(&tdev->lock, flags); - data_ready = mbox_data_ready; + data_ready = tdev->data_ready; spin_unlock_irqrestore(&tdev->lock, flags); return data_ready; @@ -227,7 +226,7 @@ static ssize_t mbox_test_message_read(struct file *filp, char __user *userbuf, *(touser + l) = '\0'; memset(tdev->rx_buffer, 0, MBOX_MAX_MSG_LEN); - mbox_data_ready = false; + tdev->data_ready = false; spin_unlock_irqrestore(&tdev->lock, flags); @@ -297,7 +296,7 @@ static void mbox_test_receive_message(struct mbox_client *client, void *message) message, MBOX_MAX_MSG_LEN); memcpy(tdev->rx_buffer, message, MBOX_MAX_MSG_LEN); } - mbox_data_ready = true; + tdev->data_ready = true; spin_unlock_irqrestore(&tdev->lock, flags); wake_up_interruptible(&tdev->waitq); @@ -336,7 +335,7 @@ mbox_test_request_channel(struct platform_device *pdev, const char *name) client = devm_kzalloc(&pdev->dev, sizeof(*client), GFP_KERNEL); if (!client) - return ERR_PTR(-ENOMEM); + return NULL; client->dev = &pdev->dev; client->rx_callback = mbox_test_receive_message; @@ -355,67 +354,80 @@ mbox_test_request_channel(struct platform_device *pdev, const char *name) return channel; } +static void __iomem *mbox_test_ioremap(struct platform_device *pdev, unsigned int res_num) +{ + struct resource *res; + void __iomem *mmio; + + res = platform_get_resource(pdev, IORESOURCE_MEM, res_num); + if (!res) + return NULL; + + mmio = devm_ioremap_resource(&pdev->dev, res); + if (PTR_ERR(mmio) == -EBUSY) { + dev_info(&pdev->dev, "trying workaround with plain ioremap\n"); + return devm_ioremap(&pdev->dev, res->start, resource_size(res)); + } + + return IS_ERR(mmio) ? NULL : mmio; +} + static int mbox_test_probe(struct platform_device *pdev) { struct mbox_test_device *tdev; - struct resource *res; - resource_size_t size; int ret; tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL); if (!tdev) return -ENOMEM; + tdev->dev = &pdev->dev; + spin_lock_init(&tdev->lock); + mutex_init(&tdev->mutex); + init_waitqueue_head(&tdev->waitq); + platform_set_drvdata(pdev, tdev); + /* It's okay for MMIO to be NULL */ - tdev->tx_mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (PTR_ERR(tdev->tx_mmio) == -EBUSY) { - /* if reserved area in SRAM, try just ioremap */ - size = resource_size(res); - tdev->tx_mmio = devm_ioremap(&pdev->dev, res->start, size); - } else if (IS_ERR(tdev->tx_mmio)) { - tdev->tx_mmio = NULL; - } + tdev->tx_mmio = mbox_test_ioremap(pdev, 0); /* If specified, second reg entry is Rx MMIO */ - tdev->rx_mmio = devm_platform_get_and_ioremap_resource(pdev, 1, &res); - if (PTR_ERR(tdev->rx_mmio) == -EBUSY) { - size = resource_size(res); - tdev->rx_mmio = devm_ioremap(&pdev->dev, res->start, size); - } else if (IS_ERR(tdev->rx_mmio)) { + tdev->rx_mmio = mbox_test_ioremap(pdev, 1); + if (!tdev->rx_mmio) tdev->rx_mmio = tdev->tx_mmio; - } tdev->tx_channel = mbox_test_request_channel(pdev, "tx"); tdev->rx_channel = mbox_test_request_channel(pdev, "rx"); - if (IS_ERR_OR_NULL(tdev->tx_channel) && IS_ERR_OR_NULL(tdev->rx_channel)) + if (!tdev->tx_channel && !tdev->rx_channel) return -EPROBE_DEFER; /* If Rx is not specified but has Rx MMIO, then Rx = Tx */ if (!tdev->rx_channel && (tdev->rx_mmio != tdev->tx_mmio)) tdev->rx_channel = tdev->tx_channel; - tdev->dev = &pdev->dev; - platform_set_drvdata(pdev, tdev); - - spin_lock_init(&tdev->lock); - mutex_init(&tdev->mutex); - if (tdev->rx_channel) { tdev->rx_buffer = devm_kzalloc(&pdev->dev, MBOX_MAX_MSG_LEN, GFP_KERNEL); - if (!tdev->rx_buffer) - return -ENOMEM; + if (!tdev->rx_buffer) { + ret = -ENOMEM; + goto err_free_chans; + } } ret = mbox_test_add_debugfs(pdev, tdev); if (ret) - return ret; + goto err_free_chans; - init_waitqueue_head(&tdev->waitq); dev_info(&pdev->dev, "Successfully registered\n"); return 0; + +err_free_chans: + if (tdev->tx_channel) + mbox_free_channel(tdev->tx_channel); + if (tdev->rx_channel && tdev->rx_channel != tdev->tx_channel) + mbox_free_channel(tdev->rx_channel); + return ret; } static void mbox_test_remove(struct platform_device *pdev) @@ -426,7 +438,7 @@ static void mbox_test_remove(struct platform_device *pdev) if (tdev->tx_channel) mbox_free_channel(tdev->tx_channel); - if (tdev->rx_channel) + if (tdev->rx_channel && tdev->rx_channel != tdev->tx_channel) mbox_free_channel(tdev->rx_channel); } diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c index 617ba505691d..bbc9fd75a95f 100644 --- a/drivers/mailbox/mailbox.c +++ b/drivers/mailbox/mailbox.c @@ -18,8 +18,6 @@ #include #include -#include "mailbox.h" - static LIST_HEAD(mbox_cons); static DEFINE_MUTEX(con_mutex); @@ -52,7 +50,7 @@ static void msg_submit(struct mbox_chan *chan) int err = -EBUSY; scoped_guard(spinlock_irqsave, &chan->lock) { - if (!chan->msg_count || chan->active_req) + if (!chan->msg_count || chan->active_req != MBOX_NO_MSG) break; count = chan->msg_count; @@ -74,7 +72,7 @@ static void msg_submit(struct mbox_chan *chan) } } - if (!err && (chan->txdone_method & TXDONE_BY_POLL)) { + if (!err && (chan->txdone_method & MBOX_TXDONE_BY_POLL)) { /* kick start the timer immediately to avoid delays */ scoped_guard(spinlock_irqsave, &chan->mbox->poll_hrt_lock) hrtimer_start(&chan->mbox->poll_hrt, 0, HRTIMER_MODE_REL); @@ -87,13 +85,13 @@ static void tx_tick(struct mbox_chan *chan, int r) scoped_guard(spinlock_irqsave, &chan->lock) { mssg = chan->active_req; - chan->active_req = NULL; + chan->active_req = MBOX_NO_MSG; } /* Submit next message */ msg_submit(chan); - if (!mssg) + if (mssg == MBOX_NO_MSG) return; /* Notify the client */ @@ -114,7 +112,7 @@ static enum hrtimer_restart txdone_hrtimer(struct hrtimer *hrtimer) for (i = 0; i < mbox->num_chans; i++) { struct mbox_chan *chan = &mbox->chans[i]; - if (chan->active_req && chan->cl) { + if (chan->active_req != MBOX_NO_MSG && chan->cl) { txdone = chan->mbox->ops->last_tx_done(chan); if (txdone) tx_tick(chan, 0); @@ -164,7 +162,7 @@ EXPORT_SYMBOL_GPL(mbox_chan_received_data); */ void mbox_chan_txdone(struct mbox_chan *chan, int r) { - if (unlikely(!(chan->txdone_method & TXDONE_BY_IRQ))) { + if (unlikely(!(chan->txdone_method & MBOX_TXDONE_BY_IRQ))) { dev_err(chan->mbox->dev, "Controller can't run the TX ticker\n"); return; @@ -185,7 +183,7 @@ EXPORT_SYMBOL_GPL(mbox_chan_txdone); */ void mbox_client_txdone(struct mbox_chan *chan, int r) { - if (unlikely(!(chan->txdone_method & TXDONE_BY_ACK))) { + if (unlikely(!(chan->txdone_method & MBOX_TXDONE_BY_ACK))) { dev_err(chan->mbox->dev, "Client can't run the TX ticker\n"); return; } @@ -218,6 +216,29 @@ bool mbox_client_peek_data(struct mbox_chan *chan) } EXPORT_SYMBOL_GPL(mbox_client_peek_data); +/** + * mbox_chan_tx_slots_available - Query the number of available TX queue slots. + * @chan: Mailbox channel to query. + * + * Clients may call this to check how many messages can be queued via + * mbox_send_message() before the channel's TX queue is full. This helps + * clients avoid the -ENOBUFS error without needing to increase + * MBOX_TX_QUEUE_LEN. + * This can be called from atomic context. + * + * Return: Number of available slots in the channel's TX queue. + */ +unsigned int mbox_chan_tx_slots_available(struct mbox_chan *chan) +{ + unsigned int ret; + + guard(spinlock_irqsave)(&chan->lock); + ret = MBOX_TX_QUEUE_LEN - chan->msg_count; + + return ret; +} +EXPORT_SYMBOL_GPL(mbox_chan_tx_slots_available); + /** * mbox_send_message - For client to submit a message to be * sent to the remote. @@ -246,7 +267,7 @@ int mbox_send_message(struct mbox_chan *chan, void *mssg) { int t; - if (!chan || !chan->cl) + if (!chan || !chan->cl || mssg == MBOX_NO_MSG) return -EINVAL; t = add_to_rbuf(chan, mssg); @@ -319,12 +340,12 @@ static int __mbox_bind_client(struct mbox_chan *chan, struct mbox_client *cl) scoped_guard(spinlock_irqsave, &chan->lock) { chan->msg_free = 0; chan->msg_count = 0; - chan->active_req = NULL; + chan->active_req = MBOX_NO_MSG; chan->cl = cl; init_completion(&chan->tx_complete); - if (chan->txdone_method == TXDONE_BY_POLL && cl->knows_txdone) - chan->txdone_method = TXDONE_BY_ACK; + if (chan->txdone_method == MBOX_TXDONE_BY_POLL && cl->knows_txdone) + chan->txdone_method = MBOX_TXDONE_BY_ACK; } if (chan->mbox->ops->startup) { @@ -341,7 +362,7 @@ static int __mbox_bind_client(struct mbox_chan *chan, struct mbox_client *cl) } /** - * mbox_bind_client - Request a mailbox channel. + * mbox_bind_client - Bind client to a mailbox channel. * @chan: The mailbox channel to bind the client to. * @cl: Identity of the client requesting the channel. * @@ -477,9 +498,9 @@ void mbox_free_channel(struct mbox_chan *chan) /* The queued TX requests are simply aborted, no callbacks are made */ scoped_guard(spinlock_irqsave, &chan->lock) { chan->cl = NULL; - chan->active_req = NULL; - if (chan->txdone_method == TXDONE_BY_ACK) - chan->txdone_method = TXDONE_BY_POLL; + chan->active_req = MBOX_NO_MSG; + if (chan->txdone_method == MBOX_TXDONE_BY_ACK) + chan->txdone_method = MBOX_TXDONE_BY_POLL; } module_put(chan->mbox->dev->driver->owner); @@ -505,18 +526,17 @@ int mbox_controller_register(struct mbox_controller *mbox) { int i, txdone; - /* Sanity check */ - if (!mbox || !mbox->dev || !mbox->ops || !mbox->num_chans) + if (!mbox || !mbox->dev || !mbox->ops || !mbox->chans || !mbox->num_chans) return -EINVAL; if (mbox->txdone_irq) - txdone = TXDONE_BY_IRQ; + txdone = MBOX_TXDONE_BY_IRQ; else if (mbox->txdone_poll) - txdone = TXDONE_BY_POLL; + txdone = MBOX_TXDONE_BY_POLL; else /* It has to be ACK then */ - txdone = TXDONE_BY_ACK; + txdone = MBOX_TXDONE_BY_ACK; - if (txdone == TXDONE_BY_POLL) { + if (txdone == MBOX_TXDONE_BY_POLL) { if (!mbox->ops->last_tx_done) { dev_err(mbox->dev, "last_tx_done method is absent\n"); @@ -532,6 +552,7 @@ int mbox_controller_register(struct mbox_controller *mbox) chan->cl = NULL; chan->mbox = mbox; + chan->active_req = MBOX_NO_MSG; chan->txdone_method = txdone; spin_lock_init(&chan->lock); } diff --git a/drivers/mailbox/mailbox.h b/drivers/mailbox/mailbox.h deleted file mode 100644 index e1ec4efab693..000000000000 --- a/drivers/mailbox/mailbox.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MAILBOX_H -#define __MAILBOX_H - -#include - -#define TXDONE_BY_IRQ BIT(0) /* controller has remote RTR irq */ -#define TXDONE_BY_POLL BIT(1) /* controller can read status of last TX */ -#define TXDONE_BY_ACK BIT(2) /* S/W ACK received by Client ticks the TX */ - -#endif /* __MAILBOX_H */ diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index d7c6b38888a3..e523c84b4808 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -493,14 +493,14 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data) if (curr_pa == end_pa - CMDQ_INST_SIZE || curr_pa == end_pa) { /* set to this task directly */ - writel(task->pa_base >> cmdq->pdata->shift, - thread->base + CMDQ_THR_CURR_ADDR); + gce_addr = cmdq_convert_gce_addr(task->pa_base, cmdq->pdata); + writel(gce_addr, thread->base + CMDQ_THR_CURR_ADDR); } else { cmdq_task_insert_into_thread(task); smp_mb(); /* modify jump before enable thread */ } - writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->pdata->shift, - thread->base + CMDQ_THR_END_ADDR); + gce_addr = cmdq_convert_gce_addr(task->pa_base + pkt->cmd_buf_size, cmdq->pdata); + writel(gce_addr, thread->base + CMDQ_THR_END_ADDR); cmdq_thread_resume(thread); } list_move_tail(&task->list_entry, &thread->task_busy_list); @@ -728,7 +728,7 @@ static int cmdq_probe(struct platform_device *pdev) cmdq->mbox.ops = &cmdq_mbox_chan_ops; cmdq->mbox.of_xlate = cmdq_xlate; - /* make use of TXDONE_BY_ACK */ + /* make use of MBOX_TXDONE_BY_ACK */ cmdq->mbox.txdone_irq = false; cmdq->mbox.txdone_poll = false; diff --git a/drivers/mailbox/mtk-vcp-mailbox.c b/drivers/mailbox/mtk-vcp-mailbox.c index cedad575528f..1b291b8ea15a 100644 --- a/drivers/mailbox/mtk-vcp-mailbox.c +++ b/drivers/mailbox/mtk-vcp-mailbox.c @@ -50,7 +50,7 @@ static struct mbox_chan *mtk_vcp_mbox_xlate(struct mbox_controller *mbox, const struct of_phandle_args *sp) { if (sp->args_count) - return NULL; + return ERR_PTR(-EINVAL); return &mbox->chans[0]; } diff --git a/drivers/mailbox/omap-mailbox.c b/drivers/mailbox/omap-mailbox.c index d9f100c18895..535ca8020877 100644 --- a/drivers/mailbox/omap-mailbox.c +++ b/drivers/mailbox/omap-mailbox.c @@ -22,8 +22,6 @@ #include #include -#include "mailbox.h" - #define MAILBOX_REVISION 0x000 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) @@ -240,7 +238,7 @@ static int omap_mbox_startup(struct omap_mbox *mbox) } if (mbox->send_no_irq) - mbox->chan->txdone_method = TXDONE_BY_ACK; + mbox->chan->txdone_method = MBOX_TXDONE_BY_ACK; omap_mbox_enable_irq(mbox, IRQ_RX); diff --git a/drivers/mailbox/pcc.c b/drivers/mailbox/pcc.c index 22e70af1ae5d..636879ae1db7 100644 --- a/drivers/mailbox/pcc.c +++ b/drivers/mailbox/pcc.c @@ -59,8 +59,6 @@ #include #include -#include "mailbox.h" - #define MBOX_IRQ_NAME "pcc-mbox" /** diff --git a/drivers/mailbox/rockchip-mailbox.c b/drivers/mailbox/rockchip-mailbox.c index 4d966cb2ed03..a1a7dee64356 100644 --- a/drivers/mailbox/rockchip-mailbox.c +++ b/drivers/mailbox/rockchip-mailbox.c @@ -46,7 +46,7 @@ struct rockchip_mbox { /* The maximum size of buf for each channel */ u32 buf_size; - struct rockchip_mbox_chan *chans; + struct rockchip_mbox_chan chans[]; }; static int rockchip_mbox_send_data(struct mbox_chan *chan, void *data) @@ -173,15 +173,10 @@ static int rockchip_mbox_probe(struct platform_device *pdev) drv_data = (const struct rockchip_mbox_data *) device_get_match_data(&pdev->dev); - mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL); + mb = devm_kzalloc(&pdev->dev, struct_size(mb, chans, drv_data->num_chans), GFP_KERNEL); if (!mb) return -ENOMEM; - mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans, - sizeof(*mb->chans), GFP_KERNEL); - if (!mb->chans) - return -ENOMEM; - mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans, sizeof(*mb->mbox.chans), GFP_KERNEL); if (!mb->mbox.chans) diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index ed9a0bb2bcd8..500fa77c7d53 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -16,8 +16,6 @@ #include -#include "mailbox.h" - #define HSP_INT_IE(x) (0x100 + ((x) * 4)) #define HSP_INT_IV 0x300 #define HSP_INT_IR 0x304 @@ -497,7 +495,7 @@ static int tegra_hsp_mailbox_flush(struct mbox_chan *chan, mbox_chan_txdone(chan, 0); /* Wait until channel is empty */ - if (chan->active_req != NULL) + if (chan->active_req != MBOX_NO_MSG) continue; return 0; @@ -516,7 +514,7 @@ static int tegra_hsp_mailbox_startup(struct mbox_chan *chan) struct tegra_hsp *hsp = mb->channel.hsp; unsigned long flags; - chan->txdone_method = TXDONE_BY_IRQ; + chan->txdone_method = MBOX_TXDONE_BY_IRQ; /* * Shared mailboxes start out as consumers by default. FULL and EMPTY diff --git a/drivers/md/md-bitmap.c b/drivers/md/md-bitmap.c index 83378c033c72..028b9ca8ce52 100644 --- a/drivers/md/md-bitmap.c +++ b/drivers/md/md-bitmap.c @@ -216,6 +216,7 @@ struct bitmap { }; static struct workqueue_struct *md_bitmap_wq; +static struct attribute_group md_bitmap_internal_group; static int __bitmap_resize(struct bitmap *bitmap, sector_t blocks, int chunksize, bool init); @@ -2580,6 +2581,30 @@ static int bitmap_resize(struct mddev *mddev, sector_t blocks, int chunksize) return __bitmap_resize(bitmap, blocks, chunksize, false); } +static bool bitmap_none_enabled(void *data, bool flush) +{ + return false; +} + +static int bitmap_none_create(struct mddev *mddev) +{ + return 0; +} + +static int bitmap_none_load(struct mddev *mddev) +{ + return 0; +} + +static void bitmap_none_destroy(struct mddev *mddev) +{ +} + +static int bitmap_none_get_stats(void *data, struct md_bitmap_stats *stats) +{ + return -ENOENT; +} + static ssize_t location_show(struct mddev *mddev, char *page) { @@ -2618,7 +2643,11 @@ location_store(struct mddev *mddev, const char *buf, size_t len) goto out; } - bitmap_destroy(mddev); + sysfs_unmerge_group(&mddev->kobj, &md_bitmap_internal_group); + md_bitmap_destroy_nosysfs(mddev); + mddev->bitmap_id = ID_BITMAP_NONE; + if (!mddev_set_bitmap_ops_nosysfs(mddev)) + goto none_err; mddev->bitmap_info.offset = 0; if (mddev->bitmap_info.file) { struct file *f = mddev->bitmap_info.file; @@ -2654,16 +2683,25 @@ location_store(struct mddev *mddev, const char *buf, size_t len) } mddev->bitmap_info.offset = offset; - rv = bitmap_create(mddev); - if (rv) - goto out; + md_bitmap_destroy_nosysfs(mddev); + mddev->bitmap_id = ID_BITMAP; + if (!mddev_set_bitmap_ops_nosysfs(mddev)) + goto bitmap_err; - rv = bitmap_load(mddev); + rv = md_bitmap_create_nosysfs(mddev); + if (rv) + goto create_err; + + rv = mddev->bitmap_ops->load(mddev); if (rv) { mddev->bitmap_info.offset = 0; - bitmap_destroy(mddev); - goto out; + goto load_err; } + + rv = sysfs_merge_group(&mddev->kobj, + &md_bitmap_internal_group); + if (rv) + goto merge_err; } } if (!mddev->external) { @@ -2679,6 +2717,22 @@ location_store(struct mddev *mddev, const char *buf, size_t len) if (rv) return rv; return len; + +merge_err: + mddev->bitmap_info.offset = 0; +load_err: + md_bitmap_destroy_nosysfs(mddev); +create_err: + mddev->bitmap_info.offset = 0; + mddev->bitmap_id = ID_BITMAP_NONE; + if (!mddev_set_bitmap_ops_nosysfs(mddev)) + rv = -ENOENT; + goto out; +bitmap_err: + rv = -ENOENT; +none_err: + mddev->bitmap_info.offset = 0; + goto out; } static struct md_sysfs_entry bitmap_location = @@ -2955,8 +3009,12 @@ static struct md_sysfs_entry max_backlog_used = __ATTR(max_backlog_used, S_IRUGO | S_IWUSR, behind_writes_used_show, behind_writes_used_reset); -static struct attribute *md_bitmap_attrs[] = { +static struct attribute *md_bitmap_common_attrs[] = { &bitmap_location.attr, + NULL +}; + +static struct attribute *md_bitmap_internal_attrs[] = { &bitmap_space.attr, &bitmap_timeout.attr, &bitmap_backlog.attr, @@ -2967,9 +3025,41 @@ static struct attribute *md_bitmap_attrs[] = { NULL }; -static struct attribute_group md_bitmap_group = { +static struct attribute_group md_bitmap_common_group = { .name = "bitmap", - .attrs = md_bitmap_attrs, + .attrs = md_bitmap_common_attrs, +}; + +static struct attribute_group md_bitmap_internal_group = { + .name = "bitmap", + .attrs = md_bitmap_internal_attrs, +}; + +static const struct attribute_group *bitmap_groups[] = { + &md_bitmap_common_group, + &md_bitmap_internal_group, + NULL, +}; + +static const struct attribute_group *bitmap_none_groups[] = { + &md_bitmap_common_group, + NULL, +}; + +static struct bitmap_operations bitmap_none_ops = { + .head = { + .type = MD_BITMAP, + .id = ID_BITMAP_NONE, + .name = "none", + }, + + .enabled = bitmap_none_enabled, + .create = bitmap_none_create, + .load = bitmap_none_load, + .destroy = bitmap_none_destroy, + .get_stats = bitmap_none_get_stats, + + .groups = bitmap_none_groups, }; static struct bitmap_operations bitmap_ops = { @@ -3013,21 +3103,38 @@ static struct bitmap_operations bitmap_ops = { .set_pages = bitmap_set_pages, .free = md_bitmap_free, - .group = &md_bitmap_group, + .groups = bitmap_groups, }; int md_bitmap_init(void) { + int err; + md_bitmap_wq = alloc_workqueue("md_bitmap", WQ_MEM_RECLAIM | WQ_UNBOUND, 0); if (!md_bitmap_wq) return -ENOMEM; - return register_md_submodule(&bitmap_ops.head); + err = register_md_submodule(&bitmap_none_ops.head); + if (err) + goto err_wq; + + err = register_md_submodule(&bitmap_ops.head); + if (err) + goto err_none; + + return 0; + +err_none: + unregister_md_submodule(&bitmap_none_ops.head); +err_wq: + destroy_workqueue(md_bitmap_wq); + return err; } void md_bitmap_exit(void) { - destroy_workqueue(md_bitmap_wq); unregister_md_submodule(&bitmap_ops.head); + unregister_md_submodule(&bitmap_none_ops.head); + destroy_workqueue(md_bitmap_wq); } diff --git a/drivers/md/md-bitmap.h b/drivers/md/md-bitmap.h index b42a28fa83a0..214f623c7e79 100644 --- a/drivers/md/md-bitmap.h +++ b/drivers/md/md-bitmap.h @@ -125,7 +125,7 @@ struct bitmap_operations { void (*set_pages)(void *data, unsigned long pages); void (*free)(void *data); - struct attribute_group *group; + const struct attribute_group **groups; }; /* the bitmap API */ diff --git a/drivers/md/md-llbitmap.c b/drivers/md/md-llbitmap.c index 9e7e6b1a6f15..1adc5b117821 100644 --- a/drivers/md/md-llbitmap.c +++ b/drivers/md/md-llbitmap.c @@ -1738,6 +1738,11 @@ static struct attribute_group md_llbitmap_group = { .attrs = md_llbitmap_attrs, }; +static const struct attribute_group *md_llbitmap_groups[] = { + &md_llbitmap_group, + NULL, +}; + static struct bitmap_operations llbitmap_ops = { .head = { .type = MD_BITMAP, @@ -1774,7 +1779,7 @@ static struct bitmap_operations llbitmap_ops = { .dirty_bits = llbitmap_dirty_bits, .write_all = llbitmap_write_all, - .group = &md_llbitmap_group, + .groups = md_llbitmap_groups, }; int md_llbitmap_init(void) diff --git a/drivers/md/md.c b/drivers/md/md.c index 5fb5ae8368ba..8b568eee8743 100644 --- a/drivers/md/md.c +++ b/drivers/md/md.c @@ -396,27 +396,19 @@ bool md_handle_request(struct mddev *mddev, struct bio *bio) { check_suspended: if (is_suspended(mddev, bio)) { - DEFINE_WAIT(__wait); /* Bail out if REQ_NOWAIT is set for the bio */ if (bio->bi_opf & REQ_NOWAIT) { bio_wouldblock_error(bio); return true; } - for (;;) { - prepare_to_wait(&mddev->sb_wait, &__wait, - TASK_UNINTERRUPTIBLE); - if (!is_suspended(mddev, bio)) - break; - schedule(); - } - finish_wait(&mddev->sb_wait, &__wait); + wait_event(mddev->sb_wait, !is_suspended(mddev, bio)); } if (!percpu_ref_tryget_live(&mddev->active_io)) goto check_suspended; if (!mddev->pers->make_request(mddev, bio)) { percpu_ref_put(&mddev->active_io); - if (!mddev->gendisk && mddev->pers->prepare_suspend) + if (mddev_is_dm(mddev) && mddev->pers->prepare_suspend) return false; goto check_suspended; } @@ -687,13 +679,38 @@ static void active_io_release(struct percpu_ref *ref) static void no_op(struct percpu_ref *r) {} -static bool mddev_set_bitmap_ops(struct mddev *mddev) +static void md_bitmap_sysfs_add(struct mddev *mddev) +{ + if (sysfs_update_groups(&mddev->kobj, mddev->bitmap_ops->groups)) + pr_warn("md: cannot register extra bitmap attributes for %s\n", + mdname(mddev)); + else + /* + * Inform user with KOBJ_CHANGE about new bitmap + * attributes. + */ + kobject_uevent(&mddev->kobj, KOBJ_CHANGE); +} + +static void md_bitmap_sysfs_del(struct mddev *mddev) +{ + int nr_groups = 0; + + for (nr_groups = 0; mddev->bitmap_ops->groups[nr_groups]; nr_groups++) + ; + + while (--nr_groups >= 1) + sysfs_unmerge_group(&mddev->kobj, + mddev->bitmap_ops->groups[nr_groups]); + sysfs_remove_group(&mddev->kobj, mddev->bitmap_ops->groups[0]); +} + +bool mddev_set_bitmap_ops_nosysfs(struct mddev *mddev) { - struct bitmap_operations *old = mddev->bitmap_ops; struct md_submodule_head *head; - if (mddev->bitmap_id == ID_BITMAP_NONE || - (old && old->head.id == mddev->bitmap_id)) + if (mddev->bitmap_ops && + mddev->bitmap_ops->head.id == mddev->bitmap_id) return true; xa_lock(&md_submodule); @@ -711,18 +728,6 @@ static bool mddev_set_bitmap_ops(struct mddev *mddev) mddev->bitmap_ops = (void *)head; xa_unlock(&md_submodule); - - if (!mddev_is_dm(mddev) && mddev->bitmap_ops->group) { - if (sysfs_create_group(&mddev->kobj, mddev->bitmap_ops->group)) - pr_warn("md: cannot register extra bitmap attributes for %s\n", - mdname(mddev)); - else - /* - * Inform user with KOBJ_CHANGE about new bitmap - * attributes. - */ - kobject_uevent(&mddev->kobj, KOBJ_CHANGE); - } return true; err: @@ -730,15 +735,6 @@ static bool mddev_set_bitmap_ops(struct mddev *mddev) return false; } -static void mddev_clear_bitmap_ops(struct mddev *mddev) -{ - if (!mddev_is_dm(mddev) && mddev->bitmap_ops && - mddev->bitmap_ops->group) - sysfs_remove_group(&mddev->kobj, mddev->bitmap_ops->group); - - mddev->bitmap_ops = NULL; -} - int mddev_init(struct mddev *mddev) { int err = 0; @@ -4279,7 +4275,7 @@ bitmap_type_show(struct mddev *mddev, char *page) xa_lock(&md_submodule); xa_for_each(&md_submodule, i, head) { - if (head->type != MD_BITMAP) + if (head->type != MD_BITMAP || head->id == ID_BITMAP_NONE) continue; if (mddev->bitmap_id == head->id) @@ -6059,10 +6055,7 @@ static struct attribute *md_default_attrs[] = { &md_logical_block_size.attr, NULL, }; - -static const struct attribute_group md_default_group = { - .attrs = md_default_attrs, -}; +ATTRIBUTE_GROUPS(md_default); static struct attribute *md_redundancy_attrs[] = { &md_scan_mode.attr, @@ -6087,11 +6080,6 @@ static const struct attribute_group md_redundancy_group = { .attrs = md_redundancy_attrs, }; -static const struct attribute_group *md_attr_groups[] = { - &md_default_group, - NULL, -}; - static ssize_t md_attr_show(struct kobject *kobj, struct attribute *attr, char *page) { @@ -6174,7 +6162,7 @@ static const struct sysfs_ops md_sysfs_ops = { static const struct kobj_type md_ktype = { .release = md_kobj_release, .sysfs_ops = &md_sysfs_ops, - .default_groups = md_attr_groups, + .default_groups = md_default_groups, }; int mdp_major = 0; @@ -6539,7 +6527,7 @@ static enum md_submodule_id md_bitmap_get_id_from_sb(struct mddev *mddev) return id; } -static int md_bitmap_create(struct mddev *mddev) +int md_bitmap_create_nosysfs(struct mddev *mddev) { enum md_submodule_id orig_id = mddev->bitmap_id; enum md_submodule_id sb_id; @@ -6548,8 +6536,10 @@ static int md_bitmap_create(struct mddev *mddev) if (mddev->bitmap_id == ID_BITMAP_NONE) return -EINVAL; - if (!mddev_set_bitmap_ops(mddev)) + if (!mddev_set_bitmap_ops_nosysfs(mddev)) { + mddev->bitmap_id = orig_id; return -ENOENT; + } err = mddev->bitmap_ops->create(mddev); if (!err) @@ -6560,37 +6550,72 @@ static int md_bitmap_create(struct mddev *mddev) * doesn't match, and mdadm is not the latest version to set * bitmap_type, set bitmap_ops based on the disk version. */ - mddev_clear_bitmap_ops(mddev); + mddev->bitmap_ops = NULL; sb_id = md_bitmap_get_id_from_sb(mddev); - if (sb_id == ID_BITMAP_NONE || sb_id == orig_id) + if (sb_id == ID_BITMAP_NONE || sb_id == orig_id) { + mddev->bitmap_id = orig_id; return err; + } pr_info("md: %s: bitmap version mismatch, switching from %d to %d\n", mdname(mddev), orig_id, sb_id); mddev->bitmap_id = sb_id; - if (!mddev_set_bitmap_ops(mddev)) { + if (!mddev_set_bitmap_ops_nosysfs(mddev)) { mddev->bitmap_id = orig_id; return -ENOENT; } err = mddev->bitmap_ops->create(mddev); if (err) { - mddev_clear_bitmap_ops(mddev); + mddev->bitmap_ops = NULL; mddev->bitmap_id = orig_id; } return err; } -static void md_bitmap_destroy(struct mddev *mddev) +static int md_bitmap_create(struct mddev *mddev) +{ + int err; + + err = md_bitmap_create_nosysfs(mddev); + if (err) + return err; + + if (!mddev_is_dm(mddev) && mddev->bitmap_ops->groups) + md_bitmap_sysfs_add(mddev); + + return 0; +} + +void md_bitmap_destroy_nosysfs(struct mddev *mddev) { if (!md_bitmap_registered(mddev)) return; mddev->bitmap_ops->destroy(mddev); - mddev_clear_bitmap_ops(mddev); + mddev->bitmap_ops = NULL; +} + +static void md_bitmap_destroy(struct mddev *mddev) +{ + if (!mddev_is_dm(mddev) && mddev->bitmap_ops && + mddev->bitmap_ops->groups) + md_bitmap_sysfs_del(mddev); + + md_bitmap_destroy_nosysfs(mddev); +} + +static void md_bitmap_set_none(struct mddev *mddev) +{ + mddev->bitmap_id = ID_BITMAP_NONE; + if (!mddev_set_bitmap_ops_nosysfs(mddev)) + return; + + if (!mddev_is_dm(mddev) && mddev->bitmap_ops->groups) + md_bitmap_sysfs_add(mddev); } int md_run(struct mddev *mddev) @@ -6713,7 +6738,7 @@ int md_run(struct mddev *mddev) } /* dm-raid expect sync_thread to be frozen until resume */ - if (mddev->gendisk) + if (!mddev_is_dm(mddev)) mddev->recovery = 0; /* may be over-ridden by personality */ @@ -6802,6 +6827,10 @@ int md_run(struct mddev *mddev) if (mddev->sb_flags) md_update_sb(mddev, 0); + if (IS_ENABLED(CONFIG_MD_BITMAP) && !mddev->bitmap_info.file && + !mddev->bitmap_info.offset) + md_bitmap_set_none(mddev); + md_new_event(); return 0; @@ -7747,7 +7776,8 @@ static int set_bitmap_file(struct mddev *mddev, int fd) { int err = 0; - if (!md_bitmap_registered(mddev)) + if (!md_bitmap_registered(mddev) || + mddev->bitmap_id == ID_BITMAP_NONE) return -EINVAL; if (mddev->pers) { @@ -7812,10 +7842,12 @@ static int set_bitmap_file(struct mddev *mddev, int fd) if (err) { md_bitmap_destroy(mddev); + md_bitmap_set_none(mddev); fd = -1; } } else if (fd < 0) { md_bitmap_destroy(mddev); + md_bitmap_set_none(mddev); } } @@ -8122,12 +8154,16 @@ static int update_array_info(struct mddev *mddev, mdu_array_info_t *info) mddev->bitmap_info.default_offset; mddev->bitmap_info.space = mddev->bitmap_info.default_space; + mddev->bitmap_id = ID_BITMAP; rv = md_bitmap_create(mddev); if (!rv) rv = mddev->bitmap_ops->load(mddev); - if (rv) + if (rv) { md_bitmap_destroy(mddev); + mddev->bitmap_info.offset = 0; + md_bitmap_set_none(mddev); + } } else { struct md_bitmap_stats stats; @@ -8155,6 +8191,7 @@ static int update_array_info(struct mddev *mddev, mdu_array_info_t *info) } md_bitmap_destroy(mddev); mddev->bitmap_info.offset = 0; + md_bitmap_set_none(mddev); } } md_update_sb(mddev, 1); @@ -9341,9 +9378,11 @@ static void md_bitmap_end(struct mddev *mddev, struct md_io_clone *md_io_clone) static void md_end_clone_io(struct bio *bio) { - struct md_io_clone *md_io_clone = bio->bi_private; + struct md_io_clone *md_io_clone = container_of(bio, struct md_io_clone, + bio_clone); struct bio *orig_bio = md_io_clone->orig_bio; struct mddev *mddev = md_io_clone->mddev; + struct completion *reshape_completion = bio->bi_private; if (bio_data_dir(orig_bio) == WRITE && md_bitmap_enabled(mddev, false)) md_bitmap_end(mddev, md_io_clone); @@ -9355,7 +9394,10 @@ static void md_end_clone_io(struct bio *bio) bio_end_io_acct(orig_bio, md_io_clone->start_time); bio_put(bio); - bio_endio(orig_bio); + if (unlikely(reshape_completion)) + complete(reshape_completion); + else + bio_endio(orig_bio); percpu_ref_put(&mddev->active_io); } @@ -9380,7 +9422,7 @@ static void md_clone_bio(struct mddev *mddev, struct bio **bio) } clone->bi_end_io = md_end_clone_io; - clone->bi_private = md_io_clone; + clone->bi_private = NULL; *bio = clone; } @@ -9391,26 +9433,6 @@ void md_account_bio(struct mddev *mddev, struct bio **bio) } EXPORT_SYMBOL_GPL(md_account_bio); -void md_free_cloned_bio(struct bio *bio) -{ - struct md_io_clone *md_io_clone = bio->bi_private; - struct bio *orig_bio = md_io_clone->orig_bio; - struct mddev *mddev = md_io_clone->mddev; - - if (bio_data_dir(orig_bio) == WRITE && md_bitmap_enabled(mddev, false)) - md_bitmap_end(mddev, md_io_clone); - - if (bio->bi_status && !orig_bio->bi_status) - orig_bio->bi_status = bio->bi_status; - - if (md_io_clone->start_time) - bio_end_io_acct(orig_bio, md_io_clone->start_time); - - bio_put(bio); - percpu_ref_put(&mddev->active_io); -} -EXPORT_SYMBOL_GPL(md_free_cloned_bio); - /* md_allow_write(mddev) * Calling this ensures that the array is marked 'active' so that writes * may proceed without blocking. It is important to call this before diff --git a/drivers/md/md.h b/drivers/md/md.h index d6f5482e2479..52c378086046 100644 --- a/drivers/md/md.h +++ b/drivers/md/md.h @@ -920,7 +920,6 @@ extern void md_finish_reshape(struct mddev *mddev); void md_submit_discard_bio(struct mddev *mddev, struct md_rdev *rdev, struct bio *bio, sector_t start, sector_t size); void md_account_bio(struct mddev *mddev, struct bio **bio); -void md_free_cloned_bio(struct bio *bio); extern bool __must_check md_flush_request(struct mddev *mddev, struct bio *bio); void md_write_metadata(struct mddev *mddev, struct md_rdev *rdev, @@ -935,6 +934,9 @@ extern void md_allow_write(struct mddev *mddev); extern void md_wait_for_blocked_rdev(struct md_rdev *rdev, struct mddev *mddev); extern void md_set_array_sectors(struct mddev *mddev, sector_t array_sectors); extern int md_check_no_bitmap(struct mddev *mddev); +bool mddev_set_bitmap_ops_nosysfs(struct mddev *mddev); +int md_bitmap_create_nosysfs(struct mddev *mddev); +void md_bitmap_destroy_nosysfs(struct mddev *mddev); extern int md_integrity_register(struct mddev *mddev); extern int strict_strtoul_scaled(const char *cp, unsigned long *res, int scale); @@ -1015,7 +1017,7 @@ static inline int mddev_suspend_and_lock(struct mddev *mddev) static inline void mddev_suspend_and_lock_nointr(struct mddev *mddev) { mddev_suspend(mddev, false); - mutex_lock(&mddev->reconfig_mutex); + mddev_lock_nointr(mddev); } static inline void mddev_unlock_and_resume(struct mddev *mddev) diff --git a/drivers/md/persistent-data/dm-btree-remove.c b/drivers/md/persistent-data/dm-btree-remove.c index 942cd47eb52d..aeec5b9a1dd5 100644 --- a/drivers/md/persistent-data/dm-btree-remove.c +++ b/drivers/md/persistent-data/dm-btree-remove.c @@ -490,12 +490,20 @@ static int rebalance_children(struct shadow_spine *s, if (le32_to_cpu(n->header.nr_entries) == 1) { struct dm_block *child; + int is_shared; dm_block_t b = value64(n, 0); + r = dm_tm_block_is_shared(info->tm, b, &is_shared); + if (r) + return r; + r = dm_tm_read_lock(info->tm, b, &btree_node_validator, &child); if (r) return r; + if (is_shared) + inc_children(info->tm, dm_block_data(child), vt); + memcpy(n, dm_block_data(child), dm_bm_block_size(dm_tm_get_bm(info->tm))); diff --git a/drivers/md/raid1-10.c b/drivers/md/raid1-10.c index c33099925f23..56a56a4da4f8 100644 --- a/drivers/md/raid1-10.c +++ b/drivers/md/raid1-10.c @@ -293,8 +293,13 @@ static inline bool raid1_should_read_first(struct mddev *mddev, * bio with REQ_RAHEAD or REQ_NOWAIT can fail at anytime, before such IO is * submitted to the underlying disks, hence don't record badblocks or retry * in this case. + * + * BLK_STS_INVAL means the bio was not valid for the underlying device. This + * is a user error, not a device failure, so retrying or recording bad blocks + * would be wrong. */ static inline bool raid1_should_handle_error(struct bio *bio) { - return !(bio->bi_opf & (REQ_RAHEAD | REQ_NOWAIT)); + return !(bio->bi_opf & (REQ_RAHEAD | REQ_NOWAIT)) && + bio->bi_status != BLK_STS_INVAL; } diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c index ba91f7e61920..64d970e2ef50 100644 --- a/drivers/md/raid1.c +++ b/drivers/md/raid1.c @@ -1510,21 +1510,14 @@ static void raid1_write_request(struct mddev *mddev, struct bio *bio, mddev->cluster_ops->area_resyncing(mddev, WRITE, bio->bi_iter.bi_sector, bio_end_sector(bio))) { - DEFINE_WAIT(w); if (bio->bi_opf & REQ_NOWAIT) { bio_wouldblock_error(bio); return; } - for (;;) { - prepare_to_wait(&conf->wait_barrier, - &w, TASK_IDLE); - if (!mddev->cluster_ops->area_resyncing(mddev, WRITE, - bio->bi_iter.bi_sector, - bio_end_sector(bio))) - break; - schedule(); - } - finish_wait(&conf->wait_barrier, &w); + wait_event_idle(conf->wait_barrier, + !mddev->cluster_ops->area_resyncing(mddev, WRITE, + bio->bi_iter.bi_sector, + bio_end_sector(bio))); } /* diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c index 4901ebe45c87..39085e7dd6d2 100644 --- a/drivers/md/raid10.c +++ b/drivers/md/raid10.c @@ -3791,6 +3791,8 @@ static int setup_geo(struct geom *geo, struct mddev *mddev, enum geo_type new) nc = layout & 255; fc = (layout >> 8) & 255; fo = layout & (1<<16); + if (!nc || !fc) + return -1; geo->raid_disks = disks; geo->near_copies = nc; geo->far_copies = fc; diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 6e79829c5acb..0d76e82f4506 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -6217,7 +6217,12 @@ static bool raid5_make_request(struct mddev *mddev, struct bio * bi) mempool_free(ctx, conf->ctx_pool); if (res == STRIPE_WAIT_RESHAPE) { - md_free_cloned_bio(bi); + DECLARE_COMPLETION_ONSTACK(done); + WRITE_ONCE(bi->bi_private, &done); + + bio_endio(bi); + + wait_for_completion(&done); return false; } diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 8aa3753aaaa1..0b076790bd9d 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -100,6 +100,17 @@ spinand_fill_page_read_op(struct spinand_device *spinand, u64 addr) return op; } +static struct spi_mem_op +spinand_fill_page_read_packed_op(struct spinand_device *spinand, u64 addr) +{ + struct spi_mem_op op = spinand->op_templates->page_read; + + op.cmd.opcode |= addr >> 16; + op.addr.val = addr & 0xFFFF; + + return op; +} + struct spi_mem_op spinand_fill_prog_exec_op(struct spinand_device *spinand, u64 addr) { @@ -453,7 +464,10 @@ static int spinand_load_page_op(struct spinand_device *spinand, { struct nand_device *nand = spinand_to_nand(spinand); unsigned int row = nanddev_pos_to_row(nand, &req->pos); - struct spi_mem_op op = SPINAND_OP(spinand, page_read, row); + bool packed = spinand->flags & SPINAND_ODTR_PACKED_PAGE_READ; + struct spi_mem_op op = packed ? + SPINAND_OP(spinand, page_read_packed, row) : + SPINAND_OP(spinand, page_read, row); return spi_mem_exec_op(spinand->spimem, &op); } @@ -1489,9 +1503,13 @@ static int spinand_init_odtr_instruction_set(struct spinand_device *spinand) if (!spi_mem_supports_op(spinand->spimem, &tmpl->blk_erase)) return -EOPNOTSUPP; - tmpl->page_read = (struct spi_mem_op)SPINAND_PAGE_READ_8D_8D_0_OP(0); - if (!spi_mem_supports_op(spinand->spimem, &tmpl->page_read)) + if (spinand->flags & SPINAND_ODTR_PACKED_PAGE_READ) + tmpl->page_read = (struct spi_mem_op)SPINAND_PAGE_READ_PACKED_8D_8D_0_OP(0); + else + tmpl->page_read = (struct spi_mem_op)SPINAND_PAGE_READ_8D_8D_0_OP(0); + if (!spi_mem_supports_op(spinand->spimem, &tmpl->page_read)) { return -EOPNOTSUPP; + } tmpl->prog_exec = (struct spi_mem_op)SPINAND_PROG_EXEC_8D_8D_0_OP(0); if (!spi_mem_supports_op(spinand->spimem, &tmpl->prog_exec)) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index ad22774096e6..7cc0f0091430 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -99,7 +99,7 @@ static SPINAND_OP_VARIANTS(update_cache_variants, #define SPINAND_WINBOND_WRITE_VCR_8D_8D_8D(reg, buf) \ SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x81, 8), \ - SPI_MEM_DTR_OP_ADDR(4, reg, 8), \ + SPI_MEM_DTR_OP_ADDR(4, reg << 8, 8), \ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_DTR_OP_DATA_OUT(2, buf, 8)) @@ -518,7 +518,7 @@ static const struct spinand_info winbond_spinand_table[] = { SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants, &write_cache_octal_variants, &update_cache_octal_variants), - 0, + SPINAND_ODTR_PACKED_PAGE_READ, SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)), @@ -529,7 +529,7 @@ static const struct spinand_info winbond_spinand_table[] = { SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants, &write_cache_octal_variants, &update_cache_octal_variants), - 0, + SPINAND_ODTR_PACKED_PAGE_READ, SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)), diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index fa6956144d2e..14ba1680c315 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 +#include #include #include #include @@ -92,7 +93,8 @@ static int spi_nor_params_show(struct seq_file *s, void *data) seq_printf(s, "address nbytes\t%u\n", nor->addr_nbytes); seq_puts(s, "flags\t\t"); - spi_nor_print_flags(s, nor->flags, snor_f_names, sizeof(snor_f_names)); + spi_nor_print_flags(s, nor->flags, snor_f_names, + ARRAY_SIZE(snor_f_names)); seq_puts(s, "\n"); seq_puts(s, "\nopcodes\n"); diff --git a/drivers/net/bareudp.c b/drivers/net/bareudp.c index 0df3208783ad..da5866ba0699 100644 --- a/drivers/net/bareudp.c +++ b/drivers/net/bareudp.c @@ -529,6 +529,9 @@ static int bareudp_fill_metadata_dst(struct net_device *dev, struct in6_addr saddr; struct socket *sock = rcu_dereference(bareudp->sock); + if (!sock) + return -ESHUTDOWN; + dst = udp_tunnel6_dst_lookup(skb, dev, bareudp->net, sock, 0, &saddr, &info->key, sport, bareudp->port, info->key.tos, diff --git a/drivers/net/bonding/bond_3ad.c b/drivers/net/bonding/bond_3ad.c index af7f74cfdc08..f0aa7d2f2171 100644 --- a/drivers/net/bonding/bond_3ad.c +++ b/drivers/net/bonding/bond_3ad.c @@ -1029,6 +1029,7 @@ static void ad_cond_set_peer_notif(struct port *port) static void ad_mux_machine(struct port *port, bool *update_slave_arr) { struct bonding *bond = __get_bond_by_port(port); + struct aggregator *aggregator; mux_states_t last_state; /* keep current State Machine state to compare later if it was @@ -1036,6 +1037,7 @@ static void ad_mux_machine(struct port *port, bool *update_slave_arr) */ last_state = port->sm_mux_state; + aggregator = rcu_dereference(port->aggregator); if (port->sm_vars & AD_PORT_BEGIN) { port->sm_mux_state = AD_MUX_DETACHED; } else { @@ -1055,7 +1057,7 @@ static void ad_mux_machine(struct port *port, bool *update_slave_arr) * cycle to update ready variable, we check * READY_N and update READY here */ - __set_agg_ports_ready(port->aggregator, __agg_ports_are_ready(port->aggregator)); + __set_agg_ports_ready(aggregator, __agg_ports_are_ready(aggregator)); port->sm_mux_state = AD_MUX_DETACHED; break; } @@ -1070,7 +1072,7 @@ static void ad_mux_machine(struct port *port, bool *update_slave_arr) * update ready variable, we check READY_N and update * READY here */ - __set_agg_ports_ready(port->aggregator, __agg_ports_are_ready(port->aggregator)); + __set_agg_ports_ready(aggregator, __agg_ports_are_ready(aggregator)); /* if the wait_while_timer expired, and the port is * in READY state, move to ATTACHED state @@ -1086,7 +1088,7 @@ static void ad_mux_machine(struct port *port, bool *update_slave_arr) if ((port->sm_vars & AD_PORT_SELECTED) && (port->partner_oper.port_state & LACP_STATE_SYNCHRONIZATION) && !__check_agg_selection_timer(port)) { - if (port->aggregator->is_active) { + if (aggregator->is_active) { int state = AD_MUX_COLLECTING_DISTRIBUTING; if (!bond->params.coupled_control) @@ -1102,9 +1104,9 @@ static void ad_mux_machine(struct port *port, bool *update_slave_arr) * cycle to update ready variable, we check * READY_N and update READY here */ - __set_agg_ports_ready(port->aggregator, __agg_ports_are_ready(port->aggregator)); + __set_agg_ports_ready(aggregator, __agg_ports_are_ready(aggregator)); port->sm_mux_state = AD_MUX_DETACHED; - } else if (port->aggregator->is_active) { + } else if (aggregator->is_active) { port->actor_oper_port_state |= LACP_STATE_SYNCHRONIZATION; } @@ -1115,7 +1117,7 @@ static void ad_mux_machine(struct port *port, bool *update_slave_arr) * sure that a collecting distributing * port in an active aggregator is enabled */ - if (port->aggregator->is_active && + if (aggregator->is_active && !__port_is_collecting_distributing(port)) { __enable_port(port); *update_slave_arr = true; @@ -1134,7 +1136,7 @@ static void ad_mux_machine(struct port *port, bool *update_slave_arr) */ struct slave *slave = port->slave; - if (port->aggregator->is_active && + if (aggregator->is_active && bond_is_slave_rx_disabled(slave)) { ad_enable_collecting(port); *update_slave_arr = true; @@ -1154,8 +1156,8 @@ static void ad_mux_machine(struct port *port, bool *update_slave_arr) * sure that a collecting distributing * port in an active aggregator is enabled */ - if (port->aggregator && - port->aggregator->is_active && + if (aggregator && + aggregator->is_active && !__port_is_collecting_distributing(port)) { __enable_port(port); *update_slave_arr = true; @@ -1187,7 +1189,7 @@ static void ad_mux_machine(struct port *port, bool *update_slave_arr) port->sm_mux_timer_counter = __ad_timer_to_ticks(AD_WAIT_WHILE_TIMER, 0); break; case AD_MUX_ATTACHED: - if (port->aggregator->is_active) + if (aggregator->is_active) port->actor_oper_port_state |= LACP_STATE_SYNCHRONIZATION; else @@ -1561,9 +1563,9 @@ static void ad_port_selection_logic(struct port *port, bool *update_slave_arr) bond = __get_bond_by_port(port); /* if the port is connected to other aggregator, detach it */ - if (port->aggregator) { + temp_aggregator = rcu_dereference(port->aggregator); + if (temp_aggregator) { /* detach the port from its former aggregator */ - temp_aggregator = port->aggregator; for (curr_port = temp_aggregator->lag_ports; curr_port; last_port = curr_port, curr_port = curr_port->next_port_in_aggregator) { @@ -1586,7 +1588,7 @@ static void ad_port_selection_logic(struct port *port, bool *update_slave_arr) /* clear the port's relations to this * aggregator */ - port->aggregator = NULL; + RCU_INIT_POINTER(port->aggregator, NULL); port->next_port_in_aggregator = NULL; port->actor_port_aggregator_identifier = 0; @@ -1609,7 +1611,7 @@ static void ad_port_selection_logic(struct port *port, bool *update_slave_arr) port->slave->bond->dev->name, port->slave->dev->name, port->actor_port_number, - port->aggregator->aggregator_identifier); + temp_aggregator->aggregator_identifier); } } /* search on all aggregators for a suitable aggregator for this port */ @@ -1633,15 +1635,15 @@ static void ad_port_selection_logic(struct port *port, bool *update_slave_arr) ) ) { /* attach to the founded aggregator */ - port->aggregator = aggregator; + rcu_assign_pointer(port->aggregator, aggregator); port->actor_port_aggregator_identifier = - port->aggregator->aggregator_identifier; + aggregator->aggregator_identifier; port->next_port_in_aggregator = aggregator->lag_ports; - port->aggregator->num_of_ports++; + aggregator->num_of_ports++; aggregator->lag_ports = port; slave_dbg(bond->dev, slave->dev, "Port %d joined LAG %d (existing LAG)\n", port->actor_port_number, - port->aggregator->aggregator_identifier); + aggregator->aggregator_identifier); /* mark this port as selected */ port->sm_vars |= AD_PORT_SELECTED; @@ -1656,39 +1658,40 @@ static void ad_port_selection_logic(struct port *port, bool *update_slave_arr) if (!found) { if (free_aggregator) { /* assign port a new aggregator */ - port->aggregator = free_aggregator; port->actor_port_aggregator_identifier = - port->aggregator->aggregator_identifier; + free_aggregator->aggregator_identifier; /* update the new aggregator's parameters * if port was responsed from the end-user */ if (port->actor_oper_port_key & AD_DUPLEX_KEY_MASKS) /* if port is full duplex */ - port->aggregator->is_individual = false; + free_aggregator->is_individual = false; else - port->aggregator->is_individual = true; + free_aggregator->is_individual = true; - port->aggregator->actor_admin_aggregator_key = + free_aggregator->actor_admin_aggregator_key = port->actor_admin_port_key; - port->aggregator->actor_oper_aggregator_key = + free_aggregator->actor_oper_aggregator_key = port->actor_oper_port_key; - port->aggregator->partner_system = + free_aggregator->partner_system = port->partner_oper.system; - port->aggregator->partner_system_priority = + free_aggregator->partner_system_priority = port->partner_oper.system_priority; - port->aggregator->partner_oper_aggregator_key = port->partner_oper.key; - port->aggregator->receive_state = 1; - port->aggregator->transmit_state = 1; - port->aggregator->lag_ports = port; - port->aggregator->num_of_ports++; + free_aggregator->partner_oper_aggregator_key = port->partner_oper.key; + free_aggregator->receive_state = 1; + free_aggregator->transmit_state = 1; + free_aggregator->lag_ports = port; + free_aggregator->num_of_ports++; + + rcu_assign_pointer(port->aggregator, free_aggregator); /* mark this port as selected */ port->sm_vars |= AD_PORT_SELECTED; slave_dbg(bond->dev, port->slave->dev, "Port %d joined LAG %d (new LAG)\n", port->actor_port_number, - port->aggregator->aggregator_identifier); + free_aggregator->aggregator_identifier); } else { slave_err(bond->dev, port->slave->dev, "Port %d did not find a suitable aggregator\n", @@ -1700,13 +1703,12 @@ static void ad_port_selection_logic(struct port *port, bool *update_slave_arr) * in all aggregator's ports, else set ready=FALSE in all * aggregator's ports */ - __set_agg_ports_ready(port->aggregator, - __agg_ports_are_ready(port->aggregator)); + aggregator = rcu_dereference(port->aggregator); + __set_agg_ports_ready(aggregator, __agg_ports_are_ready(aggregator)); - aggregator = __get_first_agg(port); - ad_agg_selection_logic(aggregator, update_slave_arr); + ad_agg_selection_logic(__get_first_agg(port), update_slave_arr); - if (!port->aggregator->is_active) + if (!aggregator->is_active) port->actor_oper_port_state &= ~LACP_STATE_SYNCHRONIZATION; } @@ -2075,13 +2077,15 @@ static void ad_initialize_port(struct port *port, const struct bond_params *bond */ static void ad_enable_collecting(struct port *port) { - if (port->aggregator->is_active) { + struct aggregator *aggregator = rcu_dereference(port->aggregator); + + if (aggregator->is_active) { struct slave *slave = port->slave; slave_dbg(slave->bond->dev, slave->dev, "Enabling collecting on port %d (LAG %d)\n", port->actor_port_number, - port->aggregator->aggregator_identifier); + aggregator->aggregator_identifier); __enable_collecting_port(port); } } @@ -2093,11 +2097,13 @@ static void ad_enable_collecting(struct port *port) */ static void ad_disable_distributing(struct port *port, bool *update_slave_arr) { - if (port->aggregator && __agg_has_partner(port->aggregator)) { + struct aggregator *aggregator = rcu_dereference(port->aggregator); + + if (aggregator && __agg_has_partner(aggregator)) { slave_dbg(port->slave->bond->dev, port->slave->dev, "Disabling distributing on port %d (LAG %d)\n", port->actor_port_number, - port->aggregator->aggregator_identifier); + aggregator->aggregator_identifier); __disable_distributing_port(port); /* Slave array needs an update */ *update_slave_arr = true; @@ -2114,11 +2120,13 @@ static void ad_disable_distributing(struct port *port, bool *update_slave_arr) static void ad_enable_collecting_distributing(struct port *port, bool *update_slave_arr) { - if (port->aggregator->is_active) { + struct aggregator *aggregator = rcu_dereference(port->aggregator); + + if (aggregator->is_active) { slave_dbg(port->slave->bond->dev, port->slave->dev, "Enabling port %d (LAG %d)\n", port->actor_port_number, - port->aggregator->aggregator_identifier); + aggregator->aggregator_identifier); __enable_port(port); /* Slave array needs update */ *update_slave_arr = true; @@ -2135,11 +2143,13 @@ static void ad_enable_collecting_distributing(struct port *port, static void ad_disable_collecting_distributing(struct port *port, bool *update_slave_arr) { - if (port->aggregator && __agg_has_partner(port->aggregator)) { + struct aggregator *aggregator = rcu_dereference(port->aggregator); + + if (aggregator && __agg_has_partner(aggregator)) { slave_dbg(port->slave->bond->dev, port->slave->dev, "Disabling port %d (LAG %d)\n", port->actor_port_number, - port->aggregator->aggregator_identifier); + aggregator->aggregator_identifier); __disable_port(port); /* Slave array needs an update */ *update_slave_arr = true; @@ -2379,7 +2389,7 @@ void bond_3ad_unbind_slave(struct slave *slave) */ for (temp_port = aggregator->lag_ports; temp_port; temp_port = temp_port->next_port_in_aggregator) { - temp_port->aggregator = new_aggregator; + rcu_assign_pointer(temp_port->aggregator, new_aggregator); temp_port->actor_port_aggregator_identifier = new_aggregator->aggregator_identifier; } @@ -2848,15 +2858,16 @@ int bond_3ad_set_carrier(struct bonding *bond) int __bond_3ad_get_active_agg_info(struct bonding *bond, struct ad_info *ad_info) { - struct aggregator *aggregator = NULL; + struct aggregator *aggregator = NULL, *tmp; struct list_head *iter; struct slave *slave; struct port *port; bond_for_each_slave_rcu(bond, slave, iter) { port = &(SLAVE_AD_INFO(slave)->port); - if (port->aggregator && port->aggregator->is_active) { - aggregator = port->aggregator; + tmp = rcu_dereference(port->aggregator); + if (tmp && tmp->is_active) { + aggregator = tmp; break; } } diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c index c7baa5c4bf40..af82a3df2c5d 100644 --- a/drivers/net/bonding/bond_main.c +++ b/drivers/net/bonding/bond_main.c @@ -1433,7 +1433,7 @@ static void bond_poll_controller(struct net_device *bond_dev) if (BOND_MODE(bond) == BOND_MODE_8023AD) { struct aggregator *agg = - SLAVE_AD_INFO(slave)->port.aggregator; + rcu_dereference(SLAVE_AD_INFO(slave)->port.aggregator); if (agg && agg->aggregator_identifier != ad_info.aggregator_id) @@ -5179,15 +5179,16 @@ int bond_update_slave_arr(struct bonding *bond, struct slave *skipslave) spin_unlock_bh(&bond->mode_lock); agg_id = ad_info.aggregator_id; } + rcu_read_lock(); bond_for_each_slave(bond, slave, iter) { if (skipslave == slave) continue; all_slaves->arr[all_slaves->count++] = slave; if (BOND_MODE(bond) == BOND_MODE_8023AD) { - struct aggregator *agg; + const struct aggregator *agg; - agg = SLAVE_AD_INFO(slave)->port.aggregator; + agg = rcu_dereference(SLAVE_AD_INFO(slave)->port.aggregator); if (!agg || agg->aggregator_identifier != agg_id) continue; } @@ -5199,6 +5200,7 @@ int bond_update_slave_arr(struct bonding *bond, struct slave *skipslave) usable_slaves->arr[usable_slaves->count++] = slave; } + rcu_read_unlock(); bond_set_slave_arr(bond, usable_slaves, all_slaves); return ret; diff --git a/drivers/net/bonding/bond_netlink.c b/drivers/net/bonding/bond_netlink.c index ea1a80e658ae..c7d3e0602c83 100644 --- a/drivers/net/bonding/bond_netlink.c +++ b/drivers/net/bonding/bond_netlink.c @@ -66,27 +66,29 @@ static int bond_fill_slave_info(struct sk_buff *skb, const struct port *ad_port; ad_port = &SLAVE_AD_INFO(slave)->port; - agg = SLAVE_AD_INFO(slave)->port.aggregator; + rcu_read_lock(); + agg = rcu_dereference(SLAVE_AD_INFO(slave)->port.aggregator); if (agg) { if (nla_put_u16(skb, IFLA_BOND_SLAVE_AD_AGGREGATOR_ID, agg->aggregator_identifier)) - goto nla_put_failure; + goto nla_put_failure_rcu; if (nla_put_u8(skb, IFLA_BOND_SLAVE_AD_ACTOR_OPER_PORT_STATE, ad_port->actor_oper_port_state)) - goto nla_put_failure; + goto nla_put_failure_rcu; if (nla_put_u16(skb, IFLA_BOND_SLAVE_AD_PARTNER_OPER_PORT_STATE, ad_port->partner_oper.port_state)) - goto nla_put_failure; + goto nla_put_failure_rcu; if (nla_put_u8(skb, IFLA_BOND_SLAVE_AD_CHURN_ACTOR_STATE, ad_port->sm_churn_actor_state)) - goto nla_put_failure; + goto nla_put_failure_rcu; if (nla_put_u8(skb, IFLA_BOND_SLAVE_AD_CHURN_PARTNER_STATE, ad_port->sm_churn_partner_state)) - goto nla_put_failure; + goto nla_put_failure_rcu; } + rcu_read_unlock(); if (nla_put_u16(skb, IFLA_BOND_SLAVE_ACTOR_PORT_PRIO, SLAVE_AD_INFO(slave)->port_priority)) @@ -95,6 +97,8 @@ static int bond_fill_slave_info(struct sk_buff *skb, return 0; +nla_put_failure_rcu: + rcu_read_unlock(); nla_put_failure: return -EMSGSIZE; } diff --git a/drivers/net/bonding/bond_procfs.c b/drivers/net/bonding/bond_procfs.c index e34f80305191..3714aab1a3d9 100644 --- a/drivers/net/bonding/bond_procfs.c +++ b/drivers/net/bonding/bond_procfs.c @@ -188,6 +188,7 @@ static void bond_info_show_master(struct seq_file *seq) } } +/* Note: runs under rcu_read_lock() */ static void bond_info_show_slave(struct seq_file *seq, const struct slave *slave) { @@ -214,7 +215,7 @@ static void bond_info_show_slave(struct seq_file *seq, if (BOND_MODE(bond) == BOND_MODE_8023AD) { const struct port *port = &SLAVE_AD_INFO(slave)->port; - const struct aggregator *agg = port->aggregator; + const struct aggregator *agg = rcu_dereference(port->aggregator); if (agg) { seq_printf(seq, "Aggregator ID: %d\n", diff --git a/drivers/net/bonding/bond_sysfs_slave.c b/drivers/net/bonding/bond_sysfs_slave.c index 36d0e8440b5b..fc6fe7181789 100644 --- a/drivers/net/bonding/bond_sysfs_slave.c +++ b/drivers/net/bonding/bond_sysfs_slave.c @@ -62,10 +62,15 @@ static ssize_t ad_aggregator_id_show(struct slave *slave, char *buf) const struct aggregator *agg; if (BOND_MODE(slave->bond) == BOND_MODE_8023AD) { - agg = SLAVE_AD_INFO(slave)->port.aggregator; - if (agg) - return sysfs_emit(buf, "%d\n", - agg->aggregator_identifier); + rcu_read_lock(); + agg = rcu_dereference(SLAVE_AD_INFO(slave)->port.aggregator); + if (agg) { + ssize_t res = sysfs_emit(buf, "%d\n", + agg->aggregator_identifier); + rcu_read_unlock(); + return res; + } + rcu_read_unlock(); } return sysfs_emit(buf, "N/A\n"); @@ -78,7 +83,7 @@ static ssize_t ad_actor_oper_port_state_show(struct slave *slave, char *buf) if (BOND_MODE(slave->bond) == BOND_MODE_8023AD) { ad_port = &SLAVE_AD_INFO(slave)->port; - if (ad_port->aggregator) + if (rcu_access_pointer(ad_port->aggregator)) return sysfs_emit(buf, "%u\n", ad_port->actor_oper_port_state); } @@ -93,7 +98,7 @@ static ssize_t ad_partner_oper_port_state_show(struct slave *slave, char *buf) if (BOND_MODE(slave->bond) == BOND_MODE_8023AD) { ad_port = &SLAVE_AD_INFO(slave)->port; - if (ad_port->aggregator) + if (rcu_access_pointer(ad_port->aggregator)) return sysfs_emit(buf, "%u\n", ad_port->partner_oper.port_state); } diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c index 2bb0a3ff9810..f8b3d53bccad 100644 --- a/drivers/net/ethernet/airoha/airoha_eth.c +++ b/drivers/net/ethernet/airoha/airoha_eth.c @@ -847,13 +847,24 @@ static void airoha_qdma_wake_netdev_txqs(struct airoha_queue *q) { struct airoha_qdma *qdma = q->qdma; struct airoha_eth *eth = qdma->eth; - int i; + int i, qid = q - &qdma->q_tx[0]; for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { struct airoha_gdm_port *port = eth->ports[i]; + int j; - if (port && port->qdma == qdma) - netif_tx_wake_all_queues(port->dev); + if (!port) + continue; + + if (port->qdma != qdma) + continue; + + for (j = 0; j < port->dev->num_tx_queues; j++) { + if (airoha_qdma_get_txq(qdma, j) != qid) + continue; + + netif_wake_subqueue(port->dev, j); + } } q->txq_stopped = false; } @@ -929,10 +940,9 @@ static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget) q->queued--; if (skb) { - u16 queue = skb_get_queue_mapping(skb); struct netdev_queue *txq; - txq = netdev_get_tx_queue(skb->dev, queue); + txq = skb_get_tx_queue(skb->dev, skb); netdev_tx_completed_queue(txq, 1, skb->len); dev_kfree_skb_any(skb); } @@ -1737,14 +1747,11 @@ static int airoha_dev_stop(struct net_device *dev) { struct airoha_gdm_port *port = netdev_priv(dev); struct airoha_qdma *qdma = port->qdma; - int i, err; + int i; netif_tx_disable(dev); - err = airoha_set_vip_for_gdm_port(port, false); - if (err) - return err; - - for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) + airoha_set_vip_for_gdm_port(port, false); + for (i = 0; i < dev->num_tx_queues; i++) netdev_tx_reset_subqueue(dev, i); airoha_set_gdm_port_fwd_cfg(qdma->eth, REG_GDM_FWD_CFG(port->id), @@ -1997,12 +2004,12 @@ static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb, struct netdev_queue *txq; struct airoha_queue *q; LIST_HEAD(tx_list); + int i = 0, qid; void *data; - int i, qid; u16 index; u8 fport; - qid = skb_get_queue_mapping(skb) % ARRAY_SIZE(qdma->q_tx); + qid = airoha_qdma_get_txq(qdma, skb_get_queue_mapping(skb)); tag = airoha_get_dsa_tag(skb, dev); msg0 = FIELD_PREP(QDMA_ETH_TXMSG_CHAN_MASK, @@ -2039,7 +2046,7 @@ static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb, spin_lock_bh(&q->lock); - txq = netdev_get_tx_queue(dev, qid); + txq = skb_get_tx_queue(dev, skb); nr_frags = 1 + skb_shinfo(skb)->nr_frags; if (q->queued + nr_frags >= q->ndesc) { @@ -2057,7 +2064,7 @@ static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb, list); index = e - q->entry; - for (i = 0; i < nr_frags; i++) { + while (true) { struct airoha_qdma_desc *desc = &q->desc[index]; skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; dma_addr_t addr; @@ -2069,7 +2076,7 @@ static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb, goto error_unmap; list_move_tail(&e->list, &tx_list); - e->skb = i ? NULL : skb; + e->skb = i == nr_frags - 1 ? skb : NULL; e->dma_addr = addr; e->dma_len = len; @@ -2088,6 +2095,9 @@ static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb, WRITE_ONCE(desc->msg1, cpu_to_le32(msg1)); WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff)); + if (++i == nr_frags) + break; + data = skb_frag_address(frag); len = skb_frag_size(frag); } @@ -2095,17 +2105,16 @@ static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb, skb_tx_timestamp(skb); netdev_tx_sent_queue(txq, skb->len); + if (q->ndesc - q->queued < q->free_thr) { + netif_tx_stop_queue(txq); + q->txq_stopped = true; + } if (netif_xmit_stopped(txq) || !netdev_xmit_more()) airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, FIELD_PREP(TX_RING_CPU_IDX_MASK, index)); - if (q->ndesc - q->queued < q->free_thr) { - netif_tx_stop_queue(txq); - q->txq_stopped = true; - } - spin_unlock_bh(&q->lock); return NETDEV_TX_OK; diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h index e389d2fe3b86..4fad3acc3ccf 100644 --- a/drivers/net/ethernet/airoha/airoha_eth.h +++ b/drivers/net/ethernet/airoha/airoha_eth.h @@ -631,6 +631,11 @@ u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val); #define airoha_qdma_clear(qdma, offset, val) \ airoha_rmw((qdma)->regs, (offset), (val), 0) +static inline u16 airoha_qdma_get_txq(struct airoha_qdma *qdma, u16 qid) +{ + return qid % ARRAY_SIZE(qdma->q_tx); +} + static inline bool airoha_is_lan_gdm_port(struct airoha_gdm_port *port) { /* GDM1 port on EN7581 SoC is connected to the lan dsa switch. diff --git a/drivers/net/ethernet/ibm/ibmveth.c b/drivers/net/ethernet/ibm/ibmveth.c index 58cc3147afe2..73e051d26b9d 100644 --- a/drivers/net/ethernet/ibm/ibmveth.c +++ b/drivers/net/ethernet/ibm/ibmveth.c @@ -1756,6 +1756,27 @@ static int ibmveth_set_mac_addr(struct net_device *dev, void *p) return 0; } +static netdev_features_t ibmveth_features_check(struct sk_buff *skb, + struct net_device *dev, + netdev_features_t features) +{ + /* Some physical adapters do not support segmentation offload with + * MSS < 224. Disable GSO for such packets to avoid adapter freeze. + * Note: Single-segment packets (gso_segs == 1) don't need this check + * as they bypass the LSO path and are transmitted without segmentation. + */ + if (skb_is_gso(skb)) { + if (skb_shinfo(skb)->gso_size < IBMVETH_MIN_LSO_MSS) { + netdev_warn_once(dev, + "MSS %u too small for LSO, disabling GSO\n", + skb_shinfo(skb)->gso_size); + features &= ~NETIF_F_GSO_MASK; + } + } + + return vlan_features_check(skb, features); +} + static const struct net_device_ops ibmveth_netdev_ops = { .ndo_open = ibmveth_open, .ndo_stop = ibmveth_close, @@ -1767,6 +1788,7 @@ static const struct net_device_ops ibmveth_netdev_ops = { .ndo_set_features = ibmveth_set_features, .ndo_validate_addr = eth_validate_addr, .ndo_set_mac_address = ibmveth_set_mac_addr, + .ndo_features_check = ibmveth_features_check, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = ibmveth_poll_controller, #endif diff --git a/drivers/net/ethernet/ibm/ibmveth.h b/drivers/net/ethernet/ibm/ibmveth.h index 068f99df133e..d87713668ed3 100644 --- a/drivers/net/ethernet/ibm/ibmveth.h +++ b/drivers/net/ethernet/ibm/ibmveth.h @@ -37,6 +37,7 @@ #define IBMVETH_ILLAN_IPV4_TCP_CSUM 0x0000000000000002UL #define IBMVETH_ILLAN_ACTIVE_TRUNK 0x0000000000000001UL +#define IBMVETH_MIN_LSO_MSS 224 /* Minimum MSS for LSO */ /* hcall macros */ #define h_register_logical_lan(ua, buflst, rxq, fltlst, mac) \ plpar_hcall_norets(H_REGISTER_LOGICAL_LAN, ua, buflst, rxq, fltlst, mac) diff --git a/drivers/net/ethernet/intel/iavf/iavf.h b/drivers/net/ethernet/intel/iavf/iavf.h index e9fb0a0919e3..050f8241ef5e 100644 --- a/drivers/net/ethernet/intel/iavf/iavf.h +++ b/drivers/net/ethernet/intel/iavf/iavf.h @@ -158,11 +158,10 @@ struct iavf_vlan { enum iavf_vlan_state_t { IAVF_VLAN_INVALID, IAVF_VLAN_ADD, /* filter needs to be added */ - IAVF_VLAN_IS_NEW, /* filter is new, wait for PF answer */ - IAVF_VLAN_ACTIVE, /* filter is accepted by PF */ - IAVF_VLAN_DISABLE, /* filter needs to be deleted by PF, then marked INACTIVE */ - IAVF_VLAN_INACTIVE, /* filter is inactive, we are in IFF_DOWN */ - IAVF_VLAN_REMOVE, /* filter needs to be removed from list */ + IAVF_VLAN_ADDING, /* ADD sent to PF, waiting for response */ + IAVF_VLAN_ACTIVE, /* PF confirmed, filter is in HW */ + IAVF_VLAN_REMOVE, /* filter queued for DEL from PF */ + IAVF_VLAN_REMOVING, /* DEL sent to PF, waiting for response */ }; struct iavf_vlan_filter { diff --git a/drivers/net/ethernet/intel/iavf/iavf_main.c b/drivers/net/ethernet/intel/iavf/iavf_main.c index 3c1465cf0515..d2914c511e1e 100644 --- a/drivers/net/ethernet/intel/iavf/iavf_main.c +++ b/drivers/net/ethernet/intel/iavf/iavf_main.c @@ -757,10 +757,10 @@ iavf_vlan_filter *iavf_add_vlan(struct iavf_adapter *adapter, adapter->num_vlan_filters++; iavf_schedule_aq_request(adapter, IAVF_FLAG_AQ_ADD_VLAN_FILTER); } else if (f->state == IAVF_VLAN_REMOVE) { - /* Re-add the filter since we cannot tell whether the - * pending delete has already been processed by the PF. - * A duplicate add is harmless. - */ + /* DEL not yet sent to PF, cancel it */ + f->state = IAVF_VLAN_ACTIVE; + } else if (f->state == IAVF_VLAN_REMOVING) { + /* DEL already sent to PF, re-add after completion */ f->state = IAVF_VLAN_ADD; iavf_schedule_aq_request(adapter, IAVF_FLAG_AQ_ADD_VLAN_FILTER); @@ -791,37 +791,19 @@ static void iavf_del_vlan(struct iavf_adapter *adapter, struct iavf_vlan vlan) list_del(&f->list); kfree(f); adapter->num_vlan_filters--; - } else { + } else if (f->state != IAVF_VLAN_REMOVING) { f->state = IAVF_VLAN_REMOVE; iavf_schedule_aq_request(adapter, IAVF_FLAG_AQ_DEL_VLAN_FILTER); } + /* If REMOVING, DEL is already sent to PF; completion + * handler will free the filter when PF confirms. + */ } spin_unlock_bh(&adapter->mac_vlan_list_lock); } -/** - * iavf_restore_filters - * @adapter: board private structure - * - * Restore existing non MAC filters when VF netdev comes back up - **/ -static void iavf_restore_filters(struct iavf_adapter *adapter) -{ - struct iavf_vlan_filter *f; - - /* re-add all VLAN filters */ - spin_lock_bh(&adapter->mac_vlan_list_lock); - - list_for_each_entry(f, &adapter->vlan_filter_list, list) { - if (f->state == IAVF_VLAN_INACTIVE) - f->state = IAVF_VLAN_ADD; - } - - spin_unlock_bh(&adapter->mac_vlan_list_lock); - adapter->aq_required |= IAVF_FLAG_AQ_ADD_VLAN_FILTER; -} /** * iavf_get_num_vlans_added - get number of VLANs added @@ -1246,13 +1228,12 @@ static void iavf_up_complete(struct iavf_adapter *adapter) } /** - * iavf_clear_mac_vlan_filters - Remove mac and vlan filters not sent to PF - * yet and mark other to be removed. + * iavf_clear_mac_filters - Remove MAC filters not sent to PF yet and mark + * others to be removed. * @adapter: board private structure **/ -static void iavf_clear_mac_vlan_filters(struct iavf_adapter *adapter) +static void iavf_clear_mac_filters(struct iavf_adapter *adapter) { - struct iavf_vlan_filter *vlf, *vlftmp; struct iavf_mac_filter *f, *ftmp; spin_lock_bh(&adapter->mac_vlan_list_lock); @@ -1271,11 +1252,6 @@ static void iavf_clear_mac_vlan_filters(struct iavf_adapter *adapter) } } - /* disable all VLAN filters */ - list_for_each_entry_safe(vlf, vlftmp, &adapter->vlan_filter_list, - list) - vlf->state = IAVF_VLAN_DISABLE; - spin_unlock_bh(&adapter->mac_vlan_list_lock); } @@ -1371,7 +1347,7 @@ void iavf_down(struct iavf_adapter *adapter) iavf_napi_disable_all(adapter); iavf_irq_disable(adapter); - iavf_clear_mac_vlan_filters(adapter); + iavf_clear_mac_filters(adapter); iavf_clear_cloud_filters(adapter); iavf_clear_fdir_filters(adapter); iavf_clear_adv_rss_conf(adapter); @@ -1388,8 +1364,6 @@ void iavf_down(struct iavf_adapter *adapter) */ if (!list_empty(&adapter->mac_filter_list)) adapter->aq_required |= IAVF_FLAG_AQ_DEL_MAC_FILTER; - if (!list_empty(&adapter->vlan_filter_list)) - adapter->aq_required |= IAVF_FLAG_AQ_DEL_VLAN_FILTER; if (!list_empty(&adapter->cloud_filter_list)) adapter->aq_required |= IAVF_FLAG_AQ_DEL_CLOUD_FILTER; if (!list_empty(&adapter->fdir_list_head)) @@ -4494,8 +4468,6 @@ static int iavf_open(struct net_device *netdev) iavf_add_filter(adapter, adapter->hw.mac.addr); spin_unlock_bh(&adapter->mac_vlan_list_lock); - /* Restore filters that were removed with IFF_DOWN */ - iavf_restore_filters(adapter); iavf_restore_fdir_filters(adapter); iavf_configure(adapter); diff --git a/drivers/net/ethernet/intel/iavf/iavf_virtchnl.c b/drivers/net/ethernet/intel/iavf/iavf_virtchnl.c index a52c100dcbc5..4f2defd2331b 100644 --- a/drivers/net/ethernet/intel/iavf/iavf_virtchnl.c +++ b/drivers/net/ethernet/intel/iavf/iavf_virtchnl.c @@ -746,7 +746,7 @@ static void iavf_vlan_add_reject(struct iavf_adapter *adapter) spin_lock_bh(&adapter->mac_vlan_list_lock); list_for_each_entry_safe(f, ftmp, &adapter->vlan_filter_list, list) { - if (f->state == IAVF_VLAN_IS_NEW) { + if (f->state == IAVF_VLAN_ADDING) { list_del(&f->list); kfree(f); adapter->num_vlan_filters--; @@ -812,7 +812,7 @@ void iavf_add_vlans(struct iavf_adapter *adapter) if (f->state == IAVF_VLAN_ADD) { vvfl->vlan_id[i] = f->vlan.vid; i++; - f->state = IAVF_VLAN_IS_NEW; + f->state = IAVF_VLAN_ADDING; if (i == count) break; } @@ -874,7 +874,7 @@ void iavf_add_vlans(struct iavf_adapter *adapter) vlan->tpid = f->vlan.tpid; i++; - f->state = IAVF_VLAN_IS_NEW; + f->state = IAVF_VLAN_ADDING; } } @@ -911,22 +911,12 @@ void iavf_del_vlans(struct iavf_adapter *adapter) spin_lock_bh(&adapter->mac_vlan_list_lock); list_for_each_entry_safe(f, ftmp, &adapter->vlan_filter_list, list) { - /* since VLAN capabilities are not allowed, we dont want to send - * a VLAN delete request because it will most likely fail and - * create unnecessary errors/noise, so just free the VLAN - * filters marked for removal to enable bailing out before - * sending a virtchnl message - */ if (f->state == IAVF_VLAN_REMOVE && !VLAN_FILTERING_ALLOWED(adapter)) { list_del(&f->list); kfree(f); adapter->num_vlan_filters--; - } else if (f->state == IAVF_VLAN_DISABLE && - !VLAN_FILTERING_ALLOWED(adapter)) { - f->state = IAVF_VLAN_INACTIVE; - } else if (f->state == IAVF_VLAN_REMOVE || - f->state == IAVF_VLAN_DISABLE) { + } else if (f->state == IAVF_VLAN_REMOVE) { count++; } } @@ -958,18 +948,10 @@ void iavf_del_vlans(struct iavf_adapter *adapter) vvfl->vsi_id = adapter->vsi_res->vsi_id; vvfl->num_elements = count; - list_for_each_entry_safe(f, ftmp, &adapter->vlan_filter_list, list) { - if (f->state == IAVF_VLAN_DISABLE) { + list_for_each_entry(f, &adapter->vlan_filter_list, list) { + if (f->state == IAVF_VLAN_REMOVE) { vvfl->vlan_id[i] = f->vlan.vid; - f->state = IAVF_VLAN_INACTIVE; - i++; - if (i == count) - break; - } else if (f->state == IAVF_VLAN_REMOVE) { - vvfl->vlan_id[i] = f->vlan.vid; - list_del(&f->list); - kfree(f); - adapter->num_vlan_filters--; + f->state = IAVF_VLAN_REMOVING; i++; if (i == count) break; @@ -1006,9 +988,8 @@ void iavf_del_vlans(struct iavf_adapter *adapter) vvfl_v2->vport_id = adapter->vsi_res->vsi_id; vvfl_v2->num_elements = count; - list_for_each_entry_safe(f, ftmp, &adapter->vlan_filter_list, list) { - if (f->state == IAVF_VLAN_DISABLE || - f->state == IAVF_VLAN_REMOVE) { + list_for_each_entry(f, &adapter->vlan_filter_list, list) { + if (f->state == IAVF_VLAN_REMOVE) { struct virtchnl_vlan_supported_caps *filtering_support = &adapter->vlan_v2_caps.filtering.filtering_support; struct virtchnl_vlan *vlan; @@ -1022,13 +1003,7 @@ void iavf_del_vlans(struct iavf_adapter *adapter) vlan->tci = f->vlan.vid; vlan->tpid = f->vlan.tpid; - if (f->state == IAVF_VLAN_DISABLE) { - f->state = IAVF_VLAN_INACTIVE; - } else { - list_del(&f->list); - kfree(f); - adapter->num_vlan_filters--; - } + f->state = IAVF_VLAN_REMOVING; i++; if (i == count) break; @@ -2391,10 +2366,6 @@ void iavf_virtchnl_completion(struct iavf_adapter *adapter, ether_addr_copy(adapter->hw.mac.addr, netdev->dev_addr); wake_up(&adapter->vc_waitqueue); break; - case VIRTCHNL_OP_DEL_VLAN: - dev_err(&adapter->pdev->dev, "Failed to delete VLAN filter, error %s\n", - iavf_stat_str(&adapter->hw, v_retval)); - break; case VIRTCHNL_OP_DEL_ETH_ADDR: dev_err(&adapter->pdev->dev, "Failed to delete MAC filter, error %s\n", iavf_stat_str(&adapter->hw, v_retval)); @@ -2905,17 +2876,42 @@ void iavf_virtchnl_completion(struct iavf_adapter *adapter, spin_unlock_bh(&adapter->adv_rss_lock); } break; + case VIRTCHNL_OP_ADD_VLAN: case VIRTCHNL_OP_ADD_VLAN_V2: { struct iavf_vlan_filter *f; + if (v_retval) + break; + spin_lock_bh(&adapter->mac_vlan_list_lock); list_for_each_entry(f, &adapter->vlan_filter_list, list) { - if (f->state == IAVF_VLAN_IS_NEW) + if (f->state == IAVF_VLAN_ADDING) f->state = IAVF_VLAN_ACTIVE; } spin_unlock_bh(&adapter->mac_vlan_list_lock); } break; + case VIRTCHNL_OP_DEL_VLAN: + case VIRTCHNL_OP_DEL_VLAN_V2: { + struct iavf_vlan_filter *f, *ftmp; + + spin_lock_bh(&adapter->mac_vlan_list_lock); + list_for_each_entry_safe(f, ftmp, &adapter->vlan_filter_list, + list) { + if (f->state == IAVF_VLAN_REMOVING) { + if (v_retval) { + /* PF rejected DEL, keep filter */ + f->state = IAVF_VLAN_ACTIVE; + } else { + list_del(&f->list); + kfree(f); + adapter->num_vlan_filters--; + } + } + } + spin_unlock_bh(&adapter->mac_vlan_list_lock); + } + break; case VIRTCHNL_OP_ENABLE_VLAN_STRIPPING: /* PF enabled vlan strip on this VF. * Update netdev->features if needed to be in sync with ethtool. diff --git a/drivers/net/ethernet/intel/ice/devlink/devlink.c b/drivers/net/ethernet/intel/ice/devlink/devlink.c index 6144cee8034d..641d6e289d5c 100644 --- a/drivers/net/ethernet/intel/ice/devlink/devlink.c +++ b/drivers/net/ethernet/intel/ice/devlink/devlink.c @@ -1245,6 +1245,8 @@ static int ice_devlink_reinit_up(struct ice_pf *pf) return err; } + ice_init_dev_hw(pf); + /* load MSI-X values */ ice_set_min_max_msix(pf); diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c index ce11fea122d0..b617a6bff891 100644 --- a/drivers/net/ethernet/intel/ice/ice_common.c +++ b/drivers/net/ethernet/intel/ice/ice_common.c @@ -1126,8 +1126,6 @@ int ice_init_hw(struct ice_hw *hw) if (status) goto err_unroll_fltr_mgmt_struct; - ice_init_dev_hw(hw->back); - mutex_init(&hw->tnl_lock); ice_init_chk_recipe_reuse_support(hw); diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c index 62f75701d652..27b460926bac 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -1154,6 +1154,32 @@ ice_dpll_input_state_get(const struct dpll_pin *pin, void *pin_priv, extack, ICE_DPLL_PIN_TYPE_INPUT); } +/** + * ice_dpll_sw_pin_notify_peer - notify the paired SW pin after a state change + * @d: pointer to dplls struct + * @changed: the SW pin that was explicitly changed (already notified by dpll core) + * + * SMA and U.FL pins share physical signal paths in pairs (SMA1/U.FL1 and + * SMA2/U.FL2). When one pin's routing changes via the PCA9575 GPIO + * expander, the paired pin's state may also change. Send a change + * notification for the peer pin so userspace consumers monitoring the + * peer via dpll netlink learn about the update. + * + * Context: Called from dpll_pin_ops callbacks after pf->dplls.lock is + * released. Uses __dpll_pin_change_ntf() because dpll_lock is + * still held by the dpll netlink layer. + */ +static void ice_dpll_sw_pin_notify_peer(struct ice_dplls *d, + struct ice_dpll_pin *changed) +{ + struct ice_dpll_pin *peer; + + peer = (changed >= d->sma && changed < d->sma + ICE_DPLL_PIN_SW_NUM) ? + &d->ufl[changed->idx] : &d->sma[changed->idx]; + if (peer->pin) + __dpll_pin_change_ntf(peer->pin); +} + /** * ice_dpll_sma_direction_set - set direction of SMA pin * @p: pointer to a pin @@ -1171,6 +1197,8 @@ static int ice_dpll_sma_direction_set(struct ice_dpll_pin *p, enum dpll_pin_direction direction, struct netlink_ext_ack *extack) { + struct ice_dplls *d = &p->pf->dplls; + struct ice_dpll_pin *peer; u8 data; int ret; @@ -1189,8 +1217,9 @@ static int ice_dpll_sma_direction_set(struct ice_dpll_pin *p, case ICE_DPLL_PIN_SW_2_IDX: if (direction == DPLL_PIN_DIRECTION_INPUT) { data &= ~ICE_SMA2_DIR_EN; + data |= ICE_SMA2_UFL2_RX_DIS; } else { - data &= ~ICE_SMA2_TX_EN; + data &= ~(ICE_SMA2_TX_EN | ICE_SMA2_UFL2_RX_DIS); data |= ICE_SMA2_DIR_EN; } break; @@ -1202,6 +1231,34 @@ static int ice_dpll_sma_direction_set(struct ice_dpll_pin *p, ret = ice_dpll_pin_state_update(p->pf, p, ICE_DPLL_PIN_TYPE_SOFTWARE, extack); + if (ret) + return ret; + + /* When a direction change activates the paired U.FL pin, enable + * its backing CGU pin so the pin reports as connected. Without + * this the U.FL routing is correct but the CGU pin stays disabled + * and userspace sees the pin as disconnected. Do not disable the + * backing pin when U.FL becomes inactive because the SMA pin may + * still be using it. + */ + peer = &d->ufl[p->idx]; + if (peer->active) { + struct ice_dpll_pin *target; + enum ice_dpll_pin_type type; + + if (peer->output) { + target = peer->output; + type = ICE_DPLL_PIN_TYPE_OUTPUT; + } else { + target = peer->input; + type = ICE_DPLL_PIN_TYPE_INPUT; + } + ret = ice_dpll_pin_enable(&p->pf->hw, target, + d->eec.dpll_idx, type, extack); + if (!ret) + ret = ice_dpll_pin_state_update(p->pf, target, + type, extack); + } return ret; } @@ -1253,6 +1310,14 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv, data &= ~ICE_SMA1_MASK; enable = true; } else if (state == DPLL_PIN_STATE_DISCONNECTED) { + /* Skip if U.FL1 is not active, setting TX_EN + * while DIR_EN is set would also deactivate + * the paired SMA1 output. + */ + if (data & (ICE_SMA1_DIR_EN | ICE_SMA1_TX_EN)) { + ret = 0; + goto unlock; + } data |= ICE_SMA1_TX_EN; enable = false; } else { @@ -1267,6 +1332,15 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv, data &= ~ICE_SMA2_UFL2_RX_DIS; enable = true; } else if (state == DPLL_PIN_STATE_DISCONNECTED) { + /* Skip if U.FL2 is not active, setting + * UFL2_RX_DIS could also disable the paired + * SMA2 input. + */ + if (!(data & ICE_SMA2_DIR_EN) || + (data & ICE_SMA2_UFL2_RX_DIS)) { + ret = 0; + goto unlock; + } data |= ICE_SMA2_UFL2_RX_DIS; enable = false; } else { @@ -1296,6 +1370,8 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv, unlock: mutex_unlock(&pf->dplls.lock); + if (!ret) + ice_dpll_sw_pin_notify_peer(&pf->dplls, p); return ret; } @@ -1414,6 +1490,8 @@ ice_dpll_sma_pin_state_set(const struct dpll_pin *pin, void *pin_priv, unlock: mutex_unlock(&pf->dplls.lock); + if (!ret) + ice_dpll_sw_pin_notify_peer(&pf->dplls, sma); return ret; } @@ -1609,6 +1687,8 @@ ice_dpll_pin_sma_direction_set(const struct dpll_pin *pin, void *pin_priv, mutex_lock(&pf->dplls.lock); ret = ice_dpll_sma_direction_set(p, direction, extack); mutex_unlock(&pf->dplls.lock); + if (!ret) + ice_dpll_sw_pin_notify_peer(&pf->dplls, p); return ret; } @@ -1915,7 +1995,10 @@ ice_dpll_phase_offset_get(const struct dpll_pin *pin, void *pin_priv, d->active_input == p->input->pin)) *phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR; else if (d->phase_offset_monitor_period) - *phase_offset = p->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR; + *phase_offset = (p->input && + p->direction == DPLL_PIN_DIRECTION_INPUT ? + p->input->phase_offset : + p->phase_offset) * ICE_DPLL_PHASE_OFFSET_FACTOR; else *phase_offset = 0; mutex_unlock(&pf->dplls.lock); @@ -2609,6 +2692,27 @@ static u64 ice_generate_clock_id(struct ice_pf *pf) return pci_get_dsn(pf->pdev); } +/** + * ice_dpll_pin_ntf - notify pin change including any SW pin wrappers + * @dplls: pointer to dplls struct + * @pin: the dpll_pin that changed + * + * Send a change notification for @pin and for any registered SMA/U.FL pin + * whose backing CGU input matches @pin. + */ +static void ice_dpll_pin_ntf(struct ice_dplls *dplls, struct dpll_pin *pin) +{ + dpll_pin_change_ntf(pin); + for (int i = 0; i < ICE_DPLL_PIN_SW_NUM; i++) { + if (dplls->sma[i].pin && dplls->sma[i].input && + dplls->sma[i].input->pin == pin) + dpll_pin_change_ntf(dplls->sma[i].pin); + if (dplls->ufl[i].pin && dplls->ufl[i].input && + dplls->ufl[i].input->pin == pin) + dpll_pin_change_ntf(dplls->ufl[i].pin); + } +} + /** * ice_dpll_notify_changes - notify dpll subsystem about changes * @d: pointer do dpll @@ -2617,6 +2721,7 @@ static u64 ice_generate_clock_id(struct ice_pf *pf) */ static void ice_dpll_notify_changes(struct ice_dpll *d) { + struct ice_dplls *dplls = &d->pf->dplls; bool pin_notified = false; if (d->prev_dpll_state != d->dpll_state) { @@ -2625,17 +2730,17 @@ static void ice_dpll_notify_changes(struct ice_dpll *d) } if (d->prev_input != d->active_input) { if (d->prev_input) - dpll_pin_change_ntf(d->prev_input); + ice_dpll_pin_ntf(dplls, d->prev_input); d->prev_input = d->active_input; if (d->active_input) { - dpll_pin_change_ntf(d->active_input); + ice_dpll_pin_ntf(dplls, d->active_input); pin_notified = true; } } if (d->prev_phase_offset != d->phase_offset) { d->prev_phase_offset = d->phase_offset; if (!pin_notified && d->active_input) - dpll_pin_change_ntf(d->active_input); + ice_dpll_pin_ntf(dplls, d->active_input); } } @@ -2664,6 +2769,7 @@ static bool ice_dpll_is_pps_phase_monitor(struct ice_pf *pf) /** * ice_dpll_pins_notify_mask - notify dpll subsystem about bulk pin changes + * @dplls: pointer to dplls struct * @pins: array of ice_dpll_pin pointers registered within dpll subsystem * @pin_num: number of pins * @phase_offset_ntf_mask: bitmask of pin indexes to notify @@ -2673,15 +2779,14 @@ static bool ice_dpll_is_pps_phase_monitor(struct ice_pf *pf) * * Context: Must be called while pf->dplls.lock is released. */ -static void ice_dpll_pins_notify_mask(struct ice_dpll_pin *pins, +static void ice_dpll_pins_notify_mask(struct ice_dplls *dplls, + struct ice_dpll_pin *pins, u8 pin_num, u32 phase_offset_ntf_mask) { - int i = 0; - - for (i = 0; i < pin_num; i++) - if (phase_offset_ntf_mask & (1 << i)) - dpll_pin_change_ntf(pins[i].pin); + for (int i = 0; i < pin_num; i++) + if (phase_offset_ntf_mask & BIT(i)) + ice_dpll_pin_ntf(dplls, pins[i].pin); } /** @@ -2857,7 +2962,7 @@ static void ice_dpll_periodic_work(struct kthread_work *work) ice_dpll_notify_changes(de); ice_dpll_notify_changes(dp); if (phase_offset_ntf) - ice_dpll_pins_notify_mask(d->inputs, d->num_inputs, + ice_dpll_pins_notify_mask(d, d->inputs, d->num_inputs, phase_offset_ntf); resched: @@ -4014,6 +4119,7 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) struct ice_dpll_pin *pin; u32 phase_adj_max, caps; int i, ret; + u8 data; if (pf->hw.device_id == ICE_DEV_ID_E810C_QSFP) input_idx_offset = ICE_E810_RCLK_PINS_NUM; @@ -4073,6 +4179,22 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) } ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max); } + + /* Initialize the SMA control register to a known-good default state. + * Without this write the PCA9575 GPIO expander retains its power-on + * default (all outputs high) which makes all SW pins appear inactive. + * Set SMA1 and SMA2 as active inputs, disable U.FL1 output and + * U.FL2 input. + */ + ret = ice_read_sma_ctrl(&pf->hw, &data); + if (ret) + return ret; + data &= ~ICE_ALL_SMA_MASK; + data |= ICE_SMA1_TX_EN | ICE_SMA2_TX_EN | ICE_SMA2_UFL2_RX_DIS; + ret = ice_write_sma_ctrl(&pf->hw, data); + if (ret) + return ret; + ret = ice_dpll_pin_state_update(pf, pin, ICE_DPLL_PIN_TYPE_SOFTWARE, NULL); if (ret) diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c index 5f92377d4dfc..1d1947a7fe11 100644 --- a/drivers/net/ethernet/intel/ice/ice_main.c +++ b/drivers/net/ethernet/intel/ice/ice_main.c @@ -5245,6 +5245,8 @@ ice_probe(struct pci_dev *pdev, const struct pci_device_id __always_unused *ent) return err; } + ice_init_dev_hw(pf); + adapter = ice_adapter_get(pdev); if (IS_ERR(adapter)) { err = PTR_ERR(adapter); diff --git a/drivers/net/ethernet/intel/ice/ice_vf_lib.c b/drivers/net/ethernet/intel/ice/ice_vf_lib.c index 772f6b07340d..b1f46707dcc0 100644 --- a/drivers/net/ethernet/intel/ice/ice_vf_lib.c +++ b/drivers/net/ethernet/intel/ice/ice_vf_lib.c @@ -804,7 +804,12 @@ void ice_reset_all_vfs(struct ice_pf *pf) ice_vf_ctrl_invalidate_vsi(vf); ice_vf_pre_vsi_rebuild(vf); - ice_vf_rebuild_vsi(vf); + if (ice_vf_rebuild_vsi(vf)) { + dev_err(dev, "VF %u VSI rebuild failed, leaving VF disabled\n", + vf->vf_id); + mutex_unlock(&vf->cfg_lock); + continue; + } ice_vf_post_vsi_rebuild(vf); ice_eswitch_attach_vf(pf, vf); diff --git a/drivers/net/ethernet/sfc/efx_devlink.c b/drivers/net/ethernet/sfc/efx_devlink.c index d842c60dfc10..e5c6f81af48b 100644 --- a/drivers/net/ethernet/sfc/efx_devlink.c +++ b/drivers/net/ethernet/sfc/efx_devlink.c @@ -531,7 +531,7 @@ static int efx_devlink_info_running_versions(struct efx_nic *efx, if (rc || outlength < MC_CMD_GET_VERSION_OUT_LEN) { netif_err(efx, drv, efx->net_dev, "mcdi MC_CMD_GET_VERSION failed\n"); - return rc; + return rc ?: -EIO; } /* Handle previous output */ diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index ca68248dbc78..3591755ea30b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -5549,9 +5549,12 @@ static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) break; /* Prefetch the next RX descriptor */ - rx_q->cur_rx = STMMAC_NEXT_ENTRY(rx_q->cur_rx, - priv->dma_conf.dma_rx_size); - next_entry = rx_q->cur_rx; + next_entry = STMMAC_NEXT_ENTRY(rx_q->cur_rx, + priv->dma_conf.dma_rx_size); + if (unlikely(next_entry == rx_q->dirty_rx)) + break; + + rx_q->cur_rx = next_entry; np = stmmac_get_rx_desc(priv, rx_q, next_entry); @@ -5686,7 +5689,6 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) dma_dir = page_pool_get_dma_dir(rx_q->page_pool); bufsz = DIV_ROUND_UP(priv->dma_conf.dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; - limit = min(priv->dma_conf.dma_rx_size - 1, (unsigned int)limit); if (netif_msg_rx_status(priv)) { void *rx_head = stmmac_get_rx_desc(priv, rx_q, 0); @@ -5733,9 +5735,12 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) if (unlikely(status & dma_own)) break; - rx_q->cur_rx = STMMAC_NEXT_ENTRY(rx_q->cur_rx, - priv->dma_conf.dma_rx_size); - next_entry = rx_q->cur_rx; + next_entry = STMMAC_NEXT_ENTRY(rx_q->cur_rx, + priv->dma_conf.dma_rx_size); + if (unlikely(next_entry == rx_q->dirty_rx)) + break; + + rx_q->cur_rx = next_entry; np = stmmac_get_rx_desc(priv, rx_q, next_entry); diff --git a/drivers/net/mctp/mctp-i2c.c b/drivers/net/mctp/mctp-i2c.c index 15fe4d1163c1..ee2913758e54 100644 --- a/drivers/net/mctp/mctp-i2c.c +++ b/drivers/net/mctp/mctp-i2c.c @@ -496,8 +496,6 @@ static void mctp_i2c_xmit(struct mctp_i2c_dev *midev, struct sk_buff *skb) u8 *pecp; int rc; - fs = mctp_i2c_get_tx_flow_state(midev, skb); - hdr = (void *)skb_mac_header(skb); /* Sanity check that packet contents matches skb length, * and can't exceed MCTP_I2C_BUFSZ @@ -509,6 +507,8 @@ static void mctp_i2c_xmit(struct mctp_i2c_dev *midev, struct sk_buff *skb) return; } + fs = mctp_i2c_get_tx_flow_state(midev, skb); + if (skb_tailroom(skb) >= 1) { /* Linear case with space, we can just append the PEC */ skb_put(skb, 1); diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index 205384dab89a..57dd6821a8aa 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c @@ -752,7 +752,7 @@ static ssize_t enabled_store(struct config_item *item, unregister_netcons_consoles(); } - ret = strnlen(buf, count); + ret = count; /* Deferred cleanup */ netconsole_process_cleanups(); out_unlock: @@ -781,7 +781,7 @@ static ssize_t release_store(struct config_item *item, const char *buf, nt->release = release; - ret = strnlen(buf, count); + ret = count; out_unlock: dynamic_netconsole_mutex_unlock(); return ret; @@ -807,7 +807,7 @@ static ssize_t extended_store(struct config_item *item, const char *buf, goto out_unlock; nt->extended = extended; - ret = strnlen(buf, count); + ret = count; out_unlock: dynamic_netconsole_mutex_unlock(); return ret; @@ -817,6 +817,13 @@ static ssize_t dev_name_store(struct config_item *item, const char *buf, size_t count) { struct netconsole_target *nt = to_target(item); + size_t len = count; + + /* Account for a trailing newline appended by tools like echo */ + if (len && buf[len - 1] == '\n') + len--; + if (len >= IFNAMSIZ) + return -ENAMETOOLONG; dynamic_netconsole_mutex_lock(); if (nt->state == STATE_ENABLED) { @@ -830,7 +837,7 @@ static ssize_t dev_name_store(struct config_item *item, const char *buf, trim_newline(nt->np.dev_name, IFNAMSIZ); dynamic_netconsole_mutex_unlock(); - return strnlen(buf, count); + return count; } static ssize_t local_port_store(struct config_item *item, const char *buf, @@ -849,7 +856,7 @@ static ssize_t local_port_store(struct config_item *item, const char *buf, ret = kstrtou16(buf, 10, &nt->np.local_port); if (ret < 0) goto out_unlock; - ret = strnlen(buf, count); + ret = count; out_unlock: dynamic_netconsole_mutex_unlock(); return ret; @@ -871,7 +878,7 @@ static ssize_t remote_port_store(struct config_item *item, ret = kstrtou16(buf, 10, &nt->np.remote_port); if (ret < 0) goto out_unlock; - ret = strnlen(buf, count); + ret = count; out_unlock: dynamic_netconsole_mutex_unlock(); return ret; @@ -896,7 +903,7 @@ static ssize_t local_ip_store(struct config_item *item, const char *buf, goto out_unlock; nt->np.ipv6 = !!ipv6; - ret = strnlen(buf, count); + ret = count; out_unlock: dynamic_netconsole_mutex_unlock(); return ret; @@ -921,7 +928,7 @@ static ssize_t remote_ip_store(struct config_item *item, const char *buf, goto out_unlock; nt->np.ipv6 = !!ipv6; - ret = strnlen(buf, count); + ret = count; out_unlock: dynamic_netconsole_mutex_unlock(); return ret; @@ -957,7 +964,7 @@ static ssize_t remote_mac_store(struct config_item *item, const char *buf, goto out_unlock; memcpy(nt->np.remote_mac, remote_mac, ETH_ALEN); - ret = strnlen(buf, count); + ret = count; out_unlock: dynamic_netconsole_mutex_unlock(); return ret; @@ -1072,26 +1079,30 @@ static ssize_t userdatum_value_store(struct config_item *item, const char *buf, size_t count) { struct userdatum *udm = to_userdatum(item); + char old_value[MAX_EXTRADATA_VALUE_LEN]; struct netconsole_target *nt; struct userdata *ud; ssize_t ret; - if (count > MAX_EXTRADATA_VALUE_LEN) + if (count >= MAX_EXTRADATA_VALUE_LEN) return -EMSGSIZE; mutex_lock(&netconsole_subsys.su_mutex); dynamic_netconsole_mutex_lock(); - - ret = strscpy(udm->value, buf, sizeof(udm->value)); - if (ret < 0) - goto out_unlock; + /* Snapshot for rollback if update_userdata() fails below */ + strscpy(old_value, udm->value, sizeof(old_value)); + /* count is bounded above, so strscpy() cannot truncate here */ + strscpy(udm->value, buf, sizeof(udm->value)); trim_newline(udm->value, sizeof(udm->value)); ud = to_userdata(item->ci_parent); nt = userdata_to_target(ud); ret = update_userdata(nt); - if (ret < 0) + if (ret < 0) { + /* Restore the previous value so it matches the live payload */ + strscpy(udm->value, old_value, sizeof(udm->value)); goto out_unlock; + } ret = count; out_unlock: dynamic_netconsole_mutex_unlock(); @@ -1133,7 +1144,7 @@ static ssize_t sysdata_msgid_enabled_store(struct config_item *item, disable_sysdata_feature(nt, SYSDATA_MSGID); unlock_ok: - ret = strnlen(buf, count); + ret = count; dynamic_netconsole_mutex_unlock(); mutex_unlock(&netconsole_subsys.su_mutex); return ret; @@ -1162,7 +1173,7 @@ static ssize_t sysdata_release_enabled_store(struct config_item *item, disable_sysdata_feature(nt, SYSDATA_RELEASE); unlock_ok: - ret = strnlen(buf, count); + ret = count; dynamic_netconsole_mutex_unlock(); mutex_unlock(&netconsole_subsys.su_mutex); return ret; @@ -1191,7 +1202,7 @@ static ssize_t sysdata_taskname_enabled_store(struct config_item *item, disable_sysdata_feature(nt, SYSDATA_TASKNAME); unlock_ok: - ret = strnlen(buf, count); + ret = count; dynamic_netconsole_mutex_unlock(); mutex_unlock(&netconsole_subsys.su_mutex); return ret; @@ -1225,7 +1236,7 @@ static ssize_t sysdata_cpu_nr_enabled_store(struct config_item *item, disable_sysdata_feature(nt, SYSDATA_CPU_NR); unlock_ok: - ret = strnlen(buf, count); + ret = count; dynamic_netconsole_mutex_unlock(); mutex_unlock(&netconsole_subsys.su_mutex); return ret; diff --git a/drivers/net/netdevsim/dev.c b/drivers/net/netdevsim/dev.c index 1e06e781c835..f00fc2f9ebde 100644 --- a/drivers/net/netdevsim/dev.c +++ b/drivers/net/netdevsim/dev.c @@ -829,7 +829,7 @@ static struct sk_buff *nsim_dev_trap_skb_build(void) skb->protocol = htons(ETH_P_IP); skb_set_network_header(skb, skb->len); - iph = skb_put(skb, sizeof(struct iphdr)); + iph = skb_put_zero(skb, sizeof(struct iphdr)); iph->protocol = IPPROTO_UDP; iph->saddr = in_aton("192.0.2.1"); iph->daddr = in_aton("198.51.100.1"); diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index 1f381d7b13ff..96a7d255f50f 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -31,6 +31,7 @@ #define DP83869_RGMIICTL 0x0032 #define DP83869_STRAP_STS1 0x006e #define DP83869_RGMIIDCTL 0x0086 +#define DP83869_ANA_PLL_PROG_PI 0x00c6 #define DP83869_RXFCFG 0x0134 #define DP83869_RXFPMD1 0x0136 #define DP83869_RXFPMD2 0x0137 @@ -826,12 +827,22 @@ static int dp83869_config_init(struct phy_device *phydev) dp83869_config_port_mirroring(phydev); /* Clock output selection if muxing property is set */ - if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) + if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) { + /* + * Table 7-121 in datasheet says we have to set register 0xc6 + * to value 0x10 before CLK_O_SEL can be modified. + */ + ret = phy_write_mmd(phydev, DP83869_DEVADDR, + DP83869_ANA_PLL_PROG_PI, 0x10); + if (ret) + return ret; + ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG, DP83869_IO_MUX_CFG_CLK_O_SEL_MASK, dp83869->clk_output_sel << DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); + } if (phy_interface_is_rgmii(phydev)) { ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL, diff --git a/drivers/net/usb/rtl8150.c b/drivers/net/usb/rtl8150.c index 4cda0643afb6..c880c95c41a5 100644 --- a/drivers/net/usb/rtl8150.c +++ b/drivers/net/usb/rtl8150.c @@ -683,6 +683,7 @@ static netdev_tx_t rtl8150_start_xmit(struct sk_buff *skb, struct net_device *netdev) { rtl8150_t *dev = netdev_priv(netdev); + unsigned int skb_len; int count, res; /* pad the frame and ensure terminating USB packet, datasheet 9.2.3 */ @@ -694,6 +695,8 @@ static netdev_tx_t rtl8150_start_xmit(struct sk_buff *skb, return NETDEV_TX_OK; } + skb_len = skb->len; + netif_stop_queue(netdev); dev->tx_skb = skb; usb_fill_bulk_urb(dev->tx_urb, dev->udev, usb_sndbulkpipe(dev->udev, 2), @@ -707,9 +710,16 @@ static netdev_tx_t rtl8150_start_xmit(struct sk_buff *skb, netdev->stats.tx_errors++; netif_start_queue(netdev); } + /* + * The URB was not submitted, so write_bulk_callback() will + * never run to free dev->tx_skb. Drop the skb here and + * clear tx_skb to avoid leaving a stale pointer. + */ + dev->tx_skb = NULL; + dev_kfree_skb_any(skb); } else { netdev->stats.tx_packets++; - netdev->stats.tx_bytes += skb->len; + netdev->stats.tx_bytes += skb_len; netif_trans_update(netdev); } diff --git a/drivers/net/vrf.c b/drivers/net/vrf.c index 2cf2dbd1c12f..46209917ae4d 100644 --- a/drivers/net/vrf.c +++ b/drivers/net/vrf.c @@ -1034,6 +1034,7 @@ static int do_vrf_add_slave(struct net_device *dev, struct net_device *port_dev, err: port_dev->priv_flags &= ~IFF_L3MDEV_SLAVE; + synchronize_net(); return ret; } @@ -1053,10 +1054,16 @@ static int vrf_add_slave(struct net_device *dev, struct net_device *port_dev, } /* inverse of do_vrf_add_slave */ -static int do_vrf_del_slave(struct net_device *dev, struct net_device *port_dev) +static int do_vrf_del_slave(struct net_device *dev, struct net_device *port_dev, + bool needs_sync) { netdev_upper_dev_unlink(port_dev, dev); port_dev->priv_flags &= ~IFF_L3MDEV_SLAVE; + /* Make sure that concurrent RCU readers that identified the device + * as a VRF port see a VRF master or no master at all. + */ + if (needs_sync) + synchronize_net(); cycle_netdev(port_dev, NULL); @@ -1065,7 +1072,7 @@ static int do_vrf_del_slave(struct net_device *dev, struct net_device *port_dev) static int vrf_del_slave(struct net_device *dev, struct net_device *port_dev) { - return do_vrf_del_slave(dev, port_dev); + return do_vrf_del_slave(dev, port_dev, true); } static void vrf_dev_uninit(struct net_device *dev) @@ -1619,7 +1626,7 @@ static void vrf_dellink(struct net_device *dev, struct list_head *head) struct list_head *iter; netdev_for_each_lower_dev(dev, port_dev, iter) - vrf_del_slave(dev, port_dev); + do_vrf_del_slave(dev, port_dev, false); vrf_map_unregister_dev(dev); @@ -1751,7 +1758,7 @@ static int vrf_device_event(struct notifier_block *unused, goto out; vrf_dev = netdev_master_upper_dev_get(dev); - vrf_del_slave(vrf_dev, dev); + do_vrf_del_slave(vrf_dev, dev, false); } out: return NOTIFY_DONE; diff --git a/drivers/nfc/trf7970a.c b/drivers/nfc/trf7970a.c index d17c701c7888..08c27bb438b5 100644 --- a/drivers/nfc/trf7970a.c +++ b/drivers/nfc/trf7970a.c @@ -317,6 +317,7 @@ #define TRF7970A_RSSI_OSC_STATUS_RSSI_MASK (BIT(2) | BIT(1) | BIT(0)) #define TRF7970A_RSSI_OSC_STATUS_RSSI_X_MASK (BIT(5) | BIT(4) | BIT(3)) #define TRF7970A_RSSI_OSC_STATUS_RSSI_OSC_OK BIT(6) +#define TRF7970A_RSSI_OSC_STATUS_RSSI_NOISE_LEVEL 1 #define TRF7970A_SPECIAL_FCN_REG1_COL_7_6 BIT(0) #define TRF7970A_SPECIAL_FCN_REG1_14_ANTICOLL BIT(1) @@ -1300,7 +1301,7 @@ static int trf7970a_is_rf_field(struct trf7970a *trf, bool *is_rf_field) if (ret) return ret; - if (rssi & TRF7970A_RSSI_OSC_STATUS_RSSI_MASK) + if ((rssi & TRF7970A_RSSI_OSC_STATUS_RSSI_MASK) > TRF7970A_RSSI_OSC_STATUS_RSSI_NOISE_LEVEL) *is_rf_field = true; else *is_rf_field = false; diff --git a/drivers/nvme/common/auth.c b/drivers/nvme/common/auth.c index 2d325fb93083..77f1d22512f8 100644 --- a/drivers/nvme/common/auth.c +++ b/drivers/nvme/common/auth.c @@ -351,18 +351,29 @@ struct nvme_dhchap_key *nvme_auth_transform_key( } EXPORT_SYMBOL_GPL(nvme_auth_transform_key); +/** + * nvme_auth_augmented_challenge() - Compute the augmented DH-HMAC-CHAP challenge + * @hmac_id: Hash algorithm identifier + * @skey: Session key + * @skey_len: Length of @skey + * @challenge: Challenge value + * @aug: Output buffer for the augmented challenge + * @hlen: Hash output length (length of @challenge and @aug) + * + * NVMe base specification 8.3.5.5.4: The augmented challenge is computed + * applying the HMAC function using the hash function H() selected by the + * HashID parameter ... with the hash of the ephemeral DH key ... as HMAC key + * to the challenge C (i.e., Ca = HMAC(H(g^xy mod p), C)). + * + * As the session key skey is already H(g^xy mod p) per section 8.3.5.5.9, use + * it directly as the HMAC key without additional hashing. + * + * Return: 0 on success, negative errno on failure. + */ int nvme_auth_augmented_challenge(u8 hmac_id, const u8 *skey, size_t skey_len, const u8 *challenge, u8 *aug, size_t hlen) { - u8 hashed_key[NVME_AUTH_MAX_DIGEST_SIZE]; - int ret; - - ret = nvme_auth_hash(hmac_id, skey, skey_len, hashed_key); - if (ret) - return ret; - ret = nvme_auth_hmac(hmac_id, hashed_key, hlen, challenge, hlen, aug); - memzero_explicit(hashed_key, sizeof(hashed_key)); - return ret; + return nvme_auth_hmac(hmac_id, skey, skey_len, challenge, hlen, aug); } EXPORT_SYMBOL_GPL(nvme_auth_augmented_challenge); @@ -403,33 +414,76 @@ int nvme_auth_gen_pubkey(struct crypto_kpp *dh_tfm, } EXPORT_SYMBOL_GPL(nvme_auth_gen_pubkey); -int nvme_auth_gen_shared_secret(struct crypto_kpp *dh_tfm, - const u8 *ctrl_key, size_t ctrl_key_len, - u8 *sess_key, size_t sess_key_len) +/** + * nvme_auth_gen_session_key() - Generate an ephemeral session key + * @dh_tfm: Diffie-Hellman transform with local private key already set + * @public_key: Peer's public key + * @public_key_len: Length of @public_key + * @sess_key: Output buffer for the session key + * @sess_key_len: Size of @sess_key buffer + * @hash_id: Hash algorithm identifier + * + * NVMe base specification 8.3.5.5.9: The session key Ks shall be computed from + * the ephemeral DH key (i.e., g^xy mod p) ... by applying the hash function + * H() selected by the HashID parameter ... (i.e., Ks = H(g^xy mod p)). + * + * Return: 0 on success, negative errno on failure. + */ +int nvme_auth_gen_session_key(struct crypto_kpp *dh_tfm, + const u8 *public_key, size_t public_key_len, + u8 *sess_key, size_t sess_key_len, u8 hash_id) { struct kpp_request *req; struct crypto_wait wait; struct scatterlist src, dst; + u8 *dh_secret; + size_t dh_secret_len, hash_len; int ret; - req = kpp_request_alloc(dh_tfm, GFP_KERNEL); - if (!req) + hash_len = nvme_auth_hmac_hash_len(hash_id); + if (!hash_len) { + pr_warn("%s: invalid hash algorithm %d\n", __func__, hash_id); + return -EINVAL; + } + + if (sess_key_len != hash_len) { + pr_warn("%s: sess_key buffer missized (%zu != %zu)\n", + __func__, sess_key_len, hash_len); + return -EINVAL; + } + + dh_secret_len = crypto_kpp_maxsize(dh_tfm); + dh_secret = kzalloc(dh_secret_len, GFP_KERNEL); + if (!dh_secret) return -ENOMEM; + req = kpp_request_alloc(dh_tfm, GFP_KERNEL); + if (!req) { + ret = -ENOMEM; + goto out_free_secret; + } + crypto_init_wait(&wait); - sg_init_one(&src, ctrl_key, ctrl_key_len); - kpp_request_set_input(req, &src, ctrl_key_len); - sg_init_one(&dst, sess_key, sess_key_len); - kpp_request_set_output(req, &dst, sess_key_len); + sg_init_one(&src, public_key, public_key_len); + kpp_request_set_input(req, &src, public_key_len); + sg_init_one(&dst, dh_secret, dh_secret_len); + kpp_request_set_output(req, &dst, dh_secret_len); kpp_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, crypto_req_done, &wait); ret = crypto_wait_req(crypto_kpp_compute_shared_secret(req), &wait); - kpp_request_free(req); + + if (ret) + goto out_free_secret; + + ret = nvme_auth_hash(hash_id, dh_secret, dh_secret_len, sess_key); + +out_free_secret: + kfree_sensitive(dh_secret); return ret; } -EXPORT_SYMBOL_GPL(nvme_auth_gen_shared_secret); +EXPORT_SYMBOL_GPL(nvme_auth_gen_session_key); int nvme_auth_parse_key(const char *secret, struct nvme_dhchap_key **ret_key) { diff --git a/drivers/nvme/host/apple.c b/drivers/nvme/host/apple.c index ed61b97fde59..423c9c628e7b 100644 --- a/drivers/nvme/host/apple.c +++ b/drivers/nvme/host/apple.c @@ -1267,11 +1267,7 @@ static int apple_nvme_get_address(struct nvme_ctrl *ctrl, char *buf, int size) static void apple_nvme_free_ctrl(struct nvme_ctrl *ctrl) { - struct apple_nvme *anv = ctrl_to_apple_nvme(ctrl); - - if (anv->ctrl.admin_q) - blk_put_queue(anv->ctrl.admin_q); - put_device(anv->dev); + put_device(ctrl->dev); } static const struct nvme_ctrl_ops nvme_ctrl_ops = { diff --git a/drivers/nvme/host/auth.c b/drivers/nvme/host/auth.c index bbedbe181c8a..16de4499a8e7 100644 --- a/drivers/nvme/host/auth.c +++ b/drivers/nvme/host/auth.c @@ -535,11 +535,12 @@ static int nvme_auth_dhchap_setup_ctrl_response(struct nvme_ctrl *ctrl, put_unaligned_le16(chap->transaction, buf); nvme_auth_hmac_update(&hmac, buf, 2); - memset(buf, 0, 4); + *buf = chap->sc_c; nvme_auth_hmac_update(&hmac, buf, 1); nvme_auth_hmac_update(&hmac, "Controller", 10); nvme_auth_hmac_update(&hmac, ctrl->opts->subsysnqn, strlen(ctrl->opts->subsysnqn)); + memset(buf, 0, 4); nvme_auth_hmac_update(&hmac, buf, 1); nvme_auth_hmac_update(&hmac, ctrl->opts->host->nqn, strlen(ctrl->opts->host->nqn)); @@ -587,7 +588,7 @@ static int nvme_auth_dhchap_exponential(struct nvme_ctrl *ctrl, } gen_sesskey: - chap->sess_key_len = chap->host_key_len; + chap->sess_key_len = chap->hash_len; chap->sess_key = kmalloc(chap->sess_key_len, GFP_KERNEL); if (!chap->sess_key) { chap->sess_key_len = 0; @@ -595,16 +596,17 @@ static int nvme_auth_dhchap_exponential(struct nvme_ctrl *ctrl, return -ENOMEM; } - ret = nvme_auth_gen_shared_secret(chap->dh_tfm, - chap->ctrl_key, chap->ctrl_key_len, - chap->sess_key, chap->sess_key_len); + ret = nvme_auth_gen_session_key(chap->dh_tfm, + chap->ctrl_key, chap->ctrl_key_len, + chap->sess_key, chap->sess_key_len, + chap->hash_id); if (ret) { dev_dbg(ctrl->device, - "failed to generate shared secret, error %d\n", ret); + "failed to generate session key, error %d\n", ret); chap->status = NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD; return ret; } - dev_dbg(ctrl->device, "shared secret %*ph\n", + dev_dbg(ctrl->device, "session key %*ph\n", (int)chap->sess_key_len, chap->sess_key); return 0; } diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c index 1e33af94c24b..dc388e24caad 100644 --- a/drivers/nvme/host/core.c +++ b/drivers/nvme/host/core.c @@ -454,11 +454,10 @@ void nvme_end_req(struct request *req) blk_mq_end_request(req, status); } -void nvme_complete_rq(struct request *req) +static void __nvme_complete_rq(struct request *req) { struct nvme_ctrl *ctrl = nvme_req(req)->ctrl; - trace_nvme_complete_rq(req); nvme_cleanup_cmd(req); /* @@ -493,6 +492,12 @@ void nvme_complete_rq(struct request *req) return; } } + +void nvme_complete_rq(struct request *req) +{ + trace_nvme_complete_rq(req); + __nvme_complete_rq(req); +} EXPORT_SYMBOL_GPL(nvme_complete_rq); void nvme_complete_batch_req(struct request *req) @@ -513,7 +518,7 @@ blk_status_t nvme_host_path_error(struct request *req) { nvme_req(req)->status = NVME_SC_HOST_PATH_ERROR; blk_mq_set_request_complete(req); - nvme_complete_rq(req); + __nvme_complete_rq(req); return BLK_STS_OK; } EXPORT_SYMBOL_GPL(nvme_host_path_error); @@ -3044,7 +3049,7 @@ static const struct nvme_core_quirk_entry core_quirks[] = { * * The device is left in a state where it is also not possible * to use "nvme set-feature" to disable APST, but booting with - * nvme_core.default_ps_max_latency=0 works. + * nvme_core.default_ps_max_latency_us=0 works. */ .vid = 0x1e0f, .mn = "KCD6XVUL6T40", @@ -4083,7 +4088,8 @@ static int nvme_init_ns_head(struct nvme_ns *ns, struct nvme_ns_info *info) mutex_unlock(&ctrl->subsys->lock); #ifdef CONFIG_NVME_MULTIPATH - cancel_delayed_work(&head->remove_work); + if (cancel_delayed_work(&head->remove_work)) + module_put(THIS_MODULE); #endif return 0; diff --git a/drivers/nvme/host/fc.c b/drivers/nvme/host/fc.c index e1bb4707183c..e4f4528fe2a2 100644 --- a/drivers/nvme/host/fc.c +++ b/drivers/nvme/host/fc.c @@ -3968,3 +3968,4 @@ module_exit(nvme_fc_exit_module); MODULE_DESCRIPTION("NVMe host FC transport driver"); MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("nvme-fc"); diff --git a/drivers/nvme/host/multipath.c b/drivers/nvme/host/multipath.c index ba00f0b72b85..263161cb8ac0 100644 --- a/drivers/nvme/host/multipath.c +++ b/drivers/nvme/host/multipath.c @@ -231,16 +231,12 @@ bool nvme_mpath_clear_current_path(struct nvme_ns *ns) bool changed = false; int node; - if (!head) - goto out; - for_each_node(node) { if (ns == rcu_access_pointer(head->current_path[node])) { rcu_assign_pointer(head->current_path[node], NULL); changed = true; } } -out: return changed; } diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index db5fc9bf6627..9fd04cd7c5cb 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -2241,6 +2241,7 @@ static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) static const struct blk_mq_ops nvme_mq_admin_ops = { .queue_rq = nvme_queue_rq, .complete = nvme_pci_complete_rq, + .commit_rqs = nvme_commit_rqs, .init_hctx = nvme_admin_init_hctx, .init_request = nvme_pci_init_request, .timeout = nvme_timeout, @@ -4104,6 +4105,10 @@ static const struct pci_device_id nvme_id_table[] = { .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, + { PCI_DEVICE(0x1c5f, 0x0555), /* Memblaze Pblaze5 adapter */ + .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, }, + { PCI_DEVICE(0x144d, 0xa808), /* Samsung PM981/983 */ + .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ diff --git a/drivers/nvme/host/rdma.c b/drivers/nvme/host/rdma.c index 57111139e84f..f77c960f7632 100644 --- a/drivers/nvme/host/rdma.c +++ b/drivers/nvme/host/rdma.c @@ -2189,6 +2189,13 @@ static void nvme_rdma_reset_ctrl_work(struct work_struct *work) nvme_rdma_reconnect_or_remove(ctrl, ret); } +static bool nvme_rdma_supports_pci_p2pdma(struct nvme_ctrl *ctrl) +{ + struct nvme_rdma_ctrl *r_ctrl = to_rdma_ctrl(ctrl); + + return ib_dma_pci_p2p_dma_supported(r_ctrl->device->dev); +} + static const struct nvme_ctrl_ops nvme_rdma_ctrl_ops = { .name = "rdma", .module = THIS_MODULE, @@ -2203,6 +2210,7 @@ static const struct nvme_ctrl_ops nvme_rdma_ctrl_ops = { .get_address = nvmf_get_address, .stop_ctrl = nvme_rdma_stop_ctrl, .get_virt_boundary = nvme_get_virt_boundary, + .supports_pci_p2pdma = nvme_rdma_supports_pci_p2pdma, }; /* @@ -2432,3 +2440,4 @@ module_exit(nvme_rdma_cleanup_module); MODULE_DESCRIPTION("NVMe host RDMA transport driver"); MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("nvme-rdma"); diff --git a/drivers/nvme/host/sysfs.c b/drivers/nvme/host/sysfs.c index 7bf2e972126b..e59758616f27 100644 --- a/drivers/nvme/host/sysfs.c +++ b/drivers/nvme/host/sysfs.c @@ -883,10 +883,26 @@ static ssize_t tls_keyring_show(struct device *dev, } static DEVICE_ATTR_RO(tls_keyring); +static ssize_t tls_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct nvme_ctrl *ctrl = dev_get_drvdata(dev); + const char *mode; + + if (ctrl->opts->tls) + mode = "tls"; + else + mode = "concat"; + + return sysfs_emit(buf, "%s\n", mode); +} +static DEVICE_ATTR_RO(tls_mode); + static struct attribute *nvme_tls_attrs[] = { &dev_attr_tls_key.attr, &dev_attr_tls_configured_key.attr, &dev_attr_tls_keyring.attr, + &dev_attr_tls_mode.attr, NULL, }; @@ -908,6 +924,9 @@ static umode_t nvme_tls_attrs_are_visible(struct kobject *kobj, if (a == &dev_attr_tls_keyring.attr && !ctrl->opts->keyring) return 0; + if (a == &dev_attr_tls_mode.attr && + !ctrl->opts->tls && !ctrl->opts->concat) + return 0; return a->mode; } diff --git a/drivers/nvme/host/tcp.c b/drivers/nvme/host/tcp.c index 243dab830dc8..15d36d6a728e 100644 --- a/drivers/nvme/host/tcp.c +++ b/drivers/nvme/host/tcp.c @@ -1438,18 +1438,32 @@ static void nvme_tcp_free_queue(struct nvme_ctrl *nctrl, int qid) { struct nvme_tcp_ctrl *ctrl = to_tcp_ctrl(nctrl); struct nvme_tcp_queue *queue = &ctrl->queues[qid]; - unsigned int noreclaim_flag; + unsigned int noio_flag; if (!test_and_clear_bit(NVME_TCP_Q_ALLOCATED, &queue->flags)) return; page_frag_cache_drain(&queue->pf_cache); - noreclaim_flag = memalloc_noreclaim_save(); - /* ->sock will be released by fput() */ - fput(queue->sock->file); + /** + * Prevent memory reclaim from triggering block I/O during socket + * teardown. The socket release path fput -> tcp_close -> + * tcp_disconnect -> tcp_send_active_reset may allocate memory, and + * allowing reclaim to issue I/O could deadlock if we're being called + * from block device teardown (e.g., del_gendisk -> elevator cleanup) + * which holds locks that the I/O completion path needs. + */ + noio_flag = memalloc_noio_save(); + + /** + * Release the socket synchronously. During reset in + * nvme_reset_ctrl_work(), queue teardown is immediately followed by + * re-allocation. fput() defers socket cleanup to delayed_fput_work + * in workqueue context, which can race with new queue setup. + */ + __fput_sync(queue->sock->file); queue->sock = NULL; - memalloc_noreclaim_restore(noreclaim_flag); + memalloc_noio_restore(noio_flag); kfree(queue->pdu); mutex_destroy(&queue->send_mutex); @@ -1901,8 +1915,8 @@ static int nvme_tcp_alloc_queue(struct nvme_ctrl *nctrl, int qid, err_rcv_pdu: kfree(queue->pdu); err_sock: - /* ->sock will be released by fput() */ - fput(queue->sock->file); + /* Use sync variant - see nvme_tcp_free_queue() for explanation */ + __fput_sync(queue->sock->file); queue->sock = NULL; err_destroy_mutex: mutex_destroy(&queue->send_mutex); @@ -3071,3 +3085,4 @@ module_exit(nvme_tcp_cleanup_module); MODULE_DESCRIPTION("NVMe host TCP transport driver"); MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("nvme-tcp"); diff --git a/drivers/nvme/target/admin-cmd.c b/drivers/nvme/target/admin-cmd.c index e4fd1caadfb0..01b799e92ae6 100644 --- a/drivers/nvme/target/admin-cmd.c +++ b/drivers/nvme/target/admin-cmd.c @@ -687,12 +687,8 @@ static void nvmet_execute_identify_ctrl(struct nvmet_req *req) id->cmic = NVME_CTRL_CMIC_MULTI_PORT | NVME_CTRL_CMIC_MULTI_CTRL | NVME_CTRL_CMIC_ANA; - /* Limit MDTS according to transport capability */ - if (ctrl->ops->get_mdts) - id->mdts = ctrl->ops->get_mdts(ctrl); - else - id->mdts = 0; - + /* Limit MDTS according to port config or transport capability */ + id->mdts = nvmet_ctrl_mdts(req); id->cntlid = cpu_to_le16(ctrl->cntlid); id->ver = cpu_to_le32(ctrl->subsys->ver); diff --git a/drivers/nvme/target/auth.c b/drivers/nvme/target/auth.c index b34610e2f19d..9a2eccdc8b13 100644 --- a/drivers/nvme/target/auth.c +++ b/drivers/nvme/target/auth.c @@ -229,9 +229,6 @@ u8 nvmet_setup_auth(struct nvmet_ctrl *ctrl, struct nvmet_sq *sq, bool reset) void nvmet_auth_sq_free(struct nvmet_sq *sq) { cancel_delayed_work(&sq->auth_expired_work); -#ifdef CONFIG_NVME_TARGET_TCP_TLS - sq->tls_key = NULL; -#endif kfree(sq->dhchap_c1); sq->dhchap_c1 = NULL; kfree(sq->dhchap_c2); @@ -402,11 +399,12 @@ int nvmet_auth_ctrl_hash(struct nvmet_req *req, u8 *response, put_unaligned_le16(req->sq->dhchap_tid, buf); nvme_auth_hmac_update(&hmac, buf, 2); - memset(buf, 0, 4); + *buf = req->sq->sc_c; nvme_auth_hmac_update(&hmac, buf, 1); nvme_auth_hmac_update(&hmac, "Controller", 10); nvme_auth_hmac_update(&hmac, ctrl->subsys->subsysnqn, strlen(ctrl->subsys->subsysnqn)); + memset(buf, 0, 4); nvme_auth_hmac_update(&hmac, buf, 1); nvme_auth_hmac_update(&hmac, ctrl->hostnqn, strlen(ctrl->hostnqn)); nvme_auth_hmac_final(&hmac, response); @@ -449,18 +447,19 @@ int nvmet_auth_ctrl_sesskey(struct nvmet_req *req, struct nvmet_ctrl *ctrl = req->sq->ctrl; int ret; - req->sq->dhchap_skey_len = ctrl->dh_keysize; + req->sq->dhchap_skey_len = nvme_auth_hmac_hash_len(ctrl->shash_id); req->sq->dhchap_skey = kzalloc(req->sq->dhchap_skey_len, GFP_KERNEL); if (!req->sq->dhchap_skey) return -ENOMEM; - ret = nvme_auth_gen_shared_secret(ctrl->dh_tfm, - pkey, pkey_size, - req->sq->dhchap_skey, - req->sq->dhchap_skey_len); + ret = nvme_auth_gen_session_key(ctrl->dh_tfm, + pkey, pkey_size, + req->sq->dhchap_skey, + req->sq->dhchap_skey_len, + ctrl->shash_id); if (ret) - pr_debug("failed to compute shared secret, err %d\n", ret); + pr_debug("failed to compute session key, err %d\n", ret); else - pr_debug("%s: shared secret %*ph\n", __func__, + pr_debug("%s: session key %*ph\n", __func__, (int)req->sq->dhchap_skey_len, req->sq->dhchap_skey); diff --git a/drivers/nvme/target/configfs.c b/drivers/nvme/target/configfs.c index 463348c7f097..b88f897f06e2 100644 --- a/drivers/nvme/target/configfs.c +++ b/drivers/nvme/target/configfs.c @@ -301,6 +301,31 @@ static ssize_t nvmet_param_max_queue_size_store(struct config_item *item, CONFIGFS_ATTR(nvmet_, param_max_queue_size); +static ssize_t nvmet_param_mdts_show(struct config_item *item, char *page) +{ + struct nvmet_port *port = to_nvmet_port(item); + + return snprintf(page, PAGE_SIZE, "%d\n", port->mdts); +} + +static ssize_t nvmet_param_mdts_store(struct config_item *item, + const char *page, size_t count) +{ + struct nvmet_port *port = to_nvmet_port(item); + int ret; + + if (nvmet_is_port_enabled(port, __func__)) + return -EACCES; + ret = kstrtoint(page, 0, &port->mdts); + if (ret) { + pr_err("Invalid value '%s' for mdts\n", page); + return -EINVAL; + } + return count; +} + +CONFIGFS_ATTR(nvmet_, param_mdts); + #ifdef CONFIG_BLK_DEV_INTEGRITY static ssize_t nvmet_param_pi_enable_show(struct config_item *item, char *page) @@ -1995,6 +2020,7 @@ static struct configfs_attribute *nvmet_port_attrs[] = { &nvmet_attr_addr_tsas, &nvmet_attr_param_inline_data_size, &nvmet_attr_param_max_queue_size, + &nvmet_attr_param_mdts, #ifdef CONFIG_BLK_DEV_INTEGRITY &nvmet_attr_param_pi_enable, #endif @@ -2053,6 +2079,7 @@ static struct config_group *nvmet_ports_make(struct config_group *group, INIT_LIST_HEAD(&port->referrals); port->inline_data_size = -1; /* < 0 == let the transport choose */ port->max_queue_size = -1; /* < 0 == let the transport choose */ + port->mdts = -1; /* < 0 == let the transport choose */ port->disc_addr.trtype = NVMF_TRTYPE_MAX; port->disc_addr.portid = cpu_to_le16(portid); diff --git a/drivers/nvme/target/core.c b/drivers/nvme/target/core.c index 45f686175fea..62dd59b9aa4f 100644 --- a/drivers/nvme/target/core.c +++ b/drivers/nvme/target/core.c @@ -370,6 +370,14 @@ int nvmet_enable_port(struct nvmet_port *port) NVMET_MIN_QUEUE_SIZE, NVMET_MAX_QUEUE_SIZE); + /* + * If the transport didn't set the mdts properly, then clamp it to the + * target limits. Also set default values in case the transport didn't + * set it at all. + */ + if (port->mdts < 0 || port->mdts > NVMET_MAX_MDTS) + port->mdts = 0; + port->enabled = true; port->tr_ops = ops; return 0; @@ -1743,7 +1751,7 @@ static void nvmet_ctrl_free(struct kref *ref) nvmet_stop_keep_alive_timer(ctrl); - flush_work(&ctrl->async_event_work); + cancel_work_sync(&ctrl->async_event_work); cancel_work_sync(&ctrl->fatal_err_work); nvmet_destroy_auth(ctrl); diff --git a/drivers/nvme/target/fabrics-cmd-auth.c b/drivers/nvme/target/fabrics-cmd-auth.c index b9ab80c7a694..f1e613e7c63e 100644 --- a/drivers/nvme/target/fabrics-cmd-auth.c +++ b/drivers/nvme/target/fabrics-cmd-auth.c @@ -395,10 +395,9 @@ void nvmet_execute_auth_send(struct nvmet_req *req) goto complete; } /* Final states, clear up variables */ - if (req->sq->dhchap_step == NVME_AUTH_DHCHAP_MESSAGE_FAILURE2) { - nvmet_auth_sq_free(req->sq); + nvmet_auth_sq_free(req->sq); + if (req->sq->dhchap_step == NVME_AUTH_DHCHAP_MESSAGE_FAILURE2) nvmet_ctrl_fatal_error(ctrl); - } complete: nvmet_req_complete(req, status); @@ -574,7 +573,9 @@ void nvmet_execute_auth_receive(struct nvmet_req *req) status = nvmet_copy_to_sgl(req, 0, d, al); kfree(d); done: - if (req->sq->dhchap_step == NVME_AUTH_DHCHAP_MESSAGE_FAILURE1) { + if (req->sq->dhchap_step == NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2) + nvmet_auth_sq_free(req->sq); + else if (req->sq->dhchap_step == NVME_AUTH_DHCHAP_MESSAGE_FAILURE1) { nvmet_auth_sq_free(req->sq); nvmet_ctrl_fatal_error(ctrl); } diff --git a/drivers/nvme/target/nvmet.h b/drivers/nvme/target/nvmet.h index 50070cfb782a..3305a88684ec 100644 --- a/drivers/nvme/target/nvmet.h +++ b/drivers/nvme/target/nvmet.h @@ -214,6 +214,7 @@ struct nvmet_port { bool enabled; int inline_data_size; int max_queue_size; + int mdts; const struct nvmet_fabrics_ops *tr_ops; bool pi_enable; }; @@ -673,6 +674,7 @@ void nvmet_add_async_event(struct nvmet_ctrl *ctrl, u8 event_type, #define NVMET_MAX_QUEUE_SIZE 1024 #define NVMET_NR_QUEUES 128 #define NVMET_MAX_CMD(ctrl) (NVME_CAP_MQES(ctrl->cap) + 1) +#define NVMET_MAX_MDTS 255 /* * Nice round number that makes a list of nsids fit into a page. @@ -761,6 +763,17 @@ static inline bool nvmet_is_pci_ctrl(struct nvmet_ctrl *ctrl) return ctrl->port->disc_addr.trtype == NVMF_TRTYPE_PCI; } +/* Limit MDTS according to port config or transport capability */ +static inline u8 nvmet_ctrl_mdts(struct nvmet_req *req) +{ + struct nvmet_ctrl *ctrl = req->sq->ctrl; + u8 mdts = req->port->mdts; + + if (!ctrl->ops->get_mdts) + return mdts; + return min_not_zero(ctrl->ops->get_mdts(ctrl), mdts); +} + #ifdef CONFIG_NVME_TARGET_PASSTHRU void nvmet_passthru_subsys_free(struct nvmet_subsys *subsys); int nvmet_passthru_ctrl_enable(struct nvmet_subsys *subsys); diff --git a/drivers/nvme/target/tcp.c b/drivers/nvme/target/tcp.c index 4b8b02341ddc..164a564ba3b4 100644 --- a/drivers/nvme/target/tcp.c +++ b/drivers/nvme/target/tcp.c @@ -349,9 +349,7 @@ static void nvmet_tcp_free_cmd_buffers(struct nvmet_tcp_cmd *cmd) cmd->req.sg = NULL; } -static void nvmet_tcp_fatal_error(struct nvmet_tcp_queue *queue); - -static void nvmet_tcp_build_pdu_iovec(struct nvmet_tcp_cmd *cmd) +static int nvmet_tcp_build_pdu_iovec(struct nvmet_tcp_cmd *cmd) { struct bio_vec *iov = cmd->iov; struct scatterlist *sg; @@ -364,22 +362,19 @@ static void nvmet_tcp_build_pdu_iovec(struct nvmet_tcp_cmd *cmd) offset = cmd->rbytes_done; cmd->sg_idx = offset / PAGE_SIZE; sg_offset = offset % PAGE_SIZE; - if (!cmd->req.sg_cnt || cmd->sg_idx >= cmd->req.sg_cnt) { - nvmet_tcp_fatal_error(cmd->queue); - return; - } + if (!cmd->req.sg_cnt || cmd->sg_idx >= cmd->req.sg_cnt) + return -EPROTO; + sg = &cmd->req.sg[cmd->sg_idx]; sg_remaining = cmd->req.sg_cnt - cmd->sg_idx; while (length) { - if (!sg_remaining) { - nvmet_tcp_fatal_error(cmd->queue); - return; - } - if (!sg->length || sg->length <= sg_offset) { - nvmet_tcp_fatal_error(cmd->queue); - return; - } + if (!sg_remaining) + return -EPROTO; + + if (!sg->length || sg->length <= sg_offset) + return -EPROTO; + u32 iov_len = min_t(u32, length, sg->length - sg_offset); bvec_set_page(iov, sg_page(sg), iov_len, @@ -394,24 +389,29 @@ static void nvmet_tcp_build_pdu_iovec(struct nvmet_tcp_cmd *cmd) iov_iter_bvec(&cmd->recv_msg.msg_iter, ITER_DEST, cmd->iov, nr_pages, cmd->pdu_len); -} - -static void nvmet_tcp_fatal_error(struct nvmet_tcp_queue *queue) -{ - queue->rcv_state = NVMET_TCP_RECV_ERR; - if (queue->nvme_sq.ctrl) - nvmet_ctrl_fatal_error(queue->nvme_sq.ctrl); - else - kernel_sock_shutdown(queue->sock, SHUT_RDWR); + return 0; } static void nvmet_tcp_socket_error(struct nvmet_tcp_queue *queue, int status) { + /* + * Keep rcv_state at RECV_ERR even for the internal -ESHUTDOWN path. + * nvmet_tcp_handle_icreq() can return -ESHUTDOWN after the ICReq has + * already been consumed and queue teardown has started. + * + * If nvmet_tcp_data_ready() or nvmet_tcp_write_space() queues + * nvmet_tcp_io_work() again before nvmet_tcp_release_queue_work() + * cancels it, the queue must not keep that old receive state. + * Otherwise the next nvmet_tcp_io_work() run can reach + * nvmet_tcp_done_recv_pdu() and try to handle the same ICReq again. + * + * That is why queue->rcv_state needs to be updated before we return. + */ queue->rcv_state = NVMET_TCP_RECV_ERR; - if (status == -EPIPE || status == -ECONNRESET) + if (status == -EPIPE || status == -ECONNRESET || !queue->nvme_sq.ctrl) kernel_sock_shutdown(queue->sock, SHUT_RDWR); else - nvmet_tcp_fatal_error(queue); + nvmet_ctrl_fatal_error(queue->nvme_sq.ctrl); } static int nvmet_tcp_map_data(struct nvmet_tcp_cmd *cmd) @@ -887,7 +887,6 @@ static int nvmet_tcp_handle_icreq(struct nvmet_tcp_queue *queue) if (le32_to_cpu(icreq->hdr.plen) != sizeof(struct nvme_tcp_icreq_pdu)) { pr_err("bad nvme-tcp pdu length (%d)\n", le32_to_cpu(icreq->hdr.plen)); - nvmet_tcp_fatal_error(queue); return -EPROTO; } @@ -922,16 +921,29 @@ static int nvmet_tcp_handle_icreq(struct nvmet_tcp_queue *queue) iov.iov_len = sizeof(*icresp); ret = kernel_sendmsg(queue->sock, &msg, &iov, 1, iov.iov_len); if (ret < 0) { + spin_lock_bh(&queue->state_lock); + if (queue->state == NVMET_TCP_Q_DISCONNECTING) { + spin_unlock_bh(&queue->state_lock); + return -ESHUTDOWN; + } queue->state = NVMET_TCP_Q_FAILED; + spin_unlock_bh(&queue->state_lock); return ret; /* queue removal will cleanup */ } + spin_lock_bh(&queue->state_lock); + if (queue->state == NVMET_TCP_Q_DISCONNECTING) { + spin_unlock_bh(&queue->state_lock); + /* Tell nvmet_tcp_socket_error() teardown is in progress. */ + return -ESHUTDOWN; + } queue->state = NVMET_TCP_Q_LIVE; + spin_unlock_bh(&queue->state_lock); nvmet_prepare_receive_pdu(queue); return 0; } -static void nvmet_tcp_handle_req_failure(struct nvmet_tcp_queue *queue, +static int nvmet_tcp_handle_req_failure(struct nvmet_tcp_queue *queue, struct nvmet_tcp_cmd *cmd, struct nvmet_req *req) { size_t data_len = le32_to_cpu(req->cmd->common.dptr.sgl.length); @@ -947,19 +959,22 @@ static void nvmet_tcp_handle_req_failure(struct nvmet_tcp_queue *queue, if (!nvme_is_write(cmd->req.cmd) || !data_len || data_len > cmd->req.port->inline_data_size) { nvmet_prepare_receive_pdu(queue); - return; + return 0; } ret = nvmet_tcp_map_data(cmd); if (unlikely(ret)) { pr_err("queue %d: failed to map data\n", queue->idx); - nvmet_tcp_fatal_error(queue); - return; + return -EPROTO; } queue->rcv_state = NVMET_TCP_RECV_DATA; - nvmet_tcp_build_pdu_iovec(cmd); cmd->flags |= NVMET_TCP_F_INIT_FAILED; + ret = nvmet_tcp_build_pdu_iovec(cmd); + if (unlikely(ret)) + pr_err("queue %d: failed to build PDU iovec\n", queue->idx); + + return ret; } static int nvmet_tcp_handle_h2c_data_pdu(struct nvmet_tcp_queue *queue) @@ -1011,7 +1026,10 @@ static int nvmet_tcp_handle_h2c_data_pdu(struct nvmet_tcp_queue *queue) goto err_proto; } cmd->pdu_recv = 0; - nvmet_tcp_build_pdu_iovec(cmd); + if (unlikely(nvmet_tcp_build_pdu_iovec(cmd))) { + pr_err("queue %d: failed to build PDU iovec\n", queue->idx); + goto err_proto; + } queue->cmd = cmd; queue->rcv_state = NVMET_TCP_RECV_DATA; @@ -1019,7 +1037,6 @@ static int nvmet_tcp_handle_h2c_data_pdu(struct nvmet_tcp_queue *queue) err_proto: /* FIXME: use proper transport errors */ - nvmet_tcp_fatal_error(queue); return -EPROTO; } @@ -1034,7 +1051,6 @@ static int nvmet_tcp_done_recv_pdu(struct nvmet_tcp_queue *queue) if (hdr->type != nvme_tcp_icreq) { pr_err("unexpected pdu type (%d) before icreq\n", hdr->type); - nvmet_tcp_fatal_error(queue); return -EPROTO; } return nvmet_tcp_handle_icreq(queue); @@ -1043,7 +1059,6 @@ static int nvmet_tcp_done_recv_pdu(struct nvmet_tcp_queue *queue) if (unlikely(hdr->type == nvme_tcp_icreq)) { pr_err("queue %d: received icreq pdu in state %d\n", queue->idx, queue->state); - nvmet_tcp_fatal_error(queue); return -EPROTO; } @@ -1060,7 +1075,6 @@ static int nvmet_tcp_done_recv_pdu(struct nvmet_tcp_queue *queue) pr_err("queue %d: out of commands (%d) send_list_len: %d, opcode: %d", queue->idx, queue->nr_cmds, queue->send_list_len, nvme_cmd->common.opcode); - nvmet_tcp_fatal_error(queue); return -ENOMEM; } @@ -1074,17 +1088,16 @@ static int nvmet_tcp_done_recv_pdu(struct nvmet_tcp_queue *queue) le32_to_cpu(req->cmd->common.dptr.sgl.length), le16_to_cpu(req->cqe->status)); - nvmet_tcp_handle_req_failure(queue, queue->cmd, req); - return 0; + return nvmet_tcp_handle_req_failure(queue, queue->cmd, req); } ret = nvmet_tcp_map_data(queue->cmd); if (unlikely(ret)) { pr_err("queue %d: failed to map data\n", queue->idx); if (nvmet_tcp_has_inline_data(queue->cmd)) - nvmet_tcp_fatal_error(queue); - else - nvmet_req_complete(req, ret); + return -EPROTO; + + nvmet_req_complete(req, ret); ret = -EAGAIN; goto out; } @@ -1092,8 +1105,11 @@ static int nvmet_tcp_done_recv_pdu(struct nvmet_tcp_queue *queue) if (nvmet_tcp_need_data_in(queue->cmd)) { if (nvmet_tcp_has_inline_data(queue->cmd)) { queue->rcv_state = NVMET_TCP_RECV_DATA; - nvmet_tcp_build_pdu_iovec(queue->cmd); - return 0; + ret = nvmet_tcp_build_pdu_iovec(queue->cmd); + if (unlikely(ret)) + pr_err("queue %d: failed to build PDU iovec\n", + queue->idx); + return ret; } /* send back R2T */ nvmet_tcp_queue_response(&queue->cmd->req); @@ -1204,7 +1220,6 @@ static int nvmet_tcp_try_recv_pdu(struct nvmet_tcp_queue *queue) if (unlikely(!nvmet_tcp_pdu_valid(hdr->type))) { pr_err("unexpected pdu type %d\n", hdr->type); - nvmet_tcp_fatal_error(queue); return -EIO; } @@ -1218,16 +1233,12 @@ static int nvmet_tcp_try_recv_pdu(struct nvmet_tcp_queue *queue) } if (queue->hdr_digest && - nvmet_tcp_verify_hdgst(queue, &queue->pdu, hdr->hlen)) { - nvmet_tcp_fatal_error(queue); /* fatal */ + nvmet_tcp_verify_hdgst(queue, &queue->pdu, hdr->hlen)) return -EPROTO; - } if (queue->data_digest && - nvmet_tcp_check_ddgst(queue, &queue->pdu)) { - nvmet_tcp_fatal_error(queue); /* fatal */ + nvmet_tcp_check_ddgst(queue, &queue->pdu)) return -EPROTO; - } return nvmet_tcp_done_recv_pdu(queue); } @@ -1310,9 +1321,9 @@ static int nvmet_tcp_try_recv_ddgst(struct nvmet_tcp_queue *queue) queue->idx, cmd->req.cmd->common.command_id, queue->pdu.cmd.hdr.type, le32_to_cpu(cmd->recv_ddgst), le32_to_cpu(cmd->exp_ddgst)); - nvmet_req_uninit(&cmd->req); + if (!(cmd->flags & NVMET_TCP_F_INIT_FAILED)) + nvmet_req_uninit(&cmd->req); nvmet_tcp_free_cmd_buffers(cmd); - nvmet_tcp_fatal_error(queue); ret = -EPROTO; goto out; } diff --git a/drivers/nvme/target/zns.c b/drivers/nvme/target/zns.c index aeaf73b54c3a..f00921931eb6 100644 --- a/drivers/nvme/target/zns.c +++ b/drivers/nvme/target/zns.c @@ -69,7 +69,6 @@ bool nvmet_bdev_zns_enable(struct nvmet_ns *ns) void nvmet_execute_identify_ctrl_zns(struct nvmet_req *req) { u8 zasl = req->sq->ctrl->subsys->zasl; - struct nvmet_ctrl *ctrl = req->sq->ctrl; struct nvme_id_ctrl_zns *id; u16 status; @@ -79,10 +78,7 @@ void nvmet_execute_identify_ctrl_zns(struct nvmet_req *req) goto out; } - if (ctrl->ops->get_mdts) - id->zasl = min_t(u8, ctrl->ops->get_mdts(ctrl), zasl); - else - id->zasl = zasl; + id->zasl = min_not_zero(nvmet_ctrl_mdts(req), zasl); status = nvmet_copy_to_sgl(req, 0, id, sizeof(*id)); diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index e8002526cfb0..d71dac9436e3 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -1231,6 +1231,7 @@ config REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY tristate "Raspberry Pi 7-inch touchscreen panel ATTINY regulator" depends on ARM || ARM64 || COMPILE_TEST depends on BACKLIGHT_CLASS_DEVICE + depends on GPIOLIB depends on I2C select REGMAP_I2C help diff --git a/drivers/s390/char/Kconfig b/drivers/s390/char/Kconfig index 4d8f09910a46..7416f941e5b6 100644 --- a/drivers/s390/char/Kconfig +++ b/drivers/s390/char/Kconfig @@ -85,14 +85,6 @@ config HMC_DRV transfer cache size from its default value 0.5MB to N bytes. If N is zero, then no caching is performed. -config SCLP_OFB - def_bool n - prompt "Support for Open-for-Business SCLP Event" - depends on S390 - help - This option enables the Open-for-Business interface to the s390 - Service Element. - config S390_UV_UAPI def_tristate m prompt "Ultravisor userspace API" diff --git a/drivers/s390/char/sclp_config.c b/drivers/s390/char/sclp_config.c index 9cfbe3fc3dca..8c77e8c44fc2 100644 --- a/drivers/s390/char/sclp_config.c +++ b/drivers/s390/char/sclp_config.c @@ -80,14 +80,11 @@ static void sclp_conf_receiver_fn(struct evbuf_header *evbuf) static struct sclp_register sclp_conf_register = { -#ifdef CONFIG_SCLP_OFB .send_mask = EVTYP_CONFMGMDATA_MASK, -#endif .receive_mask = EVTYP_CONFMGMDATA_MASK, .receiver_fn = sclp_conf_receiver_fn, }; -#ifdef CONFIG_SCLP_OFB static int sclp_ofb_send_req(char *ev_data, size_t len) { static DEFINE_MUTEX(send_mutex); @@ -143,11 +140,9 @@ static const struct bin_attribute ofb_bin_attr = { }, .write = sysfs_ofb_data_write, }; -#endif static int __init sclp_ofb_setup(void) { -#ifdef CONFIG_SCLP_OFB struct kset *ofb_kset; int rc; @@ -159,7 +154,6 @@ static int __init sclp_ofb_setup(void) kset_unregister(ofb_kset); return rc; } -#endif return 0; } diff --git a/drivers/scsi/sr.c b/drivers/scsi/sr.c index 7adb2573f50d..c36c54ecd354 100644 --- a/drivers/scsi/sr.c +++ b/drivers/scsi/sr.c @@ -395,7 +395,7 @@ static blk_status_t sr_init_command(struct scsi_cmnd *SCpnt) switch (req_op(rq)) { case REQ_OP_WRITE: - if (!cd->writeable) + if (get_disk_ro(cd->disk)) goto out; SCpnt->cmnd[0] = WRITE_10; cd->cdi.media_written = 1; @@ -681,6 +681,7 @@ static int sr_probe(struct scsi_device *sdev) error = -ENOMEM; if (get_capabilities(cd)) goto fail_minor; + cdrom_probe_write_features(&cd->cdi); sr_vendor_init(cd); set_capacity(disk, cd->capacity); @@ -899,14 +900,6 @@ static int get_capabilities(struct scsi_cd *cd) /*else I don't think it can close its tray cd->cdi.mask |= CDC_CLOSE_TRAY; */ - /* - * if DVD-RAM, MRW-W or CD-RW, we are randomly writable - */ - if ((cd->cdi.mask & (CDC_DVD_RAM | CDC_MRW_W | CDC_RAM | CDC_CD_RW)) != - (CDC_DVD_RAM | CDC_MRW_W | CDC_RAM | CDC_CD_RW)) { - cd->writeable = 1; - } - kfree(buffer); return 0; } diff --git a/drivers/scsi/sr.h b/drivers/scsi/sr.h index dc899277b3a4..2d92f9cb6fec 100644 --- a/drivers/scsi/sr.h +++ b/drivers/scsi/sr.h @@ -35,7 +35,6 @@ typedef struct scsi_cd { struct scsi_device *device; unsigned int vendor; /* vendor code, see sr_vendor.c */ unsigned long ms_offset; /* for reading multisession-CD's */ - unsigned writeable : 1; unsigned use:1; /* is this device still supportable */ unsigned xa_flag:1; /* CD has XA sectors ? */ unsigned readcd_known:1; /* drive supports READ_CD (0xbe) */ diff --git a/drivers/spi/spi-amlogic-spisg.c b/drivers/spi/spi-amlogic-spisg.c index 19c5eba412ef..f9de2d2c9213 100644 --- a/drivers/spi/spi-amlogic-spisg.c +++ b/drivers/spi/spi-amlogic-spisg.c @@ -794,6 +794,7 @@ static int aml_spisg_probe(struct platform_device *pdev) dma_set_max_seg_size(&pdev->dev, SPISG_BLOCK_MAX); + init_completion(&spisg->completion); ret = devm_request_irq(&pdev->dev, irq, aml_spisg_irq, 0, NULL, spisg); if (ret) { dev_err(&pdev->dev, "irq request failed\n"); @@ -806,8 +807,6 @@ static int aml_spisg_probe(struct platform_device *pdev) goto out_clk; } - init_completion(&spisg->completion); - pm_runtime_put(&spisg->pdev->dev); return 0; diff --git a/drivers/spi/spi-axiado.c b/drivers/spi/spi-axiado.c index 9057a0a8df4a..649f149617ce 100644 --- a/drivers/spi/spi-axiado.c +++ b/drivers/spi/spi-axiado.c @@ -201,7 +201,7 @@ static void ax_spi_fill_tx_fifo(struct ax_spi *xspi) * then spi control did't work thoroughly, add one byte delay */ if (ax_spi_read(xspi, AX_SPI_IVR) & AX_SPI_IVR_TFOV) - usleep_range(10, 10); + udelay(10); if (xspi->tx_buf) ax_spi_write_b(xspi, AX_SPI_TXFIFO, *xspi->tx_buf++); else diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 65aff2e70265..057381e56a7f 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1860,14 +1860,10 @@ static int cqspi_probe(struct platform_device *pdev) if (irq < 0) return -ENXIO; - ret = pm_runtime_set_active(dev); - if (ret) - return ret; - ret = clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); if (ret) { dev_err(dev, "Cannot enable QSPI clocks.\n"); - goto disable_rpm; + return ret; } /* Obtain QSPI reset control */ @@ -1962,10 +1958,11 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->sclk = 0; if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { - pm_runtime_enable(dev); pm_runtime_set_autosuspend_delay(dev, CQSPI_AUTOSUSPEND_TIMEOUT); pm_runtime_use_autosuspend(dev); pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); } host->num_chipselect = cqspi->num_chipselect; @@ -1977,7 +1974,7 @@ static int cqspi_probe(struct platform_device *pdev) ret = cqspi_request_mmap_dma(cqspi); if (ret == -EPROBE_DEFER) { dev_err_probe(&pdev->dev, ret, "Failed to request mmap DMA\n"); - goto disable_controller; + goto disable_rpm; } } @@ -1995,14 +1992,16 @@ static int cqspi_probe(struct platform_device *pdev) release_dma_chan: if (cqspi->rx_chan) dma_release_channel(cqspi->rx_chan); -disable_controller: +disable_rpm: + if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { + pm_runtime_disable(dev); + pm_runtime_set_suspended(dev); + pm_runtime_put_noidle(dev); + pm_runtime_dont_use_autosuspend(dev); + } cqspi_controller_enable(cqspi, 0); disable_clks: - if (pm_runtime_get_sync(&pdev->dev) >= 0) - clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); -disable_rpm: - if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) - pm_runtime_disable(dev); + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); return ret; } @@ -2026,18 +2025,19 @@ static void cqspi_remove(struct platform_device *pdev) if (cqspi->rx_chan) dma_release_channel(cqspi->rx_chan); - cqspi_controller_enable(cqspi, 0); - - if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) ret = pm_runtime_get_sync(&pdev->dev); - if (ret >= 0) + if (ret >= 0) { + cqspi_controller_enable(cqspi, 0); clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); + } if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { - pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + pm_runtime_put_noidle(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); } } diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c index 08d7dabe818d..891e2ba36958 100644 --- a/drivers/spi/spi-cadence.c +++ b/drivers/spi/spi-cadence.c @@ -741,7 +741,6 @@ static int cdns_spi_probe(struct platform_device *pdev) /* Set to default valid value */ ctlr->max_speed_hz = xspi->clk_rate / 4; xspi->speed_hz = ctlr->max_speed_hz; - pm_runtime_put_autosuspend(&pdev->dev); } else { ctlr->mode_bits |= SPI_NO_CS; ctlr->target_abort = cdns_target_abort; @@ -752,12 +751,17 @@ static int cdns_spi_probe(struct platform_device *pdev) goto clk_dis_all; } + if (!spi_controller_is_target(ctlr)) + pm_runtime_put_autosuspend(&pdev->dev); + return ret; clk_dis_all: if (!spi_controller_is_target(ctlr)) { pm_runtime_disable(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); + pm_runtime_put_noidle(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); } remove_ctlr: spi_controller_put(ctlr); @@ -776,16 +780,23 @@ static void cdns_spi_remove(struct platform_device *pdev) { struct spi_controller *ctlr = platform_get_drvdata(pdev); struct cdns_spi *xspi = spi_controller_get_devdata(ctlr); + int ret = 0; + + if (!spi_controller_is_target(ctlr)) + ret = pm_runtime_get_sync(&pdev->dev); spi_controller_get(ctlr); spi_unregister_controller(ctlr); - cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); + if (ret >= 0) + cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); if (!spi_controller_is_target(ctlr)) { pm_runtime_disable(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); + pm_runtime_put_noidle(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); } spi_controller_put(ctlr); diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 14cd1b9d9793..231fbcf0e7aa 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -98,7 +98,6 @@ #define CR0_FRF_MICROWIRE 0x2 #define CR0_XFM_OFFSET 18 -#define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) #define CR0_XFM_TR 0x0 #define CR0_XFM_TO 0x1 #define CR0_XFM_RO 0x2 @@ -109,8 +108,6 @@ #define CR0_SOI_OFFSET 23 -#define CR0_MTM_OFFSET 0x21 - /* Bit fields in SER, 2bit */ #define SER_MASK 0x3 @@ -357,7 +354,8 @@ static irqreturn_t rockchip_spi_isr(int irq, void *dev_id) struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); /* When int_cs_inactive comes, spi target abort */ - if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) { + if (rs->cs_inactive && + (readl_relaxed(rs->regs + ROCKCHIP_SPI_ISR) & INT_CS_INACTIVE)) { ctlr->target_abort(ctlr); writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); diff --git a/drivers/spi/spi-rzv2h-rspi.c b/drivers/spi/spi-rzv2h-rspi.c index f45af5884638..1655efda7d20 100644 --- a/drivers/spi/spi-rzv2h-rspi.c +++ b/drivers/spi/spi-rzv2h-rspi.c @@ -579,7 +579,7 @@ static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv *rspi, u32 hz) rspi->info->find_pclk_rate(rspi->pclk, hz, &best_clock); if (!best_clock.clk_rate) - return -EINVAL; + return 0; ret = clk_set_rate(best_clock.clk, best_clock.clk_rate); if (ret) diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c index 15ba592236e8..725a49a0eee7 100644 --- a/drivers/xen/privcmd.c +++ b/drivers/xen/privcmd.c @@ -1620,6 +1620,12 @@ static void privcmd_close(struct vm_area_struct *vma) kvfree(pages); } +static int privcmd_may_split(struct vm_area_struct *area, unsigned long addr) +{ + /* Forbid splitting, avoids double free via privcmd_close(). */ + return -EINVAL; +} + static vm_fault_t privcmd_fault(struct vm_fault *vmf) { printk(KERN_DEBUG "privcmd_fault: vma=%p %lx-%lx, pgoff=%lx, uv=%p\n", @@ -1631,6 +1637,7 @@ static vm_fault_t privcmd_fault(struct vm_fault *vmf) static const struct vm_operations_struct privcmd_vm_ops = { .close = privcmd_close, + .may_split = privcmd_may_split, .fault = privcmd_fault }; diff --git a/drivers/xen/sys-hypervisor.c b/drivers/xen/sys-hypervisor.c index b1bb01ba82f8..91923242a5ae 100644 --- a/drivers/xen/sys-hypervisor.c +++ b/drivers/xen/sys-hypervisor.c @@ -366,6 +366,8 @@ static ssize_t buildid_show(struct hyp_sysfs_attr *attr, char *buffer) ret = sprintf(buffer, ""); return ret; } + if (ret > PAGE_SIZE) + return -ENOSPC; buildid = kmalloc(sizeof(*buildid) + ret, GFP_KERNEL); if (!buildid) @@ -373,8 +375,10 @@ static ssize_t buildid_show(struct hyp_sysfs_attr *attr, char *buffer) buildid->len = ret; ret = HYPERVISOR_xen_version(XENVER_build_id, buildid); - if (ret > 0) - ret = sprintf(buffer, "%s", buildid->buf); + if (ret > 0) { + /* Build id is binary, not a string. */ + memcpy(buffer, buildid->buf, ret); + } kfree(buildid); return ret; diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c index ca3e4b99aec2..2275189b7860 100644 --- a/fs/btrfs/extent_io.c +++ b/fs/btrfs/extent_io.c @@ -4641,7 +4641,8 @@ int try_release_extent_buffer(struct folio *folio) * to read the block we will not block on anything. */ void btrfs_readahead_tree_block(struct btrfs_fs_info *fs_info, - u64 bytenr, u64 owner_root, u64 gen, int level) + u64 bytenr, u64 owner_root, u64 gen, int level, + const struct btrfs_key *first_key) { struct btrfs_tree_parent_check check = { .level = level, @@ -4650,6 +4651,11 @@ void btrfs_readahead_tree_block(struct btrfs_fs_info *fs_info, struct extent_buffer *eb; int ret; + if (first_key) { + memcpy(&check.first_key, first_key, sizeof(struct btrfs_key)); + check.has_first_key = true; + } + eb = btrfs_find_create_tree_block(fs_info, bytenr, owner_root, level); if (IS_ERR(eb)) return; @@ -4677,9 +4683,13 @@ void btrfs_readahead_tree_block(struct btrfs_fs_info *fs_info, */ void btrfs_readahead_node_child(struct extent_buffer *node, int slot) { + struct btrfs_key node_key; + + btrfs_node_key_to_cpu(node, &node_key, slot); btrfs_readahead_tree_block(node->fs_info, btrfs_node_blockptr(node, slot), btrfs_header_owner(node), btrfs_node_ptr_generation(node, slot), - btrfs_header_level(node) - 1); + btrfs_header_level(node) - 1, + &node_key); } diff --git a/fs/btrfs/extent_io.h b/fs/btrfs/extent_io.h index fd209233317f..b310a5145cf6 100644 --- a/fs/btrfs/extent_io.h +++ b/fs/btrfs/extent_io.h @@ -287,7 +287,8 @@ static inline void wait_on_extent_buffer_writeback(struct extent_buffer *eb) } void btrfs_readahead_tree_block(struct btrfs_fs_info *fs_info, - u64 bytenr, u64 owner_root, u64 gen, int level); + u64 bytenr, u64 owner_root, u64 gen, int level, + const struct btrfs_key *first_key); void btrfs_readahead_node_child(struct extent_buffer *node, int slot); /* Note: this can be used in for loops without caching the value in a variable. */ diff --git a/fs/btrfs/free-space-tree.c b/fs/btrfs/free-space-tree.c index 9efd1ec90f03..472b3060e5ac 100644 --- a/fs/btrfs/free-space-tree.c +++ b/fs/btrfs/free-space-tree.c @@ -259,7 +259,11 @@ int btrfs_convert_free_space_to_bitmaps(struct btrfs_trans_handle *trans, nr++; path->slots[0]--; } else { - ASSERT(0); + btrfs_err(fs_info, "unexpected free space tree key type %u", + found_key.type); + ret = -EUCLEAN; + btrfs_abort_transaction(trans, ret); + goto out; } } @@ -405,7 +409,11 @@ int btrfs_convert_free_space_to_extents(struct btrfs_trans_handle *trans, nr++; } else { - ASSERT(0); + btrfs_err(fs_info, "unexpected free space tree key type %u", + found_key.type); + ret = -EUCLEAN; + btrfs_abort_transaction(trans, ret); + goto out; } } @@ -1518,7 +1526,11 @@ int btrfs_remove_block_group_free_space(struct btrfs_trans_handle *trans, nr++; path->slots[0]--; } else { - ASSERT(0); + btrfs_err(trans->fs_info, "unexpected free space tree key type %u", + found_key.type); + ret = -EUCLEAN; + btrfs_abort_transaction(trans, ret); + return ret; } } diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c index 40474014c03f..906d5c21ebc4 100644 --- a/fs/btrfs/inode.c +++ b/fs/btrfs/inode.c @@ -1153,7 +1153,7 @@ static void submit_one_async_extent(struct async_chunk *async_chunk, NULL, &cached, EXTENT_LOCKED | EXTENT_DELALLOC | EXTENT_DELALLOC_NEW | - EXTENT_DEFRAG | EXTENT_DO_ACCOUNTING, + EXTENT_DEFRAG | EXTENT_CLEAR_META_RESV, PAGE_UNLOCK | PAGE_START_WRITEBACK | PAGE_END_WRITEBACK); if (async_extent->cb) @@ -4959,6 +4959,8 @@ static int btrfs_rmdir(struct inode *vfs_dir, struct dentry *dentry) if (ret) goto out; + btrfs_record_unlink_dir(trans, dir, inode, false); + /* now the directory is empty */ ret = btrfs_unlink_inode(trans, dir, inode, &fname.disk_name); if (!ret) diff --git a/fs/btrfs/ioctl.c b/fs/btrfs/ioctl.c index b2e447f5005c..a39460bf68a7 100644 --- a/fs/btrfs/ioctl.c +++ b/fs/btrfs/ioctl.c @@ -5102,7 +5102,6 @@ static int btrfs_ioctl_subvol_sync(struct btrfs_fs_info *fs_info, void __user *a return 0; } -#ifdef CONFIG_BTRFS_EXPERIMENTAL static int btrfs_ioctl_shutdown(struct btrfs_fs_info *fs_info, unsigned long arg) { int ret = 0; @@ -5134,10 +5133,12 @@ static int btrfs_ioctl_shutdown(struct btrfs_fs_info *fs_info, unsigned long arg case BTRFS_SHUTDOWN_FLAGS_NOLOGFLUSH: btrfs_force_shutdown(fs_info); break; + default: + ret = -EINVAL; + break; } return ret; } -#endif long btrfs_ioctl(struct file *file, unsigned int cmd, unsigned long arg) @@ -5294,10 +5295,8 @@ long btrfs_ioctl(struct file *file, unsigned int #endif case BTRFS_IOC_SUBVOL_SYNC_WAIT: return btrfs_ioctl_subvol_sync(fs_info, argp); -#ifdef CONFIG_BTRFS_EXPERIMENTAL case BTRFS_IOC_SHUTDOWN: return btrfs_ioctl_shutdown(fs_info, arg); -#endif } return -ENOTTY; diff --git a/fs/btrfs/raid-stripe-tree.c b/fs/btrfs/raid-stripe-tree.c index 638c4ad572c9..4b0186c83ad1 100644 --- a/fs/btrfs/raid-stripe-tree.c +++ b/fs/btrfs/raid-stripe-tree.c @@ -45,8 +45,11 @@ static int btrfs_partially_delete_raid_extent(struct btrfs_trans_handle *trans, for (int i = 0; i < btrfs_num_raid_stripes(item_size); i++) { struct btrfs_raid_stride *stride = &extent->strides[i]; + u64 devid; u64 phys; + devid = btrfs_raid_stride_devid(leaf, stride); + btrfs_set_stack_raid_stride_devid(&newitem->strides[i], devid); phys = btrfs_raid_stride_physical(leaf, stride) + frontpad; btrfs_set_stack_raid_stride_physical(&newitem->strides[i], phys); } @@ -95,14 +98,26 @@ int btrfs_delete_raid_extent(struct btrfs_trans_handle *trans, u64 start, u64 le while (1) { key.objectid = start; key.type = BTRFS_RAID_STRIPE_KEY; - key.offset = 0; + key.offset = (u64)-1; ret = btrfs_search_slot(trans, stripe_root, &key, path, -1, 1); if (ret < 0) break; - if (path->slots[0] == btrfs_header_nritems(path->nodes[0])) - path->slots[0]--; + /* + * Search with offset=(u64)-1 ensures we land on the correct + * leaf even when the target entry is the first item on a leaf. + * Since no real entry has offset=(u64)-1, ret is always 1 and + * slot points past the last entry with objectid==start (or + * past the end of the leaf if that entry is the last item). + * Back up one slot to find the actual entry. + */ + if (path->slots[0] == 0) { + /* No entry with objectid <= start exists. */ + ret = 0; + break; + } + path->slots[0]--; leaf = path->nodes[0]; slot = path->slots[0]; @@ -123,7 +138,7 @@ int btrfs_delete_raid_extent(struct btrfs_trans_handle *trans, u64 start, u64 le */ if (found_start > start) { if (slot == 0) { - ret = btrfs_previous_item(stripe_root, path, start, + ret = btrfs_previous_item(stripe_root, path, 0, BTRFS_RAID_STRIPE_KEY); if (ret) { if (ret > 0) @@ -139,7 +154,10 @@ int btrfs_delete_raid_extent(struct btrfs_trans_handle *trans, u64 start, u64 le btrfs_item_key_to_cpu(leaf, &key, slot); found_start = key.objectid; found_end = found_start + key.offset; - ASSERT(found_start <= start); + if (found_start > start || found_end <= start) { + ret = -ENOENT; + break; + } } if (key.type != BTRFS_RAID_STRIPE_KEY) @@ -176,9 +194,19 @@ int btrfs_delete_raid_extent(struct btrfs_trans_handle *trans, u64 start, u64 le /* The "right" item. */ ret = btrfs_duplicate_item(trans, stripe_root, path, &newkey); + if (ret == -EAGAIN) { + btrfs_release_path(path); + continue; + } if (ret) break; + /* + * btrfs_duplicate_item() may have triggered a leaf + * split via setup_leaf_for_split(), so we must refresh + * our leaf pointer from the path. + */ + leaf = path->nodes[0]; item_size = btrfs_item_size(leaf, path->slots[0]); extent = btrfs_item_ptr(leaf, path->slots[0], struct btrfs_stripe_extent); @@ -195,8 +223,9 @@ int btrfs_delete_raid_extent(struct btrfs_trans_handle *trans, u64 start, u64 le /* The "left" item. */ path->slots[0]--; btrfs_item_key_to_cpu(leaf, &key, path->slots[0]); - btrfs_partially_delete_raid_extent(trans, path, &key, - diff_start, 0); + ret = btrfs_partially_delete_raid_extent(trans, path, + &key, + diff_start, 0); break; } @@ -212,8 +241,11 @@ int btrfs_delete_raid_extent(struct btrfs_trans_handle *trans, u64 start, u64 le if (found_start < start) { u64 diff_start = start - found_start; - btrfs_partially_delete_raid_extent(trans, path, &key, - diff_start, 0); + ret = btrfs_partially_delete_raid_extent(trans, path, + &key, + diff_start, 0); + if (ret) + break; start += (key.offset - diff_start); length -= (key.offset - diff_start); @@ -236,9 +268,10 @@ int btrfs_delete_raid_extent(struct btrfs_trans_handle *trans, u64 start, u64 le if (found_end > end) { u64 diff_end = found_end - end; - btrfs_partially_delete_raid_extent(trans, path, &key, - key.offset - length, - length); + ret = btrfs_partially_delete_raid_extent(trans, path, + &key, + key.offset - length, + length); ASSERT(key.offset - diff_end == length); break; } diff --git a/fs/btrfs/relocation.c b/fs/btrfs/relocation.c index 1c42c5180bdd..3ebaf5880125 100644 --- a/fs/btrfs/relocation.c +++ b/fs/btrfs/relocation.c @@ -2607,7 +2607,7 @@ int relocate_tree_blocks(struct btrfs_trans_handle *trans, if (!block->key_ready) btrfs_readahead_tree_block(fs_info, block->bytenr, block->owner, 0, - block->level); + block->level, NULL); } /* Get first keys */ @@ -3876,7 +3876,7 @@ static int add_remap_tree_entries(struct btrfs_trans_handle *trans, struct btrfs ret = btrfs_insert_empty_items(trans, fs_info->remap_root, path, &batch); btrfs_release_path(path); - if (num_entries <= max_items) + if (ret || num_entries <= max_items) break; num_entries -= max_items; @@ -4174,6 +4174,12 @@ static int move_existing_remap(struct btrfs_fs_info *fs_info, return ret; } + if (ins.offset < length) { + spin_lock(&sinfo->lock); + btrfs_space_info_update_bytes_may_use(sinfo, ins.offset - length); + spin_unlock(&sinfo->lock); + } + dest_addr = ins.objectid; dest_length = ins.offset; @@ -5000,6 +5006,12 @@ static int do_remap_reloc_trans(struct btrfs_fs_info *fs_info, return ret; } + if (ins.offset < remap_length) { + spin_lock(&sinfo->lock); + btrfs_space_info_update_bytes_may_use(sinfo, ins.offset - remap_length); + spin_unlock(&sinfo->lock); + } + made_reservation = true; new_addr = ins.objectid; @@ -5023,21 +5035,27 @@ static int do_remap_reloc_trans(struct btrfs_fs_info *fs_info, if (bg_needs_free_space) { ret = btrfs_add_block_group_free_space(trans, dest_bg); - if (ret) + if (ret) { + btrfs_abort_transaction(trans, ret); goto fail; + } } ret = copy_remapped_data(fs_info, start, new_addr, length); - if (ret) + if (ret) { + btrfs_abort_transaction(trans, ret); goto fail; + } ret = btrfs_remove_from_free_space_tree(trans, new_addr, length); - if (ret) + if (ret) { + btrfs_abort_transaction(trans, ret); goto fail; + } ret = add_remap_entry(trans, path, src_bg, start, new_addr, length); if (ret) { - btrfs_add_to_free_space_tree(trans, new_addr, length); + btrfs_abort_transaction(trans, ret); goto fail; } diff --git a/fs/isofs/export.c b/fs/isofs/export.c index 421d247fae52..78f80c1a5c54 100644 --- a/fs/isofs/export.c +++ b/fs/isofs/export.c @@ -24,7 +24,7 @@ isofs_export_iget(struct super_block *sb, { struct inode *inode; - if (block == 0) + if (block == 0 || block >= ISOFS_SB(sb)->s_nzones) return ERR_PTR(-ESTALE); inode = isofs_iget(sb, block, offset); if (IS_ERR(inode)) diff --git a/fs/isofs/namei.c b/fs/isofs/namei.c index 8dd3911717e0..3ace3d6a55e7 100644 --- a/fs/isofs/namei.c +++ b/fs/isofs/namei.c @@ -10,20 +10,13 @@ #include #include "isofs.h" -/* - * ok, we cannot use strncmp, as the name is not in our data space. - * Thus we'll have to use isofs_match. No big problem. Match also makes - * some sanity tests. - */ static int isofs_cmp(struct dentry *dentry, const char *compare, int dlen) { - struct qstr qstr; - qstr.name = compare; - qstr.len = dlen; if (likely(!dentry->d_op)) return dentry->d_name.len != dlen || memcmp(dentry->d_name.name, compare, dlen); - return dentry->d_op->d_compare(NULL, dentry->d_name.len, dentry->d_name.name, &qstr); + return dentry->d_op->d_compare(NULL, dentry->d_name.len, dentry->d_name.name, + &QSTR_LEN(compare, dlen)); } /* diff --git a/fs/isofs/rock.c b/fs/isofs/rock.c index 6fe6dbd0c740..1232fab59a4e 100644 --- a/fs/isofs/rock.c +++ b/fs/isofs/rock.c @@ -101,6 +101,15 @@ static int rock_continue(struct rock_state *rs) goto out; } + if ((unsigned)rs->cont_extent >= ISOFS_SB(rs->inode->i_sb)->s_nzones) { + printk(KERN_NOTICE "rock: corrupted directory entry. " + "extent=%u out of volume (nzones=%lu)\n", + (unsigned)rs->cont_extent, + ISOFS_SB(rs->inode->i_sb)->s_nzones); + ret = -EIO; + goto out; + } + if (rs->cont_extent) { struct buffer_head *bh; diff --git a/fs/notify/fanotify/fanotify.c b/fs/notify/fanotify/fanotify.c index bfe884d624e7..38290b9c07f7 100644 --- a/fs/notify/fanotify/fanotify.c +++ b/fs/notify/fanotify/fanotify.c @@ -457,7 +457,7 @@ static int fanotify_encode_fh(struct fanotify_fh *fh, struct inode *inode, /* * Unlike file_handle, type and len of struct fanotify_fh are u8. * Traditionally, filesystem return handle_type < 0xff, but there - * is no enforecement for that in vfs. + * is no enforcement for that in vfs. */ BUILD_BUG_ON(MAX_HANDLE_SZ > 0xff || FILEID_INVALID > 0xff); if (type <= 0 || type >= FILEID_INVALID || fh_len != dwords << 2) diff --git a/fs/notify/fsnotify.c b/fs/notify/fsnotify.c index b7198c4744e3..2dac70b99b0d 100644 --- a/fs/notify/fsnotify.c +++ b/fs/notify/fsnotify.c @@ -388,7 +388,7 @@ static struct fsnotify_mark *fsnotify_first_mark(struct fsnotify_mark_connector return hlist_entry_safe(node, struct fsnotify_mark, obj_list); } -static struct fsnotify_mark *fsnotify_next_mark(struct fsnotify_mark *mark) +struct fsnotify_mark *fsnotify_next_mark(struct fsnotify_mark *mark) { struct hlist_node *node = NULL; diff --git a/fs/notify/mark.c b/fs/notify/mark.c index c2ed5b11b0fe..e256b420100d 100644 --- a/fs/notify/mark.c +++ b/fs/notify/mark.c @@ -238,7 +238,12 @@ static struct inode *fsnotify_update_iref(struct fsnotify_mark_connector *conn, return inode; } -static void *__fsnotify_recalc_mask(struct fsnotify_mark_connector *conn) +/* + * Calculate mask of events for a list of marks. + * + * Return true if any of the attached marks want to hold an inode reference. + */ +static bool __fsnotify_recalc_mask(struct fsnotify_mark_connector *conn) { u32 new_mask = 0; bool want_iref = false; @@ -262,6 +267,34 @@ static void *__fsnotify_recalc_mask(struct fsnotify_mark_connector *conn) */ WRITE_ONCE(*fsnotify_conn_mask_p(conn), new_mask); + return want_iref; +} + +/* + * Calculate mask of events for a list of marks after attach/modify mark + * and get an inode reference for the connector if needed. + * + * A concurrent add of evictable mark and detach of non-evictable mark can + * lead to __fsnotify_recalc_mask() returning false want_iref, but in this + * case we defer clearing iref to fsnotify_recalc_mask_clear_iref() called + * from fsnotify_put_mark(). + */ +static void fsnotify_recalc_mask_set_iref(struct fsnotify_mark_connector *conn) +{ + bool has_iref = conn->flags & FSNOTIFY_CONN_FLAG_HAS_IREF; + bool want_iref = __fsnotify_recalc_mask(conn) || has_iref; + + (void) fsnotify_update_iref(conn, want_iref); +} + +/* + * Calculate mask of events for a list of marks after detach mark + * and return the inode object if its reference is no longer needed. + */ +static void *fsnotify_recalc_mask_clear_iref(struct fsnotify_mark_connector *conn) +{ + bool want_iref = __fsnotify_recalc_mask(conn); + return fsnotify_update_iref(conn, want_iref); } @@ -298,7 +331,7 @@ void fsnotify_recalc_mask(struct fsnotify_mark_connector *conn) spin_lock(&conn->lock); update_children = !fsnotify_conn_watches_children(conn); - __fsnotify_recalc_mask(conn); + fsnotify_recalc_mask_set_iref(conn); update_children &= fsnotify_conn_watches_children(conn); spin_unlock(&conn->lock); /* @@ -419,7 +452,7 @@ void fsnotify_put_mark(struct fsnotify_mark *mark) /* Update watched objects after detaching mark */ if (sb) fsnotify_update_sb_watchers(sb, conn); - objp = __fsnotify_recalc_mask(conn); + objp = fsnotify_recalc_mask_clear_iref(conn); type = conn->type; } WRITE_ONCE(mark->connector, NULL); @@ -457,9 +490,6 @@ EXPORT_SYMBOL_GPL(fsnotify_put_mark); */ static bool fsnotify_get_mark_safe(struct fsnotify_mark *mark) { - if (!mark) - return true; - if (refcount_inc_not_zero(&mark->refcnt)) { spin_lock(&mark->lock); if (mark->flags & FSNOTIFY_MARK_FLAG_ATTACHED) { @@ -500,15 +530,22 @@ bool fsnotify_prepare_user_wait(struct fsnotify_iter_info *iter_info) int type; fsnotify_foreach_iter_type(type) { + struct fsnotify_mark *mark = iter_info->marks[type]; + /* This can fail if mark is being removed */ - if (!fsnotify_get_mark_safe(iter_info->marks[type])) { - __release(&fsnotify_mark_srcu); - goto fail; + while (mark && !fsnotify_get_mark_safe(mark)) { + if (mark->group == iter_info->current_group) { + __release(&fsnotify_mark_srcu); + goto fail; + } + /* This is a mark in an unrelated group, skip */ + mark = fsnotify_next_mark(mark); + iter_info->marks[type] = mark; } } /* - * Now that both marks are pinned by refcount in the inode / vfsmount + * Now that all marks are pinned by refcount in the inode / vfsmount / etc * lists, we can drop SRCU lock, and safely resume the list iteration * once userspace returns. */ diff --git a/fs/ntfs/bitmap.c b/fs/ntfs/bitmap.c index 656d802333e3..b1436b3151b9 100644 --- a/fs/ntfs/bitmap.c +++ b/fs/ntfs/bitmap.c @@ -125,7 +125,7 @@ int __ntfs_bitmap_set_bits_in_run(struct inode *vi, const s64 start_bit, struct address_space *mapping; struct folio *folio; u8 *kaddr; - int pos, len; + int pos, len, err; u8 bit; struct ntfs_inode *ni = NTFS_I(vi); struct ntfs_volume *vol = ni->vol; @@ -201,8 +201,10 @@ int __ntfs_bitmap_set_bits_in_run(struct inode *vi, const s64 start_bit, /* If we are not in the last page, deal with all subsequent pages. */ while (index < end_index) { - if (cnt <= 0) + if (cnt <= 0) { + err = -EIO; goto rollback; + } /* Update @index and get the next folio. */ folio_mark_dirty(folio); @@ -214,6 +216,7 @@ int __ntfs_bitmap_set_bits_in_run(struct inode *vi, const s64 start_bit, ntfs_error(vi->i_sb, "Failed to map subsequent page (error %li), aborting.", PTR_ERR(folio)); + err = PTR_ERR(folio); goto rollback; } @@ -265,7 +268,7 @@ int __ntfs_bitmap_set_bits_in_run(struct inode *vi, const s64 start_bit, * - @count - @cnt is the number of bits that have been modified */ if (is_rollback) - return PTR_ERR(folio); + return err; if (count != cnt) pos = __ntfs_bitmap_set_bits_in_run(vi, start_bit, count - cnt, value ? 0 : 1, true); @@ -274,14 +277,14 @@ int __ntfs_bitmap_set_bits_in_run(struct inode *vi, const s64 start_bit, if (!pos) { /* Rollback was successful. */ ntfs_error(vi->i_sb, - "Failed to map subsequent page (error %li), aborting.", - PTR_ERR(folio)); + "Failed to map subsequent page (error %i), aborting.", + err); } else { /* Rollback failed. */ ntfs_error(vi->i_sb, - "Failed to map subsequent page (error %li) and rollback failed (error %i). Aborting and leaving inconsistent metadata. Unmount and run chkdsk.", - PTR_ERR(folio), pos); + "Failed to map subsequent page (error %i) and rollback failed (error %i). Aborting and leaving inconsistent metadata. Unmount and run chkdsk.", + err, pos); NVolSetErrors(NTFS_SB(vi->i_sb)); } - return PTR_ERR(folio); + return err; } diff --git a/fs/ntfs/dir.c b/fs/ntfs/dir.c index bfa904d2ce66..20f5c7074bdd 100644 --- a/fs/ntfs/dir.c +++ b/fs/ntfs/dir.c @@ -911,8 +911,8 @@ static int ntfs_readdir(struct file *file, struct dir_context *actor) if (next->flags & INDEX_ENTRY_NODE) { next = ntfs_index_walk_down(next, ictx); - if (!next) { - err = -EIO; + if (IS_ERR(next)) { + err = PTR_ERR(next); goto out; } } @@ -920,7 +920,14 @@ static int ntfs_readdir(struct file *file, struct dir_context *actor) if (next && !(next->flags & INDEX_ENTRY_END)) goto nextdir; - while ((next = ntfs_index_next(next, ictx)) != NULL) { + while (1) { + next = ntfs_index_next(next, ictx); + if (IS_ERR(next)) { + err = PTR_ERR(next); + goto out; + } + if (!next) + break; nextdir: /* Check the consistency of an index entry */ if (ntfs_index_entry_inconsistent(ictx, vol, next, COLLATION_FILE_NAME, diff --git a/fs/ntfs/index.c b/fs/ntfs/index.c index 2080f3969137..a547bdcfa456 100644 --- a/fs/ntfs/index.c +++ b/fs/ntfs/index.c @@ -1969,15 +1969,19 @@ int ntfs_index_remove(struct ntfs_inode *dir_ni, const void *key, const u32 keyl struct index_entry *ntfs_index_walk_down(struct index_entry *ie, struct ntfs_index_context *ictx) { struct index_entry *entry; + struct index_block *ib; s64 vcn; entry = ie; do { vcn = ntfs_ie_get_vcn(entry); if (ictx->is_in_root) { + ib = kvzalloc(ictx->block_size, GFP_NOFS); + if (!ib) + return ERR_PTR(-ENOMEM); /* down from level zero */ ictx->ir = NULL; - ictx->ib = kvzalloc(ictx->block_size, GFP_NOFS); + ictx->ib = ib; ictx->pindex = 1; ictx->is_in_root = false; } else { @@ -1991,8 +1995,8 @@ struct index_entry *ntfs_index_walk_down(struct index_entry *ie, struct ntfs_ind ictx->entry = ntfs_ie_get_first(&ictx->ib->index); entry = ictx->entry; } else - entry = NULL; - } while (entry && (entry->flags & INDEX_ENTRY_NODE)); + entry = ERR_PTR(-EIO); + } while (!IS_ERR(entry) && (entry->flags & INDEX_ENTRY_NODE)); return entry; } @@ -2097,10 +2101,15 @@ struct index_entry *ntfs_index_next(struct index_entry *ie, struct ntfs_index_co /* walk down if it has a subnode */ if (flags & INDEX_ENTRY_NODE) { - if (!ictx->ia_ni) + if (!ictx->ia_ni) { ictx->ia_ni = ntfs_ia_open(ictx, ictx->idx_ni); + if (!ictx->ia_ni) + return ERR_PTR(-EIO); + } next = ntfs_index_walk_down(next, ictx); + if (IS_ERR(next)) + return next; } else { /* walk up it has no subnode, nor data */ diff --git a/fs/ntfs/iomap.c b/fs/ntfs/iomap.c index 74a4d3e971f4..dc7d8c893a69 100644 --- a/fs/ntfs/iomap.c +++ b/fs/ntfs/iomap.c @@ -788,8 +788,7 @@ static int ntfs_write_iomap_end_resident(struct inode *inode, loff_t pos, ctx = ntfs_attr_get_search_ctx(ni, NULL); if (!ctx) { written = -ENOMEM; - mutex_unlock(&ni->mrec_lock); - return written; + goto err_out; } err = ntfs_attr_lookup(ni->type, ni->name, ni->name_len, @@ -810,7 +809,8 @@ static int ntfs_write_iomap_end_resident(struct inode *inode, loff_t pos, memcpy(kattr + pos, iomap_inline_data(iomap, pos), written); mark_mft_record_dirty(ctx->ntfs_ino); err_out: - ntfs_attr_put_search_ctx(ctx); + if (ctx) + ntfs_attr_put_search_ctx(ctx); put_page(ipage); mutex_unlock(&ni->mrec_lock); return written; diff --git a/fs/ntfs/namei.c b/fs/ntfs/namei.c index 10894de519c3..96c450e62efc 100644 --- a/fs/ntfs/namei.c +++ b/fs/ntfs/namei.c @@ -945,7 +945,8 @@ static int ntfs_delete(struct ntfs_inode *ni, struct ntfs_inode *dir_ni, ni_mrec = actx->base_mrec ? actx->base_mrec : actx->mrec; ni_mrec->link_count = cpu_to_le16(le16_to_cpu(ni_mrec->link_count) - 1); - drop_nlink(VFS_I(ni)); + if (!S_ISDIR(VFS_I(ni)->i_mode)) + drop_nlink(VFS_I(ni)); mark_mft_record_dirty(ni); if (looking_for_dos_name) { @@ -955,6 +956,13 @@ static int ntfs_delete(struct ntfs_inode *ni, struct ntfs_inode *dir_ni, goto search; } + /* + * For directories, Drop VFS nlink only when mft record link count + * becomes zero. Because we fixes VFS nlink to 1 for directories. + */ + if (S_ISDIR(VFS_I(ni)->i_mode) && !le16_to_cpu(ni_mrec->link_count)) + drop_nlink(VFS_I(ni)); + /* * If hard link count is not equal to zero then we are done. In other * case there are no reference to this inode left, so we should free all @@ -1221,7 +1229,8 @@ static int __ntfs_link(struct ntfs_inode *ni, struct ntfs_inode *dir_ni, } /* Increment hard links count. */ ni_mrec->link_count = cpu_to_le16(le16_to_cpu(ni_mrec->link_count) + 1); - inc_nlink(VFS_I(ni)); + if (!S_ISDIR(vi->i_mode)) + inc_nlink(VFS_I(ni)); /* Done! */ mark_mft_record_dirty(ni); diff --git a/fs/ntfs/reparse.c b/fs/ntfs/reparse.c index 8f60ec6f66c1..74713716813f 100644 --- a/fs/ntfs/reparse.c +++ b/fs/ntfs/reparse.c @@ -505,7 +505,6 @@ int ntfs_reparse_set_wsl_symlink(struct ntfs_inode *ni, struct reparse_point *reparse; struct wsl_link_reparse_data *data; - utarget = (char *)NULL; len = ntfs_ucstonls(ni->vol, target, target_len, &utarget, 0); if (len <= 0) return -EINVAL; @@ -514,7 +513,7 @@ int ntfs_reparse_set_wsl_symlink(struct ntfs_inode *ni, reparse = kvzalloc(reparse_len, GFP_NOFS); if (!reparse) { err = -ENOMEM; - kvfree(utarget); + kfree(utarget); } else { data = (struct wsl_link_reparse_data *)reparse->reparse_data; reparse->reparse_tag = IO_REPARSE_TAG_LX_SYMLINK; @@ -528,6 +527,8 @@ int ntfs_reparse_set_wsl_symlink(struct ntfs_inode *ni, kvfree(reparse); if (!err) ni->target = utarget; + else + kfree(utarget); } return err; } diff --git a/fs/ntfs/runlist.c b/fs/ntfs/runlist.c index b213b4976d2b..da21dbeaaf66 100644 --- a/fs/ntfs/runlist.c +++ b/fs/ntfs/runlist.c @@ -15,6 +15,8 @@ * Copyright (c) 2007-2022 Jean-Pierre Andre */ +#include + #include "ntfs.h" #include "attrib.h" @@ -739,6 +741,7 @@ struct runlist_element *ntfs_mapping_pairs_decompress(const struct ntfs_volume * int rlsize; /* Size of runlist buffer. */ u16 rlpos; /* Current runlist position in units of struct runlist_elements. */ u8 b; /* Current byte offset in buf. */ + u64 lowest_vcn; /* Raw on-disk lowest_vcn. */ #ifdef DEBUG /* Make sure attr exists and is non-resident. */ @@ -747,8 +750,14 @@ struct runlist_element *ntfs_mapping_pairs_decompress(const struct ntfs_volume * return ERR_PTR(-EINVAL); } #endif + lowest_vcn = le64_to_cpu(attr->data.non_resident.lowest_vcn); + /* Validate lowest_vcn from on-disk metadata to ensure it is sane. */ + if (overflows_type(lowest_vcn, vcn)) { + ntfs_error(vol->sb, "Invalid lowest_vcn in mapping pairs."); + return ERR_PTR(-EIO); + } /* Start at vcn = lowest_vcn and lcn 0. */ - vcn = le64_to_cpu(attr->data.non_resident.lowest_vcn); + vcn = lowest_vcn; lcn = 0; /* Get start of the mapping pairs array. */ buf = (u8 *)attr + @@ -823,8 +832,17 @@ struct runlist_element *ntfs_mapping_pairs_decompress(const struct ntfs_volume * * element. */ rl[rlpos].length = deltaxcn; - /* Increment the current vcn by the current run length. */ - vcn += deltaxcn; + /* + * Increment the current vcn by the current run length. + * Guard against s64 overflow from a crafted mapping + * pairs array to preserve the monotonically-increasing + * vcn invariant. + */ + if (unlikely(check_add_overflow(vcn, deltaxcn, &vcn))) { + ntfs_error(vol->sb, "VCN overflow in mapping pairs array."); + goto err_out; + } + /* * There might be no lcn change at all, as is the case for * sparse clusters on NTFS 3.0+, in which case we set the lcn diff --git a/fs/smb/client/cifsproto.h b/fs/smb/client/cifsproto.h index 4a25afda9448..79d891f7df1a 100644 --- a/fs/smb/client/cifsproto.h +++ b/fs/smb/client/cifsproto.h @@ -89,7 +89,6 @@ int cifs_handle_standard(struct TCP_Server_Info *server, struct mid_q_entry *mid); char *smb3_fs_context_fullpath(const struct smb3_fs_context *ctx, char dirsep); int smb3_parse_devname(const char *devname, struct smb3_fs_context *ctx); -int smb3_parse_opt(const char *options, const char *key, char **val); int cifs_ipaddr_cmp(struct sockaddr *srcaddr, struct sockaddr *rhs); bool cifs_match_ipaddr(struct sockaddr *srcaddr, struct sockaddr *rhs); int cifs_discard_remaining_data(struct TCP_Server_Info *server); diff --git a/fs/smb/client/fs_context.c b/fs/smb/client/fs_context.c index b9544eb0381b..b63ec7ab6e51 100644 --- a/fs/smb/client/fs_context.c +++ b/fs/smb/client/fs_context.c @@ -536,37 +536,6 @@ cifs_parse_smb_version(struct fs_context *fc, char *value, struct smb3_fs_contex return 0; } -int smb3_parse_opt(const char *options, const char *key, char **val) -{ - int rc = -ENOENT; - char *opts, *orig, *p; - - orig = opts = kstrdup(options, GFP_KERNEL); - if (!opts) - return -ENOMEM; - - while ((p = strsep(&opts, ","))) { - char *nval; - - if (!*p) - continue; - if (strncasecmp(p, key, strlen(key))) - continue; - nval = strchr(p, '='); - if (nval) { - if (nval == p) - continue; - *nval++ = 0; - *val = kstrdup(nval, GFP_KERNEL); - rc = !*val ? -ENOMEM : 0; - goto out; - } - } -out: - kfree(orig); - return rc; -} - /* * Remove duplicate path delimiters. Windows is supposed to do that * but there are some bugs that prevent rename from working if there are diff --git a/fs/smb/client/smb2inode.c b/fs/smb/client/smb2inode.c index c6dd282fc3a9..286912616c73 100644 --- a/fs/smb/client/smb2inode.c +++ b/fs/smb/client/smb2inode.c @@ -230,7 +230,7 @@ static int smb2_compound_op(const unsigned int xid, struct cifs_tcon *tcon, num_rqst = 0; server = cifs_pick_channel(ses); - vars = kzalloc_obj(*vars, GFP_ATOMIC); + vars = kzalloc_obj(*vars, GFP_KERNEL); if (vars == NULL) { rc = -ENOMEM; goto out; diff --git a/fs/smb/client/smb2ops.c b/fs/smb/client/smb2ops.c index 7f346ee50289..e6cb9b144530 100644 --- a/fs/smb/client/smb2ops.c +++ b/fs/smb/client/smb2ops.c @@ -111,10 +111,21 @@ smb2_add_credits(struct TCP_Server_Info *server, cifs_trace_rw_credits_zero_in_flight); } server->in_flight--; + + /* + * Rebalance credits when an op drains in_flight. For session setup, + * do this only when the total accumulated credits are high enough (>2) + * so that a newly established secondary channel can reserve credits for + * echoes and oplocks. We expect this to happen at the end of the final + * session setup response. + */ if (server->in_flight == 0 && ((optype & CIFS_OP_MASK) != CIFS_NEG_OP) && ((optype & CIFS_OP_MASK) != CIFS_SESS_OP)) rc = change_conf(server); + else if (server->in_flight == 0 && + ((optype & CIFS_OP_MASK) == CIFS_SESS_OP) && *val > 2) + rc = change_conf(server); /* * Sometimes server returns 0 credits on oplock break ack - we need to * rebalance credits in this case. diff --git a/fs/smb/server/connection.c b/fs/smb/server/connection.c index fbbc0529743f..c5aac4946cbe 100644 --- a/fs/smb/server/connection.c +++ b/fs/smb/server/connection.c @@ -540,24 +540,54 @@ int ksmbd_conn_transport_init(void) static void stop_sessions(void) { - struct ksmbd_conn *conn; + struct ksmbd_conn *conn, *target; struct ksmbd_transport *t; + bool any; int bkt; + /* + * Serialised via init_lock; no concurrent stop_sessions() can + * touch conn->stop_called, so writing it under the read lock is + * safe. + */ again: + target = NULL; + any = false; down_read(&conn_list_lock); hash_for_each(conn_list, bkt, conn, hlist) { - t = conn->transport; - ksmbd_conn_set_exiting(conn); - if (t->ops->shutdown) { - up_read(&conn_list_lock); - t->ops->shutdown(t); - down_read(&conn_list_lock); - } + any = true; + if (conn->stop_called) + continue; + atomic_inc(&conn->refcnt); + conn->stop_called = true; + /* + * Mark the connection EXITING while still holding the + * read lock so the selection and the status transition + * happen together. Do not regress a connection that has + * already advanced to RELEASING on its own (e.g. the + * handler exited its receive loop for an unrelated + * reason). + */ + if (READ_ONCE(conn->status) != KSMBD_SESS_RELEASING) + ksmbd_conn_set_exiting(conn); + target = conn; + break; } up_read(&conn_list_lock); - if (!hash_empty(conn_list)) { + if (target) { + t = target->transport; + if (t->ops->shutdown) + t->ops->shutdown(t); + if (atomic_dec_and_test(&target->refcnt)) { + ida_destroy(&target->async_ida); + t->ops->free_transport(t); + kfree(target); + } + goto again; + } + + if (any) { msleep(100); goto again; } diff --git a/fs/smb/server/connection.h b/fs/smb/server/connection.h index ae21a1bd4c70..de2d46941c93 100644 --- a/fs/smb/server/connection.h +++ b/fs/smb/server/connection.h @@ -49,6 +49,7 @@ struct ksmbd_conn { struct mutex srv_mutex; int status; unsigned int cli_cap; + bool stop_called; union { __be32 inet_addr; #if IS_ENABLED(CONFIG_IPV6) diff --git a/fs/smb/server/smb2pdu.c b/fs/smb/server/smb2pdu.c index 21825a69c29a..47b7af631f7b 100644 --- a/fs/smb/server/smb2pdu.c +++ b/fs/smb/server/smb2pdu.c @@ -3946,7 +3946,13 @@ static int smb2_populate_readdir_entry(struct ksmbd_conn *conn, int info_level, goto free_conv_name; } - struct_sz = readdir_info_level_struct_sz(info_level) + conv_len; + struct_sz = readdir_info_level_struct_sz(info_level); + if (struct_sz == -EOPNOTSUPP) { + rc = -EINVAL; + goto free_conv_name; + } + + struct_sz += conv_len; next_entry_offset = ALIGN(struct_sz, KSMBD_DIR_INFO_ALIGNMENT); d_info->last_entry_off_align = next_entry_offset - struct_sz; diff --git a/fs/udf/misc.c b/fs/udf/misc.c index 0788593b6a1d..6928e378fbbd 100644 --- a/fs/udf/misc.c +++ b/fs/udf/misc.c @@ -230,8 +230,12 @@ struct buffer_head *udf_read_tagged(struct super_block *sb, uint32_t block, } /* Verify the descriptor CRC */ - if (le16_to_cpu(tag_p->descCRCLength) + sizeof(struct tag) > sb->s_blocksize || - le16_to_cpu(tag_p->descCRC) == crc_itu_t(0, + if (le16_to_cpu(tag_p->descCRCLength) + sizeof(struct tag) > sb->s_blocksize) { + udf_err(sb, "block %u: CRC length %u exceeds block size\n", + block, le16_to_cpu(tag_p->descCRCLength)); + goto error_out; + } + if (le16_to_cpu(tag_p->descCRC) == crc_itu_t(0, bh->b_data + sizeof(struct tag), le16_to_cpu(tag_p->descCRCLength))) return bh; diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index b701b5f972cb..c41d9a7565cf 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -17,6 +17,8 @@ #include #include +struct notifier_block; + struct acpi_handle_list { u32 count; acpi_handle *handles; diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 4e15583e0d25..f72e00517eb3 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -1386,6 +1386,12 @@ enum acpi_einj_command_status { #define ACPI_EINJ_CXL_MEM_FATAL (1<<17) #define ACPI_EINJ_VENDOR_DEFINED (1<<31) +/* EINJV2 error types from EINJV2_GET_ERROR_TYPE (ACPI 6.6) */ + +#define ACPI_EINJV2_PROCESSOR (1) +#define ACPI_EINJV2_MEMORY (1<<1) +#define ACPI_EINJV2_PCIE (1<<2) + /******************************************************************************* * * ERST - Error Record Serialization Table (ACPI 4.0) diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h index 2cfe1d4bfc96..27658bfb5001 100644 --- a/include/drm/display/drm_dp_mst_helper.h +++ b/include/drm/display/drm_dp_mst_helper.h @@ -916,13 +916,13 @@ void drm_dp_mst_connector_early_unregister(struct drm_connector *connector, struct drm_dp_mst_port *port); struct drm_dp_mst_topology_state * -drm_atomic_get_mst_topology_state(struct drm_atomic_state *state, +drm_atomic_get_mst_topology_state(struct drm_atomic_commit *state, struct drm_dp_mst_topology_mgr *mgr); struct drm_dp_mst_topology_state * -drm_atomic_get_old_mst_topology_state(struct drm_atomic_state *state, +drm_atomic_get_old_mst_topology_state(struct drm_atomic_commit *state, struct drm_dp_mst_topology_mgr *mgr); struct drm_dp_mst_topology_state * -drm_atomic_get_new_mst_topology_state(struct drm_atomic_state *state, +drm_atomic_get_new_mst_topology_state(struct drm_atomic_commit *state, struct drm_dp_mst_topology_mgr *mgr); struct drm_dp_mst_atomic_payload * drm_atomic_get_mst_payload_state(struct drm_dp_mst_topology_state *state, @@ -931,31 +931,31 @@ bool drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, struct drm_dp_mst_port *parent); int __must_check -drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, +drm_dp_atomic_find_time_slots(struct drm_atomic_commit *state, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int pbn); -int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state *state, +int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_commit *state, struct drm_dp_mst_port *port, int pbn, bool enable); int __must_check -drm_dp_mst_add_affected_dsc_crtcs(struct drm_atomic_state *state, +drm_dp_mst_add_affected_dsc_crtcs(struct drm_atomic_commit *state, struct drm_dp_mst_topology_mgr *mgr); int __must_check -drm_dp_atomic_release_time_slots(struct drm_atomic_state *state, +drm_dp_atomic_release_time_slots(struct drm_atomic_commit *state, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port); -void drm_dp_mst_atomic_wait_for_dependencies(struct drm_atomic_state *state); -int __must_check drm_dp_mst_atomic_setup_commit(struct drm_atomic_state *state); +void drm_dp_mst_atomic_wait_for_dependencies(struct drm_atomic_commit *state); +int __must_check drm_dp_mst_atomic_setup_commit(struct drm_atomic_commit *state); int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, bool power_up); int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, struct drm_dp_query_stream_enc_status_ack_reply *status); -int __must_check drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state, +int __must_check drm_dp_mst_atomic_check_mgr(struct drm_atomic_commit *state, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_topology_state *mst_state, struct drm_dp_mst_port **failing_port); -int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state); +int __must_check drm_dp_mst_atomic_check(struct drm_atomic_commit *state); int __must_check drm_dp_mst_root_conn_atomic_check(struct drm_connector_state *new_conn_state, struct drm_dp_mst_topology_mgr *mgr); @@ -982,7 +982,7 @@ extern const struct drm_private_state_funcs drm_dp_mst_topology_state_funcs; /** * __drm_dp_mst_state_iter_get - private atomic state iterator function for * macro-internal use - * @state: &struct drm_atomic_state pointer + * @state: &struct drm_atomic_commit pointer * @mgr: pointer to the &struct drm_dp_mst_topology_mgr iteration cursor * @old_state: optional pointer to the old &struct drm_dp_mst_topology_state * iteration cursor @@ -999,7 +999,7 @@ extern const struct drm_private_state_funcs drm_dp_mst_topology_state_funcs; * drm_dp_mst_topology_mgr, false otherwise. */ static inline bool -__drm_dp_mst_state_iter_get(struct drm_atomic_state *state, +__drm_dp_mst_state_iter_get(struct drm_atomic_commit *state, struct drm_dp_mst_topology_mgr **mgr, struct drm_dp_mst_topology_state **old_state, struct drm_dp_mst_topology_state **new_state, @@ -1022,7 +1022,7 @@ __drm_dp_mst_state_iter_get(struct drm_atomic_state *state, /** * for_each_oldnew_mst_mgr_in_state - iterate over all DP MST topology * managers in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @mgr: &struct drm_dp_mst_topology_mgr iteration cursor * @old_state: &struct drm_dp_mst_topology_state iteration cursor for the old * state @@ -1041,7 +1041,7 @@ __drm_dp_mst_state_iter_get(struct drm_atomic_state *state, /** * for_each_old_mst_mgr_in_state - iterate over all DP MST topology managers * in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @mgr: &struct drm_dp_mst_topology_mgr iteration cursor * @old_state: &struct drm_dp_mst_topology_state iteration cursor for the old * state @@ -1058,7 +1058,7 @@ __drm_dp_mst_state_iter_get(struct drm_atomic_state *state, /** * for_each_new_mst_mgr_in_state - iterate over all DP MST topology managers * in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @mgr: &struct drm_dp_mst_topology_mgr iteration cursor * @new_state: &struct drm_dp_mst_topology_state iteration cursor for the new * state diff --git a/include/drm/display/drm_dp_tunnel.h b/include/drm/display/drm_dp_tunnel.h index 87212c847915..57f5e90ba8fd 100644 --- a/include/drm/display/drm_dp_tunnel.h +++ b/include/drm/display/drm_dp_tunnel.h @@ -14,7 +14,7 @@ struct drm_dp_aux; struct drm_device; -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_dp_tunnel_mgr; struct drm_dp_tunnel_state; @@ -53,6 +53,7 @@ int drm_dp_tunnel_destroy(struct drm_dp_tunnel *tunnel); int drm_dp_tunnel_enable_bw_alloc(struct drm_dp_tunnel *tunnel); int drm_dp_tunnel_disable_bw_alloc(struct drm_dp_tunnel *tunnel); bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel); +bool drm_dp_tunnel_pr_optimization_supported(const struct drm_dp_tunnel *tunnel); int drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw); int drm_dp_tunnel_get_allocated_bw(struct drm_dp_tunnel *tunnel); int drm_dp_tunnel_update_state(struct drm_dp_tunnel *tunnel); @@ -69,25 +70,25 @@ int drm_dp_tunnel_available_bw(const struct drm_dp_tunnel *tunnel); const char *drm_dp_tunnel_name(const struct drm_dp_tunnel *tunnel); struct drm_dp_tunnel_state * -drm_dp_tunnel_atomic_get_state(struct drm_atomic_state *state, +drm_dp_tunnel_atomic_get_state(struct drm_atomic_commit *state, struct drm_dp_tunnel *tunnel); struct drm_dp_tunnel_state * -drm_dp_tunnel_atomic_get_old_state(struct drm_atomic_state *state, +drm_dp_tunnel_atomic_get_old_state(struct drm_atomic_commit *state, const struct drm_dp_tunnel *tunnel); struct drm_dp_tunnel_state * -drm_dp_tunnel_atomic_get_new_state(struct drm_atomic_state *state, +drm_dp_tunnel_atomic_get_new_state(struct drm_atomic_commit *state, const struct drm_dp_tunnel *tunnel); -int drm_dp_tunnel_atomic_set_stream_bw(struct drm_atomic_state *state, +int drm_dp_tunnel_atomic_set_stream_bw(struct drm_atomic_commit *state, struct drm_dp_tunnel *tunnel, u8 stream_id, int bw); -int drm_dp_tunnel_atomic_get_group_streams_in_state(struct drm_atomic_state *state, +int drm_dp_tunnel_atomic_get_group_streams_in_state(struct drm_atomic_commit *state, const struct drm_dp_tunnel *tunnel, u32 *stream_mask); -int drm_dp_tunnel_atomic_check_stream_bws(struct drm_atomic_state *state, +int drm_dp_tunnel_atomic_check_stream_bws(struct drm_atomic_commit *state, u32 *failed_stream_mask); int drm_dp_tunnel_atomic_get_required_bw(const struct drm_dp_tunnel_state *tunnel_state); @@ -140,6 +141,11 @@ static inline bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel return false; } +static inline bool drm_dp_tunnel_pr_optimization_supported(const struct drm_dp_tunnel *tunnel) +{ + return false; +} + static inline int drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw) { @@ -192,21 +198,21 @@ drm_dp_tunnel_name(const struct drm_dp_tunnel *tunnel) } static inline struct drm_dp_tunnel_state * -drm_dp_tunnel_atomic_get_state(struct drm_atomic_state *state, +drm_dp_tunnel_atomic_get_state(struct drm_atomic_commit *state, struct drm_dp_tunnel *tunnel) { return ERR_PTR(-EOPNOTSUPP); } static inline struct drm_dp_tunnel_state * -drm_dp_tunnel_atomic_get_new_state(struct drm_atomic_state *state, +drm_dp_tunnel_atomic_get_new_state(struct drm_atomic_commit *state, const struct drm_dp_tunnel *tunnel) { return ERR_PTR(-EOPNOTSUPP); } static inline int -drm_dp_tunnel_atomic_set_stream_bw(struct drm_atomic_state *state, +drm_dp_tunnel_atomic_set_stream_bw(struct drm_atomic_commit *state, struct drm_dp_tunnel *tunnel, u8 stream_id, int bw) { @@ -214,7 +220,7 @@ drm_dp_tunnel_atomic_set_stream_bw(struct drm_atomic_state *state, } static inline int -drm_dp_tunnel_atomic_get_group_streams_in_state(struct drm_atomic_state *state, +drm_dp_tunnel_atomic_get_group_streams_in_state(struct drm_atomic_commit *state, const struct drm_dp_tunnel *tunnel, u32 *stream_mask) { @@ -222,7 +228,7 @@ drm_dp_tunnel_atomic_get_group_streams_in_state(struct drm_atomic_state *state, } static inline int -drm_dp_tunnel_atomic_check_stream_bws(struct drm_atomic_state *state, +drm_dp_tunnel_atomic_check_stream_bws(struct drm_atomic_commit *state, u32 *failed_stream_mask) { return -EOPNOTSUPP; diff --git a/include/drm/display/drm_hdmi_state_helper.h b/include/drm/display/drm_hdmi_state_helper.h index 2349c0d0f00f..0adc30c55ec9 100644 --- a/include/drm/display/drm_hdmi_state_helper.h +++ b/include/drm/display/drm_hdmi_state_helper.h @@ -3,7 +3,7 @@ #ifndef DRM_HDMI_STATE_HELPER_H_ #define DRM_HDMI_STATE_HELPER_H_ -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_connector; struct drm_connector_state; struct drm_display_mode; @@ -15,13 +15,13 @@ void __drm_atomic_helper_connector_hdmi_reset(struct drm_connector *connector, struct drm_connector_state *new_conn_state); int drm_atomic_helper_connector_hdmi_check(struct drm_connector *connector, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); int drm_atomic_helper_connector_hdmi_update_audio_infoframe(struct drm_connector *connector, struct hdmi_audio_infoframe *frame); int drm_atomic_helper_connector_hdmi_clear_audio_infoframe(struct drm_connector *connector); int drm_atomic_helper_connector_hdmi_update_infoframes(struct drm_connector *connector, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_atomic_helper_connector_hdmi_hotplug(struct drm_connector *connector, enum drm_connector_status status); void drm_atomic_helper_connector_hdmi_force(struct drm_connector *connector); diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index 8883290cd014..1a80a8cdf269 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -169,9 +169,9 @@ struct __drm_planes_state { * @state_to_destroy: * * Used to track the @drm_plane_state we will need to free when - * tearing down the associated &drm_atomic_state in + * tearing down the associated &drm_atomic_commit in * $drm_mode_config_funcs.atomic_state_clear or - * drm_atomic_state_default_clear(). + * drm_atomic_commit_default_clear(). * * Before a commit, and the call to * drm_atomic_helper_swap_state() in particular, it points to @@ -190,9 +190,9 @@ struct __drm_crtcs_state { * @state_to_destroy: * * Used to track the @drm_crtc_state we will need to free when - * tearing down the associated &drm_atomic_state in + * tearing down the associated &drm_atomic_commit in * $drm_mode_config_funcs.atomic_state_clear or - * drm_atomic_state_default_clear(). + * drm_atomic_commit_default_clear(). * * Before a commit, and the call to * drm_atomic_helper_swap_state() in particular, it points to @@ -224,9 +224,9 @@ struct __drm_connnectors_state { * @state_to_destroy: * * Used to track the @drm_connector_state we will need to free - * when tearing down the associated &drm_atomic_state in + * when tearing down the associated &drm_atomic_commit in * $drm_mode_config_funcs.atomic_state_clear or - * drm_atomic_state_default_clear(). + * drm_atomic_commit_default_clear(). * * Before a commit, and the call to * drm_atomic_helper_swap_state() in particular, it points to @@ -402,9 +402,9 @@ struct drm_private_obj { */ struct drm_private_state { /** - * @state: backpointer to global drm_atomic_state + * @state: backpointer to global drm_atomic_commit */ - struct drm_atomic_state *state; + struct drm_atomic_commit *state; /** * @obj: backpointer to the private object @@ -419,9 +419,9 @@ struct __drm_private_objs_state { * @state_to_destroy: * * Used to track the @drm_private_state we will need to free - * when tearing down the associated &drm_atomic_state in + * when tearing down the associated &drm_atomic_commit in * $drm_mode_config_funcs.atomic_state_clear or - * drm_atomic_state_default_clear(). + * drm_atomic_commit_default_clear(). * * Before a commit, and the call to * drm_atomic_helper_swap_state() in particular, it points to @@ -434,7 +434,7 @@ struct __drm_private_objs_state { }; /** - * struct drm_atomic_state - Atomic commit structure + * struct drm_atomic_commit - Atomic commit structure * * This structure is the kernel counterpart of @drm_mode_atomic and represents * an atomic commit that transitions from an old to a new display state. It @@ -446,25 +446,25 @@ struct __drm_private_objs_state { * drm_atomic_get_plane_state(), drm_atomic_get_connector_state(), or for * private state structures, drm_atomic_get_private_obj_state(). * - * NOTE: struct drm_atomic_state first started as a single collection of + * NOTE: struct drm_atomic_commit first started as a single collection of * entities state pointers (drm_plane_state, drm_crtc_state, etc.). * * At atomic_check time, you could get the state about to be committed - * from drm_atomic_state, and the one currently running from the + * from drm_atomic_commit, and the one currently running from the * entities state pointer (drm_crtc.state, for example). After the call * to drm_atomic_helper_swap_state(), the entities state pointer would - * contain the state previously checked, and the drm_atomic_state + * contain the state previously checked, and the drm_atomic_commit * structure the old state. * - * Over time, and in order to avoid confusion, drm_atomic_state has + * Over time, and in order to avoid confusion, drm_atomic_commit has * grown to have both the old state (ie, the state we replace) and the * new state (ie, the state we want to apply). Those names are stable * during the commit process, which makes it easier to reason about. * * You can still find some traces of that evolution through some hooks - * or callbacks taking a drm_atomic_state parameter called names like + * or callbacks taking a drm_atomic_commit parameter called names like * "old_state". This doesn't necessarily mean that the previous - * drm_atomic_state is passed, but rather that this used to be the state + * drm_atomic_commit is passed, but rather that this used to be the state * collection we were replacing after drm_atomic_helper_swap_state(), * but the variable name was never updated. * @@ -472,12 +472,12 @@ struct __drm_private_objs_state { * first started to pass the entity state only. However, it was pretty * cumbersome for drivers, and especially CRTCs, to retrieve the states * of other components. Thus, we switched to passing the whole - * drm_atomic_state as a parameter to those operations. Similarly, the + * drm_atomic_commit as a parameter to those operations. Similarly, the * transition isn't complete yet, and one might still find atomic - * operations taking a drm_atomic_state pointer, or a component state + * operations taking a drm_atomic_commit pointer, or a component state * pointer. The former is the preferred form. */ -struct drm_atomic_state { +struct drm_atomic_commit { /** * @ref: * @@ -679,61 +679,61 @@ static inline void drm_crtc_commit_put(struct drm_crtc_commit *commit) int drm_crtc_commit_wait(struct drm_crtc_commit *commit); -struct drm_atomic_state * __must_check -drm_atomic_state_alloc(struct drm_device *dev); -void drm_atomic_state_clear(struct drm_atomic_state *state); +struct drm_atomic_commit * __must_check +drm_atomic_commit_alloc(struct drm_device *dev); +void drm_atomic_commit_clear(struct drm_atomic_commit *state); /** - * drm_atomic_state_get - acquire a reference to the atomic state + * drm_atomic_commit_get - acquire a reference to the atomic state * @state: The atomic state * * Returns a new reference to the @state */ -static inline struct drm_atomic_state * -drm_atomic_state_get(struct drm_atomic_state *state) +static inline struct drm_atomic_commit * +drm_atomic_commit_get(struct drm_atomic_commit *state) { kref_get(&state->ref); return state; } -void __drm_atomic_state_free(struct kref *ref); +void __drm_atomic_commit_free(struct kref *ref); /** - * drm_atomic_state_put - release a reference to the atomic state + * drm_atomic_commit_put - release a reference to the atomic state * @state: The atomic state * * This releases a reference to @state which is freed after removing the * final reference. No locking required and callable from any context. */ -static inline void drm_atomic_state_put(struct drm_atomic_state *state) +static inline void drm_atomic_commit_put(struct drm_atomic_commit *state) { - kref_put(&state->ref, __drm_atomic_state_free); + kref_put(&state->ref, __drm_atomic_commit_free); } int __must_check -drm_atomic_state_init(struct drm_device *dev, struct drm_atomic_state *state); -void drm_atomic_state_default_clear(struct drm_atomic_state *state); -void drm_atomic_state_default_release(struct drm_atomic_state *state); +drm_atomic_commit_init(struct drm_device *dev, struct drm_atomic_commit *state); +void drm_atomic_commit_default_clear(struct drm_atomic_commit *state); +void drm_atomic_commit_default_release(struct drm_atomic_commit *state); struct drm_crtc_state * __must_check -drm_atomic_get_crtc_state(struct drm_atomic_state *state, +drm_atomic_get_crtc_state(struct drm_atomic_commit *state, struct drm_crtc *crtc); struct drm_plane_state * __must_check -drm_atomic_get_plane_state(struct drm_atomic_state *state, +drm_atomic_get_plane_state(struct drm_atomic_commit *state, struct drm_plane *plane); struct drm_colorop_state * -drm_atomic_get_colorop_state(struct drm_atomic_state *state, +drm_atomic_get_colorop_state(struct drm_atomic_commit *state, struct drm_colorop *colorop); struct drm_colorop_state * -drm_atomic_get_old_colorop_state(struct drm_atomic_state *state, +drm_atomic_get_old_colorop_state(struct drm_atomic_commit *state, struct drm_colorop *colorop); struct drm_colorop_state * -drm_atomic_get_new_colorop_state(struct drm_atomic_state *state, +drm_atomic_get_new_colorop_state(struct drm_atomic_commit *state, struct drm_colorop *colorop); struct drm_connector_state * __must_check -drm_atomic_get_connector_state(struct drm_atomic_state *state, +drm_atomic_get_connector_state(struct drm_atomic_commit *state, struct drm_connector *connector); int drm_atomic_private_obj_init(struct drm_device *dev, @@ -742,30 +742,30 @@ int drm_atomic_private_obj_init(struct drm_device *dev, void drm_atomic_private_obj_fini(struct drm_private_obj *obj); struct drm_private_state * __must_check -drm_atomic_get_private_obj_state(struct drm_atomic_state *state, +drm_atomic_get_private_obj_state(struct drm_atomic_commit *state, struct drm_private_obj *obj); struct drm_private_state * -drm_atomic_get_old_private_obj_state(const struct drm_atomic_state *state, +drm_atomic_get_old_private_obj_state(const struct drm_atomic_commit *state, struct drm_private_obj *obj); struct drm_private_state * -drm_atomic_get_new_private_obj_state(const struct drm_atomic_state *state, +drm_atomic_get_new_private_obj_state(const struct drm_atomic_commit *state, struct drm_private_obj *obj); struct drm_connector * -drm_atomic_get_old_connector_for_encoder(const struct drm_atomic_state *state, +drm_atomic_get_old_connector_for_encoder(const struct drm_atomic_commit *state, struct drm_encoder *encoder); struct drm_connector * -drm_atomic_get_new_connector_for_encoder(const struct drm_atomic_state *state, +drm_atomic_get_new_connector_for_encoder(const struct drm_atomic_commit *state, struct drm_encoder *encoder); struct drm_connector * drm_atomic_get_connector_for_encoder(const struct drm_encoder *encoder, struct drm_modeset_acquire_ctx *ctx); struct drm_crtc * -drm_atomic_get_old_crtc_for_encoder(struct drm_atomic_state *state, +drm_atomic_get_old_crtc_for_encoder(struct drm_atomic_commit *state, struct drm_encoder *encoder); struct drm_crtc * -drm_atomic_get_new_crtc_for_encoder(struct drm_atomic_state *state, +drm_atomic_get_new_crtc_for_encoder(struct drm_atomic_commit *state, struct drm_encoder *encoder); /** @@ -777,7 +777,7 @@ drm_atomic_get_new_crtc_for_encoder(struct drm_atomic_state *state, * NULL if the CRTC is not part of the global atomic state. */ static inline struct drm_crtc_state * -drm_atomic_get_old_crtc_state(const struct drm_atomic_state *state, +drm_atomic_get_old_crtc_state(const struct drm_atomic_commit *state, struct drm_crtc *crtc) { return state->crtcs[drm_crtc_index(crtc)].old_state; @@ -791,7 +791,7 @@ drm_atomic_get_old_crtc_state(const struct drm_atomic_state *state, * NULL if the CRTC is not part of the global atomic state. */ static inline struct drm_crtc_state * -drm_atomic_get_new_crtc_state(const struct drm_atomic_state *state, +drm_atomic_get_new_crtc_state(const struct drm_atomic_commit *state, struct drm_crtc *crtc) { return state->crtcs[drm_crtc_index(crtc)].new_state; @@ -806,7 +806,7 @@ drm_atomic_get_new_crtc_state(const struct drm_atomic_state *state, * NULL if the plane is not part of the global atomic state. */ static inline struct drm_plane_state * -drm_atomic_get_old_plane_state(const struct drm_atomic_state *state, +drm_atomic_get_old_plane_state(const struct drm_atomic_commit *state, struct drm_plane *plane) { return state->planes[drm_plane_index(plane)].old_state; @@ -821,7 +821,7 @@ drm_atomic_get_old_plane_state(const struct drm_atomic_state *state, * NULL if the plane is not part of the global atomic state. */ static inline struct drm_plane_state * -drm_atomic_get_new_plane_state(const struct drm_atomic_state *state, +drm_atomic_get_new_plane_state(const struct drm_atomic_commit *state, struct drm_plane *plane) { return state->planes[drm_plane_index(plane)].new_state; @@ -836,7 +836,7 @@ drm_atomic_get_new_plane_state(const struct drm_atomic_state *state, * or NULL if the connector is not part of the global atomic state. */ static inline struct drm_connector_state * -drm_atomic_get_old_connector_state(const struct drm_atomic_state *state, +drm_atomic_get_old_connector_state(const struct drm_atomic_commit *state, struct drm_connector *connector) { int index = drm_connector_index(connector); @@ -856,7 +856,7 @@ drm_atomic_get_old_connector_state(const struct drm_atomic_state *state, * or NULL if the connector is not part of the global atomic state. */ static inline struct drm_connector_state * -drm_atomic_get_new_connector_state(const struct drm_atomic_state *state, +drm_atomic_get_new_connector_state(const struct drm_atomic_commit *state, struct drm_connector *connector) { int index = drm_connector_index(connector); @@ -894,7 +894,7 @@ drm_atomic_get_new_connector_state(const struct drm_atomic_state *state, * Read-only pointer to the current plane state. */ static inline const struct drm_plane_state * -__drm_atomic_get_current_plane_state(const struct drm_atomic_state *state, +__drm_atomic_get_current_plane_state(const struct drm_atomic_commit *state, struct drm_plane *plane) { struct drm_plane_state *plane_state; @@ -910,27 +910,27 @@ __drm_atomic_get_current_plane_state(const struct drm_atomic_state *state, } int __must_check -drm_atomic_add_encoder_bridges(struct drm_atomic_state *state, +drm_atomic_add_encoder_bridges(struct drm_atomic_commit *state, struct drm_encoder *encoder); int __must_check -drm_atomic_add_affected_connectors(struct drm_atomic_state *state, +drm_atomic_add_affected_connectors(struct drm_atomic_commit *state, struct drm_crtc *crtc); int __must_check -drm_atomic_add_affected_planes(struct drm_atomic_state *state, +drm_atomic_add_affected_planes(struct drm_atomic_commit *state, struct drm_crtc *crtc); int __must_check -drm_atomic_add_affected_colorops(struct drm_atomic_state *state, +drm_atomic_add_affected_colorops(struct drm_atomic_commit *state, struct drm_plane *plane); -int __must_check drm_atomic_check_only(struct drm_atomic_state *state); -int __must_check drm_atomic_commit(struct drm_atomic_state *state); -int __must_check drm_atomic_nonblocking_commit(struct drm_atomic_state *state); +int __must_check drm_atomic_check_only(struct drm_atomic_commit *state); +int __must_check drm_atomic_commit(struct drm_atomic_commit *state); +int __must_check drm_atomic_nonblocking_commit(struct drm_atomic_commit *state); void drm_state_dump(struct drm_device *dev, struct drm_printer *p); /** * for_each_oldnew_connector_in_state - iterate over all connectors in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @connector: &struct drm_connector iteration cursor * @old_connector_state: &struct drm_connector_state iteration cursor for the * old state @@ -954,7 +954,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); /** * for_each_old_connector_in_state - iterate over all connectors in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @connector: &struct drm_connector iteration cursor * @old_connector_state: &struct drm_connector_state iteration cursor for the * old state @@ -975,7 +975,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); /** * for_each_new_connector_in_state - iterate over all connectors in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @connector: &struct drm_connector iteration cursor * @new_connector_state: &struct drm_connector_state iteration cursor for the * new state @@ -997,7 +997,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); /** * for_each_oldnew_crtc_in_state - iterate over all CRTCs in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @crtc: &struct drm_crtc iteration cursor * @old_crtc_state: &struct drm_crtc_state iteration cursor for the old state * @new_crtc_state: &struct drm_crtc_state iteration cursor for the new state @@ -1021,7 +1021,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); /** * for_each_old_crtc_in_state - iterate over all CRTCs in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @crtc: &struct drm_crtc iteration cursor * @old_crtc_state: &struct drm_crtc_state iteration cursor for the old state * @__i: int iteration cursor, for macro-internal use @@ -1041,7 +1041,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); /** * for_each_new_crtc_in_state - iterate over all CRTCs in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @crtc: &struct drm_crtc iteration cursor * @new_crtc_state: &struct drm_crtc_state iteration cursor for the new state * @__i: int iteration cursor, for macro-internal use @@ -1062,7 +1062,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); /** * for_each_oldnew_colorop_in_state - iterate over all colorops in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @colorop: &struct drm_colorop iteration cursor * @old_colorop_state: &struct drm_colorop_state iteration cursor for the old state * @new_colorop_state: &struct drm_colorop_state iteration cursor for the new state @@ -1085,7 +1085,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); /** * for_each_new_colorop_in_state - iterate over all colorops in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @colorop: &struct drm_colorop iteration cursor * @new_colorop_state: &struct drm_colorop_state iteration cursor for the new state * @__i: int iteration cursor, for macro-internal use @@ -1106,7 +1106,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); /** * for_each_oldnew_plane_in_state - iterate over all planes in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @plane: &struct drm_plane iteration cursor * @old_plane_state: &struct drm_plane_state iteration cursor for the old state * @new_plane_state: &struct drm_plane_state iteration cursor for the new state @@ -1129,7 +1129,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); /** * for_each_oldnew_plane_in_state_reverse - iterate over all planes in an atomic * update in reverse order - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @plane: &struct drm_plane iteration cursor * @old_plane_state: &struct drm_plane_state iteration cursor for the old state * @new_plane_state: &struct drm_plane_state iteration cursor for the new state @@ -1151,7 +1151,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); /** * for_each_new_plane_in_state_reverse - other than only tracking new state, * it's the same as for_each_oldnew_plane_in_state_reverse - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @plane: &struct drm_plane iteration cursor * @new_plane_state: &struct drm_plane_state iteration cursor for the new state * @__i: int iteration cursor, for macro-internal use @@ -1166,7 +1166,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); /** * for_each_old_plane_in_state - iterate over all planes in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @plane: &struct drm_plane iteration cursor * @old_plane_state: &struct drm_plane_state iteration cursor for the old state * @__i: int iteration cursor, for macro-internal use @@ -1184,7 +1184,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); (old_plane_state) = (__state)->planes[__i].old_state, 1)) /** * for_each_new_plane_in_state - iterate over all planes in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @plane: &struct drm_plane iteration cursor * @new_plane_state: &struct drm_plane_state iteration cursor for the new state * @__i: int iteration cursor, for macro-internal use @@ -1205,7 +1205,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); /** * for_each_oldnew_private_obj_in_state - iterate over all private objects in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @obj: &struct drm_private_obj iteration cursor * @old_obj_state: &struct drm_private_state iteration cursor for the old state * @new_obj_state: &struct drm_private_state iteration cursor for the new state @@ -1225,7 +1225,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); /** * for_each_old_private_obj_in_state - iterate over all private objects in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @obj: &struct drm_private_obj iteration cursor * @old_obj_state: &struct drm_private_state iteration cursor for the old state * @__i: int iteration cursor, for macro-internal use @@ -1243,7 +1243,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); /** * for_each_new_private_obj_in_state - iterate over all private objects in an atomic update - * @__state: &struct drm_atomic_state pointer + * @__state: &struct drm_atomic_commit pointer * @obj: &struct drm_private_obj iteration cursor * @new_obj_state: &struct drm_private_state iteration cursor for the new state * @__i: int iteration cursor, for macro-internal use @@ -1365,13 +1365,13 @@ drm_priv_to_bridge_state(struct drm_private_state *priv) } struct drm_bridge_state * -drm_atomic_get_bridge_state(struct drm_atomic_state *state, +drm_atomic_get_bridge_state(struct drm_atomic_commit *state, struct drm_bridge *bridge); struct drm_bridge_state * -drm_atomic_get_old_bridge_state(const struct drm_atomic_state *state, +drm_atomic_get_old_bridge_state(const struct drm_atomic_commit *state, struct drm_bridge *bridge); struct drm_bridge_state * -drm_atomic_get_new_bridge_state(const struct drm_atomic_state *state, +drm_atomic_get_new_bridge_state(const struct drm_atomic_commit *state, struct drm_bridge *bridge); #endif /* DRM_ATOMIC_H_ */ diff --git a/include/drm/drm_atomic_helper.h b/include/drm/drm_atomic_helper.h index e154ee4f0696..b84152810abb 100644 --- a/include/drm/drm_atomic_helper.h +++ b/include/drm/drm_atomic_helper.h @@ -43,14 +43,14 @@ */ #define DRM_PLANE_NO_SCALING (1<<16) -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_private_obj; struct drm_private_state; int drm_atomic_helper_check_modeset(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); int drm_atomic_helper_check_wb_connector_state(struct drm_connector *connector, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); int drm_atomic_helper_check_plane_state(struct drm_plane_state *plane_state, const struct drm_crtc_state *crtc_state, int min_scale, @@ -58,92 +58,92 @@ int drm_atomic_helper_check_plane_state(struct drm_plane_state *plane_state, bool can_position, bool can_update_disabled); int drm_atomic_helper_check_planes(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); int drm_atomic_helper_check_crtc_primary_plane(struct drm_crtc_state *crtc_state); void drm_atomic_helper_commit_encoder_bridge_disable(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_atomic_helper_commit_crtc_disable(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_atomic_helper_commit_encoder_bridge_post_disable(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); int drm_atomic_helper_check(struct drm_device *dev, - struct drm_atomic_state *state); -void drm_atomic_helper_commit_tail(struct drm_atomic_state *state); -void drm_atomic_helper_commit_tail_rpm(struct drm_atomic_state *state); + struct drm_atomic_commit *state); +void drm_atomic_helper_commit_tail(struct drm_atomic_commit *state); +void drm_atomic_helper_commit_tail_rpm(struct drm_atomic_commit *state); int drm_atomic_helper_commit(struct drm_device *dev, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, bool nonblock); int drm_atomic_helper_async_check(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_atomic_helper_async_commit(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); int drm_atomic_helper_wait_for_fences(struct drm_device *dev, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, bool pre_swap); void drm_atomic_helper_wait_for_vblanks(struct drm_device *dev, - struct drm_atomic_state *old_state); + struct drm_atomic_commit *old_state); void drm_atomic_helper_wait_for_flip_done(struct drm_device *dev, - struct drm_atomic_state *old_state); + struct drm_atomic_commit *old_state); void drm_atomic_helper_update_legacy_modeset_state(struct drm_device *dev, - struct drm_atomic_state *old_state); + struct drm_atomic_commit *old_state); void -drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_state *state); +drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_commit *state); void drm_atomic_helper_commit_crtc_set_mode(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_atomic_helper_commit_modeset_disables(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_atomic_helper_commit_writebacks(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_atomic_helper_commit_encoder_bridge_pre_enable(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_atomic_helper_commit_crtc_enable(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_atomic_helper_commit_encoder_bridge_enable(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_atomic_helper_commit_modeset_enables(struct drm_device *dev, - struct drm_atomic_state *old_state); + struct drm_atomic_commit *old_state); int drm_atomic_helper_prepare_planes(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_atomic_helper_unprepare_planes(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); #define DRM_PLANE_COMMIT_ACTIVE_ONLY BIT(0) #define DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET BIT(1) void drm_atomic_helper_commit_planes(struct drm_device *dev, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, uint32_t flags); void drm_atomic_helper_cleanup_planes(struct drm_device *dev, - struct drm_atomic_state *old_state); + struct drm_atomic_commit *old_state); void drm_atomic_helper_commit_planes_on_crtc(struct drm_crtc_state *old_crtc_state); void drm_atomic_helper_disable_planes_on_crtc(struct drm_crtc_state *old_crtc_state, bool atomic); -int __must_check drm_atomic_helper_swap_state(struct drm_atomic_state *state, +int __must_check drm_atomic_helper_swap_state(struct drm_atomic_commit *state, bool stall); /* nonblocking commit helpers */ -int drm_atomic_helper_setup_commit(struct drm_atomic_state *state, +int drm_atomic_helper_setup_commit(struct drm_atomic_commit *state, bool nonblock); -void drm_atomic_helper_wait_for_dependencies(struct drm_atomic_state *state); -void drm_atomic_helper_fake_vblank(struct drm_atomic_state *state); -void drm_atomic_helper_commit_hw_done(struct drm_atomic_state *state); -void drm_atomic_helper_commit_cleanup_done(struct drm_atomic_state *state); +void drm_atomic_helper_wait_for_dependencies(struct drm_atomic_commit *state); +void drm_atomic_helper_fake_vblank(struct drm_atomic_commit *state); +void drm_atomic_helper_commit_hw_done(struct drm_atomic_commit *state); +void drm_atomic_helper_commit_cleanup_done(struct drm_atomic_commit *state); /* implementations for legacy interfaces */ int drm_atomic_helper_update_plane(struct drm_plane *plane, @@ -164,14 +164,14 @@ int drm_atomic_helper_disable_all(struct drm_device *dev, int drm_atomic_helper_reset_crtc(struct drm_crtc *crtc, struct drm_modeset_acquire_ctx *ctx); void drm_atomic_helper_shutdown(struct drm_device *dev); -struct drm_atomic_state * +struct drm_atomic_commit * drm_atomic_helper_duplicate_state(struct drm_device *dev, struct drm_modeset_acquire_ctx *ctx); -struct drm_atomic_state *drm_atomic_helper_suspend(struct drm_device *dev); -int drm_atomic_helper_commit_duplicated_state(struct drm_atomic_state *state, +struct drm_atomic_commit *drm_atomic_helper_suspend(struct drm_device *dev); +int drm_atomic_helper_commit_duplicated_state(struct drm_atomic_commit *state, struct drm_modeset_acquire_ctx *ctx); int drm_atomic_helper_resume(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); int drm_atomic_helper_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, diff --git a/include/drm/drm_atomic_state_helper.h b/include/drm/drm_atomic_state_helper.h index 900672c6ea90..61a3b38ad49f 100644 --- a/include/drm/drm_atomic_state_helper.h +++ b/include/drm/drm_atomic_state_helper.h @@ -26,7 +26,7 @@ #include -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_bridge; struct drm_bridge_state; struct drm_crtc; @@ -73,7 +73,7 @@ void __drm_atomic_helper_connector_reset(struct drm_connector *connector, void drm_atomic_helper_connector_reset(struct drm_connector *connector); void drm_atomic_helper_connector_tv_reset(struct drm_connector *connector); int drm_atomic_helper_connector_tv_check(struct drm_connector *connector, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_atomic_helper_connector_tv_margins_reset(struct drm_connector *connector); void __drm_atomic_helper_connector_duplicate_state(struct drm_connector *connector, diff --git a/include/drm/drm_blend.h b/include/drm/drm_blend.h index c7e888767c81..bebbb77a8f21 100644 --- a/include/drm/drm_blend.h +++ b/include/drm/drm_blend.h @@ -31,7 +31,7 @@ #define DRM_MODE_BLEND_COVERAGE 1 #define DRM_MODE_BLEND_PIXEL_NONE 2 -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_crtc; struct drm_device; struct drm_plane; @@ -56,7 +56,7 @@ int drm_plane_create_zpos_property(struct drm_plane *plane, int drm_plane_create_zpos_immutable_property(struct drm_plane *plane, unsigned int zpos); int drm_atomic_normalize_zpos(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); int drm_plane_create_blend_mode_property(struct drm_plane *plane, unsigned int supported_modes); void drm_crtc_attach_background_color_property(struct drm_crtc *crtc); diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h index d6cd0f5af045..fdac9a526f38 100644 --- a/include/drm/drm_bridge.h +++ b/include/drm/drm_bridge.h @@ -317,7 +317,7 @@ struct drm_bridge_funcs { * The @atomic_pre_enable callback is optional. */ void (*atomic_pre_enable)(struct drm_bridge *bridge, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_enable: @@ -337,7 +337,7 @@ struct drm_bridge_funcs { * The @atomic_enable callback is optional. */ void (*atomic_enable)(struct drm_bridge *bridge, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_disable: * @@ -354,7 +354,7 @@ struct drm_bridge_funcs { * The @atomic_disable callback is optional. */ void (*atomic_disable)(struct drm_bridge *bridge, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_post_disable: @@ -373,7 +373,7 @@ struct drm_bridge_funcs { * The @atomic_post_disable callback is optional. */ void (*atomic_post_disable)(struct drm_bridge *bridge, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_duplicate_state: @@ -1547,13 +1547,13 @@ int drm_atomic_bridge_chain_check(struct drm_bridge *bridge, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state); void drm_atomic_bridge_chain_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_atomic_bridge_chain_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_atomic_bridge_chain_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_atomic_bridge_chain_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); u32 * drm_atomic_helper_bridge_propagate_bus_fmt(struct drm_bridge *bridge, diff --git a/include/drm/drm_colorop.h b/include/drm/drm_colorop.h index bd082854ca74..c873199c60da 100644 --- a/include/drm/drm_colorop.h +++ b/include/drm/drm_colorop.h @@ -183,8 +183,8 @@ struct drm_colorop_state { */ struct drm_property_blob *data; - /** @state: backpointer to global drm_atomic_state */ - struct drm_atomic_state *state; + /** @state: backpointer to global drm_atomic_commit */ + struct drm_atomic_commit *state; }; /** diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index 3e422a4f2e72..5ad62c207d00 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -1098,8 +1098,8 @@ struct drm_connector_state { */ enum drm_link_status link_status; - /** @state: backpointer to global drm_atomic_state */ - struct drm_atomic_state *state; + /** @state: backpointer to global drm_atomic_commit */ + struct drm_atomic_commit *state; /** * @commit: Tracks the pending commit to prevent use-after-free conditions. @@ -2344,7 +2344,7 @@ struct drm_connector { * * This is protected by &drm_mode_config.connection_mutex. Note that * nonblocking atomic commits access the current connector state without - * taking locks. Either by going through the &struct drm_atomic_state + * taking locks. Either by going through the &struct drm_atomic_commit * pointers, see for_each_oldnew_connector_in_state(), * for_each_old_connector_in_state() and * for_each_new_connector_in_state(). Or through careful ordering of diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 312fc1e745d2..c6dbe8b7db9e 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -58,7 +58,7 @@ struct drm_crtc; struct drm_pending_vblank_event; struct drm_plane; struct drm_bridge; -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_crtc_helper_funcs; struct drm_plane_helper_funcs; @@ -406,8 +406,8 @@ struct drm_crtc_state { */ struct drm_crtc_commit *commit; - /** @state: backpointer to global drm_atomic_state */ - struct drm_atomic_state *state; + /** @state: backpointer to global drm_atomic_commit */ + struct drm_atomic_commit *state; }; /** @@ -1124,7 +1124,7 @@ struct drm_crtc { * * This is protected by @mutex. Note that nonblocking atomic commits * access the current CRTC state without taking locks. Either by going - * through the &struct drm_atomic_state pointers, see + * through the &struct drm_atomic_commit pointers, see * for_each_oldnew_crtc_in_state(), for_each_old_crtc_in_state() and * for_each_new_crtc_in_state(). Or through careful ordering of atomic * commit operations as implemented in the atomic helpers, see @@ -1217,7 +1217,7 @@ struct drm_crtc { * @num_connectors: size of @connectors array * * This represents a modeset configuration for the legacy SETCRTC ioctl and is - * also used internally. Atomic drivers instead use &drm_atomic_state. + * also used internally. Atomic drivers instead use &drm_atomic_commit. */ struct drm_mode_set { struct drm_framebuffer *fb; diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h index 8c886fc46ef2..855da5733c47 100644 --- a/include/drm/drm_crtc_helper.h +++ b/include/drm/drm_crtc_helper.h @@ -35,7 +35,7 @@ #include -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_connector; struct drm_crtc; struct drm_device; @@ -53,7 +53,7 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb); int drm_crtc_helper_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); bool drm_helper_crtc_in_use(struct drm_crtc *crtc); bool drm_helper_encoder_in_use(struct drm_encoder *encoder); diff --git a/include/drm/drm_damage_helper.h b/include/drm/drm_damage_helper.h index a58cbcd11276..3661aeab2cd3 100644 --- a/include/drm/drm_damage_helper.h +++ b/include/drm/drm_damage_helper.h @@ -64,7 +64,7 @@ struct drm_atomic_helper_damage_iter { bool full_update; }; -void drm_atomic_helper_check_plane_damage(struct drm_atomic_state *state, +void drm_atomic_helper_check_plane_damage(struct drm_atomic_commit *state, struct drm_plane_state *plane_state); int drm_atomic_helper_dirtyfb(struct drm_framebuffer *fb, struct drm_file *file_priv, unsigned int flags, diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h index bf391903443d..0c5e5ed7b5e7 100644 --- a/include/drm/drm_fb_helper.h +++ b/include/drm/drm_fb_helper.h @@ -273,6 +273,12 @@ int drm_fb_helper_hotplug_event(struct drm_fb_helper *fb_helper); int drm_fb_helper_initial_config(struct drm_fb_helper *fb_helper); bool drm_fb_helper_gem_is_fb(const struct drm_fb_helper *fb_helper, const struct drm_gem_object *obj); +#else +static inline bool drm_fb_helper_gem_is_fb(const struct drm_fb_helper *fb_helper, + const struct drm_gem_object *obj) +{ + return false; +} #endif #endif diff --git a/include/drm/drm_kunit_helpers.h b/include/drm/drm_kunit_helpers.h index 4948379237e9..e653bc7b1e40 100644 --- a/include/drm/drm_kunit_helpers.h +++ b/include/drm/drm_kunit_helpers.h @@ -97,7 +97,7 @@ __drm_kunit_helper_alloc_drm_device(struct kunit *test, offsetof(_type, _member), \ _feat)) -struct drm_atomic_state * +struct drm_atomic_commit * drm_kunit_helper_atomic_state_alloc(struct kunit *test, struct drm_device *drm, struct drm_modeset_acquire_ctx *ctx); diff --git a/include/drm/drm_mipi_dbi.h b/include/drm/drm_mipi_dbi.h index 07374eb5d88e..78ab23d844ce 100644 --- a/include/drm/drm_mipi_dbi.h +++ b/include/drm/drm_mipi_dbi.h @@ -220,9 +220,9 @@ int mipi_dbi_buf_copy(void *dst, struct iosys_map *src, struct drm_framebuffer * .disable_plane = drm_atomic_helper_disable_plane int drm_mipi_dbi_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_mipi_dbi_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); #define DRM_MIPI_DBI_PLANE_HELPER_FUNCS \ DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, \ @@ -243,9 +243,9 @@ void drm_mipi_dbi_plane_helper_atomic_update(struct drm_plane *plane, enum drm_mode_status drm_mipi_dbi_crtc_helper_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode); int drm_mipi_dbi_crtc_helper_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_mipi_dbi_crtc_helper_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); #define DRM_MIPI_DBI_CRTC_HELPER_FUNCS \ .mode_valid = drm_mipi_dbi_crtc_helper_mode_valid, \ diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index 687c0ee163d2..e584652ddf67 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -33,7 +33,7 @@ struct drm_file; struct drm_device; -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_mode_fb_cmd2; struct drm_format_info; struct drm_display_mode; @@ -158,7 +158,7 @@ struct drm_mode_config_funcs { * error conditions which don't have to be checked at the in this * callback. * - * See the documentation for &struct drm_atomic_state for how exactly + * See the documentation for &struct drm_atomic_commit for how exactly * an atomic modeset update is described. * * Drivers using the atomic helpers can implement this hook using @@ -184,7 +184,7 @@ struct drm_mode_config_funcs { * treated equally. */ int (*atomic_check)(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_commit: @@ -194,7 +194,7 @@ struct drm_mode_config_funcs { * calling this function, and that nothing has been changed in the * interim. * - * See the documentation for &struct drm_atomic_state for how exactly + * See the documentation for &struct drm_atomic_commit for how exactly * an atomic modeset update is described. * * Drivers using the atomic helpers can implement this hook using @@ -266,31 +266,31 @@ struct drm_mode_config_funcs { * additional modeset locks). */ int (*atomic_commit)(struct drm_device *dev, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, bool nonblock); /** * @atomic_state_alloc: * * This optional hook can be used by drivers that want to subclass struct - * &drm_atomic_state to be able to track their own driver-private global + * &drm_atomic_commit to be able to track their own driver-private global * state easily. If this hook is implemented, drivers must also * implement @atomic_state_clear and @atomic_state_free. * - * Subclassing of &drm_atomic_state is deprecated in favour of using + * Subclassing of &drm_atomic_commit is deprecated in favour of using * &drm_private_state and &drm_private_obj. * * RETURNS: * - * A new &drm_atomic_state on success or NULL on failure. + * A new &drm_atomic_commit on success or NULL on failure. */ - struct drm_atomic_state *(*atomic_state_alloc)(struct drm_device *dev); + struct drm_atomic_commit *(*atomic_state_alloc)(struct drm_device *dev); /** * @atomic_state_clear: * * This hook must clear any driver private state duplicated into the - * passed-in &drm_atomic_state. This hook is called when the caller + * passed-in &drm_atomic_commit. This hook is called when the caller * encountered a &drm_modeset_lock deadlock and needs to drop all * already acquired locks as part of the deadlock avoidance dance * implemented in drm_modeset_backoff(). @@ -299,28 +299,28 @@ struct drm_mode_config_funcs { * update might change it, and the drm atomic interfaces always apply * updates as relative changes to the current state. * - * Drivers that implement this must call drm_atomic_state_default_clear() + * Drivers that implement this must call drm_atomic_commit_default_clear() * to clear common state. * - * Subclassing of &drm_atomic_state is deprecated in favour of using + * Subclassing of &drm_atomic_commit is deprecated in favour of using * &drm_private_state and &drm_private_obj. */ - void (*atomic_state_clear)(struct drm_atomic_state *state); + void (*atomic_state_clear)(struct drm_atomic_commit *state); /** * @atomic_state_free: * - * This hook needs driver private resources and the &drm_atomic_state - * itself. Note that the core first calls drm_atomic_state_clear() to + * This hook needs driver private resources and the &drm_atomic_commit + * itself. Note that the core first calls drm_atomic_commit_clear() to * avoid code duplicate between the clear and free hooks. * * Drivers that implement this must call - * drm_atomic_state_default_release() to release common resources. + * drm_atomic_commit_default_release() to release common resources. * - * Subclassing of &drm_atomic_state is deprecated in favour of using + * Subclassing of &drm_atomic_commit is deprecated in favour of using * &drm_private_state and &drm_private_obj. */ - void (*atomic_state_free)(struct drm_atomic_state *state); + void (*atomic_state_free)(struct drm_atomic_commit *state); }; /** @@ -985,7 +985,7 @@ struct drm_mode_config { * Set by drm_mode_config_helper_suspend() and cleared by * drm_mode_config_helper_resume(). */ - struct drm_atomic_state *suspend_state; + struct drm_atomic_commit *suspend_state; const struct drm_mode_config_helper_funcs *helper_private; }; diff --git a/include/drm/drm_modeset_helper_vtables.h b/include/drm/drm_modeset_helper_vtables.h index 3e68213958dd..ca6268945c28 100644 --- a/include/drm/drm_modeset_helper_vtables.h +++ b/include/drm/drm_modeset_helper_vtables.h @@ -332,7 +332,7 @@ struct drm_crtc_helper_funcs { * deadlock. */ int (*atomic_check)(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_begin: @@ -353,7 +353,7 @@ struct drm_crtc_helper_funcs { * optional. */ void (*atomic_begin)(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_flush: * @@ -377,7 +377,7 @@ struct drm_crtc_helper_funcs { * optional. */ void (*atomic_flush)(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_enable: @@ -399,7 +399,7 @@ struct drm_crtc_helper_funcs { * This function is optional. */ void (*atomic_enable)(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_disable: @@ -419,7 +419,7 @@ struct drm_crtc_helper_funcs { * This function is optional. */ void (*atomic_disable)(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @get_scanout_position: @@ -713,7 +713,7 @@ struct drm_encoder_helper_funcs { * @atomic_enable. */ void (*atomic_disable)(struct drm_encoder *encoder, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_enable: @@ -736,7 +736,7 @@ struct drm_encoder_helper_funcs { * @atomic_disable. */ void (*atomic_enable)(struct drm_encoder *encoder, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @disable: @@ -809,7 +809,7 @@ struct drm_encoder_helper_funcs { * * This function is called in the check phase of an atomic update. The * driver is not allowed to change anything outside of the free-standing - * state objects passed-in or assembled in the overall &drm_atomic_state + * state objects passed-in or assembled in the overall &drm_atomic_commit * update tracking structure. * * Also beware that userspace can request its own custom modes, neither @@ -1044,7 +1044,7 @@ struct drm_connector_helper_funcs { * * This function is called in the check phase of an atomic update. The * driver is not allowed to change anything outside of the - * &drm_atomic_state update tracking structure passed in. + * &drm_atomic_commit update tracking structure passed in. * * RETURNS: * @@ -1054,7 +1054,7 @@ struct drm_connector_helper_funcs { * for this. */ struct drm_encoder *(*atomic_best_encoder)(struct drm_connector *connector, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_check: @@ -1077,7 +1077,7 @@ struct drm_connector_helper_funcs { * * This function is called in the check phase of an atomic update. The * driver is not allowed to change anything outside of the free-standing - * state objects passed-in or assembled in the overall &drm_atomic_state + * state objects passed-in or assembled in the overall &drm_atomic_commit * update tracking structure. * * RETURNS: @@ -1088,7 +1088,7 @@ struct drm_connector_helper_funcs { * deadlock. */ int (*atomic_check)(struct drm_connector *connector, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_commit: @@ -1103,7 +1103,7 @@ struct drm_connector_helper_funcs { * This callback is used by the atomic modeset helpers. */ void (*atomic_commit)(struct drm_connector *connector, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @prepare_writeback_job: @@ -1299,7 +1299,7 @@ struct drm_plane_helper_funcs { * * This function is called in the check phase of an atomic update. The * driver is not allowed to change anything outside of the - * &drm_atomic_state update tracking structure. + * &drm_atomic_commit update tracking structure. * * RETURNS: * @@ -1309,7 +1309,7 @@ struct drm_plane_helper_funcs { * deadlock. */ int (*atomic_check)(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_update: @@ -1326,7 +1326,7 @@ struct drm_plane_helper_funcs { * This callback is used by the atomic modeset helpers, but it is optional. */ void (*atomic_update)(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_enable: @@ -1351,7 +1351,7 @@ struct drm_plane_helper_funcs { * implement the complete plane update in @atomic_update. */ void (*atomic_enable)(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_disable: @@ -1376,7 +1376,7 @@ struct drm_plane_helper_funcs { * optional. It's intended to reverse the effects of @atomic_enable. */ void (*atomic_disable)(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @atomic_async_check: @@ -1400,7 +1400,7 @@ struct drm_plane_helper_funcs { * can not be applied in asynchronous manner. */ int (*atomic_async_check)(struct drm_plane *plane, - struct drm_atomic_state *state, bool flip); + struct drm_atomic_commit *state, bool flip); /** * @atomic_async_update: @@ -1437,7 +1437,7 @@ struct drm_plane_helper_funcs { * for deferring if needed, until a common solution is created. */ void (*atomic_async_update)(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); /** * @get_scanout_buffer: @@ -1530,7 +1530,7 @@ struct drm_mode_config_helper_funcs { * This hook is optional, the default implementation is * drm_atomic_helper_commit_tail(). */ - void (*atomic_commit_tail)(struct drm_atomic_state *state); + void (*atomic_commit_tail)(struct drm_atomic_commit *state); /** * @atomic_commit_setup: @@ -1551,7 +1551,7 @@ struct drm_mode_config_helper_funcs { * * This hook is optional. */ - int (*atomic_commit_setup)(struct drm_atomic_state *state); + int (*atomic_commit_setup)(struct drm_atomic_commit *state); }; #endif diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 703ef4d1bbbc..419c88c873a6 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -259,8 +259,8 @@ struct drm_plane_state { */ struct drm_crtc_commit *commit; - /** @state: backpointer to global drm_atomic_state */ - struct drm_atomic_state *state; + /** @state: backpointer to global drm_atomic_commit */ + struct drm_atomic_commit *state; /** * @color_mgmt_changed: Color management properties have changed. Used @@ -739,7 +739,7 @@ struct drm_plane { * * This is protected by @mutex. Note that nonblocking atomic commits * access the current plane state without taking locks. Either by going - * through the &struct drm_atomic_state pointers, see + * through the &struct drm_atomic_commit pointers, see * for_each_oldnew_plane_in_state(), for_each_old_plane_in_state() and * for_each_new_plane_in_state(). Or through careful ordering of atomic * commit operations as implemented in the atomic helpers, see diff --git a/include/drm/drm_ras.h b/include/drm/drm_ras.h index 5d50209e51db..f2a787bc4f64 100644 --- a/include/drm/drm_ras.h +++ b/include/drm/drm_ras.h @@ -58,6 +58,17 @@ struct drm_ras_node { int (*query_error_counter)(struct drm_ras_node *node, u32 error_id, const char **name, u32 *val); + /** + * @clear_error_counter: + * + * This callback is used by drm_ras to clear a specific error counter. + * Driver should implement this callback to support clearing error counters + * of a node. + * + * Returns: 0 on success, negative error code on failure. + */ + int (*clear_error_counter)(struct drm_ras_node *node, u32 error_id); + /** @priv: Driver private data */ void *priv; }; diff --git a/include/drm/drm_self_refresh_helper.h b/include/drm/drm_self_refresh_helper.h index 520235c20708..95c190125b60 100644 --- a/include/drm/drm_self_refresh_helper.h +++ b/include/drm/drm_self_refresh_helper.h @@ -8,11 +8,11 @@ #ifndef DRM_SELF_REFRESH_HELPER_H_ #define DRM_SELF_REFRESH_HELPER_H_ -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_crtc; -void drm_self_refresh_helper_alter_state(struct drm_atomic_state *state); -void drm_self_refresh_helper_update_avg_times(struct drm_atomic_state *state, +void drm_self_refresh_helper_alter_state(struct drm_atomic_commit *state); +void drm_self_refresh_helper_update_avg_times(struct drm_atomic_commit *state, unsigned int commit_time_ms, unsigned int new_self_refresh_mask); diff --git a/include/drm/drm_vblank_helper.h b/include/drm/drm_vblank_helper.h index fcd8a9b35846..28051f08d0f4 100644 --- a/include/drm/drm_vblank_helper.h +++ b/include/drm/drm_vblank_helper.h @@ -6,7 +6,7 @@ #include #include -struct drm_atomic_state; +struct drm_atomic_commit; struct drm_crtc; /* @@ -14,11 +14,11 @@ struct drm_crtc; */ void drm_crtc_vblank_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_crtc_vblank_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void drm_crtc_vblank_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *crtc_state); + struct drm_atomic_commit *crtc_state); /** * DRM_CRTC_HELPER_VBLANK_FUNCS - Default implementation for VBLANK helpers diff --git a/include/drm/intel/display_parent_interface.h b/include/drm/intel/display_parent_interface.h index 97ec94a2e749..270dc028bec2 100644 --- a/include/drm/intel/display_parent_interface.h +++ b/include/drm/intel/display_parent_interface.h @@ -6,8 +6,8 @@ #include +enum vlv_iosf_sb_unit; struct dma_fence; -struct drm_crtc; struct drm_device; struct drm_file; struct drm_framebuffer; @@ -15,6 +15,7 @@ struct drm_gem_object; struct drm_mode_fb_cmd2; struct drm_plane_state; struct drm_scanout_buffer; +struct fb_info; struct i915_vma; struct intel_dpt; struct intel_dsb_buffer; @@ -43,6 +44,12 @@ struct intel_display_bo_interface { struct drm_gem_object *(*framebuffer_lookup)(struct drm_device *drm, struct drm_file *filp, const struct drm_mode_fb_cmd2 *user_mode_cmd); +#if IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION) + struct drm_gem_object *(*fbdev_create)(struct drm_device *drm, int size); + void (*fbdev_destroy)(struct drm_gem_object *obj); + int (*fbdev_fill_info)(struct drm_gem_object *obj, struct fb_info *info, struct i915_vma *vma); + u32 (*fbdev_pitch_align)(u32 stride); +#endif }; struct intel_display_dpt_interface { @@ -79,11 +86,10 @@ struct intel_display_hdcp_interface { }; struct intel_display_initial_plane_interface { - void (*vblank_wait)(struct drm_crtc *crtc); struct drm_gem_object *(*alloc_obj)(struct drm_device *drm, struct intel_initial_plane_config *plane_config); int (*setup)(struct drm_plane_state *plane_state, struct intel_initial_plane_config *plane_config, struct drm_framebuffer *fb, struct i915_vma *vma); - void (*config_fini)(struct intel_initial_plane_config *plane_configs); + void (*config_fini)(struct intel_initial_plane_config *plane_config); }; struct intel_display_irq_interface { @@ -176,8 +182,11 @@ struct intel_display_stolen_interface { void (*node_free)(const struct intel_stolen_node *node); }; -struct intel_display_vma_interface { - int (*fence_id)(const struct i915_vma *vma); +struct intel_display_vlv_iosf_interface { + void (*get)(struct drm_device *drm, unsigned long unit_mask); + void (*put)(struct drm_device *drm, unsigned long unit_mask); + u32 (*read)(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr); + int (*write)(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr, u32 val); }; /** @@ -235,8 +244,8 @@ struct intel_display_parent_interface { /** @stolen: Stolen memory. */ const struct intel_display_stolen_interface *stolen; - /** @vma: VMA interface. Optional. */ - const struct intel_display_vma_interface *vma; + /** @vlv_iosf: VLV IOSF sideband. Optional. */ + const struct intel_display_vlv_iosf_interface *vlv_iosf; /* Generic independent functions */ struct { diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h b/include/drm/intel/mchbar_regs.h similarity index 98% rename from drivers/gpu/drm/i915/intel_mchbar_regs.h rename to include/drm/intel/mchbar_regs.h index 614d4017b57b..ca0d421be16c 100644 --- a/drivers/gpu/drm/i915/intel_mchbar_regs.h +++ b/include/drm/intel/mchbar_regs.h @@ -16,11 +16,16 @@ * every way. It is not accessible from the CP register read instructions. * * Starting from Haswell, you can't write registers using the MCHBAR mirror, - * just read. + * just read. On MTL+ the mirror no longer exists. */ #define MCHBAR_MIRROR_BASE 0x10000 +#define MCHBAR_MIRROR_END 0x13fff + #define MCHBAR_MIRROR_BASE_SNB 0x140000 +#define MCHBAR_MIRROR_END_SNB 0x147fff +#define MCHBAR_MIRROR_END_ICL_RKL 0x14ffff +#define MCHBAR_MIRROR_END_TGL 0x15ffff #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34) #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48) diff --git a/drivers/gpu/drm/i915/intel_pci_config.h b/include/drm/intel/pci_config.h similarity index 100% rename from drivers/gpu/drm/i915/intel_pci_config.h rename to include/drm/intel/pci_config.h diff --git a/drivers/gpu/drm/i915/vlv_iosf_sb_reg.h b/include/drm/intel/vlv_iosf_sb_regs.h similarity index 95% rename from drivers/gpu/drm/i915/vlv_iosf_sb_reg.h rename to include/drm/intel/vlv_iosf_sb_regs.h index f977fb3b6e17..42d1def5534b 100644 --- a/drivers/gpu/drm/i915/vlv_iosf_sb_reg.h +++ b/include/drm/intel/vlv_iosf_sb_regs.h @@ -3,8 +3,20 @@ * Copyright © 2022 Intel Corporation */ -#ifndef _VLV_IOSF_SB_REG_H_ -#define _VLV_IOSF_SB_REG_H_ +#ifndef _VLV_IOSF_SB_REGS_H_ +#define _VLV_IOSF_SB_REGS_H_ + +enum vlv_iosf_sb_unit { + VLV_IOSF_SB_BUNIT, + VLV_IOSF_SB_CCK, + VLV_IOSF_SB_CCU, + VLV_IOSF_SB_DPIO, + VLV_IOSF_SB_DPIO_2, + VLV_IOSF_SB_FLISDSI, + VLV_IOSF_SB_GPIO, + VLV_IOSF_SB_NC, + VLV_IOSF_SB_PUNIT, +}; /* See configdb bunit SB addr map */ #define BUNIT_REG_BISOC 0x11 @@ -177,4 +189,4 @@ #define CCK_FREQUENCY_STATUS_SHIFT 8 #define CCK_FREQUENCY_VALUES (0x1f << 0) -#endif /* _VLV_IOSF_SB_REG_H_ */ +#endif /* _VLV_IOSF_SB_REGS_H_ */ diff --git a/include/linux/cdrom.h b/include/linux/cdrom.h index b907e6c2307d..260d7968cf72 100644 --- a/include/linux/cdrom.h +++ b/include/linux/cdrom.h @@ -108,6 +108,7 @@ int cdrom_ioctl(struct cdrom_device_info *cdi, struct block_device *bdev, extern unsigned int cdrom_check_events(struct cdrom_device_info *cdi, unsigned int clearing); +extern void cdrom_probe_write_features(struct cdrom_device_info *cdi); extern int register_cdrom(struct gendisk *disk, struct cdrom_device_info *cdi); extern void unregister_cdrom(struct cdrom_device_info *cdi); diff --git a/include/linux/dma-buf.h b/include/linux/dma-buf.h index 166933b82e27..d1203da56fc5 100644 --- a/include/linux/dma-buf.h +++ b/include/linux/dma-buf.h @@ -322,13 +322,13 @@ struct dma_buf { * @vmapping_counter: * * Used internally to refcnt the vmaps returned by dma_buf_vmap(). - * Protected by @lock. + * Protected by @resv. */ unsigned vmapping_counter; /** * @vmap_ptr: - * The current vmap ptr if @vmapping_counter > 0. Protected by @lock. + * The current vmap ptr if @vmapping_counter > 0. Protected by @resv. */ struct iosys_map vmap_ptr; diff --git a/include/linux/dpll.h b/include/linux/dpll.h index b7277a8b484d..f8037f1ab20b 100644 --- a/include/linux/dpll.h +++ b/include/linux/dpll.h @@ -286,6 +286,7 @@ int dpll_pin_ref_sync_pair_add(struct dpll_pin *pin, int dpll_device_change_ntf(struct dpll_device *dpll); +int __dpll_pin_change_ntf(struct dpll_pin *pin); int dpll_pin_change_ntf(struct dpll_pin *pin); int register_dpll_notifier(struct notifier_block *nb); diff --git a/include/linux/fsnotify_backend.h b/include/linux/fsnotify_backend.h index 95985400d3d8..e5cde39d6e85 100644 --- a/include/linux/fsnotify_backend.h +++ b/include/linux/fsnotify_backend.h @@ -915,6 +915,7 @@ extern void fsnotify_clear_marks_by_group(struct fsnotify_group *group, unsigned int obj_type); extern void fsnotify_get_mark(struct fsnotify_mark *mark); extern void fsnotify_put_mark(struct fsnotify_mark *mark); +struct fsnotify_mark *fsnotify_next_mark(struct fsnotify_mark *mark); extern void fsnotify_finish_user_wait(struct fsnotify_iter_info *iter_info); extern bool fsnotify_prepare_user_wait(struct fsnotify_iter_info *iter_info); diff --git a/include/linux/mailbox_client.h b/include/linux/mailbox_client.h index c6eea9afb943..e5997120f45c 100644 --- a/include/linux/mailbox_client.h +++ b/include/linux/mailbox_client.h @@ -45,6 +45,7 @@ int mbox_send_message(struct mbox_chan *chan, void *mssg); int mbox_flush(struct mbox_chan *chan, unsigned long timeout); void mbox_client_txdone(struct mbox_chan *chan, int r); /* atomic */ bool mbox_client_peek_data(struct mbox_chan *chan); /* atomic */ +unsigned int mbox_chan_tx_slots_available(struct mbox_chan *chan); /* atomic */ void mbox_free_channel(struct mbox_chan *chan); /* may sleep */ #endif /* __MAILBOX_CLIENT_H */ diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_controller.h index 80a427c7ca29..dc93287a2a01 100644 --- a/include/linux/mailbox_controller.h +++ b/include/linux/mailbox_controller.h @@ -3,6 +3,7 @@ #ifndef __MAILBOX_CONTROLLER_H #define __MAILBOX_CONTROLLER_H +#include #include #include #include @@ -11,6 +12,13 @@ struct mbox_chan; +/* Sentinel value distinguishing "no active request" from "NULL message data" */ +#define MBOX_NO_MSG ((void *)-1) + +#define MBOX_TXDONE_BY_IRQ BIT(0) /* controller has remote RTR irq */ +#define MBOX_TXDONE_BY_POLL BIT(1) /* controller can read status of last TX */ +#define MBOX_TXDONE_BY_ACK BIT(2) /* S/W ACK received by Client ticks the TX */ + /** * struct mbox_chan_ops - methods to control mailbox channels * @send_data: The API asks the MBOX controller driver, in atomic @@ -54,10 +62,10 @@ struct mbox_chan_ops { /** * struct mbox_controller - Controller of a class of communication channels - * @dev: Device backing this controller - * @ops: Operators that work on each communication chan - * @chans: Array of channels - * @num_chans: Number of channels in the 'chans' array. + * @dev: Device backing this controller. Required. + * @ops: Operators that work on each communication chan. Required. + * @chans: Array of channels. Required. + * @num_chans: Number of channels in the 'chans' array. Required. * @txdone_irq: Indicates if the controller can report to API when * the last transmitted data was read by the remote. * Eg, if it has some TX ACK irq. @@ -70,6 +78,7 @@ struct mbox_chan_ops { * @of_xlate: Controller driver specific mapping of channel via DT * @poll_hrt: API private. hrtimer used to poll for TXDONE on all * channels. + * @poll_hrt_lock: API private. Lock protecting access to poll_hrt. * @node: API private. To hook into list of controllers. */ struct mbox_controller { diff --git a/include/linux/maple_tree.h b/include/linux/maple_tree.h index 0c464eade1d6..4a5631906aff 100644 --- a/include/linux/maple_tree.h +++ b/include/linux/maple_tree.h @@ -4,7 +4,7 @@ /* * Maple Tree - An RCU-safe adaptive tree for storing ranges * Copyright (c) 2018-2022 Oracle - * Authors: Liam R. Howlett + * Authors: Liam R. Howlett * Matthew Wilcox */ diff --git a/include/linux/mm.h b/include/linux/mm.h index 0b776907152e..af23453e9dbd 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -4391,7 +4391,7 @@ static inline void mmap_action_map_kernel_pages_full(struct vm_area_desc *desc, int mmap_action_prepare(struct vm_area_desc *desc); int mmap_action_complete(struct vm_area_struct *vma, - struct mmap_action *action); + struct mmap_action *action, bool is_compat); /* Look up the first VMA which exactly match the interval vm_start ... vm_end */ static inline struct vm_area_struct *find_exact_vma(struct mm_struct *mm, diff --git a/include/linux/mroute_base.h b/include/linux/mroute_base.h index cf3374580f74..5d75cc5b057e 100644 --- a/include/linux/mroute_base.h +++ b/include/linux/mroute_base.h @@ -226,6 +226,7 @@ struct mr_table_ops { /** * struct mr_table - a multicast routing table + * @work: used for table destruction * @list: entry within a list of multicast routing tables * @net: net where this table belongs * @ops: protocol specific operations @@ -243,6 +244,7 @@ struct mr_table_ops { * @mroute_reg_vif_num: PIM-device vif index */ struct mr_table { + struct rcu_work work; struct list_head list; possible_net_t net; struct mr_table_ops ops; @@ -274,6 +276,7 @@ void vif_device_init(struct vif_device *v, unsigned short flags, unsigned short get_iflink_mask); +void mr_table_free(struct mr_table *mrt); struct mr_table * mr_table_alloc(struct net *net, u32 id, struct mr_table_ops *ops, diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 58abd306ebe3..782984ba3a20 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -290,6 +290,12 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) +#define SPINAND_PAGE_READ_PACKED_8D_8D_0_OP(addr) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_PACKED_CMD(0x13, addr >> 16, 8), \ + SPI_MEM_DTR_OP_ADDR(2, addr & 0xffff, 8), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + #define SPINAND_PAGE_READ_FROM_CACHE_8D_8D_8D_OP(addr, ndummy, buf, len, freq) \ SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x9d, 8), \ SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ @@ -483,6 +489,7 @@ struct spinand_ecc_info { #define SPINAND_HAS_PROG_PLANE_SELECT_BIT BIT(2) #define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3) #define SPINAND_NO_RAW_ACCESS BIT(4) +#define SPINAND_ODTR_PACKED_PAGE_READ BIT(5) /** * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure diff --git a/include/linux/nvme-auth.h b/include/linux/nvme-auth.h index 682f81046345..d674d8ab26e6 100644 --- a/include/linux/nvme-auth.h +++ b/include/linux/nvme-auth.h @@ -49,9 +49,9 @@ int nvme_auth_augmented_challenge(u8 hmac_id, const u8 *skey, size_t skey_len, int nvme_auth_gen_privkey(struct crypto_kpp *dh_tfm, u8 dh_gid); int nvme_auth_gen_pubkey(struct crypto_kpp *dh_tfm, u8 *host_key, size_t host_key_len); -int nvme_auth_gen_shared_secret(struct crypto_kpp *dh_tfm, - const u8 *ctrl_key, size_t ctrl_key_len, - u8 *sess_key, size_t sess_key_len); +int nvme_auth_gen_session_key(struct crypto_kpp *dh_tfm, + const u8 *public_key, size_t public_key_len, + u8 *sess_key, size_t sess_key_len, u8 hash_id); int nvme_auth_generate_psk(u8 hmac_id, const u8 *skey, size_t skey_len, const u8 *c1, const u8 *c2, size_t hash_len, u8 **ret_psk, size_t *ret_len); diff --git a/include/linux/rculist.h b/include/linux/rculist.h index 2abba7552605..e3bc44225692 100644 --- a/include/linux/rculist.h +++ b/include/linux/rculist.h @@ -261,6 +261,35 @@ static inline void list_replace_rcu(struct list_head *old, old->prev = LIST_POISON2; } +static inline void __list_splice_rcu(struct list_head *list, + struct list_head *prev, + struct list_head *next) +{ + struct list_head *first = list->next; + struct list_head *last = list->prev; + + last->next = next; + first->prev = prev; + next->prev = last; + rcu_assign_pointer(list_next_rcu(prev), first); +} + +/** + * list_splice_rcu - splice a non-RCU list into an RCU-protected list, + * designed for stacks. + * @list: the non RCU-protected list to splice + * @head: the place in the existing RCU-protected list to splice + * + * The list pointed to by @head can be RCU-read traversed concurrently with + * this function. + */ +static inline void list_splice_rcu(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) + __list_splice_rcu(list, head, head->next); +} + /** * __list_splice_init_rcu - join an RCU-protected list into an existing list. * @list: the RCU-protected list to splice diff --git a/include/linux/rhashtable-types.h b/include/linux/rhashtable-types.h index 015c8298bebc..fc2f596a6df1 100644 --- a/include/linux/rhashtable-types.h +++ b/include/linux/rhashtable-types.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -49,6 +50,7 @@ typedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *arg, * @head_offset: Offset of rhash_head in struct to be hashed * @max_size: Maximum size while expanding * @min_size: Minimum size while shrinking + * @insecure_elasticity: Set to true to disable chain length checks * @automatic_shrinking: Enable automatic shrinking of tables * @hashfn: Hash function (default: jhash2 if !(key_len % 4), or jhash) * @obj_hashfn: Function to hash object @@ -61,6 +63,7 @@ struct rhashtable_params { u16 head_offset; unsigned int max_size; u16 min_size; + bool insecure_elasticity; bool automatic_shrinking; rht_hashfn_t hashfn; rht_obj_hashfn_t obj_hashfn; @@ -75,6 +78,7 @@ struct rhashtable_params { * @p: Configuration parameters * @rhlist: True if this is an rhltable * @run_work: Deferred worker to expand/shrink asynchronously + * @run_irq_work: Bounces the @run_work kick through hard IRQ context. * @mutex: Mutex to protect current/future table swapping * @lock: Spin lock to protect walker list * @nelems: Number of elements in table @@ -86,6 +90,7 @@ struct rhashtable { struct rhashtable_params p; bool rhlist; struct work_struct run_work; + struct irq_work run_irq_work; struct mutex mutex; spinlock_t lock; atomic_t nelems; diff --git a/include/linux/rhashtable.h b/include/linux/rhashtable.h index 0480509a6339..ef5230cece36 100644 --- a/include/linux/rhashtable.h +++ b/include/linux/rhashtable.h @@ -20,6 +20,7 @@ #include #include +#include #include #include #include @@ -821,14 +822,15 @@ static __always_inline void *__rhashtable_insert_fast( goto out; } - if (elasticity <= 0) + if (elasticity <= 0 && !params.insecure_elasticity) goto slow_path; data = ERR_PTR(-E2BIG); if (unlikely(rht_grow_above_max(ht, tbl))) goto out_unlock; - if (unlikely(rht_grow_above_100(ht, tbl))) + if (unlikely(rht_grow_above_100(ht, tbl)) && + !params.insecure_elasticity) goto slow_path; /* Inserting at head of list makes unlocking free. */ @@ -846,7 +848,7 @@ static __always_inline void *__rhashtable_insert_fast( rht_assign_unlock(tbl, bkt, obj, flags); if (rht_grow_above_75(ht, tbl)) - schedule_work(&ht->run_work); + irq_work_queue(&ht->run_irq_work); data = NULL; out: diff --git a/include/linux/tracepoint.h b/include/linux/tracepoint.h index 578e520b6ee6..763eea4d80d8 100644 --- a/include/linux/tracepoint.h +++ b/include/linux/tracepoint.h @@ -202,7 +202,7 @@ static inline struct tracepoint *tracepoint_ptr_deref(tracepoint_ptr_t *p) #define TP_CONDITION(args...) args /* - * Individual subsystem my have a separate configuration to + * Individual subsystem may have a separate configuration to * enable their tracepoints. By default, this file will create * the tracepoints if CONFIG_TRACEPOINTS is defined. If a subsystem * wants to be able to disable its tracepoints from being created diff --git a/include/net/bond_3ad.h b/include/net/bond_3ad.h index c92d4a976246..05572c19e14b 100644 --- a/include/net/bond_3ad.h +++ b/include/net/bond_3ad.h @@ -243,7 +243,7 @@ typedef struct port { churn_state_t sm_churn_actor_state; churn_state_t sm_churn_partner_state; struct slave *slave; /* pointer to the bond slave that this port belongs to */ - struct aggregator *aggregator; /* pointer to an aggregator that this port related to */ + struct aggregator __rcu *aggregator; /* pointer to an aggregator that this port related to */ struct port *next_port_in_aggregator; /* Next port on the linked list of the parent aggregator */ u32 transaction_id; /* continuous number for identification of Marker PDU's; */ struct lacpdu lacpdu; /* the lacpdu that will be sent for this port */ diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h index 2c0173d9309c..cff7b773e972 100644 --- a/include/net/netfilter/nf_tables.h +++ b/include/net/netfilter/nf_tables.h @@ -1204,12 +1204,15 @@ struct nft_stats { struct u64_stats_sync syncp; }; +#define NFT_HOOK_REMOVE (1 << 0) + struct nft_hook { struct list_head list; struct list_head ops_list; struct rcu_head rcu; char ifname[IFNAMSIZ]; u8 ifnamelen; + u8 flags; }; struct nf_hook_ops *nft_hook_find_ops(const struct nft_hook *hook, @@ -1664,6 +1667,16 @@ struct nft_trans { u8 put_net:1; }; +/** + * struct nft_trans_hook - nf_tables hook update in transaction + * @list: used internally + * @hook: struct nft_hook with the device hook + */ +struct nft_trans_hook { + struct list_head list; + struct nft_hook *hook; +}; + /** * struct nft_trans_binding - nf_tables object with binding support in transaction * @nft_trans: base structure, MUST be first member diff --git a/include/net/netmem.h b/include/net/netmem.h index 507b74c9f52d..78fe51e5756b 100644 --- a/include/net/netmem.h +++ b/include/net/netmem.h @@ -127,6 +127,21 @@ static inline unsigned int net_iov_idx(const struct net_iov *niov) return niov - net_iov_owner(niov)->niovs; } +/* Initialize a niov: stamp the owning area, the memory provider type, + * and the page_type "no type" sentinel expected by the page-type API + * (see PAGE_TYPE_OPS in ) so that + * page_pool_set_pp_info() can later call __SetPageNetpp() on a niov + * cast to struct page. + */ +static inline void net_iov_init(struct net_iov *niov, + struct net_iov_area *owner, + enum net_iov_type type) +{ + niov->owner = owner; + niov->type = type; + niov->page_type = UINT_MAX; +} + /* netmem */ /** diff --git a/include/uapi/drm/drm_ras.h b/include/uapi/drm/drm_ras.h index 5f40fa5b869d..218a3ee86805 100644 --- a/include/uapi/drm/drm_ras.h +++ b/include/uapi/drm/drm_ras.h @@ -41,6 +41,7 @@ enum { enum { DRM_RAS_CMD_LIST_NODES = 1, DRM_RAS_CMD_GET_ERROR_COUNTER, + DRM_RAS_CMD_CLEAR_ERROR_COUNTER, __DRM_RAS_CMD_MAX, DRM_RAS_CMD_MAX = (__DRM_RAS_CMD_MAX - 1) diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index ae2fda23ce7c..48e9f1fdb78d 100644 --- a/include/uapi/drm/xe_drm.h +++ b/include/uapi/drm/xe_drm.h @@ -83,6 +83,7 @@ extern "C" { * - &DRM_IOCTL_XE_OBSERVATION * - &DRM_IOCTL_XE_MADVISE * - &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS + * - &DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY * - &DRM_IOCTL_XE_VM_GET_PROPERTY */ @@ -167,7 +168,7 @@ extern "C" { * Typically the struct drm_xe_user_extension would be embedded in some uAPI * struct, and in this case we would feed it the head of the chain(i.e ext1), * which would then apply all of the above extensions. -*/ + */ /** * struct drm_xe_user_extension - Base class for defining a chain of extensions @@ -229,9 +230,9 @@ struct drm_xe_ext_set_property { /** * struct drm_xe_engine_class_instance - instance of an engine class * - * It is returned as part of the @drm_xe_engine, but it also is used as - * the input of engine selection for both @drm_xe_exec_queue_create and - * @drm_xe_query_engine_cycles + * It is returned as part of the &struct drm_xe_engine, but it also is used as + * the input of engine selection for both &struct drm_xe_exec_queue_create and + * &struct drm_xe_query_engine_cycles * * The @engine_class can be: * - %DRM_XE_ENGINE_CLASS_RENDER @@ -264,7 +265,7 @@ struct drm_xe_engine_class_instance { * struct drm_xe_engine - describe hardware engine */ struct drm_xe_engine { - /** @instance: The @drm_xe_engine_class_instance */ + /** @instance: The &struct drm_xe_engine_class_instance */ struct drm_xe_engine_class_instance instance; /** @reserved: Reserved */ @@ -274,9 +275,9 @@ struct drm_xe_engine { /** * struct drm_xe_query_engines - describe engines * - * If a query is made with a struct @drm_xe_device_query where .query + * If a query is made with a &struct drm_xe_device_query where .query * is equal to %DRM_XE_DEVICE_QUERY_ENGINES, then the reply uses an array of - * struct @drm_xe_query_engines in .data. + * &struct drm_xe_query_engines in .data. */ struct drm_xe_query_engines { /** @num_engines: number of engines returned in @engines */ @@ -349,7 +350,7 @@ struct drm_xe_mem_region { * is smaller than @total_size then this is referred to as a * small BAR system. * - * On systems without small BAR (full BAR), the probed_size will + * On systems without small BAR (full BAR), the @cpu_visible_size will * always equal the @total_size, since all of it will be CPU * accessible. * @@ -410,7 +411,7 @@ struct drm_xe_query_mem_regions { * device supports the userspace hint %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION. * This is exposed only on Xe2+. * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX - Flag is set - * if a queue can be creaed with + * if a queue can be created with * %DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment * required by this device, typically SZ_4K or SZ_64K @@ -705,7 +706,10 @@ struct drm_xe_query_pxp_status { * attributes. * - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY * - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES + * - %DRM_XE_DEVICE_QUERY_UC_FW_VERSION + * - %DRM_XE_DEVICE_QUERY_OA_UNITS * - %DRM_XE_DEVICE_QUERY_PXP_STATUS + * - %DRM_XE_DEVICE_QUERY_EU_STALL * * If size is set to 0, the driver fills it with the required size for * the requested type of data to query. If size is equal to the required @@ -825,7 +829,7 @@ struct drm_xe_device_query { * * This ioctl supports setting the following properties via the * %DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY extension, which uses the - * generic @drm_xe_ext_set_property struct: + * generic &struct drm_xe_ext_set_property: * * - %DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE - set the type of PXP session * this object will be used with. Valid values are listed in enum @@ -862,8 +866,7 @@ struct drm_xe_gem_create { #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2) #define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION (1 << 3) /** - * @flags: Flags, currently a mask of memory instances of where BO can - * be placed + * @flags: Flags for the GEM object, see DRM_XE_GEM_CREATE_FLAG_* */ __u32 flags; @@ -888,7 +891,7 @@ struct drm_xe_gem_create { #define DRM_XE_GEM_CPU_CACHING_WC 2 /** * @cpu_caching: The CPU caching mode to select for this object. If - * mmaping the object the mode selected here will also be used. The + * mmapping the object the mode selected here will also be used. The * exception is when mapping system memory (including data evicted * to system) on discrete GPUs. The caching mode selected will * then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency @@ -931,7 +934,7 @@ struct drm_xe_gem_create { * * err = ioctl(fd, DRM_IOCTL_XE_GEM_MMAP_OFFSET, &mmo); * map = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, mmo.offset); - * map[i] = 0xdeadbeaf; // issue barrier + * map[i] = 0xdeadbeef; // issue barrier */ struct drm_xe_gem_mmap_offset { /** @extensions: Pointer to the first extension struct, if any */ @@ -958,8 +961,8 @@ struct drm_xe_gem_mmap_offset { * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE - Map the whole virtual address * space of the VM to scratch page. A vm_bind would overwrite the scratch * page mapping. This flag is mutually exclusive with the - * %DRM_XE_VM_CREATE_FLAG_FAULT_MODE flag, with an exception of on x2 and - * xe3 platform. + * %DRM_XE_VM_CREATE_FLAG_FAULT_MODE flag, with an exception on Xe2 and + * Xe3 platforms. * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts * exec submissions to its exec_queues that don't have an upper time * limit on the job execution time. But exec submissions to these @@ -1045,7 +1048,7 @@ struct drm_xe_vm_destroy { * set, no mappings are created rather the range is reserved for CPU address * mirroring which will be populated on GPU page faults or prefetches. Only * valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address - * mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO + * mirror flag is only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO * handle MBZ, and the BO offset MBZ. * - %DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET - Can be used in combination with * %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR to reset madvises when the underlying @@ -1061,6 +1064,7 @@ struct drm_xe_vm_destroy { * not invoke autoreset. Neither will stack variables going out of scope. * Therefore it's recommended to always explicitly reset the madvises when * freeing the memory backing a region used in a &DRM_IOCTL_XE_MADVISE call. + * * - %DRM_XE_VM_BIND_FLAG_DECOMPRESS - Request on-device decompression for a MAP. * When set on a MAP bind operation, request the driver schedule an on-device * in-place decompression (via the migrate/resolve path) for the GPU mapping @@ -1109,7 +1113,7 @@ struct drm_xe_vm_bind_op { * ppGTT WT -> COH_NONE * ppGTT WB -> COH_AT_LEAST_1WAY * - * In practice UC/WC/WT should only ever used for scanout surfaces on + * In practice UC/WC/WT should only ever be used for scanout surfaces on * such platforms (or perhaps in general for dma-buf if shared with * another device) since it is only the display engine that is actually * incoherent. Everything else should typically use WB given that we @@ -1199,10 +1203,10 @@ struct drm_xe_vm_bind_op { /** * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND * - * Below is an example of a minimal use of @drm_xe_vm_bind to + * Below is an example of a minimal use of &struct drm_xe_vm_bind to * asynchronously bind the buffer `data` at address `BIND_ADDRESS` to * illustrate `userptr`. It can be synchronized by using the example - * provided for @drm_xe_sync. + * provided for &struct drm_xe_sync. * * .. code-block:: C * @@ -1355,7 +1359,7 @@ struct drm_xe_vm_get_property { * * This ioctl supports setting the following properties via the * %DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY extension, which uses the - * generic @drm_xe_ext_set_property struct: + * generic &struct drm_xe_ext_set_property: * * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY - set the queue priority. * CAP_SYS_NICE is required to set a value above normal. @@ -1366,7 +1370,7 @@ struct drm_xe_vm_get_property { * drm_xe_pxp_session_type. %DRM_XE_PXP_TYPE_NONE is the default behavior, so * there is no need to explicitly set that. When a queue of type * %DRM_XE_PXP_TYPE_HWDRM is created, the PXP default HWDRM session - * (%XE_PXP_HWDRM_DEFAULT_SESSION) will be started, if isn't already running. + * (%DRM_XE_PXP_HWDRM_DEFAULT_SESSION) will be started, if it isn't already running. * The user is expected to query the PXP status via the query ioctl (see * %DRM_XE_DEVICE_QUERY_PXP_STATUS) and to wait for PXP to be ready before * attempting to create a queue with this property. When a queue is created @@ -1390,9 +1394,9 @@ struct drm_xe_vm_get_property { * enable render color cache keying on BTP+BTI instead of just BTI * (only valid for render queues). * - * The example below shows how to use @drm_xe_exec_queue_create to create + * The example below shows how to use &struct drm_xe_exec_queue_create to create * a simple exec_queue (no parallel submission) of class - * &DRM_XE_ENGINE_CLASS_RENDER. + * %DRM_XE_ENGINE_CLASS_RENDER. * * .. code-block:: C * @@ -1402,23 +1406,25 @@ struct drm_xe_vm_get_property { * struct drm_xe_exec_queue_create exec_queue_create = { * .extensions = 0, * .vm_id = vm, - * .num_bb_per_exec = 1, - * .num_eng_per_bb = 1, + * .width = 1, + * .num_placements = 1, * .instances = to_user_pointer(&instance), * }; * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); * - * Allow users to provide a hint to kernel for cases demanding low latency - * profile. Please note it will have impact on power consumption. User can - * indicate low latency hint with flag while creating exec queue as - * mentioned below, + * Allow users to provide a hint to kernel for cases demanding low latency + * profile. Please note it will have impact on power consumption. User can + * indicate low latency hint with flag while creating exec queue as + * mentioned below: + * + * .. code-block:: C * * struct drm_xe_exec_queue_create exec_queue_create = { * .flags = DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT, * .extensions = 0, * .vm_id = vm, - * .num_bb_per_exec = 1, - * .num_eng_per_bb = 1, + * .width = 1, + * .num_placements = 1, * .instances = to_user_pointer(&instance), * }; * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); @@ -1515,7 +1521,7 @@ struct drm_xe_exec_queue_get_property { * and the @flags can be: * - %DRM_XE_SYNC_FLAG_SIGNAL * - * A minimal use of @drm_xe_sync looks like this: + * A minimal use of &struct drm_xe_sync looks like this: * * .. code-block:: C * @@ -1546,7 +1552,7 @@ struct drm_xe_sync { #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0 #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1 #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2 - /** @type: Type of the this sync object */ + /** @type: Type of this sync object */ __u32 type; #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0) @@ -1559,9 +1565,9 @@ struct drm_xe_sync { /** * @addr: Address of user fence. When sync is passed in via exec - * IOCTL this is a GPU address in the VM. When sync passed in via + * IOCTL this is a GPU address in the VM. When sync is passed in via * VM bind IOCTL this is a user pointer. In either case, it is - * the users responsibility that this address is present and + * the user's responsibility that this address is present and * mapped when the user fence is signalled. Must be qword * aligned. */ @@ -1581,10 +1587,10 @@ struct drm_xe_sync { /** * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC * - * This is an example to use @drm_xe_exec for execution of the object - * at BIND_ADDRESS (see example in @drm_xe_vm_bind) by an exec_queue - * (see example in @drm_xe_exec_queue_create). It can be synchronized - * by using the example provided for @drm_xe_sync. + * This is an example to use &struct drm_xe_exec for execution of the object + * at BIND_ADDRESS (see example in &struct drm_xe_vm_bind) by an exec_queue + * (see example in &struct drm_xe_exec_queue_create). It can be synchronized + * by using the example provided for &struct drm_xe_sync. * * .. code-block:: C * @@ -1651,7 +1657,6 @@ struct drm_xe_exec { * * and the @flags can be: * - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME - * - %DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP * * The @mask values can be for example: * - 0xffu for u8 @@ -1664,7 +1669,7 @@ struct drm_xe_wait_user_fence { __u64 extensions; /** - * @addr: user pointer address to wait on, must qword aligned + * @addr: user pointer address to wait on, must be qword aligned */ __u64 addr; @@ -1695,9 +1700,9 @@ struct drm_xe_wait_user_fence { * Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) * it contains timeout expressed in nanoseconds to wait (fence will * expire at now() + timeout). - * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait - * will end at timeout (uses system MONOTONIC_CLOCK). - * Passing negative timeout leads to neverending wait. + * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag is set (absolute timeout) wait + * will end at timeout (uses system CLOCK_MONOTONIC). + * Passing negative timeout leads to never ending wait. * * On relative timeout this value is updated with timeout left * (for restarting the call in case of signal delivery). @@ -1741,7 +1746,7 @@ enum drm_xe_observation_op { }; /** - * struct drm_xe_observation_param - Input of &DRM_XE_OBSERVATION + * struct drm_xe_observation_param - Input of &DRM_IOCTL_XE_OBSERVATION * * The observation layer enables multiplexing observation streams of * multiple types. The actual params for a particular stream operation are @@ -1751,25 +1756,25 @@ enum drm_xe_observation_op { struct drm_xe_observation_param { /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; - /** @observation_type: observation stream type, of enum @drm_xe_observation_type */ + /** @observation_type: observation stream type, of &enum drm_xe_observation_type */ __u64 observation_type; - /** @observation_op: observation stream op, of enum @drm_xe_observation_op */ + /** @observation_op: observation stream op, of &enum drm_xe_observation_op */ __u64 observation_op; /** @param: Pointer to actual stream params */ __u64 param; }; /** - * enum drm_xe_observation_ioctls - Observation stream fd ioctl's + * enum drm_xe_observation_ioctls - Observation stream fd ioctls * * Information exchanged between userspace and kernel for observation fd - * ioctl's is stream type specific + * ioctls is stream type specific */ enum drm_xe_observation_ioctls { /** @DRM_XE_OBSERVATION_IOCTL_ENABLE: Enable data capture for an observation stream */ DRM_XE_OBSERVATION_IOCTL_ENABLE = _IO('i', 0x0), - /** @DRM_XE_OBSERVATION_IOCTL_DISABLE: Disable data capture for a observation stream */ + /** @DRM_XE_OBSERVATION_IOCTL_DISABLE: Disable data capture for an observation stream */ DRM_XE_OBSERVATION_IOCTL_DISABLE = _IO('i', 0x1), /** @DRM_XE_OBSERVATION_IOCTL_CONFIG: Change observation stream configuration */ @@ -1812,7 +1817,7 @@ struct drm_xe_oa_unit { /** @oa_unit_id: OA unit ID */ __u32 oa_unit_id; - /** @oa_unit_type: OA unit type of @drm_xe_oa_unit_type */ + /** @oa_unit_type: OA unit type of &enum drm_xe_oa_unit_type */ __u32 oa_unit_type; /** @capabilities: OA capabilities bit-mask */ @@ -1875,7 +1880,7 @@ struct drm_xe_query_oa_units { /** @pad: MBZ */ __u32 pad; /** - * @oa_units: struct @drm_xe_oa_unit array returned for this device. + * @oa_units: &struct drm_xe_oa_unit array returned for this device. * Written below as a u64 array to avoid problems with nested flexible * arrays with some compilers */ @@ -1902,24 +1907,24 @@ enum drm_xe_oa_format_type { }; /** - * enum drm_xe_oa_property_id - OA stream property id's + * enum drm_xe_oa_property_id - OA stream property IDs * - * Stream params are specified as a chain of @drm_xe_ext_set_property - * struct's, with @property values from enum @drm_xe_oa_property_id and - * @drm_xe_user_extension base.name set to @DRM_XE_OA_EXTENSION_SET_PROPERTY. - * @param field in struct @drm_xe_observation_param points to the first - * @drm_xe_ext_set_property struct. + * Stream params are specified as a chain of &struct drm_xe_ext_set_property + * structs, with property values from &enum drm_xe_oa_property_id and + * &struct drm_xe_user_extension base.name set to %DRM_XE_OA_EXTENSION_SET_PROPERTY. + * The param field in &struct drm_xe_observation_param points to the first + * &struct drm_xe_ext_set_property struct. * * Exactly the same mechanism is also used for stream reconfiguration using the - * @DRM_XE_OBSERVATION_IOCTL_CONFIG observation stream fd ioctl, though only a + * %DRM_XE_OBSERVATION_IOCTL_CONFIG observation stream fd ioctl, though only a * subset of properties below can be specified for stream reconfiguration. */ enum drm_xe_oa_property_id { #define DRM_XE_OA_EXTENSION_SET_PROPERTY 0 /** * @DRM_XE_OA_PROPERTY_OA_UNIT_ID: ID of the OA unit on which to open - * the OA stream, see @oa_unit_id in 'struct - * drm_xe_query_oa_units'. Defaults to 0 if not provided. + * the OA stream, see oa_unit_id in &struct drm_xe_oa_unit. + * Defaults to 0 if not provided. */ DRM_XE_OA_PROPERTY_OA_UNIT_ID = 1, @@ -1932,7 +1937,7 @@ enum drm_xe_oa_property_id { /** * @DRM_XE_OA_PROPERTY_OA_METRIC_SET: OA metrics defining contents of OA - * reports, previously added via @DRM_XE_OBSERVATION_OP_ADD_CONFIG. + * reports, previously added via %DRM_XE_OBSERVATION_OP_ADD_CONFIG. */ DRM_XE_OA_PROPERTY_OA_METRIC_SET, @@ -1940,7 +1945,7 @@ enum drm_xe_oa_property_id { DRM_XE_OA_PROPERTY_OA_FORMAT, /* * OA_FORMAT's are specified the same way as in PRM/Bspec 52198/60942, - * in terms of the following quantities: a. enum @drm_xe_oa_format_type + * in terms of the following quantities: a. &enum drm_xe_oa_format_type * b. Counter select c. Counter size and d. BC report. Also refer to the * oa_formats array in drivers/gpu/drm/xe/xe_oa.c. */ @@ -1957,19 +1962,19 @@ enum drm_xe_oa_property_id { /** * @DRM_XE_OA_PROPERTY_OA_DISABLED: A value of 1 will open the OA - * stream in a DISABLED state (see @DRM_XE_OBSERVATION_IOCTL_ENABLE). + * stream in a DISABLED state (see %DRM_XE_OBSERVATION_IOCTL_ENABLE). */ DRM_XE_OA_PROPERTY_OA_DISABLED, /** * @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID: Open the stream for a specific - * @exec_queue_id. OA queries can be executed on this exec queue. + * exec_queue_id. OA queries can be executed on this exec queue. */ DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID, /** * @DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE: Optional engine instance to - * pass along with @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID or will default to 0. + * pass along with %DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID or will default to 0. */ DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, @@ -1981,16 +1986,16 @@ enum drm_xe_oa_property_id { /** * @DRM_XE_OA_PROPERTY_NUM_SYNCS: Number of syncs in the sync array - * specified in @DRM_XE_OA_PROPERTY_SYNCS + * specified in %DRM_XE_OA_PROPERTY_SYNCS */ DRM_XE_OA_PROPERTY_NUM_SYNCS, /** - * @DRM_XE_OA_PROPERTY_SYNCS: Pointer to struct @drm_xe_sync array - * with array size specified via @DRM_XE_OA_PROPERTY_NUM_SYNCS. OA + * @DRM_XE_OA_PROPERTY_SYNCS: Pointer to &struct drm_xe_sync array + * with array size specified via %DRM_XE_OA_PROPERTY_NUM_SYNCS. OA * configuration will wait till input fences signal. Output fences * will signal after the new OA configuration takes effect. For - * @DRM_XE_SYNC_TYPE_USER_FENCE, @addr is a user pointer, similar + * %DRM_XE_SYNC_TYPE_USER_FENCE, addr is a user pointer, similar * to the VM bind case. */ DRM_XE_OA_PROPERTY_SYNCS, @@ -2013,15 +2018,15 @@ enum drm_xe_oa_property_id { /** * struct drm_xe_oa_config - OA metric configuration * - * Multiple OA configs can be added using @DRM_XE_OBSERVATION_OP_ADD_CONFIG. A + * Multiple OA configs can be added using %DRM_XE_OBSERVATION_OP_ADD_CONFIG. A * particular config can be specified when opening an OA stream using - * @DRM_XE_OA_PROPERTY_OA_METRIC_SET property. + * %DRM_XE_OA_PROPERTY_OA_METRIC_SET property. */ struct drm_xe_oa_config { /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; - /** @uuid: String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" */ + /** @uuid: String formatted like "%08x-%04x-%04x-%04x-%012x" */ char uuid[36]; /** @n_regs: Number of regs in @regs_ptr */ @@ -2036,7 +2041,7 @@ struct drm_xe_oa_config { /** * struct drm_xe_oa_stream_status - OA stream status returned from - * @DRM_XE_OBSERVATION_IOCTL_STATUS observation stream fd ioctl. Userspace can + * %DRM_XE_OBSERVATION_IOCTL_STATUS observation stream fd ioctl. Userspace can * call the ioctl to query stream status in response to EIO errno from * observation fd read(). */ @@ -2057,7 +2062,7 @@ struct drm_xe_oa_stream_status { /** * struct drm_xe_oa_stream_info - OA stream info returned from - * @DRM_XE_OBSERVATION_IOCTL_INFO observation stream fd ioctl + * %DRM_XE_OBSERVATION_IOCTL_INFO observation stream fd ioctl */ struct drm_xe_oa_stream_info { /** @extensions: Pointer to the first extension struct, if any */ @@ -2094,27 +2099,27 @@ enum drm_xe_pxp_session_type { * enum drm_xe_eu_stall_property_id - EU stall sampling input property ids. * * These properties are passed to the driver at open as a chain of - * @drm_xe_ext_set_property structures with @property set to these - * properties' enums and @value set to the corresponding values of these - * properties. @drm_xe_user_extension base.name should be set to - * @DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY. + * &struct drm_xe_ext_set_property structures with property set to these + * properties' enums and value set to the corresponding values of these + * properties. &struct drm_xe_user_extension base.name should be set to + * %DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY. * * With the file descriptor obtained from open, user space must enable - * the EU stall stream fd with @DRM_XE_OBSERVATION_IOCTL_ENABLE before + * the EU stall stream fd with %DRM_XE_OBSERVATION_IOCTL_ENABLE before * calling read(). EIO errno from read() indicates HW dropped data * due to full buffer. */ enum drm_xe_eu_stall_property_id { #define DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY 0 /** - * @DRM_XE_EU_STALL_PROP_GT_ID: @gt_id of the GT on which + * @DRM_XE_EU_STALL_PROP_GT_ID: gt_id of the GT on which * EU stall data will be captured. */ DRM_XE_EU_STALL_PROP_GT_ID = 1, /** * @DRM_XE_EU_STALL_PROP_SAMPLE_RATE: Sampling rate in - * GPU cycles from @sampling_rates in struct @drm_xe_query_eu_stall + * GPU cycles from sampling_rates in &struct drm_xe_query_eu_stall */ DRM_XE_EU_STALL_PROP_SAMPLE_RATE, @@ -2129,9 +2134,9 @@ enum drm_xe_eu_stall_property_id { /** * struct drm_xe_query_eu_stall - Information about EU stall sampling. * - * If a query is made with a struct @drm_xe_device_query where .query - * is equal to @DRM_XE_DEVICE_QUERY_EU_STALL, then the reply uses - * struct @drm_xe_query_eu_stall in .data. + * If a query is made with a &struct drm_xe_device_query where .query + * is equal to %DRM_XE_DEVICE_QUERY_EU_STALL, then the reply uses + * &struct drm_xe_query_eu_stall in .data. */ struct drm_xe_query_eu_stall { /** @extensions: Pointer to the first extension struct, if any */ @@ -2183,7 +2188,7 @@ struct drm_xe_query_eu_stall { * .start = 0x100000, * .range = 0x2000, * .type = DRM_XE_MEM_RANGE_ATTR_ATOMIC, - * .atomic_val = DRM_XE_ATOMIC_DEVICE, + * .atomic.val = DRM_XE_ATOMIC_DEVICE, * }; * * ioctl(fd, DRM_IOCTL_XE_MADVISE, &madvise); @@ -2242,7 +2247,7 @@ struct drm_xe_madvise { /** * @preferred_mem_loc.region_instance : Region instance. - * MBZ if @devmem_fd <= &DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE. + * MBZ if @devmem_fd <= %DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE. * Otherwise should point to the desired device * VRAM instance of the device indicated by * @preferred_mem_loc.devmem_fd. @@ -2369,24 +2374,19 @@ struct drm_xe_madvise { }; /** - * struct drm_xe_mem_range_attr - Output of &DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS + * struct drm_xe_mem_range_attr - Output of &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS * * This structure is provided by userspace and filled by KMD in response to the - * DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS ioctl. It describes memory attributes of - * a memory ranges within a user specified address range in a VM. + * DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS ioctl. It describes memory attributes of + * memory ranges within a user specified address range in a VM. * * The structure includes information such as atomic access policy, * page attribute table (PAT) index, and preferred memory location. * Userspace allocates an array of these structures and passes a pointer to the - * ioctl to retrieve attributes for each memory ranges - * - * @extensions: Pointer to the first extension struct, if any - * @start: Start address of the memory range - * @end: End address of the virtual memory range - * + * ioctl to retrieve attributes for each memory range. */ struct drm_xe_mem_range_attr { - /** @extensions: Pointer to the first extension struct, if any */ + /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; /** @start: start of the memory range */ @@ -2413,7 +2413,7 @@ struct drm_xe_mem_range_attr { __u32 reserved; } atomic; - /** @pat_index: Page attribute table index */ + /** @pat_index: Page attribute table index */ struct { /** @pat_index.val: PAT index */ __u32 val; @@ -2427,7 +2427,7 @@ struct drm_xe_mem_range_attr { }; /** - * struct drm_xe_vm_query_mem_range_attr - Input of &DRM_IOCTL_XE_VM_QUERY_MEM_ATTRIBUTES + * struct drm_xe_vm_query_mem_range_attr - Input of &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS * * This structure is used to query memory attributes of memory regions * within a user specified address range in a VM. It provides detailed @@ -2435,15 +2435,15 @@ struct drm_xe_mem_range_attr { * page attribute table (PAT) index, and preferred memory location. * * Userspace first calls the ioctl with @num_mem_ranges = 0, - * @sizeof_mem_ranges_attr = 0 and @vector_of_vma_mem_attr = NULL to retrieve + * @sizeof_mem_range_attr = 0 and @vector_of_mem_attr = NULL to retrieve * the number of memory regions and size of each memory range attribute. * Then, it allocates a buffer of that size and calls the ioctl again to fill * the buffer with memory range attributes. * * If second call fails with -ENOSPC, it means memory ranges changed between * first call and now, retry IOCTL again with @num_mem_ranges = 0, - * @sizeof_mem_ranges_attr = 0 and @vector_of_vma_mem_attr = NULL followed by - * Second ioctl call. + * @sizeof_mem_range_attr = 0 and @vector_of_mem_attr = NULL followed by + * second ioctl call. * * Example: * diff --git a/include/uapi/linux/io_uring.h b/include/uapi/linux/io_uring.h index 17ac1b785440..909fb7aea638 100644 --- a/include/uapi/linux/io_uring.h +++ b/include/uapi/linux/io_uring.h @@ -905,7 +905,8 @@ struct io_uring_buf_reg { __u32 ring_entries; __u16 bgid; __u16 flags; - __u64 resv[3]; + __u32 min_left; + __u32 resv[5]; }; /* argument for IORING_REGISTER_PBUF_STATUS */ diff --git a/io_uring/kbuf.c b/io_uring/kbuf.c index 8da2ff798170..63061aa1cab9 100644 --- a/io_uring/kbuf.c +++ b/io_uring/kbuf.c @@ -47,7 +47,7 @@ static bool io_kbuf_inc_commit(struct io_buffer_list *bl, int len) this_len = min_t(u32, len, buf_len); buf_len -= this_len; /* Stop looping for invalid buffer length of 0 */ - if (buf_len || !this_len) { + if (buf_len > bl->min_left_sub_one || !this_len) { WRITE_ONCE(buf->addr, READ_ONCE(buf->addr) + this_len); WRITE_ONCE(buf->len, buf_len); return false; @@ -637,6 +637,10 @@ int io_register_pbuf_ring(struct io_ring_ctx *ctx, void __user *arg) if (reg.ring_entries >= 65536) return -EINVAL; + /* minimum left byte count is a property of incremental buffers */ + if (!(reg.flags & IOU_PBUF_RING_INC) && reg.min_left) + return -EINVAL; + bl = io_buffer_get_list(ctx, reg.bgid); if (bl) { /* if mapped buffer ring OR classic exists, don't allow */ @@ -680,10 +684,11 @@ int io_register_pbuf_ring(struct io_ring_ctx *ctx, void __user *arg) } #endif - bl->nr_entries = reg.ring_entries; bl->mask = reg.ring_entries - 1; bl->flags |= IOBL_BUF_RING; bl->buf_ring = br; + if (reg.min_left) + bl->min_left_sub_one = reg.min_left - 1; if (reg.flags & IOU_PBUF_RING_INC) bl->flags |= IOBL_INC; ret = io_buffer_add_list(ctx, bl, reg.bgid); diff --git a/io_uring/kbuf.h b/io_uring/kbuf.h index bf15e26520d3..401773e1ef80 100644 --- a/io_uring/kbuf.h +++ b/io_uring/kbuf.h @@ -27,12 +27,18 @@ struct io_buffer_list { __u16 bgid; /* below is for ring provided buffers */ - __u16 nr_entries; __u16 head; __u16 mask; __u16 flags; + /* + * minimum required amount to be left to reuse an incrementally + * consumed buffer. If less than this is left at consumption time, + * buffer is done and head is incremented to the next buffer. + */ + __u32 min_left_sub_one; + struct io_mapped_region region; }; diff --git a/io_uring/napi.c b/io_uring/napi.c index 4a10de03e426..8d68366a4b90 100644 --- a/io_uring/napi.c +++ b/io_uring/napi.c @@ -276,6 +276,8 @@ static int io_napi_register_napi(struct io_ring_ctx *ctx, /* clean the napi list for new settings */ io_napi_free(ctx); WRITE_ONCE(ctx->napi_track_mode, napi->op_param); + /* cap NAPI at 10 msec of spin time */ + napi->busy_poll_to = min(10000, napi->busy_poll_to); WRITE_ONCE(ctx->napi_busy_poll_dt, napi->busy_poll_to * NSEC_PER_USEC); WRITE_ONCE(ctx->napi_prefer_busy_poll, !!napi->prefer_busy_poll); return 0; diff --git a/io_uring/tw.c b/io_uring/tw.c index fdff81eebc95..023d5e6bc491 100644 --- a/io_uring/tw.c +++ b/io_uring/tw.c @@ -273,8 +273,18 @@ void io_req_task_work_add_remote(struct io_kiocb *req, unsigned flags) void __cold io_move_task_work_from_local(struct io_ring_ctx *ctx) { - struct llist_node *node = llist_del_all(&ctx->work_llist); + struct llist_node *node; + /* + * Running the work items may utilize ->retry_llist as a means + * for capping the number of task_work entries run at the same + * time. But that list can potentially race with moving the work + * from here, if the task is exiting. As any normal task_work + * running holds ->uring_lock already, just guard this slow path + * with ->uring_lock to avoid racing on ->retry_llist. + */ + guard(mutex)(&ctx->uring_lock); + node = llist_del_all(&ctx->work_llist); __io_fallback_tw(node, false); node = llist_del_all(&ctx->retry_llist); __io_fallback_tw(node, false); diff --git a/io_uring/zcrx.c b/io_uring/zcrx.c index 7b93c87b8371..19837e0b5e91 100644 --- a/io_uring/zcrx.c +++ b/io_uring/zcrx.c @@ -495,10 +495,9 @@ static int io_zcrx_create_area(struct io_zcrx_ifq *ifq, for (i = 0; i < nr_iovs; i++) { struct net_iov *niov = &area->nia.niovs[i]; - niov->owner = &area->nia; + net_iov_init(niov, &area->nia, NET_IOV_IOURING); area->freelist[i] = i; atomic_set(&area->user_refs[i], 0); - niov->type = NET_IOV_IOURING; } if (ifq->dev) { diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c index 43adc96c7f1a..45c0b1ed687a 100644 --- a/kernel/cgroup/cgroup.c +++ b/kernel/cgroup/cgroup.c @@ -3934,33 +3934,41 @@ static int cgroup_cpu_pressure_show(struct seq_file *seq, void *v) static ssize_t pressure_write(struct kernfs_open_file *of, char *buf, size_t nbytes, enum psi_res res) { - struct cgroup_file_ctx *ctx = of->priv; + struct cgroup_file_ctx *ctx; struct psi_trigger *new; struct cgroup *cgrp; struct psi_group *psi; + ssize_t ret = 0; cgrp = cgroup_kn_lock_live(of->kn, false); if (!cgrp) return -ENODEV; - cgroup_get(cgrp); - cgroup_kn_unlock(of->kn); + ctx = of->priv; + if (!ctx) { + ret = -ENODEV; + goto out_unlock; + } /* Allow only one trigger per file descriptor */ if (ctx->psi.trigger) { - cgroup_put(cgrp); - return -EBUSY; + ret = -EBUSY; + goto out_unlock; } psi = cgroup_psi(cgrp); new = psi_trigger_create(psi, buf, res, of->file, of); if (IS_ERR(new)) { - cgroup_put(cgrp); - return PTR_ERR(new); + ret = PTR_ERR(new); + goto out_unlock; } smp_store_release(&ctx->psi.trigger, new); - cgroup_put(cgrp); + +out_unlock: + cgroup_kn_unlock(of->kn); + if (ret) + return ret; return nbytes; } @@ -5716,16 +5724,6 @@ static void offline_css(struct cgroup_subsys_state *css) RCU_INIT_POINTER(css->cgroup->subsys[ss->id], NULL); wake_up_all(&css->cgroup->offline_waitq); - - css->cgroup->nr_dying_subsys[ss->id]++; - /* - * Parent css and cgroup cannot be freed until after the freeing - * of child css, see css_free_rwork_fn(). - */ - while ((css = css->parent)) { - css->nr_descendants--; - css->cgroup->nr_dying_subsys[ss->id]++; - } } /** @@ -6038,6 +6036,8 @@ static void css_killed_ref_fn(struct percpu_ref *ref) */ static void kill_css(struct cgroup_subsys_state *css) { + struct cgroup_subsys *ss = css->ss; + lockdep_assert_held(&cgroup_mutex); if (css->flags & CSS_DYING) @@ -6074,6 +6074,16 @@ static void kill_css(struct cgroup_subsys_state *css) * css is confirmed to be seen as killed on all CPUs. */ percpu_ref_kill_and_confirm(&css->refcnt, css_killed_ref_fn); + + css->cgroup->nr_dying_subsys[ss->id]++; + /* + * Parent css and cgroup cannot be freed until after the freeing + * of child css, see css_free_rwork_fn(). + */ + while ((css = css->parent)) { + css->nr_descendants--; + css->cgroup->nr_dying_subsys[ss->id]++; + } } /** diff --git a/kernel/cgroup/cpuset-internal.h b/kernel/cgroup/cpuset-internal.h index fd7d19842ded..bb4e692bea30 100644 --- a/kernel/cgroup/cpuset-internal.h +++ b/kernel/cgroup/cpuset-internal.h @@ -168,6 +168,11 @@ struct cpuset { int nr_deadline_tasks; int nr_migrate_dl_tasks; u64 sum_migrate_dl_bw; + /* + * CPU used for temporary DL bandwidth allocation during attach; + * -1 if no DL bandwidth was allocated in the current attach. + */ + int dl_bw_cpu; /* Invalid partition error code, not lock protected */ enum prs_errcode prs_err; diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c index 1335e437098e..e3a081a07c6d 100644 --- a/kernel/cgroup/cpuset.c +++ b/kernel/cgroup/cpuset.c @@ -288,6 +288,7 @@ struct cpuset top_cpuset = { .flags = BIT(CS_CPU_EXCLUSIVE) | BIT(CS_MEM_EXCLUSIVE) | BIT(CS_SCHED_LOAD_BALANCE), .partition_root_state = PRS_ROOT, + .dl_bw_cpu = -1, }; /** @@ -579,6 +580,8 @@ static struct cpuset *dup_or_alloc_cpuset(struct cpuset *cs) if (!trial) return NULL; + trial->dl_bw_cpu = -1; + /* Setup cpumask pointer array */ cpumask_var_t *pmask[4] = { &trial->cpus_allowed, @@ -2980,6 +2983,7 @@ static void reset_migrate_dl_data(struct cpuset *cs) { cs->nr_migrate_dl_tasks = 0; cs->sum_migrate_dl_bw = 0; + cs->dl_bw_cpu = -1; } /* Called by cgroups to determine if a cpuset is usable; cpuset_mutex held */ @@ -3056,6 +3060,8 @@ static int cpuset_can_attach(struct cgroup_taskset *tset) reset_migrate_dl_data(cs); goto out_unlock; } + + cs->dl_bw_cpu = cpu; } out_success: @@ -3080,12 +3086,11 @@ static void cpuset_cancel_attach(struct cgroup_taskset *tset) mutex_lock(&cpuset_mutex); dec_attach_in_progress_locked(cs); - if (cs->nr_migrate_dl_tasks) { - int cpu = cpumask_any(cs->effective_cpus); + if (cs->dl_bw_cpu >= 0) + dl_bw_free(cs->dl_bw_cpu, cs->sum_migrate_dl_bw); - dl_bw_free(cpu, cs->sum_migrate_dl_bw); + if (cs->nr_migrate_dl_tasks) reset_migrate_dl_data(cs); - } mutex_unlock(&cpuset_mutex); } diff --git a/kernel/cgroup/rdma.c b/kernel/cgroup/rdma.c index 9967fb25c563..4fdab4cf49e0 100644 --- a/kernel/cgroup/rdma.c +++ b/kernel/cgroup/rdma.c @@ -283,7 +283,7 @@ int rdmacg_try_charge(struct rdma_cgroup **rdmacg, ret = PTR_ERR(rpool); goto err; } else { - new = rpool->resources[index].usage + 1; + new = (s64)rpool->resources[index].usage + 1; if (new > rpool->resources[index].max) { ret = -EAGAIN; goto err; diff --git a/kernel/fork.c b/kernel/fork.c index f1ad69c6dc2d..5f3fdfdb14c7 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -1951,9 +1951,11 @@ static void rv_task_fork(struct task_struct *p) static bool need_futex_hash_allocate_default(u64 clone_flags) { - if ((clone_flags & (CLONE_THREAD | CLONE_VM)) != (CLONE_THREAD | CLONE_VM)) - return false; - return true; + /* + * Allocate a default futex hash for any sibling that will + * share the parent's mm, except vfork. + */ + return (clone_flags & (CLONE_VM | CLONE_VFORK)) == CLONE_VM; } /* @@ -2380,10 +2382,6 @@ __latent_entropy struct task_struct *copy_process( if (retval) goto bad_fork_cancel_cgroup; - /* - * Allocate a default futex hash for the user process once the first - * thread spawns. - */ if (need_futex_hash_allocate_default(clone_flags)) { retval = futex_hash_allocate_default(); if (retval) diff --git a/kernel/futex/requeue.c b/kernel/futex/requeue.c index d818b4d47f1b..b597cb3d17fc 100644 --- a/kernel/futex/requeue.c +++ b/kernel/futex/requeue.c @@ -319,8 +319,11 @@ futex_proxy_trylock_atomic(u32 __user *pifutex, struct futex_hash_bucket *hb1, return -EINVAL; /* Ensure that this does not race against an early wakeup */ - if (!futex_requeue_pi_prepare(top_waiter, NULL)) + if (!futex_requeue_pi_prepare(top_waiter, NULL)) { + plist_del(&top_waiter->list, &hb1->chain); + futex_hb_waiters_dec(hb1); return -EAGAIN; + } /* * Try to take the lock for top_waiter and set the FUTEX_WAITERS bit @@ -722,10 +725,12 @@ int handle_early_requeue_pi_wakeup(struct futex_hash_bucket *hb, /* * We were woken prior to requeue by a timeout or a signal. - * Unqueue the futex_q and determine which it was. + * Conditionally unqueue the futex_q and determine which it was. */ - plist_del(&q->list, &hb->chain); - futex_hb_waiters_dec(hb); + if (!plist_node_empty(&q->list)) { + plist_del(&q->list, &hb->chain); + futex_hb_waiters_dec(hb); + } /* Handle spurious wakeups gracefully */ ret = -EWOULDBLOCK; diff --git a/kernel/liveupdate/kexec_handover.c b/kernel/liveupdate/kexec_handover.c index 94762de1fe5f..18509d8082ea 100644 --- a/kernel/liveupdate/kexec_handover.c +++ b/kernel/liveupdate/kexec_handover.c @@ -762,19 +762,24 @@ int kho_add_subtree(const char *name, void *blob, size_t size) goto out_pack; } - err = fdt_setprop(root_fdt, off, KHO_SUB_TREE_PROP_NAME, - &phys, sizeof(phys)); - if (err < 0) - goto out_pack; + fdt_err = fdt_setprop(root_fdt, off, KHO_SUB_TREE_PROP_NAME, + &phys, sizeof(phys)); + if (fdt_err < 0) + goto out_del_node; - err = fdt_setprop(root_fdt, off, KHO_SUB_TREE_SIZE_PROP_NAME, - &size_u64, sizeof(size_u64)); - if (err < 0) - goto out_pack; + fdt_err = fdt_setprop(root_fdt, off, KHO_SUB_TREE_SIZE_PROP_NAME, + &size_u64, sizeof(size_u64)); + if (fdt_err < 0) + goto out_del_node; WARN_ON_ONCE(kho_debugfs_blob_add(&kho_out.dbg, name, blob, size, false)); + err = 0; + goto out_pack; + +out_del_node: + fdt_del_node(root_fdt, off); out_pack: fdt_pack(root_fdt); diff --git a/kernel/liveupdate/luo_session.c b/kernel/liveupdate/luo_session.c index a3327a28fc1f..7a42385dabe2 100644 --- a/kernel/liveupdate/luo_session.c +++ b/kernel/liveupdate/luo_session.c @@ -514,11 +514,12 @@ int luo_session_deserialize(void) { struct luo_session_header *sh = &luo_session_global.incoming; static bool is_deserialized; - static int err; + static int saved_err; + int err; /* If has been deserialized, always return the same error code */ if (is_deserialized) - return err; + return saved_err; is_deserialized = true; if (!sh->active) @@ -547,7 +548,8 @@ int luo_session_deserialize(void) pr_warn("Failed to allocate session [%.*s] during deserialization %pe\n", (int)sizeof(sh->ser[i].name), sh->ser[i].name, session); - return PTR_ERR(session); + err = PTR_ERR(session); + goto save_err; } err = luo_session_insert(sh, session); @@ -555,7 +557,7 @@ int luo_session_deserialize(void) pr_warn("Failed to insert session [%s] %pe\n", session->name, ERR_PTR(err)); luo_session_free(session); - return err; + goto save_err; } scoped_guard(mutex, &session->mutex) { @@ -565,7 +567,7 @@ int luo_session_deserialize(void) if (err) { pr_warn("Failed to deserialize files for session [%s] %pe\n", session->name, ERR_PTR(err)); - return err; + goto save_err; } } @@ -574,6 +576,9 @@ int luo_session_deserialize(void) sh->ser = NULL; return 0; +save_err: + saved_err = err; + return err; } int luo_session_serialize(void) diff --git a/kernel/sched/core.c b/kernel/sched/core.c index da20fb6ea25a..b8871449d3c6 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -4458,6 +4458,7 @@ static void __sched_fork(u64 clone_flags, struct task_struct *p) p->se.nr_migrations = 0; p->se.vruntime = 0; p->se.vlag = 0; + p->se.rel_deadline = 0; INIT_LIST_HEAD(&p->se.group_node); /* A delayed task cannot be in clone(). */ diff --git a/kernel/sched/ext.c b/kernel/sched/ext.c index e426e27b6794..345aa11b84b2 100644 --- a/kernel/sched/ext.c +++ b/kernel/sched/ext.c @@ -32,6 +32,7 @@ static const struct rhashtable_params scx_sched_hash_params = { .key_len = sizeof_field(struct scx_sched, ops.sub_cgroup_id), .key_offset = offsetof(struct scx_sched, ops.sub_cgroup_id), .head_offset = offsetof(struct scx_sched, hash_node), + .insecure_elasticity = true, /* inserted under scx_sched_lock */ }; static struct rhashtable scx_sched_hash; @@ -52,8 +53,6 @@ DEFINE_STATIC_KEY_FALSE(__scx_enabled); DEFINE_STATIC_PERCPU_RWSEM(scx_fork_rwsem); static atomic_t scx_enable_state_var = ATOMIC_INIT(SCX_DISABLED); static DEFINE_RAW_SPINLOCK(scx_bypass_lock); -static cpumask_var_t scx_bypass_lb_donee_cpumask; -static cpumask_var_t scx_bypass_lb_resched_cpumask; static bool scx_init_task_enabled; static bool scx_switching_all; DEFINE_STATIC_KEY_FALSE(__scx_switched_all); @@ -469,24 +468,35 @@ static inline void update_locked_rq(struct rq *rq) __this_cpu_write(scx_locked_rq_state, rq); } -#define SCX_CALL_OP(sch, op, rq, args...) \ +/* + * SCX ops can recurse via scx_bpf_sub_dispatch() - the inner call must not + * clobber the outer's scx_locked_rq_state. Save it on entry, restore on exit. + */ +#define SCX_CALL_OP(sch, op, locked_rq, args...) \ do { \ - if (rq) \ - update_locked_rq(rq); \ + struct rq *__prev_locked_rq; \ + \ + if (locked_rq) { \ + __prev_locked_rq = scx_locked_rq(); \ + update_locked_rq(locked_rq); \ + } \ (sch)->ops.op(args); \ - if (rq) \ - update_locked_rq(NULL); \ + if (locked_rq) \ + update_locked_rq(__prev_locked_rq); \ } while (0) -#define SCX_CALL_OP_RET(sch, op, rq, args...) \ +#define SCX_CALL_OP_RET(sch, op, locked_rq, args...) \ ({ \ + struct rq *__prev_locked_rq; \ __typeof__((sch)->ops.op(args)) __ret; \ \ - if (rq) \ - update_locked_rq(rq); \ + if (locked_rq) { \ + __prev_locked_rq = scx_locked_rq(); \ + update_locked_rq(locked_rq); \ + } \ __ret = (sch)->ops.op(args); \ - if (rq) \ - update_locked_rq(NULL); \ + if (locked_rq) \ + update_locked_rq(__prev_locked_rq); \ __ret; \ }) @@ -498,39 +508,39 @@ do { \ * those subject tasks. * * Every SCX_CALL_OP_TASK*() call site invokes its op with @p's rq lock held - - * either via the @rq argument here, or (for ops.select_cpu()) via @p's pi_lock - * held by try_to_wake_up() with rq tracking via scx_rq.in_select_cpu. So if - * kf_tasks[] is set, @p's scheduler-protected fields are stable. + * either via the @locked_rq argument here, or (for ops.select_cpu()) via @p's + * pi_lock held by try_to_wake_up() with rq tracking via scx_rq.in_select_cpu. + * So if kf_tasks[] is set, @p's scheduler-protected fields are stable. * * kf_tasks[] can not stack, so task-based SCX ops must not nest. The * WARN_ON_ONCE() in each macro catches a re-entry of any of the three variants * while a previous one is still in progress. */ -#define SCX_CALL_OP_TASK(sch, op, rq, task, args...) \ +#define SCX_CALL_OP_TASK(sch, op, locked_rq, task, args...) \ do { \ WARN_ON_ONCE(current->scx.kf_tasks[0]); \ current->scx.kf_tasks[0] = task; \ - SCX_CALL_OP((sch), op, rq, task, ##args); \ + SCX_CALL_OP((sch), op, locked_rq, task, ##args); \ current->scx.kf_tasks[0] = NULL; \ } while (0) -#define SCX_CALL_OP_TASK_RET(sch, op, rq, task, args...) \ +#define SCX_CALL_OP_TASK_RET(sch, op, locked_rq, task, args...) \ ({ \ __typeof__((sch)->ops.op(task, ##args)) __ret; \ WARN_ON_ONCE(current->scx.kf_tasks[0]); \ current->scx.kf_tasks[0] = task; \ - __ret = SCX_CALL_OP_RET((sch), op, rq, task, ##args); \ + __ret = SCX_CALL_OP_RET((sch), op, locked_rq, task, ##args); \ current->scx.kf_tasks[0] = NULL; \ __ret; \ }) -#define SCX_CALL_OP_2TASKS_RET(sch, op, rq, task0, task1, args...) \ +#define SCX_CALL_OP_2TASKS_RET(sch, op, locked_rq, task0, task1, args...) \ ({ \ __typeof__((sch)->ops.op(task0, task1, ##args)) __ret; \ WARN_ON_ONCE(current->scx.kf_tasks[0]); \ current->scx.kf_tasks[0] = task0; \ current->scx.kf_tasks[1] = task1; \ - __ret = SCX_CALL_OP_RET((sch), op, rq, task0, task1, ##args); \ + __ret = SCX_CALL_OP_RET((sch), op, locked_rq, task0, task1, ##args); \ current->scx.kf_tasks[0] = NULL; \ current->scx.kf_tasks[1] = NULL; \ __ret; \ @@ -1388,18 +1398,55 @@ static void call_task_dequeue(struct scx_sched *sch, struct rq *rq, p->scx.flags &= ~SCX_TASK_IN_CUSTODY; } -static void local_dsq_post_enq(struct scx_dispatch_q *dsq, struct task_struct *p, - u64 enq_flags) +static void local_dsq_post_enq(struct scx_sched *sch, struct scx_dispatch_q *dsq, + struct task_struct *p, u64 enq_flags) { struct rq *rq = container_of(dsq, struct rq, scx.local_dsq); - bool preempt = false; - call_task_dequeue(scx_root, rq, p, 0); + call_task_dequeue(sch, rq, p, 0); + + /* + * Note that @rq's lock may be dropped between this enqueue and @p + * actually getting on CPU. This gives higher-class tasks (e.g. RT) + * an opportunity to wake up on @rq and prevent @p from running. + * Here are some concrete examples: + * + * Example 1: + * + * We dispatch two tasks from a single ops.dispatch(): + * - First, a local task to this CPU's local DSQ; + * - Second, a local/remote task to a remote CPU's local DSQ. + * We must drop the local rq lock in order to finish the second + * dispatch. In that time, an RT task can wake up on the local rq. + * + * Example 2: + * + * We dispatch a local/remote task to a remote CPU's local DSQ. + * We must drop the remote rq lock before the dispatched task can run, + * which gives an RT task an opportunity to wake up on the remote rq. + * + * Both examples work the same if we replace dispatching with moving + * the tasks from a user-created DSQ. + * + * We must detect these wakeups so that we can re-enqueue IMMED tasks + * from @rq's local DSQ. scx_wakeup_preempt() serves exactly this + * purpose, but for it to be invoked, we must ensure that we bump + * @rq->next_class to &ext_sched_class if it's currently idle. + * + * wakeup_preempt() does the bumping, and since we only invoke it if + * @rq->next_class is below &ext_sched_class, it will also + * resched_curr(rq). + */ + if (sched_class_above(p->sched_class, rq->next_class)) + wakeup_preempt(rq, p, 0); /* * If @rq is in balance, the CPU is already vacant and looking for the * next task to run. No need to preempt or trigger resched after moving * @p into its local DSQ. + * Note that the wakeup_preempt() above may have already triggered + * a resched if @rq->next_class was idle. It's harmless, since + * need_resched is cleared immediately after task pick. */ if (rq->scx.flags & SCX_RQ_IN_BALANCE) return; @@ -1407,11 +1454,8 @@ static void local_dsq_post_enq(struct scx_dispatch_q *dsq, struct task_struct *p if ((enq_flags & SCX_ENQ_PREEMPT) && p != rq->curr && rq->curr->sched_class == &ext_sched_class) { rq->curr->scx.slice = 0; - preempt = true; - } - - if (preempt || sched_class_above(&ext_sched_class, rq->curr->sched_class)) resched_curr(rq); + } } static void dispatch_enqueue(struct scx_sched *sch, struct rq *rq, @@ -1494,11 +1538,13 @@ static void dispatch_enqueue(struct scx_sched *sch, struct rq *rq, if (!(dsq->id & SCX_DSQ_FLAG_BUILTIN)) rcu_assign_pointer(dsq->first_task, p); } else { - bool was_empty; - - was_empty = list_empty(&dsq->list); + /* + * dsq->list can contain parked BPF iterator cursors, so + * list_empty() here isn't a reliable proxy for "no real + * task in the DSQ". Test dsq->first_task directly. + */ list_add_tail(&p->scx.dsq_list.node, &dsq->list); - if (was_empty && !(dsq->id & SCX_DSQ_FLAG_BUILTIN)) + if (!dsq->first_task && !(dsq->id & SCX_DSQ_FLAG_BUILTIN)) rcu_assign_pointer(dsq->first_task, p); } } @@ -1518,7 +1564,7 @@ static void dispatch_enqueue(struct scx_sched *sch, struct rq *rq, * concurrently in a non-atomic way. */ if (is_local) { - local_dsq_post_enq(dsq, p, enq_flags); + local_dsq_post_enq(sch, dsq, p, enq_flags); } else { /* * Task on global/bypass DSQ: leave custody, task on @@ -2129,7 +2175,8 @@ static void wakeup_preempt_scx(struct rq *rq, struct task_struct *p, int wake_fl schedule_reenq_local(rq, 0); } -static void move_local_task_to_local_dsq(struct task_struct *p, u64 enq_flags, +static void move_local_task_to_local_dsq(struct scx_sched *sch, + struct task_struct *p, u64 enq_flags, struct scx_dispatch_q *src_dsq, struct rq *dst_rq) { @@ -2149,7 +2196,7 @@ static void move_local_task_to_local_dsq(struct task_struct *p, u64 enq_flags, dsq_inc_nr(dst_dsq, p, enq_flags); p->scx.dsq = dst_dsq; - local_dsq_post_enq(dst_dsq, p, enq_flags); + local_dsq_post_enq(sch, dst_dsq, p, enq_flags); } /** @@ -2370,7 +2417,7 @@ static struct rq *move_task_between_dsqs(struct scx_sched *sch, /* @p is going from a non-local DSQ to a local DSQ */ if (src_rq == dst_rq) { task_unlink_from_dsq(p, src_dsq); - move_local_task_to_local_dsq(p, enq_flags, + move_local_task_to_local_dsq(sch, p, enq_flags, src_dsq, dst_rq); raw_spin_unlock(&src_dsq->lock); } else { @@ -2423,7 +2470,7 @@ static bool consume_dispatch_q(struct scx_sched *sch, struct rq *rq, if (rq == task_rq) { task_unlink_from_dsq(p, dsq); - move_local_task_to_local_dsq(p, enq_flags, dsq, rq); + move_local_task_to_local_dsq(sch, p, enq_flags, dsq, rq); raw_spin_unlock(&dsq->lock); return true; } @@ -3183,7 +3230,7 @@ bool scx_prio_less(const struct task_struct *a, const struct task_struct *b, if (sch_a == sch_b && SCX_HAS_OP(sch_a, core_sched_before) && !scx_bypassing(sch_a, task_cpu(a))) return SCX_CALL_OP_2TASKS_RET(sch_a, core_sched_before, - NULL, + task_rq(a), (struct task_struct *)a, (struct task_struct *)b); else @@ -3631,6 +3678,22 @@ static void __scx_disable_and_exit_task(struct scx_sched *sch, SCX_CALL_OP_TASK(sch, exit_task, task_rq(p), p, &args); } +/* + * Undo a completed __scx_init_task(sch, p, false) when scx_enable_task() never + * ran. The task state has not been transitioned, so this mirrors the + * SCX_TASK_INIT branch in __scx_disable_and_exit_task(). + */ +static void scx_sub_init_cancel_task(struct scx_sched *sch, struct task_struct *p) +{ + struct scx_exit_task_args args = { .cancelled = true }; + + lockdep_assert_held(&p->pi_lock); + lockdep_assert_rq_held(task_rq(p)); + + if (SCX_HAS_OP(sch, exit_task)) + SCX_CALL_OP_TASK(sch, exit_task, task_rq(p), p, &args); +} + static void scx_disable_and_exit_task(struct scx_sched *sch, struct task_struct *p) { @@ -3639,11 +3702,12 @@ static void scx_disable_and_exit_task(struct scx_sched *sch, /* * If set, @p exited between __scx_init_task() and scx_enable_task() in * scx_sub_enable() and is initialized for both the associated sched and - * its parent. Disable and exit for the child too. + * its parent. Exit for the child too - scx_enable_task() never ran for + * it, so undo only init_task. */ - if ((p->scx.flags & SCX_TASK_SUB_INIT) && - !WARN_ON_ONCE(!scx_enabling_sub_sched)) { - __scx_disable_and_exit_task(scx_enabling_sub_sched, p); + if (p->scx.flags & SCX_TASK_SUB_INIT) { + if (!WARN_ON_ONCE(!scx_enabling_sub_sched)) + scx_sub_init_cancel_task(scx_enabling_sub_sched, p); p->scx.flags &= ~SCX_TASK_SUB_INIT; } @@ -4324,9 +4388,10 @@ void scx_cgroup_cancel_attach(struct cgroup_taskset *tset) void scx_group_set_weight(struct task_group *tg, unsigned long weight) { - struct scx_sched *sch = scx_root; + struct scx_sched *sch; percpu_down_read(&scx_cgroup_ops_rwsem); + sch = scx_root; if (scx_cgroup_enabled && SCX_HAS_OP(sch, cgroup_set_weight) && tg->scx.weight != weight) @@ -4339,9 +4404,10 @@ void scx_group_set_weight(struct task_group *tg, unsigned long weight) void scx_group_set_idle(struct task_group *tg, bool idle) { - struct scx_sched *sch = scx_root; + struct scx_sched *sch; percpu_down_read(&scx_cgroup_ops_rwsem); + sch = scx_root; if (scx_cgroup_enabled && SCX_HAS_OP(sch, cgroup_set_idle)) SCX_CALL_OP(sch, cgroup_set_idle, NULL, tg_cgrp(tg), idle); @@ -4355,9 +4421,10 @@ void scx_group_set_idle(struct task_group *tg, bool idle) void scx_group_set_bandwidth(struct task_group *tg, u64 period_us, u64 quota_us, u64 burst_us) { - struct scx_sched *sch = scx_root; + struct scx_sched *sch; percpu_down_read(&scx_cgroup_ops_rwsem); + sch = scx_root; if (scx_cgroup_enabled && SCX_HAS_OP(sch, cgroup_set_bandwidth) && (tg->scx.bw_period_us != period_us || @@ -4380,21 +4447,6 @@ static struct cgroup *root_cgroup(void) return &cgrp_dfl_root.cgrp; } -static struct cgroup *sch_cgroup(struct scx_sched *sch) -{ - return sch->cgrp; -} - -/* for each descendant of @cgrp including self, set ->scx_sched to @sch */ -static void set_cgroup_sched(struct cgroup *cgrp, struct scx_sched *sch) -{ - struct cgroup *pos; - struct cgroup_subsys_state *css; - - cgroup_for_each_live_descendant_pre(pos, css, cgrp) - rcu_assign_pointer(pos->scx_sched, sch); -} - static void scx_cgroup_lock(void) { #ifdef CONFIG_EXT_GROUP_SCHED @@ -4412,12 +4464,30 @@ static void scx_cgroup_unlock(void) } #else /* CONFIG_EXT_GROUP_SCHED || CONFIG_EXT_SUB_SCHED */ static struct cgroup *root_cgroup(void) { return NULL; } -static struct cgroup *sch_cgroup(struct scx_sched *sch) { return NULL; } -static void set_cgroup_sched(struct cgroup *cgrp, struct scx_sched *sch) {} static void scx_cgroup_lock(void) {} static void scx_cgroup_unlock(void) {} #endif /* CONFIG_EXT_GROUP_SCHED || CONFIG_EXT_SUB_SCHED */ +#ifdef CONFIG_EXT_SUB_SCHED +static struct cgroup *sch_cgroup(struct scx_sched *sch) +{ + return sch->cgrp; +} + +/* for each descendant of @cgrp including self, set ->scx_sched to @sch */ +static void set_cgroup_sched(struct cgroup *cgrp, struct scx_sched *sch) +{ + struct cgroup *pos; + struct cgroup_subsys_state *css; + + cgroup_for_each_live_descendant_pre(pos, css, cgrp) + rcu_assign_pointer(pos->scx_sched, sch); +} +#else /* CONFIG_EXT_SUB_SCHED */ +static struct cgroup *sch_cgroup(struct scx_sched *sch) { return NULL; } +static void set_cgroup_sched(struct cgroup *cgrp, struct scx_sched *sch) {} +#endif /* CONFIG_EXT_SUB_SCHED */ + /* * Omitted operations: * @@ -4712,6 +4782,8 @@ static void scx_sched_free_rcu_work(struct work_struct *work) irq_work_sync(&sch->disable_irq_work); kthread_destroy_worker(sch->helper); timer_shutdown_sync(&sch->bypass_lb_timer); + free_cpumask_var(sch->bypass_lb_donee_cpumask); + free_cpumask_var(sch->bypass_lb_resched_cpumask); #ifdef CONFIG_EXT_SUB_SCHED kfree(sch->cgrp_path); @@ -4938,6 +5010,25 @@ void scx_softlockup(u32 dur_s) smp_processor_id(), dur_s); } +/* + * scx_hardlockup() runs from NMI and eventually calls scx_claim_exit(), + * which takes scx_sched_lock. scx_sched_lock isn't NMI-safe and grabbing + * it from NMI context can lead to deadlocks. Defer via irq_work; the + * disable path runs off irq_work anyway. + */ +static atomic_t scx_hardlockup_cpu = ATOMIC_INIT(-1); + +static void scx_hardlockup_irq_workfn(struct irq_work *work) +{ + int cpu = atomic_xchg(&scx_hardlockup_cpu, -1); + + if (cpu >= 0 && handle_lockup("hard lockup - CPU %d", cpu)) + printk_deferred(KERN_ERR "sched_ext: Hard lockup - CPU %d, disabling BPF scheduler\n", + cpu); +} + +static DEFINE_IRQ_WORK(scx_hardlockup_irq_work, scx_hardlockup_irq_workfn); + /** * scx_hardlockup - sched_ext hardlockup handler * @@ -4946,17 +5037,19 @@ void scx_softlockup(u32 dur_s) * Try kicking out the current scheduler in an attempt to recover the system to * a good state before taking more drastic actions. * - * Returns %true if sched_ext is enabled and abort was initiated, which may - * resolve the reported hardlockup. %false if sched_ext is not enabled or - * someone else already initiated abort. + * Queues an irq_work; the handle_lockup() call happens in IRQ context (see + * scx_hardlockup_irq_workfn). + * + * Returns %true if sched_ext is enabled and the work was queued, %false + * otherwise. */ bool scx_hardlockup(int cpu) { - if (!handle_lockup("hard lockup - CPU %d", cpu)) + if (!rcu_access_pointer(scx_root)) return false; - printk_deferred(KERN_ERR "sched_ext: Hard lockup - CPU %d, disabling BPF scheduler\n", - cpu); + atomic_cmpxchg(&scx_hardlockup_cpu, -1, cpu); + irq_work_queue(&scx_hardlockup_irq_work); return true; } @@ -5000,6 +5093,15 @@ static u32 bypass_lb_cpu(struct scx_sched *sch, s32 donor, if (cpumask_empty(donee_mask)) break; + /* + * If an earlier pass placed @p on @donor_dsq from a different + * CPU and the donee hasn't consumed it yet, @p is still on the + * previous CPU and task_rq(@p) != @donor_rq. @p can't be moved + * without its rq locked. Skip. + */ + if (task_rq(p) != donor_rq) + continue; + donee = cpumask_any_and_distribute(donee_mask, p->cpus_ptr); if (donee >= nr_cpu_ids) continue; @@ -5058,8 +5160,8 @@ static u32 bypass_lb_cpu(struct scx_sched *sch, s32 donor, static void bypass_lb_node(struct scx_sched *sch, int node) { const struct cpumask *node_mask = cpumask_of_node(node); - struct cpumask *donee_mask = scx_bypass_lb_donee_cpumask; - struct cpumask *resched_mask = scx_bypass_lb_resched_cpumask; + struct cpumask *donee_mask = sch->bypass_lb_donee_cpumask; + struct cpumask *resched_mask = sch->bypass_lb_resched_cpumask; u32 nr_tasks = 0, nr_cpus = 0, nr_balanced = 0; u32 nr_target, nr_donor_target; u32 before_min = U32_MAX, before_max = 0; @@ -5698,6 +5800,8 @@ static void scx_sub_disable(struct scx_sched *sch) if (sch->ops.exit) SCX_CALL_OP(sch, exit, NULL, sch->exit_info); + if (sch->sub_kset) + kset_unregister(sch->sub_kset); kobject_del(&sch->kobj); } #else /* CONFIG_EXT_SUB_SCHED */ @@ -5829,6 +5933,10 @@ static void scx_root_disable(struct scx_sched *sch) * could observe an object of the same name still in the hierarchy when * the next scheduler is loaded. */ +#ifdef CONFIG_EXT_SUB_SCHED + if (sch->sub_kset) + kset_unregister(sch->sub_kset); +#endif kobject_del(&sch->kobj); free_kick_syncs(); @@ -5921,6 +6029,25 @@ static void scx_disable(struct scx_sched *sch, enum scx_exit_kind kind) irq_work_queue(&sch->disable_irq_work); } +/** + * scx_flush_disable_work - flush the disable work and wait for it to finish + * @sch: the scheduler + * + * sch->disable_work might still not queued, causing kthread_flush_work() + * as a noop. Syncing the irq_work first is required to guarantee the + * kthread work has been queued before waiting for it. + */ +static void scx_flush_disable_work(struct scx_sched *sch) +{ + int kind; + + do { + irq_work_sync(&sch->disable_irq_work); + kthread_flush_work(&sch->disable_work); + kind = atomic_read(&sch->exit_kind); + } while (kind != SCX_EXIT_NONE && kind != SCX_EXIT_DONE); +} + static void dump_newline(struct seq_buf *s) { trace_sched_ext_dump(""); @@ -6032,9 +6159,8 @@ static void ops_dump_exit(void) scx_dump_data.cpu = -1; } -static void scx_dump_task(struct scx_sched *sch, - struct seq_buf *s, struct scx_dump_ctx *dctx, - struct task_struct *p, char marker) +static void scx_dump_task(struct scx_sched *sch, struct seq_buf *s, struct scx_dump_ctx *dctx, + struct rq *rq, struct task_struct *p, char marker) { static unsigned long bt[SCX_EXIT_BT_LEN]; struct scx_sched *task_sch = scx_task_sched(p); @@ -6075,7 +6201,7 @@ static void scx_dump_task(struct scx_sched *sch, if (SCX_HAS_OP(sch, dump_task)) { ops_dump_init(s, " "); - SCX_CALL_OP(sch, dump_task, NULL, dctx, p); + SCX_CALL_OP(sch, dump_task, rq, dctx, p); ops_dump_exit(); } @@ -6199,8 +6325,7 @@ static void scx_dump_state(struct scx_sched *sch, struct scx_exit_info *ei, used = seq_buf_used(&ns); if (SCX_HAS_OP(sch, dump_cpu)) { ops_dump_init(&ns, " "); - SCX_CALL_OP(sch, dump_cpu, NULL, - &dctx, cpu, idle); + SCX_CALL_OP(sch, dump_cpu, rq, &dctx, cpu, idle); ops_dump_exit(); } @@ -6223,11 +6348,11 @@ static void scx_dump_state(struct scx_sched *sch, struct scx_exit_info *ei, if (rq->curr->sched_class == &ext_sched_class && (dump_all_tasks || scx_task_on_sched(sch, rq->curr))) - scx_dump_task(sch, &s, &dctx, rq->curr, '*'); + scx_dump_task(sch, &s, &dctx, rq, rq->curr, '*'); list_for_each_entry(p, &rq->scx.runnable_list, scx.runnable_node) if (dump_all_tasks || scx_task_on_sched(sch, p)) - scx_dump_task(sch, &s, &dctx, p, ' '); + scx_dump_task(sch, &s, &dctx, rq, p, ' '); next: rq_unlock_irqrestore(rq, &rf); } @@ -6437,6 +6562,15 @@ static struct scx_sched *scx_alloc_and_add_sched(struct sched_ext_ops *ops, init_irq_work(&sch->disable_irq_work, scx_disable_irq_workfn); kthread_init_work(&sch->disable_work, scx_disable_workfn); timer_setup(&sch->bypass_lb_timer, scx_bypass_lb_timerfn, 0); + + if (!alloc_cpumask_var(&sch->bypass_lb_donee_cpumask, GFP_KERNEL)) { + ret = -ENOMEM; + goto err_stop_helper; + } + if (!alloc_cpumask_var(&sch->bypass_lb_resched_cpumask, GFP_KERNEL)) { + ret = -ENOMEM; + goto err_free_lb_cpumask; + } sch->ops = *ops; rcu_assign_pointer(ops->priv, sch); @@ -6446,14 +6580,14 @@ static struct scx_sched *scx_alloc_and_add_sched(struct sched_ext_ops *ops, char *buf = kzalloc(PATH_MAX, GFP_KERNEL); if (!buf) { ret = -ENOMEM; - goto err_stop_helper; + goto err_free_lb_resched; } cgroup_path(cgrp, buf, PATH_MAX); sch->cgrp_path = kstrdup(buf, GFP_KERNEL); kfree(buf); if (!sch->cgrp_path) { ret = -ENOMEM; - goto err_stop_helper; + goto err_free_lb_resched; } sch->cgrp = cgrp; @@ -6488,10 +6622,12 @@ static struct scx_sched *scx_alloc_and_add_sched(struct sched_ext_ops *ops, #endif /* CONFIG_EXT_SUB_SCHED */ return sch; -#ifdef CONFIG_EXT_SUB_SCHED +err_free_lb_resched: + free_cpumask_var(sch->bypass_lb_resched_cpumask); +err_free_lb_cpumask: + free_cpumask_var(sch->bypass_lb_donee_cpumask); err_stop_helper: kthread_destroy_worker(sch->helper); -#endif err_free_pcpu: for_each_possible_cpu(cpu) { if (cpu == bypass_fail_cpu) @@ -6510,7 +6646,7 @@ static struct scx_sched *scx_alloc_and_add_sched(struct sched_ext_ops *ops, err_free_sch: kfree(sch); err_put_cgrp: -#if defined(CONFIG_EXT_GROUP_SCHED) || defined(CONFIG_EXT_SUB_SCHED) +#ifdef CONFIG_EXT_SUB_SCHED cgroup_put(cgrp); #endif return ERR_PTR(ret); @@ -6601,7 +6737,7 @@ static void scx_root_enable_workfn(struct kthread_work *work) if (ret) goto err_unlock; -#if defined(CONFIG_EXT_GROUP_SCHED) || defined(CONFIG_EXT_SUB_SCHED) +#ifdef CONFIG_EXT_SUB_SCHED cgroup_get(cgrp); #endif sch = scx_alloc_and_add_sched(ops, cgrp, NULL); @@ -6639,8 +6775,10 @@ static void scx_root_enable_workfn(struct kthread_work *work) rcu_assign_pointer(scx_root, sch); ret = scx_link_sched(sch); - if (ret) + if (ret) { + cpus_read_unlock(); goto err_disable; + } scx_idle_enable(ops); @@ -6821,7 +6959,7 @@ static void scx_root_enable_workfn(struct kthread_work *work) * completion. sch's base reference will be put by bpf_scx_unreg(). */ scx_error(sch, "scx_root_enable() failed (%d)", ret); - kthread_flush_work(&sch->disable_work); + scx_flush_disable_work(sch); cmd->ret = 0; } @@ -7072,23 +7210,30 @@ static void scx_sub_enable_workfn(struct kthread_work *work) abort: put_task_struct(p); scx_task_iter_stop(&sti); - scx_enabling_sub_sched = NULL; + /* + * Undo __scx_init_task() for tasks we marked. scx_enable_task() never + * ran for @sch on them, so calling scx_disable_task() here would invoke + * ops.disable() without a matching ops.enable(). scx_enabling_sub_sched + * must stay set until SUB_INIT is cleared from every marked task - + * scx_disable_and_exit_task() reads it when a task exits concurrently. + */ scx_task_iter_start(&sti, sch->cgrp); while ((p = scx_task_iter_next_locked(&sti))) { if (p->scx.flags & SCX_TASK_SUB_INIT) { - __scx_disable_and_exit_task(sch, p); + scx_sub_init_cancel_task(sch, p); p->scx.flags &= ~SCX_TASK_SUB_INIT; } } scx_task_iter_stop(&sti); + scx_enabling_sub_sched = NULL; err_unlock_and_disable: /* we'll soon enter disable path, keep bypass on */ scx_cgroup_unlock(); percpu_up_write(&scx_fork_rwsem); err_disable: mutex_unlock(&scx_enable_mutex); - kthread_flush_work(&sch->disable_work); + scx_flush_disable_work(sch); cmd->ret = 0; } @@ -7349,7 +7494,7 @@ static void bpf_scx_unreg(void *kdata, struct bpf_link *link) struct scx_sched *sch = rcu_dereference_protected(ops->priv, true); scx_disable(sch, SCX_EXIT_UNREG); - kthread_flush_work(&sch->disable_work); + scx_flush_disable_work(sch); RCU_INIT_POINTER(ops->priv, NULL); kobject_put(&sch->kobj); } @@ -8033,12 +8178,22 @@ static bool scx_dsq_move(struct bpf_iter_scx_dsq_kern *kit, struct task_struct *p, u64 dsq_id, u64 enq_flags) { struct scx_dispatch_q *src_dsq = kit->dsq, *dst_dsq; - struct scx_sched *sch = src_dsq->sched; + struct scx_sched *sch; struct rq *this_rq, *src_rq, *locked_rq; bool dispatched = false; bool in_balance; unsigned long flags; + /* + * The verifier considers an iterator slot initialized on any + * KF_ITER_NEW return, so a BPF program may legally reach here after + * bpf_iter_scx_dsq_new() failed and left @kit->dsq NULL. + */ + if (unlikely(!src_dsq)) + return false; + + sch = src_dsq->sched; + if (!scx_vet_enq_flags(sch, dsq_id, &enq_flags)) return false; @@ -8526,7 +8681,7 @@ __bpf_kfunc bool scx_bpf_task_set_slice(struct task_struct *p, u64 slice, guard(rcu)(); sch = scx_prog_sched(aux); - if (unlikely(!scx_task_on_sched(sch, p))) + if (unlikely(!sch || !scx_task_on_sched(sch, p))) return false; p->scx.slice = slice; @@ -8549,7 +8704,7 @@ __bpf_kfunc bool scx_bpf_task_set_dsq_vtime(struct task_struct *p, u64 vtime, guard(rcu)(); sch = scx_prog_sched(aux); - if (unlikely(!scx_task_on_sched(sch, p))) + if (unlikely(!sch || !scx_task_on_sched(sch, p))) return false; p->scx.dsq_vtime = vtime; @@ -8633,11 +8788,12 @@ __bpf_kfunc void scx_bpf_kick_cpu(s32 cpu, u64 flags, const struct bpf_prog_aux /** * scx_bpf_dsq_nr_queued - Return the number of queued tasks * @dsq_id: id of the DSQ + * @aux: implicit BPF argument to access bpf_prog_aux hidden from BPF progs * * Return the number of tasks in the DSQ matching @dsq_id. If not found, * -%ENOENT is returned. */ -__bpf_kfunc s32 scx_bpf_dsq_nr_queued(u64 dsq_id) +__bpf_kfunc s32 scx_bpf_dsq_nr_queued(u64 dsq_id, const struct bpf_prog_aux *aux) { struct scx_sched *sch; struct scx_dispatch_q *dsq; @@ -8645,7 +8801,7 @@ __bpf_kfunc s32 scx_bpf_dsq_nr_queued(u64 dsq_id) preempt_disable(); - sch = rcu_dereference_sched(scx_root); + sch = scx_prog_sched(aux); if (unlikely(!sch)) { ret = -ENODEV; goto out; @@ -8677,21 +8833,21 @@ __bpf_kfunc s32 scx_bpf_dsq_nr_queued(u64 dsq_id) /** * scx_bpf_destroy_dsq - Destroy a custom DSQ * @dsq_id: DSQ to destroy + * @aux: implicit BPF argument to access bpf_prog_aux hidden from BPF progs * * Destroy the custom DSQ identified by @dsq_id. Only DSQs created with * scx_bpf_create_dsq() can be destroyed. The caller must ensure that the DSQ is * empty and no further tasks are dispatched to it. Ignored if called on a DSQ * which doesn't exist. Can be called from any online scx_ops operations. */ -__bpf_kfunc void scx_bpf_destroy_dsq(u64 dsq_id) +__bpf_kfunc void scx_bpf_destroy_dsq(u64 dsq_id, const struct bpf_prog_aux *aux) { struct scx_sched *sch; - rcu_read_lock(); - sch = rcu_dereference(scx_root); + guard(rcu)(); + sch = scx_prog_sched(aux); if (sch) destroy_dsq(sch, dsq_id); - rcu_read_unlock(); } /** @@ -9445,8 +9601,8 @@ BTF_KFUNCS_START(scx_kfunc_ids_any) BTF_ID_FLAGS(func, scx_bpf_task_set_slice, KF_IMPLICIT_ARGS | KF_RCU); BTF_ID_FLAGS(func, scx_bpf_task_set_dsq_vtime, KF_IMPLICIT_ARGS | KF_RCU); BTF_ID_FLAGS(func, scx_bpf_kick_cpu, KF_IMPLICIT_ARGS) -BTF_ID_FLAGS(func, scx_bpf_dsq_nr_queued) -BTF_ID_FLAGS(func, scx_bpf_destroy_dsq) +BTF_ID_FLAGS(func, scx_bpf_dsq_nr_queued, KF_IMPLICIT_ARGS) +BTF_ID_FLAGS(func, scx_bpf_destroy_dsq, KF_IMPLICIT_ARGS) BTF_ID_FLAGS(func, scx_bpf_dsq_peek, KF_IMPLICIT_ARGS | KF_RCU_PROTECTED | KF_RET_NULL) BTF_ID_FLAGS(func, scx_bpf_dsq_reenq, KF_IMPLICIT_ARGS) BTF_ID_FLAGS(func, scx_bpf_reenqueue_local___v2, KF_IMPLICIT_ARGS) @@ -9479,6 +9635,7 @@ BTF_KFUNCS_END(scx_kfunc_ids_any) static const struct btf_kfunc_id_set scx_kfunc_set_any = { .owner = THIS_MODULE, .set = &scx_kfunc_ids_any, + .filter = scx_kfunc_context_filter, }; /* @@ -9526,13 +9683,12 @@ static const u32 scx_kf_allow_flags[] = { }; /* - * Verifier-time filter for context-sensitive SCX kfuncs. Registered via the - * .filter field on each per-group btf_kfunc_id_set. The BPF core invokes this - * for every kfunc call in the registered hook (BPF_PROG_TYPE_STRUCT_OPS or + * Verifier-time filter for SCX kfuncs. Registered via the .filter field on + * each per-group btf_kfunc_id_set. The BPF core invokes this for every kfunc + * call in the registered hook (BPF_PROG_TYPE_STRUCT_OPS or * BPF_PROG_TYPE_SYSCALL), regardless of which set originally introduced the - * kfunc - so the filter must short-circuit on kfuncs it doesn't govern (e.g. - * scx_kfunc_ids_any) by falling through to "allow" when none of the - * context-sensitive sets contain the kfunc. + * kfunc - so the filter must short-circuit on kfuncs it doesn't govern by + * falling through to "allow" when none of the SCX sets contain the kfunc. */ int scx_kfunc_context_filter(const struct bpf_prog *prog, u32 kfunc_id) { @@ -9541,18 +9697,21 @@ int scx_kfunc_context_filter(const struct bpf_prog *prog, u32 kfunc_id) bool in_enqueue = btf_id_set8_contains(&scx_kfunc_ids_enqueue_dispatch, kfunc_id); bool in_dispatch = btf_id_set8_contains(&scx_kfunc_ids_dispatch, kfunc_id); bool in_cpu_release = btf_id_set8_contains(&scx_kfunc_ids_cpu_release, kfunc_id); + bool in_idle = btf_id_set8_contains(&scx_kfunc_ids_idle, kfunc_id); + bool in_any = btf_id_set8_contains(&scx_kfunc_ids_any, kfunc_id); u32 moff, flags; - /* Not a context-sensitive kfunc (e.g. from scx_kfunc_ids_any) - allow. */ - if (!(in_unlocked || in_select_cpu || in_enqueue || in_dispatch || in_cpu_release)) + /* Not an SCX kfunc - allow. */ + if (!(in_unlocked || in_select_cpu || in_enqueue || in_dispatch || + in_cpu_release || in_idle || in_any)) return 0; /* SYSCALL progs (e.g. BPF test_run()) may call unlocked and select_cpu kfuncs. */ if (prog->type == BPF_PROG_TYPE_SYSCALL) - return (in_unlocked || in_select_cpu) ? 0 : -EACCES; + return (in_unlocked || in_select_cpu || in_idle || in_any) ? 0 : -EACCES; if (prog->type != BPF_PROG_TYPE_STRUCT_OPS) - return -EACCES; + return (in_any || in_idle) ? 0 : -EACCES; /* * add_subprog_and_kfunc() collects all kfunc calls, including dead code @@ -9565,14 +9724,15 @@ int scx_kfunc_context_filter(const struct bpf_prog *prog, u32 kfunc_id) return 0; /* - * Non-SCX struct_ops: only unlocked kfuncs are safe. The other - * context-sensitive kfuncs assume the rq lock is held by the SCX - * dispatch path, which doesn't apply to other struct_ops users. + * Non-SCX struct_ops: SCX kfuncs are not permitted. */ if (prog->aux->st_ops != &bpf_sched_ext_ops) - return in_unlocked ? 0 : -EACCES; + return -EACCES; /* SCX struct_ops: check the per-op allow list. */ + if (in_any || in_idle) + return 0; + moff = prog->aux->attach_st_ops_member_off; flags = scx_kf_allow_flags[SCX_MOFF_IDX(moff)]; @@ -9656,12 +9816,6 @@ static int __init scx_init(void) return ret; } - if (!alloc_cpumask_var(&scx_bypass_lb_donee_cpumask, GFP_KERNEL) || - !alloc_cpumask_var(&scx_bypass_lb_resched_cpumask, GFP_KERNEL)) { - pr_err("sched_ext: Failed to allocate cpumasks\n"); - return -ENOMEM; - } - return 0; } __initcall(scx_init); diff --git a/kernel/sched/ext_idle.c b/kernel/sched/ext_idle.c index 443d12a3df67..7468560a6d80 100644 --- a/kernel/sched/ext_idle.c +++ b/kernel/sched/ext_idle.c @@ -927,14 +927,24 @@ static s32 select_cpu_from_kfunc(struct scx_sched *sch, struct task_struct *p, * Accessing p->cpus_ptr / p->nr_cpus_allowed needs either @p's rq * lock or @p's pi_lock. Three cases: * - * - inside ops.select_cpu(): try_to_wake_up() holds @p's pi_lock. + * - inside ops.select_cpu(): try_to_wake_up() holds the wake-up + * task's pi_lock; the wake-up task is recorded in kf_tasks[0] + * by SCX_CALL_OP_TASK_RET(). * - other rq-locked SCX op: scx_locked_rq() points at the held rq. * - truly unlocked (UNLOCKED ops, SYSCALL, non-SCX struct_ops): * nothing held, take pi_lock ourselves. + * + * In the first two cases, BPF schedulers may pass an arbitrary task + * that the held lock doesn't cover. Refuse those. */ if (this_rq()->scx.in_select_cpu) { + if (!scx_kf_arg_task_ok(sch, p)) + return -EINVAL; lockdep_assert_held(&p->pi_lock); - } else if (!scx_locked_rq()) { + } else if (scx_locked_rq()) { + if (task_rq(p) != scx_locked_rq()) + goto cross_task; + } else { raw_spin_lock_irqsave(&p->pi_lock, irq_flags); we_locked = true; } @@ -960,6 +970,11 @@ static s32 select_cpu_from_kfunc(struct scx_sched *sch, struct task_struct *p, raw_spin_unlock_irqrestore(&p->pi_lock, irq_flags); return cpu; + +cross_task: + scx_error(sch, "select_cpu kfunc called cross-task on %s[%d]", + p->comm, p->pid); + return -EINVAL; } /** @@ -1467,6 +1482,7 @@ BTF_KFUNCS_END(scx_kfunc_ids_idle) static const struct btf_kfunc_id_set scx_kfunc_set_idle = { .owner = THIS_MODULE, .set = &scx_kfunc_ids_idle, + .filter = scx_kfunc_context_filter, }; /* diff --git a/kernel/sched/ext_idle.h b/kernel/sched/ext_idle.h index dc35f850481e..8d169d3bbdf9 100644 --- a/kernel/sched/ext_idle.h +++ b/kernel/sched/ext_idle.h @@ -12,6 +12,7 @@ struct sched_ext_ops; +extern struct btf_id_set8 scx_kfunc_ids_idle; extern struct btf_id_set8 scx_kfunc_ids_select_cpu; void scx_idle_update_selcpu_topology(struct sched_ext_ops *ops); diff --git a/kernel/sched/ext_internal.h b/kernel/sched/ext_internal.h index 62ce4eaf6a3f..a075732d4430 100644 --- a/kernel/sched/ext_internal.h +++ b/kernel/sched/ext_internal.h @@ -1075,6 +1075,8 @@ struct scx_sched { struct irq_work disable_irq_work; struct kthread_work disable_work; struct timer_list bypass_lb_timer; + cpumask_var_t bypass_lb_donee_cpumask; + cpumask_var_t bypass_lb_resched_cpumask; struct rcu_work rcu_work; /* all ancestors including self */ diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 69361c63353a..728965851842 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -847,13 +847,19 @@ static s64 entity_lag(struct cfs_rq *cfs_rq, struct sched_entity *se, u64 avrunt * Similarly, check that the entity didn't gain positive lag when DELAY_ZERO * is set. * - * Return true if the lag has been adjusted. + * Return true if the vlag has been modified. Specifically: + * + * se->vlag != avg_vruntime() - se->vruntime + * + * This can be due to clamping in entity_lag() or clamping due to + * sched_delayed. Either way, when vlag is modified and the entity is + * retained, the tree needs to be adjusted. */ static __always_inline bool update_entity_lag(struct cfs_rq *cfs_rq, struct sched_entity *se) { - s64 vlag = entity_lag(cfs_rq, se, avg_vruntime(cfs_rq)); - bool ret; + u64 avruntime = avg_vruntime(cfs_rq); + s64 vlag = entity_lag(cfs_rq, se, avruntime); WARN_ON_ONCE(!se->on_rq); @@ -863,10 +869,9 @@ bool update_entity_lag(struct cfs_rq *cfs_rq, struct sched_entity *se) if (sched_feat(DELAY_ZERO)) vlag = min(vlag, 0); } - ret = (vlag == se->vlag); se->vlag = vlag; - return ret; + return avruntime - vlag != se->vruntime; } /* @@ -1099,7 +1104,7 @@ static inline void cancel_protect_slice(struct sched_entity *se) * * Which allows tree pruning through eligibility. */ -static struct sched_entity *__pick_eevdf(struct cfs_rq *cfs_rq, bool protect) +static struct sched_entity *pick_eevdf(struct cfs_rq *cfs_rq, bool protect) { struct rb_node *node = cfs_rq->tasks_timeline.rb_root.rb_node; struct sched_entity *se = __pick_first_entity(cfs_rq); @@ -1170,11 +1175,6 @@ static struct sched_entity *__pick_eevdf(struct cfs_rq *cfs_rq, bool protect) return best; } -static struct sched_entity *pick_eevdf(struct cfs_rq *cfs_rq) -{ - return __pick_eevdf(cfs_rq, true); -} - struct sched_entity *__pick_last_entity(struct cfs_rq *cfs_rq) { struct rb_node *last = rb_last(&cfs_rq->tasks_timeline.rb_root); @@ -5749,11 +5749,11 @@ static int dequeue_entities(struct rq *rq, struct sched_entity *se, int flags); * 4) do not run the "skip" process, if something else is available */ static struct sched_entity * -pick_next_entity(struct rq *rq, struct cfs_rq *cfs_rq) +pick_next_entity(struct rq *rq, struct cfs_rq *cfs_rq, bool protect) { struct sched_entity *se; - se = pick_eevdf(cfs_rq); + se = pick_eevdf(cfs_rq, protect); if (se->sched_delayed) { dequeue_entities(rq, se, DEQUEUE_SLEEP | DEQUEUE_DELAYED); /* @@ -9027,7 +9027,7 @@ static void wakeup_preempt_fair(struct rq *rq, struct task_struct *p, int wake_f { enum preempt_wakeup_action preempt_action = PREEMPT_WAKEUP_PICK; struct task_struct *donor = rq->donor; - struct sched_entity *se = &donor->se, *pse = &p->se; + struct sched_entity *nse, *se = &donor->se, *pse = &p->se; struct cfs_rq *cfs_rq = task_cfs_rq(donor); int cse_is_idle, pse_is_idle; @@ -9138,12 +9138,18 @@ static void wakeup_preempt_fair(struct rq *rq, struct task_struct *p, int wake_f } pick: - /* - * If @p has become the most eligible task, force preemption. - */ - if (__pick_eevdf(cfs_rq, preempt_action != PREEMPT_WAKEUP_SHORT) == pse) + nse = pick_next_entity(rq, cfs_rq, preempt_action != PREEMPT_WAKEUP_SHORT); + /* If @p has become the most eligible task, force preemption */ + if (nse == pse) goto preempt; + /* + * Because p is enqueued, nse being null can only mean that we + * dequeued a delayed task. + */ + if (!nse) + goto pick; + if (sched_feat(RUN_TO_PARITY)) update_protect_slice(cfs_rq, se); @@ -9179,7 +9185,7 @@ static struct task_struct *pick_task_fair(struct rq *rq, struct rq_flags *rf) throttled |= check_cfs_rq_runtime(cfs_rq); - se = pick_next_entity(rq, cfs_rq); + se = pick_next_entity(rq, cfs_rq, true); if (!se) goto again; cfs_rq = group_cfs_rq(se); diff --git a/kernel/trace/trace_branch.c b/kernel/trace/trace_branch.c index 6809b370e991..d1564db95a8f 100644 --- a/kernel/trace/trace_branch.c +++ b/kernel/trace/trace_branch.c @@ -373,10 +373,10 @@ __init static int init_annotated_branch_stats(void) int ret; ret = register_stat_tracer(&annotated_branch_stats); - if (!ret) { + if (ret) { printk(KERN_WARNING "Warning: could not register " "annotated branches stats\n"); - return 1; + return ret; } return 0; } @@ -438,10 +438,10 @@ __init static int all_annotated_branch_stats(void) int ret; ret = register_stat_tracer(&all_branch_stats); - if (!ret) { + if (ret) { printk(KERN_WARNING "Warning: could not register " "all branches stats\n"); - return 1; + return ret; } return 0; } diff --git a/kernel/trace/trace_probe.c b/kernel/trace/trace_probe.c index e1c73065dae5..e0d3a0da26af 100644 --- a/kernel/trace/trace_probe.c +++ b/kernel/trace/trace_probe.c @@ -1523,6 +1523,12 @@ static int traceprobe_parse_probe_arg_body(const char *argv, ssize_t *size, parg->offset = *size; *size += parg->type->size * (parg->count ?: 1); + if (*size > MAX_PROBE_EVENT_SIZE) { + ret = -E2BIG; + trace_probe_log_err(ctx->offset, EVENT_TOO_BIG); + goto fail; + } + if (parg->count) { len = strlen(parg->type->fmttype) + 6; parg->fmt = kmalloc(len, GFP_KERNEL); diff --git a/kernel/trace/trace_probe.h b/kernel/trace/trace_probe.h index 9fc56c937130..262d8707a3df 100644 --- a/kernel/trace/trace_probe.h +++ b/kernel/trace/trace_probe.h @@ -38,6 +38,7 @@ #define MAX_BTF_ARGS_LEN 128 #define MAX_DENTRY_ARGS_LEN 256 #define MAX_STRING_SIZE PATH_MAX +#define MAX_PROBE_EVENT_SIZE 3072 /* Reserved field names */ #define FIELD_STRING_IP "__probe_ip" @@ -561,7 +562,8 @@ extern int traceprobe_define_arg_fields(struct trace_event_call *event_call, C(BAD_TYPE4STR, "This type does not fit for string."),\ C(NEED_STRING_TYPE, "$comm and immediate-string only accepts string type"),\ C(TOO_MANY_ARGS, "Too many arguments are specified"), \ - C(TOO_MANY_EARGS, "Too many entry arguments specified"), + C(TOO_MANY_EARGS, "Too many entry arguments specified"), \ + C(EVENT_TOO_BIG, "Event too big (too many fields?)"), #undef C #define C(a, b) TP_ERR_##a diff --git a/lib/maple_tree.c b/lib/maple_tree.c index d18d7ed9ab67..60ae5e6fc1ee 100644 --- a/lib/maple_tree.c +++ b/lib/maple_tree.c @@ -2,7 +2,7 @@ /* * Maple Tree implementation * Copyright (c) 2018-2022 Oracle Corporation - * Authors: Liam R. Howlett + * Authors: Liam R. Howlett * Matthew Wilcox * Copyright (c) 2023 ByteDance * Author: Peng Zhang diff --git a/lib/rhashtable.c b/lib/rhashtable.c index 6074ed5f66f3..7a67ef5b67b6 100644 --- a/lib/rhashtable.c +++ b/lib/rhashtable.c @@ -441,10 +441,33 @@ static void rht_deferred_worker(struct work_struct *work) mutex_unlock(&ht->mutex); + /* + * Re-arm via @run_work, not @run_irq_work. + * rhashtable_free_and_destroy() drains async work as irq_work_sync() + * followed by cancel_work_sync(). If this site queued irq_work while + * cancel_work_sync() was waiting for us, irq_work_sync() would already + * have returned and the stale irq_work could fire post-teardown. + * cancel_work_sync() natively handles self-requeue on @run_work. + */ if (err) schedule_work(&ht->run_work); } +/* + * Insert-path callers can run under a raw spinlock (e.g. an insecure_elasticity + * user). Calling schedule_work() under that lock records caller_lock -> + * pool->lock -> pi_lock -> rq->__lock, closing a locking cycle if any of + * these is acquired in the reverse direction elsewhere. Bounce through + * irq_work so the schedule_work() runs with the caller's lock no longer held. + */ +static void rht_deferred_irq_work(struct irq_work *irq_work) +{ + struct rhashtable *ht = container_of(irq_work, struct rhashtable, + run_irq_work); + + schedule_work(&ht->run_work); +} + static int rhashtable_insert_rehash(struct rhashtable *ht, struct bucket_table *tbl) { @@ -477,7 +500,7 @@ static int rhashtable_insert_rehash(struct rhashtable *ht, if (err == -EEXIST) err = 0; } else - schedule_work(&ht->run_work); + irq_work_queue(&ht->run_irq_work); return err; @@ -488,7 +511,7 @@ static int rhashtable_insert_rehash(struct rhashtable *ht, /* Schedule async rehash to retry allocation in process context. */ if (err == -ENOMEM) - schedule_work(&ht->run_work); + irq_work_queue(&ht->run_irq_work); return err; } @@ -538,7 +561,7 @@ static void *rhashtable_lookup_one(struct rhashtable *ht, return NULL; } - if (elasticity <= 0) + if (elasticity <= 0 && !ht->p.insecure_elasticity) return ERR_PTR(-EAGAIN); return ERR_PTR(-ENOENT); @@ -568,7 +591,8 @@ static struct bucket_table *rhashtable_insert_one( if (unlikely(rht_grow_above_max(ht, tbl))) return ERR_PTR(-E2BIG); - if (unlikely(rht_grow_above_100(ht, tbl))) + if (unlikely(rht_grow_above_100(ht, tbl)) && + !ht->p.insecure_elasticity) return ERR_PTR(-EAGAIN); head = rht_ptr(bkt, tbl, hash); @@ -629,7 +653,7 @@ static void *rhashtable_try_insert(struct rhashtable *ht, const void *key, rht_unlock(tbl, bkt, flags); if (inserted && rht_grow_above_75(ht, tbl)) - schedule_work(&ht->run_work); + irq_work_queue(&ht->run_irq_work); } } while (!IS_ERR_OR_NULL(new_tbl)); @@ -1084,6 +1108,7 @@ int rhashtable_init_noprof(struct rhashtable *ht, RCU_INIT_POINTER(ht->tbl, tbl); INIT_WORK(&ht->run_work, rht_deferred_worker); + init_irq_work(&ht->run_irq_work, rht_deferred_irq_work); return 0; } @@ -1149,6 +1174,7 @@ void rhashtable_free_and_destroy(struct rhashtable *ht, struct bucket_table *tbl, *next_tbl; unsigned int i; + irq_work_sync(&ht->run_irq_work); cancel_work_sync(&ht->run_work); mutex_lock(&ht->mutex); diff --git a/lib/test_maple_tree.c b/lib/test_maple_tree.c index 434d8a2fdd99..b9367c61e8b5 100644 --- a/lib/test_maple_tree.c +++ b/lib/test_maple_tree.c @@ -2,7 +2,7 @@ /* * test_maple_tree.c: Test the maple tree API * Copyright (c) 2018-2022 Oracle Corporation - * Author: Liam R. Howlett + * Author: Liam R. Howlett * * Any tests that only require the interface of the tree. */ @@ -4021,6 +4021,6 @@ static void __exit maple_tree_harvest(void) module_init(maple_tree_seed); module_exit(maple_tree_harvest); -MODULE_AUTHOR("Liam R. Howlett "); +MODULE_AUTHOR("Liam R. Howlett "); MODULE_DESCRIPTION("maple tree API test module"); MODULE_LICENSE("GPL"); diff --git a/mm/damon/lru_sort.c b/mm/damon/lru_sort.c index 554559d72976..8494040b1ee4 100644 --- a/mm/damon/lru_sort.c +++ b/mm/damon/lru_sort.c @@ -161,15 +161,6 @@ module_param(monitor_region_end, ulong, 0600); */ static unsigned long addr_unit __read_mostly = 1; -/* - * PID of the DAMON thread - * - * If DAMON_LRU_SORT is enabled, this becomes the PID of the worker thread. - * Else, -1. - */ -static int kdamond_pid __read_mostly = -1; -module_param(kdamond_pid, int, 0400); - static struct damos_stat damon_lru_sort_hot_stat; DEFINE_DAMON_MODULES_DAMOS_STATS_PARAMS(damon_lru_sort_hot_stat, lru_sort_tried_hot_regions, lru_sorted_hot_regions, @@ -386,12 +377,8 @@ static int damon_lru_sort_turn(bool on) { int err; - if (!on) { - err = damon_stop(&ctx, 1); - if (!err) - kdamond_pid = -1; - return err; - } + if (!on) + return damon_stop(&ctx, 1); err = damon_lru_sort_apply_parameters(); if (err) @@ -400,9 +387,6 @@ static int damon_lru_sort_turn(bool on) err = damon_start(&ctx, 1, true); if (err) return err; - kdamond_pid = damon_kdamond_pid(ctx); - if (kdamond_pid < 0) - return kdamond_pid; return damon_call(ctx, &call_control); } @@ -430,42 +414,83 @@ module_param_cb(addr_unit, &addr_unit_param_ops, &addr_unit, 0600); MODULE_PARM_DESC(addr_unit, "Scale factor for DAMON_LRU_SORT to ops address conversion (default: 1)"); +static bool damon_lru_sort_enabled(void) +{ + if (!ctx) + return false; + return damon_is_running(ctx); +} + static int damon_lru_sort_enabled_store(const char *val, const struct kernel_param *kp) { - bool is_enabled = enabled; - bool enable; int err; - err = kstrtobool(val, &enable); + err = kstrtobool(val, &enabled); if (err) return err; - if (is_enabled == enable) + if (damon_lru_sort_enabled() == enabled) return 0; /* Called before init function. The function will handle this. */ if (!damon_initialized()) - goto set_param_out; + return 0; - err = damon_lru_sort_turn(enable); - if (err) - return err; + return damon_lru_sort_turn(enabled); +} -set_param_out: - enabled = enable; - return err; +static int damon_lru_sort_enabled_load(char *buffer, + const struct kernel_param *kp) +{ + return sprintf(buffer, "%c\n", damon_lru_sort_enabled() ? 'Y' : 'N'); } static const struct kernel_param_ops enabled_param_ops = { .set = damon_lru_sort_enabled_store, - .get = param_get_bool, + .get = damon_lru_sort_enabled_load, }; module_param_cb(enabled, &enabled_param_ops, &enabled, 0600); MODULE_PARM_DESC(enabled, "Enable or disable DAMON_LRU_SORT (default: disabled)"); +static int damon_lru_sort_kdamond_pid_store(const char *val, + const struct kernel_param *kp) +{ + /* + * kdamond_pid is read-only, but kernel command line could write it. + * Do nothing here. + */ + return 0; +} + +static int damon_lru_sort_kdamond_pid_load(char *buffer, + const struct kernel_param *kp) +{ + int kdamond_pid = -1; + + if (ctx) { + kdamond_pid = damon_kdamond_pid(ctx); + if (kdamond_pid < 0) + kdamond_pid = -1; + } + return sprintf(buffer, "%d\n", kdamond_pid); +} + +static const struct kernel_param_ops kdamond_pid_param_ops = { + .set = damon_lru_sort_kdamond_pid_store, + .get = damon_lru_sort_kdamond_pid_load, +}; + +/* + * PID of the DAMON thread + * + * If DAMON_LRU_SORT is enabled, this becomes the PID of the worker thread. + * Else, -1. + */ +module_param_cb(kdamond_pid, &kdamond_pid_param_ops, NULL, 0400); + static int __init damon_lru_sort_init(void) { int err; diff --git a/mm/damon/reclaim.c b/mm/damon/reclaim.c index 86da14778658..fe7fce26cf6c 100644 --- a/mm/damon/reclaim.c +++ b/mm/damon/reclaim.c @@ -144,15 +144,6 @@ static unsigned long addr_unit __read_mostly = 1; static bool skip_anon __read_mostly; module_param(skip_anon, bool, 0600); -/* - * PID of the DAMON thread - * - * If DAMON_RECLAIM is enabled, this becomes the PID of the worker thread. - * Else, -1. - */ -static int kdamond_pid __read_mostly = -1; -module_param(kdamond_pid, int, 0400); - static struct damos_stat damon_reclaim_stat; DEFINE_DAMON_MODULES_DAMOS_STATS_PARAMS(damon_reclaim_stat, reclaim_tried_regions, reclaimed_regions, quota_exceeds); @@ -288,12 +279,8 @@ static int damon_reclaim_turn(bool on) { int err; - if (!on) { - err = damon_stop(&ctx, 1); - if (!err) - kdamond_pid = -1; - return err; - } + if (!on) + return damon_stop(&ctx, 1); err = damon_reclaim_apply_parameters(); if (err) @@ -302,9 +289,6 @@ static int damon_reclaim_turn(bool on) err = damon_start(&ctx, 1, true); if (err) return err; - kdamond_pid = damon_kdamond_pid(ctx); - if (kdamond_pid < 0) - return kdamond_pid; return damon_call(ctx, &call_control); } @@ -332,42 +316,83 @@ module_param_cb(addr_unit, &addr_unit_param_ops, &addr_unit, 0600); MODULE_PARM_DESC(addr_unit, "Scale factor for DAMON_RECLAIM to ops address conversion (default: 1)"); +static bool damon_reclaim_enabled(void) +{ + if (!ctx) + return false; + return damon_is_running(ctx); +} + static int damon_reclaim_enabled_store(const char *val, const struct kernel_param *kp) { - bool is_enabled = enabled; - bool enable; int err; - err = kstrtobool(val, &enable); + err = kstrtobool(val, &enabled); if (err) return err; - if (is_enabled == enable) + if (damon_reclaim_enabled() == enabled) return 0; /* Called before init function. The function will handle this. */ if (!damon_initialized()) - goto set_param_out; + return 0; - err = damon_reclaim_turn(enable); - if (err) - return err; + return damon_reclaim_turn(enabled); +} -set_param_out: - enabled = enable; - return err; +static int damon_reclaim_enabled_load(char *buffer, + const struct kernel_param *kp) +{ + return sprintf(buffer, "%c\n", damon_reclaim_enabled() ? 'Y' : 'N'); } static const struct kernel_param_ops enabled_param_ops = { .set = damon_reclaim_enabled_store, - .get = param_get_bool, + .get = damon_reclaim_enabled_load, }; module_param_cb(enabled, &enabled_param_ops, &enabled, 0600); MODULE_PARM_DESC(enabled, "Enable or disable DAMON_RECLAIM (default: disabled)"); +static int damon_reclaim_kdamond_pid_store(const char *val, + const struct kernel_param *kp) +{ + /* + * kdamond_pid is read-only, but kernel command line could write it. + * Do nothing here. + */ + return 0; +} + +static int damon_reclaim_kdamond_pid_load(char *buffer, + const struct kernel_param *kp) +{ + int kdamond_pid = -1; + + if (ctx) { + kdamond_pid = damon_kdamond_pid(ctx); + if (kdamond_pid < 0) + kdamond_pid = -1; + } + return sprintf(buffer, "%d\n", kdamond_pid); +} + +static const struct kernel_param_ops kdamond_pid_param_ops = { + .set = damon_reclaim_kdamond_pid_store, + .get = damon_reclaim_kdamond_pid_load, +}; + +/* + * PID of the DAMON thread + * + * If DAMON_RECLAIM is enabled, this becomes the PID of the worker thread. + * Else, -1. + */ +module_param_cb(kdamond_pid, &kdamond_pid_param_ops, NULL, 0400); + static int __init damon_reclaim_init(void) { int err; diff --git a/mm/damon/stat.c b/mm/damon/stat.c index 99ba346f9e32..3951b762cbdd 100644 --- a/mm/damon/stat.c +++ b/mm/damon/stat.c @@ -19,14 +19,17 @@ static int damon_stat_enabled_store( const char *val, const struct kernel_param *kp); +static int damon_stat_enabled_load(char *buffer, + const struct kernel_param *kp); + static const struct kernel_param_ops enabled_param_ops = { .set = damon_stat_enabled_store, - .get = param_get_bool, + .get = damon_stat_enabled_load, }; static bool enabled __read_mostly = IS_ENABLED( CONFIG_DAMON_STAT_ENABLED_DEFAULT); -module_param_cb(enabled, &enabled_param_ops, &enabled, 0600); +module_param_cb(enabled, &enabled_param_ops, NULL, 0600); MODULE_PARM_DESC(enabled, "Enable of disable DAMON_STAT"); static unsigned long estimated_memory_bandwidth __read_mostly; @@ -273,17 +276,23 @@ static void damon_stat_stop(void) damon_stat_context = NULL; } +static bool damon_stat_enabled(void) +{ + if (!damon_stat_context) + return false; + return damon_is_running(damon_stat_context); +} + static int damon_stat_enabled_store( const char *val, const struct kernel_param *kp) { - bool is_enabled = enabled; int err; err = kstrtobool(val, &enabled); if (err) return err; - if (is_enabled == enabled) + if (damon_stat_enabled() == enabled) return 0; if (!damon_initialized()) @@ -293,16 +302,17 @@ static int damon_stat_enabled_store( */ return 0; - if (enabled) { - err = damon_stat_start(); - if (err) - enabled = false; - return err; - } + if (enabled) + return damon_stat_start(); damon_stat_stop(); return 0; } +static int damon_stat_enabled_load(char *buffer, const struct kernel_param *kp) +{ + return sprintf(buffer, "%c\n", damon_stat_enabled() ? 'Y' : 'N'); +} + static int __init damon_stat_init(void) { int err = 0; diff --git a/mm/damon/sysfs-schemes.c b/mm/damon/sysfs-schemes.c index 5186966dafb3..245d63808411 100644 --- a/mm/damon/sysfs-schemes.c +++ b/mm/damon/sysfs-schemes.c @@ -533,9 +533,14 @@ static ssize_t memcg_path_show(struct kobject *kobj, { struct damon_sysfs_scheme_filter *filter = container_of(kobj, struct damon_sysfs_scheme_filter, kobj); + int len; - return sysfs_emit(buf, "%s\n", + if (!mutex_trylock(&damon_sysfs_lock)) + return -EBUSY; + len = sysfs_emit(buf, "%s\n", filter->memcg_path ? filter->memcg_path : ""); + mutex_unlock(&damon_sysfs_lock); + return len; } static ssize_t memcg_path_store(struct kobject *kobj, @@ -550,8 +555,13 @@ static ssize_t memcg_path_store(struct kobject *kobj, return -ENOMEM; strscpy(path, buf, count + 1); + if (!mutex_trylock(&damon_sysfs_lock)) { + kfree(path); + return -EBUSY; + } kfree(filter->memcg_path); filter->memcg_path = path; + mutex_unlock(&damon_sysfs_lock); return count; } @@ -1187,8 +1197,13 @@ static ssize_t path_show(struct kobject *kobj, { struct damos_sysfs_quota_goal *goal = container_of(kobj, struct damos_sysfs_quota_goal, kobj); + int len; - return sysfs_emit(buf, "%s\n", goal->path ? goal->path : ""); + if (!mutex_trylock(&damon_sysfs_lock)) + return -EBUSY; + len = sysfs_emit(buf, "%s\n", goal->path ? goal->path : ""); + mutex_unlock(&damon_sysfs_lock); + return len; } static ssize_t path_store(struct kobject *kobj, @@ -1203,8 +1218,13 @@ static ssize_t path_store(struct kobject *kobj, return -ENOMEM; strscpy(path, buf, count + 1); + if (!mutex_trylock(&damon_sysfs_lock)) { + kfree(path); + return -EBUSY; + } kfree(goal->path); goal->path = path; + mutex_unlock(&damon_sysfs_lock); return count; } diff --git a/mm/hugetlb_cma.c b/mm/hugetlb_cma.c index f83ae4998990..7693ccefd0c6 100644 --- a/mm/hugetlb_cma.c +++ b/mm/hugetlb_cma.c @@ -204,6 +204,7 @@ void __init hugetlb_cma_reserve(void) */ per_node = DIV_ROUND_UP(hugetlb_cma_size, nodes_weight(hugetlb_bootmem_nodes)); + per_node = round_up(per_node, PAGE_SIZE << order); pr_info("hugetlb_cma: reserve %lu MiB, up to %lu MiB per node\n", hugetlb_cma_size / SZ_1M, per_node / SZ_1M); } diff --git a/mm/memcontrol.c b/mm/memcontrol.c index c3d98ab41f1f..c03d4787d466 100644 --- a/mm/memcontrol.c +++ b/mm/memcontrol.c @@ -805,12 +805,17 @@ static long memcg_state_val_in_pages(int idx, long val) * Used in mod_memcg_state() and mod_memcg_lruvec_state() to avoid race with * reparenting of non-hierarchical state_locals. */ -static inline struct mem_cgroup *get_non_dying_memcg_start(struct mem_cgroup *memcg) +static inline struct mem_cgroup *get_non_dying_memcg_start(struct mem_cgroup *memcg, + bool *rcu_locked) { - if (cgroup_subsys_on_dfl(memory_cgrp_subsys)) + /* Rebinding can cause this value to be changed at runtime */ + if (cgroup_subsys_on_dfl(memory_cgrp_subsys)) { + *rcu_locked = false; return memcg; + } rcu_read_lock(); + *rcu_locked = true; while (memcg_is_dying(memcg)) memcg = parent_mem_cgroup(memcg); @@ -818,20 +823,21 @@ static inline struct mem_cgroup *get_non_dying_memcg_start(struct mem_cgroup *me return memcg; } -static inline void get_non_dying_memcg_end(void) +static inline void get_non_dying_memcg_end(bool rcu_locked) { - if (cgroup_subsys_on_dfl(memory_cgrp_subsys)) + if (!rcu_locked) return; rcu_read_unlock(); } #else -static inline struct mem_cgroup *get_non_dying_memcg_start(struct mem_cgroup *memcg) +static inline struct mem_cgroup *get_non_dying_memcg_start(struct mem_cgroup *memcg, + bool *rcu_locked) { return memcg; } -static inline void get_non_dying_memcg_end(void) +static inline void get_non_dying_memcg_end(bool rcu_locked) { } #endif @@ -865,12 +871,14 @@ static void __mod_memcg_state(struct mem_cgroup *memcg, void mod_memcg_state(struct mem_cgroup *memcg, enum memcg_stat_item idx, int val) { + bool rcu_locked = false; + if (mem_cgroup_disabled()) return; - memcg = get_non_dying_memcg_start(memcg); + memcg = get_non_dying_memcg_start(memcg, &rcu_locked); __mod_memcg_state(memcg, idx, val); - get_non_dying_memcg_end(); + get_non_dying_memcg_end(rcu_locked); } #ifdef CONFIG_MEMCG_V1 @@ -933,14 +941,15 @@ static void mod_memcg_lruvec_state(struct lruvec *lruvec, struct pglist_data *pgdat = lruvec_pgdat(lruvec); struct mem_cgroup_per_node *pn; struct mem_cgroup *memcg; + bool rcu_locked = false; pn = container_of(lruvec, struct mem_cgroup_per_node, lruvec); - memcg = get_non_dying_memcg_start(pn->memcg); + memcg = get_non_dying_memcg_start(pn->memcg, &rcu_locked); pn = memcg->nodeinfo[pgdat->node_id]; __mod_memcg_lruvec_state(pn, idx, val); - get_non_dying_memcg_end(); + get_non_dying_memcg_end(rcu_locked); } /** diff --git a/mm/page-writeback.c b/mm/page-writeback.c index 88cd53d4ba09..833f743f309f 100644 --- a/mm/page-writeback.c +++ b/mm/page-writeback.c @@ -1835,7 +1835,9 @@ static int balance_dirty_pages(struct bdi_writeback *wb, balance_domain_limits(mdtc, strictlimit); } - if (nr_dirty > gdtc->bg_thresh && !writeback_in_progress(wb)) + if (!writeback_in_progress(wb) && + (nr_dirty > gdtc->bg_thresh || + (strictlimit && gdtc->wb_dirty > gdtc->wb_bg_thresh))) wb_start_background_writeback(wb); /* @@ -1862,15 +1864,9 @@ static int balance_dirty_pages(struct bdi_writeback *wb, * Unconditionally start background writeback if it's not * already in progress. We need to do this because the global * dirty threshold check above (nr_dirty > gdtc->bg_thresh) - * doesn't account for these cases: - * - * a) strictlimit BDIs: throttling is calculated using per-wb - * thresholds. The per-wb threshold can be exceeded even when - * nr_dirty < gdtc->bg_thresh - * - * b) memcg-based throttling: memcg uses its own dirty count and - * thresholds and can trigger throttling even when global - * nr_dirty < gdtc->bg_thresh + * doesn't account for the memcg-based throttling case. memcg + * uses its own dirty count and thresholds and can trigger + * throttling even when global nr_dirty < gdtc->bg_thresh * * Writeback needs to be started else the writer stalls in the * throttle loop waiting for dirty pages to be written back diff --git a/mm/page_alloc.c b/mm/page_alloc.c index 65e205111553..227d58dc3de6 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -7737,6 +7737,11 @@ struct page *alloc_frozen_pages_nolock_noprof(gfp_t gfp_flags, int nid, unsigned */ if (IS_ENABLED(CONFIG_PREEMPT_RT) && (in_nmi() || in_hardirq())) return NULL; + + /* On UP, spin_trylock() always succeeds even when it is locked */ + if (!IS_ENABLED(CONFIG_SMP) && in_nmi()) + return NULL; + if (!pcp_allowed_order(order)) return NULL; diff --git a/mm/slub.c b/mm/slub.c index 161079ac5ba1..0baa906f39ab 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -5339,6 +5339,10 @@ void *kmalloc_nolock_noprof(size_t size, gfp_t gfp_flags, int node) if (IS_ENABLED(CONFIG_PREEMPT_RT) && (in_nmi() || in_hardirq())) return NULL; + /* On UP, spin_trylock() always succeeds even when it is locked */ + if (!IS_ENABLED(CONFIG_SMP) && in_nmi()) + return NULL; + retry: if (unlikely(size > KMALLOC_MAX_CACHE_SIZE)) return NULL; diff --git a/mm/userfaultfd.c b/mm/userfaultfd.c index 885da1e56466..180bad42fc79 100644 --- a/mm/userfaultfd.c +++ b/mm/userfaultfd.c @@ -443,8 +443,10 @@ static int mfill_copy_folio_locked(struct folio *folio, unsigned long src_addr) return ret; } -static int mfill_copy_folio_retry(struct mfill_state *state, struct folio *folio) +static int mfill_copy_folio_retry(struct mfill_state *state, + struct folio *folio) { + const struct vm_uffd_ops *orig_ops = vma_uffd_ops(state->vma); unsigned long src_addr = state->src_addr; void *kaddr; int err; @@ -465,6 +467,14 @@ static int mfill_copy_folio_retry(struct mfill_state *state, struct folio *folio if (err) return err; + /* + * The VMA type may have changed while the lock was dropped + * (e.g. replaced with a hugetlb mapping), making the caller's + * ops pointer stale. + */ + if (vma_uffd_ops(state->vma) != orig_ops) + return -EAGAIN; + err = mfill_establish_pmd(state); if (err) return err; diff --git a/mm/util.c b/mm/util.c index 232c3930a662..3cc949a0b7ed 100644 --- a/mm/util.c +++ b/mm/util.c @@ -1232,7 +1232,7 @@ int __compat_vma_mmap(struct vm_area_desc *desc, /* Update the VMA from the descriptor. */ compat_set_vma_from_desc(vma, desc); /* Complete any specified mmap actions. */ - return mmap_action_complete(vma, &desc->action); + return mmap_action_complete(vma, &desc->action, /*is_compat=*/true); } EXPORT_SYMBOL(__compat_vma_mmap); @@ -1389,7 +1389,8 @@ static int call_vma_mapped(struct vm_area_struct *vma) } static int mmap_action_finish(struct vm_area_struct *vma, - struct mmap_action *action, int err) + struct mmap_action *action, int err, + bool is_compat) { size_t len; @@ -1400,8 +1401,12 @@ static int mmap_action_finish(struct vm_area_struct *vma, /* do_munmap() might take rmap lock, so release if held. */ maybe_rmap_unlock_action(vma, action); - if (!err) - return 0; + /* + * If this is invoked from the compatibility layer, post-mmap() hook + * logic will handle cleanup for us. + */ + if (!err || is_compat) + return err; /* * If an error occurs, unmap the VMA altogether and return an error. We @@ -1451,13 +1456,15 @@ EXPORT_SYMBOL(mmap_action_prepare); * mmap_action_complete - Execute VMA descriptor action. * @vma: The VMA to perform the action upon. * @action: The action to perform. + * @is_compat: Is this being invoked from the compatibility layer? * * Similar to mmap_action_prepare(). * - * Return: 0 on success, or error, at which point the VMA will be unmapped. + * Return: 0 on success, or error, at which point the VMA will be unmapped if + * !@is_compat. */ int mmap_action_complete(struct vm_area_struct *vma, - struct mmap_action *action) + struct mmap_action *action, bool is_compat) { int err = 0; @@ -1478,7 +1485,7 @@ int mmap_action_complete(struct vm_area_struct *vma, break; } - return mmap_action_finish(vma, action, err); + return mmap_action_finish(vma, action, err, is_compat); } EXPORT_SYMBOL(mmap_action_complete); #else @@ -1500,7 +1507,8 @@ int mmap_action_prepare(struct vm_area_desc *desc) EXPORT_SYMBOL(mmap_action_prepare); int mmap_action_complete(struct vm_area_struct *vma, - struct mmap_action *action) + struct mmap_action *action, + bool is_compat) { int err = 0; @@ -1517,7 +1525,7 @@ int mmap_action_complete(struct vm_area_struct *vma, break; } - return mmap_action_finish(vma, action, err); + return mmap_action_finish(vma, action, err, is_compat); } EXPORT_SYMBOL(mmap_action_complete); #endif diff --git a/mm/vma.c b/mm/vma.c index 377321b48734..d90791b00a7b 100644 --- a/mm/vma.c +++ b/mm/vma.c @@ -2780,7 +2780,8 @@ static unsigned long __mmap_region(struct file *file, unsigned long addr, __mmap_complete(&map, vma); if (have_mmap_prepare && allocated_new) { - error = mmap_action_complete(vma, &desc.action); + error = mmap_action_complete(vma, &desc.action, + /*is_compat=*/false); if (error) return error; } diff --git a/mm/vmalloc.c b/mm/vmalloc.c index aa08651ec0df..c31a8615a832 100644 --- a/mm/vmalloc.c +++ b/mm/vmalloc.c @@ -4361,7 +4361,7 @@ void *vrealloc_node_align_noprof(const void *p, size_t size, unsigned long align return NULL; if (p) { - memcpy(n, p, old_size); + memcpy(n, p, min(size, old_size)); vfree(p); } diff --git a/net/core/devmem.c b/net/core/devmem.c index cde4c89bc146..468344739db2 100644 --- a/net/core/devmem.c +++ b/net/core/devmem.c @@ -297,8 +297,7 @@ net_devmem_bind_dmabuf(struct net_device *dev, for (i = 0; i < owner->area.num_niovs; i++) { niov = &owner->area.niovs[i]; - niov->type = NET_IOV_DMABUF; - niov->owner = &owner->area; + net_iov_init(niov, &owner->area, NET_IOV_DMABUF); page_pool_set_dma_addr_netmem(net_iov_to_netmem(niov), net_devmem_get_dma_addr(niov)); if (direction == DMA_TO_DEVICE) diff --git a/net/core/neighbour.c b/net/core/neighbour.c index 9e12524b67fa..5d9216016507 100644 --- a/net/core/neighbour.c +++ b/net/core/neighbour.c @@ -3210,8 +3210,10 @@ int neigh_xmit(int index, struct net_device *dev, rcu_read_lock(); tbl = rcu_dereference(neigh_tables[index]); - if (!tbl) - goto out_unlock; + if (!tbl) { + rcu_read_unlock(); + goto out_kfree_skb; + } if (index == NEIGH_ARP_TABLE) { u32 key = *((u32 *)addr); @@ -3227,7 +3229,6 @@ int neigh_xmit(int index, struct net_device *dev, goto out_kfree_skb; } err = READ_ONCE(neigh->output)(neigh, skb); -out_unlock: rcu_read_unlock(); } else if (index == NEIGH_LINK_TABLE) { @@ -3237,11 +3238,10 @@ int neigh_xmit(int index, struct net_device *dev, goto out_kfree_skb; err = dev_queue_xmit(skb); } -out: return err; out_kfree_skb: kfree_skb(skb); - goto out; + return err; } EXPORT_SYMBOL(neigh_xmit); diff --git a/net/core/netpoll.c b/net/core/netpoll.c index cd74beffd209..4381e0fc25bf 100644 --- a/net/core/netpoll.c +++ b/net/core/netpoll.c @@ -704,6 +704,23 @@ static int netpoll_take_ipv4(struct netpoll *np, struct net_device *ndev) return 0; } +/* + * Test whether the caller left np->local_ip unset, so that + * netpoll_setup() should auto-populate it from the egress device. + * + * np->local_ip is a union of __be32 (IPv4) and struct in6_addr (IPv6), + * so an IPv6 address whose first 4 bytes are zero (e.g. ::1, ::2, + * IPv4-mapped ::ffff:a.b.c.d) must not be tested via the IPv4 arm — + * doing so would misclassify a caller-supplied address as unset and + * silently overwrite it with whatever address the device exposes. + */ +static bool netpoll_local_ip_unset(const struct netpoll *np) +{ + if (np->ipv6) + return ipv6_addr_any(&np->local_ip.in6); + return !np->local_ip.ip; +} + int netpoll_setup(struct netpoll *np) { struct net *net = current->nsproxy->net_ns; @@ -747,7 +764,7 @@ int netpoll_setup(struct netpoll *np) rtnl_lock(); } - if (!np->local_ip.ip) { + if (netpoll_local_ip_unset(np)) { if (!np->ipv6) { err = netpoll_take_ipv4(np, ndev); if (err) diff --git a/net/core/page_pool.c b/net/core/page_pool.c index 877bbf7a1938..6e576dec80db 100644 --- a/net/core/page_pool.c +++ b/net/core/page_pool.c @@ -327,6 +327,11 @@ static void page_pool_uninit(struct page_pool *pool) if (!pool->system) free_percpu(pool->recycle_stats); #endif + + if (pool->mp_ops) { + pool->mp_ops->destroy(pool); + static_branch_dec(&page_pool_mem_providers); + } } /** @@ -1146,11 +1151,6 @@ static void __page_pool_destroy(struct page_pool *pool) page_pool_unlist(pool); page_pool_uninit(pool); - if (pool->mp_ops) { - pool->mp_ops->destroy(pool); - static_branch_dec(&page_pool_mem_providers); - } - kfree(pool); } diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c index 8a08d09b4c30..2058ca860294 100644 --- a/net/ipv4/ipmr.c +++ b/net/ipv4/ipmr.c @@ -151,16 +151,6 @@ static struct mr_table *__ipmr_get_table(struct net *net, u32 id) return NULL; } -static struct mr_table *ipmr_get_table(struct net *net, u32 id) -{ - struct mr_table *mrt; - - rcu_read_lock(); - mrt = __ipmr_get_table(net, id); - rcu_read_unlock(); - return mrt; -} - static int ipmr_fib_lookup(struct net *net, struct flowi4 *flp4, struct mr_table **mrt) { @@ -293,7 +283,7 @@ static void __net_exit ipmr_rules_exit_rtnl(struct net *net, struct mr_table *mrt, *next; list_for_each_entry_safe(mrt, next, &net->ipv4.mr_tables, list) { - list_del(&mrt->list); + list_del_rcu(&mrt->list); ipmr_free_table(mrt, dev_kill_list); } } @@ -315,28 +305,30 @@ bool ipmr_rule_default(const struct fib_rule *rule) } EXPORT_SYMBOL(ipmr_rule_default); #else -#define ipmr_for_each_table(mrt, net) \ - for (mrt = net->ipv4.mrt; mrt; mrt = NULL) - static struct mr_table *ipmr_mr_table_iter(struct net *net, struct mr_table *mrt) { if (!mrt) - return net->ipv4.mrt; + return rcu_dereference(net->ipv4.mrt); return NULL; } -static struct mr_table *ipmr_get_table(struct net *net, u32 id) +static struct mr_table *__ipmr_get_table(struct net *net, u32 id) { - return net->ipv4.mrt; + return rcu_dereference_check(net->ipv4.mrt, + lockdep_rtnl_is_held() || + !rcu_access_pointer(net->ipv4.mrt)); } -#define __ipmr_get_table ipmr_get_table +#define ipmr_for_each_table(mrt, net) \ + for (mrt = __ipmr_get_table(net, 0); mrt; mrt = NULL) static int ipmr_fib_lookup(struct net *net, struct flowi4 *flp4, struct mr_table **mrt) { - *mrt = net->ipv4.mrt; + *mrt = rcu_dereference(net->ipv4.mrt); + if (!*mrt) + return -EAGAIN; return 0; } @@ -347,7 +339,8 @@ static int __net_init ipmr_rules_init(struct net *net) mrt = ipmr_new_table(net, RT_TABLE_DEFAULT); if (IS_ERR(mrt)) return PTR_ERR(mrt); - net->ipv4.mrt = mrt; + + rcu_assign_pointer(net->ipv4.mrt, mrt); return 0; } @@ -358,9 +351,10 @@ static void __net_exit ipmr_rules_exit(struct net *net) static void __net_exit ipmr_rules_exit_rtnl(struct net *net, struct list_head *dev_kill_list) { - ipmr_free_table(net->ipv4.mrt, dev_kill_list); + struct mr_table *mrt = rcu_dereference_protected(net->ipv4.mrt, 1); - net->ipv4.mrt = NULL; + RCU_INIT_POINTER(net->ipv4.mrt, NULL); + ipmr_free_table(mrt, dev_kill_list); } static int ipmr_rules_dump(struct net *net, struct notifier_block *nb, @@ -381,6 +375,17 @@ bool ipmr_rule_default(const struct fib_rule *rule) EXPORT_SYMBOL(ipmr_rule_default); #endif +static struct mr_table *ipmr_get_table(struct net *net, u32 id) +{ + struct mr_table *mrt; + + rcu_read_lock(); + mrt = __ipmr_get_table(net, id); + rcu_read_unlock(); + + return mrt; +} + static inline int ipmr_hash_cmp(struct rhashtable_compare_arg *arg, const void *ptr) { @@ -441,12 +446,11 @@ static void ipmr_free_table(struct mr_table *mrt, struct list_head *dev_kill_lis WARN_ON_ONCE(!mr_can_free_table(net)); - timer_shutdown_sync(&mrt->ipmr_expire_timer); mroute_clean_tables(mrt, MRT_FLUSH_VIFS | MRT_FLUSH_VIFS_STATIC | MRT_FLUSH_MFC | MRT_FLUSH_MFC_STATIC, &ipmr_dev_kill_list); - rhltable_destroy(&mrt->mfc_hash); - kfree(mrt); + timer_shutdown_sync(&mrt->ipmr_expire_timer); + mr_table_free(mrt); WARN_ON_ONCE(!net_initialized(net) && !list_empty(&ipmr_dev_kill_list)); list_splice(&ipmr_dev_kill_list, dev_kill_list); @@ -1135,12 +1139,19 @@ static int ipmr_cache_report(const struct mr_table *mrt, static int ipmr_cache_unresolved(struct mr_table *mrt, vifi_t vifi, struct sk_buff *skb, struct net_device *dev) { + struct net *net = read_pnet(&mrt->net); const struct iphdr *iph = ip_hdr(skb); - struct mfc_cache *c; + struct mfc_cache *c = NULL; bool found = false; int err; spin_lock_bh(&mfc_unres_lock); + + if (!check_net(net)) { + err = -EINVAL; + goto err; + } + list_for_each_entry(c, &mrt->mfc_unres_queue, _c.list) { if (c->mfc_mcastgrp == iph->daddr && c->mfc_origin == iph->saddr) { @@ -1153,10 +1164,8 @@ static int ipmr_cache_unresolved(struct mr_table *mrt, vifi_t vifi, /* Create a new entry if allowable */ c = ipmr_cache_alloc_unres(); if (!c) { - spin_unlock_bh(&mfc_unres_lock); - - kfree_skb(skb); - return -ENOBUFS; + err = -ENOBUFS; + goto err; } /* Fill in the new cache entry */ @@ -1166,17 +1175,8 @@ static int ipmr_cache_unresolved(struct mr_table *mrt, vifi_t vifi, /* Reflect first query at mrouted. */ err = ipmr_cache_report(mrt, skb, vifi, IGMPMSG_NOCACHE); - - if (err < 0) { - /* If the report failed throw the cache entry - out - Brad Parker - */ - spin_unlock_bh(&mfc_unres_lock); - - ipmr_cache_free(c); - kfree_skb(skb); - return err; - } + if (err < 0) + goto err; atomic_inc(&mrt->cache_resolve_queue_len); list_add(&c->_c.list, &mrt->mfc_unres_queue); @@ -1189,18 +1189,26 @@ static int ipmr_cache_unresolved(struct mr_table *mrt, vifi_t vifi, /* See if we can append the packet */ if (c->_c.mfc_un.unres.unresolved.qlen > 3) { - kfree_skb(skb); + c = NULL; err = -ENOBUFS; - } else { - if (dev) { - skb->dev = dev; - skb->skb_iif = dev->ifindex; - } - skb_queue_tail(&c->_c.mfc_un.unres.unresolved, skb); - err = 0; + goto err; } + if (dev) { + skb->dev = dev; + skb->skb_iif = dev->ifindex; + } + + skb_queue_tail(&c->_c.mfc_un.unres.unresolved, skb); + spin_unlock_bh(&mfc_unres_lock); + return 0; + +err: + spin_unlock_bh(&mfc_unres_lock); + if (c) + ipmr_cache_free(c); + kfree_skb(skb); return err; } @@ -1346,7 +1354,7 @@ static void mroute_clean_tables(struct mr_table *mrt, int flags, } if (flags & MRT_FLUSH_MFC) { - if (atomic_read(&mrt->cache_resolve_queue_len) != 0) { + if (atomic_read(&mrt->cache_resolve_queue_len) != 0 || !check_net(net)) { spin_lock_bh(&mfc_unres_lock); list_for_each_entry_safe(c, tmp, &mrt->mfc_unres_queue, list) { list_del(&c->list); diff --git a/net/ipv4/ipmr_base.c b/net/ipv4/ipmr_base.c index 37a3c144276c..3930d612c3de 100644 --- a/net/ipv4/ipmr_base.c +++ b/net/ipv4/ipmr_base.c @@ -28,6 +28,20 @@ void vif_device_init(struct vif_device *v, v->link = dev->ifindex; } +static void __mr_free_table(struct work_struct *work) +{ + struct mr_table *mrt = container_of(to_rcu_work(work), + struct mr_table, work); + + rhltable_destroy(&mrt->mfc_hash); + kfree(mrt); +} + +void mr_table_free(struct mr_table *mrt) +{ + queue_rcu_work(system_unbound_wq, &mrt->work); +} + struct mr_table * mr_table_alloc(struct net *net, u32 id, struct mr_table_ops *ops, @@ -50,6 +64,8 @@ mr_table_alloc(struct net *net, u32 id, kfree(mrt); return ERR_PTR(err); } + + INIT_RCU_WORK(&mrt->work, __mr_free_table); INIT_LIST_HEAD(&mrt->mfc_cache_list); INIT_LIST_HEAD(&mrt->mfc_unres_queue); diff --git a/net/ipv4/netfilter/arp_tables.c b/net/ipv4/netfilter/arp_tables.c index 1cdd9c28ab2d..97ead883e4a1 100644 --- a/net/ipv4/netfilter/arp_tables.c +++ b/net/ipv4/netfilter/arp_tables.c @@ -110,13 +110,25 @@ static inline int arp_packet_match(const struct arphdr *arphdr, arpptr += dev->addr_len; memcpy(&src_ipaddr, arpptr, sizeof(u32)); arpptr += sizeof(u32); - tgt_devaddr = arpptr; - arpptr += dev->addr_len; + + if (IS_ENABLED(CONFIG_FIREWIRE_NET) && dev->type == ARPHRD_IEEE1394) { + if (unlikely(memchr_inv(arpinfo->tgt_devaddr.mask, 0, + sizeof(arpinfo->tgt_devaddr.mask)))) + return 0; + + tgt_devaddr = NULL; + } else { + tgt_devaddr = arpptr; + arpptr += dev->addr_len; + } memcpy(&tgt_ipaddr, arpptr, sizeof(u32)); if (NF_INVF(arpinfo, ARPT_INV_SRCDEVADDR, arp_devaddr_compare(&arpinfo->src_devaddr, src_devaddr, - dev->addr_len)) || + dev->addr_len))) + return 0; + + if (tgt_devaddr && NF_INVF(arpinfo, ARPT_INV_TGTDEVADDR, arp_devaddr_compare(&arpinfo->tgt_devaddr, tgt_devaddr, dev->addr_len))) diff --git a/net/ipv4/netfilter/arpt_mangle.c b/net/ipv4/netfilter/arpt_mangle.c index a4e07e5e9c11..f65dd339208e 100644 --- a/net/ipv4/netfilter/arpt_mangle.c +++ b/net/ipv4/netfilter/arpt_mangle.c @@ -40,6 +40,10 @@ target(struct sk_buff *skb, const struct xt_action_param *par) } arpptr += pln; if (mangle->flags & ARPT_MANGLE_TDEV) { + if (unlikely(IS_ENABLED(CONFIG_FIREWIRE_NET) && + skb->dev->type == ARPHRD_IEEE1394)) + return NF_DROP; + if (ARPT_DEV_ADDR_LEN_MAX < hln || (arpptr + hln > skb_tail_pointer(skb))) return NF_DROP; @@ -47,6 +51,10 @@ target(struct sk_buff *skb, const struct xt_action_param *par) } arpptr += hln; if (mangle->flags & ARPT_MANGLE_TIP) { + if (unlikely(IS_ENABLED(CONFIG_FIREWIRE_NET) && + skb->dev->type == ARPHRD_IEEE1394)) + return NF_DROP; + if (ARPT_MANGLE_ADDR_LEN_MAX < pln || (arpptr + pln > skb_tail_pointer(skb))) return NF_DROP; diff --git a/net/ipv4/tcp_timer.c b/net/ipv4/tcp_timer.c index 8d791a954cd6..322db13333c7 100644 --- a/net/ipv4/tcp_timer.c +++ b/net/ipv4/tcp_timer.c @@ -50,7 +50,8 @@ static u32 tcp_clamp_rto_to_user_timeout(const struct sock *sk) u32 tcp_clamp_probe0_to_user_timeout(const struct sock *sk, u32 when) { const struct inet_connection_sock *icsk = inet_csk(sk); - u32 remaining, user_timeout; + u32 user_timeout; + s32 remaining; s32 elapsed; user_timeout = READ_ONCE(icsk->icsk_user_timeout); @@ -61,7 +62,7 @@ u32 tcp_clamp_probe0_to_user_timeout(const struct sock *sk, u32 when) if (unlikely(elapsed < 0)) elapsed = 0; remaining = msecs_to_jiffies(user_timeout) - elapsed; - remaining = max_t(u32, remaining, TCP_TIMEOUT_MIN); + remaining = max_t(int, remaining, TCP_TIMEOUT_MIN); return min_t(u32, remaining, when); } diff --git a/net/ipv6/exthdrs.c b/net/ipv6/exthdrs.c index 95558fd6f447..03cbce842c1a 100644 --- a/net/ipv6/exthdrs.c +++ b/net/ipv6/exthdrs.c @@ -491,6 +491,7 @@ static int ipv6_rpl_srh_rcv(struct sk_buff *skb) struct net *net = dev_net(skb->dev); struct inet6_dev *idev; struct ipv6hdr *oldhdr; + unsigned int chdr_len; unsigned char *buf; int accept_rpl_seg; int i, err; @@ -592,8 +593,10 @@ static int ipv6_rpl_srh_rcv(struct sk_buff *skb) skb_pull(skb, ((hdr->hdrlen + 1) << 3)); skb_postpull_rcsum(skb, oldhdr, sizeof(struct ipv6hdr) + ((hdr->hdrlen + 1) << 3)); - if (unlikely(!hdr->segments_left)) { - if (pskb_expand_head(skb, sizeof(struct ipv6hdr) + ((chdr->hdrlen + 1) << 3), 0, + chdr_len = sizeof(struct ipv6hdr) + ((chdr->hdrlen + 1) << 3); + if (unlikely(!hdr->segments_left || + skb_headroom(skb) < chdr_len + skb->mac_len)) { + if (pskb_expand_head(skb, chdr_len + skb->mac_len, 0, GFP_ATOMIC)) { __IP6_INC_STATS(net, ip6_dst_idev(skb_dst(skb)), IPSTATS_MIB_OUTDISCARDS); kfree_skb(skb); @@ -603,7 +606,7 @@ static int ipv6_rpl_srh_rcv(struct sk_buff *skb) oldhdr = ipv6_hdr(skb); } - skb_push(skb, ((chdr->hdrlen + 1) << 3) + sizeof(struct ipv6hdr)); + skb_push(skb, chdr_len); skb_reset_network_header(skb); skb_mac_header_rebuild(skb); skb_set_transport_header(skb, sizeof(struct ipv6hdr)); diff --git a/net/ipv6/rpl_iptunnel.c b/net/ipv6/rpl_iptunnel.c index c7942cf65567..4e10adcd70e8 100644 --- a/net/ipv6/rpl_iptunnel.c +++ b/net/ipv6/rpl_iptunnel.c @@ -287,7 +287,16 @@ static int rpl_input(struct sk_buff *skb) if (!dst) { ip6_route_input(skb); + + /* ip6_route_input() sets a NOREF dst; force a refcount on it + * before caching or further use. + */ + skb_dst_force(skb); dst = skb_dst(skb); + if (unlikely(!dst)) { + err = -ENETUNREACH; + goto drop; + } /* cache only if we don't create a dst reference loop */ if (!dst->error && lwtst != dst->lwtstate) { diff --git a/net/ipv6/seg6_iptunnel.c b/net/ipv6/seg6_iptunnel.c index 9b64343ebad6..4c45c0a77d75 100644 --- a/net/ipv6/seg6_iptunnel.c +++ b/net/ipv6/seg6_iptunnel.c @@ -515,7 +515,16 @@ static int seg6_input_core(struct net *net, struct sock *sk, if (!dst) { ip6_route_input(skb); + + /* ip6_route_input() sets a NOREF dst; force a refcount on it + * before caching or further use. + */ + skb_dst_force(skb); dst = skb_dst(skb); + if (unlikely(!dst)) { + err = -ENETUNREACH; + goto drop; + } /* cache only if we don't create a dst reference loop */ if (!dst->error && lwtst != dst->lwtstate) { diff --git a/net/mptcp/pm_kernel.c b/net/mptcp/pm_kernel.c index 0ebf43be9939..c9f1e5af3cd3 100644 --- a/net/mptcp/pm_kernel.c +++ b/net/mptcp/pm_kernel.c @@ -1278,6 +1278,7 @@ static void __reset_counters(struct pm_nl_pernet *pernet) WRITE_ONCE(pernet->endp_signal_max, 0); WRITE_ONCE(pernet->endp_subflow_max, 0); WRITE_ONCE(pernet->endp_laminar_max, 0); + WRITE_ONCE(pernet->endp_fullmesh_max, 0); pernet->endpoints = 0; } diff --git a/net/mptcp/protocol.c b/net/mptcp/protocol.c index 718e910ff23f..4546a8b09884 100644 --- a/net/mptcp/protocol.c +++ b/net/mptcp/protocol.c @@ -3302,7 +3302,8 @@ bool __mptcp_close(struct sock *sk, long timeout) goto cleanup; } - if (mptcp_data_avail(msk) || timeout < 0) { + if (mptcp_data_avail(msk) || timeout < 0 || + (sock_flag(sk, SOCK_LINGER) && !sk->sk_lingertime)) { /* If the msk has read data, or the caller explicitly ask it, * do the MPTCP equivalent of TCP reset, aka MPTCP fastclose */ diff --git a/net/mptcp/sockopt.c b/net/mptcp/sockopt.c index de90a2897d2d..0efe40be2fde 100644 --- a/net/mptcp/sockopt.c +++ b/net/mptcp/sockopt.c @@ -159,10 +159,10 @@ static int mptcp_setsockopt_sol_socket_tstamp(struct mptcp_sock *msk, int optnam lock_sock(sk); mptcp_for_each_subflow(msk, subflow) { struct sock *ssk = mptcp_subflow_tcp_sock(subflow); - bool slow = lock_sock_fast(ssk); - sock_set_timestamp(sk, optname, !!val); - unlock_sock_fast(ssk, slow); + lock_sock(ssk); + sock_set_timestamp(ssk, optname, !!val); + release_sock(ssk); } release_sock(sk); @@ -235,10 +235,10 @@ static int mptcp_setsockopt_sol_socket_timestamping(struct mptcp_sock *msk, mptcp_for_each_subflow(msk, subflow) { struct sock *ssk = mptcp_subflow_tcp_sock(subflow); - bool slow = lock_sock_fast(ssk); - sock_set_timestamping(sk, optname, timestamping); - unlock_sock_fast(ssk, slow); + lock_sock(ssk); + sock_set_timestamping(ssk, optname, timestamping); + release_sock(ssk); } release_sock(sk); diff --git a/net/netfilter/nf_conntrack_proto_sctp.c b/net/netfilter/nf_conntrack_proto_sctp.c index 645d2c43ebf7..7e10fa65cbdd 100644 --- a/net/netfilter/nf_conntrack_proto_sctp.c +++ b/net/netfilter/nf_conntrack_proto_sctp.c @@ -466,9 +466,13 @@ int nf_conntrack_sctp_packet(struct nf_conn *ct, if (!ih) goto out_unlock; - if (ct->proto.sctp.init[dir] && ct->proto.sctp.init[!dir]) - ct->proto.sctp.init[!dir] = 0; - ct->proto.sctp.init[dir] = 1; + /* Do not record INIT matching peer vtag (stale or retransmitted INIT). */ + if (old_state == SCTP_CONNTRACK_NONE || + ct->proto.sctp.vtag[!dir] != ih->init_tag) { + if (ct->proto.sctp.init[dir] && ct->proto.sctp.init[!dir]) + ct->proto.sctp.init[!dir] = 0; + ct->proto.sctp.init[dir] = 1; + } pr_debug("Setting vtag %x for dir %d\n", ih->init_tag, !dir); ct->proto.sctp.vtag[!dir] = ih->init_tag; diff --git a/net/netfilter/nf_conntrack_sip.c b/net/netfilter/nf_conntrack_sip.c index 182cfb119448..1eb55907d470 100644 --- a/net/netfilter/nf_conntrack_sip.c +++ b/net/netfilter/nf_conntrack_sip.c @@ -181,6 +181,57 @@ static int sip_parse_addr(const struct nf_conn *ct, const char *cp, return 1; } +/* Parse optional port number after IP address. + * Returns false on malformed input, true otherwise. + * If port is non-NULL, stores parsed port in network byte order. + * If no port is present, sets *port to default SIP port. + */ +static bool sip_parse_port(const char *dptr, const char **endp, + const char *limit, __be16 *port) +{ + unsigned int p = 0; + int len = 0; + + if (dptr >= limit) + return false; + + if (*dptr != ':') { + if (port) + *port = htons(SIP_PORT); + if (endp) + *endp = dptr; + return true; + } + + dptr++; /* skip ':' */ + + while (dptr < limit && isdigit(*dptr)) { + p = p * 10 + (*dptr - '0'); + dptr++; + len++; + if (len > 5) /* max "65535" */ + return false; + } + + if (len == 0) + return false; + + /* reached limit while parsing port */ + if (dptr >= limit) + return false; + + if (p < 1024 || p > 65535) + return false; + + if (port) + *port = htons(p); + + if (endp) + *endp = dptr; + + return true; +} + /* skip ip address. returns its length. */ static int epaddr_len(const struct nf_conn *ct, const char *dptr, const char *limit, int *shift) @@ -193,11 +244,8 @@ static int epaddr_len(const struct nf_conn *ct, const char *dptr, return 0; } - /* Port number */ - if (*dptr == ':') { - dptr++; - dptr += digits_len(ct, dptr, limit, shift); - } + if (!sip_parse_port(dptr, &dptr, limit, NULL)) + return 0; return dptr - aux; } @@ -228,6 +276,51 @@ static int skp_epaddr_len(const struct nf_conn *ct, const char *dptr, return epaddr_len(ct, dptr, limit, shift); } +/* simple_strtoul stops after first non-number character. + * But as we're not dealing with c-strings, we can't rely on + * hitting \r,\n,\0 etc. before moving past end of buffer. + * + * This is a variant of simple_strtoul, but doesn't require + * a c-string. + * + * If value exceeds UINT_MAX, 0 is returned. + */ +static unsigned int sip_strtouint(const char *cp, unsigned int len, char **endp) +{ + const unsigned int max = sizeof("4294967295"); + unsigned int olen = len; + const char *s = cp; + u64 result = 0; + + if (len > max) + len = max; + + while (olen > 0 && isdigit(*s)) { + unsigned int value; + + if (len == 0) + goto err; + + value = *s - '0'; + result = result * 10 + value; + + if (result > UINT_MAX) + goto err; + s++; + len--; + olen--; + } + + if (endp) + *endp = (char *)s; + + return result; +err: + if (endp) + *endp = (char *)cp; + return 0; +} + /* Parse a SIP request line of the form: * * Request-Line = Method SP Request-URI SP SIP-Version CRLF @@ -241,7 +334,6 @@ int ct_sip_parse_request(const struct nf_conn *ct, { const char *start = dptr, *limit = dptr + datalen, *end; unsigned int mlen; - unsigned int p; int shift = 0; /* Skip method and following whitespace */ @@ -267,14 +359,8 @@ int ct_sip_parse_request(const struct nf_conn *ct, if (!sip_parse_addr(ct, dptr, &end, addr, limit, true)) return -1; - if (end < limit && *end == ':') { - end++; - p = simple_strtoul(end, (char **)&end, 10); - if (p < 1024 || p > 65535) - return -1; - *port = htons(p); - } else - *port = htons(SIP_PORT); + if (!sip_parse_port(end, &end, limit, port)) + return -1; if (end == dptr) return 0; @@ -509,7 +595,6 @@ int ct_sip_parse_header_uri(const struct nf_conn *ct, const char *dptr, union nf_inet_addr *addr, __be16 *port) { const char *c, *limit = dptr + datalen; - unsigned int p; int ret; ret = ct_sip_walk_headers(ct, dptr, dataoff ? *dataoff : 0, datalen, @@ -520,14 +605,8 @@ int ct_sip_parse_header_uri(const struct nf_conn *ct, const char *dptr, if (!sip_parse_addr(ct, dptr + *matchoff, &c, addr, limit, true)) return -1; - if (*c == ':') { - c++; - p = simple_strtoul(c, (char **)&c, 10); - if (p < 1024 || p > 65535) - return -1; - *port = htons(p); - } else - *port = htons(SIP_PORT); + if (!sip_parse_port(c, &c, limit, port)) + return -1; if (dataoff) *dataoff = c - dptr; @@ -609,7 +688,7 @@ int ct_sip_parse_numerical_param(const struct nf_conn *ct, const char *dptr, return 0; start += strlen(name); - *val = simple_strtoul(start, &end, 0); + *val = sip_strtouint(start, limit - start, (char **)&end); if (start == end) return -1; if (matchoff && matchlen) { @@ -1064,6 +1143,8 @@ static int process_sdp(struct sk_buff *skb, unsigned int protoff, mediaoff = sdpoff; for (i = 0; i < ARRAY_SIZE(sdp_media_types); ) { + char *end; + if (ct_sip_get_sdp_header(ct, *dptr, mediaoff, *datalen, SDP_HDR_MEDIA, SDP_HDR_UNSPEC, &mediaoff, &medialen) <= 0) @@ -1079,8 +1160,8 @@ static int process_sdp(struct sk_buff *skb, unsigned int protoff, mediaoff += t->len; medialen -= t->len; - port = simple_strtoul(*dptr + mediaoff, NULL, 10); - if (port == 0) + port = sip_strtouint(*dptr + mediaoff, *datalen - mediaoff, (char **)&end); + if (port == 0 || *dptr + mediaoff == end) continue; if (port < 1024 || port > 65535) { nf_ct_helper_log(skb, ct, "wrong port %u", port); @@ -1254,7 +1335,7 @@ static int process_register_request(struct sk_buff *skb, unsigned int protoff, */ if (ct_sip_get_header(ct, *dptr, 0, *datalen, SIP_HDR_EXPIRES, &matchoff, &matchlen) > 0) - expires = simple_strtoul(*dptr + matchoff, NULL, 10); + expires = sip_strtouint(*dptr + matchoff, *datalen - matchoff, NULL); ret = ct_sip_parse_header_uri(ct, *dptr, NULL, *datalen, SIP_HDR_CONTACT, NULL, @@ -1358,7 +1439,7 @@ static int process_register_response(struct sk_buff *skb, unsigned int protoff, if (ct_sip_get_header(ct, *dptr, 0, *datalen, SIP_HDR_EXPIRES, &matchoff, &matchlen) > 0) - expires = simple_strtoul(*dptr + matchoff, NULL, 10); + expires = sip_strtouint(*dptr + matchoff, *datalen - matchoff, NULL); while (1) { unsigned int c_expires = expires; @@ -1418,10 +1499,12 @@ static int process_sip_response(struct sk_buff *skb, unsigned int protoff, struct nf_conn *ct = nf_ct_get(skb, &ctinfo); unsigned int matchoff, matchlen, matchend; unsigned int code, cseq, i; + char *end; if (*datalen < strlen("SIP/2.0 200")) return NF_ACCEPT; - code = simple_strtoul(*dptr + strlen("SIP/2.0 "), NULL, 10); + code = sip_strtouint(*dptr + strlen("SIP/2.0 "), + *datalen - strlen("SIP/2.0 "), NULL); if (!code) { nf_ct_helper_log(skb, ct, "cannot get code"); return NF_DROP; @@ -1432,8 +1515,8 @@ static int process_sip_response(struct sk_buff *skb, unsigned int protoff, nf_ct_helper_log(skb, ct, "cannot parse cseq"); return NF_DROP; } - cseq = simple_strtoul(*dptr + matchoff, NULL, 10); - if (!cseq && *(*dptr + matchoff) != '0') { + cseq = sip_strtouint(*dptr + matchoff, *datalen - matchoff, (char **)&end); + if (*dptr + matchoff == end) { nf_ct_helper_log(skb, ct, "cannot get cseq"); return NF_DROP; } @@ -1482,6 +1565,7 @@ static int process_sip_request(struct sk_buff *skb, unsigned int protoff, for (i = 0; i < ARRAY_SIZE(sip_handlers); i++) { const struct sip_handler *handler; + char *end; handler = &sip_handlers[i]; if (handler->request == NULL) @@ -1498,8 +1582,8 @@ static int process_sip_request(struct sk_buff *skb, unsigned int protoff, nf_ct_helper_log(skb, ct, "cannot parse cseq"); return NF_DROP; } - cseq = simple_strtoul(*dptr + matchoff, NULL, 10); - if (!cseq && *(*dptr + matchoff) != '0') { + cseq = sip_strtouint(*dptr + matchoff, *datalen - matchoff, (char **)&end); + if (*dptr + matchoff == end) { nf_ct_helper_log(skb, ct, "cannot get cseq"); return NF_DROP; } @@ -1575,7 +1659,7 @@ static int sip_help_tcp(struct sk_buff *skb, unsigned int protoff, &matchoff, &matchlen) <= 0) break; - clen = simple_strtoul(dptr + matchoff, (char **)&end, 10); + clen = sip_strtouint(dptr + matchoff, datalen - matchoff, (char **)&end); if (dptr + matchoff == end) break; diff --git a/net/netfilter/nf_nat_sip.c b/net/netfilter/nf_nat_sip.c index c845b6d1a2bd..9fbfc6bff0c2 100644 --- a/net/netfilter/nf_nat_sip.c +++ b/net/netfilter/nf_nat_sip.c @@ -246,6 +246,7 @@ static unsigned int nf_nat_sip(struct sk_buff *skb, unsigned int protoff, if (ct_sip_parse_numerical_param(ct, *dptr, matchend, *datalen, "rport=", &poff, &plen, &n) > 0 && + n >= 1024 && n <= 65535 && htons(n) == ct->tuplehash[dir].tuple.dst.u.udp.port && htons(n) != ct->tuplehash[!dir].tuple.src.u.udp.port) { __be16 p = ct->tuplehash[!dir].tuple.src.u.udp.port; diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 8537b94653d3..d20ce5c36d31 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -374,6 +374,38 @@ static void nft_netdev_hook_free_rcu(struct nft_hook *hook) call_rcu(&hook->rcu, __nft_netdev_hook_free_rcu); } +static void nft_netdev_hook_unlink_free_rcu(struct nft_hook *hook) +{ + list_del_rcu(&hook->list); + nft_netdev_hook_free_rcu(hook); +} + +static void nft_trans_hook_destroy(struct nft_trans_hook *trans_hook) +{ + list_del(&trans_hook->list); + kfree(trans_hook); +} + +static void nft_netdev_unregister_trans_hook(struct net *net, + const struct nft_table *table, + struct list_head *hook_list) +{ + struct nft_trans_hook *trans_hook, *next; + struct nf_hook_ops *ops; + struct nft_hook *hook; + + list_for_each_entry_safe(trans_hook, next, hook_list, list) { + hook = trans_hook->hook; + + if (!(table->flags & NFT_TABLE_F_DORMANT)) { + list_for_each_entry(ops, &hook->ops_list, list) + nf_unregister_net_hook(net, ops); + } + nft_netdev_hook_unlink_free_rcu(hook); + nft_trans_hook_destroy(trans_hook); + } +} + static void nft_netdev_unregister_hooks(struct net *net, struct list_head *hook_list, bool release_netdev) @@ -384,10 +416,8 @@ static void nft_netdev_unregister_hooks(struct net *net, list_for_each_entry_safe(hook, next, hook_list, list) { list_for_each_entry(ops, &hook->ops_list, list) nf_unregister_net_hook(net, ops); - if (release_netdev) { - list_del(&hook->list); - nft_netdev_hook_free_rcu(hook); - } + if (release_netdev) + nft_netdev_hook_unlink_free_rcu(hook); } } @@ -1942,15 +1972,69 @@ static int nft_nla_put_hook_dev(struct sk_buff *skb, struct nft_hook *hook) return nla_put_string(skb, attr, hook->ifname); } +struct nft_hook_dump_ctx { + struct nft_hook *first; + int n; +}; + +static int nft_dump_basechain_hook_one(struct sk_buff *skb, + struct nft_hook *hook, + struct nft_hook_dump_ctx *dump_ctx) +{ + if (!dump_ctx->first) + dump_ctx->first = hook; + + if (nft_nla_put_hook_dev(skb, hook)) + return -1; + + dump_ctx->n++; + + return 0; +} + +static int nft_dump_basechain_hook_list(struct sk_buff *skb, + const struct net *net, + const struct list_head *hook_list, + struct nft_hook_dump_ctx *dump_ctx) +{ + struct nft_hook *hook; + int err; + + list_for_each_entry_rcu(hook, hook_list, list, + lockdep_commit_lock_is_held(net)) { + err = nft_dump_basechain_hook_one(skb, hook, dump_ctx); + if (err < 0) + return err; + } + + return 0; +} + +static int nft_dump_basechain_trans_hook_list(struct sk_buff *skb, + const struct list_head *trans_hook_list, + struct nft_hook_dump_ctx *dump_ctx) +{ + struct nft_trans_hook *trans_hook; + int err; + + list_for_each_entry(trans_hook, trans_hook_list, list) { + err = nft_dump_basechain_hook_one(skb, trans_hook->hook, dump_ctx); + if (err < 0) + return err; + } + + return 0; +} + static int nft_dump_basechain_hook(struct sk_buff *skb, const struct net *net, int family, const struct nft_base_chain *basechain, - const struct list_head *hook_list) + const struct list_head *hook_list, + const struct list_head *trans_hook_list) { const struct nf_hook_ops *ops = &basechain->ops; - struct nft_hook *hook, *first = NULL; + struct nft_hook_dump_ctx dump_hook_ctx = {}; struct nlattr *nest, *nest_devs; - int n = 0; nest = nla_nest_start_noflag(skb, NFTA_CHAIN_HOOK); if (nest == NULL) @@ -1965,23 +2049,23 @@ static int nft_dump_basechain_hook(struct sk_buff *skb, if (!nest_devs) goto nla_put_failure; - if (!hook_list) + if (!hook_list && !trans_hook_list) hook_list = &basechain->hook_list; - list_for_each_entry_rcu(hook, hook_list, list, - lockdep_commit_lock_is_held(net)) { - if (!first) - first = hook; - - if (nft_nla_put_hook_dev(skb, hook)) - goto nla_put_failure; - n++; + if (hook_list && + nft_dump_basechain_hook_list(skb, net, hook_list, &dump_hook_ctx)) { + goto nla_put_failure; + } else if (trans_hook_list && + nft_dump_basechain_trans_hook_list(skb, trans_hook_list, + &dump_hook_ctx)) { + goto nla_put_failure; } + nla_nest_end(skb, nest_devs); - if (n == 1 && - !hook_is_prefix(first) && - nla_put_string(skb, NFTA_HOOK_DEV, first->ifname)) + if (dump_hook_ctx.n == 1 && + !hook_is_prefix(dump_hook_ctx.first) && + nla_put_string(skb, NFTA_HOOK_DEV, dump_hook_ctx.first->ifname)) goto nla_put_failure; } nla_nest_end(skb, nest); @@ -1995,7 +2079,8 @@ static int nf_tables_fill_chain_info(struct sk_buff *skb, struct net *net, u32 portid, u32 seq, int event, u32 flags, int family, const struct nft_table *table, const struct nft_chain *chain, - const struct list_head *hook_list) + const struct list_head *hook_list, + const struct list_head *trans_hook_list) { struct nlmsghdr *nlh; @@ -2011,7 +2096,7 @@ static int nf_tables_fill_chain_info(struct sk_buff *skb, struct net *net, NFTA_CHAIN_PAD)) goto nla_put_failure; - if (!hook_list && + if (!hook_list && !trans_hook_list && (event == NFT_MSG_DELCHAIN || event == NFT_MSG_DESTROYCHAIN)) { nlmsg_end(skb, nlh); @@ -2022,7 +2107,8 @@ static int nf_tables_fill_chain_info(struct sk_buff *skb, struct net *net, const struct nft_base_chain *basechain = nft_base_chain(chain); struct nft_stats __percpu *stats; - if (nft_dump_basechain_hook(skb, net, family, basechain, hook_list)) + if (nft_dump_basechain_hook(skb, net, family, basechain, + hook_list, trans_hook_list)) goto nla_put_failure; if (nla_put_be32(skb, NFTA_CHAIN_POLICY, @@ -2058,7 +2144,8 @@ static int nf_tables_fill_chain_info(struct sk_buff *skb, struct net *net, } static void nf_tables_chain_notify(const struct nft_ctx *ctx, int event, - const struct list_head *hook_list) + const struct list_head *hook_list, + const struct list_head *trans_hook_list) { struct nftables_pernet *nft_net; struct sk_buff *skb; @@ -2078,7 +2165,7 @@ static void nf_tables_chain_notify(const struct nft_ctx *ctx, int event, err = nf_tables_fill_chain_info(skb, ctx->net, ctx->portid, ctx->seq, event, flags, ctx->family, ctx->table, - ctx->chain, hook_list); + ctx->chain, hook_list, trans_hook_list); if (err < 0) { kfree_skb(skb); goto err; @@ -2124,7 +2211,7 @@ static int nf_tables_dump_chains(struct sk_buff *skb, NFT_MSG_NEWCHAIN, NLM_F_MULTI, table->family, table, - chain, NULL) < 0) + chain, NULL, NULL) < 0) goto done; nl_dump_check_consistent(cb, nlmsg_hdr(skb)); @@ -2178,7 +2265,7 @@ static int nf_tables_getchain(struct sk_buff *skb, const struct nfnl_info *info, err = nf_tables_fill_chain_info(skb2, net, NETLINK_CB(skb).portid, info->nlh->nlmsg_seq, NFT_MSG_NEWCHAIN, - 0, family, table, chain, NULL); + 0, family, table, chain, NULL, NULL); if (err < 0) goto err_fill_chain_info; @@ -2271,10 +2358,8 @@ void nf_tables_chain_destroy(struct nft_chain *chain) if (nft_base_chain_netdev(table->family, basechain->ops.hooknum)) { list_for_each_entry_safe(hook, next, - &basechain->hook_list, list) { - list_del_rcu(&hook->list); - nft_netdev_hook_free_rcu(hook); - } + &basechain->hook_list, list) + nft_netdev_hook_unlink_free_rcu(hook); } module_put(basechain->type->owner); if (rcu_access_pointer(basechain->stats)) { @@ -2343,8 +2428,12 @@ static struct nft_hook *nft_hook_list_find(struct list_head *hook_list, list_for_each_entry(hook, hook_list, list) { if (!strncmp(hook->ifname, this->ifname, - min(hook->ifnamelen, this->ifnamelen))) + min(hook->ifnamelen, this->ifnamelen))) { + if (hook->flags & NFT_HOOK_REMOVE) + continue; + return hook; + } } return NULL; @@ -2974,6 +3063,7 @@ static int nf_tables_updchain(struct nft_ctx *ctx, u8 genmask, u8 policy, list_for_each_entry(ops, &h->ops_list, list) nf_unregister_net_hook(ctx->net, ops); } + /* hook.list is on stack, no need for list_del_rcu() */ list_del(&h->list); nft_netdev_hook_free_rcu(h); } @@ -3102,6 +3192,32 @@ static int nf_tables_newchain(struct sk_buff *skb, const struct nfnl_info *info, return nf_tables_addchain(&ctx, family, policy, flags, extack); } +static int nft_trans_delhook(struct nft_hook *hook, + struct list_head *del_list) +{ + struct nft_trans_hook *trans_hook; + + trans_hook = kmalloc_obj(*trans_hook, GFP_KERNEL); + if (!trans_hook) + return -ENOMEM; + + trans_hook->hook = hook; + list_add_tail(&trans_hook->list, del_list); + hook->flags |= NFT_HOOK_REMOVE; + + return 0; +} + +static void nft_trans_delhook_abort(struct list_head *del_list) +{ + struct nft_trans_hook *trans_hook, *next; + + list_for_each_entry_safe(trans_hook, next, del_list, list) { + trans_hook->hook->flags &= ~NFT_HOOK_REMOVE; + nft_trans_hook_destroy(trans_hook); + } +} + static int nft_delchain_hook(struct nft_ctx *ctx, struct nft_base_chain *basechain, struct netlink_ext_ack *extack) @@ -3128,7 +3244,10 @@ static int nft_delchain_hook(struct nft_ctx *ctx, err = -ENOENT; goto err_chain_del_hook; } - list_move(&hook->list, &chain_del_list); + if (nft_trans_delhook(hook, &chain_del_list) < 0) { + err = -ENOMEM; + goto err_chain_del_hook; + } } trans = nft_trans_alloc_chain(ctx, NFT_MSG_DELCHAIN); @@ -3148,7 +3267,7 @@ static int nft_delchain_hook(struct nft_ctx *ctx, return 0; err_chain_del_hook: - list_splice(&chain_del_list, &basechain->hook_list); + nft_trans_delhook_abort(&chain_del_list); nft_chain_release_hook(&chain_hook); return err; @@ -8852,10 +8971,8 @@ static void __nft_unregister_flowtable_net_hooks(struct net *net, list_for_each_entry_safe(hook, next, hook_list, list) { list_for_each_entry(ops, &hook->ops_list, list) nft_unregister_flowtable_ops(net, flowtable, ops); - if (release_netdev) { - list_del(&hook->list); - nft_netdev_hook_free_rcu(hook); - } + if (release_netdev) + nft_netdev_hook_unlink_free_rcu(hook); } } @@ -8926,8 +9043,7 @@ static int nft_register_flowtable_net_hooks(struct net *net, nft_unregister_flowtable_ops(net, flowtable, ops); } - list_del_rcu(&hook->list); - nft_netdev_hook_free_rcu(hook); + nft_netdev_hook_unlink_free_rcu(hook); } return err; @@ -8937,9 +9053,25 @@ static void nft_hooks_destroy(struct list_head *hook_list) { struct nft_hook *hook, *next; - list_for_each_entry_safe(hook, next, hook_list, list) { - list_del_rcu(&hook->list); - nft_netdev_hook_free_rcu(hook); + list_for_each_entry_safe(hook, next, hook_list, list) + nft_netdev_hook_unlink_free_rcu(hook); +} + +static void nft_flowtable_unregister_trans_hook(struct net *net, + struct nft_flowtable *flowtable, + struct list_head *hook_list) +{ + struct nft_trans_hook *trans_hook, *next; + struct nf_hook_ops *ops; + struct nft_hook *hook; + + list_for_each_entry_safe(trans_hook, next, hook_list, list) { + hook = trans_hook->hook; + list_for_each_entry(ops, &hook->ops_list, list) + nft_unregister_flowtable_ops(net, flowtable, ops); + + nft_netdev_hook_unlink_free_rcu(hook); + nft_trans_hook_destroy(trans_hook); } } @@ -9028,8 +9160,7 @@ static int nft_flowtable_update(struct nft_ctx *ctx, const struct nlmsghdr *nlh, nft_unregister_flowtable_ops(ctx->net, flowtable, ops); } - list_del_rcu(&hook->list); - nft_netdev_hook_free_rcu(hook); + nft_netdev_hook_unlink_free_rcu(hook); } return err; @@ -9202,7 +9333,10 @@ static int nft_delflowtable_hook(struct nft_ctx *ctx, err = -ENOENT; goto err_flowtable_del_hook; } - list_move(&hook->list, &flowtable_del_list); + if (nft_trans_delhook(hook, &flowtable_del_list) < 0) { + err = -ENOMEM; + goto err_flowtable_del_hook; + } } trans = nft_trans_alloc(ctx, NFT_MSG_DELFLOWTABLE, @@ -9223,7 +9357,7 @@ static int nft_delflowtable_hook(struct nft_ctx *ctx, return 0; err_flowtable_del_hook: - list_splice(&flowtable_del_list, &flowtable->hook_list); + nft_trans_delhook_abort(&flowtable_del_list); nft_flowtable_hook_release(&flowtable_hook); return err; @@ -9288,8 +9422,10 @@ static int nf_tables_fill_flowtable_info(struct sk_buff *skb, struct net *net, u32 portid, u32 seq, int event, u32 flags, int family, struct nft_flowtable *flowtable, - struct list_head *hook_list) + struct list_head *hook_list, + struct list_head *trans_hook_list) { + struct nft_trans_hook *trans_hook; struct nlattr *nest, *nest_devs; struct nft_hook *hook; struct nlmsghdr *nlh; @@ -9306,7 +9442,7 @@ static int nf_tables_fill_flowtable_info(struct sk_buff *skb, struct net *net, NFTA_FLOWTABLE_PAD)) goto nla_put_failure; - if (!hook_list && + if (!hook_list && !trans_hook_list && (event == NFT_MSG_DELFLOWTABLE || event == NFT_MSG_DESTROYFLOWTABLE)) { nlmsg_end(skb, nlh); @@ -9328,13 +9464,20 @@ static int nf_tables_fill_flowtable_info(struct sk_buff *skb, struct net *net, if (!nest_devs) goto nla_put_failure; - if (!hook_list) + if (!hook_list && !trans_hook_list) hook_list = &flowtable->hook_list; - list_for_each_entry_rcu(hook, hook_list, list, - lockdep_commit_lock_is_held(net)) { - if (nft_nla_put_hook_dev(skb, hook)) - goto nla_put_failure; + if (hook_list) { + list_for_each_entry_rcu(hook, hook_list, list, + lockdep_commit_lock_is_held(net)) { + if (nft_nla_put_hook_dev(skb, hook)) + goto nla_put_failure; + } + } else if (trans_hook_list) { + list_for_each_entry(trans_hook, trans_hook_list, list) { + if (nft_nla_put_hook_dev(skb, trans_hook->hook)) + goto nla_put_failure; + } } nla_nest_end(skb, nest_devs); nla_nest_end(skb, nest); @@ -9388,7 +9531,7 @@ static int nf_tables_dump_flowtable(struct sk_buff *skb, NFT_MSG_NEWFLOWTABLE, NLM_F_MULTI | NLM_F_APPEND, table->family, - flowtable, NULL) < 0) + flowtable, NULL, NULL) < 0) goto done; nl_dump_check_consistent(cb, nlmsg_hdr(skb)); @@ -9488,7 +9631,7 @@ static int nf_tables_getflowtable(struct sk_buff *skb, err = nf_tables_fill_flowtable_info(skb2, net, NETLINK_CB(skb).portid, info->nlh->nlmsg_seq, NFT_MSG_NEWFLOWTABLE, 0, family, - flowtable, NULL); + flowtable, NULL, NULL); if (err < 0) goto err_fill_flowtable_info; @@ -9501,7 +9644,9 @@ static int nf_tables_getflowtable(struct sk_buff *skb, static void nf_tables_flowtable_notify(struct nft_ctx *ctx, struct nft_flowtable *flowtable, - struct list_head *hook_list, int event) + struct list_head *hook_list, + struct list_head *trans_hook_list, + int event) { struct nftables_pernet *nft_net = nft_pernet(ctx->net); struct sk_buff *skb; @@ -9521,7 +9666,8 @@ static void nf_tables_flowtable_notify(struct nft_ctx *ctx, err = nf_tables_fill_flowtable_info(skb, ctx->net, ctx->portid, ctx->seq, event, flags, - ctx->family, flowtable, hook_list); + ctx->family, flowtable, + hook_list, trans_hook_list); if (err < 0) { kfree_skb(skb); goto err; @@ -9535,13 +9681,8 @@ static void nf_tables_flowtable_notify(struct nft_ctx *ctx, static void nf_tables_flowtable_destroy(struct nft_flowtable *flowtable) { - struct nft_hook *hook, *next; - flowtable->data.type->free(&flowtable->data); - list_for_each_entry_safe(hook, next, &flowtable->hook_list, list) { - list_del_rcu(&hook->list); - nft_netdev_hook_free_rcu(hook); - } + nft_hooks_destroy(&flowtable->hook_list); kfree(flowtable->name); module_put(flowtable->data.type->owner); kfree(flowtable); @@ -10060,9 +10201,7 @@ static void nft_commit_release(struct nft_trans *trans) break; case NFT_MSG_DELCHAIN: case NFT_MSG_DESTROYCHAIN: - if (nft_trans_chain_update(trans)) - nft_hooks_destroy(&nft_trans_chain_hooks(trans)); - else + if (!nft_trans_chain_update(trans)) nf_tables_chain_destroy(nft_trans_chain(trans)); break; case NFT_MSG_DELRULE: @@ -10083,9 +10222,7 @@ static void nft_commit_release(struct nft_trans *trans) break; case NFT_MSG_DELFLOWTABLE: case NFT_MSG_DESTROYFLOWTABLE: - if (nft_trans_flowtable_update(trans)) - nft_hooks_destroy(&nft_trans_flowtable_hooks(trans)); - else + if (!nft_trans_flowtable_update(trans)) nf_tables_flowtable_destroy(nft_trans_flowtable(trans)); break; } @@ -10845,31 +10982,28 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb) if (nft_trans_chain_update(trans)) { nft_chain_commit_update(nft_trans_container_chain(trans)); nf_tables_chain_notify(&ctx, NFT_MSG_NEWCHAIN, - &nft_trans_chain_hooks(trans)); - list_splice(&nft_trans_chain_hooks(trans), - &nft_trans_basechain(trans)->hook_list); + &nft_trans_chain_hooks(trans), NULL); + list_splice_rcu(&nft_trans_chain_hooks(trans), + &nft_trans_basechain(trans)->hook_list); /* trans destroyed after rcu grace period */ } else { nft_chain_commit_drop_policy(nft_trans_container_chain(trans)); nft_clear(net, nft_trans_chain(trans)); - nf_tables_chain_notify(&ctx, NFT_MSG_NEWCHAIN, NULL); + nf_tables_chain_notify(&ctx, NFT_MSG_NEWCHAIN, NULL, NULL); nft_trans_destroy(trans); } break; case NFT_MSG_DELCHAIN: case NFT_MSG_DESTROYCHAIN: if (nft_trans_chain_update(trans)) { - nf_tables_chain_notify(&ctx, NFT_MSG_DELCHAIN, + nf_tables_chain_notify(&ctx, NFT_MSG_DELCHAIN, NULL, &nft_trans_chain_hooks(trans)); - if (!(table->flags & NFT_TABLE_F_DORMANT)) { - nft_netdev_unregister_hooks(net, - &nft_trans_chain_hooks(trans), - true); - } + nft_netdev_unregister_trans_hook(net, table, + &nft_trans_chain_hooks(trans)); } else { nft_chain_del(nft_trans_chain(trans)); nf_tables_chain_notify(&ctx, NFT_MSG_DELCHAIN, - NULL); + NULL, NULL); nf_tables_unregister_hook(ctx.net, ctx.table, nft_trans_chain(trans)); } @@ -10975,14 +11109,16 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb) nf_tables_flowtable_notify(&ctx, nft_trans_flowtable(trans), &nft_trans_flowtable_hooks(trans), + NULL, NFT_MSG_NEWFLOWTABLE); - list_splice(&nft_trans_flowtable_hooks(trans), - &nft_trans_flowtable(trans)->hook_list); + list_splice_rcu(&nft_trans_flowtable_hooks(trans), + &nft_trans_flowtable(trans)->hook_list); } else { nft_clear(net, nft_trans_flowtable(trans)); nf_tables_flowtable_notify(&ctx, nft_trans_flowtable(trans), NULL, + NULL, NFT_MSG_NEWFLOWTABLE); } nft_trans_destroy(trans); @@ -10992,16 +11128,18 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb) if (nft_trans_flowtable_update(trans)) { nf_tables_flowtable_notify(&ctx, nft_trans_flowtable(trans), + NULL, &nft_trans_flowtable_hooks(trans), trans->msg_type); - nft_unregister_flowtable_net_hooks(net, - nft_trans_flowtable(trans), - &nft_trans_flowtable_hooks(trans)); + nft_flowtable_unregister_trans_hook(net, + nft_trans_flowtable(trans), + &nft_trans_flowtable_hooks(trans)); } else { list_del_rcu(&nft_trans_flowtable(trans)->list); nf_tables_flowtable_notify(&ctx, nft_trans_flowtable(trans), NULL, + NULL, trans->msg_type); nft_unregister_flowtable_net_hooks(net, nft_trans_flowtable(trans), @@ -11165,8 +11303,7 @@ static int __nf_tables_abort(struct net *net, enum nfnl_abort_action action) case NFT_MSG_DELCHAIN: case NFT_MSG_DESTROYCHAIN: if (nft_trans_chain_update(trans)) { - list_splice(&nft_trans_chain_hooks(trans), - &nft_trans_basechain(trans)->hook_list); + nft_trans_delhook_abort(&nft_trans_chain_hooks(trans)); } else { nft_use_inc_restore(&table->use); nft_clear(trans->net, nft_trans_chain(trans)); @@ -11280,8 +11417,7 @@ static int __nf_tables_abort(struct net *net, enum nfnl_abort_action action) case NFT_MSG_DELFLOWTABLE: case NFT_MSG_DESTROYFLOWTABLE: if (nft_trans_flowtable_update(trans)) { - list_splice(&nft_trans_flowtable_hooks(trans), - &nft_trans_flowtable(trans)->hook_list); + nft_trans_delhook_abort(&nft_trans_flowtable_hooks(trans)); } else { nft_use_inc_restore(&table->use); nft_clear(trans->net, nft_trans_flowtable(trans)); diff --git a/net/netfilter/nft_bitwise.c b/net/netfilter/nft_bitwise.c index 13808e9cd999..94dccdcfa06b 100644 --- a/net/netfilter/nft_bitwise.c +++ b/net/netfilter/nft_bitwise.c @@ -196,7 +196,8 @@ static int nft_bitwise_init_shift(struct nft_bitwise *priv, if (err < 0) return err; - if (priv->data.data[0] >= BITS_PER_TYPE(u32)) { + if (!priv->data.data[0] || + priv->data.data[0] >= BITS_PER_TYPE(u32)) { nft_data_release(&priv->data, desc.type); return -EINVAL; } diff --git a/net/netfilter/xt_policy.c b/net/netfilter/xt_policy.c index cb6e8279010a..b5fa65558318 100644 --- a/net/netfilter/xt_policy.c +++ b/net/netfilter/xt_policy.c @@ -63,7 +63,7 @@ match_policy_in(const struct sk_buff *skb, const struct xt_policy_info *info, return 0; for (i = sp->len - 1; i >= 0; i--) { - pos = strict ? i - sp->len + 1 : 0; + pos = strict ? sp->len - i - 1 : 0; if (pos >= info->len) return 0; e = &info->pol[pos]; diff --git a/net/phonet/socket.c b/net/phonet/socket.c index c4af26357144..631a99cdbd00 100644 --- a/net/phonet/socket.c +++ b/net/phonet/socket.c @@ -208,9 +208,15 @@ static int pn_socket_autobind(struct socket *sock) sa.spn_family = AF_PHONET; err = pn_socket_bind(sock, (struct sockaddr_unsized *)&sa, sizeof(struct sockaddr_pn)); - if (err != -EINVAL) + /* + * pn_socket_bind() also returns -EINVAL when sk_state != TCP_CLOSE + * without a prior bind, so -EINVAL alone is not sufficient to infer + * that the socket was already bound. Only treat it as "already + * bound" when the port is non-zero; otherwise propagate the error + * instead of crashing the kernel. + */ + if (err != -EINVAL || unlikely(!pn_port(pn_sk(sock->sk)->sobject))) return err; - BUG_ON(!pn_port(pn_sk(sock->sk)->sobject)); return 0; /* socket was already bound */ } diff --git a/net/psp/psp-nl-gen.c b/net/psp/psp-nl-gen.c index 22a48d0fa378..953309952cef 100644 --- a/net/psp/psp-nl-gen.c +++ b/net/psp/psp-nl-gen.c @@ -76,7 +76,7 @@ static const struct genl_split_ops psp_nl_ops[] = { .post_doit = psp_device_unlock, .policy = psp_dev_set_nl_policy, .maxattr = PSP_A_DEV_PSP_VERSIONS_ENA, - .flags = GENL_CMD_CAP_DO, + .flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DO, }, { .cmd = PSP_CMD_KEY_ROTATE, @@ -85,7 +85,7 @@ static const struct genl_split_ops psp_nl_ops[] = { .post_doit = psp_device_unlock, .policy = psp_key_rotate_nl_policy, .maxattr = PSP_A_DEV_ID, - .flags = GENL_CMD_CAP_DO, + .flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DO, }, { .cmd = PSP_CMD_RX_ASSOC, diff --git a/net/psp/psp_nl.c b/net/psp/psp_nl.c index 6afd7707ec12..0cc744a6e1c9 100644 --- a/net/psp/psp_nl.c +++ b/net/psp/psp_nl.c @@ -305,8 +305,13 @@ int psp_assoc_device_get_locked(const struct genl_split_ops *ops, psd = psp_dev_get_for_sock(socket->sk); if (psd) { - err = psp_dev_check_access(psd, genl_info_net(info)); - if (err) { + /* Extra care needed here, psp_dev_get_for_sock() only gives + * us access to struct psp_dev's memory, which is quite weak. + */ + mutex_lock(&psd->lock); + if (!psp_dev_is_registered(psd) || + psp_dev_check_access(psd, genl_info_net(info))) { + mutex_unlock(&psd->lock); psp_dev_put(psd); psd = NULL; } @@ -319,7 +324,6 @@ int psp_assoc_device_get_locked(const struct genl_split_ops *ops, id = info->attrs[PSP_A_ASSOC_DEV_ID]; if (psd) { - mutex_lock(&psd->lock); if (id && psd->id != nla_get_u32(id)) { mutex_unlock(&psd->lock); NL_SET_ERR_MSG_ATTR(info->extack, id, diff --git a/net/sched/sch_cake.c b/net/sched/sch_cake.c index 02e1fa4577ae..13c6d1869a14 100644 --- a/net/sched/sch_cake.c +++ b/net/sched/sch_cake.c @@ -813,7 +813,7 @@ static u32 cake_hash(struct cake_tin_data *q, const struct sk_buff *skb, i++, k = (k + 1) % CAKE_SET_WAYS) { if (q->tags[outer_hash + k] == flow_hash) { if (i) - q->way_hits++; + WRITE_ONCE(q->way_hits, q->way_hits + 1); if (!q->flows[outer_hash + k].set) { /* need to increment host refcnts */ @@ -831,7 +831,7 @@ static u32 cake_hash(struct cake_tin_data *q, const struct sk_buff *skb, for (i = 0; i < CAKE_SET_WAYS; i++, k = (k + 1) % CAKE_SET_WAYS) { if (!q->flows[outer_hash + k].set) { - q->way_misses++; + WRITE_ONCE(q->way_misses, q->way_misses + 1); allocate_src = cake_dsrc(flow_mode); allocate_dst = cake_ddst(flow_mode); goto found; @@ -841,7 +841,7 @@ static u32 cake_hash(struct cake_tin_data *q, const struct sk_buff *skb, /* With no empty queues, default to the original * queue, accept the collision, update the host tags. */ - q->way_collisions++; + WRITE_ONCE(q->way_collisions, q->way_collisions + 1); allocate_src = cake_dsrc(flow_mode); allocate_dst = cake_ddst(flow_mode); @@ -1379,9 +1379,9 @@ static u32 cake_calc_overhead(struct cake_sched_data *qd, u32 len, u32 off) len -= off; if (qd->max_netlen < len) - qd->max_netlen = len; + WRITE_ONCE(qd->max_netlen, len); if (qd->min_netlen > len) - qd->min_netlen = len; + WRITE_ONCE(qd->min_netlen, len); len += q->rate_overhead; @@ -1401,9 +1401,9 @@ static u32 cake_calc_overhead(struct cake_sched_data *qd, u32 len, u32 off) } if (qd->max_adjlen < len) - qd->max_adjlen = len; + WRITE_ONCE(qd->max_adjlen, len); if (qd->min_adjlen > len) - qd->min_adjlen = len; + WRITE_ONCE(qd->min_adjlen, len); return len; } @@ -1416,7 +1416,7 @@ static u32 cake_overhead(struct cake_sched_data *q, const struct sk_buff *skb) u16 segs = qdisc_pkt_segs(skb); u32 len = qdisc_pkt_len(skb); - q->avg_netoff = cake_ewma(q->avg_netoff, off << 16, 8); + WRITE_ONCE(q->avg_netoff, cake_ewma(q->avg_netoff, off << 16, 8)); if (segs == 1) return cake_calc_overhead(q, len, off); @@ -1590,16 +1590,17 @@ static unsigned int cake_drop(struct Qdisc *sch, struct sk_buff **to_free) } if (cobalt_queue_full(&flow->cvars, &b->cparams, now)) - b->unresponsive_flow_count++; + WRITE_ONCE(b->unresponsive_flow_count, + b->unresponsive_flow_count + 1); len = qdisc_pkt_len(skb); q->buffer_used -= skb->truesize; b->backlogs[idx] -= len; - b->tin_backlog -= len; + WRITE_ONCE(b->tin_backlog, b->tin_backlog - len); sch->qstats.backlog -= len; flow->dropped++; - b->tin_dropped++; + WRITE_ONCE(b->tin_dropped, b->tin_dropped + 1); if (q->config->rate_flags & CAKE_FLAG_INGRESS) cake_advance_shaper(q, b, skb, now, true); @@ -1795,7 +1796,7 @@ static s32 cake_enqueue(struct sk_buff *skb, struct Qdisc *sch, } if (unlikely(len > b->max_skblen)) - b->max_skblen = len; + WRITE_ONCE(b->max_skblen, len); if (qdisc_pkt_segs(skb) > 1 && q->config->rate_flags & CAKE_FLAG_SPLIT_GSO) { struct sk_buff *segs, *nskb; @@ -1819,15 +1820,15 @@ static s32 cake_enqueue(struct sk_buff *skb, struct Qdisc *sch, numsegs++; slen += segs->len; q->buffer_used += segs->truesize; - b->packets++; + WRITE_ONCE(b->packets, b->packets + 1); } /* stats */ - b->bytes += slen; b->backlogs[idx] += slen; - b->tin_backlog += slen; sch->qstats.backlog += slen; q->avg_window_bytes += slen; + WRITE_ONCE(b->bytes, b->bytes + slen); + WRITE_ONCE(b->tin_backlog, b->tin_backlog + slen); qdisc_tree_reduce_backlog(sch, 1-numsegs, len-slen); consume_skb(skb); @@ -1843,10 +1844,10 @@ static s32 cake_enqueue(struct sk_buff *skb, struct Qdisc *sch, ack = cake_ack_filter(q, flow); if (ack) { - b->ack_drops++; + WRITE_ONCE(b->ack_drops, b->ack_drops + 1); sch->qstats.drops++; ack_pkt_len = qdisc_pkt_len(ack); - b->bytes += ack_pkt_len; + WRITE_ONCE(b->bytes, b->bytes + ack_pkt_len); q->buffer_used += skb->truesize - ack->truesize; if (q->config->rate_flags & CAKE_FLAG_INGRESS) cake_advance_shaper(q, b, ack, now, true); @@ -1859,12 +1860,12 @@ static s32 cake_enqueue(struct sk_buff *skb, struct Qdisc *sch, } /* stats */ - b->packets++; - b->bytes += len - ack_pkt_len; + WRITE_ONCE(b->packets, b->packets + 1); b->backlogs[idx] += len - ack_pkt_len; - b->tin_backlog += len - ack_pkt_len; sch->qstats.backlog += len - ack_pkt_len; q->avg_window_bytes += len - ack_pkt_len; + WRITE_ONCE(b->bytes, b->bytes + len - ack_pkt_len); + WRITE_ONCE(b->tin_backlog, b->tin_backlog + len - ack_pkt_len); } if (q->overflow_timeout) @@ -1894,9 +1895,9 @@ static s32 cake_enqueue(struct sk_buff *skb, struct Qdisc *sch, u64 b = q->avg_window_bytes * (u64)NSEC_PER_SEC; b = div64_u64(b, window_interval); - q->avg_peak_bandwidth = - cake_ewma(q->avg_peak_bandwidth, b, - b > q->avg_peak_bandwidth ? 2 : 8); + WRITE_ONCE(q->avg_peak_bandwidth, + cake_ewma(q->avg_peak_bandwidth, b, + b > q->avg_peak_bandwidth ? 2 : 8)); q->avg_window_bytes = 0; q->avg_window_begin = now; @@ -1917,11 +1918,11 @@ static s32 cake_enqueue(struct sk_buff *skb, struct Qdisc *sch, if (!flow->set) { list_add_tail(&flow->flowchain, &b->new_flows); } else { - b->decaying_flow_count--; + WRITE_ONCE(b->decaying_flow_count, b->decaying_flow_count - 1); list_move_tail(&flow->flowchain, &b->new_flows); } flow->set = CAKE_SET_SPARSE; - b->sparse_flow_count++; + WRITE_ONCE(b->sparse_flow_count, b->sparse_flow_count + 1); flow->deficit = cake_get_flow_quantum(b, flow, q->config->flow_mode); } else if (flow->set == CAKE_SET_SPARSE_WAIT) { @@ -1929,15 +1930,15 @@ static s32 cake_enqueue(struct sk_buff *skb, struct Qdisc *sch, * in the bulk rotation. */ flow->set = CAKE_SET_BULK; - b->sparse_flow_count--; - b->bulk_flow_count++; + WRITE_ONCE(b->sparse_flow_count, b->sparse_flow_count - 1); + WRITE_ONCE(b->bulk_flow_count, b->bulk_flow_count + 1); cake_inc_srchost_bulk_flow_count(b, flow, q->config->flow_mode); cake_inc_dsthost_bulk_flow_count(b, flow, q->config->flow_mode); } if (q->buffer_used > q->buffer_max_used) - q->buffer_max_used = q->buffer_used; + WRITE_ONCE(q->buffer_max_used, q->buffer_used); if (q->buffer_used <= q->buffer_limit) return NET_XMIT_SUCCESS; @@ -1977,7 +1978,7 @@ static struct sk_buff *cake_dequeue_one(struct Qdisc *sch) skb = dequeue_head(flow); len = qdisc_pkt_len(skb); b->backlogs[q->cur_flow] -= len; - b->tin_backlog -= len; + WRITE_ONCE(b->tin_backlog, b->tin_backlog - len); sch->qstats.backlog -= len; q->buffer_used -= skb->truesize; sch->q.qlen--; @@ -2042,7 +2043,7 @@ static struct sk_buff *cake_dequeue(struct Qdisc *sch) cake_configure_rates(sch, new_rate, true); q->last_checked_active = now; - q->active_queues = num_active_qs; + WRITE_ONCE(q->active_queues, num_active_qs); } begin: @@ -2149,8 +2150,8 @@ static struct sk_buff *cake_dequeue(struct Qdisc *sch) */ if (flow->set == CAKE_SET_SPARSE) { if (flow->head) { - b->sparse_flow_count--; - b->bulk_flow_count++; + WRITE_ONCE(b->sparse_flow_count, b->sparse_flow_count - 1); + WRITE_ONCE(b->bulk_flow_count, b->bulk_flow_count + 1); cake_inc_srchost_bulk_flow_count(b, flow, q->config->flow_mode); cake_inc_dsthost_bulk_flow_count(b, flow, q->config->flow_mode); @@ -2177,7 +2178,8 @@ static struct sk_buff *cake_dequeue(struct Qdisc *sch) if (!skb) { /* this queue was actually empty */ if (cobalt_queue_empty(&flow->cvars, &b->cparams, now)) - b->unresponsive_flow_count--; + WRITE_ONCE(b->unresponsive_flow_count, + b->unresponsive_flow_count - 1); if (flow->cvars.p_drop || flow->cvars.count || ktime_before(now, flow->cvars.drop_next)) { @@ -2187,32 +2189,32 @@ static struct sk_buff *cake_dequeue(struct Qdisc *sch) list_move_tail(&flow->flowchain, &b->decaying_flows); if (flow->set == CAKE_SET_BULK) { - b->bulk_flow_count--; + WRITE_ONCE(b->bulk_flow_count, b->bulk_flow_count - 1); cake_dec_srchost_bulk_flow_count(b, flow, q->config->flow_mode); cake_dec_dsthost_bulk_flow_count(b, flow, q->config->flow_mode); - b->decaying_flow_count++; + WRITE_ONCE(b->decaying_flow_count, b->decaying_flow_count + 1); } else if (flow->set == CAKE_SET_SPARSE || flow->set == CAKE_SET_SPARSE_WAIT) { - b->sparse_flow_count--; - b->decaying_flow_count++; + WRITE_ONCE(b->sparse_flow_count, b->sparse_flow_count - 1); + WRITE_ONCE(b->decaying_flow_count, b->decaying_flow_count + 1); } flow->set = CAKE_SET_DECAYING; } else { /* remove empty queue from the flowchain */ list_del_init(&flow->flowchain); if (flow->set == CAKE_SET_SPARSE || - flow->set == CAKE_SET_SPARSE_WAIT) - b->sparse_flow_count--; - else if (flow->set == CAKE_SET_BULK) { - b->bulk_flow_count--; + flow->set == CAKE_SET_SPARSE_WAIT) { + WRITE_ONCE(b->sparse_flow_count, b->sparse_flow_count - 1); + } else if (flow->set == CAKE_SET_BULK) { + WRITE_ONCE(b->bulk_flow_count, b->bulk_flow_count - 1); cake_dec_srchost_bulk_flow_count(b, flow, q->config->flow_mode); cake_dec_dsthost_bulk_flow_count(b, flow, q->config->flow_mode); - } else - b->decaying_flow_count--; - + } else { + WRITE_ONCE(b->decaying_flow_count, b->decaying_flow_count - 1); + } flow->set = CAKE_SET_NONE; } goto begin; @@ -2234,7 +2236,7 @@ static struct sk_buff *cake_dequeue(struct Qdisc *sch) b->tin_deficit -= len; } flow->dropped++; - b->tin_dropped++; + WRITE_ONCE(b->tin_dropped, b->tin_dropped + 1); qdisc_tree_reduce_backlog(sch, 1, qdisc_pkt_len(skb)); qdisc_qstats_drop(sch); qdisc_dequeue_drop(sch, skb, reason); @@ -2242,17 +2244,19 @@ static struct sk_buff *cake_dequeue(struct Qdisc *sch) goto retry; } - b->tin_ecn_mark += !!flow->cvars.ecn_marked; + WRITE_ONCE(b->tin_ecn_mark, b->tin_ecn_mark + !!flow->cvars.ecn_marked); qdisc_bstats_update(sch, skb); WRITE_ONCE(q->last_active, now); /* collect delay stats */ delay = ktime_to_ns(ktime_sub(now, cobalt_get_enqueue_time(skb))); - b->avge_delay = cake_ewma(b->avge_delay, delay, 8); - b->peak_delay = cake_ewma(b->peak_delay, delay, - delay > b->peak_delay ? 2 : 8); - b->base_delay = cake_ewma(b->base_delay, delay, - delay < b->base_delay ? 2 : 8); + WRITE_ONCE(b->avge_delay, cake_ewma(b->avge_delay, delay, 8)); + WRITE_ONCE(b->peak_delay, + cake_ewma(b->peak_delay, delay, + delay > b->peak_delay ? 2 : 8)); + WRITE_ONCE(b->base_delay, + cake_ewma(b->base_delay, delay, + delay < b->base_delay ? 2 : 8)); len = cake_advance_shaper(q, b, skb, now, false); flow->deficit -= len; @@ -2329,9 +2333,9 @@ static void cake_set_rate(struct cake_tin_data *b, u64 rate, u32 mtu, u8 rate_shft = 0; u64 rate_ns = 0; - b->flow_quantum = 1514; if (rate) { - b->flow_quantum = max(min(rate >> 12, 1514ULL), 300ULL); + WRITE_ONCE(b->flow_quantum, + max(min(rate >> 12, 1514ULL), 300ULL)); rate_shft = 34; rate_ns = ((u64)NSEC_PER_SEC) << rate_shft; rate_ns = div64_u64(rate_ns, max(MIN_RATE, rate)); @@ -2339,9 +2343,11 @@ static void cake_set_rate(struct cake_tin_data *b, u64 rate, u32 mtu, rate_ns >>= 1; rate_shft--; } - } /* else unlimited, ie. zero delay */ - - b->tin_rate_bps = rate; + } else { + /* else unlimited, ie. zero delay */ + WRITE_ONCE(b->flow_quantum, 1514); + } + WRITE_ONCE(b->tin_rate_bps, rate); b->tin_rate_ns = rate_ns; b->tin_rate_shft = rate_shft; @@ -2350,10 +2356,11 @@ static void cake_set_rate(struct cake_tin_data *b, u64 rate, u32 mtu, byte_target_ns = (byte_target * rate_ns) >> rate_shft; - b->cparams.target = max((byte_target_ns * 3) / 2, target_ns); - b->cparams.interval = max(rtt_est_ns + - b->cparams.target - target_ns, - b->cparams.target * 2); + WRITE_ONCE(b->cparams.target, + max((byte_target_ns * 3) / 2, target_ns)); + WRITE_ONCE(b->cparams.interval, + max(rtt_est_ns + b->cparams.target - target_ns, + b->cparams.target * 2)); b->cparams.mtu_time = byte_target_ns; b->cparams.p_inc = 1 << 24; /* 1/256 */ b->cparams.p_dec = 1 << 20; /* 1/4096 */ @@ -2611,25 +2618,27 @@ static void cake_reconfigure(struct Qdisc *sch) { struct cake_sched_data *qd = qdisc_priv(sch); struct cake_sched_config *q = qd->config; + u32 buffer_limit; cake_configure_rates(sch, qd->config->rate_bps, false); if (q->buffer_config_limit) { - qd->buffer_limit = q->buffer_config_limit; + buffer_limit = q->buffer_config_limit; } else if (q->rate_bps) { u64 t = q->rate_bps * q->interval; do_div(t, USEC_PER_SEC / 4); - qd->buffer_limit = max_t(u32, t, 4U << 20); + buffer_limit = max_t(u32, t, 4U << 20); } else { - qd->buffer_limit = ~0; + buffer_limit = ~0; } sch->flags &= ~TCQ_F_CAN_BYPASS; - qd->buffer_limit = min(qd->buffer_limit, - max(sch->limit * psched_mtu(qdisc_dev(sch)), - q->buffer_config_limit)); + WRITE_ONCE(qd->buffer_limit, + min(buffer_limit, + max(sch->limit * psched_mtu(qdisc_dev(sch)), + q->buffer_config_limit))); } static int cake_config_change(struct cake_sched_config *q, struct nlattr *opt, @@ -2774,10 +2783,10 @@ static int cake_change(struct Qdisc *sch, struct nlattr *opt, return ret; if (overhead_changed) { - qd->max_netlen = 0; - qd->max_adjlen = 0; - qd->min_netlen = ~0; - qd->min_adjlen = ~0; + WRITE_ONCE(qd->max_netlen, 0); + WRITE_ONCE(qd->max_adjlen, 0); + WRITE_ONCE(qd->min_netlen, ~0); + WRITE_ONCE(qd->min_adjlen, ~0); } if (qd->tins) { @@ -2995,15 +3004,15 @@ static int cake_dump_stats(struct Qdisc *sch, struct gnet_dump *d) goto nla_put_failure; \ } while (0) - PUT_STAT_U64(CAPACITY_ESTIMATE64, q->avg_peak_bandwidth); - PUT_STAT_U32(MEMORY_LIMIT, q->buffer_limit); - PUT_STAT_U32(MEMORY_USED, q->buffer_max_used); - PUT_STAT_U32(AVG_NETOFF, ((q->avg_netoff + 0x8000) >> 16)); - PUT_STAT_U32(MAX_NETLEN, q->max_netlen); - PUT_STAT_U32(MAX_ADJLEN, q->max_adjlen); - PUT_STAT_U32(MIN_NETLEN, q->min_netlen); - PUT_STAT_U32(MIN_ADJLEN, q->min_adjlen); - PUT_STAT_U32(ACTIVE_QUEUES, q->active_queues); + PUT_STAT_U64(CAPACITY_ESTIMATE64, READ_ONCE(q->avg_peak_bandwidth)); + PUT_STAT_U32(MEMORY_LIMIT, READ_ONCE(q->buffer_limit)); + PUT_STAT_U32(MEMORY_USED, READ_ONCE(q->buffer_max_used)); + PUT_STAT_U32(AVG_NETOFF, ((READ_ONCE(q->avg_netoff) + 0x8000) >> 16)); + PUT_STAT_U32(MAX_NETLEN, READ_ONCE(q->max_netlen)); + PUT_STAT_U32(MAX_ADJLEN, READ_ONCE(q->max_adjlen)); + PUT_STAT_U32(MIN_NETLEN, READ_ONCE(q->min_netlen)); + PUT_STAT_U32(MIN_ADJLEN, READ_ONCE(q->min_adjlen)); + PUT_STAT_U32(ACTIVE_QUEUES, READ_ONCE(q->active_queues)); #undef PUT_STAT_U32 #undef PUT_STAT_U64 @@ -3029,38 +3038,38 @@ static int cake_dump_stats(struct Qdisc *sch, struct gnet_dump *d) if (!ts) goto nla_put_failure; - PUT_TSTAT_U64(THRESHOLD_RATE64, b->tin_rate_bps); - PUT_TSTAT_U64(SENT_BYTES64, b->bytes); - PUT_TSTAT_U32(BACKLOG_BYTES, b->tin_backlog); + PUT_TSTAT_U64(THRESHOLD_RATE64, READ_ONCE(b->tin_rate_bps)); + PUT_TSTAT_U64(SENT_BYTES64, READ_ONCE(b->bytes)); + PUT_TSTAT_U32(BACKLOG_BYTES, READ_ONCE(b->tin_backlog)); PUT_TSTAT_U32(TARGET_US, - ktime_to_us(ns_to_ktime(b->cparams.target))); + ktime_to_us(ns_to_ktime(READ_ONCE(b->cparams.target)))); PUT_TSTAT_U32(INTERVAL_US, - ktime_to_us(ns_to_ktime(b->cparams.interval))); + ktime_to_us(ns_to_ktime(READ_ONCE(b->cparams.interval)))); - PUT_TSTAT_U32(SENT_PACKETS, b->packets); - PUT_TSTAT_U32(DROPPED_PACKETS, b->tin_dropped); - PUT_TSTAT_U32(ECN_MARKED_PACKETS, b->tin_ecn_mark); - PUT_TSTAT_U32(ACKS_DROPPED_PACKETS, b->ack_drops); + PUT_TSTAT_U32(SENT_PACKETS, READ_ONCE(b->packets)); + PUT_TSTAT_U32(DROPPED_PACKETS, READ_ONCE(b->tin_dropped)); + PUT_TSTAT_U32(ECN_MARKED_PACKETS, READ_ONCE(b->tin_ecn_mark)); + PUT_TSTAT_U32(ACKS_DROPPED_PACKETS, READ_ONCE(b->ack_drops)); PUT_TSTAT_U32(PEAK_DELAY_US, - ktime_to_us(ns_to_ktime(b->peak_delay))); + ktime_to_us(ns_to_ktime(READ_ONCE(b->peak_delay)))); PUT_TSTAT_U32(AVG_DELAY_US, - ktime_to_us(ns_to_ktime(b->avge_delay))); + ktime_to_us(ns_to_ktime(READ_ONCE(b->avge_delay)))); PUT_TSTAT_U32(BASE_DELAY_US, - ktime_to_us(ns_to_ktime(b->base_delay))); + ktime_to_us(ns_to_ktime(READ_ONCE(b->base_delay)))); - PUT_TSTAT_U32(WAY_INDIRECT_HITS, b->way_hits); - PUT_TSTAT_U32(WAY_MISSES, b->way_misses); - PUT_TSTAT_U32(WAY_COLLISIONS, b->way_collisions); + PUT_TSTAT_U32(WAY_INDIRECT_HITS, READ_ONCE(b->way_hits)); + PUT_TSTAT_U32(WAY_MISSES, READ_ONCE(b->way_misses)); + PUT_TSTAT_U32(WAY_COLLISIONS, READ_ONCE(b->way_collisions)); - PUT_TSTAT_U32(SPARSE_FLOWS, b->sparse_flow_count + - b->decaying_flow_count); - PUT_TSTAT_U32(BULK_FLOWS, b->bulk_flow_count); - PUT_TSTAT_U32(UNRESPONSIVE_FLOWS, b->unresponsive_flow_count); - PUT_TSTAT_U32(MAX_SKBLEN, b->max_skblen); + PUT_TSTAT_U32(SPARSE_FLOWS, READ_ONCE(b->sparse_flow_count) + + READ_ONCE(b->decaying_flow_count)); + PUT_TSTAT_U32(BULK_FLOWS, READ_ONCE(b->bulk_flow_count)); + PUT_TSTAT_U32(UNRESPONSIVE_FLOWS, READ_ONCE(b->unresponsive_flow_count)); + PUT_TSTAT_U32(MAX_SKBLEN, READ_ONCE(b->max_skblen)); - PUT_TSTAT_U32(FLOW_QUANTUM, b->flow_quantum); + PUT_TSTAT_U32(FLOW_QUANTUM, READ_ONCE(b->flow_quantum)); nla_nest_end(d->skb, ts); } @@ -3298,10 +3307,10 @@ static int cake_mq_change(struct Qdisc *sch, struct nlattr *opt, struct cake_sched_data *qd = qdisc_priv(chld); if (overhead_changed) { - qd->max_netlen = 0; - qd->max_adjlen = 0; - qd->min_netlen = ~0; - qd->min_adjlen = ~0; + WRITE_ONCE(qd->max_netlen, 0); + WRITE_ONCE(qd->max_adjlen, 0); + WRITE_ONCE(qd->min_netlen, ~0); + WRITE_ONCE(qd->min_adjlen, ~0); } if (qd->tins) { diff --git a/net/sched/sch_choke.c b/net/sched/sch_choke.c index 94df8e741a97..2875bcdb18a4 100644 --- a/net/sched/sch_choke.c +++ b/net/sched/sch_choke.c @@ -229,7 +229,7 @@ static int choke_enqueue(struct sk_buff *skb, struct Qdisc *sch, /* Draw a packet at random from queue and compare flow */ if (choke_match_random(q, skb, &idx)) { - q->stats.matched++; + WRITE_ONCE(q->stats.matched, q->stats.matched + 1); choke_drop_by_idx(sch, idx, to_free); goto congestion_drop; } @@ -241,11 +241,13 @@ static int choke_enqueue(struct sk_buff *skb, struct Qdisc *sch, qdisc_qstats_overlimit(sch); if (use_harddrop(q) || !use_ecn(q) || !INET_ECN_set_ce(skb)) { - q->stats.forced_drop++; + WRITE_ONCE(q->stats.forced_drop, + q->stats.forced_drop + 1); goto congestion_drop; } - q->stats.forced_mark++; + WRITE_ONCE(q->stats.forced_mark, + q->stats.forced_mark + 1); } else if (++q->vars.qcount) { if (red_mark_probability(p, &q->vars, q->vars.qavg)) { q->vars.qcount = 0; @@ -253,11 +255,13 @@ static int choke_enqueue(struct sk_buff *skb, struct Qdisc *sch, qdisc_qstats_overlimit(sch); if (!use_ecn(q) || !INET_ECN_set_ce(skb)) { - q->stats.prob_drop++; + WRITE_ONCE(q->stats.prob_drop, + q->stats.prob_drop + 1); goto congestion_drop; } - q->stats.prob_mark++; + WRITE_ONCE(q->stats.prob_mark, + q->stats.prob_mark + 1); } } else q->vars.qR = red_random(p); @@ -272,7 +276,7 @@ static int choke_enqueue(struct sk_buff *skb, struct Qdisc *sch, return NET_XMIT_SUCCESS; } - q->stats.pdrop++; + WRITE_ONCE(q->stats.pdrop, q->stats.pdrop + 1); return qdisc_drop(skb, sch, to_free); congestion_drop: @@ -461,10 +465,12 @@ static int choke_dump_stats(struct Qdisc *sch, struct gnet_dump *d) { struct choke_sched_data *q = qdisc_priv(sch); struct tc_choke_xstats st = { - .early = q->stats.prob_drop + q->stats.forced_drop, - .marked = q->stats.prob_mark + q->stats.forced_mark, - .pdrop = q->stats.pdrop, - .matched = q->stats.matched, + .early = READ_ONCE(q->stats.prob_drop) + + READ_ONCE(q->stats.forced_drop), + .marked = READ_ONCE(q->stats.prob_mark) + + READ_ONCE(q->stats.forced_mark), + .pdrop = READ_ONCE(q->stats.pdrop), + .matched = READ_ONCE(q->stats.matched), }; return gnet_stats_copy_app(d, &st, sizeof(st)); diff --git a/net/sched/sch_fq_pie.c b/net/sched/sch_fq_pie.c index 154c70f489f2..7becbf5362b3 100644 --- a/net/sched/sch_fq_pie.c +++ b/net/sched/sch_fq_pie.c @@ -509,18 +509,19 @@ static int fq_pie_dump(struct Qdisc *sch, struct sk_buff *skb) static int fq_pie_dump_stats(struct Qdisc *sch, struct gnet_dump *d) { struct fq_pie_sched_data *q = qdisc_priv(sch); - struct tc_fq_pie_xstats st = { - .packets_in = q->stats.packets_in, - .overlimit = q->stats.overlimit, - .overmemory = q->overmemory, - .dropped = q->stats.dropped, - .ecn_mark = q->stats.ecn_mark, - .new_flow_count = q->new_flow_count, - .memory_usage = q->memory_usage, - }; + struct tc_fq_pie_xstats st = { 0 }; struct list_head *pos; sch_tree_lock(sch); + + st.packets_in = q->stats.packets_in; + st.overlimit = q->stats.overlimit; + st.overmemory = q->overmemory; + st.dropped = q->stats.dropped; + st.ecn_mark = q->stats.ecn_mark; + st.new_flow_count = q->new_flow_count; + st.memory_usage = q->memory_usage; + list_for_each(pos, &q->new_flows) st.new_flows_len++; diff --git a/net/sched/sch_netem.c b/net/sched/sch_netem.c index 20df1c08b1e9..bc18e1976b6e 100644 --- a/net/sched/sch_netem.c +++ b/net/sched/sch_netem.c @@ -227,10 +227,10 @@ static bool loss_4state(struct netem_sched_data *q) if (rnd < clg->a4) { clg->state = LOST_IN_GAP_PERIOD; return true; - } else if (clg->a4 < rnd && rnd < clg->a1 + clg->a4) { + } else if (rnd < clg->a1 + clg->a4) { clg->state = LOST_IN_BURST_PERIOD; return true; - } else if (clg->a1 + clg->a4 < rnd) { + } else { clg->state = TX_IN_GAP_PERIOD; } @@ -247,9 +247,9 @@ static bool loss_4state(struct netem_sched_data *q) case LOST_IN_BURST_PERIOD: if (rnd < clg->a3) clg->state = TX_IN_BURST_PERIOD; - else if (clg->a3 < rnd && rnd < clg->a2 + clg->a3) { + else if (rnd < clg->a2 + clg->a3) { clg->state = TX_IN_GAP_PERIOD; - } else if (clg->a2 + clg->a3 < rnd) { + } else { clg->state = LOST_IN_BURST_PERIOD; return true; } @@ -524,7 +524,7 @@ static int netem_enqueue(struct sk_buff *skb, struct Qdisc *sch, 1 << get_random_u32_below(8); } - if (unlikely(q->t_len >= sch->limit)) { + if (unlikely(sch->q.qlen >= sch->limit)) { /* re-link segs, so that qdisc_drop_all() frees them all */ skb->next = segs; qdisc_drop_all(skb, sch, to_free); @@ -659,9 +659,8 @@ static void get_slot_next(struct netem_sched_data *q, u64 now) if (!q->slot_dist) next_delay = q->slot_config.min_delay + - (get_random_u32() * - (q->slot_config.max_delay - - q->slot_config.min_delay) >> 32); + mul_u64_u32_shr(q->slot_config.max_delay - q->slot_config.min_delay, + get_random_u32(), 32); else next_delay = tabledist(q->slot_config.dist_delay, (s32)(q->slot_config.dist_jitter), @@ -827,6 +826,39 @@ static int get_dist_table(struct disttable **tbl, const struct nlattr *attr) return 0; } +static int validate_time(const struct nlattr *attr, const char *name, + struct netlink_ext_ack *extack) +{ + if (nla_get_s64(attr) < 0) { + NL_SET_ERR_MSG_ATTR_FMT(extack, attr, "negative %s", name); + return -EINVAL; + } + return 0; +} + +static int validate_slot(const struct nlattr *attr, struct netlink_ext_ack *extack) +{ + const struct tc_netem_slot *c = nla_data(attr); + + if (c->min_delay < 0 || c->max_delay < 0) { + NL_SET_ERR_MSG_ATTR(extack, attr, "negative slot delay"); + return -EINVAL; + } + if (c->min_delay > c->max_delay) { + NL_SET_ERR_MSG_ATTR(extack, attr, "slot min delay greater than max delay"); + return -EINVAL; + } + if (c->dist_delay < 0 || c->dist_jitter < 0) { + NL_SET_ERR_MSG_ATTR(extack, attr, "negative dist delay"); + return -EINVAL; + } + if (c->max_packets < 0 || c->max_bytes < 0) { + NL_SET_ERR_MSG_ATTR(extack, attr, "negative slot limit"); + return -EINVAL; + } + return 0; +} + static void get_slot(struct netem_sched_data *q, const struct nlattr *attr) { const struct tc_netem_slot *c = nla_data(attr); @@ -1040,6 +1072,24 @@ static int netem_change(struct Qdisc *sch, struct nlattr *opt, goto table_free; } + if (tb[TCA_NETEM_SLOT]) { + ret = validate_slot(tb[TCA_NETEM_SLOT], extack); + if (ret) + goto table_free; + } + + if (tb[TCA_NETEM_LATENCY64]) { + ret = validate_time(tb[TCA_NETEM_LATENCY64], "latency", extack); + if (ret) + goto table_free; + } + + if (tb[TCA_NETEM_JITTER64]) { + ret = validate_time(tb[TCA_NETEM_JITTER64], "jitter", extack); + if (ret) + goto table_free; + } + sch_tree_lock(sch); /* backup q->clg and q->loss_model */ old_clg = q->clg; @@ -1112,11 +1162,10 @@ static int netem_change(struct Qdisc *sch, struct nlattr *opt, /* capping jitter to the range acceptable by tabledist() */ q->jitter = min_t(s64, abs(q->jitter), INT_MAX); - if (tb[TCA_NETEM_PRNG_SEED]) + if (tb[TCA_NETEM_PRNG_SEED]) { q->prng.seed = nla_get_u64(tb[TCA_NETEM_PRNG_SEED]); - else - q->prng.seed = get_random_u64(); - prandom_seed_state(&q->prng.prng_state, q->prng.seed); + prandom_seed_state(&q->prng.prng_state, q->prng.seed); + } unlock: sch_tree_unlock(sch); @@ -1139,6 +1188,9 @@ static int netem_init(struct Qdisc *sch, struct nlattr *opt, return -EINVAL; q->loss_model = CLG_RANDOM; + q->prng.seed = get_random_u64(); + prandom_seed_state(&q->prng.prng_state, q->prng.seed); + ret = netem_change(sch, opt, extack); if (ret) pr_info("netem: change failed\n"); diff --git a/net/sched/sch_taprio.c b/net/sched/sch_taprio.c index a47a09d76400..45245157e00a 100644 --- a/net/sched/sch_taprio.c +++ b/net/sched/sch_taprio.c @@ -634,7 +634,7 @@ static int taprio_enqueue(struct sk_buff *skb, struct Qdisc *sch, queue = skb_get_queue_mapping(skb); child = q->qdiscs[queue]; - if (unlikely(!child)) + if (unlikely(child == &noop_qdisc)) return qdisc_drop(skb, sch, to_free); if (taprio_skb_exceeds_queue_max_sdu(sch, skb)) { @@ -717,7 +717,7 @@ static struct sk_buff *taprio_dequeue_from_txq(struct Qdisc *sch, int txq, int len; u8 tc; - if (unlikely(!child)) + if (unlikely(child == &noop_qdisc)) return NULL; if (TXTIME_ASSIST_IS_ENABLED(q->flags)) @@ -2184,6 +2184,9 @@ static int taprio_graft(struct Qdisc *sch, unsigned long cl, if (!dev_queue) return -EINVAL; + if (!new) + new = &noop_qdisc; + if (dev->flags & IFF_UP) dev_deactivate(dev, false); @@ -2197,14 +2200,14 @@ static int taprio_graft(struct Qdisc *sch, unsigned long cl, *old = q->qdiscs[cl - 1]; if (FULL_OFFLOAD_IS_ENABLED(q->flags)) { WARN_ON_ONCE(dev_graft_qdisc(dev_queue, new) != *old); - if (new) + if (new != &noop_qdisc) qdisc_refcount_inc(new); - if (*old) + if (*old && *old != &noop_qdisc) qdisc_put(*old); } q->qdiscs[cl - 1] = new; - if (new) + if (new != &noop_qdisc) new->flags |= TCQ_F_ONETXQUEUE | TCQ_F_NOPARENT; if (dev->flags & IFF_UP) diff --git a/net/sctp/sm_statefuns.c b/net/sctp/sm_statefuns.c index 7b823d759141..8e89a870780c 100644 --- a/net/sctp/sm_statefuns.c +++ b/net/sctp/sm_statefuns.c @@ -1556,6 +1556,12 @@ static enum sctp_disposition sctp_sf_do_unexpected_init( /* Tag the variable length parameters. */ chunk->param_hdr.v = skb_pull(chunk->skb, sizeof(struct sctp_inithdr)); + if (asoc->state >= SCTP_STATE_ESTABLISHED) { + /* Discard INIT matching peer vtag after handshake completion (stale INIT). */ + if (ntohl(chunk->subh.init_hdr->init_tag) == asoc->peer.i.init_tag) + return sctp_sf_pdiscard(net, ep, asoc, type, arg, commands); + } + /* Verify the INIT chunk before processing it. */ err_chunk = NULL; if (!sctp_verify_init(net, ep, asoc, chunk->chunk_hdr->type, diff --git a/net/tls/tls.h b/net/tls/tls.h index e8f81a006520..12f44cb649c9 100644 --- a/net/tls/tls.h +++ b/net/tls/tls.h @@ -188,6 +188,7 @@ int tls_strp_dev_init(void); void tls_strp_dev_exit(void); void tls_strp_done(struct tls_strparser *strp); +void __tls_strp_done(struct tls_strparser *strp); void tls_strp_stop(struct tls_strparser *strp); int tls_strp_init(struct tls_strparser *strp, struct sock *sk); void tls_strp_data_ready(struct tls_strparser *strp); diff --git a/net/tls/tls_strp.c b/net/tls/tls_strp.c index 98e12f0ff57e..c72e88317627 100644 --- a/net/tls/tls_strp.c +++ b/net/tls/tls_strp.c @@ -624,6 +624,12 @@ void tls_strp_done(struct tls_strparser *strp) WARN_ON(!strp->stopped); cancel_work_sync(&strp->work); + __tls_strp_done(strp); +} + +/* For setup error paths where the strparser was initialized but never armed. */ +void __tls_strp_done(struct tls_strparser *strp) +{ tls_strp_anchor_free(strp); } diff --git a/net/tls/tls_sw.c b/net/tls/tls_sw.c index 94d2ae0daa8c..798243eabb1f 100644 --- a/net/tls/tls_sw.c +++ b/net/tls/tls_sw.c @@ -2624,8 +2624,12 @@ void tls_sw_free_ctx_rx(struct tls_context *tls_ctx) void tls_sw_free_resources_rx(struct sock *sk) { struct tls_context *tls_ctx = tls_get_ctx(sk); + struct tls_sw_context_rx *ctx; + + ctx = tls_sw_ctx_rx(tls_ctx); tls_sw_release_resources_rx(sk); + __tls_strp_done(&ctx->strp); tls_sw_free_ctx_rx(tls_ctx); } diff --git a/net/vmw_vsock/hyperv_transport.c b/net/vmw_vsock/hyperv_transport.c index f862988c1e86..7a8963595bf9 100644 --- a/net/vmw_vsock/hyperv_transport.c +++ b/net/vmw_vsock/hyperv_transport.c @@ -375,10 +375,10 @@ static void hvs_open_connection(struct vmbus_channel *chan) } else { sndbuf = max_t(int, sk->sk_sndbuf, RINGBUFFER_HVS_SND_SIZE); sndbuf = min_t(int, sndbuf, RINGBUFFER_HVS_MAX_SIZE); - sndbuf = ALIGN(sndbuf, HV_HYP_PAGE_SIZE); + sndbuf = VMBUS_RING_SIZE(sndbuf); rcvbuf = max_t(int, sk->sk_rcvbuf, RINGBUFFER_HVS_RCV_SIZE); rcvbuf = min_t(int, rcvbuf, RINGBUFFER_HVS_MAX_SIZE); - rcvbuf = ALIGN(rcvbuf, HV_HYP_PAGE_SIZE); + rcvbuf = VMBUS_RING_SIZE(rcvbuf); } chan->max_pkt_size = HVS_MAX_PKT_SIZE; diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c index 97801966bf32..0f704380a8c8 100644 --- a/security/selinux/hooks.c +++ b/security/selinux/hooks.c @@ -2966,7 +2966,7 @@ static int selinux_inode_init_security(struct inode *inode, struct inode *dir, { const struct cred_security_struct *crsec = selinux_cred(current_cred()); struct superblock_security_struct *sbsec; - struct xattr *xattr = lsm_get_xattr_slot(xattrs, xattr_count); + struct xattr *xattr; u32 newsid, clen; u16 newsclass; int rc; @@ -2992,6 +2992,7 @@ static int selinux_inode_init_security(struct inode *inode, struct inode *dir, !(sbsec->flags & SBLABEL_MNT)) return -EOPNOTSUPP; + xattr = lsm_get_xattr_slot(xattrs, xattr_count); if (xattr) { rc = security_sid_to_context_force(newsid, &context, &clen); @@ -3208,15 +3209,13 @@ static inline int task_avdcache_search(struct task_security_struct *tsec, * @tsec: the task's security state * @isec: the inode associated with the cache entry * @avd: the AVD to cache - * @audited: the permission audit bitmask to cache * - * Update the AVD cache in @tsec with the @avdc and @audited info associated + * Update the AVD cache in @tsec with the @avd info associated * with @isec. */ static inline void task_avdcache_update(struct task_security_struct *tsec, struct inode_security_struct *isec, - struct av_decision *avd, - u32 audited) + struct av_decision *avd) { int spot; @@ -3228,9 +3227,7 @@ static inline void task_avdcache_update(struct task_security_struct *tsec, spot = (tsec->avdcache.dir_spot + 1) & (TSEC_AVDC_DIR_SIZE - 1); tsec->avdcache.dir_spot = spot; tsec->avdcache.dir[spot].isid = isec->sid; - tsec->avdcache.dir[spot].audited = audited; - tsec->avdcache.dir[spot].allowed = avd->allowed; - tsec->avdcache.dir[spot].permissive = avd->flags & AVD_FLAGS_PERMISSIVE; + tsec->avdcache.dir[spot].avd = *avd; tsec->avdcache.permissive_neveraudit = (avd->flags == (AVD_FLAGS_PERMISSIVE|AVD_FLAGS_NEVERAUDIT)); } @@ -3251,6 +3248,7 @@ static int selinux_inode_permission(struct inode *inode, int requested) struct task_security_struct *tsec; struct inode_security_struct *isec; struct avdc_entry *avdc; + struct av_decision avd, *avdp = &avd; int rc, rc2; u32 audited, denied; @@ -3272,23 +3270,21 @@ static int selinux_inode_permission(struct inode *inode, int requested) rc = task_avdcache_search(tsec, isec, &avdc); if (likely(!rc)) { /* Cache hit. */ - audited = perms & avdc->audited; - denied = perms & ~avdc->allowed; - if (unlikely(denied && enforcing_enabled() && - !avdc->permissive)) + avdp = &avdc->avd; + denied = perms & ~avdp->allowed; + if (unlikely(denied) && enforcing_enabled() && + !(avdp->flags & AVD_FLAGS_PERMISSIVE)) rc = -EACCES; } else { - struct av_decision avd; - /* Cache miss. */ rc = avc_has_perm_noaudit(sid, isec->sid, isec->sclass, - perms, 0, &avd); - audited = avc_audit_required(perms, &avd, rc, - (requested & MAY_ACCESS) ? FILE__AUDIT_ACCESS : 0, - &denied); - task_avdcache_update(tsec, isec, &avd, audited); + perms, 0, avdp); + task_avdcache_update(tsec, isec, avdp); } + audited = avc_audit_required(perms, avdp, rc, + (requested & MAY_ACCESS) ? + FILE__AUDIT_ACCESS : 0, &denied); if (likely(!audited)) return rc; @@ -4920,7 +4916,7 @@ static bool sock_skip_has_perm(u32 sid) static int sock_has_perm(struct sock *sk, u32 perms) { - struct sk_security_struct *sksec = sk->sk_security; + struct sk_security_struct *sksec = selinux_sock(sk); struct common_audit_data ad; struct lsm_network_audit net; @@ -6227,7 +6223,7 @@ static unsigned int selinux_ip_postroute(void *priv, static int nlmsg_sock_has_extended_perms(struct sock *sk, u32 perms, u16 nlmsg_type) { - struct sk_security_struct *sksec = sk->sk_security; + struct sk_security_struct *sksec = selinux_sock(sk); struct common_audit_data ad; u8 driver; u8 xperm; diff --git a/security/selinux/include/objsec.h b/security/selinux/include/objsec.h index b19e5d978e82..3c0a16ec978b 100644 --- a/security/selinux/include/objsec.h +++ b/security/selinux/include/objsec.h @@ -32,9 +32,7 @@ struct avdc_entry { u32 isid; /* inode SID */ - u32 allowed; /* allowed permission bitmask */ - u32 audited; /* audited permission bitmask */ - bool permissive; /* AVC permissive flag */ + struct av_decision avd; /* av decision */ }; struct cred_security_struct { diff --git a/sound/core/oss/pcm_oss.c b/sound/core/oss/pcm_oss.c index a140a0d9abb8..33fd34f0d615 100644 --- a/sound/core/oss/pcm_oss.c +++ b/sound/core/oss/pcm_oss.c @@ -2155,10 +2155,16 @@ static int snd_pcm_oss_get_trigger(struct snd_pcm_oss_file *pcm_oss_file) psubstream = pcm_oss_file->streams[SNDRV_PCM_STREAM_PLAYBACK]; csubstream = pcm_oss_file->streams[SNDRV_PCM_STREAM_CAPTURE]; - if (psubstream && psubstream->runtime && psubstream->runtime->oss.trigger) - result |= PCM_ENABLE_OUTPUT; - if (csubstream && csubstream->runtime && csubstream->runtime->oss.trigger) - result |= PCM_ENABLE_INPUT; + if (psubstream && psubstream->runtime) { + guard(mutex)(&psubstream->runtime->oss.params_lock); + if (psubstream->runtime->oss.trigger) + result |= PCM_ENABLE_OUTPUT; + } + if (csubstream && csubstream->runtime) { + guard(mutex)(&csubstream->runtime->oss.params_lock); + if (csubstream->runtime->oss.trigger) + result |= PCM_ENABLE_INPUT; + } return result; } @@ -2832,6 +2838,17 @@ static int snd_pcm_oss_capture_ready(struct snd_pcm_substream *substream) runtime->oss.period_frames; } +static bool need_input_retrigger(struct snd_pcm_runtime *runtime) +{ + bool ret; + + guard(mutex)(&runtime->oss.params_lock); + ret = runtime->oss.trigger; + if (ret) + runtime->oss.trigger = 0; + return ret; +} + static __poll_t snd_pcm_oss_poll(struct file *file, poll_table * wait) { struct snd_pcm_oss_file *pcm_oss_file; @@ -2864,11 +2881,11 @@ static __poll_t snd_pcm_oss_poll(struct file *file, poll_table * wait) snd_pcm_oss_capture_ready(csubstream)) mask |= EPOLLIN | EPOLLRDNORM; } - if (ostate != SNDRV_PCM_STATE_RUNNING && runtime->oss.trigger) { + if (ostate != SNDRV_PCM_STATE_RUNNING && + need_input_retrigger(runtime)) { struct snd_pcm_oss_file ofile; memset(&ofile, 0, sizeof(ofile)); ofile.streams[SNDRV_PCM_STREAM_CAPTURE] = pcm_oss_file->streams[SNDRV_PCM_STREAM_CAPTURE]; - runtime->oss.trigger = 0; snd_pcm_oss_set_trigger(&ofile, PCM_ENABLE_INPUT); } } diff --git a/sound/drivers/aloop.c b/sound/drivers/aloop.c index aa0d2fcb1a18..a37a1695f51c 100644 --- a/sound/drivers/aloop.c +++ b/sound/drivers/aloop.c @@ -99,6 +99,9 @@ struct loopback_ops { struct loopback_cable { spinlock_t lock; struct loopback_pcm *streams[2]; + /* in-flight peer stops running outside cable->lock */ + atomic_t stop_count; + wait_queue_head_t stop_wait; struct snd_pcm_hardware hw; /* flags */ unsigned int valid; @@ -366,8 +369,11 @@ static int loopback_check_format(struct loopback_cable *cable, int stream) return 0; if (stream == SNDRV_PCM_STREAM_CAPTURE) return -EIO; - else if (cruntime->state == SNDRV_PCM_STATE_RUNNING) + else if (cruntime->state == SNDRV_PCM_STATE_RUNNING) { + /* close must not free the peer runtime below */ + atomic_inc(&cable->stop_count); stop_capture = true; + } } setup = get_setup(dpcm_play); @@ -396,8 +402,11 @@ static int loopback_check_format(struct loopback_cable *cable, int stream) } } - if (stop_capture) + if (stop_capture) { snd_pcm_stop(dpcm_capt->substream, SNDRV_PCM_STATE_DRAINING); + if (atomic_dec_and_test(&cable->stop_count)) + wake_up(&cable->stop_wait); + } return 0; } @@ -1049,23 +1058,29 @@ static void free_cable(struct snd_pcm_substream *substream) struct loopback *loopback = substream->private_data; int dev = get_cable_index(substream); struct loopback_cable *cable; + struct loopback_pcm *dpcm; + bool other_alive; cable = loopback->cables[substream->number][dev]; if (!cable) return; - if (cable->streams[!substream->stream]) { - /* other stream is still alive */ - guard(spinlock_irq)(&cable->lock); - cable->streams[substream->stream] = NULL; - } else { - struct loopback_pcm *dpcm = substream->runtime->private_data; - if (cable->ops && cable->ops->close_cable && dpcm) - cable->ops->close_cable(dpcm); - /* free the cable */ - loopback->cables[substream->number][dev] = NULL; - kfree(cable); + scoped_guard(spinlock_irq, &cable->lock) { + cable->streams[substream->stream] = NULL; + other_alive = cable->streams[!substream->stream]; } + + /* Pair with the stop_count increment in loopback_check_format(). */ + wait_event(cable->stop_wait, !atomic_read(&cable->stop_count)); + if (other_alive) + return; + + dpcm = substream->runtime->private_data; + if (cable->ops && cable->ops->close_cable && dpcm) + cable->ops->close_cable(dpcm); + /* free the cable */ + loopback->cables[substream->number][dev] = NULL; + kfree(cable); } static int loopback_jiffies_timer_open(struct loopback_pcm *dpcm) @@ -1260,6 +1275,8 @@ static int loopback_open(struct snd_pcm_substream *substream) goto unlock; } spin_lock_init(&cable->lock); + atomic_set(&cable->stop_count, 0); + init_waitqueue_head(&cable->stop_wait); cable->hw = loopback_pcm_hardware; if (loopback->timer_source) cable->ops = &loopback_snd_timer_ops; diff --git a/sound/hda/codecs/Makefile b/sound/hda/codecs/Makefile index e7f03e281999..88d2f8a79467 100644 --- a/sound/hda/codecs/Makefile +++ b/sound/hda/codecs/Makefile @@ -7,7 +7,6 @@ snd-hda-codec-cm9825-y := cm9825.o snd-hda-codec-analog-y := analog.o snd-hda-codec-ca0110-y := ca0110.o snd-hda-codec-ca0132-y := ca0132.o -snd-hda-codec-cmedia-y := cmedia.o snd-hda-codec-conexant-y := conexant.o snd-hda-codec-idt-y := sigmatel.o snd-hda-codec-senarytech-y := senarytech.o @@ -26,7 +25,6 @@ obj-$(CONFIG_SND_HDA_CODEC_CM9825) += snd-hda-codec-cm9825.o obj-$(CONFIG_SND_HDA_CODEC_ANALOG) += snd-hda-codec-analog.o obj-$(CONFIG_SND_HDA_CODEC_CA0110) += snd-hda-codec-ca0110.o obj-$(CONFIG_SND_HDA_CODEC_CA0132) += snd-hda-codec-ca0132.o -obj-$(CONFIG_SND_HDA_CODEC_CMEDIA) += snd-hda-codec-cmedia.o obj-$(CONFIG_SND_HDA_CODEC_CONEXANT) += snd-hda-codec-conexant.o obj-$(CONFIG_SND_HDA_CODEC_SIGMATEL) += snd-hda-codec-idt.o obj-$(CONFIG_SND_HDA_CODEC_SENARYTECH) += snd-hda-codec-senarytech.o diff --git a/sound/hda/codecs/conexant.c b/sound/hda/codecs/conexant.c index 3a9717df39b4..e3b6aaabe3a9 100644 --- a/sound/hda/codecs/conexant.c +++ b/sound/hda/codecs/conexant.c @@ -1175,6 +1175,7 @@ static void add_cx5051_fake_mutes(struct hda_codec *codec) static int cx_probe(struct hda_codec *codec, const struct hda_device_id *id) { struct conexant_spec *spec; + struct hda_jack_callback *callback; int err; codec_info(codec, "%s: BIOS auto-probing.\n", codec->core.chip_name); @@ -1190,7 +1191,12 @@ static int cx_probe(struct hda_codec *codec, const struct hda_device_id *id) case 0x14f11f86: case 0x14f11f87: spec->is_cx11880_sn6140 = true; - snd_hda_jack_detect_enable_callback(codec, 0x19, cx_update_headset_mic_vref); + callback = snd_hda_jack_detect_enable_callback(codec, 0x19, + cx_update_headset_mic_vref); + if (IS_ERR(callback)) { + err = PTR_ERR(callback); + goto error; + } break; } diff --git a/sound/hda/codecs/realtek/alc269.c b/sound/hda/codecs/realtek/alc269.c index d720565db4aa..a9cd03bb73c4 100644 --- a/sound/hda/codecs/realtek/alc269.c +++ b/sound/hda/codecs/realtek/alc269.c @@ -3694,6 +3694,17 @@ static void alc287_fixup_lenovo_thinkpad_with_alc1318(struct hda_codec *codec, spec->power_hook = alc287_s4_power_gpio3_default; spec->gen.pcm_playback_hook = alc287_alc1318_playback_pcm_hook; } + +static void alc287_fixup_tb_vmaster_led(struct hda_codec *codec, + const struct hda_fixup *fix, int action) +{ + struct alc_spec *spec = codec->spec; + + if (action == HDA_FIXUP_ACT_PRE_PROBE) + spec->gen.vmaster_mute_led = 1; + + alc287_fixup_bind_dacs(codec, fix, action); +} /* GPIO2: mute led GPIO3: micmute led */ static void alc245_tas2781_spi_hp_fixup_muteled(struct hda_codec *codec, const struct hda_fixup *fix, int action) @@ -6448,7 +6459,7 @@ static const struct hda_fixup alc269_fixups[] = { }, [ALC287_FIXUP_MG_RTKC_CSAMP_CS35L41_I2C_THINKPAD] = { .type = HDA_FIXUP_FUNC, - .v.func = alc287_fixup_bind_dacs, + .v.func = alc287_fixup_tb_vmaster_led, .chained = true, .chain_id = ALC287_FIXUP_CS35L41_I2C_2_THINKPAD_ACPI, }, @@ -6717,6 +6728,7 @@ static const struct hda_quirk alc269_fixup_tbl[] = { SND_PCI_QUIRK(0x1025, 0x159c, "Acer Nitro 5 AN515-58", ALC2XX_FIXUP_HEADSET_MIC), SND_PCI_QUIRK(0x1025, 0x1597, "Acer Nitro 5 AN517-55", ALC2XX_FIXUP_HEADSET_MIC), SND_PCI_QUIRK(0x1025, 0x160e, "Acer PT316-51S", ALC2XX_FIXUP_HEADSET_MIC), + SND_PCI_QUIRK(0x1025, 0x1640, "Acer Aspire A315-44P", ALC256_FIXUP_ACER_SFG16_MICMUTE_LED), SND_PCI_QUIRK(0x1025, 0x1679, "Acer Nitro 16 AN16-41", ALC2XX_FIXUP_HEADSET_MIC), SND_PCI_QUIRK(0x1025, 0x169a, "Acer Swift SFG16", ALC256_FIXUP_ACER_SFG16_MICMUTE_LED), SND_PCI_QUIRK(0x1025, 0x171e, "Acer Nitro ANV15-51", ALC245_FIXUP_ACER_MICMUTE_LED), diff --git a/sound/hda/codecs/side-codecs/cs35l56_hda.c b/sound/hda/codecs/side-codecs/cs35l56_hda.c index 1ace4beef508..4c8d01799931 100644 --- a/sound/hda/codecs/side-codecs/cs35l56_hda.c +++ b/sound/hda/codecs/side-codecs/cs35l56_hda.c @@ -180,11 +180,15 @@ static int cs35l56_hda_mixer_get(struct snd_kcontrol *kcontrol, { struct cs35l56_hda *cs35l56 = snd_kcontrol_chip(kcontrol); unsigned int reg_val; - int i; + int i, ret; cs35l56_hda_wait_dsp_ready(cs35l56); - regmap_read(cs35l56->base.regmap, kcontrol->private_value, ®_val); + ret = regmap_read(cs35l56->base.regmap, kcontrol->private_value, + ®_val); + if (ret) + return ret; + reg_val &= CS35L56_ASP_TXn_SRC_MASK; for (i = 0; i < CS35L56_NUM_INPUT_SRC; ++i) { @@ -203,15 +207,20 @@ static int cs35l56_hda_mixer_put(struct snd_kcontrol *kcontrol, struct cs35l56_hda *cs35l56 = snd_kcontrol_chip(kcontrol); unsigned int item = ucontrol->value.enumerated.item[0]; bool changed; + int ret; if (item >= CS35L56_NUM_INPUT_SRC) return -EINVAL; cs35l56_hda_wait_dsp_ready(cs35l56); - regmap_update_bits_check(cs35l56->base.regmap, kcontrol->private_value, - CS35L56_INPUT_MASK, cs35l56_tx_input_values[item], - &changed); + ret = regmap_update_bits_check(cs35l56->base.regmap, + kcontrol->private_value, + CS35L56_INPUT_MASK, + cs35l56_tx_input_values[item], + &changed); + if (ret) + return ret; return changed; } @@ -967,6 +976,7 @@ static int cs35l56_hda_system_resume(struct device *dev) static int cs35l56_hda_fixup_yoga9(struct cs35l56_hda *cs35l56, int *bus_addr) { /* The cirrus,dev-index property has the wrong values */ + cs35l56->num_amps = 2; switch (*bus_addr) { case 0x30: cs35l56->index = 1; @@ -1016,7 +1026,6 @@ static int cs35l56_hda_read_acpi(struct cs35l56_hda *cs35l56, int hid, int id) char hid_string[8]; struct acpi_device *adev; const char *property, *sub; - size_t nval; int i, ret; /* @@ -1052,13 +1061,14 @@ static int cs35l56_hda_read_acpi(struct cs35l56_hda *cs35l56, int hid, int id) ret = -EINVAL; goto err; } - nval = ret; + cs35l56->num_amps = ret; - ret = device_property_read_u32_array(cs35l56->base.dev, property, values, nval); + ret = device_property_read_u32_array(cs35l56->base.dev, property, values, + cs35l56->num_amps); if (ret) goto err; - for (i = 0; i < nval; i++) { + for (i = 0; i < cs35l56->num_amps; i++) { if (values[i] == id) { cs35l56->index = i; break; @@ -1081,7 +1091,8 @@ static int cs35l56_hda_read_acpi(struct cs35l56_hda *cs35l56, int hid, int id) "Read ACPI _SUB failed(%ld): fallback to generic firmware\n", PTR_ERR(sub)); } else { - ret = cirrus_scodec_get_speaker_id(cs35l56->base.dev, cs35l56->index, nval, -1); + ret = cirrus_scodec_get_speaker_id(cs35l56->base.dev, cs35l56->index, + cs35l56->num_amps, -1); if (ret == -ENOENT) { cs35l56->system_name = sub; } else if (ret >= 0) { diff --git a/sound/hda/codecs/side-codecs/cs35l56_hda.h b/sound/hda/codecs/side-codecs/cs35l56_hda.h index cb4b5e7356a3..3705af7c186b 100644 --- a/sound/hda/codecs/side-codecs/cs35l56_hda.h +++ b/sound/hda/codecs/side-codecs/cs35l56_hda.h @@ -26,6 +26,7 @@ struct cs35l56_hda { struct work_struct dsp_work; int index; + int num_amps; const char *system_name; const char *amp_name; diff --git a/sound/hda/codecs/side-codecs/tas2781_hda_spi.c b/sound/hda/codecs/side-codecs/tas2781_hda_spi.c index 560f2385212d..0e4f3553f273 100644 --- a/sound/hda/codecs/side-codecs/tas2781_hda_spi.c +++ b/sound/hda/codecs/side-codecs/tas2781_hda_spi.c @@ -132,10 +132,18 @@ static int tasdevice_spi_dev_update_bits(struct tasdevice_priv *tas_priv, int ret, val; /* - * In our TAS2781 SPI mode, read/write was masked in last bit of - * address, it cause regmap_update_bits() not work as expected. + * In TAS2781 SPI mode, when accessing non-book-zero or page numbers + * greater than 1 in book 0, an additional byte must be read. The + * first byte in such cases is a dummy byte and should be ignored. */ - ret = tasdevice_dev_read(tas_priv, chn, reg, &val); + if ((TASDEVICE_BOOK_ID(reg) > 0) || (TASDEVICE_PAGE_ID(reg) > 1)) { + unsigned char buf[2]; + + ret = tasdevice_dev_bulk_read(tas_priv, chn, reg, buf, 2); + val = buf[1]; + } else { + ret = tasdevice_dev_read(tas_priv, chn, reg, &val); + } if (ret < 0) { dev_err(tas_priv->dev, "%s, E=%d\n", __func__, ret); return ret; diff --git a/sound/hda/core/hdmi_chmap.c b/sound/hda/core/hdmi_chmap.c index 7b276047f85a..c897fc443467 100644 --- a/sound/hda/core/hdmi_chmap.c +++ b/sound/hda/core/hdmi_chmap.c @@ -353,13 +353,16 @@ static void hdmi_std_setup_channel_mapping(struct hdac_chmap *chmap, if (hdmi_channel_mapping[ca][1] == 0) { int hdmi_slot = 0; /* fill actual channel mappings in ALSA channel (i) order */ - for (i = 0; i < ch_alloc->channels; i++) { - while (!WARN_ON(hdmi_slot >= 8) && - !ch_alloc->speakers[7 - hdmi_slot]) - hdmi_slot++; /* skip zero slots */ + for (i = 0; i < ch_alloc->channels && hdmi_slot < 8; i++) { + while (!ch_alloc->speakers[7 - hdmi_slot]) { + /* skip zero slots */ + if (++hdmi_slot >= 8) + goto out; + } hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++; } + out: /* fill the rest of the slots with ALSA channel 0xf */ for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) if (!ch_alloc->speakers[7 - hdmi_slot]) diff --git a/sound/soc/amd/acp/acp-legacy-mach.c b/sound/soc/amd/acp/acp-legacy-mach.c index a7a551366a40..235d6cc83fa9 100644 --- a/sound/soc/amd/acp/acp-legacy-mach.c +++ b/sound/soc/amd/acp/acp-legacy-mach.c @@ -174,7 +174,7 @@ static int acp_asoc_probe(struct platform_device *pdev) acp_card_drvdata->acp_rev = mach->mach_params.subsystem_rev; dmi_id = dmi_first_match(acp_quirk_table); - if (dmi_id && dmi_id->driver_data) + if (dmi_id && dmi_id->driver_data == (void *)QUIRK_TDM_MODE_ENABLE) acp_card_drvdata->tdm_mode = dmi_id->driver_data; ret = acp_legacy_dai_links_create(card); diff --git a/sound/soc/amd/acp/acp-mach-common.c b/sound/soc/amd/acp/acp-mach-common.c index 09f6c9a2c041..ef784cca13f2 100644 --- a/sound/soc/amd/acp/acp-mach-common.c +++ b/sound/soc/amd/acp/acp-mach-common.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "../../codecs/rt5682.h" #include "../../codecs/rt1019.h" @@ -37,15 +38,21 @@ #define NAU8821_FREQ_OUT 12288000 #define MAX98388_CODEC_DAI "max98388-aif1" -#define TDM_MODE_ENABLE 1 - const struct dmi_system_id acp_quirk_table[] = { { /* Google skyrim proto-0 */ .matches = { DMI_EXACT_MATCH(DMI_PRODUCT_FAMILY, "Google_Skyrim"), }, - .driver_data = (void *)TDM_MODE_ENABLE, + .driver_data = (void *)QUIRK_TDM_MODE_ENABLE, + }, + { + /* Valve Steam Deck OLED */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Valve"), + DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"), + }, + .driver_data = (void *)QUIRK_REMAP_DMIC_BT, }, {} }; @@ -1401,6 +1408,7 @@ int acp_sofdsp_dai_links_create(struct snd_soc_card *card) struct snd_soc_dai_link *links; struct device *dev = card->dev; struct acp_card_drvdata *drv_data = card->drvdata; + const struct dmi_system_id *dmi_id = dmi_first_match(acp_quirk_table); int i = 0, num_links = 0; if (drv_data->hs_cpu_id) @@ -1572,6 +1580,9 @@ int acp_sofdsp_dai_links_create(struct snd_soc_card *card) links[i].codecs = &snd_soc_dummy_dlc; links[i].num_codecs = 1; } + + if (dmi_id && dmi_id->driver_data == (void *)QUIRK_REMAP_DMIC_BT) + links[i].id = DMIC_BE_ID; i++; } @@ -1587,6 +1598,11 @@ int acp_sofdsp_dai_links_create(struct snd_soc_card *card) links[i].capture_only = 1; links[i].nonatomic = true; links[i].no_pcm = 1; + + if (dmi_id && dmi_id->driver_data == (void *)QUIRK_REMAP_DMIC_BT) { + links[i].id = BT_BE_ID; + dev_dbg(dev, "quirk REMAP_DMIC_BT enabled\n"); + } } card->dai_link = links; diff --git a/sound/soc/amd/acp/acp-mach.h b/sound/soc/amd/acp/acp-mach.h index f94c30c20f20..7177d3fd9619 100644 --- a/sound/soc/amd/acp/acp-mach.h +++ b/sound/soc/amd/acp/acp-mach.h @@ -26,6 +26,10 @@ #define acp_get_drvdata(card) ((struct acp_card_drvdata *)(card)->drvdata) +/* List of DMI quirks - check acp-mach-common.c for usage. */ +#define QUIRK_TDM_MODE_ENABLE 1 +#define QUIRK_REMAP_DMIC_BT 2 + enum be_id { HEADSET_BE_ID = 0, AMP_BE_ID, diff --git a/sound/soc/amd/acp/acp-sof-mach.c b/sound/soc/amd/acp/acp-sof-mach.c index 6215e31ecedd..36ecef7013b9 100644 --- a/sound/soc/amd/acp/acp-sof-mach.c +++ b/sound/soc/amd/acp/acp-sof-mach.c @@ -110,7 +110,7 @@ static int acp_sof_probe(struct platform_device *pdev) acp_card_drvdata = card->drvdata; dmi_id = dmi_first_match(acp_quirk_table); - if (dmi_id && dmi_id->driver_data) + if (dmi_id && dmi_id->driver_data == (void *)QUIRK_TDM_MODE_ENABLE) acp_card_drvdata->tdm_mode = dmi_id->driver_data; acp_card_drvdata->acp_rev = mach->mach_params.subsystem_rev; diff --git a/sound/soc/codecs/ab8500-codec.c b/sound/soc/codecs/ab8500-codec.c index fdda1b747bf7..8ab2e60f80b4 100644 --- a/sound/soc/codecs/ab8500-codec.c +++ b/sound/soc/codecs/ab8500-codec.c @@ -2496,13 +2496,13 @@ static int ab8500_codec_probe(struct snd_soc_component *component) return status; } fc = (struct filter_control *) - &ab8500_filter_controls[AB8500_FILTER_ANC_FIR].private_value; + ab8500_filter_controls[AB8500_FILTER_ANC_FIR].private_value; drvdata->anc_fir_values = (long *)fc->value; fc = (struct filter_control *) - &ab8500_filter_controls[AB8500_FILTER_ANC_IIR].private_value; + ab8500_filter_controls[AB8500_FILTER_ANC_IIR].private_value; drvdata->anc_iir_values = (long *)fc->value; fc = (struct filter_control *) - &ab8500_filter_controls[AB8500_FILTER_SID_FIR].private_value; + ab8500_filter_controls[AB8500_FILTER_SID_FIR].private_value; drvdata->sid_fir_values = (long *)fc->value; snd_soc_dapm_disable_pin(dapm, "ANC Configure Input"); diff --git a/sound/soc/codecs/aw88395/aw88395.c b/sound/soc/codecs/aw88395/aw88395.c index 3602b5b9f7d7..dd09bac652f7 100644 --- a/sound/soc/codecs/aw88395/aw88395.c +++ b/sound/soc/codecs/aw88395/aw88395.c @@ -456,8 +456,6 @@ static void aw88395_hw_reset(struct aw88395 *aw88395) usleep_range(AW88395_1000_US, AW88395_1000_US + 10); gpiod_set_value_cansleep(aw88395->reset_gpio, 1); usleep_range(AW88395_1000_US, AW88395_1000_US + 10); - } else { - dev_err(aw88395->aw_pa->dev, "%s failed", __func__); } } @@ -522,9 +520,10 @@ static int aw88395_i2c_probe(struct i2c_client *i2c) i2c_set_clientdata(i2c, aw88395); aw88395->reset_gpio = devm_gpiod_get_optional(&i2c->dev, "reset", GPIOD_OUT_LOW); - if (IS_ERR(aw88395->reset_gpio)) - dev_info(&i2c->dev, "reset gpio not defined\n"); - + if (IS_ERR(aw88395->reset_gpio)) { + return dev_err_probe(&i2c->dev, PTR_ERR(aw88395->reset_gpio), + "failed to get reset gpio\n"); + } /* hardware reset */ aw88395_hw_reset(aw88395); diff --git a/sound/soc/codecs/cs35l56-shared.c b/sound/soc/codecs/cs35l56-shared.c index e05d975ba794..033e56d5e9db 100644 --- a/sound/soc/codecs/cs35l56-shared.c +++ b/sound/soc/codecs/cs35l56-shared.c @@ -108,8 +108,6 @@ int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, "SND_SOC_CS35L56_SHARED"); static const struct reg_default cs35l56_reg_defaults[] = { - /* no defaults for OTP_MEM - first read populates cache */ - { CS35L56_ASP1_ENABLES1, 0x00000000 }, { CS35L56_ASP1_CONTROL1, 0x00000028 }, { CS35L56_ASP1_CONTROL2, 0x18180200 }, @@ -138,8 +136,6 @@ static const struct reg_default cs35l56_reg_defaults[] = { }; static const struct reg_default cs35l63_reg_defaults[] = { - /* no defaults for OTP_MEM - first read populates cache */ - { CS35L56_ASP1_ENABLES1, 0x00000000 }, { CS35L56_ASP1_CONTROL1, 0x00000028 }, { CS35L56_ASP1_CONTROL2, 0x18180200 }, @@ -282,6 +278,9 @@ static bool cs35l56_common_volatile_reg(unsigned int reg) case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ case CS35L56_BLOCK_ENABLES: /* owned by firmware */ case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ + case CS35L56_OTP_MEM_53: + case CS35L56_OTP_MEM_54: + case CS35L56_OTP_MEM_55: case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG: case CS35L56_UPDATE_REGS: case CS35L56_REFCLK_INPUT: /* owned by firmware */ diff --git a/sound/soc/codecs/es8389.c b/sound/soc/codecs/es8389.c index 8d418cae371a..449d9574b03a 100644 --- a/sound/soc/codecs/es8389.c +++ b/sound/soc/codecs/es8389.c @@ -892,7 +892,7 @@ static int es8389_probe(struct snd_soc_component *component) return ret; } - es8389->mclk = devm_clk_get(component->dev, "mclk"); + es8389->mclk = devm_clk_get_optional(component->dev, "mclk"); if (IS_ERR(es8389->mclk)) return dev_err_probe(component->dev, PTR_ERR(es8389->mclk), "ES8389 is unable to get mclk\n"); diff --git a/sound/soc/codecs/tas2764.c b/sound/soc/codecs/tas2764.c index 423b7073b302..6aab6d2b7419 100644 --- a/sound/soc/codecs/tas2764.c +++ b/sound/soc/codecs/tas2764.c @@ -904,6 +904,7 @@ static bool tas2764_volatile_register(struct device *dev, unsigned int reg) { switch (reg) { case TAS2764_SW_RST: + case TAS2764_TEMP: case TAS2764_INT_LTCH0 ... TAS2764_INT_LTCH4: case TAS2764_INT_CLK_CFG: return true; diff --git a/sound/soc/codecs/tas2770.c b/sound/soc/codecs/tas2770.c index d4d7d056141b..50501bcbe916 100644 --- a/sound/soc/codecs/tas2770.c +++ b/sound/soc/codecs/tas2770.c @@ -624,7 +624,7 @@ static int tas2770_read_die_temp(struct tas2770_priv *tas2770, long *result) /* * As per datasheet: divide register by 16 and subtract 93 to get * degrees Celsius. hwmon requires millidegrees. Let's avoid rounding - * errors by subtracting 93 * 16 then multiplying by 1000 / 16. + * errors by subtracting 93 * 16 and scaling before dividing. * * NOTE: The ADC registers are initialised to 0 on reset. This means * that the temperature will read -93 *C until the chip is brought out @@ -633,7 +633,7 @@ static int tas2770_read_die_temp(struct tas2770_priv *tas2770, long *result) * value read back from its registers will be the last value sampled * before entering software shutdown. */ - *result = (reading - (93 * 16)) * (1000 / 16); + *result = (reading - (93 * 16)) * 1000 / 16; return 0; } diff --git a/sound/soc/codecs/wcd937x.c b/sound/soc/codecs/wcd937x.c index 10a2d598caa7..72a53f95d688 100644 --- a/sound/soc/codecs/wcd937x.c +++ b/sound/soc/codecs/wcd937x.c @@ -546,6 +546,9 @@ static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(2), BIT(2)); + snd_soc_component_update_bits(component, + WCD937X_AUX_AUXPA, + BIT(4), BIT(4)); snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(2), BIT(2)); @@ -562,6 +565,9 @@ static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(2), 0x00); + snd_soc_component_update_bits(component, + WCD937X_AUX_AUXPA, + BIT(4), 0x00); break; } @@ -730,10 +736,23 @@ static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(1), BIT(1)); + /* Enable AUX PA related RX supplies */ + snd_soc_component_update_bits(component, + WCD937X_ANA_RX_SUPPLIES, + BIT(6), BIT(6)); + snd_soc_component_update_bits(component, + WCD937X_ANA_RX_SUPPLIES, + BIT(7), BIT(7)); enable_irq(wcd937x->aux_pdm_wd_int); break; case SND_SOC_DAPM_PRE_PMD: disable_irq_nosync(wcd937x->aux_pdm_wd_int); + snd_soc_component_update_bits(component, + WCD937X_ANA_RX_SUPPLIES, + BIT(6), 0x00); + snd_soc_component_update_bits(component, + WCD937X_ANA_RX_SUPPLIES, + BIT(7), 0x00); break; case SND_SOC_DAPM_POST_PMD: usleep_range(2000, 2010); @@ -2051,7 +2070,12 @@ static const struct snd_kcontrol_new wcd937x_snd_controls[] = { wcd937x_get_swr_port, wcd937x_set_swr_port), SOC_SINGLE_EXT("LO Switch", WCD937X_LO, 0, 1, 0, wcd937x_get_swr_port, wcd937x_set_swr_port), - + SOC_SINGLE_EXT("CLSH PA Switch", WCD937X_CLSH, 0, 1, 0, + wcd937x_get_swr_port, wcd937x_set_swr_port), + SOC_SINGLE_EXT("DSD_L Switch", WCD937X_DSD_L, 0, 1, 0, + wcd937x_get_swr_port, wcd937x_set_swr_port), + SOC_SINGLE_EXT("DSD_R Switch", WCD937X_DSD_R, 0, 1, 0, + wcd937x_get_swr_port, wcd937x_set_swr_port), SOC_SINGLE_EXT("ADC1 Switch", WCD937X_ADC1, 1, 1, 0, wcd937x_get_swr_port, wcd937x_set_swr_port), SOC_SINGLE_EXT("ADC2 Switch", WCD937X_ADC2, 1, 1, 0, diff --git a/sound/soc/intel/boards/bytcr_wm5102.c b/sound/soc/intel/boards/bytcr_wm5102.c index 4879f79aef29..4aa0cf49b033 100644 --- a/sound/soc/intel/boards/bytcr_wm5102.c +++ b/sound/soc/intel/boards/bytcr_wm5102.c @@ -170,6 +170,7 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w, ret = byt_wm5102_prepare_and_enable_pll1(codec_dai, 48000); if (ret) { dev_err(card->dev, "Error setting codec sysclk: %d\n", ret); + clk_disable_unprepare(priv->mclk); return ret; } } else { diff --git a/sound/soc/sof/intel/hda.c b/sound/soc/sof/intel/hda.c index b3d61d973ce4..8662b422eb80 100644 --- a/sound/soc/sof/intel/hda.c +++ b/sound/soc/sof/intel/hda.c @@ -1412,7 +1412,8 @@ static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev link_mask |= BIT(peripherals->array[i]->bus->link_id); link_num = hweight32(link_mask); - links = devm_kcalloc(sdev->dev, link_num, sizeof(*links), GFP_KERNEL); + /* An empty adr_link is needed to terminate the adr_link loop */ + links = devm_kcalloc(sdev->dev, link_num + 1, sizeof(*links), GFP_KERNEL); if (!links) return NULL; diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c index 1cb99f1abc7c..43481f387c44 100644 --- a/sound/soc/spacemit/k1_i2s.c +++ b/sound/soc/spacemit/k1_i2s.c @@ -93,8 +93,8 @@ static void spacemit_i2s_init(struct spacemit_i2s_dev *i2s) u32 sscr_val, sspsp_val, ssfcr_val, ssrwt_val; sscr_val = SSCR_TRAIL | SSCR_FRF_PSP; - ssfcr_val = FIELD_PREP(SSFCR_FIELD_TFT, 5) | - FIELD_PREP(SSFCR_FIELD_RFT, 5) | + ssfcr_val = FIELD_PREP(SSFCR_FIELD_TFT, 0xF) | + FIELD_PREP(SSFCR_FIELD_RFT, 0xF) | SSFCR_RSRE | SSFCR_TSRE; ssrwt_val = SSRWT_RWOT; sspsp_val = SSPSP_SFRMP; @@ -106,6 +106,37 @@ static void spacemit_i2s_init(struct spacemit_i2s_dev *i2s) writel(0, i2s->base + SSINTEN); } +static int spacemit_i2s_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct spacemit_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai); + + switch (i2s->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + snd_pcm_hw_constraint_minmax(substream->runtime, + SNDRV_PCM_HW_PARAM_CHANNELS, + 2, 2); + snd_pcm_hw_constraint_mask64(substream->runtime, + SNDRV_PCM_HW_PARAM_FORMAT, + SNDRV_PCM_FMTBIT_S16_LE); + break; + case SND_SOC_DAIFMT_DSP_A: + case SND_SOC_DAIFMT_DSP_B: + snd_pcm_hw_constraint_minmax(substream->runtime, + SNDRV_PCM_HW_PARAM_CHANNELS, + 1, 1); + snd_pcm_hw_constraint_mask64(substream->runtime, + SNDRV_PCM_HW_PARAM_FORMAT, + SNDRV_PCM_FMTBIT_S32_LE); + break; + default: + dev_dbg(i2s->dev, "unexpected format type"); + return -EINVAL; + } + + return 0; +} + static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -157,22 +188,9 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, dma_data->maxburst = 32; dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; } - - snd_pcm_hw_constraint_minmax(substream->runtime, - SNDRV_PCM_HW_PARAM_CHANNELS, - 1, 2); - snd_pcm_hw_constraint_mask64(substream->runtime, - SNDRV_PCM_HW_PARAM_FORMAT, - SNDRV_PCM_FMTBIT_S16_LE); break; case SND_SOC_DAIFMT_DSP_A: case SND_SOC_DAIFMT_DSP_B: - snd_pcm_hw_constraint_minmax(substream->runtime, - SNDRV_PCM_HW_PARAM_CHANNELS, - 1, 1); - snd_pcm_hw_constraint_mask64(substream->runtime, - SNDRV_PCM_HW_PARAM_FORMAT, - SNDRV_PCM_FMTBIT_S32_LE); break; default: dev_dbg(i2s->dev, "unexpected format type"); @@ -303,6 +321,7 @@ static int spacemit_i2s_dai_remove(struct snd_soc_dai *dai) static const struct snd_soc_dai_ops spacemit_i2s_dai_ops = { .probe = spacemit_i2s_dai_probe, .remove = spacemit_i2s_dai_remove, + .startup = spacemit_i2s_startup, .hw_params = spacemit_i2s_hw_params, .set_sysclk = spacemit_i2s_set_sysclk, .set_fmt = spacemit_i2s_set_fmt, diff --git a/sound/soc/tegra/Makefile b/sound/soc/tegra/Makefile index 3f396c87802e..1c18ef6971c0 100644 --- a/sound/soc/tegra/Makefile +++ b/sound/soc/tegra/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 # Tegra platform Support snd-soc-tegra-pcm-y := tegra_pcm.o -snd-soc-tegra-utils-y += tegra_asoc_utils.o snd-soc-tegra20-ac97-y := tegra20_ac97.o snd-soc-tegra20-das-y := tegra20_das.o snd-soc-tegra20-i2s-y := tegra20_i2s.o diff --git a/sound/usb/caiaq/device.c b/sound/usb/caiaq/device.c index 8af0c04041ee..b20aae0caf60 100644 --- a/sound/usb/caiaq/device.c +++ b/sound/usb/caiaq/device.c @@ -366,7 +366,7 @@ static int setup_card(struct snd_usb_caiaqdev *cdev) #ifdef CONFIG_SND_USB_CAIAQ_INPUT ret = snd_usb_caiaq_input_init(cdev); - if (ret < 0) { + if (ret < 0 && ret != -ENODEV) { dev_err(dev, "Unable to set up input system (ret=%d)\n", ret); return ret; } @@ -423,6 +423,7 @@ static int create_card(struct usb_device *usb_dev, cdev = caiaqdev(card); cdev->chip.dev = usb_get_dev(usb_dev); + card->private_free = card_free; cdev->chip.card = card; cdev->chip.usb_id = USB_ID(le16_to_cpu(usb_dev->descriptor.idVendor), le16_to_cpu(usb_dev->descriptor.idProduct)); @@ -511,10 +512,9 @@ static int init_card(struct snd_usb_caiaqdev *cdev) scnprintf(card->longname, sizeof(card->longname), "%s %s (%s)", cdev->vendor_name, cdev->product_name, usbpath); - card->private_free = card_free; err = setup_card(cdev); if (err < 0) - return err; + goto err_kill_urb; return 0; diff --git a/sound/usb/caiaq/input.c b/sound/usb/caiaq/input.c index a9130891bb69..5c70fdf61cc1 100644 --- a/sound/usb/caiaq/input.c +++ b/sound/usb/caiaq/input.c @@ -804,7 +804,7 @@ int snd_usb_caiaq_input_init(struct snd_usb_caiaqdev *cdev) default: /* no input methods supported on this device */ - ret = -EINVAL; + ret = -ENODEV; goto exit_free_idev; } diff --git a/sound/usb/misc/ua101.c b/sound/usb/misc/ua101.c index 49b3dd8d827d..d129b42eb979 100644 --- a/sound/usb/misc/ua101.c +++ b/sound/usb/misc/ua101.c @@ -974,6 +974,13 @@ static int detect_usb_format(struct ua101 *ua) ua->capture.channels = fmt_capture->bNrChannels; ua->playback.channels = fmt_playback->bNrChannels; + if (!ua->capture.channels || !ua->playback.channels) { + dev_err(&ua->dev->dev, + "invalid channel count: capture %u, playback %u\n", + ua->capture.channels, ua->playback.channels); + return -EINVAL; + } + ua->capture.frame_bytes = fmt_capture->bSubframeSize * ua->capture.channels; ua->playback.frame_bytes = diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c index 85653112e7f3..5fba456eb4a9 100644 --- a/sound/usb/mixer.c +++ b/sound/usb/mixer.c @@ -1190,6 +1190,16 @@ static void volume_control_quirks(struct usb_mixer_elem_info *cval, cval->res = 1; } break; + + case USB_ID(0x0e6f, 0x024a): /* PDP Riffmaster for PS4 */ + case USB_ID(0x0e6f, 0x0249): /* PDP Riffmaster for PS5 */ + if (!strcmp(kctl->id.name, "PCM Playback Volume")) { + usb_audio_info(chip, + "set volume quirk for PDP Riffmaster for PS4/PS5\n"); + cval->min = -2560; /* Mute under it */ + } + break; + case USB_ID(0x3302, 0x12db): /* MOONDROP Quark2 */ if (!strcmp(kctl->id.name, "PCM Playback Volume")) { usb_audio_info(chip, diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h index 803e03d4d77b..4e9cfff4047f 100644 --- a/sound/usb/quirks-table.h +++ b/sound/usb/quirks-table.h @@ -2652,6 +2652,9 @@ YAMAHA_DEVICE(0x7010, "UB99"), } } }, + +#endif /* disabled */ + { /* * The AudioBox USB advertises S24_3LE as the only supported format @@ -2700,7 +2703,6 @@ YAMAHA_DEVICE(0x7010, "UB99"), } } }, -#endif /* disabled */ { /* diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c index 7b803ad58487..0b4ecc2c6bcc 100644 --- a/sound/usb/quirks.c +++ b/sound/usb/quirks.c @@ -125,7 +125,7 @@ static int add_audio_stream_from_fixed_fmt(struct snd_usb_audio *chip, snd_usb_audioformat_set_sync_ep(chip, fp); - err = snd_usb_add_audio_stream(chip, stream, fp); + err = snd_usb_add_audio_stream(chip, stream, fp, NULL); if (err < 0) return err; diff --git a/sound/usb/stream.c b/sound/usb/stream.c index 2532bf97e05e..b2c5c8198281 100644 --- a/sound/usb/stream.c +++ b/sound/usb/stream.c @@ -79,7 +79,7 @@ static void snd_usb_audio_pcm_free(struct snd_pcm *pcm) static void snd_usb_init_substream(struct snd_usb_stream *as, int stream, struct audioformat *fp, - struct snd_usb_power_domain *pd) + struct snd_usb_power_domain **pdptr) { struct snd_usb_substream *subs = &as->substream[stream]; @@ -105,10 +105,11 @@ static void snd_usb_init_substream(struct snd_usb_stream *as, if (fp->channels > subs->channels_max) subs->channels_max = fp->channels; - if (pd) { - subs->str_pd = pd; + if (pdptr && *pdptr) { + subs->str_pd = *pdptr; + *pdptr = NULL; /* assigned */ /* Initialize Power Domain to idle status D1 */ - snd_usb_power_domain_set(subs->stream->chip, pd, + snd_usb_power_domain_set(subs->stream->chip, subs->str_pd, UAC3_PD_STATE_D1); } @@ -352,6 +353,8 @@ snd_pcm_chmap_elem *convert_chmap_v3(struct uac3_cluster_header_descriptor if (len < sizeof(*cs_desc)) break; cs_len = le16_to_cpu(cs_desc->wLength); + if (cs_len < sizeof(*cs_desc)) + break; if (len < cs_len) break; cs_type = cs_desc->bSegmentType; @@ -492,11 +495,14 @@ snd_pcm_chmap_elem *convert_chmap_v3(struct uac3_cluster_header_descriptor * if not, create a new pcm stream. note, fp is added to the substream * fmt_list and will be freed on the chip instance release. do not free * fp or do remove it from the substream fmt_list to avoid double-free. + * + * pdptr is optional and can be NULL. When it's non-NULL and the PD gets + * assigned to the stream, *pdptr is cleared to NULL upon return. */ -static int __snd_usb_add_audio_stream(struct snd_usb_audio *chip, - int stream, - struct audioformat *fp, - struct snd_usb_power_domain *pd) +int snd_usb_add_audio_stream(struct snd_usb_audio *chip, + int stream, + struct audioformat *fp, + struct snd_usb_power_domain **pdptr) { struct snd_usb_stream *as; @@ -529,7 +535,7 @@ static int __snd_usb_add_audio_stream(struct snd_usb_audio *chip, err = snd_pcm_new_stream(as->pcm, stream, 1); if (err < 0) return err; - snd_usb_init_substream(as, stream, fp, pd); + snd_usb_init_substream(as, stream, fp, pdptr); return add_chmap(as->pcm, stream, subs); } @@ -558,7 +564,7 @@ static int __snd_usb_add_audio_stream(struct snd_usb_audio *chip, else strscpy(pcm->name, "USB Audio"); - snd_usb_init_substream(as, stream, fp, pd); + snd_usb_init_substream(as, stream, fp, pdptr); /* * Keep using head insertion for M-Audio Audiophile USB (tm) which has a @@ -576,21 +582,6 @@ static int __snd_usb_add_audio_stream(struct snd_usb_audio *chip, return add_chmap(pcm, stream, &as->substream[stream]); } -int snd_usb_add_audio_stream(struct snd_usb_audio *chip, - int stream, - struct audioformat *fp) -{ - return __snd_usb_add_audio_stream(chip, stream, fp, NULL); -} - -static int snd_usb_add_audio_stream_v3(struct snd_usb_audio *chip, - int stream, - struct audioformat *fp, - struct snd_usb_power_domain *pd) -{ - return __snd_usb_add_audio_stream(chip, stream, fp, pd); -} - static int parse_uac_endpoint_attributes(struct snd_usb_audio *chip, struct usb_host_interface *alts, int protocol, int iface_no) @@ -1003,7 +994,7 @@ snd_usb_get_audioformat_uac3(struct snd_usb_audio *chip, * and request Cluster Descriptor */ wLength = le16_to_cpu(hc_header.wLength); - if (wLength < sizeof(cluster)) + if (wLength < sizeof(*cluster)) return NULL; cluster = kzalloc(wLength, GFP_KERNEL); if (!cluster) @@ -1113,8 +1104,7 @@ snd_usb_get_audioformat_uac3(struct snd_usb_audio *chip, } } - if (pd) - *pd_out = pd; + *pd_out = pd; return fp; } @@ -1129,7 +1119,6 @@ static int __snd_usb_parse_audio_interface(struct snd_usb_audio *chip, struct usb_interface_descriptor *altsd; int i, altno, err, stream; struct audioformat *fp = NULL; - struct snd_usb_power_domain *pd = NULL; bool set_iface_first; int num, protocol; @@ -1171,6 +1160,12 @@ static int __snd_usb_parse_audio_interface(struct snd_usb_audio *chip, if (snd_usb_apply_interface_quirk(chip, iface_no, altno)) continue; + /* pd may be allocated at snd_usb_get_audioformat_uac3() and + * assigned at snd_usb_add_audio_stream(); otherwise it'll be + * freed automatically by cleanup at each loop. + */ + struct snd_usb_power_domain *pd __free(kfree) = NULL; + /* * Roland audio streaming interfaces are marked with protocols * 0/1/2, but are UAC 1 compatible. @@ -1226,23 +1221,16 @@ static int __snd_usb_parse_audio_interface(struct snd_usb_audio *chip, *has_non_pcm = true; if ((fp->fmt_type == UAC_FORMAT_TYPE_I) == non_pcm) { audioformat_free(fp); - kfree(pd); fp = NULL; - pd = NULL; continue; } snd_usb_audioformat_set_sync_ep(chip, fp); dev_dbg(&dev->dev, "%u:%d: add audio endpoint %#x\n", iface_no, altno, fp->endpoint); - if (protocol == UAC_VERSION_3) - err = snd_usb_add_audio_stream_v3(chip, stream, fp, pd); - else - err = snd_usb_add_audio_stream(chip, stream, fp); - + err = snd_usb_add_audio_stream(chip, stream, fp, &pd); if (err < 0) { audioformat_free(fp); - kfree(pd); return err; } diff --git a/sound/usb/stream.h b/sound/usb/stream.h index d92e18d5818f..61b9a133da01 100644 --- a/sound/usb/stream.h +++ b/sound/usb/stream.h @@ -7,7 +7,8 @@ int snd_usb_parse_audio_interface(struct snd_usb_audio *chip, int snd_usb_add_audio_stream(struct snd_usb_audio *chip, int stream, - struct audioformat *fp); + struct audioformat *fp, + struct snd_usb_power_domain **pdptr); #endif /* __USBAUDIO_STREAM_H */ diff --git a/tools/sched_ext/scx_qmap.bpf.c b/tools/sched_ext/scx_qmap.bpf.c index b68abb9e760b..aad698fe294b 100644 --- a/tools/sched_ext/scx_qmap.bpf.c +++ b/tools/sched_ext/scx_qmap.bpf.c @@ -159,13 +159,7 @@ static s32 pick_direct_dispatch_cpu(struct task_struct *p, s32 prev_cpu) static struct task_ctx *lookup_task_ctx(struct task_struct *p) { - struct task_ctx *tctx; - - if (!(tctx = bpf_task_storage_get(&task_ctx_stor, p, 0, 0))) { - scx_bpf_error("task_ctx lookup failed"); - return NULL; - } - return tctx; + return bpf_task_storage_get(&task_ctx_stor, p, 0, 0); } s32 BPF_STRUCT_OPS(qmap_select_cpu, struct task_struct *p, @@ -175,7 +169,7 @@ s32 BPF_STRUCT_OPS(qmap_select_cpu, struct task_struct *p, s32 cpu; if (!(tctx = lookup_task_ctx(p))) - return -ESRCH; + return prev_cpu; if (p->scx.weight < 2 && !(p->flags & PF_KTHREAD)) return prev_cpu; @@ -540,13 +534,9 @@ void BPF_STRUCT_OPS(qmap_dispatch, s32 cpu, struct task_struct *prev) */ if (prev) { tctx = bpf_task_storage_get(&task_ctx_stor, prev, 0, 0); - if (!tctx) { - scx_bpf_error("task_ctx lookup failed"); - return; - } - - tctx->core_sched_seq = - core_sched_tail_seqs[weight_to_idx(prev->scx.weight)]++; + if (tctx) + tctx->core_sched_seq = + core_sched_tail_seqs[weight_to_idx(prev->scx.weight)]++; } } @@ -584,10 +574,8 @@ static s64 task_qdist(struct task_struct *p) s64 qdist; tctx = bpf_task_storage_get(&task_ctx_stor, p, 0, 0); - if (!tctx) { - scx_bpf_error("task_ctx lookup failed"); + if (!tctx) return 0; - } qdist = tctx->core_sched_seq - core_sched_head_seqs[idx]; diff --git a/tools/testing/radix-tree/maple.c b/tools/testing/radix-tree/maple.c index feedd5ab7058..0607913a3022 100644 --- a/tools/testing/radix-tree/maple.c +++ b/tools/testing/radix-tree/maple.c @@ -2,7 +2,7 @@ /* * maple_tree.c: Userspace testing for maple tree test-suite * Copyright (c) 2018-2022 Oracle Corporation - * Author: Liam R. Howlett + * Author: Liam R. Howlett * * Any tests that require internal knowledge of the tree or threads and other * difficult to handle in kernel tests. diff --git a/tools/testing/selftests/arm64/gcs/gcs-util.h b/tools/testing/selftests/arm64/gcs/gcs-util.h index c99a6b39ac14..7a81bb07ed4b 100644 --- a/tools/testing/selftests/arm64/gcs/gcs-util.h +++ b/tools/testing/selftests/arm64/gcs/gcs-util.h @@ -18,12 +18,6 @@ #ifndef NT_ARM_GCS #define NT_ARM_GCS 0x410 - -struct user_gcs { - __u64 features_enabled; - __u64 features_locked; - __u64 gcspr_el0; -}; #endif /* Shadow Stack/Guarded Control Stack interface */ diff --git a/tools/testing/selftests/arm64/gcs/libc-gcs.c b/tools/testing/selftests/arm64/gcs/libc-gcs.c index 17b2fabfec38..72e82bfbecc9 100644 --- a/tools/testing/selftests/arm64/gcs/libc-gcs.c +++ b/tools/testing/selftests/arm64/gcs/libc-gcs.c @@ -16,6 +16,7 @@ #include #include +#include #include diff --git a/tools/testing/selftests/drivers/net/README.rst b/tools/testing/selftests/drivers/net/README.rst index c8588436c224..c6bed9a985bc 100644 --- a/tools/testing/selftests/drivers/net/README.rst +++ b/tools/testing/selftests/drivers/net/README.rst @@ -211,8 +211,8 @@ Avoid libraries and frameworks Test files should be relatively self contained. The libraries should only include very core or non-trivial code. -It may be tempting to "factor out" the common code, but fight that urge. -Library code increases the barrier of entry, and complexity in general. +It may be tempting to "factor out" the common code to lib/py/, but fight that +urge. Library code increases the barrier of entry, and complexity in general. Avoid mixing test code and boilerplate ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -290,6 +290,12 @@ or:: def test(cfg, mode, protocol): pass +Linters +~~~~~~~ + +We expect clean ``ruff check`` and ``pylint --disable=R``. +The code should be clean, avoid disabling pylint warnings explicitly! + Running tests CI-style ====================== diff --git a/tools/testing/selftests/kvm/access_tracking_perf_test.c b/tools/testing/selftests/kvm/access_tracking_perf_test.c index b058f27b2141..e5bbdb5bbdc3 100644 --- a/tools/testing/selftests/kvm/access_tracking_perf_test.c +++ b/tools/testing/selftests/kvm/access_tracking_perf_test.c @@ -101,15 +101,15 @@ struct test_params { enum vm_mem_backing_src_type backing_src; /* The amount of memory to allocate for each vCPU. */ - uint64_t vcpu_memory_bytes; + u64 vcpu_memory_bytes; /* The number of vCPUs to create in the VM. */ int nr_vcpus; }; -static uint64_t pread_uint64(int fd, const char *filename, uint64_t index) +static u64 pread_u64(int fd, const char *filename, u64 index) { - uint64_t value; + u64 value; off_t offset = index * sizeof(value); TEST_ASSERT(pread(fd, &value, sizeof(value), offset) == sizeof(value), @@ -123,13 +123,13 @@ static uint64_t pread_uint64(int fd, const char *filename, uint64_t index) #define PAGEMAP_PRESENT (1ULL << 63) #define PAGEMAP_PFN_MASK ((1ULL << 55) - 1) -static uint64_t lookup_pfn(int pagemap_fd, struct kvm_vm *vm, uint64_t gva) +static u64 lookup_pfn(int pagemap_fd, struct kvm_vm *vm, gva_t gva) { - uint64_t hva = (uint64_t) addr_gva2hva(vm, gva); - uint64_t entry; - uint64_t pfn; + u64 hva = (u64)addr_gva2hva(vm, gva); + u64 entry; + u64 pfn; - entry = pread_uint64(pagemap_fd, "pagemap", hva / getpagesize()); + entry = pread_u64(pagemap_fd, "pagemap", hva / getpagesize()); if (!(entry & PAGEMAP_PRESENT)) return 0; @@ -139,16 +139,16 @@ static uint64_t lookup_pfn(int pagemap_fd, struct kvm_vm *vm, uint64_t gva) return pfn; } -static bool is_page_idle(int page_idle_fd, uint64_t pfn) +static bool is_page_idle(int page_idle_fd, u64 pfn) { - uint64_t bits = pread_uint64(page_idle_fd, "page_idle", pfn / 64); + u64 bits = pread_u64(page_idle_fd, "page_idle", pfn / 64); return !!((bits >> (pfn % 64)) & 1); } -static void mark_page_idle(int page_idle_fd, uint64_t pfn) +static void mark_page_idle(int page_idle_fd, u64 pfn) { - uint64_t bits = 1ULL << (pfn % 64); + u64 bits = 1ULL << (pfn % 64); TEST_ASSERT(pwrite(page_idle_fd, &bits, 8, 8 * (pfn / 64)) == 8, "Set page_idle bits for PFN 0x%" PRIx64, pfn); @@ -174,11 +174,11 @@ static void pageidle_mark_vcpu_memory_idle(struct kvm_vm *vm, struct memstress_vcpu_args *vcpu_args) { int vcpu_idx = vcpu_args->vcpu_idx; - uint64_t base_gva = vcpu_args->gva; - uint64_t pages = vcpu_args->pages; - uint64_t page; - uint64_t still_idle = 0; - uint64_t no_pfn = 0; + gva_t base_gva = vcpu_args->gva; + u64 pages = vcpu_args->pages; + u64 page; + u64 still_idle = 0; + u64 no_pfn = 0; int page_idle_fd; int pagemap_fd; @@ -193,8 +193,8 @@ static void pageidle_mark_vcpu_memory_idle(struct kvm_vm *vm, TEST_ASSERT(pagemap_fd > 0, "Failed to open pagemap."); for (page = 0; page < pages; page++) { - uint64_t gva = base_gva + page * memstress_args.guest_page_size; - uint64_t pfn = lookup_pfn(pagemap_fd, vm, gva); + gva_t gva = base_gva + page * memstress_args.guest_page_size; + u64 pfn = lookup_pfn(pagemap_fd, vm, gva); if (!pfn) { no_pfn++; @@ -297,10 +297,10 @@ static void lru_gen_mark_memory_idle(struct kvm_vm *vm) lru_gen_last_gen = new_gen; } -static void assert_ucall(struct kvm_vcpu *vcpu, uint64_t expected_ucall) +static void assert_ucall(struct kvm_vcpu *vcpu, u64 expected_ucall) { struct ucall uc; - uint64_t actual_ucall = get_ucall(vcpu, &uc); + u64 actual_ucall = get_ucall(vcpu, &uc); TEST_ASSERT(expected_ucall == actual_ucall, "Guest exited unexpectedly (expected ucall %" PRIu64 @@ -417,7 +417,7 @@ static void run_test(enum vm_guest_mode mode, void *arg) */ test_pages = params->nr_vcpus * params->vcpu_memory_bytes / max(memstress_args.guest_page_size, - (uint64_t)getpagesize()); + (u64)getpagesize()); memstress_start_vcpu_threads(nr_vcpus, vcpu_thread_main); diff --git a/tools/testing/selftests/kvm/arch_timer.c b/tools/testing/selftests/kvm/arch_timer.c index cf8fb67104f1..90c475a61b22 100644 --- a/tools/testing/selftests/kvm/arch_timer.c +++ b/tools/testing/selftests/kvm/arch_timer.c @@ -78,9 +78,9 @@ static void *test_vcpu_run(void *arg) return NULL; } -static uint32_t test_get_pcpu(void) +static u32 test_get_pcpu(void) { - uint32_t pcpu; + u32 pcpu; unsigned int nproc_conf; cpu_set_t online_cpuset; @@ -98,7 +98,7 @@ static uint32_t test_get_pcpu(void) static int test_migrate_vcpu(unsigned int vcpu_idx) { int ret; - uint32_t new_pcpu = test_get_pcpu(); + u32 new_pcpu = test_get_pcpu(); pr_debug("Migrating vCPU: %u to pCPU: %u\n", vcpu_idx, new_pcpu); diff --git a/tools/testing/selftests/kvm/arm64/aarch32_id_regs.c b/tools/testing/selftests/kvm/arm64/aarch32_id_regs.c index 713005b6f508..8a019cbaf4c4 100644 --- a/tools/testing/selftests/kvm/arm64/aarch32_id_regs.c +++ b/tools/testing/selftests/kvm/arm64/aarch32_id_regs.c @@ -66,7 +66,7 @@ static void test_guest_raz(struct kvm_vcpu *vcpu) } } -static uint64_t raz_wi_reg_ids[] = { +static u64 raz_wi_reg_ids[] = { KVM_ARM64_SYS_REG(SYS_ID_PFR0_EL1), KVM_ARM64_SYS_REG(SYS_ID_PFR1_EL1), KVM_ARM64_SYS_REG(SYS_ID_DFR0_EL1), @@ -94,8 +94,8 @@ static void test_user_raz_wi(struct kvm_vcpu *vcpu) int i; for (i = 0; i < ARRAY_SIZE(raz_wi_reg_ids); i++) { - uint64_t reg_id = raz_wi_reg_ids[i]; - uint64_t val; + u64 reg_id = raz_wi_reg_ids[i]; + u64 val; val = vcpu_get_reg(vcpu, reg_id); TEST_ASSERT_EQ(val, 0); @@ -111,7 +111,7 @@ static void test_user_raz_wi(struct kvm_vcpu *vcpu) } } -static uint64_t raz_invariant_reg_ids[] = { +static u64 raz_invariant_reg_ids[] = { KVM_ARM64_SYS_REG(SYS_ID_AFR0_EL1), KVM_ARM64_SYS_REG(sys_reg(3, 0, 0, 3, 3)), KVM_ARM64_SYS_REG(SYS_ID_DFR1_EL1), @@ -123,8 +123,8 @@ static void test_user_raz_invariant(struct kvm_vcpu *vcpu) int i, r; for (i = 0; i < ARRAY_SIZE(raz_invariant_reg_ids); i++) { - uint64_t reg_id = raz_invariant_reg_ids[i]; - uint64_t val; + u64 reg_id = raz_invariant_reg_ids[i]; + u64 val; val = vcpu_get_reg(vcpu, reg_id); TEST_ASSERT_EQ(val, 0); @@ -142,7 +142,7 @@ static void test_user_raz_invariant(struct kvm_vcpu *vcpu) static bool vcpu_aarch64_only(struct kvm_vcpu *vcpu) { - uint64_t val, el0; + u64 val, el0; val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1)); diff --git a/tools/testing/selftests/kvm/arm64/arch_timer.c b/tools/testing/selftests/kvm/arm64/arch_timer.c index d592a4515399..5fa5c0ec2b3e 100644 --- a/tools/testing/selftests/kvm/arm64/arch_timer.c +++ b/tools/testing/selftests/kvm/arm64/arch_timer.c @@ -56,7 +56,7 @@ static void guest_validate_irq(unsigned int intid, struct test_vcpu_shared_data *shared_data) { enum guest_stage stage = shared_data->guest_stage; - uint64_t xcnt = 0, xcnt_diff_us, cval = 0; + u64 xcnt = 0, xcnt_diff_us, cval = 0; unsigned long xctl = 0; unsigned int timer_irq = 0; unsigned int accessor; @@ -105,7 +105,7 @@ static void guest_validate_irq(unsigned int intid, static void guest_irq_handler(struct ex_regs *regs) { unsigned int intid = gic_get_and_ack_irq(); - uint32_t cpu = guest_get_vcpuid(); + u32 cpu = guest_get_vcpuid(); struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu]; guest_validate_irq(intid, shared_data); @@ -116,7 +116,7 @@ static void guest_irq_handler(struct ex_regs *regs) static void guest_run_stage(struct test_vcpu_shared_data *shared_data, enum guest_stage stage) { - uint32_t irq_iter, config_iter; + u32 irq_iter, config_iter; shared_data->guest_stage = stage; shared_data->nr_iter = 0; @@ -140,7 +140,7 @@ static void guest_run_stage(struct test_vcpu_shared_data *shared_data, static void guest_code(void) { - uint32_t cpu = guest_get_vcpuid(); + u32 cpu = guest_get_vcpuid(); struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu]; local_irq_disable(); diff --git a/tools/testing/selftests/kvm/arm64/arch_timer_edge_cases.c b/tools/testing/selftests/kvm/arm64/arch_timer_edge_cases.c index 993c9e38e729..f7625eb711d6 100644 --- a/tools/testing/selftests/kvm/arm64/arch_timer_edge_cases.c +++ b/tools/testing/selftests/kvm/arm64/arch_timer_edge_cases.c @@ -23,25 +23,25 @@ #include "vgic.h" /* Depends on counter width. */ -static uint64_t CVAL_MAX; +static u64 CVAL_MAX; /* tval is a signed 32-bit int. */ -static const int32_t TVAL_MAX = INT32_MAX; -static const int32_t TVAL_MIN = INT32_MIN; +static const s32 TVAL_MAX = INT32_MAX; +static const s32 TVAL_MIN = INT32_MIN; /* After how much time we say there is no IRQ. */ -static const uint32_t TIMEOUT_NO_IRQ_US = 50000; +static const u32 TIMEOUT_NO_IRQ_US = 50000; /* Counter value to use as the starting one for most tests. Set to CVAL_MAX/2 */ -static uint64_t DEF_CNT; +static u64 DEF_CNT; /* Number of runs. */ -static const uint32_t NR_TEST_ITERS_DEF = 5; +static const u32 NR_TEST_ITERS_DEF = 5; /* Default wait test time in ms. */ -static const uint32_t WAIT_TEST_MS = 10; +static const u32 WAIT_TEST_MS = 10; /* Default "long" wait test time in ms. */ -static const uint32_t LONG_WAIT_TEST_MS = 100; +static const u32 LONG_WAIT_TEST_MS = 100; /* Shared with IRQ handler. */ struct test_vcpu_shared_data { @@ -53,9 +53,9 @@ struct test_args { /* Virtual or physical timer and counter tests. */ enum arch_timer timer; /* Delay used for most timer tests. */ - uint64_t wait_ms; + u64 wait_ms; /* Delay used in the test_long_timer_delays test. */ - uint64_t long_wait_ms; + u64 long_wait_ms; /* Number of iterations. */ int iterations; /* Whether to test the physical timer. */ @@ -82,12 +82,12 @@ enum sync_cmd { NO_USERSPACE_CMD, }; -typedef void (*sleep_method_t)(enum arch_timer timer, uint64_t usec); +typedef void (*sleep_method_t)(enum arch_timer timer, u64 usec); -static void sleep_poll(enum arch_timer timer, uint64_t usec); -static void sleep_sched_poll(enum arch_timer timer, uint64_t usec); -static void sleep_in_userspace(enum arch_timer timer, uint64_t usec); -static void sleep_migrate(enum arch_timer timer, uint64_t usec); +static void sleep_poll(enum arch_timer timer, u64 usec); +static void sleep_sched_poll(enum arch_timer timer, u64 usec); +static void sleep_in_userspace(enum arch_timer timer, u64 usec); +static void sleep_migrate(enum arch_timer timer, u64 usec); sleep_method_t sleep_method[] = { sleep_poll, @@ -115,14 +115,14 @@ enum timer_view { TIMER_TVAL, }; -static void assert_irqs_handled(uint32_t n) +static void assert_irqs_handled(u32 n) { int h = atomic_read(&shared_data.handled); __GUEST_ASSERT(h == n, "Handled %d IRQS but expected %d", h, n); } -static void userspace_cmd(uint64_t cmd) +static void userspace_cmd(u64 cmd) { GUEST_SYNC_ARGS(cmd, 0, 0, 0, 0); } @@ -132,12 +132,12 @@ static void userspace_migrate_vcpu(void) userspace_cmd(USERSPACE_MIGRATE_SELF); } -static void userspace_sleep(uint64_t usecs) +static void userspace_sleep(u64 usecs) { GUEST_SYNC_ARGS(USERSPACE_USLEEP, usecs, 0, 0, 0); } -static void set_counter(enum arch_timer timer, uint64_t counter) +static void set_counter(enum arch_timer timer, u64 counter) { GUEST_SYNC_ARGS(SET_COUNTER_VALUE, counter, timer, 0, 0); } @@ -146,8 +146,8 @@ static void guest_irq_handler(struct ex_regs *regs) { unsigned int intid = gic_get_and_ack_irq(); enum arch_timer timer; - uint64_t cnt, cval; - uint32_t ctl; + u64 cnt, cval; + u32 ctl; bool timer_condition, istatus; if (intid == IAR_SPURIOUS) { @@ -178,8 +178,8 @@ static void guest_irq_handler(struct ex_regs *regs) gic_set_eoi(intid); } -static void set_cval_irq(enum arch_timer timer, uint64_t cval_cycles, - uint32_t ctl) +static void set_cval_irq(enum arch_timer timer, u64 cval_cycles, + u32 ctl) { atomic_set(&shared_data.handled, 0); atomic_set(&shared_data.spurious, 0); @@ -187,8 +187,8 @@ static void set_cval_irq(enum arch_timer timer, uint64_t cval_cycles, timer_set_ctl(timer, ctl); } -static void set_tval_irq(enum arch_timer timer, uint64_t tval_cycles, - uint32_t ctl) +static void set_tval_irq(enum arch_timer timer, u64 tval_cycles, + u32 ctl) { atomic_set(&shared_data.handled, 0); atomic_set(&shared_data.spurious, 0); @@ -196,7 +196,7 @@ static void set_tval_irq(enum arch_timer timer, uint64_t tval_cycles, timer_set_ctl(timer, ctl); } -static void set_xval_irq(enum arch_timer timer, uint64_t xval, uint32_t ctl, +static void set_xval_irq(enum arch_timer timer, u64 xval, u32 ctl, enum timer_view tv) { switch (tv) { @@ -275,13 +275,13 @@ static void wait_migrate_poll_for_irq(void) * Sleep for usec microseconds by polling in the guest or in * userspace (e.g. userspace_cmd=USERSPACE_SCHEDULE). */ -static void guest_poll(enum arch_timer test_timer, uint64_t usec, +static void guest_poll(enum arch_timer test_timer, u64 usec, enum sync_cmd usp_cmd) { - uint64_t cycles = usec_to_cycles(usec); + u64 cycles = usec_to_cycles(usec); /* Whichever timer we are testing with, sleep with the other. */ enum arch_timer sleep_timer = 1 - test_timer; - uint64_t start = timer_get_cntct(sleep_timer); + u64 start = timer_get_cntct(sleep_timer); while ((timer_get_cntct(sleep_timer) - start) < cycles) { if (usp_cmd == NO_USERSPACE_CMD) @@ -291,22 +291,22 @@ static void guest_poll(enum arch_timer test_timer, uint64_t usec, } } -static void sleep_poll(enum arch_timer timer, uint64_t usec) +static void sleep_poll(enum arch_timer timer, u64 usec) { guest_poll(timer, usec, NO_USERSPACE_CMD); } -static void sleep_sched_poll(enum arch_timer timer, uint64_t usec) +static void sleep_sched_poll(enum arch_timer timer, u64 usec) { guest_poll(timer, usec, USERSPACE_SCHED_YIELD); } -static void sleep_migrate(enum arch_timer timer, uint64_t usec) +static void sleep_migrate(enum arch_timer timer, u64 usec) { guest_poll(timer, usec, USERSPACE_MIGRATE_SELF); } -static void sleep_in_userspace(enum arch_timer timer, uint64_t usec) +static void sleep_in_userspace(enum arch_timer timer, u64 usec) { userspace_sleep(usec); } @@ -315,15 +315,15 @@ static void sleep_in_userspace(enum arch_timer timer, uint64_t usec) * Reset the timer state to some nice values like the counter not being close * to the edge, and the control register masked and disabled. */ -static void reset_timer_state(enum arch_timer timer, uint64_t cnt) +static void reset_timer_state(enum arch_timer timer, u64 cnt) { set_counter(timer, cnt); timer_set_ctl(timer, CTL_IMASK); } -static void test_timer_xval(enum arch_timer timer, uint64_t xval, +static void test_timer_xval(enum arch_timer timer, u64 xval, enum timer_view tv, irq_wait_method_t wm, bool reset_state, - uint64_t reset_cnt) + u64 reset_cnt) { local_irq_disable(); @@ -348,23 +348,23 @@ static void test_timer_xval(enum arch_timer timer, uint64_t xval, * the "runner", like: tools/testing/selftests/kselftest/runner.sh. */ -static void test_timer_cval(enum arch_timer timer, uint64_t cval, +static void test_timer_cval(enum arch_timer timer, u64 cval, irq_wait_method_t wm, bool reset_state, - uint64_t reset_cnt) + u64 reset_cnt) { test_timer_xval(timer, cval, TIMER_CVAL, wm, reset_state, reset_cnt); } -static void test_timer_tval(enum arch_timer timer, int32_t tval, +static void test_timer_tval(enum arch_timer timer, s32 tval, irq_wait_method_t wm, bool reset_state, - uint64_t reset_cnt) + u64 reset_cnt) { - test_timer_xval(timer, (uint64_t) tval, TIMER_TVAL, wm, reset_state, + test_timer_xval(timer, (u64)tval, TIMER_TVAL, wm, reset_state, reset_cnt); } -static void test_xval_check_no_irq(enum arch_timer timer, uint64_t xval, - uint64_t usec, enum timer_view timer_view, +static void test_xval_check_no_irq(enum arch_timer timer, u64 xval, + u64 usec, enum timer_view timer_view, sleep_method_t guest_sleep) { local_irq_disable(); @@ -379,17 +379,17 @@ static void test_xval_check_no_irq(enum arch_timer timer, uint64_t xval, assert_irqs_handled(0); } -static void test_cval_no_irq(enum arch_timer timer, uint64_t cval, - uint64_t usec, sleep_method_t wm) +static void test_cval_no_irq(enum arch_timer timer, u64 cval, + u64 usec, sleep_method_t wm) { test_xval_check_no_irq(timer, cval, usec, TIMER_CVAL, wm); } -static void test_tval_no_irq(enum arch_timer timer, int32_t tval, uint64_t usec, +static void test_tval_no_irq(enum arch_timer timer, s32 tval, u64 usec, sleep_method_t wm) { - /* tval will be cast to an int32_t in test_xval_check_no_irq */ - test_xval_check_no_irq(timer, (uint64_t) tval, usec, TIMER_TVAL, wm); + /* tval will be cast to an s32 in test_xval_check_no_irq */ + test_xval_check_no_irq(timer, (u64)tval, usec, TIMER_TVAL, wm); } /* Test masking/unmasking a timer using the timer mask (not the IRQ mask). */ @@ -463,7 +463,7 @@ static void test_timers_fired_multiple_times(enum arch_timer timer) * timeout for the wait: we use the wfi instruction. */ static void test_reprogramming_timer(enum arch_timer timer, irq_wait_method_t wm, - int32_t delta_1_ms, int32_t delta_2_ms) + s32 delta_1_ms, s32 delta_2_ms) { local_irq_disable(); reset_timer_state(timer, DEF_CNT); @@ -488,7 +488,7 @@ static void test_reprogramming_timer(enum arch_timer timer, irq_wait_method_t wm static void test_reprogram_timers(enum arch_timer timer) { int i; - uint64_t base_wait = test_args.wait_ms; + u64 base_wait = test_args.wait_ms; for (i = 0; i < ARRAY_SIZE(irq_wait_method); i++) { /* @@ -504,8 +504,8 @@ static void test_reprogram_timers(enum arch_timer timer) static void test_basic_functionality(enum arch_timer timer) { - int32_t tval = (int32_t) msec_to_cycles(test_args.wait_ms); - uint64_t cval = DEF_CNT + msec_to_cycles(test_args.wait_ms); + s32 tval = (s32)msec_to_cycles(test_args.wait_ms); + u64 cval = DEF_CNT + msec_to_cycles(test_args.wait_ms); int i; for (i = 0; i < ARRAY_SIZE(irq_wait_method); i++) { @@ -593,7 +593,7 @@ static void test_set_cnt_after_tval_max(enum arch_timer timer, irq_wait_method_t reset_timer_state(timer, DEF_CNT); set_cval_irq(timer, - (uint64_t) TVAL_MAX + + (u64)TVAL_MAX + msec_to_cycles(test_args.wait_ms) / 2, CTL_ENABLE); set_counter(timer, TVAL_MAX); @@ -608,7 +608,7 @@ static void test_set_cnt_after_tval_max(enum arch_timer timer, irq_wait_method_t /* Test timers set for: cval = now + TVAL_MAX + wait_ms / 2 */ static void test_timers_above_tval_max(enum arch_timer timer) { - uint64_t cval; + u64 cval; int i; /* @@ -638,8 +638,8 @@ static void test_timers_above_tval_max(enum arch_timer timer) * sets the counter to cnt_1, the [c|t]val, the counter to cnt_2, and * then waits for an IRQ. */ -static void test_set_cnt_after_xval(enum arch_timer timer, uint64_t cnt_1, - uint64_t xval, uint64_t cnt_2, +static void test_set_cnt_after_xval(enum arch_timer timer, u64 cnt_1, + u64 xval, u64 cnt_2, irq_wait_method_t wm, enum timer_view tv) { local_irq_disable(); @@ -662,8 +662,8 @@ static void test_set_cnt_after_xval(enum arch_timer timer, uint64_t cnt_1, * then waits for an IRQ. */ static void test_set_cnt_after_xval_no_irq(enum arch_timer timer, - uint64_t cnt_1, uint64_t xval, - uint64_t cnt_2, + u64 cnt_1, u64 xval, + u64 cnt_2, sleep_method_t guest_sleep, enum timer_view tv) { @@ -684,31 +684,31 @@ static void test_set_cnt_after_xval_no_irq(enum arch_timer timer, timer_set_ctl(timer, CTL_IMASK); } -static void test_set_cnt_after_tval(enum arch_timer timer, uint64_t cnt_1, - int32_t tval, uint64_t cnt_2, +static void test_set_cnt_after_tval(enum arch_timer timer, u64 cnt_1, + s32 tval, u64 cnt_2, irq_wait_method_t wm) { test_set_cnt_after_xval(timer, cnt_1, tval, cnt_2, wm, TIMER_TVAL); } -static void test_set_cnt_after_cval(enum arch_timer timer, uint64_t cnt_1, - uint64_t cval, uint64_t cnt_2, +static void test_set_cnt_after_cval(enum arch_timer timer, u64 cnt_1, + u64 cval, u64 cnt_2, irq_wait_method_t wm) { test_set_cnt_after_xval(timer, cnt_1, cval, cnt_2, wm, TIMER_CVAL); } static void test_set_cnt_after_tval_no_irq(enum arch_timer timer, - uint64_t cnt_1, int32_t tval, - uint64_t cnt_2, sleep_method_t wm) + u64 cnt_1, s32 tval, + u64 cnt_2, sleep_method_t wm) { test_set_cnt_after_xval_no_irq(timer, cnt_1, tval, cnt_2, wm, TIMER_TVAL); } static void test_set_cnt_after_cval_no_irq(enum arch_timer timer, - uint64_t cnt_1, uint64_t cval, - uint64_t cnt_2, sleep_method_t wm) + u64 cnt_1, u64 cval, + u64 cnt_2, sleep_method_t wm) { test_set_cnt_after_xval_no_irq(timer, cnt_1, cval, cnt_2, wm, TIMER_CVAL); @@ -718,7 +718,7 @@ static void test_set_cnt_after_cval_no_irq(enum arch_timer timer, static void test_move_counters_ahead_of_timers(enum arch_timer timer) { int i; - int32_t tval; + s32 tval; for (i = 0; i < ARRAY_SIZE(irq_wait_method); i++) { irq_wait_method_t wm = irq_wait_method[i]; @@ -730,8 +730,7 @@ static void test_move_counters_ahead_of_timers(enum arch_timer timer) test_set_cnt_after_tval(timer, 0, -1, DEF_CNT + 1, wm); test_set_cnt_after_tval(timer, 0, -1, TVAL_MAX, wm); tval = TVAL_MAX; - test_set_cnt_after_tval(timer, 0, tval, (uint64_t) tval + 1, - wm); + test_set_cnt_after_tval(timer, 0, tval, (u64)tval + 1, wm); } } @@ -754,8 +753,8 @@ static void test_move_counters_behind_timers(enum arch_timer timer) static void test_timers_in_the_past(enum arch_timer timer) { - int32_t tval = -1 * (int32_t) msec_to_cycles(test_args.wait_ms); - uint64_t cval; + s32 tval = -1 * (s32)msec_to_cycles(test_args.wait_ms); + u64 cval; int i; for (i = 0; i < ARRAY_SIZE(irq_wait_method); i++) { @@ -790,8 +789,8 @@ static void test_timers_in_the_past(enum arch_timer timer) static void test_long_timer_delays(enum arch_timer timer) { - int32_t tval = (int32_t) msec_to_cycles(test_args.long_wait_ms); - uint64_t cval = DEF_CNT + msec_to_cycles(test_args.long_wait_ms); + s32 tval = (s32)msec_to_cycles(test_args.long_wait_ms); + u64 cval = DEF_CNT + msec_to_cycles(test_args.long_wait_ms); int i; for (i = 0; i < ARRAY_SIZE(irq_wait_method); i++) { @@ -846,11 +845,11 @@ static void guest_code(enum arch_timer timer) static cpu_set_t default_cpuset; -static uint32_t next_pcpu(void) +static u32 next_pcpu(void) { - uint32_t max = get_nprocs(); - uint32_t cur = sched_getcpu(); - uint32_t next = cur; + u32 max = get_nprocs(); + u32 cur = sched_getcpu(); + u32 next = cur; cpu_set_t cpuset = default_cpuset; TEST_ASSERT(max > 1, "Need at least two physical cpus"); @@ -862,7 +861,7 @@ static uint32_t next_pcpu(void) return next; } -static void kvm_set_cntxct(struct kvm_vcpu *vcpu, uint64_t cnt, +static void kvm_set_cntxct(struct kvm_vcpu *vcpu, u64 cnt, enum arch_timer timer) { if (timer == PHYSICAL) @@ -874,7 +873,7 @@ static void kvm_set_cntxct(struct kvm_vcpu *vcpu, uint64_t cnt, static void handle_sync(struct kvm_vcpu *vcpu, struct ucall *uc) { enum sync_cmd cmd = uc->args[1]; - uint64_t val = uc->args[2]; + u64 val = uc->args[2]; enum arch_timer timer = uc->args[3]; switch (cmd) { @@ -1018,8 +1017,8 @@ static bool parse_args(int argc, char *argv[]) static void set_counter_defaults(void) { - const uint64_t MIN_ROLLOVER_SECS = 40ULL * 365 * 24 * 3600; - uint64_t freq = read_sysreg(CNTFRQ_EL0); + const u64 MIN_ROLLOVER_SECS = 40ULL * 365 * 24 * 3600; + u64 freq = read_sysreg(CNTFRQ_EL0); int width = ilog2(MIN_ROLLOVER_SECS * freq); width = clamp(width, 56, 64); diff --git a/tools/testing/selftests/kvm/arm64/debug-exceptions.c b/tools/testing/selftests/kvm/arm64/debug-exceptions.c index 1d431de8729c..3eb4b1b6682d 100644 --- a/tools/testing/selftests/kvm/arm64/debug-exceptions.c +++ b/tools/testing/selftests/kvm/arm64/debug-exceptions.c @@ -31,14 +31,14 @@ extern unsigned char sw_bp, sw_bp2, hw_bp, hw_bp2, bp_svc, bp_brk, hw_wp, ss_start, hw_bp_ctx; extern unsigned char iter_ss_begin, iter_ss_end; -static volatile uint64_t sw_bp_addr, hw_bp_addr; -static volatile uint64_t wp_addr, wp_data_addr; -static volatile uint64_t svc_addr; -static volatile uint64_t ss_addr[4], ss_idx; -#define PC(v) ((uint64_t)&(v)) +static volatile u64 sw_bp_addr, hw_bp_addr; +static volatile u64 wp_addr, wp_data_addr; +static volatile u64 svc_addr; +static volatile u64 ss_addr[4], ss_idx; +#define PC(v) ((u64)&(v)) #define GEN_DEBUG_WRITE_REG(reg_name) \ -static void write_##reg_name(int num, uint64_t val) \ +static void write_##reg_name(int num, u64 val) \ { \ switch (num) { \ case 0: \ @@ -102,8 +102,8 @@ GEN_DEBUG_WRITE_REG(dbgwvr) static void reset_debug_state(void) { - uint8_t brps, wrps, i; - uint64_t dfr0; + u8 brps, wrps, i; + u64 dfr0; asm volatile("msr daifset, #8"); @@ -140,7 +140,7 @@ static void enable_os_lock(void) static void enable_monitor_debug_exceptions(void) { - uint64_t mdscr; + u64 mdscr; asm volatile("msr daifclr, #8"); @@ -149,9 +149,9 @@ static void enable_monitor_debug_exceptions(void) isb(); } -static void install_wp(uint8_t wpn, uint64_t addr) +static void install_wp(u8 wpn, u64 addr) { - uint32_t wcr; + u32 wcr; wcr = DBGWCR_LEN8 | DBGWCR_RD | DBGWCR_WR | DBGWCR_EL1 | DBGWCR_E; write_dbgwcr(wpn, wcr); @@ -162,9 +162,9 @@ static void install_wp(uint8_t wpn, uint64_t addr) enable_monitor_debug_exceptions(); } -static void install_hw_bp(uint8_t bpn, uint64_t addr) +static void install_hw_bp(u8 bpn, u64 addr) { - uint32_t bcr; + u32 bcr; bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E; write_dbgbcr(bpn, bcr); @@ -174,11 +174,10 @@ static void install_hw_bp(uint8_t bpn, uint64_t addr) enable_monitor_debug_exceptions(); } -static void install_wp_ctx(uint8_t addr_wp, uint8_t ctx_bp, uint64_t addr, - uint64_t ctx) +static void install_wp_ctx(u8 addr_wp, u8 ctx_bp, u64 addr, u64 ctx) { - uint32_t wcr; - uint64_t ctx_bcr; + u32 wcr; + u64 ctx_bcr; /* Setup a context-aware breakpoint for Linked Context ID Match */ ctx_bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E | @@ -188,7 +187,7 @@ static void install_wp_ctx(uint8_t addr_wp, uint8_t ctx_bp, uint64_t addr, /* Setup a linked watchpoint (linked to the context-aware breakpoint) */ wcr = DBGWCR_LEN8 | DBGWCR_RD | DBGWCR_WR | DBGWCR_EL1 | DBGWCR_E | - DBGWCR_WT_LINK | ((uint32_t)ctx_bp << DBGWCR_LBN_SHIFT); + DBGWCR_WT_LINK | ((u32)ctx_bp << DBGWCR_LBN_SHIFT); write_dbgwcr(addr_wp, wcr); write_dbgwvr(addr_wp, addr); isb(); @@ -196,10 +195,9 @@ static void install_wp_ctx(uint8_t addr_wp, uint8_t ctx_bp, uint64_t addr, enable_monitor_debug_exceptions(); } -void install_hw_bp_ctx(uint8_t addr_bp, uint8_t ctx_bp, uint64_t addr, - uint64_t ctx) +void install_hw_bp_ctx(u8 addr_bp, u8 ctx_bp, u64 addr, u64 ctx) { - uint32_t addr_bcr, ctx_bcr; + u32 addr_bcr, ctx_bcr; /* Setup a context-aware breakpoint for Linked Context ID Match */ ctx_bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E | @@ -213,7 +211,7 @@ void install_hw_bp_ctx(uint8_t addr_bp, uint8_t ctx_bp, uint64_t addr, */ addr_bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E | DBGBCR_BT_ADDR_LINK_CTX | - ((uint32_t)ctx_bp << DBGBCR_LBN_SHIFT); + ((u32)ctx_bp << DBGBCR_LBN_SHIFT); write_dbgbcr(addr_bp, addr_bcr); write_dbgbvr(addr_bp, addr); isb(); @@ -223,7 +221,7 @@ void install_hw_bp_ctx(uint8_t addr_bp, uint8_t ctx_bp, uint64_t addr, static void install_ss(void) { - uint64_t mdscr; + u64 mdscr; asm volatile("msr daifclr, #8"); @@ -234,9 +232,9 @@ static void install_ss(void) static volatile char write_data; -static void guest_code(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) +static void guest_code(u8 bpn, u8 wpn, u8 ctx_bpn) { - uint64_t ctx = 0xabcdef; /* a random context number */ + u64 ctx = 0xabcdef; /* a random context number */ /* Software-breakpoint */ reset_debug_state(); @@ -377,8 +375,8 @@ static void guest_svc_handler(struct ex_regs *regs) static void guest_code_ss(int test_cnt) { - uint64_t i; - uint64_t bvr, wvr, w_bvr, w_wvr; + u64 i; + u64 bvr, wvr, w_bvr, w_wvr; for (i = 0; i < test_cnt; i++) { /* Bits [1:0] of dbg{b,w}vr are RES0 */ @@ -416,12 +414,12 @@ static void guest_code_ss(int test_cnt) GUEST_DONE(); } -static int debug_version(uint64_t id_aa64dfr0) +static int debug_version(u64 id_aa64dfr0) { return FIELD_GET(ID_AA64DFR0_EL1_DebugVer, id_aa64dfr0); } -static void test_guest_debug_exceptions(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) +static void test_guest_debug_exceptions(u8 bpn, u8 wpn, u8 ctx_bpn) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; @@ -468,8 +466,8 @@ void test_single_step_from_userspace(int test_cnt) struct kvm_vm *vm; struct ucall uc; struct kvm_run *run; - uint64_t pc, cmd; - uint64_t test_pc = 0; + u64 pc, cmd; + u64 test_pc = 0; bool ss_enable = false; struct kvm_guest_debug debug = {}; @@ -506,7 +504,7 @@ void test_single_step_from_userspace(int test_cnt) "Unexpected pc 0x%lx (expected 0x%lx)", pc, test_pc); - if ((pc + 4) == (uint64_t)&iter_ss_end) { + if ((pc + 4) == (u64)&iter_ss_end) { test_pc = 0; debug.control = KVM_GUESTDBG_ENABLE; ss_enable = false; @@ -519,8 +517,8 @@ void test_single_step_from_userspace(int test_cnt) * iter_ss_end, the pc for the next KVM_EXIT_DEBUG should * be the current pc + 4. */ - if ((pc >= (uint64_t)&iter_ss_begin) && - (pc < (uint64_t)&iter_ss_end)) + if ((pc >= (u64)&iter_ss_begin) && + (pc < (u64)&iter_ss_end)) test_pc = pc + 4; else test_pc = 0; @@ -533,9 +531,9 @@ void test_single_step_from_userspace(int test_cnt) * Run debug testing using the various breakpoint#, watchpoint# and * context-aware breakpoint# with the given ID_AA64DFR0_EL1 configuration. */ -void test_guest_debug_exceptions_all(uint64_t aa64dfr0) +void test_guest_debug_exceptions_all(u64 aa64dfr0) { - uint8_t brp_num, wrp_num, ctx_brp_num, normal_brp_num, ctx_brp_base; + u8 brp_num, wrp_num, ctx_brp_num, normal_brp_num, ctx_brp_base; int b, w, c; /* Number of breakpoints */ @@ -580,7 +578,7 @@ int main(int argc, char *argv[]) struct kvm_vm *vm; int opt; int ss_iteration = 10000; - uint64_t aa64dfr0; + u64 aa64dfr0; vm = vm_create_with_one_vcpu(&vcpu, guest_code); aa64dfr0 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1)); diff --git a/tools/testing/selftests/kvm/arm64/hypercalls.c b/tools/testing/selftests/kvm/arm64/hypercalls.c index bf038a0371f4..5d96cdf382c4 100644 --- a/tools/testing/selftests/kvm/arm64/hypercalls.c +++ b/tools/testing/selftests/kvm/arm64/hypercalls.c @@ -29,9 +29,9 @@ #define KVM_REG_ARM_VENDOR_HYP_BMAP_2_RESET_VAL 0 struct kvm_fw_reg_info { - uint64_t reg; /* Register definition */ - uint64_t max_feat_bit; /* Bit that represents the upper limit of the feature-map */ - uint64_t reset_val; /* Reset value for the register */ + u64 reg; /* Register definition */ + u64 max_feat_bit; /* Bit that represents the upper limit of the feature-map */ + u64 reset_val; /* Reset value for the register */ }; #define FW_REG_INFO(r) \ @@ -59,8 +59,8 @@ enum test_stage { static int stage = TEST_STAGE_REG_IFACE; struct test_hvc_info { - uint32_t func_id; - uint64_t arg1; + u32 func_id; + u64 arg1; }; #define TEST_HVC_INFO(f, a1) \ @@ -152,9 +152,9 @@ static void guest_code(void) } struct st_time { - uint32_t rev; - uint32_t attr; - uint64_t st_time; + u32 rev; + u32 attr; + u64 st_time; }; #define STEAL_TIME_SIZE ((sizeof(struct st_time) + 63) & ~63) @@ -162,7 +162,7 @@ struct st_time { static void steal_time_init(struct kvm_vcpu *vcpu) { - uint64_t st_ipa = (ulong)ST_GPA_BASE; + u64 st_ipa = (ulong)ST_GPA_BASE; unsigned int gpages; gpages = vm_calc_num_guest_pages(VM_MODE_DEFAULT, STEAL_TIME_SIZE); @@ -174,13 +174,13 @@ static void steal_time_init(struct kvm_vcpu *vcpu) static void test_fw_regs_before_vm_start(struct kvm_vcpu *vcpu) { - uint64_t val; + u64 val; unsigned int i; int ret; for (i = 0; i < ARRAY_SIZE(fw_reg_info); i++) { const struct kvm_fw_reg_info *reg_info = &fw_reg_info[i]; - uint64_t set_val; + u64 set_val; /* First 'read' should be the reset value for the reg */ val = vcpu_get_reg(vcpu, reg_info->reg); @@ -229,7 +229,7 @@ static void test_fw_regs_before_vm_start(struct kvm_vcpu *vcpu) static void test_fw_regs_after_vm_start(struct kvm_vcpu *vcpu) { - uint64_t val; + u64 val; unsigned int i; int ret; diff --git a/tools/testing/selftests/kvm/arm64/idreg-idst.c b/tools/testing/selftests/kvm/arm64/idreg-idst.c index 9ca9f125abdb..a3e84701d814 100644 --- a/tools/testing/selftests/kvm/arm64/idreg-idst.c +++ b/tools/testing/selftests/kvm/arm64/idreg-idst.c @@ -13,7 +13,7 @@ static volatile bool sys64, undef; #define __check_sr_read(r) \ ({ \ - uint64_t val; \ + u64 val; \ \ sys64 = false; \ undef = false; \ @@ -101,7 +101,7 @@ int main(int argc, char *argv[]) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; - uint64_t mmfr2; + u64 mmfr2; test_disable_default_vgic(); diff --git a/tools/testing/selftests/kvm/arm64/no-vgic.c b/tools/testing/selftests/kvm/arm64/no-vgic.c index b14686ef17d1..25b2e3222f68 100644 --- a/tools/testing/selftests/kvm/arm64/no-vgic.c +++ b/tools/testing/selftests/kvm/arm64/no-vgic.c @@ -15,7 +15,7 @@ static volatile bool handled; #define __check_sr_read(r) \ ({ \ - uint64_t val; \ + u64 val; \ \ handled = false; \ dsb(sy); \ @@ -33,7 +33,7 @@ static volatile bool handled; #define __check_gicv5_gicr_op(r) \ ({ \ - uint64_t val; \ + u64 val; \ \ handled = false; \ dsb(sy); \ @@ -82,7 +82,7 @@ static volatile bool handled; static void guest_code_gicv3(void) { - uint64_t val; + u64 val; /* * Check that we advertise that ID_AA64PFR0_EL1.GIC == 0, having @@ -262,7 +262,7 @@ int main(int argc, char *argv[]) struct kvm_vcpu *vcpu; struct kvm_vm *vm; bool has_v3, has_v5; - uint64_t pfr; + u64 pfr; test_disable_default_vgic(); diff --git a/tools/testing/selftests/kvm/arm64/page_fault_test.c b/tools/testing/selftests/kvm/arm64/page_fault_test.c index 4ccbd389d133..6bb3d82906b2 100644 --- a/tools/testing/selftests/kvm/arm64/page_fault_test.c +++ b/tools/testing/selftests/kvm/arm64/page_fault_test.c @@ -23,7 +23,7 @@ #define TEST_PTE_GVA 0xb0000000 #define TEST_DATA 0x0123456789ABCDEF -static uint64_t *guest_test_memory = (uint64_t *)TEST_GVA; +static u64 *guest_test_memory = (u64 *)TEST_GVA; #define CMD_NONE (0) #define CMD_SKIP_TEST (1ULL << 1) @@ -48,7 +48,7 @@ static struct event_cnt { struct test_desc { const char *name; - uint64_t mem_mark_cmd; + u64 mem_mark_cmd; /* Skip the test if any prepare function returns false */ bool (*guest_prepare[PREPARE_FN_NR])(void); void (*guest_test)(void); @@ -59,8 +59,8 @@ struct test_desc { void (*iabt_handler)(struct ex_regs *regs); void (*mmio_handler)(struct kvm_vm *vm, struct kvm_run *run); void (*fail_vcpu_run_handler)(int ret); - uint32_t pt_memslot_flags; - uint32_t data_memslot_flags; + u32 pt_memslot_flags; + u32 data_memslot_flags; bool skip; struct event_cnt expected_events; }; @@ -70,9 +70,9 @@ struct test_params { struct test_desc *test_desc; }; -static inline void flush_tlb_page(uint64_t vaddr) +static inline void flush_tlb_page(gva_t gva) { - uint64_t page = vaddr >> 12; + gva_t page = gva >> 12; dsb(ishst); asm volatile("tlbi vaae1is, %0" :: "r" (page)); @@ -82,7 +82,7 @@ static inline void flush_tlb_page(uint64_t vaddr) static void guest_write64(void) { - uint64_t val; + u64 val; WRITE_ONCE(*guest_test_memory, TEST_DATA); val = READ_ONCE(*guest_test_memory); @@ -92,8 +92,8 @@ static void guest_write64(void) /* Check the system for atomic instructions. */ static bool guest_check_lse(void) { - uint64_t isar0 = read_sysreg(id_aa64isar0_el1); - uint64_t atomic; + u64 isar0 = read_sysreg(id_aa64isar0_el1); + u64 atomic; atomic = FIELD_GET(ID_AA64ISAR0_EL1_ATOMIC, isar0); return atomic >= 2; @@ -101,8 +101,8 @@ static bool guest_check_lse(void) static bool guest_check_dc_zva(void) { - uint64_t dczid = read_sysreg(dczid_el0); - uint64_t dzp = FIELD_GET(DCZID_EL0_DZP, dczid); + u64 dczid = read_sysreg(dczid_el0); + u64 dzp = FIELD_GET(DCZID_EL0_DZP, dczid); return dzp == 0; } @@ -110,7 +110,7 @@ static bool guest_check_dc_zva(void) /* Compare and swap instruction. */ static void guest_cas(void) { - uint64_t val; + u64 val; GUEST_ASSERT(guest_check_lse()); asm volatile(".arch_extension lse\n" @@ -122,7 +122,7 @@ static void guest_cas(void) static void guest_read64(void) { - uint64_t val; + u64 val; val = READ_ONCE(*guest_test_memory); GUEST_ASSERT_EQ(val, 0); @@ -131,7 +131,7 @@ static void guest_read64(void) /* Address translation instruction */ static void guest_at(void) { - uint64_t par; + u64 par; asm volatile("at s1e1r, %0" :: "r" (guest_test_memory)); isb(); @@ -148,7 +148,7 @@ static void guest_at(void) */ static void guest_dc_zva(void) { - uint16_t val; + u16 val; asm volatile("dc zva, %0" :: "r" (guest_test_memory)); dsb(ish); @@ -164,8 +164,8 @@ static void guest_dc_zva(void) */ static void guest_ld_preidx(void) { - uint64_t val; - uint64_t addr = TEST_GVA - 8; + u64 val; + u64 addr = TEST_GVA - 8; /* * This ends up accessing "TEST_GVA + 8 - 8", where "TEST_GVA - 8" is @@ -179,8 +179,8 @@ static void guest_ld_preidx(void) static void guest_st_preidx(void) { - uint64_t val = TEST_DATA; - uint64_t addr = TEST_GVA - 8; + u64 val = TEST_DATA; + u64 addr = TEST_GVA - 8; asm volatile("str %0, [%1, #8]!" : "+r" (val), "+r" (addr)); @@ -191,8 +191,8 @@ static void guest_st_preidx(void) static bool guest_set_ha(void) { - uint64_t mmfr1 = read_sysreg(id_aa64mmfr1_el1); - uint64_t hadbs, tcr; + u64 mmfr1 = read_sysreg(id_aa64mmfr1_el1); + u64 hadbs, tcr; /* Skip if HA is not supported. */ hadbs = FIELD_GET(ID_AA64MMFR1_EL1_HAFDBS, mmfr1); @@ -208,7 +208,7 @@ static bool guest_set_ha(void) static bool guest_clear_pte_af(void) { - *((uint64_t *)TEST_PTE_GVA) &= ~PTE_AF; + *((u64 *)TEST_PTE_GVA) &= ~PTE_AF; flush_tlb_page(TEST_GVA); return true; @@ -217,7 +217,7 @@ static bool guest_clear_pte_af(void) static void guest_check_pte_af(void) { dsb(ish); - GUEST_ASSERT_EQ(*((uint64_t *)TEST_PTE_GVA) & PTE_AF, PTE_AF); + GUEST_ASSERT_EQ(*((u64 *)TEST_PTE_GVA) & PTE_AF, PTE_AF); } static void guest_check_write_in_dirty_log(void) @@ -302,26 +302,26 @@ static void no_iabt_handler(struct ex_regs *regs) static struct uffd_args { char *copy; void *hva; - uint64_t paging_size; + u64 paging_size; } pt_args, data_args; /* Returns true to continue the test, and false if it should be skipped. */ static int uffd_generic_handler(int uffd_mode, int uffd, struct uffd_msg *msg, struct uffd_args *args) { - uint64_t addr = msg->arg.pagefault.address; - uint64_t flags = msg->arg.pagefault.flags; + u64 addr = msg->arg.pagefault.address; + u64 flags = msg->arg.pagefault.flags; struct uffdio_copy copy; int ret; TEST_ASSERT(uffd_mode == UFFDIO_REGISTER_MODE_MISSING, "The only expected UFFD mode is MISSING"); - TEST_ASSERT_EQ(addr, (uint64_t)args->hva); + TEST_ASSERT_EQ(addr, (u64)args->hva); pr_debug("uffd fault: addr=%p write=%d\n", (void *)addr, !!(flags & UFFD_PAGEFAULT_FLAG_WRITE)); - copy.src = (uint64_t)args->copy; + copy.src = (u64)args->copy; copy.dst = addr; copy.len = args->paging_size; copy.mode = 0; @@ -407,7 +407,7 @@ static bool punch_hole_in_backing_store(struct kvm_vm *vm, struct userspace_mem_region *region) { void *hva = (void *)region->region.userspace_addr; - uint64_t paging_size = region->region.memory_size; + u64 paging_size = region->region.memory_size; int ret, fd = region->fd; if (fd != -1) { @@ -438,7 +438,7 @@ static void mmio_on_test_gpa_handler(struct kvm_vm *vm, struct kvm_run *run) static void mmio_no_handler(struct kvm_vm *vm, struct kvm_run *run) { - uint64_t data; + u64 data; memcpy(&data, run->mmio.data, sizeof(data)); pr_debug("addr=%lld len=%d w=%d data=%lx\n", @@ -449,11 +449,11 @@ static void mmio_no_handler(struct kvm_vm *vm, struct kvm_run *run) static bool check_write_in_dirty_log(struct kvm_vm *vm, struct userspace_mem_region *region, - uint64_t host_pg_nr) + u64 host_pg_nr) { unsigned long *bmap; bool first_page_dirty; - uint64_t size = region->region.memory_size; + u64 size = region->region.memory_size; /* getpage_size() is not always equal to vm->page_size */ bmap = bitmap_zalloc(size / getpagesize()); @@ -468,7 +468,7 @@ static bool handle_cmd(struct kvm_vm *vm, int cmd) { struct userspace_mem_region *data_region, *pt_region; bool continue_test = true; - uint64_t pte_gpa, pte_pg; + u64 pte_gpa, pte_pg; data_region = vm_get_mem_region(vm, MEM_REGION_TEST_DATA); pt_region = vm_get_mem_region(vm, MEM_REGION_PT); @@ -510,7 +510,7 @@ void fail_vcpu_run_mmio_no_syndrome_handler(int ret) events.fail_vcpu_runs += 1; } -typedef uint32_t aarch64_insn_t; +typedef u32 aarch64_insn_t; extern aarch64_insn_t __exec_test[2]; noinline void __return_0x77(void) @@ -525,7 +525,7 @@ noinline void __return_0x77(void) */ static void load_exec_code_for_test(struct kvm_vm *vm) { - uint64_t *code; + u64 *code; struct userspace_mem_region *region; void *hva; @@ -552,7 +552,7 @@ static void setup_abort_handlers(struct kvm_vm *vm, struct kvm_vcpu *vcpu, static void setup_gva_maps(struct kvm_vm *vm) { struct userspace_mem_region *region; - uint64_t pte_gpa; + u64 pte_gpa; region = vm_get_mem_region(vm, MEM_REGION_TEST_DATA); /* Map TEST_GVA first. This will install a new PTE. */ @@ -574,12 +574,12 @@ enum pf_test_memslots { */ static void setup_memslots(struct kvm_vm *vm, struct test_params *p) { - uint64_t backing_src_pagesz = get_backing_src_pagesz(p->src_type); - uint64_t guest_page_size = vm->page_size; - uint64_t max_gfn = vm_compute_max_gfn(vm); + u64 backing_src_pagesz = get_backing_src_pagesz(p->src_type); + u64 guest_page_size = vm->page_size; + u64 max_gfn = vm_compute_max_gfn(vm); /* Enough for 2M of code when using 4K guest pages. */ - uint64_t code_npages = 512; - uint64_t pt_size, data_size, data_gpa; + u64 code_npages = 512; + u64 pt_size, data_size, data_gpa; /* * This test requires 1 pgd, 2 pud, 4 pmd, and 6 pte pages when using diff --git a/tools/testing/selftests/kvm/arm64/psci_test.c b/tools/testing/selftests/kvm/arm64/psci_test.c index 98e49f710aef..e775faf20868 100644 --- a/tools/testing/selftests/kvm/arm64/psci_test.c +++ b/tools/testing/selftests/kvm/arm64/psci_test.c @@ -22,8 +22,7 @@ #define CPU_ON_ENTRY_ADDR 0xfeedf00dul #define CPU_ON_CONTEXT_ID 0xdeadc0deul -static uint64_t psci_cpu_on(uint64_t target_cpu, uint64_t entry_addr, - uint64_t context_id) +static u64 psci_cpu_on(u64 target_cpu, u64 entry_addr, u64 context_id) { struct arm_smccc_res res; @@ -33,8 +32,7 @@ static uint64_t psci_cpu_on(uint64_t target_cpu, uint64_t entry_addr, return res.a0; } -static uint64_t psci_affinity_info(uint64_t target_affinity, - uint64_t lowest_affinity_level) +static u64 psci_affinity_info(u64 target_affinity, u64 lowest_affinity_level) { struct arm_smccc_res res; @@ -44,7 +42,7 @@ static uint64_t psci_affinity_info(uint64_t target_affinity, return res.a0; } -static uint64_t psci_system_suspend(uint64_t entry_addr, uint64_t context_id) +static u64 psci_system_suspend(u64 entry_addr, u64 context_id) { struct arm_smccc_res res; @@ -54,7 +52,7 @@ static uint64_t psci_system_suspend(uint64_t entry_addr, uint64_t context_id) return res.a0; } -static uint64_t psci_system_off2(uint64_t type, uint64_t cookie) +static u64 psci_system_off2(u64 type, u64 cookie) { struct arm_smccc_res res; @@ -63,7 +61,7 @@ static uint64_t psci_system_off2(uint64_t type, uint64_t cookie) return res.a0; } -static uint64_t psci_features(uint32_t func_id) +static u64 psci_features(u32 func_id) { struct arm_smccc_res res; @@ -110,7 +108,7 @@ static void enter_guest(struct kvm_vcpu *vcpu) static void assert_vcpu_reset(struct kvm_vcpu *vcpu) { - uint64_t obs_pc, obs_x0; + u64 obs_pc, obs_x0; obs_pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc)); obs_x0 = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.regs[0])); @@ -123,9 +121,9 @@ static void assert_vcpu_reset(struct kvm_vcpu *vcpu) obs_x0, CPU_ON_CONTEXT_ID); } -static void guest_test_cpu_on(uint64_t target_cpu) +static void guest_test_cpu_on(u64 target_cpu) { - uint64_t target_state; + u64 target_state; GUEST_ASSERT(!psci_cpu_on(target_cpu, CPU_ON_ENTRY_ADDR, CPU_ON_CONTEXT_ID)); @@ -142,7 +140,7 @@ static void guest_test_cpu_on(uint64_t target_cpu) static void host_test_cpu_on(void) { struct kvm_vcpu *source, *target; - uint64_t target_mpidr; + u64 target_mpidr; struct kvm_vm *vm; struct ucall uc; @@ -166,7 +164,7 @@ static void host_test_cpu_on(void) static void guest_test_system_suspend(void) { - uint64_t ret; + u64 ret; /* assert that SYSTEM_SUSPEND is discoverable */ GUEST_ASSERT(!psci_features(PSCI_1_0_FN_SYSTEM_SUSPEND)); @@ -200,7 +198,7 @@ static void host_test_system_suspend(void) static void guest_test_system_off2(void) { - uint64_t ret; + u64 ret; /* assert that SYSTEM_OFF2 is discoverable */ GUEST_ASSERT(psci_features(PSCI_1_3_FN_SYSTEM_OFF2) & @@ -238,7 +236,7 @@ static void host_test_system_off2(void) { struct kvm_vcpu *source, *target; struct kvm_mp_state mps; - uint64_t psci_version = 0; + u64 psci_version = 0; int nr_shutdowns = 0; struct kvm_run *run; struct ucall uc; diff --git a/tools/testing/selftests/kvm/arm64/sea_to_user.c b/tools/testing/selftests/kvm/arm64/sea_to_user.c index 573dd790aeb8..e96d8982c28b 100644 --- a/tools/testing/selftests/kvm/arm64/sea_to_user.c +++ b/tools/testing/selftests/kvm/arm64/sea_to_user.c @@ -51,18 +51,16 @@ #define EINJ_OFFSET 0x01234badUL #define EINJ_GVA ((START_GVA) + (EINJ_OFFSET)) -static vm_paddr_t einj_gpa; +static gpa_t einj_gpa; static void *einj_hva; -static uint64_t einj_hpa; +static u64 einj_hpa; static bool far_invalid; -static uint64_t translate_to_host_paddr(unsigned long vaddr) +static u64 translate_hva_to_hpa(unsigned long hva) { - uint64_t pinfo; - int64_t offset = vaddr / getpagesize() * sizeof(pinfo); + u64 pinfo; + s64 offset = hva / getpagesize() * sizeof(pinfo); int fd; - uint64_t page_addr; - uint64_t paddr; fd = open("/proc/self/pagemap", O_RDONLY); if (fd < 0) @@ -77,12 +75,11 @@ static uint64_t translate_to_host_paddr(unsigned long vaddr) if ((pinfo & PAGE_PRESENT) == 0) ksft_exit_fail_perror("Page not present"); - page_addr = (pinfo & PAGE_PHYSICAL) << MIN_PAGE_SHIFT; - paddr = page_addr + (vaddr & (getpagesize() - 1)); - return paddr; + return ((pinfo & PAGE_PHYSICAL) << MIN_PAGE_SHIFT) + + (hva & (getpagesize() - 1)); } -static void write_einj_entry(const char *einj_path, uint64_t val) +static void write_einj_entry(const char *einj_path, u64 val) { char cmd[256] = {0}; FILE *cmdfile = NULL; @@ -96,7 +93,7 @@ static void write_einj_entry(const char *einj_path, uint64_t val) ksft_exit_fail_perror("Failed to write EINJ entry"); } -static void inject_uer(uint64_t paddr) +static void inject_uer(u64 hpa) { if (access("/sys/firmware/acpi/tables/EINJ", R_OK) == -1) ksft_test_result_skip("EINJ table no available in firmware"); @@ -106,7 +103,7 @@ static void inject_uer(uint64_t paddr) write_einj_entry(EINJ_ETYPE, ERROR_TYPE_MEMORY_UER); write_einj_entry(EINJ_FLAGS, MASK_MEMORY_UER); - write_einj_entry(EINJ_ADDR, paddr); + write_einj_entry(EINJ_ADDR, hpa); write_einj_entry(EINJ_MASK, ~0x0UL); write_einj_entry(EINJ_NOTRIGGER, 1); write_einj_entry(EINJ_DOIT, 1); @@ -145,10 +142,10 @@ static void setup_sigbus_handler(void) static void guest_code(void) { - uint64_t guest_data; + u64 guest_data; /* Consumes error will cause a SEA. */ - guest_data = *(uint64_t *)EINJ_GVA; + guest_data = *(u64 *)EINJ_GVA; GUEST_FAIL("Poison not protected by SEA: gva=%#lx, guest_data=%#lx\n", EINJ_GVA, guest_data); @@ -253,8 +250,8 @@ static struct kvm_vm *vm_create_with_sea_handler(struct kvm_vcpu **vcpu) size_t backing_page_size; size_t guest_page_size; size_t alignment; - uint64_t num_guest_pages; - vm_paddr_t start_gpa; + u64 num_guest_pages; + gpa_t start_gpa; enum vm_mem_backing_src_type src_type = VM_MEM_SRC_ANONYMOUS_HUGETLB_1GB; struct kvm_vm *vm; @@ -278,7 +275,7 @@ static struct kvm_vm *vm_create_with_sea_handler(struct kvm_vcpu **vcpu) vm_userspace_mem_region_add( /*vm=*/vm, /*src_type=*/src_type, - /*guest_paddr=*/start_gpa, + /*gpa=*/start_gpa, /*slot=*/1, /*npages=*/num_guest_pages, /*flags=*/0); @@ -292,18 +289,18 @@ static struct kvm_vm *vm_create_with_sea_handler(struct kvm_vcpu **vcpu) static void vm_inject_memory_uer(struct kvm_vm *vm) { - uint64_t guest_data; + u64 guest_data; einj_gpa = addr_gva2gpa(vm, EINJ_GVA); einj_hva = addr_gva2hva(vm, EINJ_GVA); /* Populate certain data before injecting UER. */ - *(uint64_t *)einj_hva = 0xBAADCAFE; - guest_data = *(uint64_t *)einj_hva; + *(u64 *)einj_hva = 0xBAADCAFE; + guest_data = *(u64 *)einj_hva; ksft_print_msg("Before EINJect: data=%#lx\n", guest_data); - einj_hpa = translate_to_host_paddr((unsigned long)einj_hva); + einj_hpa = translate_hva_to_hpa((unsigned long)einj_hva); ksft_print_msg("EINJ_GVA=%#lx, einj_gpa=%#lx, einj_hva=%p, einj_hpa=%#lx\n", EINJ_GVA, einj_gpa, einj_hva, einj_hpa); diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testing/selftests/kvm/arm64/set_id_regs.c index 3a7e5fe9ae7a..7429a1055df5 100644 --- a/tools/testing/selftests/kvm/arm64/set_id_regs.c +++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c @@ -30,20 +30,20 @@ struct reg_ftr_bits { char *name; bool sign; enum ftr_type type; - uint8_t shift; - uint64_t mask; + u8 shift; + u64 mask; /* * For FTR_EXACT, safe_val is used as the exact safe value. * For FTR_LOWER_SAFE, safe_val is used as the minimal safe value. */ - int64_t safe_val; + s64 safe_val; /* Allowed to be changed by the host after run */ bool mutable; }; struct test_feature_reg { - uint32_t reg; + u32 reg; const struct reg_ftr_bits *ftr_bits; }; @@ -275,9 +275,9 @@ static void guest_code(void) } /* Return a safe value to a given ftr_bits an ftr value */ -uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) +u64 get_safe_value(const struct reg_ftr_bits *ftr_bits, u64 ftr) { - uint64_t ftr_max = ftr_bits->mask >> ftr_bits->shift; + u64 ftr_max = ftr_bits->mask >> ftr_bits->shift; TEST_ASSERT(ftr_max > 1, "This test doesn't support single bit features"); @@ -329,16 +329,16 @@ uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) } /* Return an invalid value to a given ftr_bits an ftr value */ -uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) +u64 get_invalid_value(const struct reg_ftr_bits *ftr_bits, u64 ftr) { - uint64_t ftr_max = ftr_bits->mask >> ftr_bits->shift; + u64 ftr_max = ftr_bits->mask >> ftr_bits->shift; TEST_ASSERT(ftr_max > 1, "This test doesn't support single bit features"); if (ftr_bits->sign == FTR_UNSIGNED) { switch (ftr_bits->type) { case FTR_EXACT: - ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1); + ftr = max((u64)ftr_bits->safe_val + 1, ftr + 1); break; case FTR_LOWER_SAFE: ftr++; @@ -358,7 +358,7 @@ uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) } else if (ftr != ftr_max) { switch (ftr_bits->type) { case FTR_EXACT: - ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1); + ftr = max((u64)ftr_bits->safe_val + 1, ftr + 1); break; case FTR_LOWER_SAFE: ftr++; @@ -382,12 +382,12 @@ uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) return ftr; } -static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg, - const struct reg_ftr_bits *ftr_bits) +static u64 test_reg_set_success(struct kvm_vcpu *vcpu, u64 reg, + const struct reg_ftr_bits *ftr_bits) { - uint8_t shift = ftr_bits->shift; - uint64_t mask = ftr_bits->mask; - uint64_t val, new_val, ftr; + u8 shift = ftr_bits->shift; + u64 mask = ftr_bits->mask; + u64 val, new_val, ftr; val = vcpu_get_reg(vcpu, reg); ftr = (val & mask) >> shift; @@ -405,12 +405,12 @@ static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg, return new_val; } -static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg, +static void test_reg_set_fail(struct kvm_vcpu *vcpu, u64 reg, const struct reg_ftr_bits *ftr_bits) { - uint8_t shift = ftr_bits->shift; - uint64_t mask = ftr_bits->mask; - uint64_t val, old_val, ftr; + u8 shift = ftr_bits->shift; + u64 mask = ftr_bits->mask; + u64 val, old_val, ftr; int r; val = vcpu_get_reg(vcpu, reg); @@ -431,7 +431,7 @@ static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg, TEST_ASSERT_EQ(val, old_val); } -static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE]; +static u64 test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE]; #define encoding_to_range_idx(encoding) \ KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(encoding), sys_reg_Op1(encoding), \ @@ -441,7 +441,7 @@ static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE]; static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only) { - uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; + u64 masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; struct reg_mask_range range = { .addr = (__u64)masks, }; @@ -458,8 +458,8 @@ static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only) for (int i = 0; i < ARRAY_SIZE(test_regs); i++) { const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits; - uint32_t reg_id = test_regs[i].reg; - uint64_t reg = KVM_ARM64_SYS_REG(reg_id); + u32 reg_id = test_regs[i].reg; + u64 reg = KVM_ARM64_SYS_REG(reg_id); int idx; /* Get the index to masks array for the idreg */ @@ -489,11 +489,11 @@ static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only) #define MPAM_IDREG_TEST 6 static void test_user_set_mpam_reg(struct kvm_vcpu *vcpu) { - uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; + u64 masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; struct reg_mask_range range = { .addr = (__u64)masks, }; - uint64_t val; + u64 val; int idx, err; /* @@ -584,13 +584,13 @@ static void test_user_set_mpam_reg(struct kvm_vcpu *vcpu) #define MTE_IDREG_TEST 1 static void test_user_set_mte_reg(struct kvm_vcpu *vcpu) { - uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; + u64 masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; struct reg_mask_range range = { .addr = (__u64)masks, }; - uint64_t val; - uint64_t mte; - uint64_t mte_frac; + u64 val; + u64 mte; + u64 mte_frac; int idx, err; val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1)); @@ -644,7 +644,7 @@ static void test_user_set_mte_reg(struct kvm_vcpu *vcpu) ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac no longer 0xF\n"); } -static uint64_t reset_mutable_bits(uint32_t id, uint64_t val) +static u64 reset_mutable_bits(u32 id, u64 val) { struct test_feature_reg *reg = NULL; @@ -674,7 +674,7 @@ static void test_guest_reg_read(struct kvm_vcpu *vcpu) struct ucall uc; while (!done) { - uint64_t val; + u64 val; vcpu_run(vcpu); @@ -707,7 +707,7 @@ static void test_guest_reg_read(struct kvm_vcpu *vcpu) static void test_clidr(struct kvm_vcpu *vcpu) { - uint64_t clidr; + u64 clidr; int level; clidr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1)); @@ -772,10 +772,10 @@ static void test_vcpu_non_ftr_id_regs(struct kvm_vcpu *vcpu) ksft_test_result_pass("%s\n", __func__); } -static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t encoding) +static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, u32 encoding) { size_t idx = encoding_to_range_idx(encoding); - uint64_t observed; + u64 observed; observed = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding)); TEST_ASSERT_EQ(reset_mutable_bits(encoding, test_reg_vals[idx]), @@ -808,7 +808,7 @@ int main(void) struct kvm_vcpu *vcpu; struct kvm_vm *vm; bool aarch64_only; - uint64_t val, el0; + u64 val, el0; int test_cnt, i, j; TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES)); diff --git a/tools/testing/selftests/kvm/arm64/smccc_filter.c b/tools/testing/selftests/kvm/arm64/smccc_filter.c index 1763b9d45400..21e41880261b 100644 --- a/tools/testing/selftests/kvm/arm64/smccc_filter.c +++ b/tools/testing/selftests/kvm/arm64/smccc_filter.c @@ -37,7 +37,7 @@ static bool test_runs_at_el2(void) for (conduit = test_runs_at_el2() ? SMC_INSN : HVC_INSN; \ conduit <= SMC_INSN; conduit++) -static void guest_main(uint32_t func_id, enum smccc_conduit conduit) +static void guest_main(u32 func_id, enum smccc_conduit conduit) { struct arm_smccc_res res; @@ -49,7 +49,7 @@ static void guest_main(uint32_t func_id, enum smccc_conduit conduit) GUEST_SYNC(res.a0); } -static int __set_smccc_filter(struct kvm_vm *vm, uint32_t start, uint32_t nr_functions, +static int __set_smccc_filter(struct kvm_vm *vm, u32 start, u32 nr_functions, enum kvm_smccc_filter_action action) { struct kvm_smccc_filter filter = { @@ -62,7 +62,7 @@ static int __set_smccc_filter(struct kvm_vm *vm, uint32_t start, uint32_t nr_fun KVM_ARM_VM_SMCCC_FILTER, &filter); } -static void set_smccc_filter(struct kvm_vm *vm, uint32_t start, uint32_t nr_functions, +static void set_smccc_filter(struct kvm_vm *vm, u32 start, u32 nr_functions, enum kvm_smccc_filter_action action) { int ret = __set_smccc_filter(vm, start, nr_functions, action); @@ -112,7 +112,7 @@ static void test_filter_reserved_range(void) { struct kvm_vcpu *vcpu; struct kvm_vm *vm = setup_vm(&vcpu); - uint32_t smc64_fn; + u32 smc64_fn; int r; r = __set_smccc_filter(vm, ARM_SMCCC_ARCH_WORKAROUND_1, @@ -217,7 +217,7 @@ static void test_filter_denied(void) } } -static void expect_call_fwd_to_user(struct kvm_vcpu *vcpu, uint32_t func_id, +static void expect_call_fwd_to_user(struct kvm_vcpu *vcpu, u32 func_id, enum smccc_conduit conduit) { struct kvm_run *run = vcpu->run; diff --git a/tools/testing/selftests/kvm/arm64/vgic_init.c b/tools/testing/selftests/kvm/arm64/vgic_init.c index 8d6d3a4ae4db..47e34b43afb2 100644 --- a/tools/testing/selftests/kvm/arm64/vgic_init.c +++ b/tools/testing/selftests/kvm/arm64/vgic_init.c @@ -19,7 +19,7 @@ #define NR_VCPUS 4 -#define REG_OFFSET(vcpu, offset) (((uint64_t)vcpu << 32) | offset) +#define REG_OFFSET(vcpu, offset) (((u64)vcpu << 32) | offset) #define VGIC_DEV_IS_V2(_d) ((_d) == KVM_DEV_TYPE_ARM_VGIC_V2) #define VGIC_DEV_IS_V3(_d) ((_d) == KVM_DEV_TYPE_ARM_VGIC_V3) @@ -27,10 +27,10 @@ struct vm_gic { struct kvm_vm *vm; int gic_fd; - uint32_t gic_dev_type; + u32 gic_dev_type; }; -static uint64_t max_phys_size; +static u64 max_phys_size; /* * Helpers to access a redistributor register and verify the ioctl() failed or @@ -39,17 +39,17 @@ static uint64_t max_phys_size; static void v3_redist_reg_get_errno(int gicv3_fd, int vcpu, int offset, int want, const char *msg) { - uint32_t ignored_val; + u32 ignored_val; int ret = __kvm_device_attr_get(gicv3_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, REG_OFFSET(vcpu, offset), &ignored_val); TEST_ASSERT(ret && errno == want, "%s; want errno = %d", msg, want); } -static void v3_redist_reg_get(int gicv3_fd, int vcpu, int offset, uint32_t want, +static void v3_redist_reg_get(int gicv3_fd, int vcpu, int offset, u32 want, const char *msg) { - uint32_t val; + u32 val; kvm_device_attr_get(gicv3_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, REG_OFFSET(vcpu, offset), &val); @@ -71,8 +71,8 @@ static int run_vcpu(struct kvm_vcpu *vcpu) return __vcpu_run(vcpu) ? -errno : 0; } -static struct vm_gic vm_gic_create_with_vcpus(uint32_t gic_dev_type, - uint32_t nr_vcpus, +static struct vm_gic vm_gic_create_with_vcpus(u32 gic_dev_type, + u32 nr_vcpus, struct kvm_vcpu *vcpus[]) { struct vm_gic v; @@ -84,7 +84,7 @@ static struct vm_gic vm_gic_create_with_vcpus(uint32_t gic_dev_type, return v; } -static struct vm_gic vm_gic_create_barebones(uint32_t gic_dev_type) +static struct vm_gic vm_gic_create_barebones(u32 gic_dev_type) { struct vm_gic v; @@ -103,9 +103,9 @@ static void vm_gic_destroy(struct vm_gic *v) } struct vgic_region_attr { - uint64_t attr; - uint64_t size; - uint64_t alignment; + u64 attr; + u64 size; + u64 alignment; }; struct vgic_region_attr gic_v3_dist_region = { @@ -143,7 +143,7 @@ struct vgic_region_attr gic_v2_cpu_region = { static void subtest_dist_rdist(struct vm_gic *v) { int ret; - uint64_t addr; + u64 addr; struct vgic_region_attr rdist; /* CPU interface in GICv2*/ struct vgic_region_attr dist; @@ -223,7 +223,7 @@ static void subtest_dist_rdist(struct vm_gic *v) /* Test the new REDIST region API */ static void subtest_v3_redist_regions(struct vm_gic *v) { - uint64_t addr, expected_addr; + u64 addr, expected_addr; int ret; ret = __kvm_has_device_attr(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR, @@ -332,7 +332,7 @@ static void subtest_v3_redist_regions(struct vm_gic *v) * VGIC KVM device is created and initialized before the secondary CPUs * get created */ -static void test_vgic_then_vcpus(uint32_t gic_dev_type) +static void test_vgic_then_vcpus(u32 gic_dev_type) { struct kvm_vcpu *vcpus[NR_VCPUS]; struct vm_gic v; @@ -353,7 +353,7 @@ static void test_vgic_then_vcpus(uint32_t gic_dev_type) } /* All the VCPUs are created before the VGIC KVM device gets initialized */ -static void test_vcpus_then_vgic(uint32_t gic_dev_type) +static void test_vcpus_then_vgic(u32 gic_dev_type) { struct kvm_vcpu *vcpus[NR_VCPUS]; struct vm_gic v; @@ -408,7 +408,7 @@ static void test_v3_new_redist_regions(void) struct kvm_vcpu *vcpus[NR_VCPUS]; void *dummy = NULL; struct vm_gic v; - uint64_t addr; + u64 addr; int ret; v = vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, NR_VCPUS, vcpus); @@ -460,7 +460,7 @@ static void test_v3_new_redist_regions(void) static void test_v3_typer_accesses(void) { struct vm_gic v; - uint64_t addr; + u64 addr; int ret, i; v.vm = vm_create(NR_VCPUS); @@ -518,7 +518,7 @@ static void test_v3_typer_accesses(void) } static struct vm_gic vm_gic_v3_create_with_vcpuids(int nr_vcpus, - uint32_t vcpuids[]) + u32 vcpuids[]) { struct vm_gic v; int i; @@ -544,9 +544,9 @@ static struct vm_gic vm_gic_v3_create_with_vcpuids(int nr_vcpus, */ static void test_v3_last_bit_redist_regions(void) { - uint32_t vcpuids[] = { 0, 3, 5, 4, 1, 2 }; + u32 vcpuids[] = { 0, 3, 5, 4, 1, 2 }; struct vm_gic v; - uint64_t addr; + u64 addr; v = vm_gic_v3_create_with_vcpuids(ARRAY_SIZE(vcpuids), vcpuids); @@ -578,9 +578,9 @@ static void test_v3_last_bit_redist_regions(void) /* Test last bit with legacy region */ static void test_v3_last_bit_single_rdist(void) { - uint32_t vcpuids[] = { 0, 3, 5, 4, 1, 2 }; + u32 vcpuids[] = { 0, 3, 5, 4, 1, 2 }; struct vm_gic v; - uint64_t addr; + u64 addr; v = vm_gic_v3_create_with_vcpuids(ARRAY_SIZE(vcpuids), vcpuids); @@ -606,7 +606,7 @@ static void test_v3_redist_ipa_range_check_at_vcpu_run(void) struct kvm_vcpu *vcpus[NR_VCPUS]; struct vm_gic v; int ret, i; - uint64_t addr; + u64 addr; v = vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, 1, vcpus); @@ -638,7 +638,7 @@ static void test_v3_its_region(void) { struct kvm_vcpu *vcpus[NR_VCPUS]; struct vm_gic v; - uint64_t addr; + u64 addr; int its_fd, ret; v = vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, NR_VCPUS, vcpus); @@ -717,11 +717,11 @@ static void test_v3_nassgicap(void) /* * Returns 0 if it's possible to create GIC device of a given type (V2 or V3). */ -int test_kvm_device(uint32_t gic_dev_type) +int test_kvm_device(u32 gic_dev_type) { struct kvm_vcpu *vcpus[NR_VCPUS]; struct vm_gic v; - uint32_t other; + u32 other; int ret; v.vm = vm_create_with_vcpus(NR_VCPUS, guest_code, vcpus); @@ -968,7 +968,7 @@ static void test_v3_sysregs(void) kvm_vm_free(vm); } -void run_tests(uint32_t gic_dev_type) +void run_tests(u32 gic_dev_type) { test_vcpus_then_vgic(gic_dev_type); test_vgic_then_vcpus(gic_dev_type); diff --git a/tools/testing/selftests/kvm/arm64/vgic_irq.c b/tools/testing/selftests/kvm/arm64/vgic_irq.c index 2fb2c7939fe9..5e231998617e 100644 --- a/tools/testing/selftests/kvm/arm64/vgic_irq.c +++ b/tools/testing/selftests/kvm/arm64/vgic_irq.c @@ -24,12 +24,12 @@ * function. */ struct test_args { - uint32_t nr_irqs; /* number of KVM supported IRQs. */ + u32 nr_irqs; /* number of KVM supported IRQs. */ bool eoi_split; /* 1 is eoir+dir, 0 is eoir only */ bool level_sensitive; /* 1 is level, 0 is edge */ int kvm_max_routes; /* output of KVM_CAP_IRQ_ROUTING */ bool kvm_supports_irqfd; /* output of KVM_CAP_IRQFD */ - uint32_t shared_data; + u32 shared_data; }; /* @@ -64,15 +64,15 @@ typedef enum { struct kvm_inject_args { kvm_inject_cmd cmd; - uint32_t first_intid; - uint32_t num; + u32 first_intid; + u32 num; int level; bool expect_failure; }; /* Used on the guest side to perform the hypercall. */ -static void kvm_inject_call(kvm_inject_cmd cmd, uint32_t first_intid, - uint32_t num, int level, bool expect_failure); +static void kvm_inject_call(kvm_inject_cmd cmd, u32 first_intid, + u32 num, int level, bool expect_failure); /* Used on the host side to get the hypercall info. */ static void kvm_inject_get_call(struct kvm_vm *vm, struct ucall *uc, @@ -133,8 +133,8 @@ static struct kvm_inject_desc set_active_fns[] = { for_each_supported_inject_fn((args), (t), (f)) /* Shared between the guest main thread and the IRQ handlers. */ -volatile uint64_t irq_handled; -volatile uint32_t irqnr_received[MAX_SPI + 1]; +volatile u64 irq_handled; +volatile u32 irqnr_received[MAX_SPI + 1]; static void reset_stats(void) { @@ -145,25 +145,25 @@ static void reset_stats(void) irqnr_received[i] = 0; } -static uint64_t gic_read_ap1r0(void) +static u64 gic_read_ap1r0(void) { - uint64_t reg = read_sysreg_s(SYS_ICC_AP1R0_EL1); + u64 reg = read_sysreg_s(SYS_ICC_AP1R0_EL1); dsb(sy); return reg; } -static void gic_write_ap1r0(uint64_t val) +static void gic_write_ap1r0(u64 val) { write_sysreg_s(val, SYS_ICC_AP1R0_EL1); isb(); } -static void guest_set_irq_line(uint32_t intid, uint32_t level); +static void guest_set_irq_line(u32 intid, u32 level); static void guest_irq_generic_handler(bool eoi_split, bool level_sensitive) { - uint32_t intid = gic_get_and_ack_irq(); + u32 intid = gic_get_and_ack_irq(); if (intid == IAR_SPURIOUS) return; @@ -189,8 +189,8 @@ static void guest_irq_generic_handler(bool eoi_split, bool level_sensitive) GUEST_ASSERT(!gic_irq_get_pending(intid)); } -static void kvm_inject_call(kvm_inject_cmd cmd, uint32_t first_intid, - uint32_t num, int level, bool expect_failure) +static void kvm_inject_call(kvm_inject_cmd cmd, u32 first_intid, + u32 num, int level, bool expect_failure) { struct kvm_inject_args args = { .cmd = cmd, @@ -204,7 +204,7 @@ static void kvm_inject_call(kvm_inject_cmd cmd, uint32_t first_intid, #define GUEST_ASSERT_IAR_EMPTY() \ do { \ - uint32_t _intid; \ + u32 _intid; \ _intid = gic_get_and_ack_irq(); \ GUEST_ASSERT(_intid == IAR_SPURIOUS); \ } while (0) @@ -237,13 +237,13 @@ static void reset_priorities(struct test_args *args) gic_set_priority(i, IRQ_DEFAULT_PRIO_REG); } -static void guest_set_irq_line(uint32_t intid, uint32_t level) +static void guest_set_irq_line(u32 intid, u32 level) { kvm_inject_call(KVM_SET_IRQ_LINE, intid, 1, level, false); } static void test_inject_fail(struct test_args *args, - uint32_t intid, kvm_inject_cmd cmd) + u32 intid, kvm_inject_cmd cmd) { reset_stats(); @@ -255,10 +255,10 @@ static void test_inject_fail(struct test_args *args, } static void guest_inject(struct test_args *args, - uint32_t first_intid, uint32_t num, - kvm_inject_cmd cmd) + u32 first_intid, u32 num, + kvm_inject_cmd cmd) { - uint32_t i; + u32 i; reset_stats(); @@ -292,10 +292,10 @@ static void guest_inject(struct test_args *args, * deactivated yet. */ static void guest_restore_active(struct test_args *args, - uint32_t first_intid, uint32_t num, - kvm_inject_cmd cmd) + u32 first_intid, u32 num, + kvm_inject_cmd cmd) { - uint32_t prio, intid, ap1r; + u32 prio, intid, ap1r; int i; /* @@ -342,9 +342,9 @@ static void guest_restore_active(struct test_args *args, * This function should only be used in test_inject_preemption (with IRQs * masked). */ -static uint32_t wait_for_and_activate_irq(void) +static u32 wait_for_and_activate_irq(void) { - uint32_t intid; + u32 intid; do { asm volatile("wfi" : : : "memory"); @@ -360,11 +360,11 @@ static uint32_t wait_for_and_activate_irq(void) * interrupts for the whole test. */ static void test_inject_preemption(struct test_args *args, - uint32_t first_intid, int num, + u32 first_intid, int num, const unsigned long *exclude, kvm_inject_cmd cmd) { - uint32_t intid, prio, step = KVM_PRIO_STEPS; + u32 intid, prio, step = KVM_PRIO_STEPS; int i; /* Set the priorities of the first (KVM_NUM_PRIOS - 1) IRQs @@ -379,7 +379,7 @@ static void test_inject_preemption(struct test_args *args, local_irq_disable(); for (i = 0; i < num; i++) { - uint32_t tmp; + u32 tmp; intid = i + first_intid; if (exclude && test_bit(i, exclude)) @@ -431,7 +431,7 @@ static void test_inject_preemption(struct test_args *args, static void test_injection(struct test_args *args, struct kvm_inject_desc *f) { - uint32_t nr_irqs = args->nr_irqs; + u32 nr_irqs = args->nr_irqs; if (f->sgi) { guest_inject(args, MIN_SGI, 1, f->cmd); @@ -451,7 +451,7 @@ static void test_injection(struct test_args *args, struct kvm_inject_desc *f) static void test_injection_failure(struct test_args *args, struct kvm_inject_desc *f) { - uint32_t bad_intid[] = { args->nr_irqs, 1020, 1024, 1120, 5120, ~0U, }; + u32 bad_intid[] = { args->nr_irqs, 1020, 1024, 1120, 5120, ~0U, }; int i; for (i = 0; i < ARRAY_SIZE(bad_intid); i++) @@ -490,7 +490,7 @@ static void test_restore_active(struct test_args *args, struct kvm_inject_desc * static void guest_code(struct test_args *args) { - uint32_t i, nr_irqs = args->nr_irqs; + u32 i, nr_irqs = args->nr_irqs; bool level_sensitive = args->level_sensitive; struct kvm_inject_desc *f, *inject_fns; @@ -529,8 +529,8 @@ static void guest_code(struct test_args *args) GUEST_DONE(); } -static void kvm_irq_line_check(struct kvm_vm *vm, uint32_t intid, int level, - struct test_args *test_args, bool expect_failure) +static void kvm_irq_line_check(struct kvm_vm *vm, u32 intid, int level, + struct test_args *test_args, bool expect_failure) { int ret; @@ -548,8 +548,8 @@ static void kvm_irq_line_check(struct kvm_vm *vm, uint32_t intid, int level, } } -void kvm_irq_set_level_info_check(int gic_fd, uint32_t intid, int level, - bool expect_failure) +void kvm_irq_set_level_info_check(int gic_fd, u32 intid, int level, + bool expect_failure) { if (!expect_failure) { kvm_irq_set_level_info(gic_fd, intid, level); @@ -573,17 +573,18 @@ void kvm_irq_set_level_info_check(int gic_fd, uint32_t intid, int level, } static void kvm_set_gsi_routing_irqchip_check(struct kvm_vm *vm, - uint32_t intid, uint32_t num, uint32_t kvm_max_routes, - bool expect_failure) + u32 intid, u32 num, + u32 kvm_max_routes, + bool expect_failure) { struct kvm_irq_routing *routing; int ret; - uint64_t i; + u64 i; assert(num <= kvm_max_routes && kvm_max_routes <= KVM_MAX_IRQ_ROUTES); routing = kvm_gsi_routing_create(); - for (i = intid; i < (uint64_t)intid + num; i++) + for (i = intid; i < (u64)intid + num; i++) kvm_gsi_routing_irqchip_add(routing, i - MIN_SPI, i - MIN_SPI); if (!expect_failure) { @@ -591,7 +592,7 @@ static void kvm_set_gsi_routing_irqchip_check(struct kvm_vm *vm, } else { ret = _kvm_gsi_routing_write(vm, routing); /* The kernel only checks e->irqchip.pin >= KVM_IRQCHIP_NUM_PINS */ - if (((uint64_t)intid + num - 1 - MIN_SPI) >= KVM_IRQCHIP_NUM_PINS) + if (((u64)intid + num - 1 - MIN_SPI) >= KVM_IRQCHIP_NUM_PINS) TEST_ASSERT(ret != 0 && errno == EINVAL, "Bad intid %u did not cause KVM_SET_GSI_ROUTING " "error: rc: %i errno: %i", intid, ret, errno); @@ -602,7 +603,7 @@ static void kvm_set_gsi_routing_irqchip_check(struct kvm_vm *vm, } } -static void kvm_irq_write_ispendr_check(int gic_fd, uint32_t intid, +static void kvm_irq_write_ispendr_check(int gic_fd, u32 intid, struct kvm_vcpu *vcpu, bool expect_failure) { @@ -618,13 +619,13 @@ static void kvm_irq_write_ispendr_check(int gic_fd, uint32_t intid, } static void kvm_routing_and_irqfd_check(struct kvm_vm *vm, - uint32_t intid, uint32_t num, uint32_t kvm_max_routes, - bool expect_failure) + u32 intid, u32 num, u32 kvm_max_routes, + bool expect_failure) { int fd[MAX_SPI]; - uint64_t val; + u64 val; int ret, f; - uint64_t i; + u64 i; /* * There is no way to try injecting an SGI or PPI as the interface @@ -643,29 +644,29 @@ static void kvm_routing_and_irqfd_check(struct kvm_vm *vm, * that no actual interrupt was injected for those cases. */ - for (f = 0, i = intid; i < (uint64_t)intid + num; i++, f++) + for (f = 0, i = intid; i < (u64)intid + num; i++, f++) fd[f] = kvm_new_eventfd(); - for (f = 0, i = intid; i < (uint64_t)intid + num; i++, f++) { - assert(i <= (uint64_t)UINT_MAX); + for (f = 0, i = intid; i < (u64)intid + num; i++, f++) { + assert(i <= (u64)UINT_MAX); kvm_assign_irqfd(vm, i - MIN_SPI, fd[f]); } - for (f = 0, i = intid; i < (uint64_t)intid + num; i++, f++) { + for (f = 0, i = intid; i < (u64)intid + num; i++, f++) { val = 1; - ret = write(fd[f], &val, sizeof(uint64_t)); - TEST_ASSERT(ret == sizeof(uint64_t), + ret = write(fd[f], &val, sizeof(u64)); + TEST_ASSERT(ret == sizeof(u64), __KVM_SYSCALL_ERROR("write()", ret)); } - for (f = 0, i = intid; i < (uint64_t)intid + num; i++, f++) + for (f = 0, i = intid; i < (u64)intid + num; i++, f++) kvm_close(fd[f]); } /* handles the valid case: intid=0xffffffff num=1 */ #define for_each_intid(first, num, tmp, i) \ for ((tmp) = (i) = (first); \ - (tmp) < (uint64_t)(first) + (uint64_t)(num); \ + (tmp) < (u64)(first) + (u64)(num); \ (tmp)++, (i)++) static void run_guest_cmd(struct kvm_vcpu *vcpu, int gic_fd, @@ -673,13 +674,13 @@ static void run_guest_cmd(struct kvm_vcpu *vcpu, int gic_fd, struct test_args *test_args) { kvm_inject_cmd cmd = inject_args->cmd; - uint32_t intid = inject_args->first_intid; - uint32_t num = inject_args->num; + u32 intid = inject_args->first_intid; + u32 num = inject_args->num; int level = inject_args->level; bool expect_failure = inject_args->expect_failure; struct kvm_vm *vm = vcpu->vm; - uint64_t tmp; - uint32_t i; + u64 tmp; + u32 i; /* handles the valid case: intid=0xffffffff num=1 */ assert(intid < UINT_MAX - num || num == 1); @@ -731,7 +732,7 @@ static void kvm_inject_get_call(struct kvm_vm *vm, struct ucall *uc, struct kvm_inject_args *args) { struct kvm_inject_args *kvm_args_hva; - vm_vaddr_t kvm_args_gva; + gva_t kvm_args_gva; kvm_args_gva = uc->args[1]; kvm_args_hva = (struct kvm_inject_args *)addr_gva2hva(vm, kvm_args_gva); @@ -745,14 +746,14 @@ static void print_args(struct test_args *args) args->eoi_split); } -static void test_vgic(uint32_t nr_irqs, bool level_sensitive, bool eoi_split) +static void test_vgic(u32 nr_irqs, bool level_sensitive, bool eoi_split) { struct ucall uc; int gic_fd; struct kvm_vcpu *vcpu; struct kvm_vm *vm; struct kvm_inject_args inject_args; - vm_vaddr_t args_gva; + gva_t args_gva; struct test_args args = { .nr_irqs = nr_irqs, @@ -770,7 +771,7 @@ static void test_vgic(uint32_t nr_irqs, bool level_sensitive, bool eoi_split) vcpu_init_descriptor_tables(vcpu); /* Setup the guest args page (so it gets the args). */ - args_gva = vm_vaddr_alloc_page(vm); + args_gva = vm_alloc_page(vm); memcpy(addr_gva2hva(vm, args_gva), &args, sizeof(args)); vcpu_args_set(vcpu, 1, args_gva); @@ -810,7 +811,7 @@ static void guest_code_asym_dir(struct test_args *args, int cpuid) gic_set_priority_mask(CPU_PRIO_MASK); if (cpuid == 0) { - uint32_t intid; + u32 intid; local_irq_disable(); @@ -848,7 +849,7 @@ static void guest_code_asym_dir(struct test_args *args, int cpuid) static void guest_code_group_en(struct test_args *args, int cpuid) { - uint32_t intid; + u32 intid; gic_init(GIC_V3, 2); @@ -896,7 +897,7 @@ static void guest_code_group_en(struct test_args *args, int cpuid) static void guest_code_timer_spi(struct test_args *args, int cpuid) { - uint32_t intid; + u32 intid; u64 val; gic_init(GIC_V3, 2); @@ -986,7 +987,7 @@ static void test_vgic_two_cpus(void *gcode) struct kvm_vcpu *vcpus[2]; struct test_args args = {}; struct kvm_vm *vm; - vm_vaddr_t args_gva; + gva_t args_gva; int gic_fd, ret; vm = vm_create_with_vcpus(2, gcode, vcpus); @@ -996,7 +997,7 @@ static void test_vgic_two_cpus(void *gcode) vcpu_init_descriptor_tables(vcpus[1]); /* Setup the guest args page (so it gets the args). */ - args_gva = vm_vaddr_alloc_page(vm); + args_gva = vm_alloc_page(vm); memcpy(addr_gva2hva(vm, args_gva), &args, sizeof(args)); vcpu_args_set(vcpus[0], 2, args_gva, 0); vcpu_args_set(vcpus[1], 2, args_gva, 1); @@ -1033,7 +1034,7 @@ static void help(const char *name) int main(int argc, char **argv) { - uint32_t nr_irqs = 64; + u32 nr_irqs = 64; bool default_args = true; bool level_sensitive = false; int opt; diff --git a/tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c b/tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c index e857a605f577..d64d434d3f06 100644 --- a/tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c +++ b/tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c @@ -23,7 +23,7 @@ #define GIC_LPI_OFFSET 8192 static size_t nr_iterations = 1000; -static vm_paddr_t gpa_base; +static gpa_t gpa_base; static struct kvm_vm *vm; static struct kvm_vcpu **vcpus; @@ -35,14 +35,14 @@ static struct test_data { u32 nr_devices; u32 nr_event_ids; - vm_paddr_t device_table; - vm_paddr_t collection_table; - vm_paddr_t cmdq_base; + gpa_t device_table; + gpa_t collection_table; + gpa_t cmdq_base; void *cmdq_base_va; - vm_paddr_t itt_tables; + gpa_t itt_tables; - vm_paddr_t lpi_prop_table; - vm_paddr_t lpi_pend_tables; + gpa_t lpi_prop_table; + gpa_t lpi_pend_tables; } test_data = { .nr_cpus = 1, .nr_devices = 1, @@ -73,7 +73,7 @@ static void guest_setup_its_mappings(void) /* Round-robin the LPIs to all of the vCPUs in the VM */ coll_id = 0; for (device_id = 0; device_id < nr_devices; device_id++) { - vm_paddr_t itt_base = test_data.itt_tables + (device_id * SZ_64K); + gpa_t itt_base = test_data.itt_tables + (device_id * SZ_64K); its_send_mapd_cmd(test_data.cmdq_base_va, device_id, itt_base, SZ_64K, true); @@ -188,7 +188,7 @@ static void setup_test_data(void) size_t pages_per_64k = vm_calc_num_guest_pages(vm->mode, SZ_64K); u32 nr_devices = test_data.nr_devices; u32 nr_cpus = test_data.nr_cpus; - vm_paddr_t cmdq_base; + gpa_t cmdq_base; test_data.device_table = vm_phy_pages_alloc(vm, pages_per_64k, gpa_base, @@ -224,7 +224,7 @@ static void setup_gic(void) static void signal_lpi(u32 device_id, u32 event_id) { - vm_paddr_t db_addr = GITS_BASE_GPA + GITS_TRANSLATER; + gpa_t db_addr = GITS_BASE_GPA + GITS_TRANSLATER; struct kvm_msi msi = { .address_lo = db_addr, diff --git a/tools/testing/selftests/kvm/arm64/vgic_v5.c b/tools/testing/selftests/kvm/arm64/vgic_v5.c index 3ce6cf37a629..d785b660d847 100644 --- a/tools/testing/selftests/kvm/arm64/vgic_v5.c +++ b/tools/testing/selftests/kvm/arm64/vgic_v5.c @@ -17,10 +17,10 @@ struct vm_gic { struct kvm_vm *vm; int gic_fd; - uint32_t gic_dev_type; + u32 gic_dev_type; }; -static uint64_t max_phys_size; +static u64 max_phys_size; #define GUEST_CMD_IRQ_CDIA 10 #define GUEST_CMD_IRQ_DIEOI 11 @@ -96,7 +96,7 @@ static void vm_gic_destroy(struct vm_gic *v) kvm_vm_free(v->vm); } -static void test_vgic_v5_ppis(uint32_t gic_dev_type) +static void test_vgic_v5_ppis(u32 gic_dev_type) { struct kvm_vcpu *vcpus[NR_VCPUS]; struct ucall uc; @@ -173,7 +173,7 @@ static void test_vgic_v5_ppis(uint32_t gic_dev_type) /* * Returns 0 if it's possible to create GIC device of a given type (V5). */ -int test_kvm_device(uint32_t gic_dev_type) +int test_kvm_device(u32 gic_dev_type) { struct kvm_vcpu *vcpus[NR_VCPUS]; struct vm_gic v; @@ -199,7 +199,7 @@ int test_kvm_device(uint32_t gic_dev_type) return 0; } -void run_tests(uint32_t gic_dev_type) +void run_tests(u32 gic_dev_type) { pr_info("Test VGICv5 PPIs\n"); test_vgic_v5_ppis(gic_dev_type); diff --git a/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c b/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c index ae36325c022f..22223395969e 100644 --- a/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c +++ b/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c @@ -33,20 +33,20 @@ struct vpmu_vm { static struct vpmu_vm vpmu_vm; struct pmreg_sets { - uint64_t set_reg_id; - uint64_t clr_reg_id; + u64 set_reg_id; + u64 clr_reg_id; }; #define PMREG_SET(set, clr) {.set_reg_id = set, .clr_reg_id = clr} -static uint64_t get_pmcr_n(uint64_t pmcr) +static u64 get_pmcr_n(u64 pmcr) { return FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); } -static uint64_t get_counters_mask(uint64_t n) +static u64 get_counters_mask(u64 n) { - uint64_t mask = BIT(ARMV8_PMU_CYCLE_IDX); + u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); if (n) mask |= GENMASK(n - 1, 0); @@ -89,7 +89,7 @@ static inline void write_sel_evtyper(int sel, unsigned long val) static void pmu_disable_reset(void) { - uint64_t pmcr = read_sysreg(pmcr_el0); + u64 pmcr = read_sysreg(pmcr_el0); /* Reset all counters, disabling them */ pmcr &= ~ARMV8_PMU_PMCR_E; @@ -169,7 +169,7 @@ struct pmc_accessor pmc_accessors[] = { #define GUEST_ASSERT_BITMAP_REG(regname, mask, set_expected) \ { \ - uint64_t _tval = read_sysreg(regname); \ + u64 _tval = read_sysreg(regname); \ \ if (set_expected) \ __GUEST_ASSERT((_tval & mask), \ @@ -185,7 +185,7 @@ struct pmc_accessor pmc_accessors[] = { * Check if @mask bits in {PMCNTEN,PMINTEN,PMOVS}{SET,CLR} registers * are set or cleared as specified in @set_expected. */ -static void check_bitmap_pmu_regs(uint64_t mask, bool set_expected) +static void check_bitmap_pmu_regs(u64 mask, bool set_expected) { GUEST_ASSERT_BITMAP_REG(pmcntenset_el0, mask, set_expected); GUEST_ASSERT_BITMAP_REG(pmcntenclr_el0, mask, set_expected); @@ -207,7 +207,7 @@ static void check_bitmap_pmu_regs(uint64_t mask, bool set_expected) */ static void test_bitmap_pmu_regs(int pmc_idx, bool set_op) { - uint64_t pmcr_n, test_bit = BIT(pmc_idx); + u64 pmcr_n, test_bit = BIT(pmc_idx); bool set_expected = false; if (set_op) { @@ -232,7 +232,7 @@ static void test_bitmap_pmu_regs(int pmc_idx, bool set_op) */ static void test_access_pmc_regs(struct pmc_accessor *acc, int pmc_idx) { - uint64_t write_data, read_data; + u64 write_data, read_data; /* Disable all PMCs and reset all PMCs to zero. */ pmu_disable_reset(); @@ -287,11 +287,11 @@ static void test_access_pmc_regs(struct pmc_accessor *acc, int pmc_idx) } #define INVALID_EC (-1ul) -uint64_t expected_ec = INVALID_EC; +u64 expected_ec = INVALID_EC; static void guest_sync_handler(struct ex_regs *regs) { - uint64_t esr, ec; + u64 esr, ec; esr = read_sysreg(esr_el1); ec = ESR_ELx_EC(esr); @@ -351,9 +351,9 @@ static void test_access_invalid_pmc_regs(struct pmc_accessor *acc, int pmc_idx) * if reading/writing PMU registers for implemented or unimplemented * counters works as expected. */ -static void guest_code(uint64_t expected_pmcr_n) +static void guest_code(u64 expected_pmcr_n) { - uint64_t pmcr, pmcr_n, unimp_mask; + u64 pmcr, pmcr_n, unimp_mask; int i, pmc; __GUEST_ASSERT(expected_pmcr_n <= ARMV8_PMU_MAX_GENERAL_COUNTERS, @@ -402,12 +402,12 @@ static void guest_code(uint64_t expected_pmcr_n) static void create_vpmu_vm(void *guest_code) { struct kvm_vcpu_init init; - uint8_t pmuver, ec; - uint64_t dfr0, irq = 23; + u8 pmuver, ec; + u64 dfr0, irq = 23; struct kvm_device_attr irq_attr = { .group = KVM_ARM_VCPU_PMU_V3_CTRL, .attr = KVM_ARM_VCPU_PMU_V3_IRQ, - .addr = (uint64_t)&irq, + .addr = (u64)&irq, }; /* The test creates the vpmu_vm multiple times. Ensure a clean state */ @@ -443,7 +443,7 @@ static void destroy_vpmu_vm(void) kvm_vm_free(vpmu_vm.vm); } -static void run_vcpu(struct kvm_vcpu *vcpu, uint64_t pmcr_n) +static void run_vcpu(struct kvm_vcpu *vcpu, u64 pmcr_n) { struct ucall uc; @@ -489,9 +489,9 @@ static void test_create_vpmu_vm_with_nr_counters(unsigned int nr_counters, bool * Create a guest with one vCPU, set the PMCR_EL0.N for the vCPU to @pmcr_n, * and run the test. */ -static void run_access_test(uint64_t pmcr_n) +static void run_access_test(u64 pmcr_n) { - uint64_t sp; + u64 sp; struct kvm_vcpu *vcpu; struct kvm_vcpu_init init; @@ -514,7 +514,7 @@ static void run_access_test(uint64_t pmcr_n) aarch64_vcpu_setup(vcpu, &init); vcpu_init_descriptor_tables(vcpu); vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SP_EL1), sp); - vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), (uint64_t)guest_code); + vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), (u64)guest_code); run_vcpu(vcpu, pmcr_n); @@ -531,12 +531,12 @@ static struct pmreg_sets validity_check_reg_sets[] = { * Create a VM, and check if KVM handles the userspace accesses of * the PMU register sets in @validity_check_reg_sets[] correctly. */ -static void run_pmregs_validity_test(uint64_t pmcr_n) +static void run_pmregs_validity_test(u64 pmcr_n) { int i; struct kvm_vcpu *vcpu; - uint64_t set_reg_id, clr_reg_id, reg_val; - uint64_t valid_counters_mask, max_counters_mask; + u64 set_reg_id, clr_reg_id, reg_val; + u64 valid_counters_mask, max_counters_mask; test_create_vpmu_vm_with_nr_counters(pmcr_n, false); vcpu = vpmu_vm.vcpu; @@ -588,7 +588,7 @@ static void run_pmregs_validity_test(uint64_t pmcr_n) * the vCPU to @pmcr_n, which is larger than the host value. * The attempt should fail as @pmcr_n is too big to set for the vCPU. */ -static void run_error_test(uint64_t pmcr_n) +static void run_error_test(u64 pmcr_n) { pr_debug("Error test with pmcr_n %lu (larger than the host)\n", pmcr_n); @@ -600,9 +600,9 @@ static void run_error_test(uint64_t pmcr_n) * Return the default number of implemented PMU event counters excluding * the cycle counter (i.e. PMCR_EL0.N value) for the guest. */ -static uint64_t get_pmcr_n_limit(void) +static u64 get_pmcr_n_limit(void) { - uint64_t pmcr; + u64 pmcr; create_vpmu_vm(guest_code); pmcr = vcpu_get_reg(vpmu_vm.vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0)); @@ -624,7 +624,7 @@ static bool kvm_supports_nr_counters_attr(void) int main(void) { - uint64_t i, pmcr_n; + u64 i, pmcr_n; TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_PMU_V3)); TEST_REQUIRE(kvm_supports_vgic_v3()); diff --git a/tools/testing/selftests/kvm/coalesced_io_test.c b/tools/testing/selftests/kvm/coalesced_io_test.c index 60cb25454899..df4ed5e3877c 100644 --- a/tools/testing/selftests/kvm/coalesced_io_test.c +++ b/tools/testing/selftests/kvm/coalesced_io_test.c @@ -14,16 +14,16 @@ struct kvm_coalesced_io { struct kvm_coalesced_mmio_ring *ring; - uint32_t ring_size; - uint64_t mmio_gpa; - uint64_t *mmio; + u32 ring_size; + u64 mmio_gpa; + u64 *mmio; /* * x86-only, but define pio_port for all architectures to minimize the * amount of #ifdeffery and complexity, without having to sacrifice * verbose error messages. */ - uint8_t pio_port; + u8 pio_port; }; static struct kvm_coalesced_io kvm_builtin_io_ring; @@ -70,13 +70,13 @@ static void guest_code(struct kvm_coalesced_io *io) static void vcpu_run_and_verify_io_exit(struct kvm_vcpu *vcpu, struct kvm_coalesced_io *io, - uint32_t ring_start, - uint32_t expected_exit) + u32 ring_start, + u32 expected_exit) { const bool want_pio = expected_exit == KVM_EXIT_IO; struct kvm_coalesced_mmio_ring *ring = io->ring; struct kvm_run *run = vcpu->run; - uint32_t pio_value; + u32 pio_value; WRITE_ONCE(ring->first, ring_start); WRITE_ONCE(ring->last, ring_start); @@ -88,13 +88,13 @@ static void vcpu_run_and_verify_io_exit(struct kvm_vcpu *vcpu, * data_offset is garbage, e.g. an MMIO gpa. */ if (run->exit_reason == KVM_EXIT_IO) - pio_value = *(uint32_t *)((void *)run + run->io.data_offset); + pio_value = *(u32 *)((void *)run + run->io.data_offset); else pio_value = 0; TEST_ASSERT((!want_pio && (run->exit_reason == KVM_EXIT_MMIO && run->mmio.is_write && run->mmio.phys_addr == io->mmio_gpa && run->mmio.len == 8 && - *(uint64_t *)run->mmio.data == io->mmio_gpa + io->ring_size - 1)) || + *(u64 *)run->mmio.data == io->mmio_gpa + io->ring_size - 1)) || (want_pio && (run->exit_reason == KVM_EXIT_IO && run->io.port == io->pio_port && run->io.direction == KVM_EXIT_IO_OUT && run->io.count == 1 && pio_value == io->pio_port + io->ring_size - 1)), @@ -105,14 +105,14 @@ static void vcpu_run_and_verify_io_exit(struct kvm_vcpu *vcpu, want_pio ? (unsigned long long)io->pio_port : io->mmio_gpa, (want_pio ? io->pio_port : io->mmio_gpa) + io->ring_size - 1, run->exit_reason, run->exit_reason == KVM_EXIT_MMIO ? "MMIO" : run->exit_reason == KVM_EXIT_IO ? "PIO" : "other", - run->mmio.phys_addr, run->mmio.is_write, run->mmio.len, *(uint64_t *)run->mmio.data, + run->mmio.phys_addr, run->mmio.is_write, run->mmio.len, *(u64 *)run->mmio.data, run->io.port, run->io.direction, run->io.size, run->io.count, pio_value); } static void vcpu_run_and_verify_coalesced_io(struct kvm_vcpu *vcpu, struct kvm_coalesced_io *io, - uint32_t ring_start, - uint32_t expected_exit) + u32 ring_start, + u32 expected_exit) { struct kvm_coalesced_mmio_ring *ring = io->ring; int i; @@ -124,18 +124,18 @@ static void vcpu_run_and_verify_coalesced_io(struct kvm_vcpu *vcpu, ring->first, ring->last, io->ring_size, ring_start); for (i = 0; i < io->ring_size - 1; i++) { - uint32_t idx = (ring->first + i) % io->ring_size; + u32 idx = (ring->first + i) % io->ring_size; struct kvm_coalesced_mmio *entry = &ring->coalesced_mmio[idx]; #ifdef __x86_64__ if (i & 1) TEST_ASSERT(entry->phys_addr == io->pio_port && entry->len == 4 && entry->pio && - *(uint32_t *)entry->data == io->pio_port + i, + *(u32 *)entry->data == io->pio_port + i, "Wanted 4-byte port I/O 0x%x = 0x%x in entry %u, got %u-byte %s 0x%llx = 0x%x", io->pio_port, io->pio_port + i, i, entry->len, entry->pio ? "PIO" : "MMIO", - entry->phys_addr, *(uint32_t *)entry->data); + entry->phys_addr, *(u32 *)entry->data); else #endif TEST_ASSERT(entry->phys_addr == io->mmio_gpa && @@ -143,12 +143,12 @@ static void vcpu_run_and_verify_coalesced_io(struct kvm_vcpu *vcpu, "Wanted 8-byte MMIO to 0x%lx = %lx in entry %u, got %u-byte %s 0x%llx = 0x%lx", io->mmio_gpa, io->mmio_gpa + i, i, entry->len, entry->pio ? "PIO" : "MMIO", - entry->phys_addr, *(uint64_t *)entry->data); + entry->phys_addr, *(u64 *)entry->data); } } static void test_coalesced_io(struct kvm_vcpu *vcpu, - struct kvm_coalesced_io *io, uint32_t ring_start) + struct kvm_coalesced_io *io, u32 ring_start) { struct kvm_coalesced_mmio_ring *ring = io->ring; @@ -219,11 +219,11 @@ int main(int argc, char *argv[]) * the MMIO GPA identity mapped in the guest. */ .mmio_gpa = 4ull * SZ_1G, - .mmio = (uint64_t *)(4ull * SZ_1G), + .mmio = (u64 *)(4ull * SZ_1G), .pio_port = 0x80, }; - virt_map(vm, (uint64_t)kvm_builtin_io_ring.mmio, kvm_builtin_io_ring.mmio_gpa, 1); + virt_map(vm, (u64)kvm_builtin_io_ring.mmio, kvm_builtin_io_ring.mmio_gpa, 1); sync_global_to_guest(vm, kvm_builtin_io_ring); vcpu_args_set(vcpu, 1, &kvm_builtin_io_ring); diff --git a/tools/testing/selftests/kvm/demand_paging_test.c b/tools/testing/selftests/kvm/demand_paging_test.c index 0202b78f8680..302c4923d093 100644 --- a/tools/testing/selftests/kvm/demand_paging_test.c +++ b/tools/testing/selftests/kvm/demand_paging_test.c @@ -24,7 +24,7 @@ #ifdef __NR_userfaultfd static int nr_vcpus = 1; -static uint64_t guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE; +static u64 guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE; static size_t demand_paging_size; static char *guest_data_prototype; @@ -58,7 +58,7 @@ static int handle_uffd_page_request(int uffd_mode, int uffd, struct uffd_msg *msg) { pid_t tid = syscall(__NR_gettid); - uint64_t addr = msg->arg.pagefault.address; + u64 addr = msg->arg.pagefault.address; struct timespec start; struct timespec ts_diff; int r; @@ -68,7 +68,7 @@ static int handle_uffd_page_request(int uffd_mode, int uffd, if (uffd_mode == UFFDIO_REGISTER_MODE_MISSING) { struct uffdio_copy copy; - copy.src = (uint64_t)guest_data_prototype; + copy.src = (u64)guest_data_prototype; copy.dst = addr; copy.len = demand_paging_size; copy.mode = 0; @@ -138,7 +138,7 @@ struct test_params { bool partition_vcpu_memory_access; }; -static void prefault_mem(void *alias, uint64_t len) +static void prefault_mem(void *alias, u64 len) { size_t p; @@ -154,7 +154,7 @@ static void run_test(enum vm_guest_mode mode, void *arg) struct memstress_vcpu_args *vcpu_args; struct test_params *p = arg; struct uffd_desc **uffd_descs = NULL; - uint64_t uffd_region_size; + u64 uffd_region_size; struct timespec start; struct timespec ts_diff; double vcpu_paging_rate; diff --git a/tools/testing/selftests/kvm/dirty_log_perf_test.c b/tools/testing/selftests/kvm/dirty_log_perf_test.c index 0a1ea1d1e2d8..ef779fa91827 100644 --- a/tools/testing/selftests/kvm/dirty_log_perf_test.c +++ b/tools/testing/selftests/kvm/dirty_log_perf_test.c @@ -24,7 +24,7 @@ #define TEST_HOST_LOOP_N 2UL static int nr_vcpus = 1; -static uint64_t guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE; +static u64 guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE; static bool run_vcpus_while_disabling_dirty_logging; /* Host variables */ @@ -37,7 +37,7 @@ static void vcpu_worker(struct memstress_vcpu_args *vcpu_args) { struct kvm_vcpu *vcpu = vcpu_args->vcpu; int vcpu_idx = vcpu_args->vcpu_idx; - uint64_t pages_count = 0; + u64 pages_count = 0; struct kvm_run *run; struct timespec start; struct timespec ts_diff; @@ -93,11 +93,11 @@ static void vcpu_worker(struct memstress_vcpu_args *vcpu_args) struct test_params { unsigned long iterations; - uint64_t phys_offset; + u64 phys_offset; bool partition_vcpu_memory_access; enum vm_mem_backing_src_type backing_src; int slots; - uint32_t write_percent; + u32 write_percent; bool random_access; }; @@ -106,9 +106,9 @@ static void run_test(enum vm_guest_mode mode, void *arg) struct test_params *p = arg; struct kvm_vm *vm; unsigned long **bitmaps; - uint64_t guest_num_pages; - uint64_t host_num_pages; - uint64_t pages_per_slot; + u64 guest_num_pages; + u64 host_num_pages; + u64 pages_per_slot; struct timespec start; struct timespec ts_diff; struct timespec get_dirty_log_total = (struct timespec){0}; diff --git a/tools/testing/selftests/kvm/dirty_log_test.c b/tools/testing/selftests/kvm/dirty_log_test.c index 7627b328f18a..12446a4b6e8d 100644 --- a/tools/testing/selftests/kvm/dirty_log_test.c +++ b/tools/testing/selftests/kvm/dirty_log_test.c @@ -74,11 +74,11 @@ * the host. READ/WRITE_ONCE() should also be used with anything * that may change. */ -static uint64_t host_page_size; -static uint64_t guest_page_size; -static uint64_t guest_num_pages; -static uint64_t iteration; -static uint64_t nr_writes; +static u64 host_page_size; +static u64 guest_page_size; +static u64 guest_num_pages; +static u64 iteration; +static u64 nr_writes; static bool vcpu_stop; /* @@ -86,13 +86,13 @@ static bool vcpu_stop; * This will be set to the topmost valid physical address minus * the test memory size. */ -static uint64_t guest_test_phys_mem; +static u64 guest_test_phys_mem; /* * Guest virtual memory offset of the testing memory slot. * Must not conflict with identity mapped test code. */ -static uint64_t guest_test_virt_mem = DEFAULT_GUEST_TEST_MEM; +static u64 guest_test_virt_mem = DEFAULT_GUEST_TEST_MEM; /* * Continuously write to the first 8 bytes of a random pages within @@ -100,10 +100,10 @@ static uint64_t guest_test_virt_mem = DEFAULT_GUEST_TEST_MEM; */ static void guest_code(void) { - uint64_t addr; + u64 addr; #ifdef __s390x__ - uint64_t i; + u64 i; /* * On s390x, all pages of a 1M segment are initially marked as dirty @@ -113,7 +113,7 @@ static void guest_code(void) */ for (i = 0; i < guest_num_pages; i++) { addr = guest_test_virt_mem + i * guest_page_size; - vcpu_arch_put_guest(*(uint64_t *)addr, READ_ONCE(iteration)); + vcpu_arch_put_guest(*(u64 *)addr, READ_ONCE(iteration)); nr_writes++; } #endif @@ -125,7 +125,7 @@ static void guest_code(void) * guest_page_size; addr = align_down(addr, host_page_size); - vcpu_arch_put_guest(*(uint64_t *)addr, READ_ONCE(iteration)); + vcpu_arch_put_guest(*(u64 *)addr, READ_ONCE(iteration)); nr_writes++; } @@ -138,11 +138,11 @@ static bool host_quit; /* Points to the test VM memory region on which we track dirty logs */ static void *host_test_mem; -static uint64_t host_num_pages; +static u64 host_num_pages; /* For statistics only */ -static uint64_t host_dirty_count; -static uint64_t host_clear_count; +static u64 host_dirty_count; +static u64 host_clear_count; /* Whether dirty ring reset is requested, or finished */ static sem_t sem_vcpu_stop; @@ -169,7 +169,7 @@ static bool dirty_ring_vcpu_ring_full; * dirty gfn we've collected, so that if a mismatch of data found later in the * verifying process, we let it pass. */ -static uint64_t dirty_ring_last_page = -1ULL; +static u64 dirty_ring_last_page = -1ULL; /* * In addition to the above, it is possible (especially if this @@ -213,7 +213,7 @@ static uint64_t dirty_ring_last_page = -1ULL; * and also don't fail when it is reported in the next iteration, together with * an outdated iteration count. */ -static uint64_t dirty_ring_prev_iteration_last_page; +static u64 dirty_ring_prev_iteration_last_page; enum log_mode_t { /* Only use KVM_GET_DIRTY_LOG for logging */ @@ -236,7 +236,7 @@ static enum log_mode_t host_log_mode_option = LOG_MODE_ALL; /* Logging mode for current run */ static enum log_mode_t host_log_mode; static pthread_t vcpu_thread; -static uint32_t test_dirty_ring_count = TEST_DIRTY_RING_COUNT; +static u32 test_dirty_ring_count = TEST_DIRTY_RING_COUNT; static bool clear_log_supported(void) { @@ -255,15 +255,15 @@ static void clear_log_create_vm_done(struct kvm_vm *vm) } static void dirty_log_collect_dirty_pages(struct kvm_vcpu *vcpu, int slot, - void *bitmap, uint32_t num_pages, - uint32_t *unused) + void *bitmap, u32 num_pages, + u32 *unused) { kvm_vm_get_dirty_log(vcpu->vm, slot, bitmap); } static void clear_log_collect_dirty_pages(struct kvm_vcpu *vcpu, int slot, - void *bitmap, uint32_t num_pages, - uint32_t *unused) + void *bitmap, u32 num_pages, + u32 *unused) { kvm_vm_get_dirty_log(vcpu->vm, slot, bitmap); kvm_vm_clear_dirty_log(vcpu->vm, slot, bitmap, 0, num_pages); @@ -297,8 +297,8 @@ static bool dirty_ring_supported(void) static void dirty_ring_create_vm_done(struct kvm_vm *vm) { - uint64_t pages; - uint32_t limit; + u64 pages; + u32 limit; /* * We rely on vcpu exit due to full dirty ring state. Adjust @@ -333,12 +333,12 @@ static inline void dirty_gfn_set_collected(struct kvm_dirty_gfn *gfn) smp_store_release(&gfn->flags, KVM_DIRTY_GFN_F_RESET); } -static uint32_t dirty_ring_collect_one(struct kvm_dirty_gfn *dirty_gfns, - int slot, void *bitmap, - uint32_t num_pages, uint32_t *fetch_index) +static u32 dirty_ring_collect_one(struct kvm_dirty_gfn *dirty_gfns, + int slot, void *bitmap, + u32 num_pages, u32 *fetch_index) { struct kvm_dirty_gfn *cur; - uint32_t count = 0; + u32 count = 0; while (true) { cur = &dirty_gfns[*fetch_index % test_dirty_ring_count]; @@ -359,10 +359,10 @@ static uint32_t dirty_ring_collect_one(struct kvm_dirty_gfn *dirty_gfns, } static void dirty_ring_collect_dirty_pages(struct kvm_vcpu *vcpu, int slot, - void *bitmap, uint32_t num_pages, - uint32_t *ring_buf_idx) + void *bitmap, u32 num_pages, + u32 *ring_buf_idx) { - uint32_t count, cleared; + u32 count, cleared; /* Only have one vcpu */ count = dirty_ring_collect_one(vcpu_map_dirty_ring(vcpu), @@ -404,8 +404,8 @@ struct log_mode { void (*create_vm_done)(struct kvm_vm *vm); /* Hook to collect the dirty pages into the bitmap provided */ void (*collect_dirty_pages) (struct kvm_vcpu *vcpu, int slot, - void *bitmap, uint32_t num_pages, - uint32_t *ring_buf_idx); + void *bitmap, u32 num_pages, + u32 *ring_buf_idx); /* Hook to call when after each vcpu run */ void (*after_vcpu_run)(struct kvm_vcpu *vcpu); } log_modes[LOG_MODE_NUM] = { @@ -459,8 +459,8 @@ static void log_mode_create_vm_done(struct kvm_vm *vm) } static void log_mode_collect_dirty_pages(struct kvm_vcpu *vcpu, int slot, - void *bitmap, uint32_t num_pages, - uint32_t *ring_buf_idx) + void *bitmap, u32 num_pages, + u32 *ring_buf_idx) { struct log_mode *mode = &log_modes[host_log_mode]; @@ -494,11 +494,11 @@ static void *vcpu_worker(void *data) static void vm_dirty_log_verify(enum vm_guest_mode mode, unsigned long **bmap) { - uint64_t page, nr_dirty_pages = 0, nr_clean_pages = 0; - uint64_t step = vm_num_host_pages(mode, 1); + u64 page, nr_dirty_pages = 0, nr_clean_pages = 0; + u64 step = vm_num_host_pages(mode, 1); for (page = 0; page < host_num_pages; page += step) { - uint64_t val = *(uint64_t *)(host_test_mem + page * host_page_size); + u64 val = *(u64 *)(host_test_mem + page * host_page_size); bool bmap0_dirty = __test_and_clear_bit_le(page, bmap[0]); /* @@ -575,7 +575,7 @@ static void vm_dirty_log_verify(enum vm_guest_mode mode, unsigned long **bmap) } static struct kvm_vm *create_vm(enum vm_guest_mode mode, struct kvm_vcpu **vcpu, - uint64_t extra_mem_pages, void *guest_code) + u64 extra_mem_pages, void *guest_code) { struct kvm_vm *vm; @@ -592,7 +592,7 @@ static struct kvm_vm *create_vm(enum vm_guest_mode mode, struct kvm_vcpu **vcpu, struct test_params { unsigned long iterations; unsigned long interval; - uint64_t phys_offset; + u64 phys_offset; }; static void run_test(enum vm_guest_mode mode, void *arg) @@ -601,7 +601,7 @@ static void run_test(enum vm_guest_mode mode, void *arg) struct kvm_vcpu *vcpu; struct kvm_vm *vm; unsigned long *bmap[2]; - uint32_t ring_buf_idx = 0; + u32 ring_buf_idx = 0; int sem_val; if (!log_mode_supported()) { @@ -667,7 +667,7 @@ static void run_test(enum vm_guest_mode mode, void *arg) virt_map(vm, guest_test_virt_mem, guest_test_phys_mem, guest_num_pages); /* Cache the HVA pointer of the region */ - host_test_mem = addr_gpa2hva(vm, (vm_paddr_t)guest_test_phys_mem); + host_test_mem = addr_gpa2hva(vm, (gpa_t)guest_test_phys_mem); /* Export the shared variables to the guest */ sync_global_to_guest(vm, host_page_size); diff --git a/tools/testing/selftests/kvm/get-reg-list.c b/tools/testing/selftests/kvm/get-reg-list.c index f4644c9d2d3b..216f10644c1a 100644 --- a/tools/testing/selftests/kvm/get-reg-list.c +++ b/tools/testing/selftests/kvm/get-reg-list.c @@ -216,7 +216,7 @@ static void run_test(struct vcpu_reg_list *c) * since we don't know the capabilities of any new registers. */ for_each_present_blessed_reg(i) { - uint8_t addr[2048 / 8]; + u8 addr[2048 / 8]; struct kvm_one_reg reg = { .id = reg_list->reg[i], .addr = (__u64)&addr, diff --git a/tools/testing/selftests/kvm/guest_memfd_test.c b/tools/testing/selftests/kvm/guest_memfd_test.c index ec7644aae999..d6528c6f5e03 100644 --- a/tools/testing/selftests/kvm/guest_memfd_test.c +++ b/tools/testing/selftests/kvm/guest_memfd_test.c @@ -171,7 +171,7 @@ static void test_numa_allocation(int fd, size_t total_size) kvm_munmap(mem, total_size); } -static void test_collapse(int fd, uint64_t flags) +static void test_collapse(int fd, u64 flags) { const size_t pmd_size = get_trans_hugepagesz(); void *reserved_addr; @@ -346,7 +346,7 @@ static void test_invalid_punch_hole(int fd, size_t total_size) } static void test_create_guest_memfd_invalid_sizes(struct kvm_vm *vm, - uint64_t guest_memfd_flags) + u64 guest_memfd_flags) { size_t size; int fd; @@ -389,8 +389,8 @@ static void test_create_guest_memfd_multiple(struct kvm_vm *vm) static void test_guest_memfd_flags(struct kvm_vm *vm) { - uint64_t valid_flags = vm_check_cap(vm, KVM_CAP_GUEST_MEMFD_FLAGS); - uint64_t flag; + u64 valid_flags = vm_check_cap(vm, KVM_CAP_GUEST_MEMFD_FLAGS); + u64 flag; int fd; for (flag = BIT(0); flag; flag <<= 1) { @@ -419,7 +419,7 @@ do { \ #define gmem_test(__test, __vm, __flags) \ __gmem_test(__test, __vm, __flags, page_size * 4) -static void __test_guest_memfd(struct kvm_vm *vm, uint64_t flags) +static void __test_guest_memfd(struct kvm_vm *vm, u64 flags) { test_create_guest_memfd_multiple(vm); test_create_guest_memfd_invalid_sizes(vm, flags); @@ -452,7 +452,7 @@ static void __test_guest_memfd(struct kvm_vm *vm, uint64_t flags) static void test_guest_memfd(unsigned long vm_type) { struct kvm_vm *vm = vm_create_barebones_type(vm_type); - uint64_t flags; + u64 flags; test_guest_memfd_flags(vm); @@ -470,7 +470,7 @@ static void test_guest_memfd(unsigned long vm_type) kvm_vm_free(vm); } -static void guest_code(uint8_t *mem, uint64_t size) +static void guest_code(u8 *mem, u64 size) { size_t i; @@ -489,12 +489,12 @@ static void test_guest_memfd_guest(void) * the guest's code, stack, and page tables, and low memory contains * the PCI hole and other MMIO regions that need to be avoided. */ - const uint64_t gpa = SZ_4G; + const gpa_t gpa = SZ_4G; const int slot = 1; struct kvm_vcpu *vcpu; struct kvm_vm *vm; - uint8_t *mem; + u8 *mem; size_t size; int fd, i; diff --git a/tools/testing/selftests/kvm/guest_print_test.c b/tools/testing/selftests/kvm/guest_print_test.c index bcf582852db9..79d3fc326e91 100644 --- a/tools/testing/selftests/kvm/guest_print_test.c +++ b/tools/testing/selftests/kvm/guest_print_test.c @@ -16,22 +16,22 @@ #include "ucall_common.h" struct guest_vals { - uint64_t a; - uint64_t b; - uint64_t type; + u64 a; + u64 b; + u64 type; }; static struct guest_vals vals; /* GUEST_PRINTF()/GUEST_ASSERT_FMT() does not support float or double. */ #define TYPE_LIST \ -TYPE(test_type_i64, I64, "%ld", int64_t) \ -TYPE(test_type_u64, U64u, "%lu", uint64_t) \ -TYPE(test_type_x64, U64x, "0x%lx", uint64_t) \ -TYPE(test_type_X64, U64X, "0x%lX", uint64_t) \ -TYPE(test_type_u32, U32u, "%u", uint32_t) \ -TYPE(test_type_x32, U32x, "0x%x", uint32_t) \ -TYPE(test_type_X32, U32X, "0x%X", uint32_t) \ +TYPE(test_type_i64, I64, "%ld", s64) \ +TYPE(test_type_u64, U64u, "%lu", u64) \ +TYPE(test_type_x64, U64x, "0x%lx", u64) \ +TYPE(test_type_X64, U64X, "0x%lX", u64) \ +TYPE(test_type_u32, U32u, "%u", u32) \ +TYPE(test_type_x32, U32x, "0x%x", u32) \ +TYPE(test_type_X32, U32X, "0x%X", u32) \ TYPE(test_type_int, INT, "%d", int) \ TYPE(test_type_char, CHAR, "%c", char) \ TYPE(test_type_str, STR, "'%s'", const char *) \ @@ -56,7 +56,7 @@ static void fn(struct kvm_vcpu *vcpu, T a, T b) \ \ snprintf(expected_printf, UCALL_BUFFER_LEN, PRINTF_FMT_##ext, a, b); \ snprintf(expected_assert, UCALL_BUFFER_LEN, ASSERT_FMT_##ext, a, b); \ - vals = (struct guest_vals){ (uint64_t)a, (uint64_t)b, TYPE_##ext }; \ + vals = (struct guest_vals){ (u64)a, (u64)b, TYPE_##ext }; \ sync_global_to_guest(vcpu->vm, vals); \ run_test(vcpu, expected_printf, expected_assert); \ } diff --git a/tools/testing/selftests/kvm/hardware_disable_test.c b/tools/testing/selftests/kvm/hardware_disable_test.c index 94bd6ed24cf3..3147f5c97e94 100644 --- a/tools/testing/selftests/kvm/hardware_disable_test.c +++ b/tools/testing/selftests/kvm/hardware_disable_test.c @@ -80,7 +80,7 @@ static inline void check_join(pthread_t thread, void **retval) TEST_ASSERT(r == 0, "%s: failed to join thread", __func__); } -static void run_test(uint32_t run) +static void run_test(u32 run) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; @@ -88,7 +88,7 @@ static void run_test(uint32_t run) pthread_t threads[VCPU_NUM]; pthread_t throw_away; void *b; - uint32_t i, j; + u32 i, j; CPU_ZERO(&cpu_set); for (i = 0; i < VCPU_NUM; i++) @@ -149,7 +149,7 @@ void wait_for_child_setup(pid_t pid) int main(int argc, char **argv) { - uint32_t i; + u32 i; int s, r; pid_t pid; diff --git a/tools/testing/selftests/kvm/include/arm64/arch_timer.h b/tools/testing/selftests/kvm/include/arm64/arch_timer.h index e2c4e9f0010f..a5836d4ab7ee 100644 --- a/tools/testing/selftests/kvm/include/arm64/arch_timer.h +++ b/tools/testing/selftests/kvm/include/arm64/arch_timer.h @@ -18,20 +18,20 @@ enum arch_timer { #define CTL_ISTATUS (1 << 2) #define msec_to_cycles(msec) \ - (timer_get_cntfrq() * (uint64_t)(msec) / 1000) + (timer_get_cntfrq() * (u64)(msec) / 1000) #define usec_to_cycles(usec) \ - (timer_get_cntfrq() * (uint64_t)(usec) / 1000000) + (timer_get_cntfrq() * (u64)(usec) / 1000000) #define cycles_to_usec(cycles) \ - ((uint64_t)(cycles) * 1000000 / timer_get_cntfrq()) + ((u64)(cycles) * 1000000 / timer_get_cntfrq()) -static inline uint32_t timer_get_cntfrq(void) +static inline u32 timer_get_cntfrq(void) { return read_sysreg(cntfrq_el0); } -static inline uint64_t timer_get_cntct(enum arch_timer timer) +static inline u64 timer_get_cntct(enum arch_timer timer) { isb(); @@ -48,7 +48,7 @@ static inline uint64_t timer_get_cntct(enum arch_timer timer) return 0; } -static inline void timer_set_cval(enum arch_timer timer, uint64_t cval) +static inline void timer_set_cval(enum arch_timer timer, u64 cval) { switch (timer) { case VIRTUAL: @@ -64,7 +64,7 @@ static inline void timer_set_cval(enum arch_timer timer, uint64_t cval) isb(); } -static inline uint64_t timer_get_cval(enum arch_timer timer) +static inline u64 timer_get_cval(enum arch_timer timer) { switch (timer) { case VIRTUAL: @@ -79,7 +79,7 @@ static inline uint64_t timer_get_cval(enum arch_timer timer) return 0; } -static inline void timer_set_tval(enum arch_timer timer, int32_t tval) +static inline void timer_set_tval(enum arch_timer timer, s32 tval) { switch (timer) { case VIRTUAL: @@ -95,7 +95,7 @@ static inline void timer_set_tval(enum arch_timer timer, int32_t tval) isb(); } -static inline int32_t timer_get_tval(enum arch_timer timer) +static inline s32 timer_get_tval(enum arch_timer timer) { isb(); switch (timer) { @@ -111,7 +111,7 @@ static inline int32_t timer_get_tval(enum arch_timer timer) return 0; } -static inline void timer_set_ctl(enum arch_timer timer, uint32_t ctl) +static inline void timer_set_ctl(enum arch_timer timer, u32 ctl) { switch (timer) { case VIRTUAL: @@ -127,7 +127,7 @@ static inline void timer_set_ctl(enum arch_timer timer, uint32_t ctl) isb(); } -static inline uint32_t timer_get_ctl(enum arch_timer timer) +static inline u32 timer_get_ctl(enum arch_timer timer) { switch (timer) { case VIRTUAL: @@ -142,15 +142,15 @@ static inline uint32_t timer_get_ctl(enum arch_timer timer) return 0; } -static inline void timer_set_next_cval_ms(enum arch_timer timer, uint32_t msec) +static inline void timer_set_next_cval_ms(enum arch_timer timer, u32 msec) { - uint64_t now_ct = timer_get_cntct(timer); - uint64_t next_ct = now_ct + msec_to_cycles(msec); + u64 now_ct = timer_get_cntct(timer); + u64 next_ct = now_ct + msec_to_cycles(msec); timer_set_cval(timer, next_ct); } -static inline void timer_set_next_tval_ms(enum arch_timer timer, uint32_t msec) +static inline void timer_set_next_tval_ms(enum arch_timer timer, u32 msec) { timer_set_tval(timer, msec_to_cycles(msec)); } diff --git a/tools/testing/selftests/kvm/include/arm64/delay.h b/tools/testing/selftests/kvm/include/arm64/delay.h index 329e4f5079ea..6a5d4634af2c 100644 --- a/tools/testing/selftests/kvm/include/arm64/delay.h +++ b/tools/testing/selftests/kvm/include/arm64/delay.h @@ -8,10 +8,10 @@ #include "arch_timer.h" -static inline void __delay(uint64_t cycles) +static inline void __delay(u64 cycles) { enum arch_timer timer = VIRTUAL; - uint64_t start = timer_get_cntct(timer); + u64 start = timer_get_cntct(timer); while ((timer_get_cntct(timer) - start) < cycles) cpu_relax(); diff --git a/tools/testing/selftests/kvm/include/arm64/gic.h b/tools/testing/selftests/kvm/include/arm64/gic.h index cc7a7f34ed37..615745093c98 100644 --- a/tools/testing/selftests/kvm/include/arm64/gic.h +++ b/tools/testing/selftests/kvm/include/arm64/gic.h @@ -48,8 +48,8 @@ void gic_set_dir(unsigned int intid); * split is true, EOI drops the priority and deactivates the interrupt. */ void gic_set_eoi_split(bool split); -void gic_set_priority_mask(uint64_t mask); -void gic_set_priority(uint32_t intid, uint32_t prio); +void gic_set_priority_mask(u64 mask); +void gic_set_priority(u32 intid, u32 prio); void gic_irq_set_active(unsigned int intid); void gic_irq_clear_active(unsigned int intid); bool gic_irq_get_active(unsigned int intid); @@ -59,7 +59,7 @@ bool gic_irq_get_pending(unsigned int intid); void gic_irq_set_config(unsigned int intid, bool is_edge); void gic_irq_set_group(unsigned int intid, bool group); -void gic_rdist_enable_lpis(vm_paddr_t cfg_table, size_t cfg_table_size, - vm_paddr_t pend_table); +void gic_rdist_enable_lpis(gpa_t cfg_table, size_t cfg_table_size, + gpa_t pend_table); #endif /* SELFTEST_KVM_GIC_H */ diff --git a/tools/testing/selftests/kvm/include/arm64/gic_v3_its.h b/tools/testing/selftests/kvm/include/arm64/gic_v3_its.h index 58feef3eb386..a43a407e2d5c 100644 --- a/tools/testing/selftests/kvm/include/arm64/gic_v3_its.h +++ b/tools/testing/selftests/kvm/include/arm64/gic_v3_its.h @@ -5,11 +5,10 @@ #include -void its_init(vm_paddr_t coll_tbl, size_t coll_tbl_sz, - vm_paddr_t device_tbl, size_t device_tbl_sz, - vm_paddr_t cmdq, size_t cmdq_size); +void its_init(gpa_t coll_tbl, size_t coll_tbl_sz, gpa_t device_tbl, + size_t device_tbl_sz, gpa_t cmdq, size_t cmdq_size); -void its_send_mapd_cmd(void *cmdq_base, u32 device_id, vm_paddr_t itt_base, +void its_send_mapd_cmd(void *cmdq_base, u32 device_id, gpa_t itt_base, size_t itt_size, bool valid); void its_send_mapc_cmd(void *cmdq_base, u32 vcpu_id, u32 collection_id, bool valid); void its_send_mapti_cmd(void *cmdq_base, u32 device_id, u32 event_id, diff --git a/tools/testing/selftests/kvm/include/arm64/processor.h b/tools/testing/selftests/kvm/include/arm64/processor.h index ac97a1c436fc..b8a902ba8573 100644 --- a/tools/testing/selftests/kvm/include/arm64/processor.h +++ b/tools/testing/selftests/kvm/include/arm64/processor.h @@ -128,7 +128,7 @@ #define PTE_ADDR_51_50_LPA2_SHIFT 8 void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init); -struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, +struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, u32 vcpu_id, struct kvm_vcpu_init *init, void *guest_code); struct ex_regs { @@ -167,8 +167,8 @@ enum { (v) == VECTOR_SYNC_LOWER_64 || \ (v) == VECTOR_SYNC_LOWER_32) -void aarch64_get_supported_page_sizes(uint32_t ipa, uint32_t *ipa4k, - uint32_t *ipa16k, uint32_t *ipa64k); +void aarch64_get_supported_page_sizes(u32 ipa, u32 *ipa4k, + u32 *ipa16k, u32 *ipa64k); void vm_init_descriptor_tables(struct kvm_vm *vm); void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu); @@ -179,8 +179,8 @@ void vm_install_exception_handler(struct kvm_vm *vm, void vm_install_sync_handler(struct kvm_vm *vm, int vector, int ec, handler_fn handler); -uint64_t *virt_get_pte_hva_at_level(struct kvm_vm *vm, vm_vaddr_t gva, int level); -uint64_t *virt_get_pte_hva(struct kvm_vm *vm, vm_vaddr_t gva); +u64 *virt_get_pte_hva_at_level(struct kvm_vm *vm, gva_t gva, int level); +u64 *virt_get_pte_hva(struct kvm_vm *vm, gva_t gva); static inline void cpu_relax(void) { @@ -287,9 +287,9 @@ struct arm_smccc_res { * @res: pointer to write the return values from registers x0-x3 * */ -void smccc_hvc(uint32_t function_id, uint64_t arg0, uint64_t arg1, - uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, - uint64_t arg6, struct arm_smccc_res *res); +void smccc_hvc(u32 function_id, u64 arg0, u64 arg1, + u64 arg2, u64 arg3, u64 arg4, u64 arg5, + u64 arg6, struct arm_smccc_res *res); /** * smccc_smc - Invoke a SMCCC function using the smc conduit @@ -298,9 +298,9 @@ void smccc_hvc(uint32_t function_id, uint64_t arg0, uint64_t arg1, * @res: pointer to write the return values from registers x0-x3 * */ -void smccc_smc(uint32_t function_id, uint64_t arg0, uint64_t arg1, - uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, - uint64_t arg6, struct arm_smccc_res *res); +void smccc_smc(u32 function_id, u64 arg0, u64 arg1, + u64 arg2, u64 arg3, u64 arg4, u64 arg5, + u64 arg6, struct arm_smccc_res *res); /* Execute a Wait For Interrupt instruction. */ void wfi(void); diff --git a/tools/testing/selftests/kvm/include/arm64/ucall.h b/tools/testing/selftests/kvm/include/arm64/ucall.h index 4ec801f37f00..2210d3d94c40 100644 --- a/tools/testing/selftests/kvm/include/arm64/ucall.h +++ b/tools/testing/selftests/kvm/include/arm64/ucall.h @@ -10,9 +10,9 @@ * ucall_exit_mmio_addr holds per-VM values (global data is duplicated by each * VM), it must not be accessed from host code. */ -extern vm_vaddr_t *ucall_exit_mmio_addr; +extern gva_t *ucall_exit_mmio_addr; -static inline void ucall_arch_do_ucall(vm_vaddr_t uc) +static inline void ucall_arch_do_ucall(gva_t uc) { WRITE_ONCE(*ucall_exit_mmio_addr, uc); } diff --git a/tools/testing/selftests/kvm/include/arm64/vgic.h b/tools/testing/selftests/kvm/include/arm64/vgic.h index 688beccc9436..1f8b04373987 100644 --- a/tools/testing/selftests/kvm/include/arm64/vgic.h +++ b/tools/testing/selftests/kvm/include/arm64/vgic.h @@ -11,27 +11,27 @@ #include "kvm_util.h" #define REDIST_REGION_ATTR_ADDR(count, base, flags, index) \ - (((uint64_t)(count) << 52) | \ - ((uint64_t)((base) >> 16) << 16) | \ - ((uint64_t)(flags) << 12) | \ + (((u64)(count) << 52) | \ + ((u64)((base) >> 16) << 16) | \ + ((u64)(flags) << 12) | \ index) bool kvm_supports_vgic_v3(void); -int __vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, uint32_t nr_irqs); +int __vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, u32 nr_irqs); void __vgic_v3_init(int fd); -int vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, uint32_t nr_irqs); +int vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, u32 nr_irqs); #define VGIC_MAX_RESERVED 1023 -void kvm_irq_set_level_info(int gic_fd, uint32_t intid, int level); -int _kvm_irq_set_level_info(int gic_fd, uint32_t intid, int level); +void kvm_irq_set_level_info(int gic_fd, u32 intid, int level); +int _kvm_irq_set_level_info(int gic_fd, u32 intid, int level); -void kvm_arm_irq_line(struct kvm_vm *vm, uint32_t intid, int level); -int _kvm_arm_irq_line(struct kvm_vm *vm, uint32_t intid, int level); +void kvm_arm_irq_line(struct kvm_vm *vm, u32 intid, int level); +int _kvm_arm_irq_line(struct kvm_vm *vm, u32 intid, int level); /* The vcpu arg only applies to private interrupts. */ -void kvm_irq_write_ispendr(int gic_fd, uint32_t intid, struct kvm_vcpu *vcpu); -void kvm_irq_write_isactiver(int gic_fd, uint32_t intid, struct kvm_vcpu *vcpu); +void kvm_irq_write_ispendr(int gic_fd, u32 intid, struct kvm_vcpu *vcpu); +void kvm_irq_write_isactiver(int gic_fd, u32 intid, struct kvm_vcpu *vcpu); #define KVM_IRQCHIP_NUM_PINS (1020 - 32) diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing/selftests/kvm/include/kvm_util.h index f861242b4ae8..2ecaaa0e9965 100644 --- a/tools/testing/selftests/kvm/include/kvm_util.h +++ b/tools/testing/selftests/kvm/include/kvm_util.h @@ -58,7 +58,7 @@ struct kvm_binary_stats { struct kvm_vcpu { struct list_head list; - uint32_t id; + u32 id; int fd; struct kvm_vm *vm; struct kvm_run *run; @@ -70,8 +70,8 @@ struct kvm_vcpu { #endif struct kvm_binary_stats stats; struct kvm_dirty_gfn *dirty_gfns; - uint32_t fetch_index; - uint32_t dirty_gfns_count; + u32 fetch_index; + u32 dirty_gfns_count; }; struct userspace_mem_regions { @@ -90,7 +90,7 @@ enum kvm_mem_region_type { struct kvm_mmu { bool pgd_created; - uint64_t pgd; + u64 pgd; int pgtable_levels; struct kvm_mmu_arch arch; @@ -105,16 +105,16 @@ struct kvm_vm { unsigned int page_shift; unsigned int pa_bits; unsigned int va_bits; - uint64_t max_gfn; + u64 max_gfn; struct list_head vcpus; struct userspace_mem_regions regions; struct sparsebit *vpages_valid; struct sparsebit *vpages_mapped; bool has_irqchip; - vm_paddr_t ucall_mmio_addr; - vm_vaddr_t handlers; - uint32_t dirty_ring_size; - uint64_t gpa_tag_mask; + gpa_t ucall_mmio_addr; + gva_t handlers; + u32 dirty_ring_size; + gpa_t gpa_tag_mask; /* * "mmu" is the guest's stage-1, with a short name because the vast @@ -132,7 +132,7 @@ struct kvm_vm { * allocators, e.g., lib/elf uses the memslots[MEM_REGION_CODE] * memslot. */ - uint32_t memslots[NR_MEM_REGIONS]; + u32 memslots[NR_MEM_REGIONS]; }; struct vcpu_reg_sublist { @@ -164,7 +164,7 @@ struct vcpu_reg_list { else struct userspace_mem_region * -memslot2region(struct kvm_vm *vm, uint32_t memslot); +memslot2region(struct kvm_vm *vm, u32 memslot); static inline struct userspace_mem_region *vm_get_mem_region(struct kvm_vm *vm, enum kvm_mem_region_type type) @@ -213,13 +213,13 @@ enum vm_guest_mode { }; struct vm_shape { - uint32_t type; - uint8_t mode; - uint8_t pad0; - uint16_t pad1; + u32 type; + u8 mode; + u8 pad0; + u16 pad1; }; -kvm_static_assert(sizeof(struct vm_shape) == sizeof(uint64_t)); +kvm_static_assert(sizeof(struct vm_shape) == sizeof(u64)); #define VM_TYPE_DEFAULT 0 @@ -404,21 +404,22 @@ static inline int vm_check_cap(struct kvm_vm *vm, long cap) return ret; } -static inline int __vm_enable_cap(struct kvm_vm *vm, uint32_t cap, uint64_t arg0) +static inline int __vm_enable_cap(struct kvm_vm *vm, u32 cap, u64 arg0) { struct kvm_enable_cap enable_cap = { .cap = cap, .args = { arg0 } }; return __vm_ioctl(vm, KVM_ENABLE_CAP, &enable_cap); } -static inline void vm_enable_cap(struct kvm_vm *vm, uint32_t cap, uint64_t arg0) + +static inline void vm_enable_cap(struct kvm_vm *vm, u32 cap, u64 arg0) { struct kvm_enable_cap enable_cap = { .cap = cap, .args = { arg0 } }; vm_ioctl(vm, KVM_ENABLE_CAP, &enable_cap); } -static inline void vm_set_memory_attributes(struct kvm_vm *vm, uint64_t gpa, - uint64_t size, uint64_t attributes) +static inline void vm_set_memory_attributes(struct kvm_vm *vm, gpa_t gpa, + u64 size, u64 attributes) { struct kvm_memory_attributes attr = { .attributes = attributes, @@ -438,35 +439,35 @@ static inline void vm_set_memory_attributes(struct kvm_vm *vm, uint64_t gpa, } -static inline void vm_mem_set_private(struct kvm_vm *vm, uint64_t gpa, - uint64_t size) +static inline void vm_mem_set_private(struct kvm_vm *vm, gpa_t gpa, + u64 size) { vm_set_memory_attributes(vm, gpa, size, KVM_MEMORY_ATTRIBUTE_PRIVATE); } -static inline void vm_mem_set_shared(struct kvm_vm *vm, uint64_t gpa, - uint64_t size) +static inline void vm_mem_set_shared(struct kvm_vm *vm, gpa_t gpa, + u64 size) { vm_set_memory_attributes(vm, gpa, size, 0); } -void vm_guest_mem_fallocate(struct kvm_vm *vm, uint64_t gpa, uint64_t size, +void vm_guest_mem_fallocate(struct kvm_vm *vm, gpa_t gpa, u64 size, bool punch_hole); -static inline void vm_guest_mem_punch_hole(struct kvm_vm *vm, uint64_t gpa, - uint64_t size) +static inline void vm_guest_mem_punch_hole(struct kvm_vm *vm, gpa_t gpa, + u64 size) { vm_guest_mem_fallocate(vm, gpa, size, true); } -static inline void vm_guest_mem_allocate(struct kvm_vm *vm, uint64_t gpa, - uint64_t size) +static inline void vm_guest_mem_allocate(struct kvm_vm *vm, gpa_t gpa, + u64 size) { vm_guest_mem_fallocate(vm, gpa, size, false); } -void vm_enable_dirty_ring(struct kvm_vm *vm, uint32_t ring_size); -const char *vm_guest_mode_string(uint32_t i); +void vm_enable_dirty_ring(struct kvm_vm *vm, u32 ring_size); +const char *vm_guest_mode_string(u32 i); void kvm_vm_free(struct kvm_vm *vmp); void kvm_vm_restart(struct kvm_vm *vmp); @@ -474,7 +475,7 @@ void kvm_vm_release(struct kvm_vm *vmp); void kvm_vm_elf_load(struct kvm_vm *vm, const char *filename); int kvm_memfd_alloc(size_t size, bool hugepages); -void vm_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent); +void vm_dump(FILE *stream, struct kvm_vm *vm, u8 indent); static inline void kvm_vm_get_dirty_log(struct kvm_vm *vm, int slot, void *log) { @@ -484,7 +485,7 @@ static inline void kvm_vm_get_dirty_log(struct kvm_vm *vm, int slot, void *log) } static inline void kvm_vm_clear_dirty_log(struct kvm_vm *vm, int slot, void *log, - uint64_t first_page, uint32_t num_pages) + u64 first_page, u32 num_pages) { struct kvm_clear_dirty_log args = { .dirty_bitmap = log, @@ -496,14 +497,14 @@ static inline void kvm_vm_clear_dirty_log(struct kvm_vm *vm, int slot, void *log vm_ioctl(vm, KVM_CLEAR_DIRTY_LOG, &args); } -static inline uint32_t kvm_vm_reset_dirty_ring(struct kvm_vm *vm) +static inline u32 kvm_vm_reset_dirty_ring(struct kvm_vm *vm) { return __vm_ioctl(vm, KVM_RESET_DIRTY_RINGS, NULL); } static inline void kvm_vm_register_coalesced_io(struct kvm_vm *vm, - uint64_t address, - uint64_t size, bool pio) + u64 address, + u64 size, bool pio) { struct kvm_coalesced_mmio_zone zone = { .addr = address, @@ -515,8 +516,8 @@ static inline void kvm_vm_register_coalesced_io(struct kvm_vm *vm, } static inline void kvm_vm_unregister_coalesced_io(struct kvm_vm *vm, - uint64_t address, - uint64_t size, bool pio) + u64 address, + u64 size, bool pio) { struct kvm_coalesced_mmio_zone zone = { .addr = address, @@ -535,8 +536,8 @@ static inline int vm_get_stats_fd(struct kvm_vm *vm) return fd; } -static inline int __kvm_irqfd(struct kvm_vm *vm, uint32_t gsi, int eventfd, - uint32_t flags) +static inline int __kvm_irqfd(struct kvm_vm *vm, u32 gsi, int eventfd, + u32 flags) { struct kvm_irqfd irqfd = { .fd = eventfd, @@ -548,20 +549,19 @@ static inline int __kvm_irqfd(struct kvm_vm *vm, uint32_t gsi, int eventfd, return __vm_ioctl(vm, KVM_IRQFD, &irqfd); } -static inline void kvm_irqfd(struct kvm_vm *vm, uint32_t gsi, int eventfd, - uint32_t flags) +static inline void kvm_irqfd(struct kvm_vm *vm, u32 gsi, int eventfd, u32 flags) { int ret = __kvm_irqfd(vm, gsi, eventfd, flags); TEST_ASSERT_VM_VCPU_IOCTL(!ret, KVM_IRQFD, ret, vm); } -static inline void kvm_assign_irqfd(struct kvm_vm *vm, uint32_t gsi, int eventfd) +static inline void kvm_assign_irqfd(struct kvm_vm *vm, u32 gsi, int eventfd) { kvm_irqfd(vm, gsi, eventfd, 0); } -static inline void kvm_deassign_irqfd(struct kvm_vm *vm, uint32_t gsi, int eventfd) +static inline void kvm_deassign_irqfd(struct kvm_vm *vm, u32 gsi, int eventfd) { kvm_irqfd(vm, gsi, eventfd, KVM_IRQFD_FLAG_DEASSIGN); } @@ -610,15 +610,15 @@ static inline struct kvm_stats_desc *get_stats_descriptor(struct kvm_stats_desc } void read_stat_data(int stats_fd, struct kvm_stats_header *header, - struct kvm_stats_desc *desc, uint64_t *data, + struct kvm_stats_desc *desc, u64 *data, size_t max_elements); void kvm_get_stat(struct kvm_binary_stats *stats, const char *name, - uint64_t *data, size_t max_elements); + u64 *data, size_t max_elements); #define __get_stat(stats, stat) \ ({ \ - uint64_t data; \ + u64 data; \ \ kvm_get_stat(stats, #stat, &data, 1); \ data; \ @@ -664,8 +664,8 @@ static inline bool is_smt_on(void) void vm_create_irqchip(struct kvm_vm *vm); -static inline int __vm_create_guest_memfd(struct kvm_vm *vm, uint64_t size, - uint64_t flags) +static inline int __vm_create_guest_memfd(struct kvm_vm *vm, u64 size, + u64 flags) { struct kvm_create_guest_memfd guest_memfd = { .size = size, @@ -675,8 +675,8 @@ static inline int __vm_create_guest_memfd(struct kvm_vm *vm, uint64_t size, return __vm_ioctl(vm, KVM_CREATE_GUEST_MEMFD, &guest_memfd); } -static inline int vm_create_guest_memfd(struct kvm_vm *vm, uint64_t size, - uint64_t flags) +static inline int vm_create_guest_memfd(struct kvm_vm *vm, u64 size, + u64 flags) { int fd = __vm_create_guest_memfd(vm, size, flags); @@ -684,24 +684,23 @@ static inline int vm_create_guest_memfd(struct kvm_vm *vm, uint64_t size, return fd; } -void vm_set_user_memory_region(struct kvm_vm *vm, uint32_t slot, uint32_t flags, - uint64_t gpa, uint64_t size, void *hva); -int __vm_set_user_memory_region(struct kvm_vm *vm, uint32_t slot, uint32_t flags, - uint64_t gpa, uint64_t size, void *hva); -void vm_set_user_memory_region2(struct kvm_vm *vm, uint32_t slot, uint32_t flags, - uint64_t gpa, uint64_t size, void *hva, - uint32_t guest_memfd, uint64_t guest_memfd_offset); -int __vm_set_user_memory_region2(struct kvm_vm *vm, uint32_t slot, uint32_t flags, - uint64_t gpa, uint64_t size, void *hva, - uint32_t guest_memfd, uint64_t guest_memfd_offset); +void vm_set_user_memory_region(struct kvm_vm *vm, u32 slot, u32 flags, + gpa_t gpa, u64 size, void *hva); +int __vm_set_user_memory_region(struct kvm_vm *vm, u32 slot, u32 flags, + gpa_t gpa, u64 size, void *hva); +void vm_set_user_memory_region2(struct kvm_vm *vm, u32 slot, u32 flags, + gpa_t gpa, u64 size, void *hva, + u32 guest_memfd, u64 guest_memfd_offset); +int __vm_set_user_memory_region2(struct kvm_vm *vm, u32 slot, u32 flags, + gpa_t gpa, u64 size, void *hva, + u32 guest_memfd, u64 guest_memfd_offset); void vm_userspace_mem_region_add(struct kvm_vm *vm, enum vm_mem_backing_src_type src_type, - uint64_t gpa, uint32_t slot, uint64_t npages, - uint32_t flags); + gpa_t gpa, u32 slot, u64 npages, u32 flags); void vm_mem_add(struct kvm_vm *vm, enum vm_mem_backing_src_type src_type, - uint64_t gpa, uint32_t slot, uint64_t npages, uint32_t flags, - int guest_memfd_fd, uint64_t guest_memfd_offset); + gpa_t gpa, u32 slot, u64 npages, u32 flags, + int guest_memfd_fd, u64 guest_memfd_offset); #ifndef vm_arch_has_protected_memory static inline bool vm_arch_has_protected_memory(struct kvm_vm *vm) @@ -710,36 +709,34 @@ static inline bool vm_arch_has_protected_memory(struct kvm_vm *vm) } #endif -void vm_mem_region_set_flags(struct kvm_vm *vm, uint32_t slot, uint32_t flags); -void vm_mem_region_reload(struct kvm_vm *vm, uint32_t slot); -void vm_mem_region_move(struct kvm_vm *vm, uint32_t slot, uint64_t new_gpa); -void vm_mem_region_delete(struct kvm_vm *vm, uint32_t slot); -struct kvm_vcpu *__vm_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id); -void vm_populate_vaddr_bitmap(struct kvm_vm *vm); -vm_vaddr_t vm_vaddr_unused_gap(struct kvm_vm *vm, size_t sz, vm_vaddr_t vaddr_min); -vm_vaddr_t vm_vaddr_alloc(struct kvm_vm *vm, size_t sz, vm_vaddr_t vaddr_min); -vm_vaddr_t __vm_vaddr_alloc(struct kvm_vm *vm, size_t sz, vm_vaddr_t vaddr_min, - enum kvm_mem_region_type type); -vm_vaddr_t vm_vaddr_alloc_shared(struct kvm_vm *vm, size_t sz, - vm_vaddr_t vaddr_min, - enum kvm_mem_region_type type); -vm_vaddr_t vm_vaddr_alloc_pages(struct kvm_vm *vm, int nr_pages); -vm_vaddr_t __vm_vaddr_alloc_page(struct kvm_vm *vm, - enum kvm_mem_region_type type); -vm_vaddr_t vm_vaddr_alloc_page(struct kvm_vm *vm); +void vm_mem_region_set_flags(struct kvm_vm *vm, u32 slot, u32 flags); +void vm_mem_region_reload(struct kvm_vm *vm, u32 slot); +void vm_mem_region_move(struct kvm_vm *vm, u32 slot, u64 new_gpa); +void vm_mem_region_delete(struct kvm_vm *vm, u32 slot); +struct kvm_vcpu *__vm_vcpu_add(struct kvm_vm *vm, u32 vcpu_id); +void vm_populate_gva_bitmap(struct kvm_vm *vm); +gva_t vm_unused_gva_gap(struct kvm_vm *vm, size_t sz, gva_t min_gva); +gva_t vm_alloc(struct kvm_vm *vm, size_t sz, gva_t min_gva); +gva_t __vm_alloc(struct kvm_vm *vm, size_t sz, gva_t min_gva, + enum kvm_mem_region_type type); +gva_t vm_alloc_shared(struct kvm_vm *vm, size_t sz, gva_t min_gva, + enum kvm_mem_region_type type); +gva_t vm_alloc_pages(struct kvm_vm *vm, int nr_pages); +gva_t __vm_alloc_page(struct kvm_vm *vm, enum kvm_mem_region_type type); +gva_t vm_alloc_page(struct kvm_vm *vm); -void virt_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, +void virt_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa, unsigned int npages); -void *addr_gpa2hva(struct kvm_vm *vm, vm_paddr_t gpa); -void *addr_gva2hva(struct kvm_vm *vm, vm_vaddr_t gva); -vm_paddr_t addr_hva2gpa(struct kvm_vm *vm, void *hva); -void *addr_gpa2alias(struct kvm_vm *vm, vm_paddr_t gpa); +void *addr_gpa2hva(struct kvm_vm *vm, gpa_t gpa); +void *addr_gva2hva(struct kvm_vm *vm, gva_t gva); +gpa_t addr_hva2gpa(struct kvm_vm *vm, void *hva); +void *addr_gpa2alias(struct kvm_vm *vm, gpa_t gpa); #ifndef vcpu_arch_put_guest #define vcpu_arch_put_guest(mem, val) do { (mem) = (val); } while (0) #endif -static inline vm_paddr_t vm_untag_gpa(struct kvm_vm *vm, vm_paddr_t gpa) +static inline gpa_t vm_untag_gpa(struct kvm_vm *vm, gpa_t gpa) { return gpa & ~vm->gpa_tag_mask; } @@ -755,8 +752,8 @@ static inline int __vcpu_run(struct kvm_vcpu *vcpu) void vcpu_run_complete_io(struct kvm_vcpu *vcpu); struct kvm_reg_list *vcpu_get_reg_list(struct kvm_vcpu *vcpu); -static inline void vcpu_enable_cap(struct kvm_vcpu *vcpu, uint32_t cap, - uint64_t arg0) +static inline void vcpu_enable_cap(struct kvm_vcpu *vcpu, u32 cap, + u64 arg0) { struct kvm_enable_cap enable_cap = { .cap = cap, .args = { arg0 } }; @@ -811,31 +808,34 @@ static inline void vcpu_fpu_set(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) vcpu_ioctl(vcpu, KVM_SET_FPU, fpu); } -static inline int __vcpu_get_reg(struct kvm_vcpu *vcpu, uint64_t id, void *addr) +static inline int __vcpu_get_reg(struct kvm_vcpu *vcpu, u64 id, void *addr) { - struct kvm_one_reg reg = { .id = id, .addr = (uint64_t)addr }; + struct kvm_one_reg reg = { .id = id, .addr = (u64)addr }; return __vcpu_ioctl(vcpu, KVM_GET_ONE_REG, ®); } -static inline int __vcpu_set_reg(struct kvm_vcpu *vcpu, uint64_t id, uint64_t val) + +static inline int __vcpu_set_reg(struct kvm_vcpu *vcpu, u64 id, u64 val) { - struct kvm_one_reg reg = { .id = id, .addr = (uint64_t)&val }; + struct kvm_one_reg reg = { .id = id, .addr = (u64)&val }; return __vcpu_ioctl(vcpu, KVM_SET_ONE_REG, ®); } -static inline uint64_t vcpu_get_reg(struct kvm_vcpu *vcpu, uint64_t id) + +static inline u64 vcpu_get_reg(struct kvm_vcpu *vcpu, u64 id) { - uint64_t val; - struct kvm_one_reg reg = { .id = id, .addr = (uint64_t)&val }; + u64 val; + struct kvm_one_reg reg = { .id = id, .addr = (u64)&val }; TEST_ASSERT(KVM_REG_SIZE(id) <= sizeof(val), "Reg %lx too big", id); vcpu_ioctl(vcpu, KVM_GET_ONE_REG, ®); return val; } -static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, uint64_t id, uint64_t val) + +static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u64 id, u64 val) { - struct kvm_one_reg reg = { .id = id, .addr = (uint64_t)&val }; + struct kvm_one_reg reg = { .id = id, .addr = (u64)&val }; TEST_ASSERT(KVM_REG_SIZE(id) <= sizeof(val), "Reg %lx too big", id); @@ -880,75 +880,75 @@ static inline int vcpu_get_stats_fd(struct kvm_vcpu *vcpu) return fd; } -int __kvm_has_device_attr(int dev_fd, uint32_t group, uint64_t attr); +int __kvm_has_device_attr(int dev_fd, u32 group, u64 attr); -static inline void kvm_has_device_attr(int dev_fd, uint32_t group, uint64_t attr) +static inline void kvm_has_device_attr(int dev_fd, u32 group, u64 attr) { int ret = __kvm_has_device_attr(dev_fd, group, attr); TEST_ASSERT(!ret, "KVM_HAS_DEVICE_ATTR failed, rc: %i errno: %i", ret, errno); } -int __kvm_device_attr_get(int dev_fd, uint32_t group, uint64_t attr, void *val); +int __kvm_device_attr_get(int dev_fd, u32 group, u64 attr, void *val); -static inline void kvm_device_attr_get(int dev_fd, uint32_t group, - uint64_t attr, void *val) +static inline void kvm_device_attr_get(int dev_fd, u32 group, + u64 attr, void *val) { int ret = __kvm_device_attr_get(dev_fd, group, attr, val); TEST_ASSERT(!ret, KVM_IOCTL_ERROR(KVM_GET_DEVICE_ATTR, ret)); } -int __kvm_device_attr_set(int dev_fd, uint32_t group, uint64_t attr, void *val); +int __kvm_device_attr_set(int dev_fd, u32 group, u64 attr, void *val); -static inline void kvm_device_attr_set(int dev_fd, uint32_t group, - uint64_t attr, void *val) +static inline void kvm_device_attr_set(int dev_fd, u32 group, + u64 attr, void *val) { int ret = __kvm_device_attr_set(dev_fd, group, attr, val); TEST_ASSERT(!ret, KVM_IOCTL_ERROR(KVM_SET_DEVICE_ATTR, ret)); } -static inline int __vcpu_has_device_attr(struct kvm_vcpu *vcpu, uint32_t group, - uint64_t attr) +static inline int __vcpu_has_device_attr(struct kvm_vcpu *vcpu, u32 group, + u64 attr) { return __kvm_has_device_attr(vcpu->fd, group, attr); } -static inline void vcpu_has_device_attr(struct kvm_vcpu *vcpu, uint32_t group, - uint64_t attr) +static inline void vcpu_has_device_attr(struct kvm_vcpu *vcpu, u32 group, + u64 attr) { kvm_has_device_attr(vcpu->fd, group, attr); } -static inline int __vcpu_device_attr_get(struct kvm_vcpu *vcpu, uint32_t group, - uint64_t attr, void *val) +static inline int __vcpu_device_attr_get(struct kvm_vcpu *vcpu, u32 group, + u64 attr, void *val) { return __kvm_device_attr_get(vcpu->fd, group, attr, val); } -static inline void vcpu_device_attr_get(struct kvm_vcpu *vcpu, uint32_t group, - uint64_t attr, void *val) +static inline void vcpu_device_attr_get(struct kvm_vcpu *vcpu, u32 group, + u64 attr, void *val) { kvm_device_attr_get(vcpu->fd, group, attr, val); } -static inline int __vcpu_device_attr_set(struct kvm_vcpu *vcpu, uint32_t group, - uint64_t attr, void *val) +static inline int __vcpu_device_attr_set(struct kvm_vcpu *vcpu, u32 group, + u64 attr, void *val) { return __kvm_device_attr_set(vcpu->fd, group, attr, val); } -static inline void vcpu_device_attr_set(struct kvm_vcpu *vcpu, uint32_t group, - uint64_t attr, void *val) +static inline void vcpu_device_attr_set(struct kvm_vcpu *vcpu, u32 group, + u64 attr, void *val) { kvm_device_attr_set(vcpu->fd, group, attr, val); } -int __kvm_test_create_device(struct kvm_vm *vm, uint64_t type); -int __kvm_create_device(struct kvm_vm *vm, uint64_t type); +int __kvm_test_create_device(struct kvm_vm *vm, u64 type); +int __kvm_create_device(struct kvm_vm *vm, u64 type); -static inline int kvm_create_device(struct kvm_vm *vm, uint64_t type) +static inline int kvm_create_device(struct kvm_vm *vm, u64 type) { int fd = __kvm_create_device(vm, type); @@ -964,7 +964,7 @@ void *vcpu_map_dirty_ring(struct kvm_vcpu *vcpu); * Input Args: * vcpu - vCPU * num - number of arguments - * ... - arguments, each of type uint64_t + * ... - arguments, each of type u64 * * Output Args: None * @@ -972,40 +972,38 @@ void *vcpu_map_dirty_ring(struct kvm_vcpu *vcpu); * * Sets the first @num input parameters for the function at @vcpu's entry point, * per the C calling convention of the architecture, to the values given as - * variable args. Each of the variable args is expected to be of type uint64_t. + * variable args. Each of the variable args is expected to be of type u64. * The maximum @num can be is specific to the architecture. */ void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...); -void kvm_irq_line(struct kvm_vm *vm, uint32_t irq, int level); -int _kvm_irq_line(struct kvm_vm *vm, uint32_t irq, int level); +void kvm_irq_line(struct kvm_vm *vm, u32 irq, int level); +int _kvm_irq_line(struct kvm_vm *vm, u32 irq, int level); #define KVM_MAX_IRQ_ROUTES 4096 struct kvm_irq_routing *kvm_gsi_routing_create(void); void kvm_gsi_routing_irqchip_add(struct kvm_irq_routing *routing, - uint32_t gsi, uint32_t pin); + u32 gsi, u32 pin); int _kvm_gsi_routing_write(struct kvm_vm *vm, struct kvm_irq_routing *routing); void kvm_gsi_routing_write(struct kvm_vm *vm, struct kvm_irq_routing *routing); const char *exit_reason_str(unsigned int exit_reason); -vm_paddr_t vm_phy_page_alloc(struct kvm_vm *vm, vm_paddr_t paddr_min, - uint32_t memslot); -vm_paddr_t __vm_phy_pages_alloc(struct kvm_vm *vm, size_t num, - vm_paddr_t paddr_min, uint32_t memslot, - bool protected); -vm_paddr_t vm_alloc_page_table(struct kvm_vm *vm); +gpa_t vm_phy_page_alloc(struct kvm_vm *vm, gpa_t min_gpa, u32 memslot); +gpa_t __vm_phy_pages_alloc(struct kvm_vm *vm, size_t num, gpa_t min_gpa, + u32 memslot, bool protected); +gpa_t vm_alloc_page_table(struct kvm_vm *vm); -static inline vm_paddr_t vm_phy_pages_alloc(struct kvm_vm *vm, size_t num, - vm_paddr_t paddr_min, uint32_t memslot) +static inline gpa_t vm_phy_pages_alloc(struct kvm_vm *vm, size_t num, + gpa_t min_gpa, u32 memslot) { /* * By default, allocate memory as protected for VMs that support * protected memory, as the majority of memory for such VMs is * protected, i.e. using shared memory is effectively opt-in. */ - return __vm_phy_pages_alloc(vm, num, paddr_min, memslot, + return __vm_phy_pages_alloc(vm, num, min_gpa, memslot, vm_arch_has_protected_memory(vm)); } @@ -1016,8 +1014,8 @@ static inline vm_paddr_t vm_phy_pages_alloc(struct kvm_vm *vm, size_t num, * calculate the amount of memory needed for per-vCPU data, e.g. stacks. */ struct kvm_vm *____vm_create(struct vm_shape shape); -struct kvm_vm *__vm_create(struct vm_shape shape, uint32_t nr_runnable_vcpus, - uint64_t nr_extra_pages); +struct kvm_vm *__vm_create(struct vm_shape shape, u32 nr_runnable_vcpus, + u64 nr_extra_pages); static inline struct kvm_vm *vm_create_barebones(void) { @@ -1034,16 +1032,16 @@ static inline struct kvm_vm *vm_create_barebones_type(unsigned long type) return ____vm_create(shape); } -static inline struct kvm_vm *vm_create(uint32_t nr_runnable_vcpus) +static inline struct kvm_vm *vm_create(u32 nr_runnable_vcpus) { return __vm_create(VM_SHAPE_DEFAULT, nr_runnable_vcpus, 0); } -struct kvm_vm *__vm_create_with_vcpus(struct vm_shape shape, uint32_t nr_vcpus, - uint64_t extra_mem_pages, +struct kvm_vm *__vm_create_with_vcpus(struct vm_shape shape, u32 nr_vcpus, + u64 extra_mem_pages, void *guest_code, struct kvm_vcpu *vcpus[]); -static inline struct kvm_vm *vm_create_with_vcpus(uint32_t nr_vcpus, +static inline struct kvm_vm *vm_create_with_vcpus(u32 nr_vcpus, void *guest_code, struct kvm_vcpu *vcpus[]) { @@ -1054,7 +1052,7 @@ static inline struct kvm_vm *vm_create_with_vcpus(uint32_t nr_vcpus, struct kvm_vm *__vm_create_shape_with_one_vcpu(struct vm_shape shape, struct kvm_vcpu **vcpu, - uint64_t extra_mem_pages, + u64 extra_mem_pages, void *guest_code); /* @@ -1062,7 +1060,7 @@ struct kvm_vm *__vm_create_shape_with_one_vcpu(struct vm_shape shape, * additional pages of guest memory. Returns the VM and vCPU (via out param). */ static inline struct kvm_vm *__vm_create_with_one_vcpu(struct kvm_vcpu **vcpu, - uint64_t extra_mem_pages, + u64 extra_mem_pages, void *guest_code) { return __vm_create_shape_with_one_vcpu(VM_SHAPE_DEFAULT, vcpu, @@ -1084,7 +1082,7 @@ static inline struct kvm_vm *vm_create_shape_with_one_vcpu(struct vm_shape shape struct kvm_vcpu *vm_recreate_with_one_vcpu(struct kvm_vm *vm); -void kvm_set_files_rlimit(uint32_t nr_vcpus); +void kvm_set_files_rlimit(u32 nr_vcpus); int __pin_task_to_cpu(pthread_t task, int cpu); @@ -1115,7 +1113,7 @@ static inline int pin_self_to_any_cpu(void) } void kvm_print_vcpu_pinning_help(void); -void kvm_parse_vcpu_pinning(const char *pcpus_string, uint32_t vcpu_to_pcpu[], +void kvm_parse_vcpu_pinning(const char *pcpus_string, u32 vcpu_to_pcpu[], int nr_vcpus); unsigned long vm_compute_max_gfn(struct kvm_vm *vm); @@ -1131,12 +1129,12 @@ vm_adjust_num_guest_pages(enum vm_guest_mode mode, unsigned int num_guest_pages) } #define sync_global_to_guest(vm, g) ({ \ - typeof(g) *_p = addr_gva2hva(vm, (vm_vaddr_t)&(g)); \ + typeof(g) *_p = addr_gva2hva(vm, (gva_t)&(g)); \ memcpy(_p, &(g), sizeof(g)); \ }) #define sync_global_from_guest(vm, g) ({ \ - typeof(g) *_p = addr_gva2hva(vm, (vm_vaddr_t)&(g)); \ + typeof(g) *_p = addr_gva2hva(vm, (gva_t)&(g)); \ memcpy(&(g), _p, sizeof(g)); \ }) @@ -1147,7 +1145,7 @@ vm_adjust_num_guest_pages(enum vm_guest_mode mode, unsigned int num_guest_pages) * undesirable to change the host's copy of the global. */ #define write_guest_global(vm, g, val) ({ \ - typeof(g) *_p = addr_gva2hva(vm, (vm_vaddr_t)&(g)); \ + typeof(g) *_p = addr_gva2hva(vm, (gva_t)&(g)); \ typeof(g) _val = val; \ \ memcpy(_p, &(_val), sizeof(g)); \ @@ -1156,10 +1154,10 @@ vm_adjust_num_guest_pages(enum vm_guest_mode mode, unsigned int num_guest_pages) void assert_on_unhandled_exception(struct kvm_vcpu *vcpu); void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, - uint8_t indent); + u8 indent); static inline void vcpu_dump(FILE *stream, struct kvm_vcpu *vcpu, - uint8_t indent) + u8 indent) { vcpu_arch_dump(stream, vcpu, indent); } @@ -1171,10 +1169,10 @@ static inline void vcpu_dump(FILE *stream, struct kvm_vcpu *vcpu, * vm - Virtual Machine * vcpu_id - The id of the VCPU to add to the VM. */ -struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id); +struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u32 vcpu_id); void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code); -static inline struct kvm_vcpu *vm_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, +static inline struct kvm_vcpu *vm_vcpu_add(struct kvm_vm *vm, u32 vcpu_id, void *guest_code) { struct kvm_vcpu *vcpu = vm_arch_vcpu_add(vm, vcpu_id); @@ -1185,10 +1183,10 @@ static inline struct kvm_vcpu *vm_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, } /* Re-create a vCPU after restarting a VM, e.g. for state save/restore tests. */ -struct kvm_vcpu *vm_arch_vcpu_recreate(struct kvm_vm *vm, uint32_t vcpu_id); +struct kvm_vcpu *vm_arch_vcpu_recreate(struct kvm_vm *vm, u32 vcpu_id); static inline struct kvm_vcpu *vm_vcpu_recreate(struct kvm_vm *vm, - uint32_t vcpu_id) + u32 vcpu_id) { return vm_arch_vcpu_recreate(vm, vcpu_id); } @@ -1203,27 +1201,15 @@ static inline void virt_pgd_alloc(struct kvm_vm *vm) } /* - * VM Virtual Page Map - * - * Input Args: - * vm - Virtual Machine - * vaddr - VM Virtual Address - * paddr - VM Physical Address - * memslot - Memory region slot for new virtual translation tables - * - * Output Args: None - * - * Return: None - * * Within @vm, creates a virtual translation for the page starting - * at @vaddr to the page starting at @paddr. + * at @gva to the page starting at @gpa. */ -void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr); +void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa); -static inline void virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr) +static inline void virt_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa) { - virt_arch_pg_map(vm, vaddr, paddr); - sparsebit_set(vm->vpages_mapped, vaddr >> vm->page_shift); + virt_arch_pg_map(vm, gva, gpa); + sparsebit_set(vm->vpages_mapped, gva >> vm->page_shift); } @@ -1242,9 +1228,9 @@ static inline void virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr * Returns the VM physical address of the translated VM virtual * address given by @gva. */ -vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva); +gpa_t addr_arch_gva2gpa(struct kvm_vm *vm, gva_t gva); -static inline vm_paddr_t addr_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) +static inline gpa_t addr_gva2gpa(struct kvm_vm *vm, gva_t gva) { return addr_arch_gva2gpa(vm, gva); } @@ -1264,9 +1250,9 @@ static inline vm_paddr_t addr_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) * Dumps to the FILE stream given by @stream, the contents of all the * virtual translation tables for the VM given by @vm. */ -void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent); +void virt_arch_dump(FILE *stream, struct kvm_vm *vm, u8 indent); -static inline void virt_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) +static inline void virt_dump(FILE *stream, struct kvm_vm *vm, u8 indent) { virt_arch_dump(stream, vm, indent); } @@ -1277,7 +1263,7 @@ static inline int __vm_disable_nx_huge_pages(struct kvm_vm *vm) return __vm_enable_cap(vm, KVM_CAP_VM_DISABLE_NX_HUGE_PAGES, 0); } -static inline uint64_t vm_page_align(struct kvm_vm *vm, uint64_t v) +static inline u64 vm_page_align(struct kvm_vm *vm, u64 v) { return (v + vm->page_size - 1) & ~(vm->page_size - 1); } @@ -1293,9 +1279,9 @@ void kvm_arch_vm_post_create(struct kvm_vm *vm, unsigned int nr_vcpus); void kvm_arch_vm_finalize_vcpus(struct kvm_vm *vm); void kvm_arch_vm_release(struct kvm_vm *vm); -bool vm_is_gpa_protected(struct kvm_vm *vm, vm_paddr_t paddr); +bool vm_is_gpa_protected(struct kvm_vm *vm, gpa_t gpa); -uint32_t guest_get_vcpuid(void); +u32 guest_get_vcpuid(void); bool kvm_arch_has_default_irqchip(void); diff --git a/tools/testing/selftests/kvm/include/kvm_util_types.h b/tools/testing/selftests/kvm/include/kvm_util_types.h index 0366e9bce7f9..ed0087e31674 100644 --- a/tools/testing/selftests/kvm/include/kvm_util_types.h +++ b/tools/testing/selftests/kvm/include/kvm_util_types.h @@ -2,6 +2,8 @@ #ifndef SELFTEST_KVM_UTIL_TYPES_H #define SELFTEST_KVM_UTIL_TYPES_H +#include + /* * Provide a version of static_assert() that is guaranteed to have an optional * message param. _GNU_SOURCE is defined for all KVM selftests, _GNU_SOURCE @@ -14,9 +16,9 @@ #define __kvm_static_assert(expr, msg, ...) _Static_assert(expr, msg) #define kvm_static_assert(expr, ...) __kvm_static_assert(expr, ##__VA_ARGS__, #expr) -typedef uint64_t vm_paddr_t; /* Virtual Machine (Guest) physical address */ -typedef uint64_t vm_vaddr_t; /* Virtual Machine (Guest) virtual address */ +typedef u64 gpa_t; /* Virtual Machine (Guest) physical address */ +typedef u64 gva_t; /* Virtual Machine (Guest) virtual address */ -#define INVALID_GPA (~(uint64_t)0) +#define INVALID_GPA (~(u64)0) #endif /* SELFTEST_KVM_UTIL_TYPES_H */ diff --git a/tools/testing/selftests/kvm/include/loongarch/arch_timer.h b/tools/testing/selftests/kvm/include/loongarch/arch_timer.h index 2ed106b32c81..3888aeeb3524 100644 --- a/tools/testing/selftests/kvm/include/loongarch/arch_timer.h +++ b/tools/testing/selftests/kvm/include/loongarch/arch_timer.h @@ -70,9 +70,9 @@ static inline void timer_set_next_cmp_ms(unsigned int msec, bool period) csr_write(val, LOONGARCH_CSR_TCFG); } -static inline void __delay(uint64_t cycles) +static inline void __delay(u64 cycles) { - uint64_t start = timer_get_cycles(); + u64 start = timer_get_cycles(); while ((timer_get_cycles() - start) < cycles) cpu_relax(); diff --git a/tools/testing/selftests/kvm/include/loongarch/ucall.h b/tools/testing/selftests/kvm/include/loongarch/ucall.h index 4ec801f37f00..2210d3d94c40 100644 --- a/tools/testing/selftests/kvm/include/loongarch/ucall.h +++ b/tools/testing/selftests/kvm/include/loongarch/ucall.h @@ -10,9 +10,9 @@ * ucall_exit_mmio_addr holds per-VM values (global data is duplicated by each * VM), it must not be accessed from host code. */ -extern vm_vaddr_t *ucall_exit_mmio_addr; +extern gva_t *ucall_exit_mmio_addr; -static inline void ucall_arch_do_ucall(vm_vaddr_t uc) +static inline void ucall_arch_do_ucall(gva_t uc) { WRITE_ONCE(*ucall_exit_mmio_addr, uc); } diff --git a/tools/testing/selftests/kvm/include/memstress.h b/tools/testing/selftests/kvm/include/memstress.h index 9071eb6dea60..0d1d6230cc05 100644 --- a/tools/testing/selftests/kvm/include/memstress.h +++ b/tools/testing/selftests/kvm/include/memstress.h @@ -20,9 +20,9 @@ #define MEMSTRESS_MEM_SLOT_INDEX 1 struct memstress_vcpu_args { - uint64_t gpa; - uint64_t gva; - uint64_t pages; + gpa_t gpa; + gva_t gva; + u64 pages; /* Only used by the host userspace part of the vCPU thread */ struct kvm_vcpu *vcpu; @@ -32,11 +32,11 @@ struct memstress_vcpu_args { struct memstress_args { struct kvm_vm *vm; /* The starting address and size of the guest test region. */ - uint64_t gpa; - uint64_t size; - uint64_t guest_page_size; - uint32_t random_seed; - uint32_t write_percent; + gpa_t gpa; + u64 size; + u64 guest_page_size; + u32 random_seed; + u32 write_percent; /* Run vCPUs in L2 instead of L1, if the architecture supports it. */ bool nested; @@ -45,7 +45,7 @@ struct memstress_args { /* True if all vCPUs are pinned to pCPUs */ bool pin_vcpus; /* The vCPU=>pCPU pinning map. Only valid if pin_vcpus is true. */ - uint32_t vcpu_to_pcpu[KVM_MAX_VCPUS]; + u32 vcpu_to_pcpu[KVM_MAX_VCPUS]; /* Test is done, stop running vCPUs. */ bool stop_vcpus; @@ -56,27 +56,27 @@ struct memstress_args { extern struct memstress_args memstress_args; struct kvm_vm *memstress_create_vm(enum vm_guest_mode mode, int nr_vcpus, - uint64_t vcpu_memory_bytes, int slots, + u64 vcpu_memory_bytes, int slots, enum vm_mem_backing_src_type backing_src, bool partition_vcpu_memory_access); void memstress_destroy_vm(struct kvm_vm *vm); -void memstress_set_write_percent(struct kvm_vm *vm, uint32_t write_percent); +void memstress_set_write_percent(struct kvm_vm *vm, u32 write_percent); void memstress_set_random_access(struct kvm_vm *vm, bool random_access); void memstress_start_vcpu_threads(int vcpus, void (*vcpu_fn)(struct memstress_vcpu_args *)); void memstress_join_vcpu_threads(int vcpus); -void memstress_guest_code(uint32_t vcpu_id); +void memstress_guest_code(u32 vcpu_id); -uint64_t memstress_nested_pages(int nr_vcpus); +u64 memstress_nested_pages(int nr_vcpus); void memstress_setup_nested(struct kvm_vm *vm, int nr_vcpus, struct kvm_vcpu *vcpus[]); void memstress_enable_dirty_logging(struct kvm_vm *vm, int slots); void memstress_disable_dirty_logging(struct kvm_vm *vm, int slots); void memstress_get_dirty_log(struct kvm_vm *vm, unsigned long *bitmaps[], int slots); void memstress_clear_dirty_log(struct kvm_vm *vm, unsigned long *bitmaps[], - int slots, uint64_t pages_per_slot); -unsigned long **memstress_alloc_bitmaps(int slots, uint64_t pages_per_slot); + int slots, u64 pages_per_slot); +unsigned long **memstress_alloc_bitmaps(int slots, u64 pages_per_slot); void memstress_free_bitmaps(unsigned long *bitmaps[], int slots); #endif /* SELFTEST_KVM_MEMSTRESS_H */ diff --git a/tools/testing/selftests/kvm/include/riscv/arch_timer.h b/tools/testing/selftests/kvm/include/riscv/arch_timer.h index 225d81dad064..28ffc014da2a 100644 --- a/tools/testing/selftests/kvm/include/riscv/arch_timer.h +++ b/tools/testing/selftests/kvm/include/riscv/arch_timer.h @@ -14,25 +14,25 @@ static unsigned long timer_freq; #define msec_to_cycles(msec) \ - ((timer_freq) * (uint64_t)(msec) / 1000) + ((timer_freq) * (u64)(msec) / 1000) #define usec_to_cycles(usec) \ - ((timer_freq) * (uint64_t)(usec) / 1000000) + ((timer_freq) * (u64)(usec) / 1000000) #define cycles_to_usec(cycles) \ - ((uint64_t)(cycles) * 1000000 / (timer_freq)) + ((u64)(cycles) * 1000000 / (timer_freq)) -static inline uint64_t timer_get_cycles(void) +static inline u64 timer_get_cycles(void) { return csr_read(CSR_TIME); } -static inline void timer_set_cmp(uint64_t cval) +static inline void timer_set_cmp(u64 cval) { csr_write(CSR_STIMECMP, cval); } -static inline uint64_t timer_get_cmp(void) +static inline u64 timer_get_cmp(void) { return csr_read(CSR_STIMECMP); } @@ -47,17 +47,17 @@ static inline void timer_irq_disable(void) csr_clear(CSR_SIE, IE_TIE); } -static inline void timer_set_next_cmp_ms(uint32_t msec) +static inline void timer_set_next_cmp_ms(u32 msec) { - uint64_t now_ct = timer_get_cycles(); - uint64_t next_ct = now_ct + msec_to_cycles(msec); + u64 now_ct = timer_get_cycles(); + u64 next_ct = now_ct + msec_to_cycles(msec); timer_set_cmp(next_ct); } -static inline void __delay(uint64_t cycles) +static inline void __delay(u64 cycles) { - uint64_t start = timer_get_cycles(); + u64 start = timer_get_cycles(); while ((timer_get_cycles() - start) < cycles) cpu_relax(); diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h index 4dade8c4d18e..e3acf2ae9881 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -25,8 +25,7 @@ #define GET_RM(insn) (((insn) & INSN_MASK_FUNCT3) >> INSN_SHIFT_FUNCT3) #define GET_CSR_NUM(insn) (((insn) & INSN_CSR_MASK) >> INSN_CSR_SHIFT) -static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t subtype, - uint64_t idx, uint64_t size) +static inline u64 __kvm_reg_id(u64 type, u64 subtype, u64 idx, u64 size) { return KVM_REG_RISCV | type | subtype | idx | size; } @@ -62,14 +61,14 @@ static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t subtype, KVM_REG_RISCV_SBI_SINGLE, \ idx, KVM_REG_SIZE_ULONG) -bool __vcpu_has_ext(struct kvm_vcpu *vcpu, uint64_t ext); +bool __vcpu_has_ext(struct kvm_vcpu *vcpu, u64 ext); -static inline bool __vcpu_has_isa_ext(struct kvm_vcpu *vcpu, uint64_t isa_ext) +static inline bool __vcpu_has_isa_ext(struct kvm_vcpu *vcpu, u64 isa_ext) { return __vcpu_has_ext(vcpu, RISCV_ISA_EXT_REG(isa_ext)); } -static inline bool __vcpu_has_sbi_ext(struct kvm_vcpu *vcpu, uint64_t sbi_ext) +static inline bool __vcpu_has_sbi_ext(struct kvm_vcpu *vcpu, u64 sbi_ext) { return __vcpu_has_ext(vcpu, RISCV_SBI_EXT_REG(sbi_ext)); } diff --git a/tools/testing/selftests/kvm/include/riscv/ucall.h b/tools/testing/selftests/kvm/include/riscv/ucall.h index a695ae36f3e0..2de7c6a36096 100644 --- a/tools/testing/selftests/kvm/include/riscv/ucall.h +++ b/tools/testing/selftests/kvm/include/riscv/ucall.h @@ -7,11 +7,11 @@ #define UCALL_EXIT_REASON KVM_EXIT_RISCV_SBI -static inline void ucall_arch_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa) +static inline void ucall_arch_init(struct kvm_vm *vm, gpa_t mmio_gpa) { } -static inline void ucall_arch_do_ucall(vm_vaddr_t uc) +static inline void ucall_arch_do_ucall(gva_t uc) { sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT, KVM_RISCV_SELFTESTS_SBI_UCALL, diff --git a/tools/testing/selftests/kvm/include/s390/diag318_test_handler.h b/tools/testing/selftests/kvm/include/s390/diag318_test_handler.h index b0ed71302722..6deaf18fec22 100644 --- a/tools/testing/selftests/kvm/include/s390/diag318_test_handler.h +++ b/tools/testing/selftests/kvm/include/s390/diag318_test_handler.h @@ -8,6 +8,6 @@ #ifndef SELFTEST_KVM_DIAG318_TEST_HANDLER #define SELFTEST_KVM_DIAG318_TEST_HANDLER -uint64_t get_diag318_info(void); +u64 get_diag318_info(void); #endif diff --git a/tools/testing/selftests/kvm/include/s390/facility.h b/tools/testing/selftests/kvm/include/s390/facility.h index 00a1ced6538b..41a265742666 100644 --- a/tools/testing/selftests/kvm/include/s390/facility.h +++ b/tools/testing/selftests/kvm/include/s390/facility.h @@ -16,7 +16,7 @@ /* alt_stfle_fac_list[16] + stfle_fac_list[16] */ #define NB_STFL_DOUBLEWORDS 32 -extern uint64_t stfl_doublewords[NB_STFL_DOUBLEWORDS]; +extern u64 stfl_doublewords[NB_STFL_DOUBLEWORDS]; extern bool stfle_flag; static inline bool test_bit_inv(unsigned long nr, const unsigned long *ptr) @@ -24,7 +24,7 @@ static inline bool test_bit_inv(unsigned long nr, const unsigned long *ptr) return test_bit(nr ^ (BITS_PER_LONG - 1), ptr); } -static inline void stfle(uint64_t *fac, unsigned int nb_doublewords) +static inline void stfle(u64 *fac, unsigned int nb_doublewords) { register unsigned long r0 asm("0") = nb_doublewords - 1; diff --git a/tools/testing/selftests/kvm/include/s390/ucall.h b/tools/testing/selftests/kvm/include/s390/ucall.h index 8035a872a351..3907d629304f 100644 --- a/tools/testing/selftests/kvm/include/s390/ucall.h +++ b/tools/testing/selftests/kvm/include/s390/ucall.h @@ -6,11 +6,11 @@ #define UCALL_EXIT_REASON KVM_EXIT_S390_SIEIC -static inline void ucall_arch_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa) +static inline void ucall_arch_init(struct kvm_vm *vm, gpa_t mmio_gpa) { } -static inline void ucall_arch_do_ucall(vm_vaddr_t uc) +static inline void ucall_arch_do_ucall(gva_t uc) { /* Exit via DIAGNOSE 0x501 (normally used for breakpoints) */ asm volatile ("diag 0,%0,0x501" : : "a"(uc) : "memory"); diff --git a/tools/testing/selftests/kvm/include/sparsebit.h b/tools/testing/selftests/kvm/include/sparsebit.h index bc760761e1a3..e027e5790946 100644 --- a/tools/testing/selftests/kvm/include/sparsebit.h +++ b/tools/testing/selftests/kvm/include/sparsebit.h @@ -6,7 +6,7 @@ * * Header file that describes API to the sparsebit library. * This library provides a memory efficient means of storing - * the settings of bits indexed via a uint64_t. Memory usage + * the settings of bits indexed via a u64. Memory usage * is reasonable, significantly less than (2^64 / 8) bytes, as * long as bits that are mostly set or mostly cleared are close * to each other. This library is efficient in memory usage @@ -25,8 +25,8 @@ extern "C" { #endif struct sparsebit; -typedef uint64_t sparsebit_idx_t; -typedef uint64_t sparsebit_num_t; +typedef u64 sparsebit_idx_t; +typedef u64 sparsebit_num_t; struct sparsebit *sparsebit_alloc(void); void sparsebit_free(struct sparsebit **sbitp); diff --git a/tools/testing/selftests/kvm/include/test_util.h b/tools/testing/selftests/kvm/include/test_util.h index b4872ba8ed12..d9b433b834f1 100644 --- a/tools/testing/selftests/kvm/include/test_util.h +++ b/tools/testing/selftests/kvm/include/test_util.h @@ -22,6 +22,8 @@ #include #include "kselftest.h" +#include + #define msecs_to_usecs(msec) ((msec) * 1000ULL) static inline __printf(1, 2) int _no_printf(const char *format, ...) { return 0; } @@ -99,25 +101,25 @@ do { \ size_t parse_size(const char *size); -int64_t timespec_to_ns(struct timespec ts); -struct timespec timespec_add_ns(struct timespec ts, int64_t ns); +s64 timespec_to_ns(struct timespec ts); +struct timespec timespec_add_ns(struct timespec ts, s64 ns); struct timespec timespec_add(struct timespec ts1, struct timespec ts2); struct timespec timespec_sub(struct timespec ts1, struct timespec ts2); struct timespec timespec_elapsed(struct timespec start); struct timespec timespec_div(struct timespec ts, int divisor); struct guest_random_state { - uint32_t seed; + u32 seed; }; -extern uint32_t guest_random_seed; +extern u32 guest_random_seed; extern struct guest_random_state guest_rng; -struct guest_random_state new_guest_random_state(uint32_t seed); -uint32_t guest_random_u32(struct guest_random_state *state); +struct guest_random_state new_guest_random_state(u32 seed); +u32 guest_random_u32(struct guest_random_state *state); static inline bool __guest_random_bool(struct guest_random_state *state, - uint8_t percent) + u8 percent) { return (guest_random_u32(state) % 100) < percent; } @@ -127,9 +129,9 @@ static inline bool guest_random_bool(struct guest_random_state *state) return __guest_random_bool(state, 50); } -static inline uint64_t guest_random_u64(struct guest_random_state *state) +static inline u64 guest_random_u64(struct guest_random_state *state) { - return ((uint64_t)guest_random_u32(state) << 32) | guest_random_u32(state); + return ((u64)guest_random_u32(state) << 32) | guest_random_u32(state); } enum vm_mem_backing_src_type { @@ -158,7 +160,7 @@ enum vm_mem_backing_src_type { struct vm_mem_backing_src_alias { const char *name; - uint32_t flag; + u32 flag; }; #define MIN_RUN_DELAY_NS 200000UL @@ -166,9 +168,9 @@ struct vm_mem_backing_src_alias { bool thp_configured(void); size_t get_trans_hugepagesz(void); size_t get_def_hugetlb_pagesz(void); -const struct vm_mem_backing_src_alias *vm_mem_backing_src_alias(uint32_t i); -size_t get_backing_src_pagesz(uint32_t i); -bool is_backing_src_hugetlb(uint32_t i); +const struct vm_mem_backing_src_alias *vm_mem_backing_src_alias(u32 i); +size_t get_backing_src_pagesz(u32 i); +bool is_backing_src_hugetlb(u32 i); void backing_src_help(const char *flag); enum vm_mem_backing_src_type parse_backing_src_type(const char *type_name); long get_run_delay(void); @@ -189,18 +191,18 @@ static inline bool backing_src_can_be_huge(enum vm_mem_backing_src_type t) } /* Aligns x up to the next multiple of size. Size must be a power of 2. */ -static inline uint64_t align_up(uint64_t x, uint64_t size) +static inline u64 align_up(u64 x, u64 size) { - uint64_t mask = size - 1; + u64 mask = size - 1; TEST_ASSERT(size != 0 && !(size & (size - 1)), "size not a power of 2: %lu", size); return ((x + mask) & ~mask); } -static inline uint64_t align_down(uint64_t x, uint64_t size) +static inline u64 align_down(u64 x, u64 size) { - uint64_t x_aligned_up = align_up(x, size); + u64 x_aligned_up = align_up(x, size); if (x == x_aligned_up) return x; @@ -215,7 +217,7 @@ static inline void *align_ptr_up(void *x, size_t size) int atoi_paranoid(const char *num_str); -static inline uint32_t atoi_positive(const char *name, const char *num_str) +static inline u32 atoi_positive(const char *name, const char *num_str) { int num = atoi_paranoid(num_str); @@ -223,7 +225,7 @@ static inline uint32_t atoi_positive(const char *name, const char *num_str) return num; } -static inline uint32_t atoi_non_negative(const char *name, const char *num_str) +static inline u32 atoi_non_negative(const char *name, const char *num_str) { int num = atoi_paranoid(num_str); diff --git a/tools/testing/selftests/kvm/include/timer_test.h b/tools/testing/selftests/kvm/include/timer_test.h index 9b6edaafe6d4..b7d5d2c84701 100644 --- a/tools/testing/selftests/kvm/include/timer_test.h +++ b/tools/testing/selftests/kvm/include/timer_test.h @@ -18,21 +18,21 @@ /* Timer test cmdline parameters */ struct test_args { - uint32_t nr_vcpus; - uint32_t nr_iter; - uint32_t timer_period_ms; - uint32_t migration_freq_ms; - uint32_t timer_err_margin_us; + u32 nr_vcpus; + u32 nr_iter; + u32 timer_period_ms; + u32 migration_freq_ms; + u32 timer_err_margin_us; /* Members of struct kvm_arm_counter_offset */ - uint64_t counter_offset; - uint64_t reserved; + u64 counter_offset; + u64 reserved; }; /* Shared variables between host and guest */ struct test_vcpu_shared_data { - uint32_t nr_iter; + u32 nr_iter; int guest_stage; - uint64_t xcnt; + u64 xcnt; }; extern struct test_args test_args; diff --git a/tools/testing/selftests/kvm/include/ucall_common.h b/tools/testing/selftests/kvm/include/ucall_common.h index d9d6581b8d4f..cbdcb0a50c4f 100644 --- a/tools/testing/selftests/kvm/include/ucall_common.h +++ b/tools/testing/selftests/kvm/include/ucall_common.h @@ -21,26 +21,26 @@ enum { #define UCALL_BUFFER_LEN 1024 struct ucall { - uint64_t cmd; - uint64_t args[UCALL_MAX_ARGS]; + u64 cmd; + u64 args[UCALL_MAX_ARGS]; char buffer[UCALL_BUFFER_LEN]; /* Host virtual address of this struct. */ struct ucall *hva; }; -void ucall_arch_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa); -void ucall_arch_do_ucall(vm_vaddr_t uc); +void ucall_arch_init(struct kvm_vm *vm, gpa_t mmio_gpa); +void ucall_arch_do_ucall(gva_t uc); void *ucall_arch_get_ucall(struct kvm_vcpu *vcpu); -void ucall(uint64_t cmd, int nargs, ...); -__printf(2, 3) void ucall_fmt(uint64_t cmd, const char *fmt, ...); -__printf(5, 6) void ucall_assert(uint64_t cmd, const char *exp, +void ucall(u64 cmd, int nargs, ...); +__printf(2, 3) void ucall_fmt(u64 cmd, const char *fmt, ...); +__printf(5, 6) void ucall_assert(u64 cmd, const char *exp, const char *file, unsigned int line, const char *fmt, ...); -uint64_t get_ucall(struct kvm_vcpu *vcpu, struct ucall *uc); -void ucall_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa); -int ucall_nr_pages_required(uint64_t page_size); +u64 get_ucall(struct kvm_vcpu *vcpu, struct ucall *uc); +void ucall_init(struct kvm_vm *vm, gpa_t mmio_gpa); +int ucall_nr_pages_required(u64 page_size); /* * Perform userspace call without any associated data. This bare call avoids @@ -48,7 +48,7 @@ int ucall_nr_pages_required(uint64_t page_size); * the full ucall() are problematic and/or unwanted. Note, this will come out * as UCALL_NONE on the backend. */ -#define GUEST_UCALL_NONE() ucall_arch_do_ucall((vm_vaddr_t)NULL) +#define GUEST_UCALL_NONE() ucall_arch_do_ucall((gva_t)NULL) #define GUEST_SYNC_ARGS(stage, arg1, arg2, arg3, arg4) \ ucall(UCALL_SYNC, 6, "hello", stage, arg1, arg2, arg3, arg4) diff --git a/tools/testing/selftests/kvm/include/userfaultfd_util.h b/tools/testing/selftests/kvm/include/userfaultfd_util.h index 60f7f9d435dc..0bc1dc16600e 100644 --- a/tools/testing/selftests/kvm/include/userfaultfd_util.h +++ b/tools/testing/selftests/kvm/include/userfaultfd_util.h @@ -25,7 +25,7 @@ struct uffd_reader_args { struct uffd_desc { int uffd; - uint64_t num_readers; + u64 num_readers; /* Holds the write ends of the pipes for killing the readers. */ int *pipefds; pthread_t *readers; @@ -33,8 +33,8 @@ struct uffd_desc { }; struct uffd_desc *uffd_setup_demand_paging(int uffd_mode, useconds_t delay, - void *hva, uint64_t len, - uint64_t num_readers, + void *hva, u64 len, + u64 num_readers, uffd_handler_t handler); void uffd_stop_demand_paging(struct uffd_desc *uffd); diff --git a/tools/testing/selftests/kvm/include/x86/apic.h b/tools/testing/selftests/kvm/include/x86/apic.h index 5ca6bacbd70e..31887bdc3d6c 100644 --- a/tools/testing/selftests/kvm/include/x86/apic.h +++ b/tools/testing/selftests/kvm/include/x86/apic.h @@ -79,42 +79,42 @@ void apic_disable(void); void xapic_enable(void); void x2apic_enable(void); -static inline uint32_t get_bsp_flag(void) +static inline u32 get_bsp_flag(void) { return rdmsr(MSR_IA32_APICBASE) & MSR_IA32_APICBASE_BSP; } -static inline uint32_t xapic_read_reg(unsigned int reg) +static inline u32 xapic_read_reg(unsigned int reg) { - return ((volatile uint32_t *)APIC_DEFAULT_GPA)[reg >> 2]; + return ((volatile u32 *)APIC_DEFAULT_GPA)[reg >> 2]; } -static inline void xapic_write_reg(unsigned int reg, uint32_t val) +static inline void xapic_write_reg(unsigned int reg, u32 val) { - ((volatile uint32_t *)APIC_DEFAULT_GPA)[reg >> 2] = val; + ((volatile u32 *)APIC_DEFAULT_GPA)[reg >> 2] = val; } -static inline uint64_t x2apic_read_reg(unsigned int reg) +static inline u64 x2apic_read_reg(unsigned int reg) { return rdmsr(APIC_BASE_MSR + (reg >> 4)); } -static inline uint8_t x2apic_write_reg_safe(unsigned int reg, uint64_t value) +static inline u8 x2apic_write_reg_safe(unsigned int reg, u64 value) { return wrmsr_safe(APIC_BASE_MSR + (reg >> 4), value); } -static inline void x2apic_write_reg(unsigned int reg, uint64_t value) +static inline void x2apic_write_reg(unsigned int reg, u64 value) { - uint8_t fault = x2apic_write_reg_safe(reg, value); + u8 fault = x2apic_write_reg_safe(reg, value); __GUEST_ASSERT(!fault, "Unexpected fault 0x%x on WRMSR(%x) = %lx\n", fault, APIC_BASE_MSR + (reg >> 4), value); } -static inline void x2apic_write_reg_fault(unsigned int reg, uint64_t value) +static inline void x2apic_write_reg_fault(unsigned int reg, u64 value) { - uint8_t fault = x2apic_write_reg_safe(reg, value); + u8 fault = x2apic_write_reg_safe(reg, value); __GUEST_ASSERT(fault == GP_VECTOR, "Wanted #GP on WRMSR(%x) = %lx, got 0x%x\n", diff --git a/tools/testing/selftests/kvm/include/x86/evmcs.h b/tools/testing/selftests/kvm/include/x86/evmcs.h index 5a74bb30e2f8..be79bda024bf 100644 --- a/tools/testing/selftests/kvm/include/x86/evmcs.h +++ b/tools/testing/selftests/kvm/include/x86/evmcs.h @@ -10,9 +10,9 @@ #include "hyperv.h" #include "vmx.h" -#define u16 uint16_t -#define u32 uint32_t -#define u64 uint64_t +#define u16 u16 +#define u32 u32 +#define u64 u64 #define EVMCS_VERSION 1 @@ -245,7 +245,7 @@ static inline void evmcs_enable(void) enable_evmcs = true; } -static inline int evmcs_vmptrld(uint64_t vmcs_pa, void *vmcs) +static inline int evmcs_vmptrld(u64 vmcs_pa, void *vmcs) { current_vp_assist->current_nested_vmcs = vmcs_pa; current_vp_assist->enlighten_vmentry = 1; @@ -265,7 +265,7 @@ static inline bool load_evmcs(struct hyperv_test_pages *hv) return true; } -static inline int evmcs_vmptrst(uint64_t *value) +static inline int evmcs_vmptrst(u64 *value) { *value = current_vp_assist->current_nested_vmcs & ~HV_X64_MSR_VP_ASSIST_PAGE_ENABLE; @@ -273,7 +273,7 @@ static inline int evmcs_vmptrst(uint64_t *value) return 0; } -static inline int evmcs_vmread(uint64_t encoding, uint64_t *value) +static inline int evmcs_vmread(u64 encoding, u64 *value) { switch (encoding) { case GUEST_RIP: @@ -672,7 +672,7 @@ static inline int evmcs_vmread(uint64_t encoding, uint64_t *value) return 0; } -static inline int evmcs_vmwrite(uint64_t encoding, uint64_t value) +static inline int evmcs_vmwrite(u64 encoding, u64 value) { switch (encoding) { case GUEST_RIP: @@ -1226,9 +1226,9 @@ static inline int evmcs_vmlaunch(void) "pop %%rbp;" : [ret]"=&a"(ret) : [host_rsp]"r" - ((uint64_t)¤t_evmcs->host_rsp), + ((u64)¤t_evmcs->host_rsp), [host_rip]"r" - ((uint64_t)¤t_evmcs->host_rip) + ((u64)¤t_evmcs->host_rip) : "memory", "cc", "rbx", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"); return ret; @@ -1265,9 +1265,9 @@ static inline int evmcs_vmresume(void) "pop %%rbp;" : [ret]"=&a"(ret) : [host_rsp]"r" - ((uint64_t)¤t_evmcs->host_rsp), + ((u64)¤t_evmcs->host_rsp), [host_rip]"r" - ((uint64_t)¤t_evmcs->host_rip) + ((u64)¤t_evmcs->host_rip) : "memory", "cc", "rbx", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"); return ret; diff --git a/tools/testing/selftests/kvm/include/x86/hyperv.h b/tools/testing/selftests/kvm/include/x86/hyperv.h index f13e532be240..78003f5a22f3 100644 --- a/tools/testing/selftests/kvm/include/x86/hyperv.h +++ b/tools/testing/selftests/kvm/include/x86/hyperv.h @@ -254,12 +254,12 @@ * Issue a Hyper-V hypercall. Returns exception vector raised or 0, 'hv_status' * is set to the hypercall status (if no exception occurred). */ -static inline uint8_t __hyperv_hypercall(u64 control, vm_vaddr_t input_address, - vm_vaddr_t output_address, - uint64_t *hv_status) +static inline u8 __hyperv_hypercall(u64 control, gva_t input_address, + gva_t output_address, + u64 *hv_status) { - uint64_t error_code; - uint8_t vector; + u64 error_code; + u8 vector; /* Note both the hypercall and the "asm safe" clobber r9-r11. */ asm volatile("mov %[output_address], %%r8\n\t" @@ -274,11 +274,11 @@ static inline uint8_t __hyperv_hypercall(u64 control, vm_vaddr_t input_address, } /* Issue a Hyper-V hypercall and assert that it succeeded. */ -static inline void hyperv_hypercall(u64 control, vm_vaddr_t input_address, - vm_vaddr_t output_address) +static inline void hyperv_hypercall(u64 control, gva_t input_address, + gva_t output_address) { - uint64_t hv_status; - uint8_t vector; + u64 hv_status; + u8 vector; vector = __hyperv_hypercall(control, input_address, output_address, &hv_status); @@ -327,27 +327,27 @@ struct hv_vp_assist_page { extern struct hv_vp_assist_page *current_vp_assist; -int enable_vp_assist(uint64_t vp_assist_pa, void *vp_assist); +int enable_vp_assist(u64 vp_assist_pa, void *vp_assist); struct hyperv_test_pages { /* VP assist page */ void *vp_assist_hva; - uint64_t vp_assist_gpa; + u64 vp_assist_gpa; void *vp_assist; /* Partition assist page */ void *partition_assist_hva; - uint64_t partition_assist_gpa; + u64 partition_assist_gpa; void *partition_assist; /* Enlightened VMCS */ void *enlightened_vmcs_hva; - uint64_t enlightened_vmcs_gpa; + u64 enlightened_vmcs_gpa; void *enlightened_vmcs; }; struct hyperv_test_pages *vcpu_alloc_hyperv_test_pages(struct kvm_vm *vm, - vm_vaddr_t *p_hv_pages_gva); + gva_t *p_hv_pages_gva); /* HV_X64_MSR_TSC_INVARIANT_CONTROL bits */ #define HV_INVARIANT_TSC_EXPOSED BIT_ULL(0) diff --git a/tools/testing/selftests/kvm/include/x86/kvm_util_arch.h b/tools/testing/selftests/kvm/include/x86/kvm_util_arch.h index be35d26bb320..c33ab6e04171 100644 --- a/tools/testing/selftests/kvm/include/x86/kvm_util_arch.h +++ b/tools/testing/selftests/kvm/include/x86/kvm_util_arch.h @@ -11,19 +11,19 @@ extern bool is_forced_emulation_enabled; struct pte_masks { - uint64_t present; - uint64_t writable; - uint64_t user; - uint64_t readable; - uint64_t executable; - uint64_t accessed; - uint64_t dirty; - uint64_t huge; - uint64_t nx; - uint64_t c; - uint64_t s; + u64 present; + u64 writable; + u64 user; + u64 readable; + u64 executable; + u64 accessed; + u64 dirty; + u64 huge; + u64 nx; + u64 c; + u64 s; - uint64_t always_set; + u64 always_set; }; struct kvm_mmu_arch { @@ -33,12 +33,12 @@ struct kvm_mmu_arch { struct kvm_mmu; struct kvm_vm_arch { - vm_vaddr_t gdt; - vm_vaddr_t tss; - vm_vaddr_t idt; + gva_t gdt; + gva_t tss; + gva_t idt; - uint64_t c_bit; - uint64_t s_bit; + u64 c_bit; + u64 s_bit; int sev_fd; bool is_pt_protected; }; @@ -62,7 +62,7 @@ do { \ : "+m" (mem) \ : "r" (val) : "memory"); \ } else { \ - uint64_t __old = READ_ONCE(mem); \ + u64 __old = READ_ONCE(mem); \ \ __asm__ __volatile__(KVM_FEP LOCK_PREFIX "cmpxchg %[new], %[ptr]" \ : [ptr] "+m" (mem), [old] "+a" (__old) \ diff --git a/tools/testing/selftests/kvm/include/x86/pmu.h b/tools/testing/selftests/kvm/include/x86/pmu.h index 72575eadb63a..98537cc8840d 100644 --- a/tools/testing/selftests/kvm/include/x86/pmu.h +++ b/tools/testing/selftests/kvm/include/x86/pmu.h @@ -6,8 +6,8 @@ #define SELFTEST_KVM_PMU_H #include -#include +#include #include #define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300 @@ -104,14 +104,15 @@ enum amd_pmu_zen_events { NR_AMD_ZEN_EVENTS, }; -extern const uint64_t intel_pmu_arch_events[]; -extern const uint64_t amd_pmu_zen_events[]; +extern const u64 intel_pmu_arch_events[]; +extern const u64 amd_pmu_zen_events[]; enum pmu_errata { INSTRUCTIONS_RETIRED_OVERCOUNT, BRANCHES_RETIRED_OVERCOUNT, }; -extern uint64_t pmu_errata_mask; + +extern u64 pmu_errata_mask; void kvm_init_pmu_errata(void); diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/testing/selftests/kvm/include/x86/processor.h index d8634a760a60..77f576ee7789 100644 --- a/tools/testing/selftests/kvm/include/x86/processor.h +++ b/tools/testing/selftests/kvm/include/x86/processor.h @@ -23,7 +23,7 @@ extern bool host_cpu_is_intel; extern bool host_cpu_is_amd; extern bool host_cpu_is_hygon; extern bool host_cpu_is_amd_compatible; -extern uint64_t guest_tsc_khz; +extern u64 guest_tsc_khz; #ifndef MAX_NR_CPUID_ENTRIES #define MAX_NR_CPUID_ENTRIES 100 @@ -399,17 +399,17 @@ struct gpr64_regs { }; struct desc64 { - uint16_t limit0; - uint16_t base0; + u16 limit0; + u16 base0; unsigned base1:8, type:4, s:1, dpl:2, p:1; unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8; - uint32_t base3; - uint32_t zero1; + u32 base3; + u32 zero1; } __attribute__((packed)); struct desc_ptr { - uint16_t size; - uint64_t address; + u16 size; + u64 address; } __attribute__((packed)); struct kvm_x86_state { @@ -427,18 +427,18 @@ struct kvm_x86_state { struct kvm_msrs msrs; }; -static inline uint64_t get_desc64_base(const struct desc64 *desc) +static inline u64 get_desc64_base(const struct desc64 *desc) { - return (uint64_t)desc->base3 << 32 | - (uint64_t)desc->base2 << 24 | - (uint64_t)desc->base1 << 16 | - (uint64_t)desc->base0; + return (u64)desc->base3 << 32 | + (u64)desc->base2 << 24 | + (u64)desc->base1 << 16 | + (u64)desc->base0; } -static inline uint64_t rdtsc(void) +static inline u64 rdtsc(void) { - uint32_t eax, edx; - uint64_t tsc_val; + u32 eax, edx; + u64 tsc_val; /* * The lfence is to wait (on Intel CPUs) until all previous * instructions have been executed. If software requires RDTSC to be @@ -446,39 +446,39 @@ static inline uint64_t rdtsc(void) * execute LFENCE immediately after RDTSC */ __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); - tsc_val = ((uint64_t)edx) << 32 | eax; + tsc_val = ((u64)edx) << 32 | eax; return tsc_val; } -static inline uint64_t rdtscp(uint32_t *aux) +static inline u64 rdtscp(u32 *aux) { - uint32_t eax, edx; + u32 eax, edx; __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux)); - return ((uint64_t)edx) << 32 | eax; + return ((u64)edx) << 32 | eax; } -static inline uint64_t rdmsr(uint32_t msr) +static inline u64 rdmsr(u32 msr) { - uint32_t a, d; + u32 a, d; __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory"); - return a | ((uint64_t) d << 32); + return a | ((u64)d << 32); } -static inline void wrmsr(uint32_t msr, uint64_t value) +static inline void wrmsr(u32 msr, u64 value) { - uint32_t a = value; - uint32_t d = value >> 32; + u32 a = value; + u32 d = value >> 32; __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory"); } -static inline uint16_t inw(uint16_t port) +static inline u16 inw(u16 port) { - uint16_t tmp; + u16 tmp; __asm__ __volatile__("in %%dx, %%ax" : /* output */ "=a" (tmp) @@ -487,120 +487,120 @@ static inline uint16_t inw(uint16_t port) return tmp; } -static inline uint16_t get_es(void) +static inline u16 get_es(void) { - uint16_t es; + u16 es; __asm__ __volatile__("mov %%es, %[es]" : /* output */ [es]"=rm"(es)); return es; } -static inline uint16_t get_cs(void) +static inline u16 get_cs(void) { - uint16_t cs; + u16 cs; __asm__ __volatile__("mov %%cs, %[cs]" : /* output */ [cs]"=rm"(cs)); return cs; } -static inline uint16_t get_ss(void) +static inline u16 get_ss(void) { - uint16_t ss; + u16 ss; __asm__ __volatile__("mov %%ss, %[ss]" : /* output */ [ss]"=rm"(ss)); return ss; } -static inline uint16_t get_ds(void) +static inline u16 get_ds(void) { - uint16_t ds; + u16 ds; __asm__ __volatile__("mov %%ds, %[ds]" : /* output */ [ds]"=rm"(ds)); return ds; } -static inline uint16_t get_fs(void) +static inline u16 get_fs(void) { - uint16_t fs; + u16 fs; __asm__ __volatile__("mov %%fs, %[fs]" : /* output */ [fs]"=rm"(fs)); return fs; } -static inline uint16_t get_gs(void) +static inline u16 get_gs(void) { - uint16_t gs; + u16 gs; __asm__ __volatile__("mov %%gs, %[gs]" : /* output */ [gs]"=rm"(gs)); return gs; } -static inline uint16_t get_tr(void) +static inline u16 get_tr(void) { - uint16_t tr; + u16 tr; __asm__ __volatile__("str %[tr]" : /* output */ [tr]"=rm"(tr)); return tr; } -static inline uint64_t get_cr0(void) +static inline u64 get_cr0(void) { - uint64_t cr0; + u64 cr0; __asm__ __volatile__("mov %%cr0, %[cr0]" : /* output */ [cr0]"=r"(cr0)); return cr0; } -static inline void set_cr0(uint64_t val) +static inline void set_cr0(u64 val) { __asm__ __volatile__("mov %0, %%cr0" : : "r" (val) : "memory"); } -static inline uint64_t get_cr3(void) +static inline u64 get_cr3(void) { - uint64_t cr3; + u64 cr3; __asm__ __volatile__("mov %%cr3, %[cr3]" : /* output */ [cr3]"=r"(cr3)); return cr3; } -static inline void set_cr3(uint64_t val) +static inline void set_cr3(u64 val) { __asm__ __volatile__("mov %0, %%cr3" : : "r" (val) : "memory"); } -static inline uint64_t get_cr4(void) +static inline u64 get_cr4(void) { - uint64_t cr4; + u64 cr4; __asm__ __volatile__("mov %%cr4, %[cr4]" : /* output */ [cr4]"=r"(cr4)); return cr4; } -static inline void set_cr4(uint64_t val) +static inline void set_cr4(u64 val) { __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory"); } -static inline uint64_t get_cr8(void) +static inline u64 get_cr8(void) { - uint64_t cr8; + u64 cr8; __asm__ __volatile__("mov %%cr8, %[cr8]" : [cr8]"=r"(cr8)); return cr8; } -static inline void set_cr8(uint64_t val) +static inline void set_cr8(u64 val) { __asm__ __volatile__("mov %0, %%cr8" : : "r" (val) : "memory"); } @@ -651,14 +651,14 @@ static inline struct desc_ptr get_idt(void) return idt; } -static inline void outl(uint16_t port, uint32_t value) +static inline void outl(u16 port, u32 value) { __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value)); } -static inline void __cpuid(uint32_t function, uint32_t index, - uint32_t *eax, uint32_t *ebx, - uint32_t *ecx, uint32_t *edx) +static inline void __cpuid(u32 function, u32 index, + u32 *eax, u32 *ebx, + u32 *ecx, u32 *edx) { *eax = function; *ecx = index; @@ -672,35 +672,35 @@ static inline void __cpuid(uint32_t function, uint32_t index, : "memory"); } -static inline void cpuid(uint32_t function, - uint32_t *eax, uint32_t *ebx, - uint32_t *ecx, uint32_t *edx) +static inline void cpuid(u32 function, + u32 *eax, u32 *ebx, + u32 *ecx, u32 *edx) { return __cpuid(function, 0, eax, ebx, ecx, edx); } -static inline uint32_t this_cpu_fms(void) +static inline u32 this_cpu_fms(void) { - uint32_t eax, ebx, ecx, edx; + u32 eax, ebx, ecx, edx; cpuid(1, &eax, &ebx, &ecx, &edx); return eax; } -static inline uint32_t this_cpu_family(void) +static inline u32 this_cpu_family(void) { return x86_family(this_cpu_fms()); } -static inline uint32_t this_cpu_model(void) +static inline u32 this_cpu_model(void) { return x86_model(this_cpu_fms()); } static inline bool this_cpu_vendor_string_is(const char *vendor) { - const uint32_t *chunk = (const uint32_t *)vendor; - uint32_t eax, ebx, ecx, edx; + const u32 *chunk = (const u32 *)vendor; + u32 eax, ebx, ecx, edx; cpuid(0, &eax, &ebx, &ecx, &edx); return (ebx == chunk[0] && edx == chunk[1] && ecx == chunk[2]); @@ -724,10 +724,9 @@ static inline bool this_cpu_is_hygon(void) return this_cpu_vendor_string_is("HygonGenuine"); } -static inline uint32_t __this_cpu_has(uint32_t function, uint32_t index, - uint8_t reg, uint8_t lo, uint8_t hi) +static inline u32 __this_cpu_has(u32 function, u32 index, u8 reg, u8 lo, u8 hi) { - uint32_t gprs[4]; + u32 gprs[4]; __cpuid(function, index, &gprs[KVM_CPUID_EAX], &gprs[KVM_CPUID_EBX], @@ -742,7 +741,7 @@ static inline bool this_cpu_has(struct kvm_x86_cpu_feature feature) feature.reg, feature.bit, feature.bit); } -static inline uint32_t this_cpu_property(struct kvm_x86_cpu_property property) +static inline u32 this_cpu_property(struct kvm_x86_cpu_property property) { return __this_cpu_has(property.function, property.index, property.reg, property.lo_bit, property.hi_bit); @@ -750,7 +749,7 @@ static inline uint32_t this_cpu_property(struct kvm_x86_cpu_property property) static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property) { - uint32_t max_leaf; + u32 max_leaf; switch (property.function & 0xc0000000) { case 0: @@ -770,7 +769,7 @@ static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property) static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature) { - uint32_t nr_bits; + u32 nr_bits; if (feature.f.reg == KVM_CPUID_EBX) { nr_bits = this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); @@ -782,13 +781,13 @@ static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature) return nr_bits > feature.f.bit || this_cpu_has(feature.f); } -static __always_inline uint64_t this_cpu_supported_xcr0(void) +static __always_inline u64 this_cpu_supported_xcr0(void) { if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) return 0; return this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | - ((uint64_t)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); + ((u64)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); } typedef u32 __attribute__((vector_size(16))) sse128_t; @@ -867,7 +866,7 @@ static inline void cpu_relax(void) static inline void udelay(unsigned long usec) { - uint64_t start, now, cycles; + u64 start, now, cycles; GUEST_ASSERT(guest_tsc_khz); cycles = guest_tsc_khz / 1000 * usec; @@ -898,8 +897,8 @@ void kvm_x86_state_cleanup(struct kvm_x86_state *state); const struct kvm_msr_list *kvm_get_msr_index_list(void); const struct kvm_msr_list *kvm_get_feature_msr_index_list(void); -bool kvm_msr_is_in_save_restore_list(uint32_t msr_index); -uint64_t kvm_get_feature_msr(uint64_t msr_index); +bool kvm_msr_is_in_save_restore_list(u32 msr_index); +u64 kvm_get_feature_msr(u64 msr_index); static inline void vcpu_msrs_get(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs) @@ -954,20 +953,20 @@ static inline void vcpu_xcrs_set(struct kvm_vcpu *vcpu, struct kvm_xcrs *xcrs) } const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid, - uint32_t function, uint32_t index); + u32 function, u32 index); const struct kvm_cpuid2 *kvm_get_supported_cpuid(void); -static inline uint32_t kvm_cpu_fms(void) +static inline u32 kvm_cpu_fms(void) { return get_cpuid_entry(kvm_get_supported_cpuid(), 0x1, 0)->eax; } -static inline uint32_t kvm_cpu_family(void) +static inline u32 kvm_cpu_family(void) { return x86_family(kvm_cpu_fms()); } -static inline uint32_t kvm_cpu_model(void) +static inline u32 kvm_cpu_model(void) { return x86_model(kvm_cpu_fms()); } @@ -980,17 +979,17 @@ static inline bool kvm_cpu_has(struct kvm_x86_cpu_feature feature) return kvm_cpuid_has(kvm_get_supported_cpuid(), feature); } -uint32_t kvm_cpuid_property(const struct kvm_cpuid2 *cpuid, - struct kvm_x86_cpu_property property); +u32 kvm_cpuid_property(const struct kvm_cpuid2 *cpuid, + struct kvm_x86_cpu_property property); -static inline uint32_t kvm_cpu_property(struct kvm_x86_cpu_property property) +static inline u32 kvm_cpu_property(struct kvm_x86_cpu_property property) { return kvm_cpuid_property(kvm_get_supported_cpuid(), property); } static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property) { - uint32_t max_leaf; + u32 max_leaf; switch (property.function & 0xc0000000) { case 0: @@ -1010,7 +1009,7 @@ static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property) static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature) { - uint32_t nr_bits; + u32 nr_bits; if (feature.f.reg == KVM_CPUID_EBX) { nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); @@ -1022,13 +1021,13 @@ static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature) return nr_bits > feature.f.bit || kvm_cpu_has(feature.f); } -static __always_inline uint64_t kvm_cpu_supported_xcr0(void) +static __always_inline u64 kvm_cpu_supported_xcr0(void) { if (!kvm_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) return 0; return kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | - ((uint64_t)kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); + ((u64)kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); } static inline size_t kvm_cpuid2_size(int nr_entries) @@ -1062,8 +1061,8 @@ static inline void vcpu_get_cpuid(struct kvm_vcpu *vcpu) } static inline struct kvm_cpuid_entry2 *__vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, - uint32_t function, - uint32_t index) + u32 function, + u32 index) { TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first (or equivalent)"); @@ -1074,7 +1073,7 @@ static inline struct kvm_cpuid_entry2 *__vcpu_get_cpuid_entry(struct kvm_vcpu *v } static inline struct kvm_cpuid_entry2 *vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, - uint32_t function) + u32 function) { return __vcpu_get_cpuid_entry(vcpu, function, 0); } @@ -1104,10 +1103,10 @@ static inline void vcpu_set_cpuid(struct kvm_vcpu *vcpu) void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, struct kvm_x86_cpu_property property, - uint32_t value); -void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, uint8_t maxphyaddr); + u32 value); +void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, u8 maxphyaddr); -void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function); +void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, u32 function); static inline bool vcpu_cpuid_has(struct kvm_vcpu *vcpu, struct kvm_x86_cpu_feature feature) @@ -1135,8 +1134,8 @@ static inline void vcpu_clear_cpuid_feature(struct kvm_vcpu *vcpu, vcpu_set_or_clear_cpuid_feature(vcpu, feature, false); } -uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index); -int _vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index, uint64_t msr_value); +u64 vcpu_get_msr(struct kvm_vcpu *vcpu, u64 msr_index); +int _vcpu_set_msr(struct kvm_vcpu *vcpu, u64 msr_index, u64 msr_value); /* * Assert on an MSR access(es) and pretty print the MSR name when possible. @@ -1161,14 +1160,14 @@ do { \ * is changing, etc. This is NOT an exhaustive list! The intent is to filter * out MSRs that are not durable _and_ that a selftest wants to write. */ -static inline bool is_durable_msr(uint32_t msr) +static inline bool is_durable_msr(u32 msr) { return msr != MSR_IA32_TSC; } #define vcpu_set_msr(vcpu, msr, val) \ do { \ - uint64_t r, v = val; \ + u64 r, v = val; \ \ TEST_ASSERT_MSR(_vcpu_set_msr(vcpu, msr, v) == 1, \ "KVM_SET_MSRS failed on %s, value = 0x%lx", msr, #msr, v); \ @@ -1182,28 +1181,28 @@ void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits); void kvm_init_vm_address_properties(struct kvm_vm *vm); struct ex_regs { - uint64_t rax, rcx, rdx, rbx; - uint64_t rbp, rsi, rdi; - uint64_t r8, r9, r10, r11; - uint64_t r12, r13, r14, r15; - uint64_t vector; - uint64_t error_code; - uint64_t rip; - uint64_t cs; - uint64_t rflags; + u64 rax, rcx, rdx, rbx; + u64 rbp, rsi, rdi; + u64 r8, r9, r10, r11; + u64 r12, r13, r14, r15; + u64 vector; + u64 error_code; + u64 rip; + u64 cs; + u64 rflags; }; struct idt_entry { - uint16_t offset0; - uint16_t selector; - uint16_t ist : 3; - uint16_t : 5; - uint16_t type : 4; - uint16_t : 1; - uint16_t dpl : 2; - uint16_t p : 1; - uint16_t offset1; - uint32_t offset2; uint32_t reserved; + u16 offset0; + u16 selector; + u16 ist : 3; + u16 : 5; + u16 type : 4; + u16 : 1; + u16 dpl : 2; + u16 p : 1; + u16 offset1; + u32 offset2; u32 reserved; }; void vm_install_exception_handler(struct kvm_vm *vm, int vector, @@ -1262,8 +1261,8 @@ void vm_install_exception_handler(struct kvm_vm *vm, int vector, #define kvm_asm_safe(insn, inputs...) \ ({ \ - uint64_t ign_error_code; \ - uint8_t vector; \ + u64 ign_error_code; \ + u8 vector; \ \ asm volatile(KVM_ASM_SAFE(insn) \ : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ @@ -1274,7 +1273,7 @@ void vm_install_exception_handler(struct kvm_vm *vm, int vector, #define kvm_asm_safe_ec(insn, error_code, inputs...) \ ({ \ - uint8_t vector; \ + u8 vector; \ \ asm volatile(KVM_ASM_SAFE(insn) \ : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ @@ -1285,8 +1284,8 @@ void vm_install_exception_handler(struct kvm_vm *vm, int vector, #define kvm_asm_safe_fep(insn, inputs...) \ ({ \ - uint64_t ign_error_code; \ - uint8_t vector; \ + u64 ign_error_code; \ + u8 vector; \ \ asm volatile(KVM_ASM_SAFE_FEP(insn) \ : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ @@ -1297,7 +1296,7 @@ void vm_install_exception_handler(struct kvm_vm *vm, int vector, #define kvm_asm_safe_ec_fep(insn, error_code, inputs...) \ ({ \ - uint8_t vector; \ + u8 vector; \ \ asm volatile(KVM_ASM_SAFE_FEP(insn) \ : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ @@ -1307,11 +1306,11 @@ void vm_install_exception_handler(struct kvm_vm *vm, int vector, }) #define BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \ -static inline uint8_t insn##_safe ##_fep(uint32_t idx, uint64_t *val) \ +static inline u8 insn##_safe ##_fep(u32 idx, u64 *val) \ { \ - uint64_t error_code; \ - uint8_t vector; \ - uint32_t a, d; \ + u64 error_code; \ + u8 vector; \ + u32 a, d; \ \ asm volatile(KVM_ASM_SAFE##_FEP(#insn) \ : "=a"(a), "=d"(d), \ @@ -1319,7 +1318,7 @@ static inline uint8_t insn##_safe ##_fep(uint32_t idx, uint64_t *val) \ : "c"(idx) \ : KVM_ASM_SAFE_CLOBBERS); \ \ - *val = (uint64_t)a | ((uint64_t)d << 32); \ + *val = (u64)a | ((u64)d << 32); \ return vector; \ } @@ -1335,12 +1334,12 @@ BUILD_READ_U64_SAFE_HELPERS(rdmsr) BUILD_READ_U64_SAFE_HELPERS(rdpmc) BUILD_READ_U64_SAFE_HELPERS(xgetbv) -static inline uint8_t wrmsr_safe(uint32_t msr, uint64_t val) +static inline u8 wrmsr_safe(u32 msr, u64 val) { return kvm_asm_safe("wrmsr", "a"(val & -1u), "d"(val >> 32), "c"(msr)); } -static inline uint8_t xsetbv_safe(uint32_t index, uint64_t value) +static inline u8 xsetbv_safe(u32 index, u64 value) { u32 eax = value; u32 edx = value >> 32; @@ -1395,23 +1394,20 @@ static inline bool kvm_is_lbrv_enabled(void) return !!get_kvm_amd_param_integer("lbrv"); } -uint64_t *vm_get_pte(struct kvm_vm *vm, uint64_t vaddr); +u64 *vm_get_pte(struct kvm_vm *vm, gva_t gva); -uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2, - uint64_t a3); -uint64_t __xen_hypercall(uint64_t nr, uint64_t a0, void *a1); -void xen_hypercall(uint64_t nr, uint64_t a0, void *a1); +u64 kvm_hypercall(u64 nr, u64 a0, u64 a1, u64 a2, u64 a3); +u64 __xen_hypercall(u64 nr, u64 a0, void *a1); +void xen_hypercall(u64 nr, u64 a0, void *a1); -static inline uint64_t __kvm_hypercall_map_gpa_range(uint64_t gpa, - uint64_t size, uint64_t flags) +static inline u64 __kvm_hypercall_map_gpa_range(gpa_t gpa, u64 size, u64 flags) { return kvm_hypercall(KVM_HC_MAP_GPA_RANGE, gpa, size >> PAGE_SHIFT, flags, 0); } -static inline void kvm_hypercall_map_gpa_range(uint64_t gpa, uint64_t size, - uint64_t flags) +static inline void kvm_hypercall_map_gpa_range(gpa_t gpa, u64 size, u64 flags) { - uint64_t ret = __kvm_hypercall_map_gpa_range(gpa, size, flags); + u64 ret = __kvm_hypercall_map_gpa_range(gpa, size, flags); GUEST_ASSERT(!ret); } @@ -1456,7 +1452,7 @@ static inline void cli(void) asm volatile ("cli"); } -void __vm_xsave_require_permission(uint64_t xfeature, const char *name); +void __vm_xsave_require_permission(u64 xfeature, const char *name); #define vm_xsave_require_permission(xfeature) \ __vm_xsave_require_permission(xfeature, #xfeature) @@ -1511,17 +1507,17 @@ enum pg_level { void tdp_mmu_init(struct kvm_vm *vm, int pgtable_levels, struct pte_masks *pte_masks); -void __virt_pg_map(struct kvm_vm *vm, struct kvm_mmu *mmu, uint64_t vaddr, - uint64_t paddr, int level); -void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, - uint64_t nr_bytes, int level); +void __virt_pg_map(struct kvm_vm *vm, struct kvm_mmu *mmu, gva_t gva, + gpa_t gpa, int level); +void virt_map_level(struct kvm_vm *vm, gva_t gva, gpa_t gpa, + u64 nr_bytes, int level); void vm_enable_tdp(struct kvm_vm *vm); bool kvm_cpu_has_tdp(void); -void tdp_map(struct kvm_vm *vm, uint64_t nested_paddr, uint64_t paddr, uint64_t size); +void tdp_map(struct kvm_vm *vm, gpa_t l2_gpa, gpa_t gpa, u64 size); void tdp_identity_map_default_memslots(struct kvm_vm *vm); -void tdp_identity_map_1g(struct kvm_vm *vm, uint64_t addr, uint64_t size); -uint64_t *tdp_get_pte(struct kvm_vm *vm, uint64_t l2_gpa); +void tdp_identity_map_1g(struct kvm_vm *vm, u64 addr, u64 size); +u64 *tdp_get_pte(struct kvm_vm *vm, u64 l2_gpa); /* * Basic CPU control in CR0 diff --git a/tools/testing/selftests/kvm/include/x86/sev.h b/tools/testing/selftests/kvm/include/x86/sev.h index 008b4169f5e2..1af44c151d60 100644 --- a/tools/testing/selftests/kvm/include/x86/sev.h +++ b/tools/testing/selftests/kvm/include/x86/sev.h @@ -46,16 +46,16 @@ static inline bool is_sev_vm(struct kvm_vm *vm) return is_sev_es_vm(vm) || vm->type == KVM_X86_SEV_VM; } -void sev_vm_launch(struct kvm_vm *vm, uint32_t policy); -void sev_vm_launch_measure(struct kvm_vm *vm, uint8_t *measurement); +void sev_vm_launch(struct kvm_vm *vm, u32 policy); +void sev_vm_launch_measure(struct kvm_vm *vm, u8 *measurement); void sev_vm_launch_finish(struct kvm_vm *vm); -void snp_vm_launch_start(struct kvm_vm *vm, uint64_t policy); +void snp_vm_launch_start(struct kvm_vm *vm, u64 policy); void snp_vm_launch_update(struct kvm_vm *vm); void snp_vm_launch_finish(struct kvm_vm *vm); -struct kvm_vm *vm_sev_create_with_one_vcpu(uint32_t type, void *guest_code, +struct kvm_vm *vm_sev_create_with_one_vcpu(u32 type, void *guest_code, struct kvm_vcpu **cpu); -void vm_sev_launch(struct kvm_vm *vm, uint64_t policy, uint8_t *measurement); +void vm_sev_launch(struct kvm_vm *vm, u64 policy, u8 *measurement); kvm_static_assert(SEV_RET_SUCCESS == 0); @@ -85,7 +85,7 @@ static inline u64 snp_default_policy(void) unsigned long raw; \ } sev_cmd = { .c = { \ .id = (cmd), \ - .data = (uint64_t)(arg), \ + .data = (u64)(arg), \ .sev_fd = (vm)->arch.sev_fd, \ } }; \ \ @@ -120,8 +120,8 @@ static inline void sev_register_encrypted_memory(struct kvm_vm *vm, vm_ioctl(vm, KVM_MEMORY_ENCRYPT_REG_REGION, &range); } -static inline void sev_launch_update_data(struct kvm_vm *vm, vm_paddr_t gpa, - uint64_t size) +static inline void sev_launch_update_data(struct kvm_vm *vm, gpa_t gpa, + u64 size) { struct kvm_sev_launch_update_data update_data = { .uaddr = (unsigned long)addr_gpa2hva(vm, gpa), @@ -131,8 +131,8 @@ static inline void sev_launch_update_data(struct kvm_vm *vm, vm_paddr_t gpa, vm_sev_ioctl(vm, KVM_SEV_LAUNCH_UPDATE_DATA, &update_data); } -static inline void snp_launch_update_data(struct kvm_vm *vm, vm_paddr_t gpa, - uint64_t hva, uint64_t size, uint8_t type) +static inline void snp_launch_update_data(struct kvm_vm *vm, gpa_t gpa, + u64 hva, u64 size, u8 type) { struct kvm_sev_snp_launch_update update_data = { .uaddr = hva, diff --git a/tools/testing/selftests/kvm/include/x86/smm.h b/tools/testing/selftests/kvm/include/x86/smm.h index 19337c34f13e..2d1afa09819b 100644 --- a/tools/testing/selftests/kvm/include/x86/smm.h +++ b/tools/testing/selftests/kvm/include/x86/smm.h @@ -8,8 +8,7 @@ #define SMRAM_MEMSLOT ((1 << 16) | 1) #define SMRAM_PAGES (SMRAM_SIZE / PAGE_SIZE) -void setup_smram(struct kvm_vm *vm, struct kvm_vcpu *vcpu, - uint64_t smram_gpa, +void setup_smram(struct kvm_vm *vm, struct kvm_vcpu *vcpu, u64 smram_gpa, const void *smi_handler, size_t handler_size); void inject_smi(struct kvm_vcpu *vcpu); diff --git a/tools/testing/selftests/kvm/include/x86/svm_util.h b/tools/testing/selftests/kvm/include/x86/svm_util.h index 5d7c42534bc4..6c013eb838be 100644 --- a/tools/testing/selftests/kvm/include/x86/svm_util.h +++ b/tools/testing/selftests/kvm/include/x86/svm_util.h @@ -16,20 +16,20 @@ struct svm_test_data { /* VMCB */ struct vmcb *vmcb; /* gva */ void *vmcb_hva; - uint64_t vmcb_gpa; + u64 vmcb_gpa; /* host state-save area */ struct vmcb_save_area *save_area; /* gva */ void *save_area_hva; - uint64_t save_area_gpa; + u64 save_area_gpa; /* MSR-Bitmap */ void *msr; /* gva */ void *msr_hva; - uint64_t msr_gpa; + u64 msr_gpa; /* NPT */ - uint64_t ncr3_gpa; + u64 ncr3_gpa; }; static inline void vmmcall(void) @@ -56,9 +56,9 @@ static inline void vmmcall(void) "clgi\n" \ ) -struct svm_test_data *vcpu_alloc_svm(struct kvm_vm *vm, vm_vaddr_t *p_svm_gva); +struct svm_test_data *vcpu_alloc_svm(struct kvm_vm *vm, gva_t *p_svm_gva); void generic_svm_setup(struct svm_test_data *svm, void *guest_rip, void *guest_rsp); -void run_guest(struct vmcb *vmcb, uint64_t vmcb_gpa); +void run_guest(struct vmcb *vmcb, u64 vmcb_gpa); static inline bool kvm_cpu_has_npt(void) { diff --git a/tools/testing/selftests/kvm/include/x86/ucall.h b/tools/testing/selftests/kvm/include/x86/ucall.h index d3825dcc3cd9..0e4950041e3e 100644 --- a/tools/testing/selftests/kvm/include/x86/ucall.h +++ b/tools/testing/selftests/kvm/include/x86/ucall.h @@ -6,7 +6,7 @@ #define UCALL_EXIT_REASON KVM_EXIT_IO -static inline void ucall_arch_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa) +static inline void ucall_arch_init(struct kvm_vm *vm, gpa_t mmio_gpa) { } diff --git a/tools/testing/selftests/kvm/include/x86/vmx.h b/tools/testing/selftests/kvm/include/x86/vmx.h index 92b918700d24..90fffaf91595 100644 --- a/tools/testing/selftests/kvm/include/x86/vmx.h +++ b/tools/testing/selftests/kvm/include/x86/vmx.h @@ -285,16 +285,16 @@ enum vmcs_field { }; struct vmx_msr_entry { - uint32_t index; - uint32_t reserved; - uint64_t value; + u32 index; + u32 reserved; + u64 value; } __attribute__ ((aligned(16))); #include "evmcs.h" -static inline int vmxon(uint64_t phys) +static inline int vmxon(u64 phys) { - uint8_t ret; + u8 ret; __asm__ __volatile__ ("vmxon %[pa]; setna %[ret]" : [ret]"=rm"(ret) @@ -309,9 +309,9 @@ static inline void vmxoff(void) __asm__ __volatile__("vmxoff"); } -static inline int vmclear(uint64_t vmcs_pa) +static inline int vmclear(u64 vmcs_pa) { - uint8_t ret; + u8 ret; __asm__ __volatile__ ("vmclear %[pa]; setna %[ret]" : [ret]"=rm"(ret) @@ -321,9 +321,9 @@ static inline int vmclear(uint64_t vmcs_pa) return ret; } -static inline int vmptrld(uint64_t vmcs_pa) +static inline int vmptrld(u64 vmcs_pa) { - uint8_t ret; + u8 ret; if (enable_evmcs) return -1; @@ -336,10 +336,10 @@ static inline int vmptrld(uint64_t vmcs_pa) return ret; } -static inline int vmptrst(uint64_t *value) +static inline int vmptrst(u64 *value) { - uint64_t tmp; - uint8_t ret; + u64 tmp; + u8 ret; if (enable_evmcs) return evmcs_vmptrst(value); @@ -356,9 +356,9 @@ static inline int vmptrst(uint64_t *value) * A wrapper around vmptrst that ignores errors and returns zero if the * vmptrst instruction fails. */ -static inline uint64_t vmptrstz(void) +static inline u64 vmptrstz(void) { - uint64_t value = 0; + u64 value = 0; vmptrst(&value); return value; } @@ -391,8 +391,8 @@ static inline int vmlaunch(void) "pop %%rcx;" "pop %%rbp;" : [ret]"=&a"(ret) - : [host_rsp]"r"((uint64_t)HOST_RSP), - [host_rip]"r"((uint64_t)HOST_RIP) + : [host_rsp]"r"((u64)HOST_RSP), + [host_rip]"r"((u64)HOST_RIP) : "memory", "cc", "rbx", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"); return ret; @@ -426,8 +426,8 @@ static inline int vmresume(void) "pop %%rcx;" "pop %%rbp;" : [ret]"=&a"(ret) - : [host_rsp]"r"((uint64_t)HOST_RSP), - [host_rip]"r"((uint64_t)HOST_RIP) + : [host_rsp]"r"((u64)HOST_RSP), + [host_rip]"r"((u64)HOST_RIP) : "memory", "cc", "rbx", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"); return ret; @@ -447,10 +447,10 @@ static inline void vmcall(void) "r10", "r11", "r12", "r13", "r14", "r15"); } -static inline int vmread(uint64_t encoding, uint64_t *value) +static inline int vmread(u64 encoding, u64 *value) { - uint64_t tmp; - uint8_t ret; + u64 tmp; + u8 ret; if (enable_evmcs) return evmcs_vmread(encoding, value); @@ -468,16 +468,16 @@ static inline int vmread(uint64_t encoding, uint64_t *value) * A wrapper around vmread that ignores errors and returns zero if the * vmread instruction fails. */ -static inline uint64_t vmreadz(uint64_t encoding) +static inline u64 vmreadz(u64 encoding) { - uint64_t value = 0; + u64 value = 0; vmread(encoding, &value); return value; } -static inline int vmwrite(uint64_t encoding, uint64_t value) +static inline int vmwrite(u64 encoding, u64 value) { - uint8_t ret; + u8 ret; if (enable_evmcs) return evmcs_vmwrite(encoding, value); @@ -490,41 +490,41 @@ static inline int vmwrite(uint64_t encoding, uint64_t value) return ret; } -static inline uint32_t vmcs_revision(void) +static inline u32 vmcs_revision(void) { return rdmsr(MSR_IA32_VMX_BASIC); } struct vmx_pages { void *vmxon_hva; - uint64_t vmxon_gpa; + u64 vmxon_gpa; void *vmxon; void *vmcs_hva; - uint64_t vmcs_gpa; + u64 vmcs_gpa; void *vmcs; void *msr_hva; - uint64_t msr_gpa; + u64 msr_gpa; void *msr; void *shadow_vmcs_hva; - uint64_t shadow_vmcs_gpa; + u64 shadow_vmcs_gpa; void *shadow_vmcs; void *vmread_hva; - uint64_t vmread_gpa; + u64 vmread_gpa; void *vmread; void *vmwrite_hva; - uint64_t vmwrite_gpa; + u64 vmwrite_gpa; void *vmwrite; void *apic_access_hva; - uint64_t apic_access_gpa; + u64 apic_access_gpa; void *apic_access; - uint64_t eptp_gpa; + u64 eptp_gpa; }; union vmx_basic { @@ -550,7 +550,7 @@ union vmx_ctrl_msr { }; }; -struct vmx_pages *vcpu_alloc_vmx(struct kvm_vm *vm, vm_vaddr_t *p_vmx_gva); +struct vmx_pages *vcpu_alloc_vmx(struct kvm_vm *vm, gva_t *p_vmx_gva); bool prepare_for_vmx_operation(struct vmx_pages *vmx); void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip, void *guest_rsp); bool load_vmcs(struct vmx_pages *vmx); diff --git a/tools/testing/selftests/kvm/kvm_page_table_test.c b/tools/testing/selftests/kvm/kvm_page_table_test.c index c60a24a92829..fc5242fb956f 100644 --- a/tools/testing/selftests/kvm/kvm_page_table_test.c +++ b/tools/testing/selftests/kvm/kvm_page_table_test.c @@ -46,12 +46,12 @@ static const char * const test_stage_string[] = { struct test_args { struct kvm_vm *vm; - uint64_t guest_test_virt_mem; - uint64_t host_page_size; - uint64_t host_num_pages; - uint64_t large_page_size; - uint64_t large_num_pages; - uint64_t host_pages_per_lpage; + u64 guest_test_virt_mem; + u64 host_page_size; + u64 host_num_pages; + u64 large_page_size; + u64 large_num_pages; + u64 host_pages_per_lpage; enum vm_mem_backing_src_type src_type; struct kvm_vcpu *vcpus[KVM_MAX_VCPUS]; }; @@ -63,7 +63,7 @@ struct test_args { static enum test_stage guest_test_stage; /* Host variables */ -static uint32_t nr_vcpus = 1; +static u32 nr_vcpus = 1; static struct test_args test_args; static enum test_stage *current_stage; static bool host_quit; @@ -77,19 +77,19 @@ static sem_t test_stage_completed; * This will be set to the topmost valid physical address minus * the test memory size. */ -static uint64_t guest_test_phys_mem; +static u64 guest_test_phys_mem; /* * Guest virtual memory offset of the testing memory slot. * Must not conflict with identity mapped test code. */ -static uint64_t guest_test_virt_mem = DEFAULT_GUEST_TEST_MEM; +static u64 guest_test_virt_mem = DEFAULT_GUEST_TEST_MEM; static void guest_code(bool do_write) { struct test_args *p = &test_args; enum test_stage *current_stage = &guest_test_stage; - uint64_t addr; + u64 addr; int i, j; while (true) { @@ -113,9 +113,9 @@ static void guest_code(bool do_write) case KVM_CREATE_MAPPINGS: for (i = 0; i < p->large_num_pages; i++) { if (do_write) - *(uint64_t *)addr = 0x0123456789ABCDEF; + *(u64 *)addr = 0x0123456789ABCDEF; else - READ_ONCE(*(uint64_t *)addr); + READ_ONCE(*(u64 *)addr); addr += p->large_page_size; } @@ -131,7 +131,7 @@ static void guest_code(bool do_write) case KVM_UPDATE_MAPPINGS: if (p->src_type == VM_MEM_SRC_ANONYMOUS) { for (i = 0; i < p->host_num_pages; i++) { - *(uint64_t *)addr = 0x0123456789ABCDEF; + *(u64 *)addr = 0x0123456789ABCDEF; addr += p->host_page_size; } break; @@ -142,7 +142,7 @@ static void guest_code(bool do_write) * Write to the first host page in each large * page region, and triger break of large pages. */ - *(uint64_t *)addr = 0x0123456789ABCDEF; + *(u64 *)addr = 0x0123456789ABCDEF; /* * Access the middle host pages in each large @@ -152,7 +152,7 @@ static void guest_code(bool do_write) */ addr += p->large_page_size / 2; for (j = 0; j < p->host_pages_per_lpage / 2; j++) { - READ_ONCE(*(uint64_t *)addr); + READ_ONCE(*(u64 *)addr); addr += p->host_page_size; } } @@ -167,7 +167,7 @@ static void guest_code(bool do_write) */ case KVM_ADJUST_MAPPINGS: for (i = 0; i < p->host_num_pages; i++) { - READ_ONCE(*(uint64_t *)addr); + READ_ONCE(*(u64 *)addr); addr += p->host_page_size; } break; @@ -227,8 +227,8 @@ static void *vcpu_worker(void *data) } struct test_params { - uint64_t phys_offset; - uint64_t test_mem_size; + u64 phys_offset; + u64 test_mem_size; enum vm_mem_backing_src_type src_type; }; @@ -237,12 +237,12 @@ static struct kvm_vm *pre_init_before_test(enum vm_guest_mode mode, void *arg) int ret; struct test_params *p = arg; enum vm_mem_backing_src_type src_type = p->src_type; - uint64_t large_page_size = get_backing_src_pagesz(src_type); - uint64_t guest_page_size = vm_guest_mode_params[mode].page_size; - uint64_t host_page_size = getpagesize(); - uint64_t test_mem_size = p->test_mem_size; - uint64_t guest_num_pages; - uint64_t alignment; + u64 large_page_size = get_backing_src_pagesz(src_type); + u64 guest_page_size = vm_guest_mode_params[mode].page_size; + u64 host_page_size = getpagesize(); + u64 test_mem_size = p->test_mem_size; + u64 guest_num_pages; + u64 alignment; void *host_test_mem; struct kvm_vm *vm; @@ -281,7 +281,7 @@ static struct kvm_vm *pre_init_before_test(enum vm_guest_mode mode, void *arg) virt_map(vm, guest_test_virt_mem, guest_test_phys_mem, guest_num_pages); /* Cache the HVA pointer of the region */ - host_test_mem = addr_gpa2hva(vm, (vm_paddr_t)guest_test_phys_mem); + host_test_mem = addr_gpa2hva(vm, (gpa_t)guest_test_phys_mem); /* Export shared structure test_args to guest */ sync_global_to_guest(vm, test_args); @@ -292,7 +292,7 @@ static struct kvm_vm *pre_init_before_test(enum vm_guest_mode mode, void *arg) ret = sem_init(&test_stage_completed, 0, 0); TEST_ASSERT(ret == 0, "Error in sem_init"); - current_stage = addr_gva2hva(vm, (vm_vaddr_t)(&guest_test_stage)); + current_stage = addr_gva2hva(vm, (gva_t)(&guest_test_stage)); *current_stage = NUM_TEST_STAGES; pr_info("Testing guest mode: %s\n", vm_guest_mode_string(mode)); @@ -304,7 +304,7 @@ static struct kvm_vm *pre_init_before_test(enum vm_guest_mode mode, void *arg) pr_info("Guest physical test memory offset: 0x%lx\n", guest_test_phys_mem); pr_info("Host virtual test memory offset: 0x%lx\n", - (uint64_t)host_test_mem); + (u64)host_test_mem); pr_info("Number of testing vCPUs: %d\n", nr_vcpus); return vm; diff --git a/tools/testing/selftests/kvm/lib/arm64/gic.c b/tools/testing/selftests/kvm/lib/arm64/gic.c index b023868fe0b8..011dfe1dfcb3 100644 --- a/tools/testing/selftests/kvm/lib/arm64/gic.c +++ b/tools/testing/selftests/kvm/lib/arm64/gic.c @@ -50,7 +50,7 @@ static void gic_dist_init(enum gic_type type, unsigned int nr_cpus) void gic_init(enum gic_type type, unsigned int nr_cpus) { - uint32_t cpu = guest_get_vcpuid(); + u32 cpu = guest_get_vcpuid(); GUEST_ASSERT(type < GIC_TYPE_MAX); GUEST_ASSERT(nr_cpus); @@ -73,7 +73,7 @@ void gic_irq_disable(unsigned int intid) unsigned int gic_get_and_ack_irq(void) { - uint64_t irqstat; + u64 irqstat; unsigned int intid; GUEST_ASSERT(gic_common_ops); @@ -102,7 +102,7 @@ void gic_set_eoi_split(bool split) gic_common_ops->gic_set_eoi_split(split); } -void gic_set_priority_mask(uint64_t pmr) +void gic_set_priority_mask(u64 pmr) { GUEST_ASSERT(gic_common_ops); gic_common_ops->gic_set_priority_mask(pmr); diff --git a/tools/testing/selftests/kvm/lib/arm64/gic_private.h b/tools/testing/selftests/kvm/lib/arm64/gic_private.h index b6a7e30c3eb1..6d393f5c5685 100644 --- a/tools/testing/selftests/kvm/lib/arm64/gic_private.h +++ b/tools/testing/selftests/kvm/lib/arm64/gic_private.h @@ -12,20 +12,20 @@ struct gic_common_ops { void (*gic_cpu_init)(unsigned int cpu); void (*gic_irq_enable)(unsigned int intid); void (*gic_irq_disable)(unsigned int intid); - uint64_t (*gic_read_iar)(void); - void (*gic_write_eoir)(uint32_t irq); - void (*gic_write_dir)(uint32_t irq); + u64 (*gic_read_iar)(void); + void (*gic_write_eoir)(u32 irq); + void (*gic_write_dir)(u32 irq); void (*gic_set_eoi_split)(bool split); - void (*gic_set_priority_mask)(uint64_t mask); - void (*gic_set_priority)(uint32_t intid, uint32_t prio); - void (*gic_irq_set_active)(uint32_t intid); - void (*gic_irq_clear_active)(uint32_t intid); - bool (*gic_irq_get_active)(uint32_t intid); - void (*gic_irq_set_pending)(uint32_t intid); - void (*gic_irq_clear_pending)(uint32_t intid); - bool (*gic_irq_get_pending)(uint32_t intid); - void (*gic_irq_set_config)(uint32_t intid, bool is_edge); - void (*gic_irq_set_group)(uint32_t intid, bool group); + void (*gic_set_priority_mask)(u64 mask); + void (*gic_set_priority)(u32 intid, u32 prio); + void (*gic_irq_set_active)(u32 intid); + void (*gic_irq_clear_active)(u32 intid); + bool (*gic_irq_get_active)(u32 intid); + void (*gic_irq_set_pending)(u32 intid); + void (*gic_irq_clear_pending)(u32 intid); + bool (*gic_irq_get_pending)(u32 intid); + void (*gic_irq_set_config)(u32 intid, bool is_edge); + void (*gic_irq_set_group)(u32 intid, bool group); }; extern const struct gic_common_ops gicv3_ops; diff --git a/tools/testing/selftests/kvm/lib/arm64/gic_v3.c b/tools/testing/selftests/kvm/lib/arm64/gic_v3.c index 50754a27f493..a99a53accfe9 100644 --- a/tools/testing/selftests/kvm/lib/arm64/gic_v3.c +++ b/tools/testing/selftests/kvm/lib/arm64/gic_v3.c @@ -50,13 +50,13 @@ static void gicv3_gicd_wait_for_rwp(void) } } -static inline volatile void *gicr_base_cpu(uint32_t cpu) +static inline volatile void *gicr_base_cpu(u32 cpu) { /* Align all the redistributors sequentially */ return GICR_BASE_GVA + cpu * SZ_64K * 2; } -static void gicv3_gicr_wait_for_rwp(uint32_t cpu) +static void gicv3_gicr_wait_for_rwp(u32 cpu) { unsigned int count = 100000; /* 1s */ @@ -66,7 +66,7 @@ static void gicv3_gicr_wait_for_rwp(uint32_t cpu) } } -static void gicv3_wait_for_rwp(uint32_t cpu_or_dist) +static void gicv3_wait_for_rwp(u32 cpu_or_dist) { if (cpu_or_dist & DIST_BIT) gicv3_gicd_wait_for_rwp(); @@ -91,34 +91,34 @@ static enum gicv3_intid_range get_intid_range(unsigned int intid) return INVALID_RANGE; } -static uint64_t gicv3_read_iar(void) +static u64 gicv3_read_iar(void) { - uint64_t irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1); + u64 irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1); dsb(sy); return irqstat; } -static void gicv3_write_eoir(uint32_t irq) +static void gicv3_write_eoir(u32 irq) { write_sysreg_s(irq, SYS_ICC_EOIR1_EL1); isb(); } -static void gicv3_write_dir(uint32_t irq) +static void gicv3_write_dir(u32 irq) { write_sysreg_s(irq, SYS_ICC_DIR_EL1); isb(); } -static void gicv3_set_priority_mask(uint64_t mask) +static void gicv3_set_priority_mask(u64 mask) { write_sysreg_s(mask, SYS_ICC_PMR_EL1); } static void gicv3_set_eoi_split(bool split) { - uint32_t val; + u32 val; /* * All other fields are read-only, so no need to read CTLR first. In @@ -129,29 +129,29 @@ static void gicv3_set_eoi_split(bool split) isb(); } -uint32_t gicv3_reg_readl(uint32_t cpu_or_dist, uint64_t offset) +u32 gicv3_reg_readl(u32 cpu_or_dist, u64 offset) { volatile void *base = cpu_or_dist & DIST_BIT ? GICD_BASE_GVA : sgi_base_from_redist(gicr_base_cpu(cpu_or_dist)); return readl(base + offset); } -void gicv3_reg_writel(uint32_t cpu_or_dist, uint64_t offset, uint32_t reg_val) +void gicv3_reg_writel(u32 cpu_or_dist, u64 offset, u32 reg_val) { volatile void *base = cpu_or_dist & DIST_BIT ? GICD_BASE_GVA : sgi_base_from_redist(gicr_base_cpu(cpu_or_dist)); writel(reg_val, base + offset); } -uint32_t gicv3_getl_fields(uint32_t cpu_or_dist, uint64_t offset, uint32_t mask) +u32 gicv3_getl_fields(u32 cpu_or_dist, u64 offset, u32 mask) { return gicv3_reg_readl(cpu_or_dist, offset) & mask; } -void gicv3_setl_fields(uint32_t cpu_or_dist, uint64_t offset, - uint32_t mask, uint32_t reg_val) +void gicv3_setl_fields(u32 cpu_or_dist, u64 offset, + u32 mask, u32 reg_val) { - uint32_t tmp = gicv3_reg_readl(cpu_or_dist, offset) & ~mask; + u32 tmp = gicv3_reg_readl(cpu_or_dist, offset) & ~mask; tmp |= (reg_val & mask); gicv3_reg_writel(cpu_or_dist, offset, tmp); @@ -165,14 +165,14 @@ void gicv3_setl_fields(uint32_t cpu_or_dist, uint64_t offset, * map that doesn't implement it; like GICR_WAKER's offset of 0x0014 being * marked as "Reserved" in the Distributor map. */ -static void gicv3_access_reg(uint32_t intid, uint64_t offset, - uint32_t reg_bits, uint32_t bits_per_field, - bool write, uint32_t *val) +static void gicv3_access_reg(u32 intid, u64 offset, + u32 reg_bits, u32 bits_per_field, + bool write, u32 *val) { - uint32_t cpu = guest_get_vcpuid(); + u32 cpu = guest_get_vcpuid(); enum gicv3_intid_range intid_range = get_intid_range(intid); - uint32_t fields_per_reg, index, mask, shift; - uint32_t cpu_or_dist; + u32 fields_per_reg, index, mask, shift; + u32 cpu_or_dist; GUEST_ASSERT(bits_per_field <= reg_bits); GUEST_ASSERT(!write || *val < (1U << bits_per_field)); @@ -197,32 +197,32 @@ static void gicv3_access_reg(uint32_t intid, uint64_t offset, *val = gicv3_getl_fields(cpu_or_dist, offset, mask) >> shift; } -static void gicv3_write_reg(uint32_t intid, uint64_t offset, - uint32_t reg_bits, uint32_t bits_per_field, uint32_t val) +static void gicv3_write_reg(u32 intid, u64 offset, + u32 reg_bits, u32 bits_per_field, u32 val) { gicv3_access_reg(intid, offset, reg_bits, bits_per_field, true, &val); } -static uint32_t gicv3_read_reg(uint32_t intid, uint64_t offset, - uint32_t reg_bits, uint32_t bits_per_field) +static u32 gicv3_read_reg(u32 intid, u64 offset, + u32 reg_bits, u32 bits_per_field) { - uint32_t val; + u32 val; gicv3_access_reg(intid, offset, reg_bits, bits_per_field, false, &val); return val; } -static void gicv3_set_priority(uint32_t intid, uint32_t prio) +static void gicv3_set_priority(u32 intid, u32 prio) { gicv3_write_reg(intid, GICD_IPRIORITYR, 32, 8, prio); } /* Sets the intid to be level-sensitive or edge-triggered. */ -static void gicv3_irq_set_config(uint32_t intid, bool is_edge) +static void gicv3_irq_set_config(u32 intid, bool is_edge) { - uint32_t val; + u32 val; /* N/A for private interrupts. */ GUEST_ASSERT(get_intid_range(intid) == SPI_RANGE); @@ -230,57 +230,57 @@ static void gicv3_irq_set_config(uint32_t intid, bool is_edge) gicv3_write_reg(intid, GICD_ICFGR, 32, 2, val); } -static void gicv3_irq_enable(uint32_t intid) +static void gicv3_irq_enable(u32 intid) { bool is_spi = get_intid_range(intid) == SPI_RANGE; - uint32_t cpu = guest_get_vcpuid(); + u32 cpu = guest_get_vcpuid(); gicv3_write_reg(intid, GICD_ISENABLER, 32, 1, 1); gicv3_wait_for_rwp(is_spi ? DIST_BIT : cpu); } -static void gicv3_irq_disable(uint32_t intid) +static void gicv3_irq_disable(u32 intid) { bool is_spi = get_intid_range(intid) == SPI_RANGE; - uint32_t cpu = guest_get_vcpuid(); + u32 cpu = guest_get_vcpuid(); gicv3_write_reg(intid, GICD_ICENABLER, 32, 1, 1); gicv3_wait_for_rwp(is_spi ? DIST_BIT : cpu); } -static void gicv3_irq_set_active(uint32_t intid) +static void gicv3_irq_set_active(u32 intid) { gicv3_write_reg(intid, GICD_ISACTIVER, 32, 1, 1); } -static void gicv3_irq_clear_active(uint32_t intid) +static void gicv3_irq_clear_active(u32 intid) { gicv3_write_reg(intid, GICD_ICACTIVER, 32, 1, 1); } -static bool gicv3_irq_get_active(uint32_t intid) +static bool gicv3_irq_get_active(u32 intid) { return gicv3_read_reg(intid, GICD_ISACTIVER, 32, 1); } -static void gicv3_irq_set_pending(uint32_t intid) +static void gicv3_irq_set_pending(u32 intid) { gicv3_write_reg(intid, GICD_ISPENDR, 32, 1, 1); } -static void gicv3_irq_clear_pending(uint32_t intid) +static void gicv3_irq_clear_pending(u32 intid) { gicv3_write_reg(intid, GICD_ICPENDR, 32, 1, 1); } -static bool gicv3_irq_get_pending(uint32_t intid) +static bool gicv3_irq_get_pending(u32 intid) { return gicv3_read_reg(intid, GICD_ISPENDR, 32, 1); } static void gicv3_enable_redist(volatile void *redist_base) { - uint32_t val = readl(redist_base + GICR_WAKER); + u32 val = readl(redist_base + GICR_WAKER); unsigned int count = 100000; /* 1s */ val &= ~GICR_WAKER_ProcessorSleep; @@ -293,10 +293,10 @@ static void gicv3_enable_redist(volatile void *redist_base) } } -static void gicv3_set_group(uint32_t intid, bool grp) +static void gicv3_set_group(u32 intid, bool grp) { - uint32_t cpu_or_dist; - uint32_t val; + u32 cpu_or_dist; + u32 val; cpu_or_dist = (get_intid_range(intid) == SPI_RANGE) ? DIST_BIT : guest_get_vcpuid(); val = gicv3_reg_readl(cpu_or_dist, GICD_IGROUPR + (intid / 32) * 4); @@ -424,8 +424,8 @@ const struct gic_common_ops gicv3_ops = { .gic_irq_set_group = gicv3_set_group, }; -void gic_rdist_enable_lpis(vm_paddr_t cfg_table, size_t cfg_table_size, - vm_paddr_t pend_table) +void gic_rdist_enable_lpis(gpa_t cfg_table, size_t cfg_table_size, + gpa_t pend_table) { volatile void *rdist_base = gicr_base_cpu(guest_get_vcpuid()); diff --git a/tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c b/tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c index 7f9fdcf42ae6..1188b578121d 100644 --- a/tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c +++ b/tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c @@ -54,7 +54,7 @@ static unsigned long its_find_baser(unsigned int type) return -1; } -static void its_install_table(unsigned int type, vm_paddr_t base, size_t size) +static void its_install_table(unsigned int type, gpa_t base, size_t size) { unsigned long offset = its_find_baser(type); u64 baser; @@ -69,7 +69,7 @@ static void its_install_table(unsigned int type, vm_paddr_t base, size_t size) its_write_u64(offset, baser); } -static void its_install_cmdq(vm_paddr_t base, size_t size) +static void its_install_cmdq(gpa_t base, size_t size) { u64 cbaser; @@ -82,9 +82,8 @@ static void its_install_cmdq(vm_paddr_t base, size_t size) its_write_u64(GITS_CBASER, cbaser); } -void its_init(vm_paddr_t coll_tbl, size_t coll_tbl_sz, - vm_paddr_t device_tbl, size_t device_tbl_sz, - vm_paddr_t cmdq, size_t cmdq_size) +void its_init(gpa_t coll_tbl, size_t coll_tbl_sz, gpa_t device_tbl, + size_t device_tbl_sz, gpa_t cmdq, size_t cmdq_size) { u32 ctlr; @@ -204,7 +203,7 @@ static void its_send_cmd(void *cmdq_base, struct its_cmd_block *cmd) } } -void its_send_mapd_cmd(void *cmdq_base, u32 device_id, vm_paddr_t itt_base, +void its_send_mapd_cmd(void *cmdq_base, u32 device_id, gpa_t itt_base, size_t itt_size, bool valid) { struct its_cmd_block cmd = {}; diff --git a/tools/testing/selftests/kvm/lib/arm64/processor.c b/tools/testing/selftests/kvm/lib/arm64/processor.c index 43ea40edc533..01325bf4d36f 100644 --- a/tools/testing/selftests/kvm/lib/arm64/processor.c +++ b/tools/testing/selftests/kvm/lib/arm64/processor.c @@ -19,20 +19,20 @@ #define DEFAULT_ARM64_GUEST_STACK_VADDR_MIN 0xac0000 -static vm_vaddr_t exception_handlers; +static gva_t exception_handlers; -static uint64_t pgd_index(struct kvm_vm *vm, vm_vaddr_t gva) +static u64 pgd_index(struct kvm_vm *vm, gva_t gva) { unsigned int shift = (vm->mmu.pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift; - uint64_t mask = (1UL << (vm->va_bits - shift)) - 1; + u64 mask = (1UL << (vm->va_bits - shift)) - 1; return (gva >> shift) & mask; } -static uint64_t pud_index(struct kvm_vm *vm, vm_vaddr_t gva) +static u64 pud_index(struct kvm_vm *vm, gva_t gva) { unsigned int shift = 2 * (vm->page_shift - 3) + vm->page_shift; - uint64_t mask = (1UL << (vm->page_shift - 3)) - 1; + u64 mask = (1UL << (vm->page_shift - 3)) - 1; TEST_ASSERT(vm->mmu.pgtable_levels == 4, "Mode %d does not have 4 page table levels", vm->mode); @@ -40,10 +40,10 @@ static uint64_t pud_index(struct kvm_vm *vm, vm_vaddr_t gva) return (gva >> shift) & mask; } -static uint64_t pmd_index(struct kvm_vm *vm, vm_vaddr_t gva) +static u64 pmd_index(struct kvm_vm *vm, gva_t gva) { unsigned int shift = (vm->page_shift - 3) + vm->page_shift; - uint64_t mask = (1UL << (vm->page_shift - 3)) - 1; + u64 mask = (1UL << (vm->page_shift - 3)) - 1; TEST_ASSERT(vm->mmu.pgtable_levels >= 3, "Mode %d does not have >= 3 page table levels", vm->mode); @@ -51,9 +51,9 @@ static uint64_t pmd_index(struct kvm_vm *vm, vm_vaddr_t gva) return (gva >> shift) & mask; } -static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva) +static u64 pte_index(struct kvm_vm *vm, gva_t gva) { - uint64_t mask = (1UL << (vm->page_shift - 3)) - 1; + u64 mask = (1UL << (vm->page_shift - 3)) - 1; return (gva >> vm->page_shift) & mask; } @@ -63,9 +63,9 @@ static inline bool use_lpa2_pte_format(struct kvm_vm *vm) (vm->pa_bits > 48 || vm->va_bits > 48); } -static uint64_t addr_pte(struct kvm_vm *vm, uint64_t pa, uint64_t attrs) +static u64 addr_pte(struct kvm_vm *vm, u64 pa, u64 attrs) { - uint64_t pte; + u64 pte; if (use_lpa2_pte_format(vm)) { pte = pa & PTE_ADDR_MASK_LPA2(vm->page_shift); @@ -81,9 +81,9 @@ static uint64_t addr_pte(struct kvm_vm *vm, uint64_t pa, uint64_t attrs) return pte; } -static uint64_t pte_addr(struct kvm_vm *vm, uint64_t pte) +static u64 pte_addr(struct kvm_vm *vm, u64 pte) { - uint64_t pa; + u64 pa; if (use_lpa2_pte_format(vm)) { pa = pte & PTE_ADDR_MASK_LPA2(vm->page_shift); @@ -97,13 +97,13 @@ static uint64_t pte_addr(struct kvm_vm *vm, uint64_t pte) return pa; } -static uint64_t ptrs_per_pgd(struct kvm_vm *vm) +static u64 ptrs_per_pgd(struct kvm_vm *vm) { unsigned int shift = (vm->mmu.pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift; return 1 << (vm->va_bits - shift); } -static uint64_t __maybe_unused ptrs_per_pte(struct kvm_vm *vm) +static u64 __maybe_unused ptrs_per_pte(struct kvm_vm *vm) { return 1 << (vm->page_shift - 3); } @@ -121,47 +121,46 @@ void virt_arch_pgd_alloc(struct kvm_vm *vm) vm->mmu.pgd_created = true; } -static void _virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, - uint64_t flags) +static void _virt_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa, + u64 flags) { - uint8_t attr_idx = flags & (PTE_ATTRINDX_MASK >> PTE_ATTRINDX_SHIFT); - uint64_t pg_attr; - uint64_t *ptep; + u8 attr_idx = flags & (PTE_ATTRINDX_MASK >> PTE_ATTRINDX_SHIFT); + u64 pg_attr; + u64 *ptep; - TEST_ASSERT((vaddr % vm->page_size) == 0, + TEST_ASSERT((gva % vm->page_size) == 0, "Virtual address not on page boundary,\n" - " vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size); - TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, - (vaddr >> vm->page_shift)), - "Invalid virtual address, vaddr: 0x%lx", vaddr); - TEST_ASSERT((paddr % vm->page_size) == 0, - "Physical address not on page boundary,\n" - " paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size); - TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn, - "Physical address beyond beyond maximum supported,\n" - " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", - paddr, vm->max_gfn, vm->page_size); + " gva: 0x%lx vm->page_size: 0x%x", gva, vm->page_size); + TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)), + "Invalid virtual address, gva: 0x%lx", gva); + TEST_ASSERT((gpa % vm->page_size) == 0, + "Physical address not on page boundary,\n" + " gpa: 0x%lx vm->page_size: 0x%x", gpa, vm->page_size); + TEST_ASSERT((gpa >> vm->page_shift) <= vm->max_gfn, + "Physical address beyond beyond maximum supported,\n" + " gpa: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", + gpa, vm->max_gfn, vm->page_size); - ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pgd_index(vm, vaddr) * 8; + ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pgd_index(vm, gva) * 8; if (!*ptep) *ptep = addr_pte(vm, vm_alloc_page_table(vm), PGD_TYPE_TABLE | PTE_VALID); switch (vm->mmu.pgtable_levels) { case 4: - ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, vaddr) * 8; + ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, gva) * 8; if (!*ptep) *ptep = addr_pte(vm, vm_alloc_page_table(vm), PUD_TYPE_TABLE | PTE_VALID); /* fall through */ case 3: - ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, vaddr) * 8; + ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, gva) * 8; if (!*ptep) *ptep = addr_pte(vm, vm_alloc_page_table(vm), PMD_TYPE_TABLE | PTE_VALID); /* fall through */ case 2: - ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, vaddr) * 8; + ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, gva) * 8; break; default: TEST_FAIL("Page table levels must be 2, 3, or 4"); @@ -171,19 +170,19 @@ static void _virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, if (!use_lpa2_pte_format(vm)) pg_attr |= PTE_SHARED; - *ptep = addr_pte(vm, paddr, pg_attr); + *ptep = addr_pte(vm, gpa, pg_attr); } -void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr) +void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa) { - uint64_t attr_idx = MT_NORMAL; + u64 attr_idx = MT_NORMAL; - _virt_pg_map(vm, vaddr, paddr, attr_idx); + _virt_pg_map(vm, gva, gpa, attr_idx); } -uint64_t *virt_get_pte_hva_at_level(struct kvm_vm *vm, vm_vaddr_t gva, int level) +u64 *virt_get_pte_hva_at_level(struct kvm_vm *vm, gva_t gva, int level) { - uint64_t *ptep; + u64 *ptep; if (!vm->mmu.pgd_created) goto unmapped_gva; @@ -225,23 +224,23 @@ uint64_t *virt_get_pte_hva_at_level(struct kvm_vm *vm, vm_vaddr_t gva, int level exit(EXIT_FAILURE); } -uint64_t *virt_get_pte_hva(struct kvm_vm *vm, vm_vaddr_t gva) +u64 *virt_get_pte_hva(struct kvm_vm *vm, gva_t gva) { return virt_get_pte_hva_at_level(vm, gva, 3); } -vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) +gpa_t addr_arch_gva2gpa(struct kvm_vm *vm, gva_t gva) { - uint64_t *ptep = virt_get_pte_hva(vm, gva); + u64 *ptep = virt_get_pte_hva(vm, gva); return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1)); } -static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, uint64_t page, int level) +static void pte_dump(FILE *stream, struct kvm_vm *vm, u8 indent, u64 page, int level) { #ifdef DEBUG static const char * const type[] = { "", "pud", "pmd", "pte" }; - uint64_t pte, *ptep; + u64 pte, *ptep; if (level == 4) return; @@ -256,10 +255,10 @@ static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, uint64_t p #endif } -void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) +void virt_arch_dump(FILE *stream, struct kvm_vm *vm, u8 indent) { int level = 4 - (vm->mmu.pgtable_levels - 1); - uint64_t pgd, *ptep; + u64 pgd, *ptep; if (!vm->mmu.pgd_created) return; @@ -298,7 +297,7 @@ void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init) { struct kvm_vcpu_init default_init = { .target = -1, }; struct kvm_vm *vm = vcpu->vm; - uint64_t sctlr_el1, tcr_el1, ttbr0_el1; + u64 sctlr_el1, tcr_el1, ttbr0_el1; if (!init) { kvm_get_default_vcpu_target(vm, &default_init); @@ -397,9 +396,9 @@ void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init) HCR_EL2_RW | HCR_EL2_TGE | HCR_EL2_E2H); } -void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent) +void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, u8 indent) { - uint64_t pstate, pc; + u64 pstate, pc; pstate = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate)); pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc)); @@ -410,29 +409,29 @@ void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent) void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code) { - vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), (uint64_t)guest_code); + vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), (u64)guest_code); } -static struct kvm_vcpu *__aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, +static struct kvm_vcpu *__aarch64_vcpu_add(struct kvm_vm *vm, u32 vcpu_id, struct kvm_vcpu_init *init) { size_t stack_size; - uint64_t stack_vaddr; + gva_t stack_gva; struct kvm_vcpu *vcpu = __vm_vcpu_add(vm, vcpu_id); stack_size = vm->page_size == 4096 ? DEFAULT_STACK_PGS * vm->page_size : vm->page_size; - stack_vaddr = __vm_vaddr_alloc(vm, stack_size, - DEFAULT_ARM64_GUEST_STACK_VADDR_MIN, - MEM_REGION_DATA); + stack_gva = __vm_alloc(vm, stack_size, + DEFAULT_ARM64_GUEST_STACK_VADDR_MIN, + MEM_REGION_DATA); aarch64_vcpu_setup(vcpu, init); - vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SP_EL1), stack_vaddr + stack_size); + vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SP_EL1), stack_gva + stack_size); return vcpu; } -struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, +struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, u32 vcpu_id, struct kvm_vcpu_init *init, void *guest_code) { struct kvm_vcpu *vcpu = __aarch64_vcpu_add(vm, vcpu_id, init); @@ -442,7 +441,7 @@ struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, return vcpu; } -struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) +struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u32 vcpu_id) { return __aarch64_vcpu_add(vm, vcpu_id, NULL); } @@ -459,13 +458,13 @@ void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...) for (i = 0; i < num; i++) { vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.regs[i]), - va_arg(ap, uint64_t)); + va_arg(ap, u64)); } va_end(ap); } -void kvm_exit_unexpected_exception(int vector, uint64_t ec, bool valid_ec) +void kvm_exit_unexpected_exception(int vector, u64 ec, bool valid_ec) { ucall(UCALL_UNHANDLED, 3, vector, ec, valid_ec); while (1) @@ -498,7 +497,7 @@ void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu) { extern char vectors; - vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_VBAR_EL1), (uint64_t)&vectors); + vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_VBAR_EL1), (u64)&vectors); } void route_exception(struct ex_regs *regs, int vector) @@ -536,10 +535,10 @@ void route_exception(struct ex_regs *regs, int vector) void vm_init_descriptor_tables(struct kvm_vm *vm) { - vm->handlers = __vm_vaddr_alloc(vm, sizeof(struct handlers), - vm->page_size, MEM_REGION_DATA); + vm->handlers = __vm_alloc(vm, sizeof(struct handlers), vm->page_size, + MEM_REGION_DATA); - *(vm_vaddr_t *)addr_gva2hva(vm, (vm_vaddr_t)(&exception_handlers)) = vm->handlers; + *(gva_t *)addr_gva2hva(vm, (gva_t)(&exception_handlers)) = vm->handlers; } void vm_install_sync_handler(struct kvm_vm *vm, int vector, int ec, @@ -563,13 +562,13 @@ void vm_install_exception_handler(struct kvm_vm *vm, int vector, handlers->exception_handlers[vector][0] = handler; } -uint32_t guest_get_vcpuid(void) +u32 guest_get_vcpuid(void) { return read_sysreg(tpidr_el1); } -static uint32_t max_ipa_for_page_size(uint32_t vm_ipa, uint32_t gran, - uint32_t not_sup_val, uint32_t ipa52_min_val) +static u32 max_ipa_for_page_size(u32 vm_ipa, u32 gran, + u32 not_sup_val, u32 ipa52_min_val) { if (gran == not_sup_val) return 0; @@ -579,16 +578,16 @@ static uint32_t max_ipa_for_page_size(uint32_t vm_ipa, uint32_t gran, return min(vm_ipa, 48U); } -void aarch64_get_supported_page_sizes(uint32_t ipa, uint32_t *ipa4k, - uint32_t *ipa16k, uint32_t *ipa64k) +void aarch64_get_supported_page_sizes(u32 ipa, u32 *ipa4k, + u32 *ipa16k, u32 *ipa64k) { struct kvm_vcpu_init preferred_init; int kvm_fd, vm_fd, vcpu_fd, err; - uint64_t val; - uint32_t gran; + u64 val; + u32 gran; struct kvm_one_reg reg = { .id = KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR0_EL1), - .addr = (uint64_t)&val, + .addr = (u64)&val, }; kvm_fd = open_kvm_dev_path_or_exit(); @@ -646,17 +645,17 @@ void aarch64_get_supported_page_sizes(uint32_t ipa, uint32_t *ipa4k, : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7") -void smccc_hvc(uint32_t function_id, uint64_t arg0, uint64_t arg1, - uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, - uint64_t arg6, struct arm_smccc_res *res) +void smccc_hvc(u32 function_id, u64 arg0, u64 arg1, + u64 arg2, u64 arg3, u64 arg4, u64 arg5, + u64 arg6, struct arm_smccc_res *res) { __smccc_call(hvc, function_id, arg0, arg1, arg2, arg3, arg4, arg5, arg6, res); } -void smccc_smc(uint32_t function_id, uint64_t arg0, uint64_t arg1, - uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, - uint64_t arg6, struct arm_smccc_res *res) +void smccc_smc(u32 function_id, u64 arg0, u64 arg1, + u64 arg2, u64 arg3, u64 arg4, u64 arg5, + u64 arg6, struct arm_smccc_res *res) { __smccc_call(smc, function_id, arg0, arg1, arg2, arg3, arg4, arg5, arg6, res); @@ -671,7 +670,7 @@ void kvm_selftest_arch_init(void) guest_modes_append_default(); } -void vm_vaddr_populate_bitmap(struct kvm_vm *vm) +void vm_populate_gva_bitmap(struct kvm_vm *vm) { /* * arm64 selftests use only TTBR0_EL1, meaning that the valid VA space diff --git a/tools/testing/selftests/kvm/lib/arm64/ucall.c b/tools/testing/selftests/kvm/lib/arm64/ucall.c index ddab0ce89d4d..e0550ad5aa75 100644 --- a/tools/testing/selftests/kvm/lib/arm64/ucall.c +++ b/tools/testing/selftests/kvm/lib/arm64/ucall.c @@ -6,17 +6,17 @@ */ #include "kvm_util.h" -vm_vaddr_t *ucall_exit_mmio_addr; +gva_t *ucall_exit_mmio_addr; -void ucall_arch_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa) +void ucall_arch_init(struct kvm_vm *vm, gpa_t mmio_gpa) { - vm_vaddr_t mmio_gva = vm_vaddr_unused_gap(vm, vm->page_size, KVM_UTIL_MIN_VADDR); + gva_t mmio_gva = vm_unused_gva_gap(vm, vm->page_size, KVM_UTIL_MIN_VADDR); virt_map(vm, mmio_gva, mmio_gpa, 1); vm->ucall_mmio_addr = mmio_gpa; - write_guest_global(vm, ucall_exit_mmio_addr, (vm_vaddr_t *)mmio_gva); + write_guest_global(vm, ucall_exit_mmio_addr, (gva_t *)mmio_gva); } void *ucall_arch_get_ucall(struct kvm_vcpu *vcpu) @@ -25,9 +25,9 @@ void *ucall_arch_get_ucall(struct kvm_vcpu *vcpu) if (run->exit_reason == KVM_EXIT_MMIO && run->mmio.phys_addr == vcpu->vm->ucall_mmio_addr) { - TEST_ASSERT(run->mmio.is_write && run->mmio.len == sizeof(uint64_t), + TEST_ASSERT(run->mmio.is_write && run->mmio.len == sizeof(u64), "Unexpected ucall exit mmio address access"); - return (void *)(*((uint64_t *)run->mmio.data)); + return (void *)(*((u64 *)run->mmio.data)); } return NULL; diff --git a/tools/testing/selftests/kvm/lib/arm64/vgic.c b/tools/testing/selftests/kvm/lib/arm64/vgic.c index d0f7bd0984b8..4ecebf3146a2 100644 --- a/tools/testing/selftests/kvm/lib/arm64/vgic.c +++ b/tools/testing/selftests/kvm/lib/arm64/vgic.c @@ -41,10 +41,10 @@ bool kvm_supports_vgic_v3(void) * redistributor regions of the guest. Since it depends on the number of * vCPUs for the VM, it must be called after all the vCPUs have been created. */ -int __vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, uint32_t nr_irqs) +int __vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, u32 nr_irqs) { int gic_fd; - uint64_t attr; + u64 attr; unsigned int nr_gic_pages; /* Distributor setup */ @@ -77,7 +77,7 @@ void __vgic_v3_init(int fd) KVM_DEV_ARM_VGIC_CTRL_INIT, NULL); } -int vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, uint32_t nr_irqs) +int vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, u32 nr_irqs) { unsigned int nr_vcpus_created = 0; struct list_head *iter; @@ -104,11 +104,11 @@ int vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, uint32_t nr_irqs) } /* should only work for level sensitive interrupts */ -int _kvm_irq_set_level_info(int gic_fd, uint32_t intid, int level) +int _kvm_irq_set_level_info(int gic_fd, u32 intid, int level) { - uint64_t attr = 32 * (intid / 32); - uint64_t index = intid % 32; - uint64_t val; + u64 attr = 32 * (intid / 32); + u64 index = intid % 32; + u64 val; int ret; ret = __kvm_device_attr_get(gic_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO, @@ -122,16 +122,16 @@ int _kvm_irq_set_level_info(int gic_fd, uint32_t intid, int level) return ret; } -void kvm_irq_set_level_info(int gic_fd, uint32_t intid, int level) +void kvm_irq_set_level_info(int gic_fd, u32 intid, int level) { int ret = _kvm_irq_set_level_info(gic_fd, intid, level); TEST_ASSERT(!ret, KVM_IOCTL_ERROR(KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO, ret)); } -int _kvm_arm_irq_line(struct kvm_vm *vm, uint32_t intid, int level) +int _kvm_arm_irq_line(struct kvm_vm *vm, u32 intid, int level) { - uint32_t irq = intid & KVM_ARM_IRQ_NUM_MASK; + u32 irq = intid & KVM_ARM_IRQ_NUM_MASK; TEST_ASSERT(!INTID_IS_SGI(intid), "KVM_IRQ_LINE's interface itself " "doesn't allow injecting SGIs. There's no mask for it."); @@ -144,23 +144,23 @@ int _kvm_arm_irq_line(struct kvm_vm *vm, uint32_t intid, int level) return _kvm_irq_line(vm, irq, level); } -void kvm_arm_irq_line(struct kvm_vm *vm, uint32_t intid, int level) +void kvm_arm_irq_line(struct kvm_vm *vm, u32 intid, int level) { int ret = _kvm_arm_irq_line(vm, intid, level); TEST_ASSERT(!ret, KVM_IOCTL_ERROR(KVM_IRQ_LINE, ret)); } -static void vgic_poke_irq(int gic_fd, uint32_t intid, struct kvm_vcpu *vcpu, - uint64_t reg_off) +static void vgic_poke_irq(int gic_fd, u32 intid, struct kvm_vcpu *vcpu, + u64 reg_off) { - uint64_t reg = intid / 32; - uint64_t index = intid % 32; - uint64_t attr = reg_off + reg * 4; - uint64_t val; + u64 reg = intid / 32; + u64 index = intid % 32; + u64 attr = reg_off + reg * 4; + u64 val; bool intid_is_private = INTID_IS_SGI(intid) || INTID_IS_PPI(intid); - uint32_t group = intid_is_private ? KVM_DEV_ARM_VGIC_GRP_REDIST_REGS + u32 group = intid_is_private ? KVM_DEV_ARM_VGIC_GRP_REDIST_REGS : KVM_DEV_ARM_VGIC_GRP_DIST_REGS; if (intid_is_private) { @@ -183,12 +183,12 @@ static void vgic_poke_irq(int gic_fd, uint32_t intid, struct kvm_vcpu *vcpu, kvm_device_attr_set(gic_fd, group, attr, &val); } -void kvm_irq_write_ispendr(int gic_fd, uint32_t intid, struct kvm_vcpu *vcpu) +void kvm_irq_write_ispendr(int gic_fd, u32 intid, struct kvm_vcpu *vcpu) { vgic_poke_irq(gic_fd, intid, vcpu, GICD_ISPENDR); } -void kvm_irq_write_isactiver(int gic_fd, uint32_t intid, struct kvm_vcpu *vcpu) +void kvm_irq_write_isactiver(int gic_fd, u32 intid, struct kvm_vcpu *vcpu) { vgic_poke_irq(gic_fd, intid, vcpu, GICD_ISACTIVER); } diff --git a/tools/testing/selftests/kvm/lib/elf.c b/tools/testing/selftests/kvm/lib/elf.c index f34d926d9735..b689c4df4a01 100644 --- a/tools/testing/selftests/kvm/lib/elf.c +++ b/tools/testing/selftests/kvm/lib/elf.c @@ -156,21 +156,20 @@ void kvm_vm_elf_load(struct kvm_vm *vm, const char *filename) TEST_ASSERT(phdr.p_memsz > 0, "Unexpected loadable segment " "memsize of 0,\n" " phdr index: %u p_memsz: 0x%" PRIx64, - n1, (uint64_t) phdr.p_memsz); - vm_vaddr_t seg_vstart = align_down(phdr.p_vaddr, vm->page_size); - vm_vaddr_t seg_vend = phdr.p_vaddr + phdr.p_memsz - 1; + n1, (u64)phdr.p_memsz); + gva_t seg_vstart = align_down(phdr.p_vaddr, vm->page_size); + gva_t seg_vend = phdr.p_vaddr + phdr.p_memsz - 1; seg_vend |= vm->page_size - 1; size_t seg_size = seg_vend - seg_vstart + 1; - vm_vaddr_t vaddr = __vm_vaddr_alloc(vm, seg_size, seg_vstart, - MEM_REGION_CODE); - TEST_ASSERT(vaddr == seg_vstart, "Unable to allocate " + gva_t gva = __vm_alloc(vm, seg_size, seg_vstart, MEM_REGION_CODE); + TEST_ASSERT(gva == seg_vstart, "Unable to allocate " "virtual memory for segment at requested min addr,\n" " segment idx: %u\n" " seg_vstart: 0x%lx\n" - " vaddr: 0x%lx", - n1, seg_vstart, vaddr); - memset(addr_gva2hva(vm, vaddr), 0, seg_size); + " gva: 0x%lx", + n1, seg_vstart, gva); + memset(addr_gva2hva(vm, gva), 0, seg_size); /* TODO(lhuemill): Set permissions of each memory segment * based on the least-significant 3 bits of phdr.p_flags. */ diff --git a/tools/testing/selftests/kvm/lib/guest_modes.c b/tools/testing/selftests/kvm/lib/guest_modes.c index ce3099630397..7a96c43b5704 100644 --- a/tools/testing/selftests/kvm/lib/guest_modes.c +++ b/tools/testing/selftests/kvm/lib/guest_modes.c @@ -20,7 +20,7 @@ void guest_modes_append_default(void) #ifdef __aarch64__ { unsigned int limit = kvm_check_cap(KVM_CAP_ARM_VM_IPA_SIZE); - uint32_t ipa4k, ipa16k, ipa64k; + u32 ipa4k, ipa16k, ipa64k; int i; aarch64_get_supported_page_sizes(limit, &ipa4k, &ipa16k, &ipa64k); diff --git a/tools/testing/selftests/kvm/lib/guest_sprintf.c b/tools/testing/selftests/kvm/lib/guest_sprintf.c index 74627514c4d4..7a33965349a7 100644 --- a/tools/testing/selftests/kvm/lib/guest_sprintf.c +++ b/tools/testing/selftests/kvm/lib/guest_sprintf.c @@ -35,8 +35,8 @@ static int skip_atoi(const char **s) ({ \ int __res; \ \ - __res = ((uint64_t) n) % (uint32_t) base; \ - n = ((uint64_t) n) / (uint32_t) base; \ + __res = ((u64)n) % (u32)base; \ + n = ((u64)n) / (u32)base; \ __res; \ }) @@ -119,7 +119,7 @@ int guest_vsnprintf(char *buf, int n, const char *fmt, va_list args) { char *str, *end; const char *s; - uint64_t num; + u64 num; int i, base; int len; @@ -216,7 +216,7 @@ int guest_vsnprintf(char *buf, int n, const char *fmt, va_list args) while (--field_width > 0) APPEND_BUFFER_SAFE(str, end, ' '); APPEND_BUFFER_SAFE(str, end, - (uint8_t)va_arg(args, int)); + (u8)va_arg(args, int)); while (--field_width > 0) APPEND_BUFFER_SAFE(str, end, ' '); continue; @@ -240,7 +240,7 @@ int guest_vsnprintf(char *buf, int n, const char *fmt, va_list args) flags |= SPECIAL | SMALL | ZEROPAD; } str = number(str, end, - (uint64_t)va_arg(args, void *), 16, + (u64)va_arg(args, void *), 16, field_width, precision, flags); continue; @@ -284,15 +284,15 @@ int guest_vsnprintf(char *buf, int n, const char *fmt, va_list args) continue; } if (qualifier == 'l') - num = va_arg(args, uint64_t); + num = va_arg(args, u64); else if (qualifier == 'h') { - num = (uint16_t)va_arg(args, int); + num = (u16)va_arg(args, int); if (flags & SIGN) - num = (int16_t)num; + num = (s16)num; } else if (flags & SIGN) num = va_arg(args, int); else - num = va_arg(args, uint32_t); + num = va_arg(args, u32); str = number(str, end, num, base, field_width, precision, flags); } diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/selftests/kvm/lib/kvm_util.c index f5e076591c64..2a76eca7029d 100644 --- a/tools/testing/selftests/kvm/lib/kvm_util.c +++ b/tools/testing/selftests/kvm/lib/kvm_util.c @@ -20,9 +20,9 @@ #define KVM_UTIL_MIN_PFN 2 -uint32_t guest_random_seed; +u32 guest_random_seed; struct guest_random_state guest_rng; -static uint32_t last_guest_seed; +static u32 last_guest_seed; static size_t vcpu_mmap_sz(void); @@ -165,7 +165,7 @@ unsigned int kvm_check_cap(long cap) return (unsigned int)ret; } -void vm_enable_dirty_ring(struct kvm_vm *vm, uint32_t ring_size) +void vm_enable_dirty_ring(struct kvm_vm *vm, u32 ring_size) { if (vm_check_cap(vm, KVM_CAP_DIRTY_LOG_RING_ACQ_REL)) vm_enable_cap(vm, KVM_CAP_DIRTY_LOG_RING_ACQ_REL, ring_size); @@ -189,7 +189,7 @@ static void vm_open(struct kvm_vm *vm) vm->stats.fd = -1; } -const char *vm_guest_mode_string(uint32_t i) +const char *vm_guest_mode_string(u32 i) { static const char * const strings[] = { [VM_MODE_P52V48_4K] = "PA-bits:52, VA-bits:48, 4K pages", @@ -267,7 +267,7 @@ _Static_assert(sizeof(vm_guest_mode_params)/sizeof(struct vm_guest_mode_params) * based on the MSB of the VA. On architectures with this behavior * the VA region spans [0, 2^(va_bits - 1)), [-(2^(va_bits - 1), -1]. */ -__weak void vm_vaddr_populate_bitmap(struct kvm_vm *vm) +__weak void vm_populate_gva_bitmap(struct kvm_vm *vm) { sparsebit_set_num(vm->vpages_valid, 0, (1ULL << (vm->va_bits - 1)) >> vm->page_shift); @@ -385,7 +385,7 @@ struct kvm_vm *____vm_create(struct vm_shape shape) /* Limit to VA-bit canonical virtual addresses. */ vm->vpages_valid = sparsebit_alloc(); - vm_vaddr_populate_bitmap(vm); + vm_populate_gva_bitmap(vm); /* Limit physical addresses to PA-bits. */ vm->max_gfn = vm_compute_max_gfn(vm); @@ -396,12 +396,12 @@ struct kvm_vm *____vm_create(struct vm_shape shape) return vm; } -static uint64_t vm_nr_pages_required(enum vm_guest_mode mode, - uint32_t nr_runnable_vcpus, - uint64_t extra_mem_pages) +static u64 vm_nr_pages_required(enum vm_guest_mode mode, + u32 nr_runnable_vcpus, + u64 extra_mem_pages) { - uint64_t page_size = vm_guest_mode_params[mode].page_size; - uint64_t nr_pages; + u64 page_size = vm_guest_mode_params[mode].page_size; + u64 nr_pages; TEST_ASSERT(nr_runnable_vcpus, "Use vm_create_barebones() for VMs that _never_ have vCPUs"); @@ -435,7 +435,7 @@ static uint64_t vm_nr_pages_required(enum vm_guest_mode mode, return vm_adjust_num_guest_pages(mode, nr_pages); } -void kvm_set_files_rlimit(uint32_t nr_vcpus) +void kvm_set_files_rlimit(u32 nr_vcpus) { /* * Each vCPU will open two file descriptors: the vCPU itself and the @@ -476,10 +476,10 @@ static bool is_guest_memfd_required(struct vm_shape shape) #endif } -struct kvm_vm *__vm_create(struct vm_shape shape, uint32_t nr_runnable_vcpus, - uint64_t nr_extra_pages) +struct kvm_vm *__vm_create(struct vm_shape shape, u32 nr_runnable_vcpus, + u64 nr_extra_pages) { - uint64_t nr_pages = vm_nr_pages_required(shape.mode, nr_runnable_vcpus, + u64 nr_pages = vm_nr_pages_required(shape.mode, nr_runnable_vcpus, nr_extra_pages); struct userspace_mem_region *slot0; struct kvm_vm *vm; @@ -546,8 +546,8 @@ struct kvm_vm *__vm_create(struct vm_shape shape, uint32_t nr_runnable_vcpus, * extra_mem_pages is only used to calculate the maximum page table size, * no real memory allocation for non-slot0 memory in this function. */ -struct kvm_vm *__vm_create_with_vcpus(struct vm_shape shape, uint32_t nr_vcpus, - uint64_t extra_mem_pages, +struct kvm_vm *__vm_create_with_vcpus(struct vm_shape shape, u32 nr_vcpus, + u64 extra_mem_pages, void *guest_code, struct kvm_vcpu *vcpus[]) { struct kvm_vm *vm; @@ -566,7 +566,7 @@ struct kvm_vm *__vm_create_with_vcpus(struct vm_shape shape, uint32_t nr_vcpus, struct kvm_vm *__vm_create_shape_with_one_vcpu(struct vm_shape shape, struct kvm_vcpu **vcpu, - uint64_t extra_mem_pages, + u64 extra_mem_pages, void *guest_code) { struct kvm_vcpu *vcpus[1]; @@ -614,7 +614,7 @@ void kvm_vm_restart(struct kvm_vm *vmp) } __weak struct kvm_vcpu *vm_arch_vcpu_recreate(struct kvm_vm *vm, - uint32_t vcpu_id) + u32 vcpu_id) { return __vm_vcpu_add(vm, vcpu_id); } @@ -636,9 +636,9 @@ int __pin_task_to_cpu(pthread_t task, int cpu) return pthread_setaffinity_np(task, sizeof(cpuset), &cpuset); } -static uint32_t parse_pcpu(const char *cpu_str, const cpu_set_t *allowed_mask) +static u32 parse_pcpu(const char *cpu_str, const cpu_set_t *allowed_mask) { - uint32_t pcpu = atoi_non_negative("CPU number", cpu_str); + u32 pcpu = atoi_non_negative("CPU number", cpu_str); TEST_ASSERT(CPU_ISSET(pcpu, allowed_mask), "Not allowed to run on pCPU '%d', check cgroups?", pcpu); @@ -662,7 +662,7 @@ void kvm_print_vcpu_pinning_help(void) " (default: no pinning)\n", name, name); } -void kvm_parse_vcpu_pinning(const char *pcpus_string, uint32_t vcpu_to_pcpu[], +void kvm_parse_vcpu_pinning(const char *pcpus_string, u32 vcpu_to_pcpu[], int nr_vcpus) { cpu_set_t allowed_mask; @@ -715,15 +715,15 @@ void kvm_parse_vcpu_pinning(const char *pcpus_string, uint32_t vcpu_to_pcpu[], * region exists. */ static struct userspace_mem_region * -userspace_mem_region_find(struct kvm_vm *vm, uint64_t start, uint64_t end) +userspace_mem_region_find(struct kvm_vm *vm, u64 start, u64 end) { struct rb_node *node; for (node = vm->regions.gpa_tree.rb_node; node; ) { struct userspace_mem_region *region = container_of(node, struct userspace_mem_region, gpa_node); - uint64_t existing_start = region->region.guest_phys_addr; - uint64_t existing_end = region->region.guest_phys_addr + u64 existing_start = region->region.guest_phys_addr; + u64 existing_end = region->region.guest_phys_addr + region->region.memory_size - 1; if (start <= existing_end && end >= existing_start) return region; @@ -918,8 +918,8 @@ static void vm_userspace_mem_region_hva_insert(struct rb_root *hva_tree, } -int __vm_set_user_memory_region(struct kvm_vm *vm, uint32_t slot, uint32_t flags, - uint64_t gpa, uint64_t size, void *hva) +int __vm_set_user_memory_region(struct kvm_vm *vm, u32 slot, u32 flags, + gpa_t gpa, u64 size, void *hva) { struct kvm_userspace_memory_region region = { .slot = slot, @@ -932,8 +932,8 @@ int __vm_set_user_memory_region(struct kvm_vm *vm, uint32_t slot, uint32_t flags return ioctl(vm->fd, KVM_SET_USER_MEMORY_REGION, ®ion); } -void vm_set_user_memory_region(struct kvm_vm *vm, uint32_t slot, uint32_t flags, - uint64_t gpa, uint64_t size, void *hva) +void vm_set_user_memory_region(struct kvm_vm *vm, u32 slot, u32 flags, + gpa_t gpa, u64 size, void *hva) { int ret = __vm_set_user_memory_region(vm, slot, flags, gpa, size, hva); @@ -945,9 +945,9 @@ void vm_set_user_memory_region(struct kvm_vm *vm, uint32_t slot, uint32_t flags, __TEST_REQUIRE(kvm_has_cap(KVM_CAP_USER_MEMORY2), \ "KVM selftests now require KVM_SET_USER_MEMORY_REGION2 (introduced in v6.8)") -int __vm_set_user_memory_region2(struct kvm_vm *vm, uint32_t slot, uint32_t flags, - uint64_t gpa, uint64_t size, void *hva, - uint32_t guest_memfd, uint64_t guest_memfd_offset) +int __vm_set_user_memory_region2(struct kvm_vm *vm, u32 slot, u32 flags, + gpa_t gpa, u64 size, void *hva, + u32 guest_memfd, u64 guest_memfd_offset) { struct kvm_userspace_memory_region2 region = { .slot = slot, @@ -964,9 +964,9 @@ int __vm_set_user_memory_region2(struct kvm_vm *vm, uint32_t slot, uint32_t flag return ioctl(vm->fd, KVM_SET_USER_MEMORY_REGION2, ®ion); } -void vm_set_user_memory_region2(struct kvm_vm *vm, uint32_t slot, uint32_t flags, - uint64_t gpa, uint64_t size, void *hva, - uint32_t guest_memfd, uint64_t guest_memfd_offset) +void vm_set_user_memory_region2(struct kvm_vm *vm, u32 slot, u32 flags, + gpa_t gpa, u64 size, void *hva, + u32 guest_memfd, u64 guest_memfd_offset) { int ret = __vm_set_user_memory_region2(vm, slot, flags, gpa, size, hva, guest_memfd, guest_memfd_offset); @@ -978,8 +978,8 @@ void vm_set_user_memory_region2(struct kvm_vm *vm, uint32_t slot, uint32_t flags /* FIXME: This thing needs to be ripped apart and rewritten. */ void vm_mem_add(struct kvm_vm *vm, enum vm_mem_backing_src_type src_type, - uint64_t gpa, uint32_t slot, uint64_t npages, uint32_t flags, - int guest_memfd, uint64_t guest_memfd_offset) + gpa_t gpa, u32 slot, u64 npages, u32 flags, + int guest_memfd, u64 guest_memfd_offset) { int ret; struct userspace_mem_region *region; @@ -1016,8 +1016,8 @@ void vm_mem_add(struct kvm_vm *vm, enum vm_mem_backing_src_type src_type, " requested gpa: 0x%lx npages: 0x%lx page_size: 0x%x\n" " existing gpa: 0x%lx size: 0x%lx", gpa, npages, vm->page_size, - (uint64_t) region->region.guest_phys_addr, - (uint64_t) region->region.memory_size); + (u64)region->region.guest_phys_addr, + (u64)region->region.memory_size); /* Confirm no region with the requested slot already exists. */ hash_for_each_possible(vm->regions.slot_hash, region, slot_node, @@ -1027,11 +1027,11 @@ void vm_mem_add(struct kvm_vm *vm, enum vm_mem_backing_src_type src_type, TEST_FAIL("A mem region with the requested slot " "already exists.\n" - " requested slot: %u paddr: 0x%lx npages: 0x%lx\n" - " existing slot: %u paddr: 0x%lx size: 0x%lx", + " requested slot: %u gpa: 0x%lx npages: 0x%lx\n" + " existing slot: %u gpa: 0x%lx size: 0x%lx", slot, gpa, npages, region->region.slot, - (uint64_t) region->region.guest_phys_addr, - (uint64_t) region->region.memory_size); + (u64)region->region.guest_phys_addr, + (u64)region->region.memory_size); } /* Allocate and initialize new mem region structure. */ @@ -1085,7 +1085,7 @@ void vm_mem_add(struct kvm_vm *vm, enum vm_mem_backing_src_type src_type, if (flags & KVM_MEM_GUEST_MEMFD) { if (guest_memfd < 0) { - uint32_t guest_memfd_flags = 0; + u32 guest_memfd_flags = 0; TEST_ASSERT(!guest_memfd_offset, "Offset must be zero when creating new guest_memfd"); guest_memfd = vm_create_guest_memfd(vm, mem_size, guest_memfd_flags); @@ -1141,8 +1141,7 @@ void vm_mem_add(struct kvm_vm *vm, enum vm_mem_backing_src_type src_type, void vm_userspace_mem_region_add(struct kvm_vm *vm, enum vm_mem_backing_src_type src_type, - uint64_t gpa, uint32_t slot, uint64_t npages, - uint32_t flags) + gpa_t gpa, u32 slot, u64 npages, u32 flags) { vm_mem_add(vm, src_type, gpa, slot, npages, flags, -1, 0); } @@ -1163,7 +1162,7 @@ void vm_userspace_mem_region_add(struct kvm_vm *vm, * memory slot ID). */ struct userspace_mem_region * -memslot2region(struct kvm_vm *vm, uint32_t memslot) +memslot2region(struct kvm_vm *vm, u32 memslot) { struct userspace_mem_region *region; @@ -1194,7 +1193,7 @@ memslot2region(struct kvm_vm *vm, uint32_t memslot) * Sets the flags of the memory region specified by the value of slot, * to the values given by flags. */ -void vm_mem_region_set_flags(struct kvm_vm *vm, uint32_t slot, uint32_t flags) +void vm_mem_region_set_flags(struct kvm_vm *vm, u32 slot, u32 flags) { int ret; struct userspace_mem_region *region; @@ -1210,7 +1209,7 @@ void vm_mem_region_set_flags(struct kvm_vm *vm, uint32_t slot, uint32_t flags) ret, errno, slot, flags); } -void vm_mem_region_reload(struct kvm_vm *vm, uint32_t slot) +void vm_mem_region_reload(struct kvm_vm *vm, u32 slot) { struct userspace_mem_region *region = memslot2region(vm, slot); struct kvm_userspace_memory_region2 tmp = region->region; @@ -1234,7 +1233,7 @@ void vm_mem_region_reload(struct kvm_vm *vm, uint32_t slot) * * Change the gpa of a memory region. */ -void vm_mem_region_move(struct kvm_vm *vm, uint32_t slot, uint64_t new_gpa) +void vm_mem_region_move(struct kvm_vm *vm, u32 slot, u64 new_gpa) { struct userspace_mem_region *region; int ret; @@ -1263,7 +1262,7 @@ void vm_mem_region_move(struct kvm_vm *vm, uint32_t slot, uint64_t new_gpa) * * Delete a memory region. */ -void vm_mem_region_delete(struct kvm_vm *vm, uint32_t slot) +void vm_mem_region_delete(struct kvm_vm *vm, u32 slot) { struct userspace_mem_region *region = memslot2region(vm, slot); @@ -1273,18 +1272,18 @@ void vm_mem_region_delete(struct kvm_vm *vm, uint32_t slot) __vm_mem_region_delete(vm, region); } -void vm_guest_mem_fallocate(struct kvm_vm *vm, uint64_t base, uint64_t size, +void vm_guest_mem_fallocate(struct kvm_vm *vm, u64 base, u64 size, bool punch_hole) { const int mode = FALLOC_FL_KEEP_SIZE | (punch_hole ? FALLOC_FL_PUNCH_HOLE : 0); struct userspace_mem_region *region; - uint64_t end = base + size; - uint64_t gpa, len; + u64 end = base + size; + gpa_t gpa, len; off_t fd_offset; int ret; for (gpa = base; gpa < end; gpa += len) { - uint64_t offset; + u64 offset; region = userspace_mem_region_find(vm, gpa, gpa); TEST_ASSERT(region && region->region.flags & KVM_MEM_GUEST_MEMFD, @@ -1292,7 +1291,7 @@ void vm_guest_mem_fallocate(struct kvm_vm *vm, uint64_t base, uint64_t size, offset = gpa - region->region.guest_phys_addr; fd_offset = region->region.guest_memfd_offset + offset; - len = min_t(uint64_t, end - gpa, region->region.memory_size - offset); + len = min_t(u64, end - gpa, region->region.memory_size - offset); ret = fallocate(region->region.guest_memfd, mode, fd_offset, len); TEST_ASSERT(!ret, "fallocate() failed to %s at %lx (len = %lu), fd = %d, mode = %x, offset = %lx", @@ -1317,7 +1316,7 @@ static size_t vcpu_mmap_sz(void) return ret; } -static bool vcpu_exists(struct kvm_vm *vm, uint32_t vcpu_id) +static bool vcpu_exists(struct kvm_vm *vm, u32 vcpu_id) { struct kvm_vcpu *vcpu; @@ -1333,7 +1332,7 @@ static bool vcpu_exists(struct kvm_vm *vm, uint32_t vcpu_id) * Adds a virtual CPU to the VM specified by vm with the ID given by vcpu_id. * No additional vCPU setup is done. Returns the vCPU. */ -struct kvm_vcpu *__vm_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) +struct kvm_vcpu *__vm_vcpu_add(struct kvm_vm *vm, u32 vcpu_id) { struct kvm_vcpu *vcpu; @@ -1367,33 +1366,18 @@ struct kvm_vcpu *__vm_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) } /* - * VM Virtual Address Unused Gap - * - * Input Args: - * vm - Virtual Machine - * sz - Size (bytes) - * vaddr_min - Minimum Virtual Address - * - * Output Args: None - * - * Return: - * Lowest virtual address at or above vaddr_min, with at least - * sz unused bytes. TEST_ASSERT failure if no area of at least - * size sz is available. - * - * Within the VM specified by vm, locates the lowest starting virtual - * address >= vaddr_min, that has at least sz unallocated bytes. A + * Within the VM specified by @vm, locates the lowest starting guest virtual + * address >= @min_gva, that has at least @sz unallocated bytes. A * TEST_ASSERT failure occurs for invalid input or no area of at least - * sz unallocated bytes >= vaddr_min is available. + * @sz unallocated bytes >= @min_gva is available. */ -vm_vaddr_t vm_vaddr_unused_gap(struct kvm_vm *vm, size_t sz, - vm_vaddr_t vaddr_min) +gva_t vm_unused_gva_gap(struct kvm_vm *vm, size_t sz, gva_t min_gva) { - uint64_t pages = (sz + vm->page_size - 1) >> vm->page_shift; + u64 pages = (sz + vm->page_size - 1) >> vm->page_shift; /* Determine lowest permitted virtual page index. */ - uint64_t pgidx_start = (vaddr_min + vm->page_size - 1) >> vm->page_shift; - if ((pgidx_start * vm->page_size) < vaddr_min) + u64 pgidx_start = (min_gva + vm->page_size - 1) >> vm->page_shift; + if ((pgidx_start * vm->page_size) < min_gva) goto no_va_found; /* Loop over section with enough valid virtual page indexes. */ @@ -1430,7 +1414,7 @@ vm_vaddr_t vm_vaddr_unused_gap(struct kvm_vm *vm, size_t sz, } while (pgidx_start != 0); no_va_found: - TEST_FAIL("No vaddr of specified pages available, pages: 0x%lx", pages); + TEST_FAIL("No gva of specified pages available, pages: 0x%lx", pages); /* NOT REACHED */ return -1; @@ -1452,145 +1436,91 @@ vm_vaddr_t vm_vaddr_unused_gap(struct kvm_vm *vm, size_t sz, return pgidx_start * vm->page_size; } -static vm_vaddr_t ____vm_vaddr_alloc(struct kvm_vm *vm, size_t sz, - vm_vaddr_t vaddr_min, - enum kvm_mem_region_type type, - bool protected) +static gva_t ____vm_alloc(struct kvm_vm *vm, size_t sz, gva_t min_gva, + enum kvm_mem_region_type type, bool protected) { - uint64_t pages = (sz >> vm->page_shift) + ((sz % vm->page_size) != 0); + u64 pages = (sz >> vm->page_shift) + ((sz % vm->page_size) != 0); virt_pgd_alloc(vm); - vm_paddr_t paddr = __vm_phy_pages_alloc(vm, pages, - KVM_UTIL_MIN_PFN * vm->page_size, - vm->memslots[type], protected); + gpa_t gpa = __vm_phy_pages_alloc(vm, pages, + KVM_UTIL_MIN_PFN * vm->page_size, + vm->memslots[type], protected); /* * Find an unused range of virtual page addresses of at least * pages in length. */ - vm_vaddr_t vaddr_start = vm_vaddr_unused_gap(vm, sz, vaddr_min); + gva_t gva_start = vm_unused_gva_gap(vm, sz, min_gva); /* Map the virtual pages. */ - for (vm_vaddr_t vaddr = vaddr_start; pages > 0; - pages--, vaddr += vm->page_size, paddr += vm->page_size) { + for (gva_t gva = gva_start; pages > 0; + pages--, gva += vm->page_size, gpa += vm->page_size) { - virt_pg_map(vm, vaddr, paddr); + virt_pg_map(vm, gva, gpa); } - return vaddr_start; + return gva_start; } -vm_vaddr_t __vm_vaddr_alloc(struct kvm_vm *vm, size_t sz, vm_vaddr_t vaddr_min, - enum kvm_mem_region_type type) +gva_t __vm_alloc(struct kvm_vm *vm, size_t sz, gva_t min_gva, + enum kvm_mem_region_type type) { - return ____vm_vaddr_alloc(vm, sz, vaddr_min, type, - vm_arch_has_protected_memory(vm)); + return ____vm_alloc(vm, sz, min_gva, type, + vm_arch_has_protected_memory(vm)); } -vm_vaddr_t vm_vaddr_alloc_shared(struct kvm_vm *vm, size_t sz, - vm_vaddr_t vaddr_min, - enum kvm_mem_region_type type) +gva_t vm_alloc_shared(struct kvm_vm *vm, size_t sz, gva_t min_gva, + enum kvm_mem_region_type type) { - return ____vm_vaddr_alloc(vm, sz, vaddr_min, type, false); + return ____vm_alloc(vm, sz, min_gva, type, false); } /* - * VM Virtual Address Allocate - * - * Input Args: - * vm - Virtual Machine - * sz - Size in bytes - * vaddr_min - Minimum starting virtual address - * - * Output Args: None - * - * Return: - * Starting guest virtual address - * - * Allocates at least sz bytes within the virtual address space of the vm - * given by vm. The allocated bytes are mapped to a virtual address >= - * the address given by vaddr_min. Note that each allocation uses a - * a unique set of pages, with the minimum real allocation being at least - * a page. The allocated physical space comes from the TEST_DATA memory region. + * Allocates at least sz bytes within the virtual address space of the VM + * given by @vm. The allocated bytes are mapped to a virtual address >= the + * address given by @min_gva. Note that each allocation uses a a unique set + * of pages, with the minimum real allocation being at least a page. The + * allocated physical space comes from the TEST_DATA memory region. */ -vm_vaddr_t vm_vaddr_alloc(struct kvm_vm *vm, size_t sz, vm_vaddr_t vaddr_min) +gva_t vm_alloc(struct kvm_vm *vm, size_t sz, gva_t min_gva) { - return __vm_vaddr_alloc(vm, sz, vaddr_min, MEM_REGION_TEST_DATA); + return __vm_alloc(vm, sz, min_gva, MEM_REGION_TEST_DATA); +} + +gva_t vm_alloc_pages(struct kvm_vm *vm, int nr_pages) +{ + return vm_alloc(vm, nr_pages * getpagesize(), KVM_UTIL_MIN_VADDR); +} + +gva_t __vm_alloc_page(struct kvm_vm *vm, enum kvm_mem_region_type type) +{ + return __vm_alloc(vm, getpagesize(), KVM_UTIL_MIN_VADDR, type); +} + +gva_t vm_alloc_page(struct kvm_vm *vm) +{ + return vm_alloc_pages(vm, 1); } /* - * VM Virtual Address Allocate Pages + * Map a range of VM virtual address to the VM's physical address. * - * Input Args: - * vm - Virtual Machine - * - * Output Args: None - * - * Return: - * Starting guest virtual address - * - * Allocates at least N system pages worth of bytes within the virtual address - * space of the vm. + * Within the VM given by @vm, creates a virtual translation for @npages + * starting at @gva to the page range starting at @gpa. */ -vm_vaddr_t vm_vaddr_alloc_pages(struct kvm_vm *vm, int nr_pages) -{ - return vm_vaddr_alloc(vm, nr_pages * getpagesize(), KVM_UTIL_MIN_VADDR); -} - -vm_vaddr_t __vm_vaddr_alloc_page(struct kvm_vm *vm, enum kvm_mem_region_type type) -{ - return __vm_vaddr_alloc(vm, getpagesize(), KVM_UTIL_MIN_VADDR, type); -} - -/* - * VM Virtual Address Allocate Page - * - * Input Args: - * vm - Virtual Machine - * - * Output Args: None - * - * Return: - * Starting guest virtual address - * - * Allocates at least one system page worth of bytes within the virtual address - * space of the vm. - */ -vm_vaddr_t vm_vaddr_alloc_page(struct kvm_vm *vm) -{ - return vm_vaddr_alloc_pages(vm, 1); -} - -/* - * Map a range of VM virtual address to the VM's physical address - * - * Input Args: - * vm - Virtual Machine - * vaddr - Virtuall address to map - * paddr - VM Physical Address - * npages - The number of pages to map - * - * Output Args: None - * - * Return: None - * - * Within the VM given by @vm, creates a virtual translation for - * @npages starting at @vaddr to the page range starting at @paddr. - */ -void virt_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, - unsigned int npages) +void virt_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa, unsigned int npages) { size_t page_size = vm->page_size; size_t size = npages * page_size; - TEST_ASSERT(vaddr + size > vaddr, "Vaddr overflow"); - TEST_ASSERT(paddr + size > paddr, "Paddr overflow"); + TEST_ASSERT(gva + size > gva, "Vaddr overflow"); + TEST_ASSERT(gpa + size > gpa, "Paddr overflow"); while (npages--) { - virt_pg_map(vm, vaddr, paddr); + virt_pg_map(vm, gva, gpa); - vaddr += page_size; - paddr += page_size; + gva += page_size; + gpa += page_size; } } @@ -1611,7 +1541,7 @@ void virt_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, * address providing the memory to the vm physical address is returned. * A TEST_ASSERT failure occurs if no region containing gpa exists. */ -void *addr_gpa2hva(struct kvm_vm *vm, vm_paddr_t gpa) +void *addr_gpa2hva(struct kvm_vm *vm, gpa_t gpa) { struct userspace_mem_region *region; @@ -1644,7 +1574,7 @@ void *addr_gpa2hva(struct kvm_vm *vm, vm_paddr_t gpa) * VM physical address is returned. A TEST_ASSERT failure occurs if no * region containing hva exists. */ -vm_paddr_t addr_hva2gpa(struct kvm_vm *vm, void *hva) +gpa_t addr_hva2gpa(struct kvm_vm *vm, void *hva) { struct rb_node *node; @@ -1655,7 +1585,7 @@ vm_paddr_t addr_hva2gpa(struct kvm_vm *vm, void *hva) if (hva >= region->host_mem) { if (hva <= (region->host_mem + region->region.memory_size - 1)) - return (vm_paddr_t)((uintptr_t) + return (gpa_t)((uintptr_t) region->region.guest_phys_addr + (hva - (uintptr_t)region->host_mem)); @@ -1687,7 +1617,7 @@ vm_paddr_t addr_hva2gpa(struct kvm_vm *vm, void *hva) * memory without mapping said memory in the guest's address space. And, for * userfaultfd-based demand paging, to do so without triggering userfaults. */ -void *addr_gpa2alias(struct kvm_vm *vm, vm_paddr_t gpa) +void *addr_gpa2alias(struct kvm_vm *vm, gpa_t gpa) { struct userspace_mem_region *region; uintptr_t offset; @@ -1781,8 +1711,8 @@ struct kvm_reg_list *vcpu_get_reg_list(struct kvm_vcpu *vcpu) void *vcpu_map_dirty_ring(struct kvm_vcpu *vcpu) { - uint32_t page_size = getpagesize(); - uint32_t size = vcpu->vm->dirty_ring_size; + u32 page_size = getpagesize(); + u32 size = vcpu->vm->dirty_ring_size; TEST_ASSERT(size > 0, "Should enable dirty ring first"); @@ -1811,7 +1741,7 @@ void *vcpu_map_dirty_ring(struct kvm_vcpu *vcpu) * Device Ioctl */ -int __kvm_has_device_attr(int dev_fd, uint32_t group, uint64_t attr) +int __kvm_has_device_attr(int dev_fd, u32 group, u64 attr) { struct kvm_device_attr attribute = { .group = group, @@ -1822,7 +1752,7 @@ int __kvm_has_device_attr(int dev_fd, uint32_t group, uint64_t attr) return ioctl(dev_fd, KVM_HAS_DEVICE_ATTR, &attribute); } -int __kvm_test_create_device(struct kvm_vm *vm, uint64_t type) +int __kvm_test_create_device(struct kvm_vm *vm, u64 type) { struct kvm_create_device create_dev = { .type = type, @@ -1832,7 +1762,7 @@ int __kvm_test_create_device(struct kvm_vm *vm, uint64_t type) return __vm_ioctl(vm, KVM_CREATE_DEVICE, &create_dev); } -int __kvm_create_device(struct kvm_vm *vm, uint64_t type) +int __kvm_create_device(struct kvm_vm *vm, u64 type) { struct kvm_create_device create_dev = { .type = type, @@ -1846,7 +1776,7 @@ int __kvm_create_device(struct kvm_vm *vm, uint64_t type) return err ? : create_dev.fd; } -int __kvm_device_attr_get(int dev_fd, uint32_t group, uint64_t attr, void *val) +int __kvm_device_attr_get(int dev_fd, u32 group, u64 attr, void *val) { struct kvm_device_attr kvmattr = { .group = group, @@ -1858,7 +1788,7 @@ int __kvm_device_attr_get(int dev_fd, uint32_t group, uint64_t attr, void *val) return __kvm_ioctl(dev_fd, KVM_GET_DEVICE_ATTR, &kvmattr); } -int __kvm_device_attr_set(int dev_fd, uint32_t group, uint64_t attr, void *val) +int __kvm_device_attr_set(int dev_fd, u32 group, u64 attr, void *val) { struct kvm_device_attr kvmattr = { .group = group, @@ -1874,7 +1804,7 @@ int __kvm_device_attr_set(int dev_fd, uint32_t group, uint64_t attr, void *val) * IRQ related functions. */ -int _kvm_irq_line(struct kvm_vm *vm, uint32_t irq, int level) +int _kvm_irq_line(struct kvm_vm *vm, u32 irq, int level) { struct kvm_irq_level irq_level = { .irq = irq, @@ -1884,7 +1814,7 @@ int _kvm_irq_line(struct kvm_vm *vm, uint32_t irq, int level) return __vm_ioctl(vm, KVM_IRQ_LINE, &irq_level); } -void kvm_irq_line(struct kvm_vm *vm, uint32_t irq, int level) +void kvm_irq_line(struct kvm_vm *vm, u32 irq, int level) { int ret = _kvm_irq_line(vm, irq, level); @@ -1906,7 +1836,7 @@ struct kvm_irq_routing *kvm_gsi_routing_create(void) } void kvm_gsi_routing_irqchip_add(struct kvm_irq_routing *routing, - uint32_t gsi, uint32_t pin) + u32 gsi, u32 pin) { int i; @@ -1956,7 +1886,7 @@ void kvm_gsi_routing_write(struct kvm_vm *vm, struct kvm_irq_routing *routing) * Dumps the current state of the VM given by vm, to the FILE stream * given by stream. */ -void vm_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) +void vm_dump(FILE *stream, struct kvm_vm *vm, u8 indent) { int ctr; struct userspace_mem_region *region; @@ -1969,8 +1899,8 @@ void vm_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) hash_for_each(vm->regions.slot_hash, ctr, region, slot_node) { fprintf(stream, "%*sguest_phys: 0x%lx size: 0x%lx " "host_virt: %p\n", indent + 2, "", - (uint64_t) region->region.guest_phys_addr, - (uint64_t) region->region.memory_size, + (u64)region->region.guest_phys_addr, + (u64)region->region.memory_size, region->host_mem); fprintf(stream, "%*sunused_phy_pages: ", indent + 2, ""); sparsebit_dump(stream, region->unused_phy_pages, 0); @@ -2077,7 +2007,7 @@ const char *exit_reason_str(unsigned int exit_reason) * Input Args: * vm - Virtual Machine * num - number of pages - * paddr_min - Physical address minimum + * min_gpa - Physical address minimum * memslot - Memory region to allocate page from * protected - True if the pages will be used as protected/private memory * @@ -2087,29 +2017,29 @@ const char *exit_reason_str(unsigned int exit_reason) * Starting physical address * * Within the VM specified by vm, locates a range of available physical - * pages at or above paddr_min. If found, the pages are marked as in use + * pages at or above min_gpa. If found, the pages are marked as in use * and their base address is returned. A TEST_ASSERT failure occurs if - * not enough pages are available at or above paddr_min. + * not enough pages are available at or above min_gpa. */ -vm_paddr_t __vm_phy_pages_alloc(struct kvm_vm *vm, size_t num, - vm_paddr_t paddr_min, uint32_t memslot, - bool protected) +gpa_t __vm_phy_pages_alloc(struct kvm_vm *vm, size_t num, + gpa_t min_gpa, u32 memslot, + bool protected) { struct userspace_mem_region *region; sparsebit_idx_t pg, base; TEST_ASSERT(num > 0, "Must allocate at least one page"); - TEST_ASSERT((paddr_min % vm->page_size) == 0, "Min physical address " + TEST_ASSERT((min_gpa % vm->page_size) == 0, "Min physical address " "not divisible by page size.\n" - " paddr_min: 0x%lx page_size: 0x%x", - paddr_min, vm->page_size); + " min_gpa: 0x%lx page_size: 0x%x", + min_gpa, vm->page_size); region = memslot2region(vm, memslot); TEST_ASSERT(!protected || region->protected_phy_pages, "Region doesn't support protected memory"); - base = pg = paddr_min >> vm->page_shift; + base = pg = min_gpa >> vm->page_shift; do { for (; pg < base + num; ++pg) { if (!sparsebit_is_set(region->unused_phy_pages, pg)) { @@ -2121,8 +2051,8 @@ vm_paddr_t __vm_phy_pages_alloc(struct kvm_vm *vm, size_t num, if (pg == 0) { fprintf(stderr, "No guest physical page available, " - "paddr_min: 0x%lx page_size: 0x%x memslot: %u\n", - paddr_min, vm->page_size, memslot); + "min_gpa: 0x%lx page_size: 0x%x memslot: %u\n", + min_gpa, vm->page_size, memslot); fputs("---- vm dump ----\n", stderr); vm_dump(stderr, vm, 2); abort(); @@ -2137,13 +2067,12 @@ vm_paddr_t __vm_phy_pages_alloc(struct kvm_vm *vm, size_t num, return base * vm->page_size; } -vm_paddr_t vm_phy_page_alloc(struct kvm_vm *vm, vm_paddr_t paddr_min, - uint32_t memslot) +gpa_t vm_phy_page_alloc(struct kvm_vm *vm, gpa_t min_gpa, u32 memslot) { - return vm_phy_pages_alloc(vm, 1, paddr_min, memslot); + return vm_phy_pages_alloc(vm, 1, min_gpa, memslot); } -vm_paddr_t vm_alloc_page_table(struct kvm_vm *vm) +gpa_t vm_alloc_page_table(struct kvm_vm *vm) { return vm_phy_page_alloc(vm, KVM_GUEST_PAGE_TABLE_MIN_PADDR, vm->memslots[MEM_REGION_PT]); @@ -2161,7 +2090,7 @@ vm_paddr_t vm_alloc_page_table(struct kvm_vm *vm) * Return: * Equivalent host virtual address */ -void *addr_gva2hva(struct kvm_vm *vm, vm_vaddr_t gva) +void *addr_gva2hva(struct kvm_vm *vm, gva_t gva) { return addr_gpa2hva(vm, addr_gva2gpa(vm, gva)); } @@ -2259,7 +2188,7 @@ struct kvm_stats_desc *read_stats_descriptors(int stats_fd, * Read the data values of a specified stat from the binary stats interface. */ void read_stat_data(int stats_fd, struct kvm_stats_header *header, - struct kvm_stats_desc *desc, uint64_t *data, + struct kvm_stats_desc *desc, u64 *data, size_t max_elements) { size_t nr_elements = min_t(ssize_t, desc->size, max_elements); @@ -2280,7 +2209,7 @@ void read_stat_data(int stats_fd, struct kvm_stats_header *header, } void kvm_get_stat(struct kvm_binary_stats *stats, const char *name, - uint64_t *data, size_t max_elements) + u64 *data, size_t max_elements) { struct kvm_stats_desc *desc; size_t size_desc; @@ -2357,7 +2286,7 @@ void __attribute((constructor)) kvm_selftest_init(void) kvm_selftest_arch_init(); } -bool vm_is_gpa_protected(struct kvm_vm *vm, vm_paddr_t paddr) +bool vm_is_gpa_protected(struct kvm_vm *vm, gpa_t gpa) { sparsebit_idx_t pg = 0; struct userspace_mem_region *region; @@ -2365,10 +2294,10 @@ bool vm_is_gpa_protected(struct kvm_vm *vm, vm_paddr_t paddr) if (!vm_arch_has_protected_memory(vm)) return false; - region = userspace_mem_region_find(vm, paddr, paddr); - TEST_ASSERT(region, "No vm physical memory at 0x%lx", paddr); + region = userspace_mem_region_find(vm, gpa, gpa); + TEST_ASSERT(region, "No vm physical memory at 0x%lx", gpa); - pg = paddr >> vm->page_shift; + pg = gpa >> vm->page_shift; return sparsebit_is_set(region->protected_phy_pages, pg); } diff --git a/tools/testing/selftests/kvm/lib/loongarch/processor.c b/tools/testing/selftests/kvm/lib/loongarch/processor.c index ee4ad3b1d2a4..64d91fb76522 100644 --- a/tools/testing/selftests/kvm/lib/loongarch/processor.c +++ b/tools/testing/selftests/kvm/lib/loongarch/processor.c @@ -12,32 +12,32 @@ #define LOONGARCH_PAGE_TABLE_PHYS_MIN 0x200000 #define LOONGARCH_GUEST_STACK_VADDR_MIN 0x200000 -static vm_paddr_t invalid_pgtable[4]; -static vm_vaddr_t exception_handlers; +static gpa_t invalid_pgtable[4]; +static gva_t exception_handlers; -static uint64_t virt_pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int level) +static u64 virt_pte_index(struct kvm_vm *vm, gva_t gva, int level) { unsigned int shift; - uint64_t mask; + u64 mask; shift = level * (vm->page_shift - 3) + vm->page_shift; mask = (1UL << (vm->page_shift - 3)) - 1; return (gva >> shift) & mask; } -static uint64_t pte_addr(struct kvm_vm *vm, uint64_t entry) +static u64 pte_addr(struct kvm_vm *vm, u64 entry) { return entry & ~((0x1UL << vm->page_shift) - 1); } -static uint64_t ptrs_per_pte(struct kvm_vm *vm) +static u64 ptrs_per_pte(struct kvm_vm *vm) { return 1 << (vm->page_shift - 3); } -static void virt_set_pgtable(struct kvm_vm *vm, vm_paddr_t table, vm_paddr_t child) +static void virt_set_pgtable(struct kvm_vm *vm, gpa_t table, gpa_t child) { - uint64_t *ptep; + u64 *ptep; int i, ptrs_per_pte; ptep = addr_gpa2hva(vm, table); @@ -49,7 +49,7 @@ static void virt_set_pgtable(struct kvm_vm *vm, vm_paddr_t table, vm_paddr_t chi void virt_arch_pgd_alloc(struct kvm_vm *vm) { int i; - vm_paddr_t child, table; + gpa_t child, table; if (vm->mmu.pgd_created) return; @@ -67,16 +67,16 @@ void virt_arch_pgd_alloc(struct kvm_vm *vm) vm->mmu.pgd_created = true; } -static int virt_pte_none(uint64_t *ptep, int level) +static int virt_pte_none(u64 *ptep, int level) { return *ptep == invalid_pgtable[level]; } -static uint64_t *virt_populate_pte(struct kvm_vm *vm, vm_vaddr_t gva, int alloc) +static u64 *virt_populate_pte(struct kvm_vm *vm, gva_t gva, int alloc) { int level; - uint64_t *ptep; - vm_paddr_t child; + u64 *ptep; + gpa_t child; if (!vm->mmu.pgd_created) goto unmapped_gva; @@ -106,43 +106,42 @@ static uint64_t *virt_populate_pte(struct kvm_vm *vm, vm_vaddr_t gva, int alloc) exit(EXIT_FAILURE); } -vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) +gpa_t addr_arch_gva2gpa(struct kvm_vm *vm, gva_t gva) { - uint64_t *ptep; + u64 *ptep; ptep = virt_populate_pte(vm, gva, 0); - TEST_ASSERT(*ptep != 0, "Virtual address vaddr: 0x%lx not mapped\n", gva); + TEST_ASSERT(*ptep != 0, "Virtual address gva: 0x%lx not mapped\n", gva); return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1)); } -void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr) +void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa) { - uint32_t prot_bits; - uint64_t *ptep; + u32 prot_bits; + u64 *ptep; - TEST_ASSERT((vaddr % vm->page_size) == 0, + TEST_ASSERT((gva % vm->page_size) == 0, "Virtual address not on page boundary,\n" - "vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size); - TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, - (vaddr >> vm->page_shift)), - "Invalid virtual address, vaddr: 0x%lx", vaddr); - TEST_ASSERT((paddr % vm->page_size) == 0, + "gva: 0x%lx vm->page_size: 0x%x", gva, vm->page_size); + TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)), + "Invalid virtual address, gva: 0x%lx", gva); + TEST_ASSERT((gpa % vm->page_size) == 0, "Physical address not on page boundary,\n" - "paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size); - TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn, + "gpa: 0x%lx vm->page_size: 0x%x", gpa, vm->page_size); + TEST_ASSERT((gpa >> vm->page_shift) <= vm->max_gfn, "Physical address beyond maximum supported,\n" - "paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", - paddr, vm->max_gfn, vm->page_size); + "gpa: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", + gpa, vm->max_gfn, vm->page_size); - ptep = virt_populate_pte(vm, vaddr, 1); + ptep = virt_populate_pte(vm, gva, 1); prot_bits = _PAGE_PRESENT | __READABLE | __WRITEABLE | _CACHE_CC | _PAGE_USER; - WRITE_ONCE(*ptep, paddr | prot_bits); + WRITE_ONCE(*ptep, gpa | prot_bits); } -static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, uint64_t page, int level) +static void pte_dump(FILE *stream, struct kvm_vm *vm, u8 indent, u64 page, int level) { - uint64_t pte, *ptep; + u64 pte, *ptep; static const char * const type[] = { "pte", "pmd", "pud", "pgd"}; if (level < 0) @@ -158,7 +157,7 @@ static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, uint64_t p } } -void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) +void virt_arch_dump(FILE *stream, struct kvm_vm *vm, u8 indent) { int level; @@ -169,7 +168,7 @@ void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) pte_dump(stream, vm, indent, vm->mmu.pgd, level); } -void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent) +void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, u8 indent) { } @@ -206,8 +205,9 @@ void vm_init_descriptor_tables(struct kvm_vm *vm) { void *addr; - vm->handlers = __vm_vaddr_alloc(vm, sizeof(struct handlers), - LOONGARCH_GUEST_STACK_VADDR_MIN, MEM_REGION_DATA); + vm->handlers = __vm_alloc(vm, sizeof(struct handlers), + LOONGARCH_GUEST_STACK_VADDR_MIN, + MEM_REGION_DATA); addr = addr_gva2hva(vm, vm->handlers); memset(addr, 0, vm->page_size); @@ -223,7 +223,7 @@ void vm_install_exception_handler(struct kvm_vm *vm, int vector, handler_fn hand handlers->exception_handlers[vector] = handler; } -uint32_t guest_get_vcpuid(void) +u32 guest_get_vcpuid(void) { return csr_read(LOONGARCH_CSR_CPUID); } @@ -241,36 +241,36 @@ void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...) va_start(ap, num); for (i = 0; i < num; i++) - regs.gpr[i + 4] = va_arg(ap, uint64_t); + regs.gpr[i + 4] = va_arg(ap, u64); va_end(ap); vcpu_regs_set(vcpu, ®s); } -static void loongarch_set_reg(struct kvm_vcpu *vcpu, uint64_t id, uint64_t val) +static void loongarch_set_reg(struct kvm_vcpu *vcpu, u64 id, u64 val) { __vcpu_set_reg(vcpu, id, val); } -static void loongarch_set_cpucfg(struct kvm_vcpu *vcpu, uint64_t id, uint64_t val) +static void loongarch_set_cpucfg(struct kvm_vcpu *vcpu, u64 id, u64 val) { - uint64_t cfgid; + u64 cfgid; cfgid = KVM_REG_LOONGARCH_CPUCFG | KVM_REG_SIZE_U64 | 8 * id; __vcpu_set_reg(vcpu, cfgid, val); } -static void loongarch_get_csr(struct kvm_vcpu *vcpu, uint64_t id, void *addr) +static void loongarch_get_csr(struct kvm_vcpu *vcpu, u64 id, void *addr) { - uint64_t csrid; + u64 csrid; csrid = KVM_REG_LOONGARCH_CSR | KVM_REG_SIZE_U64 | 8 * id; __vcpu_get_reg(vcpu, csrid, addr); } -static void loongarch_set_csr(struct kvm_vcpu *vcpu, uint64_t id, uint64_t val) +static void loongarch_set_csr(struct kvm_vcpu *vcpu, u64 id, u64 val) { - uint64_t csrid; + u64 csrid; csrid = KVM_REG_LOONGARCH_CSR | KVM_REG_SIZE_U64 | 8 * id; __vcpu_set_reg(vcpu, csrid, val); @@ -354,8 +354,8 @@ void loongarch_vcpu_setup(struct kvm_vcpu *vcpu) loongarch_set_csr(vcpu, LOONGARCH_CSR_STLBPGSIZE, PS_DEFAULT_SIZE); /* LOONGARCH_CSR_KS1 is used for exception stack */ - val = __vm_vaddr_alloc(vm, vm->page_size, - LOONGARCH_GUEST_STACK_VADDR_MIN, MEM_REGION_DATA); + val = __vm_alloc(vm, vm->page_size, LOONGARCH_GUEST_STACK_VADDR_MIN, + MEM_REGION_DATA); TEST_ASSERT(val != 0, "No memory for exception stack"); val = val + vm->page_size; loongarch_set_csr(vcpu, LOONGARCH_CSR_KS1, val); @@ -369,23 +369,23 @@ void loongarch_vcpu_setup(struct kvm_vcpu *vcpu) loongarch_set_csr(vcpu, LOONGARCH_CSR_TMID, vcpu->id); } -struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) +struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u32 vcpu_id) { size_t stack_size; - uint64_t stack_vaddr; + u64 stack_gva; struct kvm_regs regs; struct kvm_vcpu *vcpu; vcpu = __vm_vcpu_add(vm, vcpu_id); stack_size = vm->page_size; - stack_vaddr = __vm_vaddr_alloc(vm, stack_size, - LOONGARCH_GUEST_STACK_VADDR_MIN, MEM_REGION_DATA); - TEST_ASSERT(stack_vaddr != 0, "No memory for vm stack"); + stack_gva = __vm_alloc(vm, stack_size, + LOONGARCH_GUEST_STACK_VADDR_MIN, MEM_REGION_DATA); + TEST_ASSERT(stack_gva != 0, "No memory for vm stack"); loongarch_vcpu_setup(vcpu); /* Setup guest general purpose registers */ vcpu_regs_get(vcpu, ®s); - regs.gpr[3] = stack_vaddr + stack_size; + regs.gpr[3] = stack_gva + stack_size; vcpu_regs_set(vcpu, ®s); return vcpu; @@ -397,6 +397,6 @@ void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code) /* Setup guest PC register */ vcpu_regs_get(vcpu, ®s); - regs.pc = (uint64_t)guest_code; + regs.pc = (u64)guest_code; vcpu_regs_set(vcpu, ®s); } diff --git a/tools/testing/selftests/kvm/lib/loongarch/ucall.c b/tools/testing/selftests/kvm/lib/loongarch/ucall.c index fc6cbb50573f..cd49a3440ead 100644 --- a/tools/testing/selftests/kvm/lib/loongarch/ucall.c +++ b/tools/testing/selftests/kvm/lib/loongarch/ucall.c @@ -9,17 +9,17 @@ * ucall_exit_mmio_addr holds per-VM values (global data is duplicated by each * VM), it must not be accessed from host code. */ -vm_vaddr_t *ucall_exit_mmio_addr; +gva_t *ucall_exit_mmio_addr; -void ucall_arch_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa) +void ucall_arch_init(struct kvm_vm *vm, gpa_t mmio_gpa) { - vm_vaddr_t mmio_gva = vm_vaddr_unused_gap(vm, vm->page_size, KVM_UTIL_MIN_VADDR); + gva_t mmio_gva = vm_unused_gva_gap(vm, vm->page_size, KVM_UTIL_MIN_VADDR); virt_map(vm, mmio_gva, mmio_gpa, 1); vm->ucall_mmio_addr = mmio_gpa; - write_guest_global(vm, ucall_exit_mmio_addr, (vm_vaddr_t *)mmio_gva); + write_guest_global(vm, ucall_exit_mmio_addr, (gva_t *)mmio_gva); } void *ucall_arch_get_ucall(struct kvm_vcpu *vcpu) @@ -28,10 +28,10 @@ void *ucall_arch_get_ucall(struct kvm_vcpu *vcpu) if (run->exit_reason == KVM_EXIT_MMIO && run->mmio.phys_addr == vcpu->vm->ucall_mmio_addr) { - TEST_ASSERT(run->mmio.is_write && run->mmio.len == sizeof(uint64_t), + TEST_ASSERT(run->mmio.is_write && run->mmio.len == sizeof(u64), "Unexpected ucall exit mmio address access"); - return (void *)(*((uint64_t *)run->mmio.data)); + return (void *)(*((u64 *)run->mmio.data)); } return NULL; diff --git a/tools/testing/selftests/kvm/lib/memstress.c b/tools/testing/selftests/kvm/lib/memstress.c index 1ea735d66e15..6dcd15910a06 100644 --- a/tools/testing/selftests/kvm/lib/memstress.c +++ b/tools/testing/selftests/kvm/lib/memstress.c @@ -16,7 +16,7 @@ struct memstress_args memstress_args; * Guest virtual memory offset of the testing memory slot. * Must not conflict with identity mapped test code. */ -static uint64_t guest_test_virt_mem = DEFAULT_GUEST_TEST_MEM; +static u64 guest_test_virt_mem = DEFAULT_GUEST_TEST_MEM; struct vcpu_thread { /* The index of the vCPU. */ @@ -44,15 +44,15 @@ static struct kvm_vcpu *vcpus[KVM_MAX_VCPUS]; * Continuously write to the first 8 bytes of each page in the * specified region. */ -void memstress_guest_code(uint32_t vcpu_idx) +void memstress_guest_code(u32 vcpu_idx) { struct memstress_args *args = &memstress_args; struct memstress_vcpu_args *vcpu_args = &args->vcpu_args[vcpu_idx]; struct guest_random_state rand_state; - uint64_t gva; - uint64_t pages; - uint64_t addr; - uint64_t page; + gva_t gva; + u64 pages; + u64 addr; + u64 page; int i; rand_state = new_guest_random_state(guest_random_seed + vcpu_idx); @@ -76,9 +76,9 @@ void memstress_guest_code(uint32_t vcpu_idx) addr = gva + (page * args->guest_page_size); if (__guest_random_bool(&rand_state, args->write_percent)) - *(uint64_t *)addr = 0x0123456789ABCDEF; + *(u64 *)addr = 0x0123456789ABCDEF; else - READ_ONCE(*(uint64_t *)addr); + READ_ONCE(*(u64 *)addr); } GUEST_SYNC(1); @@ -87,7 +87,7 @@ void memstress_guest_code(uint32_t vcpu_idx) void memstress_setup_vcpus(struct kvm_vm *vm, int nr_vcpus, struct kvm_vcpu *vcpus[], - uint64_t vcpu_memory_bytes, + u64 vcpu_memory_bytes, bool partition_vcpu_memory_access) { struct memstress_args *args = &memstress_args; @@ -122,15 +122,15 @@ void memstress_setup_vcpus(struct kvm_vm *vm, int nr_vcpus, } struct kvm_vm *memstress_create_vm(enum vm_guest_mode mode, int nr_vcpus, - uint64_t vcpu_memory_bytes, int slots, + u64 vcpu_memory_bytes, int slots, enum vm_mem_backing_src_type backing_src, bool partition_vcpu_memory_access) { struct memstress_args *args = &memstress_args; struct kvm_vm *vm; - uint64_t guest_num_pages, slot0_pages = 0; - uint64_t backing_src_pagesz = get_backing_src_pagesz(backing_src); - uint64_t region_end_gfn; + u64 guest_num_pages, slot0_pages = 0; + u64 backing_src_pagesz = get_backing_src_pagesz(backing_src); + u64 region_end_gfn; int i; pr_info("Testing guest mode: %s\n", vm_guest_mode_string(mode)); @@ -202,8 +202,8 @@ struct kvm_vm *memstress_create_vm(enum vm_guest_mode mode, int nr_vcpus, /* Add extra memory slots for testing */ for (i = 0; i < slots; i++) { - uint64_t region_pages = guest_num_pages / slots; - vm_paddr_t region_start = args->gpa + region_pages * args->guest_page_size * i; + u64 region_pages = guest_num_pages / slots; + gpa_t region_start = args->gpa + region_pages * args->guest_page_size * i; vm_userspace_mem_region_add(vm, backing_src, region_start, MEMSTRESS_MEM_SLOT_INDEX + i, @@ -232,7 +232,7 @@ void memstress_destroy_vm(struct kvm_vm *vm) kvm_vm_free(vm); } -void memstress_set_write_percent(struct kvm_vm *vm, uint32_t write_percent) +void memstress_set_write_percent(struct kvm_vm *vm, u32 write_percent) { memstress_args.write_percent = write_percent; sync_global_to_guest(vm, memstress_args.write_percent); @@ -244,7 +244,7 @@ void memstress_set_random_access(struct kvm_vm *vm, bool random_access) sync_global_to_guest(vm, memstress_args.random_access); } -uint64_t __weak memstress_nested_pages(int nr_vcpus) +u64 __weak memstress_nested_pages(int nr_vcpus) { return 0; } @@ -349,7 +349,7 @@ void memstress_get_dirty_log(struct kvm_vm *vm, unsigned long *bitmaps[], int sl } void memstress_clear_dirty_log(struct kvm_vm *vm, unsigned long *bitmaps[], - int slots, uint64_t pages_per_slot) + int slots, u64 pages_per_slot) { int i; @@ -360,7 +360,7 @@ void memstress_clear_dirty_log(struct kvm_vm *vm, unsigned long *bitmaps[], } } -unsigned long **memstress_alloc_bitmaps(int slots, uint64_t pages_per_slot) +unsigned long **memstress_alloc_bitmaps(int slots, u64 pages_per_slot) { unsigned long **bitmaps; int i; diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c index 067c6b2c15b0..ded5429f3448 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -15,9 +15,9 @@ #define DEFAULT_RISCV_GUEST_STACK_VADDR_MIN 0xac0000 -static vm_vaddr_t exception_handlers; +static gva_t exception_handlers; -bool __vcpu_has_ext(struct kvm_vcpu *vcpu, uint64_t ext) +bool __vcpu_has_ext(struct kvm_vcpu *vcpu, u64 ext) { unsigned long value = 0; int ret; @@ -27,32 +27,32 @@ bool __vcpu_has_ext(struct kvm_vcpu *vcpu, uint64_t ext) return !ret && !!value; } -static uint64_t pte_addr(struct kvm_vm *vm, uint64_t entry) +static u64 pte_addr(struct kvm_vm *vm, u64 entry) { return ((entry & PGTBL_PTE_ADDR_MASK) >> PGTBL_PTE_ADDR_SHIFT) << PGTBL_PAGE_SIZE_SHIFT; } -static uint64_t ptrs_per_pte(struct kvm_vm *vm) +static u64 ptrs_per_pte(struct kvm_vm *vm) { - return PGTBL_PAGE_SIZE / sizeof(uint64_t); + return PGTBL_PAGE_SIZE / sizeof(u64); } -static uint64_t pte_index_mask[] = { +static u64 pte_index_mask[] = { PGTBL_L0_INDEX_MASK, PGTBL_L1_INDEX_MASK, PGTBL_L2_INDEX_MASK, PGTBL_L3_INDEX_MASK, }; -static uint32_t pte_index_shift[] = { +static u32 pte_index_shift[] = { PGTBL_L0_INDEX_SHIFT, PGTBL_L1_INDEX_SHIFT, PGTBL_L2_INDEX_SHIFT, PGTBL_L3_INDEX_SHIFT, }; -static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int level) +static u64 pte_index(struct kvm_vm *vm, gva_t gva, int level) { TEST_ASSERT(level > -1, "Negative page table level (%d) not possible", level); @@ -75,26 +75,25 @@ void virt_arch_pgd_alloc(struct kvm_vm *vm) vm->mmu.pgd_created = true; } -void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr) +void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa) { - uint64_t *ptep, next_ppn; + u64 *ptep, next_ppn; int level = vm->mmu.pgtable_levels - 1; - TEST_ASSERT((vaddr % vm->page_size) == 0, + TEST_ASSERT((gva % vm->page_size) == 0, "Virtual address not on page boundary,\n" - " vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size); - TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, - (vaddr >> vm->page_shift)), - "Invalid virtual address, vaddr: 0x%lx", vaddr); - TEST_ASSERT((paddr % vm->page_size) == 0, + " gva: 0x%lx vm->page_size: 0x%x", gva, vm->page_size); + TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)), + "Invalid virtual address, gva: 0x%lx", gva); + TEST_ASSERT((gpa % vm->page_size) == 0, "Physical address not on page boundary,\n" - " paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size); - TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn, + " gpa: 0x%lx vm->page_size: 0x%x", gpa, vm->page_size); + TEST_ASSERT((gpa >> vm->page_shift) <= vm->max_gfn, "Physical address beyond maximum supported,\n" - " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", - paddr, vm->max_gfn, vm->page_size); + " gpa: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", + gpa, vm->max_gfn, vm->page_size); - ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pte_index(vm, vaddr, level) * 8; + ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pte_index(vm, gva, level) * 8; if (!*ptep) { next_ppn = vm_alloc_page_table(vm) >> PGTBL_PAGE_SIZE_SHIFT; *ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) | @@ -104,7 +103,7 @@ void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr) while (level > -1) { ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + - pte_index(vm, vaddr, level) * 8; + pte_index(vm, gva, level) * 8; if (!*ptep && level > 0) { next_ppn = vm_alloc_page_table(vm) >> PGTBL_PAGE_SIZE_SHIFT; @@ -114,14 +113,14 @@ void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr) level--; } - paddr = paddr >> PGTBL_PAGE_SIZE_SHIFT; - *ptep = (paddr << PGTBL_PTE_ADDR_SHIFT) | + gpa = gpa >> PGTBL_PAGE_SIZE_SHIFT; + *ptep = (gpa << PGTBL_PTE_ADDR_SHIFT) | PGTBL_PTE_PERM_MASK | PGTBL_PTE_VALID_MASK; } -vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) +gpa_t addr_arch_gva2gpa(struct kvm_vm *vm, gva_t gva) { - uint64_t *ptep; + u64 *ptep; int level = vm->mmu.pgtable_levels - 1; if (!vm->mmu.pgd_created) @@ -148,12 +147,12 @@ vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) exit(1); } -static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, - uint64_t page, int level) +static void pte_dump(FILE *stream, struct kvm_vm *vm, u8 indent, + u64 page, int level) { #ifdef DEBUG static const char *const type[] = { "pte", "pmd", "pud", "p4d"}; - uint64_t pte, *ptep; + u64 pte, *ptep; if (level < 0) return; @@ -170,11 +169,11 @@ static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, #endif } -void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) +void virt_arch_dump(FILE *stream, struct kvm_vm *vm, u8 indent) { struct kvm_mmu *mmu = &vm->mmu; int level = mmu->pgtable_levels - 1; - uint64_t pgd, *ptep; + u64 pgd, *ptep; if (!mmu->pgd_created) return; @@ -233,7 +232,7 @@ void riscv_vcpu_mmu_setup(struct kvm_vcpu *vcpu) vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(satp), satp); } -void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent) +void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, u8 indent) { struct kvm_riscv_core core; @@ -311,20 +310,20 @@ void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code) vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.pc), (unsigned long)guest_code); } -struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) +struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u32 vcpu_id) { int r; size_t stack_size; - unsigned long stack_vaddr; + unsigned long stack_gva; unsigned long current_gp = 0; struct kvm_mp_state mps; struct kvm_vcpu *vcpu; stack_size = vm->page_size == 4096 ? DEFAULT_STACK_PGS * vm->page_size : vm->page_size; - stack_vaddr = __vm_vaddr_alloc(vm, stack_size, - DEFAULT_RISCV_GUEST_STACK_VADDR_MIN, - MEM_REGION_DATA); + stack_gva = __vm_alloc(vm, stack_size, + DEFAULT_RISCV_GUEST_STACK_VADDR_MIN, + MEM_REGION_DATA); vcpu = __vm_vcpu_add(vm, vcpu_id); riscv_vcpu_mmu_setup(vcpu); @@ -344,7 +343,7 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.gp), current_gp); /* Setup stack pointer and program counter of guest */ - vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.sp), stack_vaddr + stack_size); + vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.sp), stack_gva + stack_size); /* Setup sscratch for guest_get_vcpuid() */ vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(sscratch), vcpu_id); @@ -358,7 +357,7 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...) { va_list ap; - uint64_t id = RISCV_CORE_REG(regs.a0); + u64 id = RISCV_CORE_REG(regs.a0); int i; TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n" @@ -393,7 +392,7 @@ void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...) id = RISCV_CORE_REG(regs.a7); break; } - vcpu_set_reg(vcpu, id, va_arg(ap, uint64_t)); + vcpu_set_reg(vcpu, id, va_arg(ap, u64)); } va_end(ap); @@ -449,10 +448,10 @@ void vcpu_init_vector_tables(struct kvm_vcpu *vcpu) void vm_init_vector_tables(struct kvm_vm *vm) { - vm->handlers = __vm_vaddr_alloc(vm, sizeof(struct handlers), - vm->page_size, MEM_REGION_DATA); + vm->handlers = __vm_alloc(vm, sizeof(struct handlers), vm->page_size, + MEM_REGION_DATA); - *(vm_vaddr_t *)addr_gva2hva(vm, (vm_vaddr_t)(&exception_handlers)) = vm->handlers; + *(gva_t *)addr_gva2hva(vm, (gva_t)(&exception_handlers)) = vm->handlers; } void vm_install_exception_handler(struct kvm_vm *vm, int vector, exception_handler_fn handler) @@ -470,7 +469,7 @@ void vm_install_interrupt_handler(struct kvm_vm *vm, exception_handler_fn handle handlers->exception_handlers[1][0] = handler; } -uint32_t guest_get_vcpuid(void) +u32 guest_get_vcpuid(void) { return csr_read(CSR_SSCRATCH); } @@ -544,10 +543,10 @@ void kvm_selftest_arch_init(void) unsigned long riscv64_get_satp_mode(void) { int kvm_fd, vm_fd, vcpu_fd, err; - uint64_t val; + u64 val; struct kvm_one_reg reg = { .id = RISCV_CONFIG_REG(satp_mode), - .addr = (uint64_t)&val, + .addr = (u64)&val, }; kvm_fd = open_kvm_dev_path_or_exit(); diff --git a/tools/testing/selftests/kvm/lib/s390/diag318_test_handler.c b/tools/testing/selftests/kvm/lib/s390/diag318_test_handler.c index 2c432fa164f1..f5480473f192 100644 --- a/tools/testing/selftests/kvm/lib/s390/diag318_test_handler.c +++ b/tools/testing/selftests/kvm/lib/s390/diag318_test_handler.c @@ -13,7 +13,7 @@ static void guest_code(void) { - uint64_t diag318_info = 0x12345678; + u64 diag318_info = 0x12345678; asm volatile ("diag %0,0,0x318\n" : : "d" (diag318_info)); } @@ -23,13 +23,13 @@ static void guest_code(void) * we create an ad-hoc VM here to handle the instruction then extract the * necessary data. It is up to the caller to decide what to do with that data. */ -static uint64_t diag318_handler(void) +static u64 diag318_handler(void) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; struct kvm_run *run; - uint64_t reg; - uint64_t diag318_info; + u64 reg; + u64 diag318_info; vm = vm_create_with_one_vcpu(&vcpu, guest_code); vcpu_run(vcpu); @@ -51,9 +51,9 @@ static uint64_t diag318_handler(void) return diag318_info; } -uint64_t get_diag318_info(void) +u64 get_diag318_info(void) { - static uint64_t diag318_info; + static u64 diag318_info; static bool printed_skip; /* diff --git a/tools/testing/selftests/kvm/lib/s390/facility.c b/tools/testing/selftests/kvm/lib/s390/facility.c index d540812d911a..9a778054f07f 100644 --- a/tools/testing/selftests/kvm/lib/s390/facility.c +++ b/tools/testing/selftests/kvm/lib/s390/facility.c @@ -10,5 +10,5 @@ #include "facility.h" -uint64_t stfl_doublewords[NB_STFL_DOUBLEWORDS]; +u64 stfl_doublewords[NB_STFL_DOUBLEWORDS]; bool stfle_flag; diff --git a/tools/testing/selftests/kvm/lib/s390/processor.c b/tools/testing/selftests/kvm/lib/s390/processor.c index 6a9a660413a7..a9adb3782b35 100644 --- a/tools/testing/selftests/kvm/lib/s390/processor.c +++ b/tools/testing/selftests/kvm/lib/s390/processor.c @@ -12,7 +12,7 @@ void virt_arch_pgd_alloc(struct kvm_vm *vm) { - vm_paddr_t paddr; + gpa_t gpa; TEST_ASSERT(vm->page_size == PAGE_SIZE, "Unsupported page size: 0x%x", vm->page_size); @@ -20,12 +20,12 @@ void virt_arch_pgd_alloc(struct kvm_vm *vm) if (vm->mmu.pgd_created) return; - paddr = vm_phy_pages_alloc(vm, PAGES_PER_REGION, + gpa = vm_phy_pages_alloc(vm, PAGES_PER_REGION, KVM_GUEST_PAGE_TABLE_MIN_PADDR, vm->memslots[MEM_REGION_PT]); - memset(addr_gpa2hva(vm, paddr), 0xff, PAGES_PER_REGION * vm->page_size); + memset(addr_gpa2hva(vm, gpa), 0xff, PAGES_PER_REGION * vm->page_size); - vm->mmu.pgd = paddr; + vm->mmu.pgd = gpa; vm->mmu.pgd_created = true; } @@ -34,9 +34,9 @@ void virt_arch_pgd_alloc(struct kvm_vm *vm) * a page table (ri == 4). Returns a suitable region/segment table entry * which points to the freshly allocated pages. */ -static uint64_t virt_alloc_region(struct kvm_vm *vm, int ri) +static u64 virt_alloc_region(struct kvm_vm *vm, int ri) { - uint64_t taddr; + u64 taddr; taddr = vm_phy_pages_alloc(vm, ri < 4 ? PAGES_PER_REGION : 1, KVM_GUEST_PAGE_TABLE_MIN_PADDR, 0); @@ -47,26 +47,24 @@ static uint64_t virt_alloc_region(struct kvm_vm *vm, int ri) | ((ri < 4 ? (PAGES_PER_REGION - 1) : 0) & REGION_ENTRY_LENGTH); } -void virt_arch_pg_map(struct kvm_vm *vm, uint64_t gva, uint64_t gpa) +void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa) { int ri, idx; - uint64_t *entry; + u64 *entry; TEST_ASSERT((gva % vm->page_size) == 0, - "Virtual address not on page boundary,\n" - " vaddr: 0x%lx vm->page_size: 0x%x", - gva, vm->page_size); - TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, - (gva >> vm->page_shift)), - "Invalid virtual address, vaddr: 0x%lx", - gva); + "Virtual address not on page boundary,\n" + " gva: 0x%lx vm->page_size: 0x%x", + gva, vm->page_size); + TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)), + "Invalid virtual address, gva: 0x%lx", gva); TEST_ASSERT((gpa % vm->page_size) == 0, "Physical address not on page boundary,\n" - " paddr: 0x%lx vm->page_size: 0x%x", + " gpa: 0x%lx vm->page_size: 0x%x", gva, vm->page_size); TEST_ASSERT((gpa >> vm->page_shift) <= vm->max_gfn, "Physical address beyond beyond maximum supported,\n" - " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", + " gpa: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", gva, vm->max_gfn, vm->page_size); /* Walk through region and segment tables */ @@ -86,10 +84,10 @@ void virt_arch_pg_map(struct kvm_vm *vm, uint64_t gva, uint64_t gpa) entry[idx] = gpa; } -vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) +gpa_t addr_arch_gva2gpa(struct kvm_vm *vm, gva_t gva) { int ri, idx; - uint64_t *entry; + u64 *entry; TEST_ASSERT(vm->page_size == PAGE_SIZE, "Unsupported page size: 0x%x", vm->page_size); @@ -111,10 +109,10 @@ vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) return (entry[idx] & ~0xffful) + (gva & 0xffful); } -static void virt_dump_ptes(FILE *stream, struct kvm_vm *vm, uint8_t indent, - uint64_t ptea_start) +static void virt_dump_ptes(FILE *stream, struct kvm_vm *vm, u8 indent, + u64 ptea_start) { - uint64_t *pte, ptea; + u64 *pte, ptea; for (ptea = ptea_start; ptea < ptea_start + 0x100 * 8; ptea += 8) { pte = addr_gpa2hva(vm, ptea); @@ -125,10 +123,10 @@ static void virt_dump_ptes(FILE *stream, struct kvm_vm *vm, uint8_t indent, } } -static void virt_dump_region(FILE *stream, struct kvm_vm *vm, uint8_t indent, - uint64_t reg_tab_addr) +static void virt_dump_region(FILE *stream, struct kvm_vm *vm, u8 indent, + u64 reg_tab_addr) { - uint64_t addr, *entry; + u64 addr, *entry; for (addr = reg_tab_addr; addr < reg_tab_addr + 0x400 * 8; addr += 8) { entry = addr_gpa2hva(vm, addr); @@ -147,7 +145,7 @@ static void virt_dump_region(FILE *stream, struct kvm_vm *vm, uint8_t indent, } } -void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) +void virt_arch_dump(FILE *stream, struct kvm_vm *vm, u8 indent) { if (!vm->mmu.pgd_created) return; @@ -160,10 +158,10 @@ void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code) vcpu->run->psw_addr = (uintptr_t)guest_code; } -struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) +struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u32 vcpu_id) { size_t stack_size = DEFAULT_STACK_PGS * getpagesize(); - uint64_t stack_vaddr; + u64 stack_gva; struct kvm_regs regs; struct kvm_sregs sregs; struct kvm_vcpu *vcpu; @@ -171,15 +169,14 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) TEST_ASSERT(vm->page_size == PAGE_SIZE, "Unsupported page size: 0x%x", vm->page_size); - stack_vaddr = __vm_vaddr_alloc(vm, stack_size, - DEFAULT_GUEST_STACK_VADDR_MIN, - MEM_REGION_DATA); + stack_gva = __vm_alloc(vm, stack_size, DEFAULT_GUEST_STACK_VADDR_MIN, + MEM_REGION_DATA); vcpu = __vm_vcpu_add(vm, vcpu_id); /* Setup guest registers */ vcpu_regs_get(vcpu, ®s); - regs.gprs[15] = stack_vaddr + (DEFAULT_STACK_PGS * getpagesize()) - 160; + regs.gprs[15] = stack_gva + (DEFAULT_STACK_PGS * getpagesize()) - 160; vcpu_regs_set(vcpu, ®s); vcpu_sregs_get(vcpu, &sregs); @@ -206,13 +203,13 @@ void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...) vcpu_regs_get(vcpu, ®s); for (i = 0; i < num; i++) - regs.gprs[i + 2] = va_arg(ap, uint64_t); + regs.gprs[i + 2] = va_arg(ap, u64); vcpu_regs_set(vcpu, ®s); va_end(ap); } -void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent) +void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, u8 indent) { fprintf(stream, "%*spstate: psw: 0x%.16llx:0x%.16llx\n", indent, "", vcpu->run->psw_mask, vcpu->run->psw_addr); diff --git a/tools/testing/selftests/kvm/lib/sparsebit.c b/tools/testing/selftests/kvm/lib/sparsebit.c index a99188f87a38..4d845000de15 100644 --- a/tools/testing/selftests/kvm/lib/sparsebit.c +++ b/tools/testing/selftests/kvm/lib/sparsebit.c @@ -76,11 +76,11 @@ * the use of a binary-search tree, where each node contains at least * the following members: * - * typedef uint64_t sparsebit_idx_t; - * typedef uint64_t sparsebit_num_t; + * typedef u64 sparsebit_idx_t; + * typedef u64 sparsebit_num_t; * * sparsebit_idx_t idx; - * uint32_t mask; + * u32 mask; * sparsebit_num_t num_after; * * The idx member contains the bit index of the first bit described by this @@ -162,7 +162,7 @@ #define DUMP_LINE_MAX 100 /* Does not include indent amount */ -typedef uint32_t mask_t; +typedef u32 mask_t; #define MASK_BITS (sizeof(mask_t) * CHAR_BIT) struct node { @@ -2056,9 +2056,9 @@ unsigned char get8(void) return ch; } -uint64_t get64(void) +u64 get64(void) { - uint64_t x; + u64 x; x = get8(); x = (x << 8) | get8(); @@ -2074,9 +2074,9 @@ int main(void) { s = sparsebit_alloc(); for (;;) { - uint8_t op = get8() & 0xf; - uint64_t first = get64(); - uint64_t last = get64(); + u8 op = get8() & 0xf; + u64 first = get64(); + u64 last = get64(); operate(op, first, last); } diff --git a/tools/testing/selftests/kvm/lib/test_util.c b/tools/testing/selftests/kvm/lib/test_util.c index 8a1848586a85..bab1bd2b775b 100644 --- a/tools/testing/selftests/kvm/lib/test_util.c +++ b/tools/testing/selftests/kvm/lib/test_util.c @@ -30,15 +30,15 @@ void __attribute__((used)) expect_sigbus_handler(int signum) * Park-Miller LCG using standard constants. */ -struct guest_random_state new_guest_random_state(uint32_t seed) +struct guest_random_state new_guest_random_state(u32 seed) { struct guest_random_state s = {.seed = seed}; return s; } -uint32_t guest_random_u32(struct guest_random_state *state) +u32 guest_random_u32(struct guest_random_state *state) { - state->seed = (uint64_t)state->seed * 48271 % ((uint32_t)(1 << 31) - 1); + state->seed = (u64)state->seed * 48271 % ((u32)(1 << 31) - 1); return state->seed; } @@ -83,12 +83,12 @@ size_t parse_size(const char *size) return base << shift; } -int64_t timespec_to_ns(struct timespec ts) +s64 timespec_to_ns(struct timespec ts) { - return (int64_t)ts.tv_nsec + 1000000000LL * (int64_t)ts.tv_sec; + return (s64)ts.tv_nsec + 1000000000LL * (s64)ts.tv_sec; } -struct timespec timespec_add_ns(struct timespec ts, int64_t ns) +struct timespec timespec_add_ns(struct timespec ts, s64 ns) { struct timespec res; @@ -101,15 +101,15 @@ struct timespec timespec_add_ns(struct timespec ts, int64_t ns) struct timespec timespec_add(struct timespec ts1, struct timespec ts2) { - int64_t ns1 = timespec_to_ns(ts1); - int64_t ns2 = timespec_to_ns(ts2); + s64 ns1 = timespec_to_ns(ts1); + s64 ns2 = timespec_to_ns(ts2); return timespec_add_ns((struct timespec){0}, ns1 + ns2); } struct timespec timespec_sub(struct timespec ts1, struct timespec ts2) { - int64_t ns1 = timespec_to_ns(ts1); - int64_t ns2 = timespec_to_ns(ts2); + s64 ns1 = timespec_to_ns(ts1); + s64 ns2 = timespec_to_ns(ts2); return timespec_add_ns((struct timespec){0}, ns1 - ns2); } @@ -123,7 +123,7 @@ struct timespec timespec_elapsed(struct timespec start) struct timespec timespec_div(struct timespec ts, int divisor) { - int64_t ns = timespec_to_ns(ts) / divisor; + s64 ns = timespec_to_ns(ts) / divisor; return timespec_add_ns((struct timespec){0}, ns); } @@ -225,7 +225,7 @@ size_t get_def_hugetlb_pagesz(void) #define ANON_FLAGS (MAP_PRIVATE | MAP_ANONYMOUS) #define ANON_HUGE_FLAGS (ANON_FLAGS | MAP_HUGETLB) -const struct vm_mem_backing_src_alias *vm_mem_backing_src_alias(uint32_t i) +const struct vm_mem_backing_src_alias *vm_mem_backing_src_alias(u32 i) { static const struct vm_mem_backing_src_alias aliases[] = { [VM_MEM_SRC_ANONYMOUS] = { @@ -317,9 +317,9 @@ const struct vm_mem_backing_src_alias *vm_mem_backing_src_alias(uint32_t i) #define MAP_HUGE_PAGE_SIZE(x) (1ULL << ((x >> MAP_HUGE_SHIFT) & MAP_HUGE_MASK)) -size_t get_backing_src_pagesz(uint32_t i) +size_t get_backing_src_pagesz(u32 i) { - uint32_t flag = vm_mem_backing_src_alias(i)->flag; + u32 flag = vm_mem_backing_src_alias(i)->flag; switch (i) { case VM_MEM_SRC_ANONYMOUS: @@ -335,7 +335,7 @@ size_t get_backing_src_pagesz(uint32_t i) } } -bool is_backing_src_hugetlb(uint32_t i) +bool is_backing_src_hugetlb(u32 i) { return !!(vm_mem_backing_src_alias(i)->flag & MAP_HUGETLB); } diff --git a/tools/testing/selftests/kvm/lib/ucall_common.c b/tools/testing/selftests/kvm/lib/ucall_common.c index 42151e571953..029ce21f9f2f 100644 --- a/tools/testing/selftests/kvm/lib/ucall_common.c +++ b/tools/testing/selftests/kvm/lib/ucall_common.c @@ -14,7 +14,7 @@ struct ucall_header { struct ucall ucalls[KVM_MAX_VCPUS]; }; -int ucall_nr_pages_required(uint64_t page_size) +int ucall_nr_pages_required(u64 page_size) { return align_up(sizeof(struct ucall_header), page_size) / page_size; } @@ -25,16 +25,16 @@ int ucall_nr_pages_required(uint64_t page_size) */ static struct ucall_header *ucall_pool; -void ucall_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa) +void ucall_init(struct kvm_vm *vm, gpa_t mmio_gpa) { struct ucall_header *hdr; struct ucall *uc; - vm_vaddr_t vaddr; + gva_t gva; int i; - vaddr = vm_vaddr_alloc_shared(vm, sizeof(*hdr), KVM_UTIL_MIN_VADDR, - MEM_REGION_DATA); - hdr = (struct ucall_header *)addr_gva2hva(vm, vaddr); + gva = vm_alloc_shared(vm, sizeof(*hdr), KVM_UTIL_MIN_VADDR, + MEM_REGION_DATA); + hdr = (struct ucall_header *)addr_gva2hva(vm, gva); memset(hdr, 0, sizeof(*hdr)); for (i = 0; i < KVM_MAX_VCPUS; ++i) { @@ -42,7 +42,7 @@ void ucall_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa) uc->hva = uc; } - write_guest_global(vm, ucall_pool, (struct ucall_header *)vaddr); + write_guest_global(vm, ucall_pool, (struct ucall_header *)gva); ucall_arch_init(vm, mmio_gpa); } @@ -79,7 +79,7 @@ static void ucall_free(struct ucall *uc) clear_bit(uc - ucall_pool->ucalls, ucall_pool->in_use); } -void ucall_assert(uint64_t cmd, const char *exp, const char *file, +void ucall_assert(u64 cmd, const char *exp, const char *file, unsigned int line, const char *fmt, ...) { struct ucall *uc; @@ -88,20 +88,20 @@ void ucall_assert(uint64_t cmd, const char *exp, const char *file, uc = ucall_alloc(); uc->cmd = cmd; - WRITE_ONCE(uc->args[GUEST_ERROR_STRING], (uint64_t)(exp)); - WRITE_ONCE(uc->args[GUEST_FILE], (uint64_t)(file)); + WRITE_ONCE(uc->args[GUEST_ERROR_STRING], (u64)(exp)); + WRITE_ONCE(uc->args[GUEST_FILE], (u64)(file)); WRITE_ONCE(uc->args[GUEST_LINE], line); va_start(va, fmt); guest_vsnprintf(uc->buffer, UCALL_BUFFER_LEN, fmt, va); va_end(va); - ucall_arch_do_ucall((vm_vaddr_t)uc->hva); + ucall_arch_do_ucall((gva_t)uc->hva); ucall_free(uc); } -void ucall_fmt(uint64_t cmd, const char *fmt, ...) +void ucall_fmt(u64 cmd, const char *fmt, ...) { struct ucall *uc; va_list va; @@ -113,12 +113,12 @@ void ucall_fmt(uint64_t cmd, const char *fmt, ...) guest_vsnprintf(uc->buffer, UCALL_BUFFER_LEN, fmt, va); va_end(va); - ucall_arch_do_ucall((vm_vaddr_t)uc->hva); + ucall_arch_do_ucall((gva_t)uc->hva); ucall_free(uc); } -void ucall(uint64_t cmd, int nargs, ...) +void ucall(u64 cmd, int nargs, ...) { struct ucall *uc; va_list va; @@ -132,15 +132,15 @@ void ucall(uint64_t cmd, int nargs, ...) va_start(va, nargs); for (i = 0; i < nargs; ++i) - WRITE_ONCE(uc->args[i], va_arg(va, uint64_t)); + WRITE_ONCE(uc->args[i], va_arg(va, u64)); va_end(va); - ucall_arch_do_ucall((vm_vaddr_t)uc->hva); + ucall_arch_do_ucall((gva_t)uc->hva); ucall_free(uc); } -uint64_t get_ucall(struct kvm_vcpu *vcpu, struct ucall *uc) +u64 get_ucall(struct kvm_vcpu *vcpu, struct ucall *uc) { struct ucall ucall; void *addr; diff --git a/tools/testing/selftests/kvm/lib/userfaultfd_util.c b/tools/testing/selftests/kvm/lib/userfaultfd_util.c index 5bde176cedd5..ef8d76f71f83 100644 --- a/tools/testing/selftests/kvm/lib/userfaultfd_util.c +++ b/tools/testing/selftests/kvm/lib/userfaultfd_util.c @@ -27,7 +27,7 @@ static void *uffd_handler_thread_fn(void *arg) { struct uffd_reader_args *reader_args = (struct uffd_reader_args *)arg; int uffd = reader_args->uffd; - int64_t pages = 0; + s64 pages = 0; struct timespec start; struct timespec ts_diff; struct epoll_event evt; @@ -100,8 +100,8 @@ static void *uffd_handler_thread_fn(void *arg) } struct uffd_desc *uffd_setup_demand_paging(int uffd_mode, useconds_t delay, - void *hva, uint64_t len, - uint64_t num_readers, + void *hva, u64 len, + u64 num_readers, uffd_handler_t handler) { struct uffd_desc *uffd_desc; @@ -109,7 +109,7 @@ struct uffd_desc *uffd_setup_demand_paging(int uffd_mode, useconds_t delay, int uffd; struct uffdio_api uffdio_api; struct uffdio_register uffdio_register; - uint64_t expected_ioctls = ((uint64_t) 1) << _UFFDIO_COPY; + u64 expected_ioctls = ((u64)1) << _UFFDIO_COPY; int ret, i; PER_PAGE_DEBUG("Userfaultfd %s mode, faults resolved with %s\n", @@ -132,7 +132,7 @@ struct uffd_desc *uffd_setup_demand_paging(int uffd_mode, useconds_t delay, /* In order to get minor faults, prefault via the alias. */ if (is_minor) - expected_ioctls = ((uint64_t) 1) << _UFFDIO_CONTINUE; + expected_ioctls = ((u64)1) << _UFFDIO_CONTINUE; uffd = syscall(__NR_userfaultfd, O_CLOEXEC | O_NONBLOCK); TEST_ASSERT(uffd >= 0, "uffd creation failed, errno: %d", errno); @@ -141,9 +141,9 @@ struct uffd_desc *uffd_setup_demand_paging(int uffd_mode, useconds_t delay, uffdio_api.features = 0; TEST_ASSERT(ioctl(uffd, UFFDIO_API, &uffdio_api) != -1, "ioctl UFFDIO_API failed: %" PRIu64, - (uint64_t)uffdio_api.api); + (u64)uffdio_api.api); - uffdio_register.range.start = (uint64_t)hva; + uffdio_register.range.start = (u64)hva; uffdio_register.range.len = len; uffdio_register.mode = uffd_mode; TEST_ASSERT(ioctl(uffd, UFFDIO_REGISTER, &uffdio_register) != -1, diff --git a/tools/testing/selftests/kvm/lib/x86/apic.c b/tools/testing/selftests/kvm/lib/x86/apic.c index 89153a333e83..5182fd0d6a76 100644 --- a/tools/testing/selftests/kvm/lib/x86/apic.c +++ b/tools/testing/selftests/kvm/lib/x86/apic.c @@ -14,7 +14,7 @@ void apic_disable(void) void xapic_enable(void) { - uint64_t val = rdmsr(MSR_IA32_APICBASE); + u64 val = rdmsr(MSR_IA32_APICBASE); /* Per SDM: to enable xAPIC when in x2APIC must first disable APIC */ if (val & MSR_IA32_APICBASE_EXTD) { diff --git a/tools/testing/selftests/kvm/lib/x86/hyperv.c b/tools/testing/selftests/kvm/lib/x86/hyperv.c index 15bc8cd583aa..d200c5c26e2e 100644 --- a/tools/testing/selftests/kvm/lib/x86/hyperv.c +++ b/tools/testing/selftests/kvm/lib/x86/hyperv.c @@ -76,23 +76,23 @@ bool kvm_hv_cpu_has(struct kvm_x86_cpu_feature feature) } struct hyperv_test_pages *vcpu_alloc_hyperv_test_pages(struct kvm_vm *vm, - vm_vaddr_t *p_hv_pages_gva) + gva_t *p_hv_pages_gva) { - vm_vaddr_t hv_pages_gva = vm_vaddr_alloc_page(vm); + gva_t hv_pages_gva = vm_alloc_page(vm); struct hyperv_test_pages *hv = addr_gva2hva(vm, hv_pages_gva); /* Setup of a region of guest memory for the VP Assist page. */ - hv->vp_assist = (void *)vm_vaddr_alloc_page(vm); + hv->vp_assist = (void *)vm_alloc_page(vm); hv->vp_assist_hva = addr_gva2hva(vm, (uintptr_t)hv->vp_assist); hv->vp_assist_gpa = addr_gva2gpa(vm, (uintptr_t)hv->vp_assist); /* Setup of a region of guest memory for the partition assist page. */ - hv->partition_assist = (void *)vm_vaddr_alloc_page(vm); + hv->partition_assist = (void *)vm_alloc_page(vm); hv->partition_assist_hva = addr_gva2hva(vm, (uintptr_t)hv->partition_assist); hv->partition_assist_gpa = addr_gva2gpa(vm, (uintptr_t)hv->partition_assist); /* Setup of a region of guest memory for the enlightened VMCS. */ - hv->enlightened_vmcs = (void *)vm_vaddr_alloc_page(vm); + hv->enlightened_vmcs = (void *)vm_alloc_page(vm); hv->enlightened_vmcs_hva = addr_gva2hva(vm, (uintptr_t)hv->enlightened_vmcs); hv->enlightened_vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)hv->enlightened_vmcs); @@ -100,9 +100,9 @@ struct hyperv_test_pages *vcpu_alloc_hyperv_test_pages(struct kvm_vm *vm, return hv; } -int enable_vp_assist(uint64_t vp_assist_pa, void *vp_assist) +int enable_vp_assist(u64 vp_assist_pa, void *vp_assist) { - uint64_t val = (vp_assist_pa & HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK) | + u64 val = (vp_assist_pa & HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK) | HV_X64_MSR_VP_ASSIST_PAGE_ENABLE; wrmsr(HV_X64_MSR_VP_ASSIST_PAGE, val); diff --git a/tools/testing/selftests/kvm/lib/x86/memstress.c b/tools/testing/selftests/kvm/lib/x86/memstress.c index f53414ba7103..61cf952cd2dc 100644 --- a/tools/testing/selftests/kvm/lib/x86/memstress.c +++ b/tools/testing/selftests/kvm/lib/x86/memstress.c @@ -16,7 +16,7 @@ #include "svm_util.h" #include "vmx.h" -void memstress_l2_guest_code(uint64_t vcpu_id) +void memstress_l2_guest_code(u64 vcpu_id) { memstress_guest_code(vcpu_id); vmcall(); @@ -32,7 +32,7 @@ __asm__( #define L2_GUEST_STACK_SIZE 64 -static void l1_vmx_code(struct vmx_pages *vmx, uint64_t vcpu_id) +static void l1_vmx_code(struct vmx_pages *vmx, u64 vcpu_id) { unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE]; unsigned long *rsp; @@ -51,7 +51,7 @@ static void l1_vmx_code(struct vmx_pages *vmx, uint64_t vcpu_id) GUEST_DONE(); } -static void l1_svm_code(struct svm_test_data *svm, uint64_t vcpu_id) +static void l1_svm_code(struct svm_test_data *svm, u64 vcpu_id) { unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE]; unsigned long *rsp; @@ -67,7 +67,7 @@ static void l1_svm_code(struct svm_test_data *svm, uint64_t vcpu_id) } -static void memstress_l1_guest_code(void *data, uint64_t vcpu_id) +static void memstress_l1_guest_code(void *data, u64 vcpu_id) { if (this_cpu_has(X86_FEATURE_VMX)) l1_vmx_code(data, vcpu_id); @@ -75,7 +75,7 @@ static void memstress_l1_guest_code(void *data, uint64_t vcpu_id) l1_svm_code(data, vcpu_id); } -uint64_t memstress_nested_pages(int nr_vcpus) +u64 memstress_nested_pages(int nr_vcpus) { /* * 513 page tables is enough to identity-map 256 TiB of L2 with 1G @@ -87,7 +87,7 @@ uint64_t memstress_nested_pages(int nr_vcpus) static void memstress_setup_ept_mappings(struct kvm_vm *vm) { - uint64_t start, end; + u64 start, end; /* * Identity map the first 4G and the test region with 1G pages so that @@ -104,7 +104,7 @@ static void memstress_setup_ept_mappings(struct kvm_vm *vm) void memstress_setup_nested(struct kvm_vm *vm, int nr_vcpus, struct kvm_vcpu *vcpus[]) { struct kvm_regs regs; - vm_vaddr_t nested_gva; + gva_t nested_gva; int vcpu_id; TEST_REQUIRE(kvm_cpu_has_tdp()); diff --git a/tools/testing/selftests/kvm/lib/x86/pmu.c b/tools/testing/selftests/kvm/lib/x86/pmu.c index 34cb57d1d671..0851b74b4e46 100644 --- a/tools/testing/selftests/kvm/lib/x86/pmu.c +++ b/tools/testing/selftests/kvm/lib/x86/pmu.c @@ -11,7 +11,7 @@ #include "processor.h" #include "pmu.h" -const uint64_t intel_pmu_arch_events[] = { +const u64 intel_pmu_arch_events[] = { INTEL_ARCH_CPU_CYCLES, INTEL_ARCH_INSTRUCTIONS_RETIRED, INTEL_ARCH_REFERENCE_CYCLES, @@ -28,7 +28,7 @@ const uint64_t intel_pmu_arch_events[] = { }; kvm_static_assert(ARRAY_SIZE(intel_pmu_arch_events) == NR_INTEL_ARCH_EVENTS); -const uint64_t amd_pmu_zen_events[] = { +const u64 amd_pmu_zen_events[] = { AMD_ZEN_CORE_CYCLES, AMD_ZEN_INSTRUCTIONS_RETIRED, AMD_ZEN_BRANCHES_RETIRED, @@ -50,7 +50,7 @@ kvm_static_assert(ARRAY_SIZE(amd_pmu_zen_events) == NR_AMD_ZEN_EVENTS); * be overcounted on these certain instructions, but for Clearwater Forest * only "Instruction Retired" event is overcounted on these instructions. */ -static uint64_t get_pmu_errata(void) +static u64 get_pmu_errata(void) { if (!this_cpu_is_intel()) return 0; @@ -72,7 +72,7 @@ static uint64_t get_pmu_errata(void) } } -uint64_t pmu_errata_mask; +u64 pmu_errata_mask; void kvm_init_pmu_errata(void) { diff --git a/tools/testing/selftests/kvm/lib/x86/processor.c b/tools/testing/selftests/kvm/lib/x86/processor.c index 01f0f97d4430..b51467d70f6e 100644 --- a/tools/testing/selftests/kvm/lib/x86/processor.c +++ b/tools/testing/selftests/kvm/lib/x86/processor.c @@ -21,13 +21,13 @@ #define KERNEL_DS 0x10 #define KERNEL_TSS 0x18 -vm_vaddr_t exception_handlers; +gva_t exception_handlers; bool host_cpu_is_amd; bool host_cpu_is_intel; bool host_cpu_is_hygon; bool host_cpu_is_amd_compatible; bool is_forced_emulation_enabled; -uint64_t guest_tsc_khz; +u64 guest_tsc_khz; const char *ex_str(int vector) { @@ -62,7 +62,7 @@ const char *ex_str(int vector) } } -static void regs_dump(FILE *stream, struct kvm_regs *regs, uint8_t indent) +static void regs_dump(FILE *stream, struct kvm_regs *regs, u8 indent) { fprintf(stream, "%*srax: 0x%.16llx rbx: 0x%.16llx " "rcx: 0x%.16llx rdx: 0x%.16llx\n", @@ -86,7 +86,7 @@ static void regs_dump(FILE *stream, struct kvm_regs *regs, uint8_t indent) } static void segment_dump(FILE *stream, struct kvm_segment *segment, - uint8_t indent) + u8 indent) { fprintf(stream, "%*sbase: 0x%.16llx limit: 0x%.8x " "selector: 0x%.4x type: 0x%.2x\n", @@ -103,7 +103,7 @@ static void segment_dump(FILE *stream, struct kvm_segment *segment, } static void dtable_dump(FILE *stream, struct kvm_dtable *dtable, - uint8_t indent) + u8 indent) { fprintf(stream, "%*sbase: 0x%.16llx limit: 0x%.4x " "padding: 0x%.4x 0x%.4x 0x%.4x\n", @@ -111,7 +111,7 @@ static void dtable_dump(FILE *stream, struct kvm_dtable *dtable, dtable->padding[0], dtable->padding[1], dtable->padding[2]); } -static void sregs_dump(FILE *stream, struct kvm_sregs *sregs, uint8_t indent) +static void sregs_dump(FILE *stream, struct kvm_sregs *sregs, u8 indent) { unsigned int i; @@ -207,37 +207,37 @@ void tdp_mmu_init(struct kvm_vm *vm, int pgtable_levels, } static void *virt_get_pte(struct kvm_vm *vm, struct kvm_mmu *mmu, - uint64_t *parent_pte, uint64_t vaddr, int level) + u64 *parent_pte, gva_t gva, int level) { - uint64_t pt_gpa = PTE_GET_PA(*parent_pte); - uint64_t *page_table = addr_gpa2hva(vm, pt_gpa); - int index = (vaddr >> PG_LEVEL_SHIFT(level)) & 0x1ffu; + u64 pt_gpa = PTE_GET_PA(*parent_pte); + u64 *page_table = addr_gpa2hva(vm, pt_gpa); + int index = (gva >> PG_LEVEL_SHIFT(level)) & 0x1ffu; TEST_ASSERT((*parent_pte == mmu->pgd) || is_present_pte(mmu, parent_pte), "Parent PTE (level %d) not PRESENT for gva: 0x%08lx", - level + 1, vaddr); + level + 1, gva); return &page_table[index]; } -static uint64_t *virt_create_upper_pte(struct kvm_vm *vm, - struct kvm_mmu *mmu, - uint64_t *parent_pte, - uint64_t vaddr, - uint64_t paddr, - int current_level, - int target_level) +static u64 *virt_create_upper_pte(struct kvm_vm *vm, + struct kvm_mmu *mmu, + u64 *parent_pte, + gva_t gva, + gpa_t gpa, + int current_level, + int target_level) { - uint64_t *pte = virt_get_pte(vm, mmu, parent_pte, vaddr, current_level); + u64 *pte = virt_get_pte(vm, mmu, parent_pte, gva, current_level); - paddr = vm_untag_gpa(vm, paddr); + gpa = vm_untag_gpa(vm, gpa); if (!is_present_pte(mmu, pte)) { *pte = PTE_PRESENT_MASK(mmu) | PTE_READABLE_MASK(mmu) | PTE_WRITABLE_MASK(mmu) | PTE_EXECUTABLE_MASK(mmu) | PTE_ALWAYS_SET_MASK(mmu); if (current_level == target_level) - *pte |= PTE_HUGE_MASK(mmu) | (paddr & PHYSICAL_PAGE_MASK); + *pte |= PTE_HUGE_MASK(mmu) | (gpa & PHYSICAL_PAGE_MASK); else *pte |= vm_alloc_page_table(vm) & PHYSICAL_PAGE_MASK; } else { @@ -247,39 +247,39 @@ static uint64_t *virt_create_upper_pte(struct kvm_vm *vm, * this level. */ TEST_ASSERT(current_level != target_level, - "Cannot create hugepage at level: %u, vaddr: 0x%lx", - current_level, vaddr); + "Cannot create hugepage at level: %u, gva: 0x%lx", + current_level, gva); TEST_ASSERT(!is_huge_pte(mmu, pte), - "Cannot create page table at level: %u, vaddr: 0x%lx", - current_level, vaddr); + "Cannot create page table at level: %u, gva: 0x%lx", + current_level, gva); } return pte; } -void __virt_pg_map(struct kvm_vm *vm, struct kvm_mmu *mmu, uint64_t vaddr, - uint64_t paddr, int level) +void __virt_pg_map(struct kvm_vm *vm, struct kvm_mmu *mmu, gva_t gva, + gpa_t gpa, int level) { - const uint64_t pg_size = PG_LEVEL_SIZE(level); - uint64_t *pte = &mmu->pgd; + const u64 pg_size = PG_LEVEL_SIZE(level); + u64 *pte = &mmu->pgd; int current_level; TEST_ASSERT(vm->mode == VM_MODE_PXXVYY_4K, "Unknown or unsupported guest mode: 0x%x", vm->mode); - TEST_ASSERT((vaddr % pg_size) == 0, + TEST_ASSERT((gva % pg_size) == 0, "Virtual address not aligned,\n" - "vaddr: 0x%lx page size: 0x%lx", vaddr, pg_size); - TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (vaddr >> vm->page_shift)), - "Invalid virtual address, vaddr: 0x%lx", vaddr); - TEST_ASSERT((paddr % pg_size) == 0, + "gva: 0x%lx page size: 0x%lx", gva, pg_size); + TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)), + "Invalid virtual address, gva: 0x%lx", gva); + TEST_ASSERT((gpa % pg_size) == 0, "Physical address not aligned,\n" - " paddr: 0x%lx page size: 0x%lx", paddr, pg_size); - TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn, + " gpa: 0x%lx page size: 0x%lx", gpa, pg_size); + TEST_ASSERT((gpa >> vm->page_shift) <= vm->max_gfn, "Physical address beyond maximum supported,\n" - " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", - paddr, vm->max_gfn, vm->page_size); - TEST_ASSERT(vm_untag_gpa(vm, paddr) == paddr, - "Unexpected bits in paddr: %lx", paddr); + " gpa: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", + gpa, vm->max_gfn, vm->page_size); + TEST_ASSERT(vm_untag_gpa(vm, gpa) == gpa, + "Unexpected bits in gpa: %lx", gpa); TEST_ASSERT(!PTE_EXECUTABLE_MASK(mmu) || !PTE_NX_MASK(mmu), "X and NX bit masks cannot be used simultaneously"); @@ -291,40 +291,40 @@ void __virt_pg_map(struct kvm_vm *vm, struct kvm_mmu *mmu, uint64_t vaddr, for (current_level = mmu->pgtable_levels; current_level > PG_LEVEL_4K; current_level--) { - pte = virt_create_upper_pte(vm, mmu, pte, vaddr, paddr, + pte = virt_create_upper_pte(vm, mmu, pte, gva, gpa, current_level, level); if (is_huge_pte(mmu, pte)) return; } /* Fill in page table entry. */ - pte = virt_get_pte(vm, mmu, pte, vaddr, PG_LEVEL_4K); + pte = virt_get_pte(vm, mmu, pte, gva, PG_LEVEL_4K); TEST_ASSERT(!is_present_pte(mmu, pte), - "PTE already present for 4k page at vaddr: 0x%lx", vaddr); + "PTE already present for 4k page at gva: 0x%lx", gva); *pte = PTE_PRESENT_MASK(mmu) | PTE_READABLE_MASK(mmu) | PTE_WRITABLE_MASK(mmu) | PTE_EXECUTABLE_MASK(mmu) | - PTE_ALWAYS_SET_MASK(mmu) | (paddr & PHYSICAL_PAGE_MASK); + PTE_ALWAYS_SET_MASK(mmu) | (gpa & PHYSICAL_PAGE_MASK); /* * Neither SEV nor TDX supports shared page tables, so only the final * leaf PTE needs manually set the C/S-bit. */ - if (vm_is_gpa_protected(vm, paddr)) + if (vm_is_gpa_protected(vm, gpa)) *pte |= PTE_C_BIT_MASK(mmu); else *pte |= PTE_S_BIT_MASK(mmu); } -void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr) +void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa) { - __virt_pg_map(vm, &vm->mmu, vaddr, paddr, PG_LEVEL_4K); + __virt_pg_map(vm, &vm->mmu, gva, gpa, PG_LEVEL_4K); } -void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, - uint64_t nr_bytes, int level) +void virt_map_level(struct kvm_vm *vm, gva_t gva, gpa_t gpa, + u64 nr_bytes, int level) { - uint64_t pg_size = PG_LEVEL_SIZE(level); - uint64_t nr_pages = nr_bytes / pg_size; + u64 pg_size = PG_LEVEL_SIZE(level); + u64 nr_pages = nr_bytes / pg_size; int i; TEST_ASSERT(nr_bytes % pg_size == 0, @@ -332,16 +332,16 @@ void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, nr_bytes, pg_size); for (i = 0; i < nr_pages; i++) { - __virt_pg_map(vm, &vm->mmu, vaddr, paddr, level); - sparsebit_set_num(vm->vpages_mapped, vaddr >> vm->page_shift, + __virt_pg_map(vm, &vm->mmu, gva, gpa, level); + sparsebit_set_num(vm->vpages_mapped, gva >> vm->page_shift, nr_bytes / PAGE_SIZE); - vaddr += pg_size; - paddr += pg_size; + gva += pg_size; + gpa += pg_size; } } -static bool vm_is_target_pte(struct kvm_mmu *mmu, uint64_t *pte, +static bool vm_is_target_pte(struct kvm_mmu *mmu, u64 *pte, int *level, int current_level) { if (is_huge_pte(mmu, pte)) { @@ -354,13 +354,13 @@ static bool vm_is_target_pte(struct kvm_mmu *mmu, uint64_t *pte, return *level == current_level; } -static uint64_t *__vm_get_page_table_entry(struct kvm_vm *vm, - struct kvm_mmu *mmu, - uint64_t vaddr, - int *level) +static u64 *__vm_get_page_table_entry(struct kvm_vm *vm, + struct kvm_mmu *mmu, + gva_t gva, + int *level) { int va_width = 12 + (mmu->pgtable_levels) * 9; - uint64_t *pte = &mmu->pgd; + u64 *pte = &mmu->pgd; int current_level; TEST_ASSERT(!vm->arch.is_pt_protected, @@ -371,49 +371,46 @@ static uint64_t *__vm_get_page_table_entry(struct kvm_vm *vm, TEST_ASSERT(vm->mode == VM_MODE_PXXVYY_4K, "Unknown or unsupported guest mode: 0x%x", vm->mode); - TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, - (vaddr >> vm->page_shift)), - "Invalid virtual address, vaddr: 0x%lx", - vaddr); + TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)), + "Invalid virtual address, gva: 0x%lx", gva); /* - * Check that the vaddr is a sign-extended va_width value. + * Check that the gva is a sign-extended va_width value. */ - TEST_ASSERT(vaddr == - (((int64_t)vaddr << (64 - va_width) >> (64 - va_width))), + TEST_ASSERT(gva == (((s64)gva << (64 - va_width) >> (64 - va_width))), "Canonical check failed. The virtual address is invalid."); for (current_level = mmu->pgtable_levels; current_level > PG_LEVEL_4K; current_level--) { - pte = virt_get_pte(vm, mmu, pte, vaddr, current_level); + pte = virt_get_pte(vm, mmu, pte, gva, current_level); if (vm_is_target_pte(mmu, pte, level, current_level)) return pte; } - return virt_get_pte(vm, mmu, pte, vaddr, PG_LEVEL_4K); + return virt_get_pte(vm, mmu, pte, gva, PG_LEVEL_4K); } -uint64_t *tdp_get_pte(struct kvm_vm *vm, uint64_t l2_gpa) +u64 *tdp_get_pte(struct kvm_vm *vm, u64 l2_gpa) { int level = PG_LEVEL_4K; return __vm_get_page_table_entry(vm, &vm->stage2_mmu, l2_gpa, &level); } -uint64_t *vm_get_pte(struct kvm_vm *vm, uint64_t vaddr) +u64 *vm_get_pte(struct kvm_vm *vm, gva_t gva) { int level = PG_LEVEL_4K; - return __vm_get_page_table_entry(vm, &vm->mmu, vaddr, &level); + return __vm_get_page_table_entry(vm, &vm->mmu, gva, &level); } -void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) +void virt_arch_dump(FILE *stream, struct kvm_vm *vm, u8 indent) { struct kvm_mmu *mmu = &vm->mmu; - uint64_t *pml4e, *pml4e_start; - uint64_t *pdpe, *pdpe_start; - uint64_t *pde, *pde_start; - uint64_t *pte, *pte_start; + u64 *pml4e, *pml4e_start; + u64 *pdpe, *pdpe_start; + u64 *pde, *pde_start; + u64 *pte, *pte_start; if (!mmu->pgd_created) return; @@ -423,8 +420,8 @@ void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) fprintf(stream, "%*s index hvaddr gpaddr " "addr w exec dirty\n", indent, ""); - pml4e_start = (uint64_t *) addr_gpa2hva(vm, mmu->pgd); - for (uint16_t n1 = 0; n1 <= 0x1ffu; n1++) { + pml4e_start = (u64 *)addr_gpa2hva(vm, mmu->pgd); + for (u16 n1 = 0; n1 <= 0x1ffu; n1++) { pml4e = &pml4e_start[n1]; if (!is_present_pte(mmu, pml4e)) continue; @@ -436,7 +433,7 @@ void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) is_writable_pte(mmu, pml4e), is_nx_pte(mmu, pml4e)); pdpe_start = addr_gpa2hva(vm, *pml4e & PHYSICAL_PAGE_MASK); - for (uint16_t n2 = 0; n2 <= 0x1ffu; n2++) { + for (u16 n2 = 0; n2 <= 0x1ffu; n2++) { pdpe = &pdpe_start[n2]; if (!is_present_pte(mmu, pdpe)) continue; @@ -449,7 +446,7 @@ void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) is_nx_pte(mmu, pdpe)); pde_start = addr_gpa2hva(vm, *pdpe & PHYSICAL_PAGE_MASK); - for (uint16_t n3 = 0; n3 <= 0x1ffu; n3++) { + for (u16 n3 = 0; n3 <= 0x1ffu; n3++) { pde = &pde_start[n3]; if (!is_present_pte(mmu, pde)) continue; @@ -461,7 +458,7 @@ void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) is_nx_pte(mmu, pde)); pte_start = addr_gpa2hva(vm, *pde & PHYSICAL_PAGE_MASK); - for (uint16_t n4 = 0; n4 <= 0x1ffu; n4++) { + for (u16 n4 = 0; n4 <= 0x1ffu; n4++) { pte = &pte_start[n4]; if (!is_present_pte(mmu, pte)) continue; @@ -475,10 +472,10 @@ void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) is_writable_pte(mmu, pte), is_nx_pte(mmu, pte), is_dirty_pte(mmu, pte), - ((uint64_t) n1 << 27) - | ((uint64_t) n2 << 18) - | ((uint64_t) n3 << 9) - | ((uint64_t) n4)); + ((u64)n1 << 27) + | ((u64)n2 << 18) + | ((u64)n3 << 9) + | ((u64)n4)); } } } @@ -498,26 +495,24 @@ bool kvm_cpu_has_tdp(void) return kvm_cpu_has_ept() || kvm_cpu_has_npt(); } -void __tdp_map(struct kvm_vm *vm, uint64_t nested_paddr, uint64_t paddr, - uint64_t size, int level) +void __tdp_map(struct kvm_vm *vm, gpa_t l2_gpa, gpa_t gpa, u64 size, int level) { size_t page_size = PG_LEVEL_SIZE(level); size_t npages = size / page_size; - TEST_ASSERT(nested_paddr + size > nested_paddr, "Vaddr overflow"); - TEST_ASSERT(paddr + size > paddr, "Paddr overflow"); + TEST_ASSERT(l2_gpa + size > l2_gpa, "L2 GPA overflow"); + TEST_ASSERT(gpa + size > gpa, "GPA overflow"); while (npages--) { - __virt_pg_map(vm, &vm->stage2_mmu, nested_paddr, paddr, level); - nested_paddr += page_size; - paddr += page_size; + __virt_pg_map(vm, &vm->stage2_mmu, l2_gpa, gpa, level); + l2_gpa += page_size; + gpa += page_size; } } -void tdp_map(struct kvm_vm *vm, uint64_t nested_paddr, uint64_t paddr, - uint64_t size) +void tdp_map(struct kvm_vm *vm, gpa_t l2_gpa, gpa_t gpa, u64 size) { - __tdp_map(vm, nested_paddr, paddr, size, PG_LEVEL_4K); + __tdp_map(vm, l2_gpa, gpa, size, PG_LEVEL_4K); } /* Prepare an identity extended page table that maps all the @@ -525,7 +520,7 @@ void tdp_map(struct kvm_vm *vm, uint64_t nested_paddr, uint64_t paddr, */ void tdp_identity_map_default_memslots(struct kvm_vm *vm) { - uint32_t s, memslot = 0; + u32 s, memslot = 0; sparsebit_idx_t i, last; struct userspace_mem_region *region = memslot2region(vm, memslot); @@ -540,13 +535,13 @@ void tdp_identity_map_default_memslots(struct kvm_vm *vm) if (i > last) break; - tdp_map(vm, (uint64_t)i << vm->page_shift, - (uint64_t)i << vm->page_shift, 1 << vm->page_shift); + tdp_map(vm, (u64)i << vm->page_shift, + (u64)i << vm->page_shift, 1 << vm->page_shift); } } /* Identity map a region with 1GiB Pages. */ -void tdp_identity_map_1g(struct kvm_vm *vm, uint64_t addr, uint64_t size) +void tdp_identity_map_1g(struct kvm_vm *vm, u64 addr, u64 size) { __tdp_map(vm, addr, addr, size, PG_LEVEL_1G); } @@ -618,10 +613,10 @@ static void kvm_seg_set_kernel_data_64bit(struct kvm_segment *segp) segp->present = true; } -vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) +gpa_t addr_arch_gva2gpa(struct kvm_vm *vm, gva_t gva) { int level = PG_LEVEL_NONE; - uint64_t *pte = __vm_get_page_table_entry(vm, &vm->mmu, gva, &level); + u64 *pte = __vm_get_page_table_entry(vm, &vm->mmu, gva, &level); TEST_ASSERT(is_present_pte(&vm->mmu, pte), "Leaf PTE not PRESENT for gva: 0x%08lx", gva); @@ -633,7 +628,7 @@ vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) return vm_untag_gpa(vm, PTE_GET_PA(*pte)) | (gva & ~HUGEPAGE_MASK(level)); } -static void kvm_seg_set_tss_64bit(vm_vaddr_t base, struct kvm_segment *segp) +static void kvm_seg_set_tss_64bit(gva_t base, struct kvm_segment *segp) { memset(segp, 0, sizeof(*segp)); segp->base = base; @@ -746,16 +741,16 @@ static void vm_init_descriptor_tables(struct kvm_vm *vm) struct kvm_segment seg; int i; - vm->arch.gdt = __vm_vaddr_alloc_page(vm, MEM_REGION_DATA); - vm->arch.idt = __vm_vaddr_alloc_page(vm, MEM_REGION_DATA); - vm->handlers = __vm_vaddr_alloc_page(vm, MEM_REGION_DATA); - vm->arch.tss = __vm_vaddr_alloc_page(vm, MEM_REGION_DATA); + vm->arch.gdt = __vm_alloc_page(vm, MEM_REGION_DATA); + vm->arch.idt = __vm_alloc_page(vm, MEM_REGION_DATA); + vm->handlers = __vm_alloc_page(vm, MEM_REGION_DATA); + vm->arch.tss = __vm_alloc_page(vm, MEM_REGION_DATA); /* Handlers have the same address in both address spaces.*/ for (i = 0; i < NUM_INTERRUPTS; i++) set_idt_entry(vm, i, (unsigned long)(&idt_handlers)[i], 0, KERNEL_CS); - *(vm_vaddr_t *)addr_gva2hva(vm, (vm_vaddr_t)(&exception_handlers)) = vm->handlers; + *(gva_t *)addr_gva2hva(vm, (gva_t)(&exception_handlers)) = vm->handlers; kvm_seg_set_kernel_code_64bit(&seg); kvm_seg_fill_gdt_64bit(vm, &seg); @@ -770,9 +765,9 @@ static void vm_init_descriptor_tables(struct kvm_vm *vm) void vm_install_exception_handler(struct kvm_vm *vm, int vector, void (*handler)(struct ex_regs *)) { - vm_vaddr_t *handlers = (vm_vaddr_t *)addr_gva2hva(vm, vm->handlers); + gva_t *handlers = (gva_t *)addr_gva2hva(vm, vm->handlers); - handlers[vector] = (vm_vaddr_t)handler; + handlers[vector] = (gva_t)handler; } void assert_on_unhandled_exception(struct kvm_vcpu *vcpu) @@ -821,18 +816,17 @@ void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code) vcpu_regs_set(vcpu, ®s); } -struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) +struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u32 vcpu_id) { struct kvm_mp_state mp_state; struct kvm_regs regs; - vm_vaddr_t stack_vaddr; + gva_t stack_gva; struct kvm_vcpu *vcpu; - stack_vaddr = __vm_vaddr_alloc(vm, DEFAULT_STACK_PGS * getpagesize(), - DEFAULT_GUEST_STACK_VADDR_MIN, - MEM_REGION_DATA); + stack_gva = __vm_alloc(vm, DEFAULT_STACK_PGS * getpagesize(), + DEFAULT_GUEST_STACK_VADDR_MIN, MEM_REGION_DATA); - stack_vaddr += DEFAULT_STACK_PGS * getpagesize(); + stack_gva += DEFAULT_STACK_PGS * getpagesize(); /* * Align stack to match calling sequence requirements in section "The @@ -843,9 +837,9 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) * If this code is ever used to launch a vCPU with 32-bit entry point it * may need to subtract 4 bytes instead of 8 bytes. */ - TEST_ASSERT(IS_ALIGNED(stack_vaddr, PAGE_SIZE), - "__vm_vaddr_alloc() did not provide a page-aligned address"); - stack_vaddr -= 8; + TEST_ASSERT(IS_ALIGNED(stack_gva, PAGE_SIZE), + "__vm_alloc() did not provide a page-aligned address"); + stack_gva -= 8; vcpu = __vm_vcpu_add(vm, vcpu_id); vcpu_init_cpuid(vcpu, kvm_get_supported_cpuid()); @@ -855,7 +849,7 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) /* Setup guest general purpose registers */ vcpu_regs_get(vcpu, ®s); regs.rflags = regs.rflags | 0x2; - regs.rsp = stack_vaddr; + regs.rsp = stack_gva; vcpu_regs_set(vcpu, ®s); /* Setup the MP state */ @@ -872,7 +866,7 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) return vcpu; } -struct kvm_vcpu *vm_arch_vcpu_recreate(struct kvm_vm *vm, uint32_t vcpu_id) +struct kvm_vcpu *vm_arch_vcpu_recreate(struct kvm_vm *vm, u32 vcpu_id) { struct kvm_vcpu *vcpu = __vm_vcpu_add(vm, vcpu_id); @@ -907,9 +901,9 @@ const struct kvm_cpuid2 *kvm_get_supported_cpuid(void) return kvm_supported_cpuid; } -static uint32_t __kvm_cpu_has(const struct kvm_cpuid2 *cpuid, - uint32_t function, uint32_t index, - uint8_t reg, uint8_t lo, uint8_t hi) +static u32 __kvm_cpu_has(const struct kvm_cpuid2 *cpuid, + u32 function, u32 index, + u8 reg, u8 lo, u8 hi) { const struct kvm_cpuid_entry2 *entry; int i; @@ -936,14 +930,14 @@ bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid, feature.reg, feature.bit, feature.bit); } -uint32_t kvm_cpuid_property(const struct kvm_cpuid2 *cpuid, - struct kvm_x86_cpu_property property) +u32 kvm_cpuid_property(const struct kvm_cpuid2 *cpuid, + struct kvm_x86_cpu_property property) { return __kvm_cpu_has(cpuid, property.function, property.index, property.reg, property.lo_bit, property.hi_bit); } -uint64_t kvm_get_feature_msr(uint64_t msr_index) +u64 kvm_get_feature_msr(u64 msr_index) { struct { struct kvm_msrs header; @@ -962,7 +956,7 @@ uint64_t kvm_get_feature_msr(uint64_t msr_index) return buffer.entry.data; } -void __vm_xsave_require_permission(uint64_t xfeature, const char *name) +void __vm_xsave_require_permission(u64 xfeature, const char *name) { int kvm_fd; u64 bitmask; @@ -1019,7 +1013,7 @@ void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid) void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, struct kvm_x86_cpu_property property, - uint32_t value) + u32 value) { struct kvm_cpuid_entry2 *entry; @@ -1034,7 +1028,7 @@ void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, TEST_ASSERT_EQ(kvm_cpuid_property(vcpu->cpuid, property), value); } -void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function) +void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, u32 function) { struct kvm_cpuid_entry2 *entry = vcpu_get_cpuid_entry(vcpu, function); @@ -1063,7 +1057,7 @@ void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu, vcpu_set_cpuid(vcpu); } -uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index) +u64 vcpu_get_msr(struct kvm_vcpu *vcpu, u64 msr_index) { struct { struct kvm_msrs header; @@ -1078,7 +1072,7 @@ uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index) return buffer.entry.data; } -int _vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index, uint64_t msr_value) +int _vcpu_set_msr(struct kvm_vcpu *vcpu, u64 msr_index, u64 msr_value) { struct { struct kvm_msrs header; @@ -1106,28 +1100,28 @@ void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...) vcpu_regs_get(vcpu, ®s); if (num >= 1) - regs.rdi = va_arg(ap, uint64_t); + regs.rdi = va_arg(ap, u64); if (num >= 2) - regs.rsi = va_arg(ap, uint64_t); + regs.rsi = va_arg(ap, u64); if (num >= 3) - regs.rdx = va_arg(ap, uint64_t); + regs.rdx = va_arg(ap, u64); if (num >= 4) - regs.rcx = va_arg(ap, uint64_t); + regs.rcx = va_arg(ap, u64); if (num >= 5) - regs.r8 = va_arg(ap, uint64_t); + regs.r8 = va_arg(ap, u64); if (num >= 6) - regs.r9 = va_arg(ap, uint64_t); + regs.r9 = va_arg(ap, u64); vcpu_regs_set(vcpu, ®s); va_end(ap); } -void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent) +void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, u8 indent) { struct kvm_regs regs; struct kvm_sregs sregs; @@ -1196,7 +1190,7 @@ const struct kvm_msr_list *kvm_get_feature_msr_index_list(void) return list; } -bool kvm_msr_is_in_save_restore_list(uint32_t msr_index) +bool kvm_msr_is_in_save_restore_list(u32 msr_index) { const struct kvm_msr_list *list = kvm_get_msr_index_list(); int i; @@ -1327,7 +1321,7 @@ void kvm_init_vm_address_properties(struct kvm_vm *vm) } const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid, - uint32_t function, uint32_t index) + u32 function, u32 index) { int i; @@ -1344,7 +1338,7 @@ const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid, #define X86_HYPERCALL(inputs...) \ ({ \ - uint64_t r; \ + u64 r; \ \ asm volatile("test %[use_vmmcall], %[use_vmmcall]\n\t" \ "jnz 1f\n\t" \ @@ -1359,18 +1353,17 @@ const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid, r; \ }) -uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2, - uint64_t a3) +u64 kvm_hypercall(u64 nr, u64 a0, u64 a1, u64 a2, u64 a3) { return X86_HYPERCALL("a"(nr), "b"(a0), "c"(a1), "d"(a2), "S"(a3)); } -uint64_t __xen_hypercall(uint64_t nr, uint64_t a0, void *a1) +u64 __xen_hypercall(u64 nr, u64 a0, void *a1) { return X86_HYPERCALL("a"(nr), "D"(a0), "S"(a1)); } -void xen_hypercall(uint64_t nr, uint64_t a0, void *a1) +void xen_hypercall(u64 nr, u64 a0, void *a1) { GUEST_ASSERT(!__xen_hypercall(nr, a0, a1)); } @@ -1379,7 +1372,7 @@ unsigned long vm_compute_max_gfn(struct kvm_vm *vm) { const unsigned long num_ht_pages = 12 << (30 - vm->page_shift); /* 12 GiB */ unsigned long ht_gfn, max_gfn, max_pfn; - uint8_t maxphyaddr, guest_maxphyaddr; + u8 maxphyaddr, guest_maxphyaddr; /* * Use "guest MAXPHYADDR" from KVM if it's available. Guest MAXPHYADDR @@ -1453,8 +1446,7 @@ bool kvm_arch_has_default_irqchip(void) return true; } -void setup_smram(struct kvm_vm *vm, struct kvm_vcpu *vcpu, - uint64_t smram_gpa, +void setup_smram(struct kvm_vm *vm, struct kvm_vcpu *vcpu, u64 smram_gpa, const void *smi_handler, size_t handler_size) { vm_userspace_mem_region_add(vm, VM_MEM_SRC_ANONYMOUS, smram_gpa, diff --git a/tools/testing/selftests/kvm/lib/x86/sev.c b/tools/testing/selftests/kvm/lib/x86/sev.c index c3a9838f4806..93f916903461 100644 --- a/tools/testing/selftests/kvm/lib/x86/sev.c +++ b/tools/testing/selftests/kvm/lib/x86/sev.c @@ -15,10 +15,10 @@ * expression would cause us to quit the loop. */ static void encrypt_region(struct kvm_vm *vm, struct userspace_mem_region *region, - uint8_t page_type, bool private) + u8 page_type, bool private) { const struct sparsebit *protected_phy_pages = region->protected_phy_pages; - const vm_paddr_t gpa_base = region->region.guest_phys_addr; + const gpa_t gpa_base = region->region.guest_phys_addr; const sparsebit_idx_t lowest_page_in_region = gpa_base >> vm->page_shift; sparsebit_idx_t i, j; @@ -29,15 +29,15 @@ static void encrypt_region(struct kvm_vm *vm, struct userspace_mem_region *regio sev_register_encrypted_memory(vm, region); sparsebit_for_each_set_range(protected_phy_pages, i, j) { - const uint64_t size = (j - i + 1) * vm->page_size; - const uint64_t offset = (i - lowest_page_in_region) * vm->page_size; + const u64 size = (j - i + 1) * vm->page_size; + const u64 offset = (i - lowest_page_in_region) * vm->page_size; if (private) vm_mem_set_private(vm, gpa_base + offset, size); if (is_sev_snp_vm(vm)) snp_launch_update_data(vm, gpa_base + offset, - (uint64_t)addr_gpa2hva(vm, gpa_base + offset), + (u64)addr_gpa2hva(vm, gpa_base + offset), size, page_type); else sev_launch_update_data(vm, gpa_base + offset, size); @@ -79,7 +79,7 @@ void snp_vm_init(struct kvm_vm *vm) vm_sev_ioctl(vm, KVM_SEV_INIT2, &init); } -void sev_vm_launch(struct kvm_vm *vm, uint32_t policy) +void sev_vm_launch(struct kvm_vm *vm, u32 policy) { struct kvm_sev_launch_start launch_start = { .policy = policy, @@ -103,7 +103,7 @@ void sev_vm_launch(struct kvm_vm *vm, uint32_t policy) vm->arch.is_pt_protected = true; } -void sev_vm_launch_measure(struct kvm_vm *vm, uint8_t *measurement) +void sev_vm_launch_measure(struct kvm_vm *vm, u8 *measurement) { struct kvm_sev_launch_measure launch_measure; struct kvm_sev_guest_status guest_status; @@ -131,7 +131,7 @@ void sev_vm_launch_finish(struct kvm_vm *vm) TEST_ASSERT_EQ(status.state, SEV_GUEST_STATE_RUNNING); } -void snp_vm_launch_start(struct kvm_vm *vm, uint64_t policy) +void snp_vm_launch_start(struct kvm_vm *vm, u64 policy) { struct kvm_sev_snp_launch_start launch_start = { .policy = policy, @@ -158,7 +158,7 @@ void snp_vm_launch_finish(struct kvm_vm *vm) vm_sev_ioctl(vm, KVM_SEV_SNP_LAUNCH_FINISH, &launch_finish); } -struct kvm_vm *vm_sev_create_with_one_vcpu(uint32_t type, void *guest_code, +struct kvm_vm *vm_sev_create_with_one_vcpu(u32 type, void *guest_code, struct kvm_vcpu **cpu) { struct vm_shape shape = { @@ -174,7 +174,7 @@ struct kvm_vm *vm_sev_create_with_one_vcpu(uint32_t type, void *guest_code, return vm; } -void vm_sev_launch(struct kvm_vm *vm, uint64_t policy, uint8_t *measurement) +void vm_sev_launch(struct kvm_vm *vm, u64 policy, u8 *measurement) { if (is_sev_snp_vm(vm)) { vm_enable_cap(vm, KVM_CAP_EXIT_HYPERCALL, BIT(KVM_HC_MAP_GPA_RANGE)); diff --git a/tools/testing/selftests/kvm/lib/x86/svm.c b/tools/testing/selftests/kvm/lib/x86/svm.c index eb20b00112c7..3b01605ab016 100644 --- a/tools/testing/selftests/kvm/lib/x86/svm.c +++ b/tools/testing/selftests/kvm/lib/x86/svm.c @@ -28,20 +28,20 @@ u64 rflags; * Pointer to structure with the addresses of the SVM areas. */ struct svm_test_data * -vcpu_alloc_svm(struct kvm_vm *vm, vm_vaddr_t *p_svm_gva) +vcpu_alloc_svm(struct kvm_vm *vm, gva_t *p_svm_gva) { - vm_vaddr_t svm_gva = vm_vaddr_alloc_page(vm); + gva_t svm_gva = vm_alloc_page(vm); struct svm_test_data *svm = addr_gva2hva(vm, svm_gva); - svm->vmcb = (void *)vm_vaddr_alloc_page(vm); + svm->vmcb = (void *)vm_alloc_page(vm); svm->vmcb_hva = addr_gva2hva(vm, (uintptr_t)svm->vmcb); svm->vmcb_gpa = addr_gva2gpa(vm, (uintptr_t)svm->vmcb); - svm->save_area = (void *)vm_vaddr_alloc_page(vm); + svm->save_area = (void *)vm_alloc_page(vm); svm->save_area_hva = addr_gva2hva(vm, (uintptr_t)svm->save_area); svm->save_area_gpa = addr_gva2gpa(vm, (uintptr_t)svm->save_area); - svm->msr = (void *)vm_vaddr_alloc_page(vm); + svm->msr = (void *)vm_alloc_page(vm); svm->msr_hva = addr_gva2hva(vm, (uintptr_t)svm->msr); svm->msr_gpa = addr_gva2gpa(vm, (uintptr_t)svm->msr); memset(svm->msr_hva, 0, getpagesize()); @@ -84,14 +84,14 @@ void vm_enable_npt(struct kvm_vm *vm) void generic_svm_setup(struct svm_test_data *svm, void *guest_rip, void *guest_rsp) { struct vmcb *vmcb = svm->vmcb; - uint64_t vmcb_gpa = svm->vmcb_gpa; + u64 vmcb_gpa = svm->vmcb_gpa; struct vmcb_save_area *save = &vmcb->save; struct vmcb_control_area *ctrl = &vmcb->control; u32 data_seg_attr = 3 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_P_MASK | SVM_SELECTOR_DB_MASK | SVM_SELECTOR_G_MASK; u32 code_seg_attr = 9 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_P_MASK | SVM_SELECTOR_L_MASK | SVM_SELECTOR_G_MASK; - uint64_t efer; + u64 efer; efer = rdmsr(MSR_EFER); wrmsr(MSR_EFER, efer | EFER_SVME); @@ -158,7 +158,7 @@ void generic_svm_setup(struct svm_test_data *svm, void *guest_rip, void *guest_r * for now. registers involved in LOAD/SAVE_GPR_C are eventually * unmodified so they do not need to be in the clobber list. */ -void run_guest(struct vmcb *vmcb, uint64_t vmcb_gpa) +void run_guest(struct vmcb *vmcb, u64 vmcb_gpa) { asm volatile ( "vmload %[vmcb_gpa]\n\t" diff --git a/tools/testing/selftests/kvm/lib/x86/ucall.c b/tools/testing/selftests/kvm/lib/x86/ucall.c index 1265cecc7dd1..e7dd5791959b 100644 --- a/tools/testing/selftests/kvm/lib/x86/ucall.c +++ b/tools/testing/selftests/kvm/lib/x86/ucall.c @@ -6,9 +6,9 @@ */ #include "kvm_util.h" -#define UCALL_PIO_PORT ((uint16_t)0x1000) +#define UCALL_PIO_PORT ((u16)0x1000) -void ucall_arch_do_ucall(vm_vaddr_t uc) +void ucall_arch_do_ucall(gva_t uc) { /* * FIXME: Revert this hack (the entire commit that added it) once nVMX diff --git a/tools/testing/selftests/kvm/lib/x86/vmx.c b/tools/testing/selftests/kvm/lib/x86/vmx.c index c87b340362a9..67642759e4a0 100644 --- a/tools/testing/selftests/kvm/lib/x86/vmx.c +++ b/tools/testing/selftests/kvm/lib/x86/vmx.c @@ -27,7 +27,7 @@ struct hv_vp_assist_page *current_vp_assist; int vcpu_enable_evmcs(struct kvm_vcpu *vcpu) { - uint16_t evmcs_ver; + u16 evmcs_ver; vcpu_enable_cap(vcpu, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, (unsigned long)&evmcs_ver); @@ -79,39 +79,39 @@ void vm_enable_ept(struct kvm_vm *vm) * Pointer to structure with the addresses of the VMX areas. */ struct vmx_pages * -vcpu_alloc_vmx(struct kvm_vm *vm, vm_vaddr_t *p_vmx_gva) +vcpu_alloc_vmx(struct kvm_vm *vm, gva_t *p_vmx_gva) { - vm_vaddr_t vmx_gva = vm_vaddr_alloc_page(vm); + gva_t vmx_gva = vm_alloc_page(vm); struct vmx_pages *vmx = addr_gva2hva(vm, vmx_gva); /* Setup of a region of guest memory for the vmxon region. */ - vmx->vmxon = (void *)vm_vaddr_alloc_page(vm); + vmx->vmxon = (void *)vm_alloc_page(vm); vmx->vmxon_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmxon); vmx->vmxon_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmxon); /* Setup of a region of guest memory for a vmcs. */ - vmx->vmcs = (void *)vm_vaddr_alloc_page(vm); + vmx->vmcs = (void *)vm_alloc_page(vm); vmx->vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmcs); vmx->vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmcs); /* Setup of a region of guest memory for the MSR bitmap. */ - vmx->msr = (void *)vm_vaddr_alloc_page(vm); + vmx->msr = (void *)vm_alloc_page(vm); vmx->msr_hva = addr_gva2hva(vm, (uintptr_t)vmx->msr); vmx->msr_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->msr); memset(vmx->msr_hva, 0, getpagesize()); /* Setup of a region of guest memory for the shadow VMCS. */ - vmx->shadow_vmcs = (void *)vm_vaddr_alloc_page(vm); + vmx->shadow_vmcs = (void *)vm_alloc_page(vm); vmx->shadow_vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->shadow_vmcs); vmx->shadow_vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->shadow_vmcs); /* Setup of a region of guest memory for the VMREAD and VMWRITE bitmaps. */ - vmx->vmread = (void *)vm_vaddr_alloc_page(vm); + vmx->vmread = (void *)vm_alloc_page(vm); vmx->vmread_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmread); vmx->vmread_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmread); memset(vmx->vmread_hva, 0, getpagesize()); - vmx->vmwrite = (void *)vm_vaddr_alloc_page(vm); + vmx->vmwrite = (void *)vm_alloc_page(vm); vmx->vmwrite_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmwrite); vmx->vmwrite_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmwrite); memset(vmx->vmwrite_hva, 0, getpagesize()); @@ -125,8 +125,8 @@ vcpu_alloc_vmx(struct kvm_vm *vm, vm_vaddr_t *p_vmx_gva) bool prepare_for_vmx_operation(struct vmx_pages *vmx) { - uint64_t feature_control; - uint64_t required; + u64 feature_control; + u64 required; unsigned long cr0; unsigned long cr4; @@ -160,7 +160,7 @@ bool prepare_for_vmx_operation(struct vmx_pages *vmx) wrmsr(MSR_IA32_FEAT_CTL, feature_control | required); /* Enter VMX root operation. */ - *(uint32_t *)(vmx->vmxon) = vmcs_revision(); + *(u32 *)(vmx->vmxon) = vmcs_revision(); if (vmxon(vmx->vmxon_gpa)) return false; @@ -170,7 +170,7 @@ bool prepare_for_vmx_operation(struct vmx_pages *vmx) bool load_vmcs(struct vmx_pages *vmx) { /* Load a VMCS. */ - *(uint32_t *)(vmx->vmcs) = vmcs_revision(); + *(u32 *)(vmx->vmcs) = vmcs_revision(); if (vmclear(vmx->vmcs_gpa)) return false; @@ -178,14 +178,14 @@ bool load_vmcs(struct vmx_pages *vmx) return false; /* Setup shadow VMCS, do not load it yet. */ - *(uint32_t *)(vmx->shadow_vmcs) = vmcs_revision() | 0x80000000ul; + *(u32 *)(vmx->shadow_vmcs) = vmcs_revision() | 0x80000000ul; if (vmclear(vmx->shadow_vmcs_gpa)) return false; return true; } -static bool ept_vpid_cap_supported(uint64_t mask) +static bool ept_vpid_cap_supported(u64 mask) { return rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & mask; } @@ -200,7 +200,7 @@ bool ept_1g_pages_supported(void) */ static inline void init_vmcs_control_fields(struct vmx_pages *vmx) { - uint32_t sec_exec_ctl = 0; + u32 sec_exec_ctl = 0; vmwrite(VIRTUAL_PROCESSOR_ID, 0); vmwrite(POSTED_INTR_NV, 0); @@ -208,7 +208,7 @@ static inline void init_vmcs_control_fields(struct vmx_pages *vmx) vmwrite(PIN_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS)); if (vmx->eptp_gpa) { - uint64_t eptp = vmx->eptp_gpa | EPTP_WB | EPTP_PWL_4; + u64 eptp = vmx->eptp_gpa | EPTP_WB | EPTP_PWL_4; TEST_ASSERT((vmx->eptp_gpa & ~PHYSICAL_PAGE_MASK) == 0, "Illegal bits set in vmx->eptp_gpa"); @@ -259,7 +259,7 @@ static inline void init_vmcs_control_fields(struct vmx_pages *vmx) */ static inline void init_vmcs_host_state(void) { - uint32_t exit_controls = vmreadz(VM_EXIT_CONTROLS); + u32 exit_controls = vmreadz(VM_EXIT_CONTROLS); vmwrite(HOST_ES_SELECTOR, get_es()); vmwrite(HOST_CS_SELECTOR, get_cs()); @@ -358,8 +358,8 @@ static inline void init_vmcs_guest_state(void *rip, void *rsp) vmwrite(GUEST_GDTR_BASE, vmreadz(HOST_GDTR_BASE)); vmwrite(GUEST_IDTR_BASE, vmreadz(HOST_IDTR_BASE)); vmwrite(GUEST_DR7, 0x400); - vmwrite(GUEST_RSP, (uint64_t)rsp); - vmwrite(GUEST_RIP, (uint64_t)rip); + vmwrite(GUEST_RSP, (u64)rsp); + vmwrite(GUEST_RIP, (u64)rip); vmwrite(GUEST_RFLAGS, 2); vmwrite(GUEST_PENDING_DBG_EXCEPTIONS, 0); vmwrite(GUEST_SYSENTER_ESP, vmreadz(HOST_IA32_SYSENTER_ESP)); @@ -375,7 +375,7 @@ void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip, void *guest_rsp) bool kvm_cpu_has_ept(void) { - uint64_t ctrl; + u64 ctrl; if (!kvm_cpu_has(X86_FEATURE_VMX)) return false; @@ -390,7 +390,7 @@ bool kvm_cpu_has_ept(void) void prepare_virtualize_apic_accesses(struct vmx_pages *vmx, struct kvm_vm *vm) { - vmx->apic_access = (void *)vm_vaddr_alloc_page(vm); + vmx->apic_access = (void *)vm_alloc_page(vm); vmx->apic_access_hva = addr_gva2hva(vm, (uintptr_t)vmx->apic_access); vmx->apic_access_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->apic_access); } diff --git a/tools/testing/selftests/kvm/loongarch/arch_timer.c b/tools/testing/selftests/kvm/loongarch/arch_timer.c index 355ecac30954..a7279ded8518 100644 --- a/tools/testing/selftests/kvm/loongarch/arch_timer.c +++ b/tools/testing/selftests/kvm/loongarch/arch_timer.c @@ -27,8 +27,8 @@ static void do_idle(void) static void guest_irq_handler(struct ex_regs *regs) { unsigned int intid; - uint32_t cpu = guest_get_vcpuid(); - uint64_t xcnt, val, cfg, xcnt_diff_us; + u32 cpu = guest_get_vcpuid(); + u64 xcnt, val, cfg, xcnt_diff_us; struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu]; intid = !!(regs->estat & BIT(INT_TI)); @@ -62,10 +62,10 @@ static void guest_irq_handler(struct ex_regs *regs) WRITE_ONCE(shared_data->nr_iter, shared_data->nr_iter + 1); } -static void guest_test_period_timer(uint32_t cpu) +static void guest_test_period_timer(u32 cpu) { - uint32_t irq_iter, config_iter; - uint64_t us; + u32 irq_iter, config_iter; + u64 us; struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu]; shared_data->nr_iter = test_args.nr_iter; @@ -86,10 +86,10 @@ static void guest_test_period_timer(uint32_t cpu) irq_iter); } -static void guest_test_oneshot_timer(uint32_t cpu) +static void guest_test_oneshot_timer(u32 cpu) { - uint32_t irq_iter, config_iter; - uint64_t us; + u32 irq_iter, config_iter; + u64 us; struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu]; shared_data->nr_iter = 0; @@ -112,10 +112,10 @@ static void guest_test_oneshot_timer(uint32_t cpu) } } -static void guest_test_emulate_timer(uint32_t cpu) +static void guest_test_emulate_timer(u32 cpu) { - uint32_t config_iter; - uint64_t xcnt_diff_us, us; + u32 config_iter; + u64 xcnt_diff_us, us; struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu]; local_irq_disable(); @@ -136,9 +136,9 @@ static void guest_test_emulate_timer(uint32_t cpu) local_irq_enable(); } -static void guest_time_count_test(uint32_t cpu) +static void guest_time_count_test(u32 cpu) { - uint32_t config_iter; + u32 config_iter; unsigned long start, end, prev, us; /* Assuming that test case starts to run in 1 second */ @@ -165,7 +165,7 @@ static void guest_time_count_test(uint32_t cpu) static void guest_code(void) { - uint32_t cpu = guest_get_vcpuid(); + u32 cpu = guest_get_vcpuid(); /* must run at first */ guest_time_count_test(cpu); diff --git a/tools/testing/selftests/kvm/loongarch/pmu_test.c b/tools/testing/selftests/kvm/loongarch/pmu_test.c index 88bb530e336e..ec3fefb9ea97 100644 --- a/tools/testing/selftests/kvm/loongarch/pmu_test.c +++ b/tools/testing/selftests/kvm/loongarch/pmu_test.c @@ -15,7 +15,7 @@ static int pmu_irq_count; /* Check PMU support */ static bool has_pmu_support(void) { - uint32_t cfg6; + u32 cfg6; /* Read CPUCFG6 to check PMU */ cfg6 = read_cpucfg(LOONGARCH_CPUCFG6); @@ -34,7 +34,7 @@ static bool has_pmu_support(void) /* Dump PMU capabilities */ static void dump_pmu_caps(void) { - uint32_t cfg6; + u32 cfg6; int nr_counters, counter_bits; cfg6 = read_cpucfg(LOONGARCH_CPUCFG6); @@ -51,8 +51,8 @@ static void dump_pmu_caps(void) static void guest_pmu_base_test(void) { int i; - uint32_t cfg6, pmnum; - uint64_t cnt[4]; + u32 cfg6, pmnum; + u64 cnt[4]; cfg6 = read_cpucfg(LOONGARCH_CPUCFG6); pmnum = (cfg6 >> 4) & 0xf; @@ -114,7 +114,7 @@ static void guest_irq_handler(struct ex_regs *regs) static void guest_pmu_interrupt_test(void) { - uint64_t cnt; + u64 cnt; csr_write(PMU_OVERFLOW - 1, LOONGARCH_CSR_PERFCNTR0); csr_write(PMU_ENVENT_ENABLED | CSR_PERFCTRL_PMIE | LOONGARCH_PMU_EVENT_CYCLES, LOONGARCH_CSR_PERFCTRL0); diff --git a/tools/testing/selftests/kvm/memslot_modification_stress_test.c b/tools/testing/selftests/kvm/memslot_modification_stress_test.c index 3cdfa3b19b85..9c7578a098c3 100644 --- a/tools/testing/selftests/kvm/memslot_modification_stress_test.c +++ b/tools/testing/selftests/kvm/memslot_modification_stress_test.c @@ -30,7 +30,7 @@ static int nr_vcpus = 1; -static uint64_t guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE; +static u64 guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE; static void vcpu_worker(struct memstress_vcpu_args *vcpu_args) { @@ -55,10 +55,10 @@ static void vcpu_worker(struct memstress_vcpu_args *vcpu_args) } static void add_remove_memslot(struct kvm_vm *vm, useconds_t delay, - uint64_t nr_modifications) + u64 nr_modifications) { - uint64_t pages = max_t(int, vm->page_size, getpagesize()) / vm->page_size; - uint64_t gpa; + u64 pages = max_t(int, vm->page_size, getpagesize()) / vm->page_size; + gpa_t gpa; int i; /* @@ -78,7 +78,7 @@ static void add_remove_memslot(struct kvm_vm *vm, useconds_t delay, struct test_params { useconds_t delay; - uint64_t nr_iterations; + u64 nr_iterations; bool partition_vcpu_memory_access; bool disable_slot_zap_quirk; }; diff --git a/tools/testing/selftests/kvm/memslot_perf_test.c b/tools/testing/selftests/kvm/memslot_perf_test.c index 5087d082c4b0..3d02db371422 100644 --- a/tools/testing/selftests/kvm/memslot_perf_test.c +++ b/tools/testing/selftests/kvm/memslot_perf_test.c @@ -85,17 +85,17 @@ struct vm_data { struct kvm_vm *vm; struct kvm_vcpu *vcpu; pthread_t vcpu_thread; - uint32_t nslots; - uint64_t npages; - uint64_t pages_per_slot; + u32 nslots; + u64 npages; + u64 pages_per_slot; void **hva_slots; bool mmio_ok; - uint64_t mmio_gpa_min; - uint64_t mmio_gpa_max; + u64 mmio_gpa_min; + u64 mmio_gpa_max; }; struct sync_area { - uint32_t guest_page_size; + u32 guest_page_size; atomic_bool start_flag; atomic_bool exit_flag; atomic_bool sync_flag; @@ -186,12 +186,12 @@ static void wait_for_vcpu(void) "sem_timedwait() failed: %d", errno); } -static void *vm_gpa2hva(struct vm_data *data, uint64_t gpa, uint64_t *rempages) +static void *vm_gpa2hva(struct vm_data *data, gpa_t gpa, u64 *rempages) { - uint64_t gpage, pgoffs; - uint32_t slot, slotoffs; + gpa_t gpage, pgoffs; + u32 slot, slotoffs; void *base; - uint32_t guest_page_size = data->vm->page_size; + u32 guest_page_size = data->vm->page_size; TEST_ASSERT(gpa >= MEM_GPA, "Too low gpa to translate"); TEST_ASSERT(gpa < MEM_GPA + data->npages * guest_page_size, @@ -200,11 +200,11 @@ static void *vm_gpa2hva(struct vm_data *data, uint64_t gpa, uint64_t *rempages) gpage = gpa / guest_page_size; pgoffs = gpa % guest_page_size; - slot = min(gpage / data->pages_per_slot, (uint64_t)data->nslots - 1); + slot = min(gpage / data->pages_per_slot, (u64)data->nslots - 1); slotoffs = gpage - (slot * data->pages_per_slot); if (rempages) { - uint64_t slotpages; + u64 slotpages; if (slot == data->nslots - 1) slotpages = data->npages - slot * data->pages_per_slot; @@ -217,12 +217,12 @@ static void *vm_gpa2hva(struct vm_data *data, uint64_t gpa, uint64_t *rempages) } base = data->hva_slots[slot]; - return (uint8_t *)base + slotoffs * guest_page_size + pgoffs; + return (u8 *)base + slotoffs * guest_page_size + pgoffs; } -static uint64_t vm_slot2gpa(struct vm_data *data, uint32_t slot) +static u64 vm_slot2gpa(struct vm_data *data, u32 slot) { - uint32_t guest_page_size = data->vm->page_size; + u32 guest_page_size = data->vm->page_size; TEST_ASSERT(slot < data->nslots, "Too high slot number"); @@ -243,8 +243,8 @@ static struct vm_data *alloc_vm(void) return data; } -static bool check_slot_pages(uint32_t host_page_size, uint32_t guest_page_size, - uint64_t pages_per_slot, uint64_t rempages) +static bool check_slot_pages(u32 host_page_size, u32 guest_page_size, + u64 pages_per_slot, u64 rempages) { if (!pages_per_slot) return false; @@ -259,11 +259,11 @@ static bool check_slot_pages(uint32_t host_page_size, uint32_t guest_page_size, } -static uint64_t get_max_slots(struct vm_data *data, uint32_t host_page_size) +static u64 get_max_slots(struct vm_data *data, u32 host_page_size) { - uint32_t guest_page_size = data->vm->page_size; - uint64_t mempages, pages_per_slot, rempages; - uint64_t slots; + u32 guest_page_size = data->vm->page_size; + u64 mempages, pages_per_slot, rempages; + u64 slots; mempages = data->npages; slots = data->nslots; @@ -281,13 +281,13 @@ static uint64_t get_max_slots(struct vm_data *data, uint32_t host_page_size) return 0; } -static bool prepare_vm(struct vm_data *data, int nslots, uint64_t *maxslots, - void *guest_code, uint64_t mem_size, +static bool prepare_vm(struct vm_data *data, int nslots, u64 *maxslots, + void *guest_code, u64 mem_size, struct timespec *slot_runtime) { - uint64_t mempages, rempages; - uint64_t guest_addr; - uint32_t slot, host_page_size, guest_page_size; + u64 mempages, rempages; + u64 guest_addr; + u32 slot, host_page_size, guest_page_size; struct timespec tstart; struct sync_area *sync; @@ -317,7 +317,7 @@ static bool prepare_vm(struct vm_data *data, int nslots, uint64_t *maxslots, clock_gettime(CLOCK_MONOTONIC, &tstart); for (slot = 1, guest_addr = MEM_GPA; slot <= data->nslots; slot++) { - uint64_t npages; + u64 npages; npages = data->pages_per_slot; if (slot == data->nslots) @@ -331,8 +331,8 @@ static bool prepare_vm(struct vm_data *data, int nslots, uint64_t *maxslots, *slot_runtime = timespec_elapsed(tstart); for (slot = 1, guest_addr = MEM_GPA; slot <= data->nslots; slot++) { - uint64_t npages; - uint64_t gpa; + u64 npages; + gpa_t gpa; npages = data->pages_per_slot; if (slot == data->nslots) @@ -448,7 +448,7 @@ static bool guest_perform_sync(void) static void guest_code_test_memslot_move(void) { struct sync_area *sync = (typeof(sync))MEM_SYNC_GPA; - uint32_t page_size = (typeof(page_size))READ_ONCE(sync->guest_page_size); + u32 page_size = (typeof(page_size))READ_ONCE(sync->guest_page_size); uintptr_t base = (typeof(base))READ_ONCE(sync->move_area_ptr); GUEST_SYNC(0); @@ -460,7 +460,7 @@ static void guest_code_test_memslot_move(void) for (ptr = base; ptr < base + MEM_TEST_MOVE_SIZE; ptr += page_size) - *(uint64_t *)ptr = MEM_TEST_VAL_1; + *(u64 *)ptr = MEM_TEST_VAL_1; /* * No host sync here since the MMIO exits are so expensive @@ -477,7 +477,7 @@ static void guest_code_test_memslot_move(void) static void guest_code_test_memslot_map(void) { struct sync_area *sync = (typeof(sync))MEM_SYNC_GPA; - uint32_t page_size = (typeof(page_size))READ_ONCE(sync->guest_page_size); + u32 page_size = (typeof(page_size))READ_ONCE(sync->guest_page_size); GUEST_SYNC(0); @@ -489,7 +489,7 @@ static void guest_code_test_memslot_map(void) for (ptr = MEM_TEST_GPA; ptr < MEM_TEST_GPA + MEM_TEST_MAP_SIZE / 2; ptr += page_size) - *(uint64_t *)ptr = MEM_TEST_VAL_1; + *(u64 *)ptr = MEM_TEST_VAL_1; if (!guest_perform_sync()) break; @@ -497,7 +497,7 @@ static void guest_code_test_memslot_map(void) for (ptr = MEM_TEST_GPA + MEM_TEST_MAP_SIZE / 2; ptr < MEM_TEST_GPA + MEM_TEST_MAP_SIZE; ptr += page_size) - *(uint64_t *)ptr = MEM_TEST_VAL_2; + *(u64 *)ptr = MEM_TEST_VAL_2; if (!guest_perform_sync()) break; @@ -526,13 +526,13 @@ static void guest_code_test_memslot_unmap(void) * * Just access a single page to be on the safe side. */ - *(uint64_t *)ptr = MEM_TEST_VAL_1; + *(u64 *)ptr = MEM_TEST_VAL_1; if (!guest_perform_sync()) break; ptr += MEM_TEST_UNMAP_SIZE / 2; - *(uint64_t *)ptr = MEM_TEST_VAL_2; + *(u64 *)ptr = MEM_TEST_VAL_2; if (!guest_perform_sync()) break; @@ -544,7 +544,7 @@ static void guest_code_test_memslot_unmap(void) static void guest_code_test_memslot_rw(void) { struct sync_area *sync = (typeof(sync))MEM_SYNC_GPA; - uint32_t page_size = (typeof(page_size))READ_ONCE(sync->guest_page_size); + u32 page_size = (typeof(page_size))READ_ONCE(sync->guest_page_size); GUEST_SYNC(0); @@ -555,17 +555,17 @@ static void guest_code_test_memslot_rw(void) for (ptr = MEM_TEST_GPA; ptr < MEM_TEST_GPA + MEM_TEST_SIZE; ptr += page_size) - *(uint64_t *)ptr = MEM_TEST_VAL_1; + *(u64 *)ptr = MEM_TEST_VAL_1; if (!guest_perform_sync()) break; for (ptr = MEM_TEST_GPA + page_size / 2; ptr < MEM_TEST_GPA + MEM_TEST_SIZE; ptr += page_size) { - uint64_t val = *(uint64_t *)ptr; + u64 val = *(u64 *)ptr; GUEST_ASSERT_EQ(val, MEM_TEST_VAL_2); - *(uint64_t *)ptr = 0; + *(u64 *)ptr = 0; } if (!guest_perform_sync()) @@ -577,10 +577,10 @@ static void guest_code_test_memslot_rw(void) static bool test_memslot_move_prepare(struct vm_data *data, struct sync_area *sync, - uint64_t *maxslots, bool isactive) + u64 *maxslots, bool isactive) { - uint32_t guest_page_size = data->vm->page_size; - uint64_t movesrcgpa, movetestgpa; + u32 guest_page_size = data->vm->page_size; + u64 movesrcgpa, movetestgpa; #ifdef __x86_64__ if (disable_slot_zap_quirk) @@ -590,7 +590,7 @@ static bool test_memslot_move_prepare(struct vm_data *data, movesrcgpa = vm_slot2gpa(data, data->nslots - 1); if (isactive) { - uint64_t lastpages; + u64 lastpages; vm_gpa2hva(data, movesrcgpa, &lastpages); if (lastpages * guest_page_size < MEM_TEST_MOVE_SIZE / 2) { @@ -613,21 +613,21 @@ static bool test_memslot_move_prepare(struct vm_data *data, static bool test_memslot_move_prepare_active(struct vm_data *data, struct sync_area *sync, - uint64_t *maxslots) + u64 *maxslots) { return test_memslot_move_prepare(data, sync, maxslots, true); } static bool test_memslot_move_prepare_inactive(struct vm_data *data, struct sync_area *sync, - uint64_t *maxslots) + u64 *maxslots) { return test_memslot_move_prepare(data, sync, maxslots, false); } static void test_memslot_move_loop(struct vm_data *data, struct sync_area *sync) { - uint64_t movesrcgpa; + u64 movesrcgpa; movesrcgpa = vm_slot2gpa(data, data->nslots - 1); vm_mem_region_move(data->vm, data->nslots - 1 + 1, @@ -636,13 +636,13 @@ static void test_memslot_move_loop(struct vm_data *data, struct sync_area *sync) } static void test_memslot_do_unmap(struct vm_data *data, - uint64_t offsp, uint64_t count) + u64 offsp, u64 count) { - uint64_t gpa, ctr; - uint32_t guest_page_size = data->vm->page_size; + gpa_t gpa, ctr; + u32 guest_page_size = data->vm->page_size; for (gpa = MEM_TEST_GPA + offsp * guest_page_size, ctr = 0; ctr < count; ) { - uint64_t npages; + u64 npages; void *hva; int ret; @@ -661,11 +661,11 @@ static void test_memslot_do_unmap(struct vm_data *data, } static void test_memslot_map_unmap_check(struct vm_data *data, - uint64_t offsp, uint64_t valexp) + u64 offsp, u64 valexp) { - uint64_t gpa; - uint64_t *val; - uint32_t guest_page_size = data->vm->page_size; + gpa_t gpa; + u64 *val; + u32 guest_page_size = data->vm->page_size; if (!map_unmap_verify) return; @@ -680,8 +680,8 @@ static void test_memslot_map_unmap_check(struct vm_data *data, static void test_memslot_map_loop(struct vm_data *data, struct sync_area *sync) { - uint32_t guest_page_size = data->vm->page_size; - uint64_t guest_pages = MEM_TEST_MAP_SIZE / guest_page_size; + u32 guest_page_size = data->vm->page_size; + u64 guest_pages = MEM_TEST_MAP_SIZE / guest_page_size; /* * Unmap the second half of the test area while guest writes to (maps) @@ -718,11 +718,11 @@ static void test_memslot_map_loop(struct vm_data *data, struct sync_area *sync) static void test_memslot_unmap_loop_common(struct vm_data *data, struct sync_area *sync, - uint64_t chunk) + u64 chunk) { - uint32_t guest_page_size = data->vm->page_size; - uint64_t guest_pages = MEM_TEST_UNMAP_SIZE / guest_page_size; - uint64_t ctr; + u32 guest_page_size = data->vm->page_size; + u64 guest_pages = MEM_TEST_UNMAP_SIZE / guest_page_size; + u64 ctr; /* * Wait for the guest to finish mapping page(s) in the first half @@ -746,9 +746,9 @@ static void test_memslot_unmap_loop_common(struct vm_data *data, static void test_memslot_unmap_loop(struct vm_data *data, struct sync_area *sync) { - uint32_t host_page_size = getpagesize(); - uint32_t guest_page_size = data->vm->page_size; - uint64_t guest_chunk_pages = guest_page_size >= host_page_size ? + u32 host_page_size = getpagesize(); + u32 guest_page_size = data->vm->page_size; + u64 guest_chunk_pages = guest_page_size >= host_page_size ? 1 : host_page_size / guest_page_size; test_memslot_unmap_loop_common(data, sync, guest_chunk_pages); @@ -757,27 +757,27 @@ static void test_memslot_unmap_loop(struct vm_data *data, static void test_memslot_unmap_loop_chunked(struct vm_data *data, struct sync_area *sync) { - uint32_t guest_page_size = data->vm->page_size; - uint64_t guest_chunk_pages = MEM_TEST_UNMAP_CHUNK_SIZE / guest_page_size; + u32 guest_page_size = data->vm->page_size; + u64 guest_chunk_pages = MEM_TEST_UNMAP_CHUNK_SIZE / guest_page_size; test_memslot_unmap_loop_common(data, sync, guest_chunk_pages); } static void test_memslot_rw_loop(struct vm_data *data, struct sync_area *sync) { - uint64_t gptr; - uint32_t guest_page_size = data->vm->page_size; + u64 gptr; + u32 guest_page_size = data->vm->page_size; for (gptr = MEM_TEST_GPA + guest_page_size / 2; gptr < MEM_TEST_GPA + MEM_TEST_SIZE; gptr += guest_page_size) - *(uint64_t *)vm_gpa2hva(data, gptr, NULL) = MEM_TEST_VAL_2; + *(u64 *)vm_gpa2hva(data, gptr, NULL) = MEM_TEST_VAL_2; host_perform_sync(sync); for (gptr = MEM_TEST_GPA; gptr < MEM_TEST_GPA + MEM_TEST_SIZE; gptr += guest_page_size) { - uint64_t *vptr = (typeof(vptr))vm_gpa2hva(data, gptr, NULL); - uint64_t val = *vptr; + u64 *vptr = (typeof(vptr))vm_gpa2hva(data, gptr, NULL); + u64 val = *vptr; TEST_ASSERT(val == MEM_TEST_VAL_1, "Guest written values should read back correctly (is %"PRIu64" @ %"PRIx64")", @@ -790,21 +790,21 @@ static void test_memslot_rw_loop(struct vm_data *data, struct sync_area *sync) struct test_data { const char *name; - uint64_t mem_size; + u64 mem_size; void (*guest_code)(void); bool (*prepare)(struct vm_data *data, struct sync_area *sync, - uint64_t *maxslots); + u64 *maxslots); void (*loop)(struct vm_data *data, struct sync_area *sync); }; -static bool test_execute(int nslots, uint64_t *maxslots, +static bool test_execute(int nslots, u64 *maxslots, unsigned int maxtime, const struct test_data *tdata, - uint64_t *nloops, + u64 *nloops, struct timespec *slot_runtime, struct timespec *guest_runtime) { - uint64_t mem_size = tdata->mem_size ? : MEM_SIZE; + u64 mem_size = tdata->mem_size ? : MEM_SIZE; struct vm_data *data; struct sync_area *sync; struct timespec tstart; @@ -924,8 +924,8 @@ static void help(char *name, struct test_args *targs) static bool check_memory_sizes(void) { - uint32_t host_page_size = getpagesize(); - uint32_t guest_page_size = vm_guest_mode_params[VM_MODE_DEFAULT].page_size; + u32 host_page_size = getpagesize(); + u32 guest_page_size = vm_guest_mode_params[VM_MODE_DEFAULT].page_size; if (host_page_size > SZ_64K || guest_page_size > SZ_64K) { pr_info("Unsupported page size on host (0x%x) or guest (0x%x)\n", @@ -961,7 +961,7 @@ static bool check_memory_sizes(void) static bool parse_args(int argc, char *argv[], struct test_args *targs) { - uint32_t max_mem_slots; + u32 max_mem_slots; int opt; while ((opt = getopt(argc, argv, "hvdqs:f:e:l:r:")) != -1) { @@ -1040,8 +1040,8 @@ static bool parse_args(int argc, char *argv[], struct test_result { struct timespec slot_runtime, guest_runtime, iter_runtime; - int64_t slottimens, runtimens; - uint64_t nloops; + s64 slottimens, runtimens; + u64 nloops; }; static bool test_loop(const struct test_data *data, @@ -1049,7 +1049,7 @@ static bool test_loop(const struct test_data *data, struct test_result *rbestslottime, struct test_result *rbestruntime) { - uint64_t maxslots; + u64 maxslots; struct test_result result = {}; if (!test_execute(targs->nslots, &maxslots, targs->seconds, data, diff --git a/tools/testing/selftests/kvm/mmu_stress_test.c b/tools/testing/selftests/kvm/mmu_stress_test.c index 51c070556f3e..54d281419d31 100644 --- a/tools/testing/selftests/kvm/mmu_stress_test.c +++ b/tools/testing/selftests/kvm/mmu_stress_test.c @@ -20,19 +20,19 @@ static bool mprotect_ro_done; static bool all_vcpus_hit_ro_fault; -static void guest_code(uint64_t start_gpa, uint64_t end_gpa, uint64_t stride) +static void guest_code(u64 start_gpa, u64 end_gpa, u64 stride) { - uint64_t gpa; + gpa_t gpa; int i; for (i = 0; i < 2; i++) { for (gpa = start_gpa; gpa < end_gpa; gpa += stride) - vcpu_arch_put_guest(*((volatile uint64_t *)gpa), gpa); + vcpu_arch_put_guest(*((volatile u64 *)gpa), gpa); GUEST_SYNC(i); } for (gpa = start_gpa; gpa < end_gpa; gpa += stride) - *((volatile uint64_t *)gpa); + *((volatile u64 *)gpa); GUEST_SYNC(2); /* @@ -55,7 +55,7 @@ static void guest_code(uint64_t start_gpa, uint64_t end_gpa, uint64_t stride) #elif defined(__aarch64__) asm volatile("str %0, [%0]" :: "r" (gpa) : "memory"); #else - vcpu_arch_put_guest(*((volatile uint64_t *)gpa), gpa); + vcpu_arch_put_guest(*((volatile u64 *)gpa), gpa); #endif } while (!READ_ONCE(mprotect_ro_done) || !READ_ONCE(all_vcpus_hit_ro_fault)); @@ -68,7 +68,7 @@ static void guest_code(uint64_t start_gpa, uint64_t end_gpa, uint64_t stride) #endif for (gpa = start_gpa; gpa < end_gpa; gpa += stride) - vcpu_arch_put_guest(*((volatile uint64_t *)gpa), gpa); + vcpu_arch_put_guest(*((volatile u64 *)gpa), gpa); GUEST_SYNC(4); GUEST_ASSERT(0); @@ -76,8 +76,8 @@ static void guest_code(uint64_t start_gpa, uint64_t end_gpa, uint64_t stride) struct vcpu_info { struct kvm_vcpu *vcpu; - uint64_t start_gpa; - uint64_t end_gpa; + u64 start_gpa; + u64 end_gpa; }; static int nr_vcpus; @@ -203,10 +203,10 @@ static void *vcpu_worker(void *data) } static pthread_t *spawn_workers(struct kvm_vm *vm, struct kvm_vcpu **vcpus, - uint64_t start_gpa, uint64_t end_gpa) + u64 start_gpa, u64 end_gpa) { struct vcpu_info *info; - uint64_t gpa, nr_bytes; + gpa_t gpa, nr_bytes; pthread_t *threads; int i; @@ -217,7 +217,7 @@ static pthread_t *spawn_workers(struct kvm_vm *vm, struct kvm_vcpu **vcpus, TEST_ASSERT(info, "Failed to allocate vCPU gpa ranges"); nr_bytes = ((end_gpa - start_gpa) / nr_vcpus) & - ~((uint64_t)vm->page_size - 1); + ~((u64)vm->page_size - 1); TEST_ASSERT(nr_bytes, "C'mon, no way you have %d CPUs", nr_vcpus); for (i = 0, gpa = start_gpa; i < nr_vcpus; i++, gpa += nr_bytes) { @@ -278,11 +278,11 @@ int main(int argc, char *argv[]) * just below the 4gb boundary. This test could create memory at * 1gb-3gb,but it's simpler to skip straight to 4gb. */ - const uint64_t start_gpa = SZ_4G; + const u64 start_gpa = SZ_4G; const int first_slot = 1; struct timespec time_start, time_run1, time_reset, time_run2, time_ro, time_rw; - uint64_t max_gpa, gpa, slot_size, max_mem, i; + u64 max_gpa, gpa, slot_size, max_mem, i; int max_slots, slot, opt, fd; bool hugepages = false; struct kvm_vcpu **vcpus; @@ -347,7 +347,7 @@ int main(int argc, char *argv[]) /* Pre-fault the memory to avoid taking mmap_sem on guest page faults. */ for (i = 0; i < slot_size; i += vm->page_size) - ((uint8_t *)mem)[i] = 0xaa; + ((u8 *)mem)[i] = 0xaa; gpa = 0; for (slot = first_slot; slot < max_slots; slot++) { diff --git a/tools/testing/selftests/kvm/pre_fault_memory_test.c b/tools/testing/selftests/kvm/pre_fault_memory_test.c index f3de0386ba7b..fcb57fd034e6 100644 --- a/tools/testing/selftests/kvm/pre_fault_memory_test.c +++ b/tools/testing/selftests/kvm/pre_fault_memory_test.c @@ -17,13 +17,13 @@ #define TEST_NPAGES (TEST_SIZE / PAGE_SIZE) #define TEST_SLOT 10 -static void guest_code(uint64_t base_gva) +static void guest_code(u64 base_gva) { - volatile uint64_t val __used; + volatile u64 val __used; int i; for (i = 0; i < TEST_NPAGES; i++) { - uint64_t *src = (uint64_t *)(base_gva + i * PAGE_SIZE); + u64 *src = (u64 *)(base_gva + i * PAGE_SIZE); val = *src; } @@ -33,8 +33,8 @@ static void guest_code(uint64_t base_gva) struct slot_worker_data { struct kvm_vm *vm; - u64 gpa; - uint32_t flags; + gpa_t gpa; + u32 flags; bool worker_ready; bool prefault_ready; bool recreate_slot; @@ -161,7 +161,7 @@ static void pre_fault_memory(struct kvm_vcpu *vcpu, u64 base_gpa, u64 offset, static void __test_pre_fault_memory(unsigned long vm_type, bool private) { - uint64_t gpa, gva, alignment, guest_page_size; + gpa_t gpa, gva, alignment, guest_page_size; const struct vm_shape shape = { .mode = VM_MODE_DEFAULT, .type = vm_type, diff --git a/tools/testing/selftests/kvm/riscv/arch_timer.c b/tools/testing/selftests/kvm/riscv/arch_timer.c index f962fefc48fa..d67c918ee310 100644 --- a/tools/testing/selftests/kvm/riscv/arch_timer.c +++ b/tools/testing/selftests/kvm/riscv/arch_timer.c @@ -17,9 +17,9 @@ static int timer_irq = IRQ_S_TIMER; static void guest_irq_handler(struct pt_regs *regs) { - uint64_t xcnt, xcnt_diff_us, cmp; + u64 xcnt, xcnt_diff_us, cmp; unsigned int intid = regs->cause & ~CAUSE_IRQ_FLAG; - uint32_t cpu = guest_get_vcpuid(); + u32 cpu = guest_get_vcpuid(); struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu]; timer_irq_disable(); @@ -40,7 +40,7 @@ static void guest_irq_handler(struct pt_regs *regs) static void guest_run(struct test_vcpu_shared_data *shared_data) { - uint32_t irq_iter, config_iter; + u32 irq_iter, config_iter; shared_data->nr_iter = 0; shared_data->guest_stage = 0; @@ -66,7 +66,7 @@ static void guest_run(struct test_vcpu_shared_data *shared_data) static void guest_code(void) { - uint32_t cpu = guest_get_vcpuid(); + u32 cpu = guest_get_vcpuid(); struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu]; timer_irq_disable(); diff --git a/tools/testing/selftests/kvm/riscv/ebreak_test.c b/tools/testing/selftests/kvm/riscv/ebreak_test.c index 739d17befb5a..3f44b045a22e 100644 --- a/tools/testing/selftests/kvm/riscv/ebreak_test.c +++ b/tools/testing/selftests/kvm/riscv/ebreak_test.c @@ -8,10 +8,10 @@ #include "kvm_util.h" #include "ucall_common.h" -#define LABEL_ADDRESS(v) ((uint64_t)&(v)) +#define LABEL_ADDRESS(v) ((u64)&(v)) extern unsigned char sw_bp_1, sw_bp_2; -static uint64_t sw_bp_addr; +static u64 sw_bp_addr; static void guest_code(void) { @@ -37,7 +37,7 @@ int main(void) { struct kvm_vm *vm; struct kvm_vcpu *vcpu; - uint64_t pc; + u64 pc; struct kvm_guest_debug debug = { .control = KVM_GUESTDBG_ENABLE, }; diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 8d6b951434eb..8d6fdb5d38b8 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -162,7 +162,7 @@ bool check_reject_set(int err) } static int override_vector_reg_size(struct kvm_vcpu *vcpu, struct vcpu_reg_sublist *s, - uint64_t feature) + u64 feature) { unsigned long vlenb_reg = 0; int rc; @@ -197,7 +197,7 @@ void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c) { unsigned long isa_ext_state[KVM_RISCV_ISA_EXT_MAX] = { 0 }; struct vcpu_reg_sublist *s; - uint64_t feature; + u64 feature; int rc; for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c index cec1621ace23..e56a3dd6a51e 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -24,7 +24,7 @@ union sbi_pmu_ctr_info ctrinfo_arr[RISCV_MAX_PMU_COUNTERS]; /* Snapshot shared memory data */ #define PMU_SNAPSHOT_GPA_BASE BIT(30) static void *snapshot_gva; -static vm_paddr_t snapshot_gpa; +static gpa_t snapshot_gpa; static int vcpu_shared_irq_count; static int counter_in_use; @@ -86,7 +86,7 @@ unsigned long pmu_csr_read_num(int csr_num) #undef switchcase_csr_read } -static inline void dummy_func_loop(uint64_t iter) +static inline void dummy_func_loop(u64 iter) { int i = 0; @@ -259,7 +259,7 @@ static inline void verify_sbi_requirement_assert(void) __GUEST_ASSERT(0, "SBI implementation version doesn't support PMU Snapshot"); } -static void snapshot_set_shmem(vm_paddr_t gpa, unsigned long flags) +static void snapshot_set_shmem(gpa_t gpa, unsigned long flags) { unsigned long lo = (unsigned long)gpa; #if __riscv_xlen == 32 @@ -610,7 +610,7 @@ static void test_vm_setup_snapshot_mem(struct kvm_vm *vm, struct kvm_vcpu *vcpu) virt_map(vm, PMU_SNAPSHOT_GPA_BASE, PMU_SNAPSHOT_GPA_BASE, 1); snapshot_gva = (void *)(PMU_SNAPSHOT_GPA_BASE); - snapshot_gpa = addr_gva2gpa(vcpu->vm, (vm_vaddr_t)snapshot_gva); + snapshot_gpa = addr_gva2gpa(vcpu->vm, (gva_t)snapshot_gva); sync_global_to_guest(vcpu->vm, snapshot_gva); sync_global_to_guest(vcpu->vm, snapshot_gpa); } diff --git a/tools/testing/selftests/kvm/s390/debug_test.c b/tools/testing/selftests/kvm/s390/debug_test.c index ad8095968601..751c61c0f056 100644 --- a/tools/testing/selftests/kvm/s390/debug_test.c +++ b/tools/testing/selftests/kvm/s390/debug_test.c @@ -17,7 +17,7 @@ asm("int_handler:\n" "j .\n"); static struct kvm_vm *test_step_int_1(struct kvm_vcpu **vcpu, void *guest_code, - size_t new_psw_off, uint64_t *new_psw) + size_t new_psw_off, u64 *new_psw) { struct kvm_guest_debug debug = {}; struct kvm_regs regs; @@ -27,7 +27,7 @@ static struct kvm_vm *test_step_int_1(struct kvm_vcpu **vcpu, void *guest_code, vm = vm_create_with_one_vcpu(vcpu, guest_code); lowcore = addr_gpa2hva(vm, 0); new_psw[0] = (*vcpu)->run->psw_mask; - new_psw[1] = (uint64_t)int_handler; + new_psw[1] = (u64)int_handler; memcpy(lowcore + new_psw_off, new_psw, 16); vcpu_regs_get(*vcpu, ®s); regs.gprs[2] = -1; @@ -42,7 +42,7 @@ static struct kvm_vm *test_step_int_1(struct kvm_vcpu **vcpu, void *guest_code, static void test_step_int(void *guest_code, size_t new_psw_off) { struct kvm_vcpu *vcpu; - uint64_t new_psw[2]; + u64 new_psw[2]; struct kvm_vm *vm; vm = test_step_int_1(&vcpu, guest_code, new_psw_off, new_psw); @@ -79,7 +79,7 @@ static void test_step_pgm_diag(void) .u.pgm.code = PGM_SPECIFICATION, }; struct kvm_vcpu *vcpu; - uint64_t new_psw[2]; + u64 new_psw[2]; struct kvm_vm *vm; vm = test_step_int_1(&vcpu, test_step_pgm_diag_guest_code, diff --git a/tools/testing/selftests/kvm/s390/irq_routing.c b/tools/testing/selftests/kvm/s390/irq_routing.c index 7819a0af19a8..f3839284ac08 100644 --- a/tools/testing/selftests/kvm/s390/irq_routing.c +++ b/tools/testing/selftests/kvm/s390/irq_routing.c @@ -27,7 +27,7 @@ static void test(void) struct kvm_irq_routing *routing; struct kvm_vcpu *vcpu; struct kvm_vm *vm; - vm_paddr_t mem; + gpa_t mem; int ret; struct kvm_irq_routing_entry ue = { diff --git a/tools/testing/selftests/kvm/s390/memop.c b/tools/testing/selftests/kvm/s390/memop.c index 4374b4cd2a80..0244848621b3 100644 --- a/tools/testing/selftests/kvm/s390/memop.c +++ b/tools/testing/selftests/kvm/s390/memop.c @@ -34,7 +34,7 @@ enum mop_access_mode { struct mop_desc { uintptr_t gaddr; uintptr_t gaddr_v; - uint64_t set_flags; + u64 set_flags; unsigned int f_check : 1; unsigned int f_inject : 1; unsigned int f_key : 1; @@ -42,19 +42,19 @@ struct mop_desc { unsigned int _set_flags : 1; unsigned int _sida_offset : 1; unsigned int _ar : 1; - uint32_t size; + u32 size; enum mop_target target; enum mop_access_mode mode; void *buf; - uint32_t sida_offset; + u32 sida_offset; void *old; - uint8_t old_value[16]; + u8 old_value[16]; bool *cmpxchg_success; - uint8_t ar; - uint8_t key; + u8 ar; + u8 key; }; -const uint8_t NO_KEY = 0xff; +const u8 NO_KEY = 0xff; static struct kvm_s390_mem_op ksmo_from_desc(struct mop_desc *desc) { @@ -85,7 +85,7 @@ static struct kvm_s390_mem_op ksmo_from_desc(struct mop_desc *desc) ksmo.op = KVM_S390_MEMOP_ABSOLUTE_WRITE; if (desc->mode == CMPXCHG) { ksmo.op = KVM_S390_MEMOP_ABSOLUTE_CMPXCHG; - ksmo.old_addr = (uint64_t)desc->old; + ksmo.old_addr = (u64)desc->old; memcpy(desc->old_value, desc->old, desc->size); } break; @@ -230,8 +230,8 @@ static void memop_ioctl(struct test_info info, struct kvm_s390_mem_op *ksmo, #define CR0_FETCH_PROTECTION_OVERRIDE (1UL << (63 - 38)) #define CR0_STORAGE_PROTECTION_OVERRIDE (1UL << (63 - 39)) -static uint8_t __aligned(PAGE_SIZE) mem1[65536]; -static uint8_t __aligned(PAGE_SIZE) mem2[65536]; +static u8 __aligned(PAGE_SIZE) mem1[65536]; +static u8 __aligned(PAGE_SIZE) mem2[65536]; struct test_default { struct kvm_vm *kvm_vm; @@ -296,7 +296,7 @@ static void prepare_mem12(void) TEST_ASSERT(!memcmp(p1, p2, size), "Memory contents do not match!") static void default_write_read(struct test_info copy_cpu, struct test_info mop_cpu, - enum mop_target mop_target, uint32_t size, uint8_t key) + enum mop_target mop_target, u32 size, u8 key) { prepare_mem12(); CHECK_N_DO(MOP, mop_cpu, mop_target, WRITE, mem1, size, @@ -308,7 +308,7 @@ static void default_write_read(struct test_info copy_cpu, struct test_info mop_c } static void default_read(struct test_info copy_cpu, struct test_info mop_cpu, - enum mop_target mop_target, uint32_t size, uint8_t key) + enum mop_target mop_target, u32 size, u8 key) { prepare_mem12(); CHECK_N_DO(MOP, mop_cpu, mop_target, WRITE, mem1, size, GADDR_V(mem1)); @@ -318,12 +318,12 @@ static void default_read(struct test_info copy_cpu, struct test_info mop_cpu, ASSERT_MEM_EQ(mem1, mem2, size); } -static void default_cmpxchg(struct test_default *test, uint8_t key) +static void default_cmpxchg(struct test_default *test, u8 key) { for (int size = 1; size <= 16; size *= 2) { for (int offset = 0; offset < 16; offset += size) { - uint8_t __aligned(16) new[16] = {}; - uint8_t __aligned(16) old[16]; + u8 __aligned(16) new[16] = {}; + u8 __aligned(16) old[16]; bool succ; prepare_mem12(); @@ -400,7 +400,7 @@ static void test_copy_access_register(void) kvm_vm_free(t.kvm_vm); } -static void set_storage_key_range(void *addr, size_t len, uint8_t key) +static void set_storage_key_range(void *addr, size_t len, u8 key) { uintptr_t _addr, abs, i; int not_mapped = 0; @@ -483,13 +483,13 @@ static __uint128_t cut_to_size(int size, __uint128_t val) { switch (size) { case 1: - return (uint8_t)val; + return (u8)val; case 2: - return (uint16_t)val; + return (u16)val; case 4: - return (uint32_t)val; + return (u32)val; case 8: - return (uint64_t)val; + return (u64)val; case 16: return val; } @@ -501,10 +501,10 @@ static bool popcount_eq(__uint128_t a, __uint128_t b) { unsigned int count_a, count_b; - count_a = __builtin_popcountl((uint64_t)(a >> 64)) + - __builtin_popcountl((uint64_t)a); - count_b = __builtin_popcountl((uint64_t)(b >> 64)) + - __builtin_popcountl((uint64_t)b); + count_a = __builtin_popcountl((u64)(a >> 64)) + + __builtin_popcountl((u64)a); + count_b = __builtin_popcountl((u64)(b >> 64)) + + __builtin_popcountl((u64)b); return count_a == count_b; } @@ -553,7 +553,7 @@ static __uint128_t permutate_bits(bool guest, int i, int size, __uint128_t old) if (swap) { int i, j; __uint128_t new; - uint8_t byte0, byte1; + u8 byte0, byte1; rand = rand * 3 + 1; i = rand % size; @@ -585,28 +585,28 @@ static bool _cmpxchg(int size, void *target, __uint128_t *old_addr, __uint128_t switch (size) { case 4: { - uint32_t old = *old_addr; + u32 old = *old_addr; asm volatile ("cs %[old],%[new],%[address]" : [old] "+d" (old), - [address] "+Q" (*(uint32_t *)(target)) - : [new] "d" ((uint32_t)new) + [address] "+Q" (*(u32 *)(target)) + : [new] "d" ((u32)new) : "cc" ); - ret = old == (uint32_t)*old_addr; + ret = old == (u32)*old_addr; *old_addr = old; return ret; } case 8: { - uint64_t old = *old_addr; + u64 old = *old_addr; asm volatile ("csg %[old],%[new],%[address]" : [old] "+d" (old), - [address] "+Q" (*(uint64_t *)(target)) - : [new] "d" ((uint64_t)new) + [address] "+Q" (*(u64 *)(target)) + : [new] "d" ((u64)new) : "cc" ); - ret = old == (uint64_t)*old_addr; + ret = old == (u64)*old_addr; *old_addr = old; return ret; } @@ -811,10 +811,10 @@ static void test_errors_cmpxchg_key(void) static void test_termination(void) { struct test_default t = test_default_init(guest_error_key); - uint64_t prefix; - uint64_t teid; - uint64_t teid_mask = BIT(63 - 56) | BIT(63 - 60) | BIT(63 - 61); - uint64_t psw[2]; + u64 prefix; + u64 teid; + u64 teid_mask = BIT(63 - 56) | BIT(63 - 60) | BIT(63 - 61); + u64 psw[2]; HOST_SYNC(t.vcpu, STAGE_INITED); HOST_SYNC(t.vcpu, STAGE_SKEYS_SET); @@ -855,7 +855,7 @@ static void test_errors_key_storage_prot_override(void) kvm_vm_free(t.kvm_vm); } -const uint64_t last_page_addr = -PAGE_SIZE; +const u64 last_page_addr = -PAGE_SIZE; static void guest_copy_key_fetch_prot_override(void) { @@ -878,10 +878,10 @@ static void guest_copy_key_fetch_prot_override(void) static void test_copy_key_fetch_prot_override(void) { struct test_default t = test_default_init(guest_copy_key_fetch_prot_override); - vm_vaddr_t guest_0_page, guest_last_page; + gva_t guest_0_page, guest_last_page; - guest_0_page = vm_vaddr_alloc(t.kvm_vm, PAGE_SIZE, 0); - guest_last_page = vm_vaddr_alloc(t.kvm_vm, PAGE_SIZE, last_page_addr); + guest_0_page = vm_alloc(t.kvm_vm, PAGE_SIZE, 0); + guest_last_page = vm_alloc(t.kvm_vm, PAGE_SIZE, last_page_addr); if (guest_0_page != 0 || guest_last_page != last_page_addr) { print_skip("did not allocate guest pages at required positions"); goto out; @@ -917,10 +917,10 @@ static void test_copy_key_fetch_prot_override(void) static void test_errors_key_fetch_prot_override_not_enabled(void) { struct test_default t = test_default_init(guest_copy_key_fetch_prot_override); - vm_vaddr_t guest_0_page, guest_last_page; + gva_t guest_0_page, guest_last_page; - guest_0_page = vm_vaddr_alloc(t.kvm_vm, PAGE_SIZE, 0); - guest_last_page = vm_vaddr_alloc(t.kvm_vm, PAGE_SIZE, last_page_addr); + guest_0_page = vm_alloc(t.kvm_vm, PAGE_SIZE, 0); + guest_last_page = vm_alloc(t.kvm_vm, PAGE_SIZE, last_page_addr); if (guest_0_page != 0 || guest_last_page != last_page_addr) { print_skip("did not allocate guest pages at required positions"); goto out; @@ -938,10 +938,10 @@ static void test_errors_key_fetch_prot_override_not_enabled(void) static void test_errors_key_fetch_prot_override_enabled(void) { struct test_default t = test_default_init(guest_copy_key_fetch_prot_override); - vm_vaddr_t guest_0_page, guest_last_page; + gva_t guest_0_page, guest_last_page; - guest_0_page = vm_vaddr_alloc(t.kvm_vm, PAGE_SIZE, 0); - guest_last_page = vm_vaddr_alloc(t.kvm_vm, PAGE_SIZE, last_page_addr); + guest_0_page = vm_alloc(t.kvm_vm, PAGE_SIZE, 0); + guest_last_page = vm_alloc(t.kvm_vm, PAGE_SIZE, last_page_addr); if (guest_0_page != 0 || guest_last_page != last_page_addr) { print_skip("did not allocate guest pages at required positions"); goto out; diff --git a/tools/testing/selftests/kvm/s390/resets.c b/tools/testing/selftests/kvm/s390/resets.c index b58f75b381e5..e3c7a2f148f9 100644 --- a/tools/testing/selftests/kvm/s390/resets.c +++ b/tools/testing/selftests/kvm/s390/resets.c @@ -20,7 +20,7 @@ struct kvm_s390_irq buf[ARBITRARY_NON_ZERO_VCPU_ID + LOCAL_IRQS]; -static uint8_t regs_null[512]; +static u8 regs_null[512]; static void guest_code_initial(void) { @@ -57,9 +57,9 @@ static void guest_code_initial(void) ); } -static void test_one_reg(struct kvm_vcpu *vcpu, uint64_t id, uint64_t value) +static void test_one_reg(struct kvm_vcpu *vcpu, u64 id, u64 value) { - uint64_t eval_reg; + u64 eval_reg; eval_reg = vcpu_get_reg(vcpu, id); TEST_ASSERT(eval_reg == value, "value == 0x%lx", value); diff --git a/tools/testing/selftests/kvm/s390/shared_zeropage_test.c b/tools/testing/selftests/kvm/s390/shared_zeropage_test.c index bba0d9a6dcc8..a9e5a01200b8 100644 --- a/tools/testing/selftests/kvm/s390/shared_zeropage_test.c +++ b/tools/testing/selftests/kvm/s390/shared_zeropage_test.c @@ -13,7 +13,7 @@ #include "kselftest.h" #include "ucall_common.h" -static void set_storage_key(void *addr, uint8_t skey) +static void set_storage_key(void *addr, u8 skey) { asm volatile("sske %0,%1" : : "d" (skey), "a" (addr)); } diff --git a/tools/testing/selftests/kvm/s390/tprot.c b/tools/testing/selftests/kvm/s390/tprot.c index 12d5e1cb62e3..8054d2b178f0 100644 --- a/tools/testing/selftests/kvm/s390/tprot.c +++ b/tools/testing/selftests/kvm/s390/tprot.c @@ -14,12 +14,12 @@ #define CR0_FETCH_PROTECTION_OVERRIDE (1UL << (63 - 38)) #define CR0_STORAGE_PROTECTION_OVERRIDE (1UL << (63 - 39)) -static __aligned(PAGE_SIZE) uint8_t pages[2][PAGE_SIZE]; -static uint8_t *const page_store_prot = pages[0]; -static uint8_t *const page_fetch_prot = pages[1]; +static __aligned(PAGE_SIZE) u8 pages[2][PAGE_SIZE]; +static u8 *const page_store_prot = pages[0]; +static u8 *const page_fetch_prot = pages[1]; /* Nonzero return value indicates that address not mapped */ -static int set_storage_key(void *addr, uint8_t key) +static int set_storage_key(void *addr, u8 key) { int not_mapped = 0; @@ -44,9 +44,9 @@ enum permission { TRANSL_UNAVAIL = 3, }; -static enum permission test_protection(void *addr, uint8_t key) +static enum permission test_protection(void *addr, u8 key) { - uint64_t mask; + u64 mask; asm volatile ( "tprot %[addr], 0(%[key])\n" @@ -72,7 +72,7 @@ enum stage { struct test { enum stage stage; void *addr; - uint8_t key; + u8 key; enum permission expected; } tests[] = { /* @@ -146,7 +146,7 @@ static enum stage perform_next_stage(int *i, bool mapped_0) /* * Some fetch protection override tests require that page 0 * be mapped, however, when the hosts tries to map that page via - * vm_vaddr_alloc, it may happen that some other page gets mapped + * vm_alloc, it may happen that some other page gets mapped * instead. * In order to skip these tests we detect this inside the guest */ @@ -207,7 +207,7 @@ int main(int argc, char *argv[]) struct kvm_vcpu *vcpu; struct kvm_vm *vm; struct kvm_run *run; - vm_vaddr_t guest_0_page; + gva_t guest_0_page; ksft_print_header(); ksft_set_plan(STAGE_END); @@ -216,10 +216,10 @@ int main(int argc, char *argv[]) run = vcpu->run; HOST_SYNC(vcpu, STAGE_INIT_SIMPLE); - mprotect(addr_gva2hva(vm, (vm_vaddr_t)pages), PAGE_SIZE * 2, PROT_READ); + mprotect(addr_gva2hva(vm, (gva_t)pages), PAGE_SIZE * 2, PROT_READ); HOST_SYNC(vcpu, TEST_SIMPLE); - guest_0_page = vm_vaddr_alloc(vm, PAGE_SIZE, 0); + guest_0_page = vm_alloc(vm, PAGE_SIZE, 0); if (guest_0_page != 0) { /* Use NO_TAP so we don't get a PASS print */ HOST_SYNC_NO_TAP(vcpu, STAGE_INIT_FETCH_PROT_OVERRIDE); @@ -229,7 +229,7 @@ int main(int argc, char *argv[]) HOST_SYNC(vcpu, STAGE_INIT_FETCH_PROT_OVERRIDE); } if (guest_0_page == 0) - mprotect(addr_gva2hva(vm, (vm_vaddr_t)0), PAGE_SIZE, PROT_READ); + mprotect(addr_gva2hva(vm, (gva_t)0), PAGE_SIZE, PROT_READ); run->s.regs.crs[0] |= CR0_FETCH_PROTECTION_OVERRIDE; run->kvm_dirty_regs = KVM_SYNC_CRS; HOST_SYNC(vcpu, TEST_FETCH_PROT_OVERRIDE); diff --git a/tools/testing/selftests/kvm/s390/ucontrol_test.c b/tools/testing/selftests/kvm/s390/ucontrol_test.c index 50bc1c38225a..b8c6f37b53e0 100644 --- a/tools/testing/selftests/kvm/s390/ucontrol_test.c +++ b/tools/testing/selftests/kvm/s390/ucontrol_test.c @@ -111,7 +111,7 @@ FIXTURE(uc_kvm) uintptr_t base_hva; uintptr_t code_hva; int kvm_run_size; - vm_paddr_t pgd; + gpa_t pgd; void *vm_mem; int vcpu_fd; int kvm_fd; @@ -269,7 +269,7 @@ TEST(uc_cap_hpage) } /* calculate host virtual addr from guest physical addr */ -static void *gpa2hva(FIXTURE_DATA(uc_kvm) *self, u64 gpa) +static void *gpa2hva(FIXTURE_DATA(uc_kvm) *self, gpa_t gpa) { return (void *)(self->base_hva - self->base_gpa + gpa); } @@ -571,7 +571,7 @@ TEST_F(uc_kvm, uc_skey) { struct kvm_s390_sie_block *sie_block = self->sie_block; struct kvm_sync_regs *sync_regs = &self->run->s.regs; - u64 test_vaddr = VM_MEM_SIZE - (SZ_1M / 2); + u64 test_gva = VM_MEM_SIZE - (SZ_1M / 2); struct kvm_run *run = self->run; const u8 skeyvalue = 0x34; @@ -583,7 +583,7 @@ TEST_F(uc_kvm, uc_skey) /* set register content for test_skey_asm to access not mapped memory */ sync_regs->gprs[1] = skeyvalue; sync_regs->gprs[5] = self->base_gpa; - sync_regs->gprs[6] = test_vaddr; + sync_regs->gprs[6] = test_gva; run->kvm_dirty_regs |= KVM_SYNC_GPRS; /* DAT disabled + 64 bit mode */ diff --git a/tools/testing/selftests/kvm/set_memory_region_test.c b/tools/testing/selftests/kvm/set_memory_region_test.c index a398dc3a8c4b..9b919a231c93 100644 --- a/tools/testing/selftests/kvm/set_memory_region_test.c +++ b/tools/testing/selftests/kvm/set_memory_region_test.c @@ -30,19 +30,19 @@ #define MEM_REGION_GPA 0xc0000000 #define MEM_REGION_SLOT 10 -static const uint64_t MMIO_VAL = 0xbeefull; +static const u64 MMIO_VAL = 0xbeefull; -extern const uint64_t final_rip_start; -extern const uint64_t final_rip_end; +extern const u64 final_rip_start; +extern const u64 final_rip_end; static sem_t vcpu_ready; -static inline uint64_t guest_spin_on_val(uint64_t spin_val) +static inline u64 guest_spin_on_val(u64 spin_val) { - uint64_t val; + u64 val; do { - val = READ_ONCE(*((uint64_t *)MEM_REGION_GPA)); + val = READ_ONCE(*((u64 *)MEM_REGION_GPA)); } while (val == spin_val); GUEST_SYNC(0); @@ -54,7 +54,7 @@ static void *vcpu_worker(void *data) struct kvm_vcpu *vcpu = data; struct kvm_run *run = vcpu->run; struct ucall uc; - uint64_t cmd; + u64 cmd; /* * Loop until the guest is done. Re-enter the guest on all MMIO exits, @@ -111,8 +111,8 @@ static struct kvm_vm *spawn_vm(struct kvm_vcpu **vcpu, pthread_t *vcpu_thread, void *guest_code) { struct kvm_vm *vm; - uint64_t *hva; - uint64_t gpa; + u64 *hva; + gpa_t gpa; vm = vm_create_with_one_vcpu(vcpu, guest_code); @@ -144,7 +144,7 @@ static struct kvm_vm *spawn_vm(struct kvm_vcpu **vcpu, pthread_t *vcpu_thread, static void guest_code_move_memory_region(void) { - uint64_t val; + u64 val; GUEST_SYNC(0); @@ -180,7 +180,7 @@ static void test_move_memory_region(bool disable_slot_zap_quirk) pthread_t vcpu_thread; struct kvm_vcpu *vcpu; struct kvm_vm *vm; - uint64_t *hva; + u64 *hva; vm = spawn_vm(&vcpu, &vcpu_thread, guest_code_move_memory_region); @@ -224,7 +224,7 @@ static void test_move_memory_region(bool disable_slot_zap_quirk) static void guest_code_delete_memory_region(void) { struct desc_ptr idt; - uint64_t val; + u64 val; /* * Clobber the IDT so that a #PF due to the memory region being deleted @@ -345,8 +345,8 @@ static void test_zero_memory_regions(void) static void test_invalid_memory_region_flags(void) { - uint32_t supported_flags = KVM_MEM_LOG_DIRTY_PAGES; - const uint32_t v2_only_flags = KVM_MEM_GUEST_MEMFD; + u32 supported_flags = KVM_MEM_LOG_DIRTY_PAGES; + const u32 v2_only_flags = KVM_MEM_GUEST_MEMFD; struct kvm_vm *vm; int r, i; @@ -410,8 +410,8 @@ static void test_add_max_memory_regions(void) { int ret; struct kvm_vm *vm; - uint32_t max_mem_slots; - uint32_t slot; + u32 max_mem_slots; + u32 slot; void *mem, *mem_aligned, *mem_extra; size_t alignment = 1; @@ -434,16 +434,16 @@ static void test_add_max_memory_regions(void) for (slot = 0; slot < max_mem_slots; slot++) vm_set_user_memory_region(vm, slot, 0, - ((uint64_t)slot * MEM_REGION_SIZE), + ((u64)slot * MEM_REGION_SIZE), MEM_REGION_SIZE, - mem_aligned + (uint64_t)slot * MEM_REGION_SIZE); + mem_aligned + (u64)slot * MEM_REGION_SIZE); /* Check it cannot be added memory slots beyond the limit */ mem_extra = kvm_mmap(MEM_REGION_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1); ret = __vm_set_user_memory_region(vm, max_mem_slots, 0, - (uint64_t)max_mem_slots * MEM_REGION_SIZE, + (u64)max_mem_slots * MEM_REGION_SIZE, MEM_REGION_SIZE, mem_extra); TEST_ASSERT(ret == -1 && errno == EINVAL, "Adding one more memory slot should fail with EINVAL"); @@ -556,7 +556,7 @@ static void guest_code_mmio_during_vectoring(void) set_idt(&idt_desc); /* Generate a #GP by dereferencing a non-canonical address */ - *((uint8_t *)NONCANONICAL) = 0x1; + *((u8 *)NONCANONICAL) = 0x1; GUEST_ASSERT(0); } diff --git a/tools/testing/selftests/kvm/steal_time.c b/tools/testing/selftests/kvm/steal_time.c index efe56a10d13e..7df2bc8eec02 100644 --- a/tools/testing/selftests/kvm/steal_time.c +++ b/tools/testing/selftests/kvm/steal_time.c @@ -25,7 +25,7 @@ #define ST_GPA_BASE (1 << 30) static void *st_gva[NR_VCPUS]; -static uint64_t guest_stolen_time[NR_VCPUS]; +static u64 guest_stolen_time[NR_VCPUS]; #if defined(__x86_64__) @@ -42,9 +42,9 @@ static void check_status(struct kvm_steal_time *st) static void guest_code(int cpu) { struct kvm_steal_time *st = st_gva[cpu]; - uint32_t version; + u32 version; - GUEST_ASSERT_EQ(rdmsr(MSR_KVM_STEAL_TIME), ((uint64_t)st_gva[cpu] | KVM_MSR_ENABLED)); + GUEST_ASSERT_EQ(rdmsr(MSR_KVM_STEAL_TIME), ((u64)st_gva[cpu] | KVM_MSR_ENABLED)); memset(st, 0, sizeof(*st)); GUEST_SYNC(0); @@ -67,7 +67,7 @@ static bool is_steal_time_supported(struct kvm_vcpu *vcpu) return kvm_cpu_has(X86_FEATURE_KVM_STEAL_TIME); } -static void steal_time_init(struct kvm_vcpu *vcpu, uint32_t i) +static void steal_time_init(struct kvm_vcpu *vcpu, u32 i) { /* ST_GPA_BASE is identity mapped */ st_gva[i] = (void *)(ST_GPA_BASE + i * STEAL_TIME_SIZE); @@ -76,7 +76,7 @@ static void steal_time_init(struct kvm_vcpu *vcpu, uint32_t i) vcpu_set_msr(vcpu, MSR_KVM_STEAL_TIME, (ulong)st_gva[i] | KVM_MSR_ENABLED); } -static void steal_time_dump(struct kvm_vm *vm, uint32_t vcpu_idx) +static void steal_time_dump(struct kvm_vm *vm, u32 vcpu_idx) { struct kvm_steal_time *st = addr_gva2hva(vm, (ulong)st_gva[vcpu_idx]); @@ -118,12 +118,12 @@ static void check_steal_time_uapi(void) #define PV_TIME_ST 0xc5000021 struct st_time { - uint32_t rev; - uint32_t attr; - uint64_t st_time; + u32 rev; + u32 attr; + u64 st_time; }; -static int64_t smccc(uint32_t func, uint64_t arg) +static s64 smccc(u32 func, u64 arg) { struct arm_smccc_res res; @@ -140,7 +140,7 @@ static void check_status(struct st_time *st) static void guest_code(int cpu) { struct st_time *st; - int64_t status; + s64 status; status = smccc(SMCCC_ARCH_FEATURES, PV_TIME_FEATURES); GUEST_ASSERT_EQ(status, 0); @@ -175,15 +175,15 @@ static bool is_steal_time_supported(struct kvm_vcpu *vcpu) return !__vcpu_ioctl(vcpu, KVM_HAS_DEVICE_ATTR, &dev); } -static void steal_time_init(struct kvm_vcpu *vcpu, uint32_t i) +static void steal_time_init(struct kvm_vcpu *vcpu, u32 i) { struct kvm_vm *vm = vcpu->vm; - uint64_t st_ipa; + u64 st_ipa; struct kvm_device_attr dev = { .group = KVM_ARM_VCPU_PVTIME_CTRL, .attr = KVM_ARM_VCPU_PVTIME_IPA, - .addr = (uint64_t)&st_ipa, + .addr = (u64)&st_ipa, }; /* ST_GPA_BASE is identity mapped */ @@ -194,7 +194,7 @@ static void steal_time_init(struct kvm_vcpu *vcpu, uint32_t i) vcpu_ioctl(vcpu, KVM_SET_DEVICE_ATTR, &dev); } -static void steal_time_dump(struct kvm_vm *vm, uint32_t vcpu_idx) +static void steal_time_dump(struct kvm_vm *vm, u32 vcpu_idx) { struct st_time *st = addr_gva2hva(vm, (ulong)st_gva[vcpu_idx]); @@ -208,7 +208,7 @@ static void check_steal_time_uapi(void) { struct kvm_vm *vm; struct kvm_vcpu *vcpu; - uint64_t st_ipa; + u64 st_ipa; int ret; vm = vm_create_with_one_vcpu(&vcpu, NULL); @@ -216,7 +216,7 @@ static void check_steal_time_uapi(void) struct kvm_device_attr dev = { .group = KVM_ARM_VCPU_PVTIME_CTRL, .attr = KVM_ARM_VCPU_PVTIME_IPA, - .addr = (uint64_t)&st_ipa, + .addr = (u64)&st_ipa, }; vcpu_ioctl(vcpu, KVM_HAS_DEVICE_ATTR, &dev); @@ -239,17 +239,17 @@ static void check_steal_time_uapi(void) /* SBI STA shmem must have 64-byte alignment */ #define STEAL_TIME_SIZE ((sizeof(struct sta_struct) + 63) & ~63) -static vm_paddr_t st_gpa[NR_VCPUS]; +static gpa_t st_gpa[NR_VCPUS]; struct sta_struct { - uint32_t sequence; - uint32_t flags; - uint64_t steal; - uint8_t preempted; - uint8_t pad[47]; + u32 sequence; + u32 flags; + u64 steal; + u8 preempted; + u8 pad[47]; } __packed; -static void sta_set_shmem(vm_paddr_t gpa, unsigned long flags) +static void sta_set_shmem(gpa_t gpa, unsigned long flags) { unsigned long lo = (unsigned long)gpa; #if __riscv_xlen == 32 @@ -272,7 +272,7 @@ static void check_status(struct sta_struct *st) static void guest_code(int cpu) { struct sta_struct *st = st_gva[cpu]; - uint32_t sequence; + u32 sequence; long out_val = 0; bool probe; @@ -297,7 +297,7 @@ static void guest_code(int cpu) static bool is_steal_time_supported(struct kvm_vcpu *vcpu) { - uint64_t id = RISCV_SBI_EXT_REG(KVM_RISCV_SBI_EXT_STA); + u64 id = RISCV_SBI_EXT_REG(KVM_RISCV_SBI_EXT_STA); unsigned long enabled = vcpu_get_reg(vcpu, id); TEST_ASSERT(enabled == 0 || enabled == 1, "Expected boolean result"); @@ -305,16 +305,16 @@ static bool is_steal_time_supported(struct kvm_vcpu *vcpu) return enabled; } -static void steal_time_init(struct kvm_vcpu *vcpu, uint32_t i) +static void steal_time_init(struct kvm_vcpu *vcpu, u32 i) { /* ST_GPA_BASE is identity mapped */ st_gva[i] = (void *)(ST_GPA_BASE + i * STEAL_TIME_SIZE); - st_gpa[i] = addr_gva2gpa(vcpu->vm, (vm_vaddr_t)st_gva[i]); + st_gpa[i] = addr_gva2gpa(vcpu->vm, (gva_t)st_gva[i]); sync_global_to_guest(vcpu->vm, st_gva[i]); sync_global_to_guest(vcpu->vm, st_gpa[i]); } -static void steal_time_dump(struct kvm_vm *vm, uint32_t vcpu_idx) +static void steal_time_dump(struct kvm_vm *vm, u32 vcpu_idx) { struct sta_struct *st = addr_gva2hva(vm, (ulong)st_gva[vcpu_idx]); int i; @@ -335,7 +335,7 @@ static void check_steal_time_uapi(void) struct kvm_vm *vm; struct kvm_vcpu *vcpu; struct kvm_one_reg reg; - uint64_t shmem; + u64 shmem; int ret; vm = vm_create_with_one_vcpu(&vcpu, NULL); @@ -345,7 +345,7 @@ static void check_steal_time_uapi(void) KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_lo); - reg.addr = (uint64_t)&shmem; + reg.addr = (u64)&shmem; shmem = ST_GPA_BASE + 1; ret = __vcpu_ioctl(vcpu, KVM_SET_ONE_REG, ®); @@ -388,7 +388,7 @@ static void check_status(struct kvm_steal_time *st) static void guest_code(int cpu) { - uint32_t version; + u32 version; struct kvm_steal_time *st = st_gva[cpu]; memset(st, 0, sizeof(*st)); @@ -410,11 +410,11 @@ static void guest_code(int cpu) static bool is_steal_time_supported(struct kvm_vcpu *vcpu) { int err; - uint64_t val; + u64 val; struct kvm_device_attr attr = { .group = KVM_LOONGARCH_VCPU_CPUCFG, .attr = CPUCFG_KVM_FEATURE, - .addr = (uint64_t)&val, + .addr = (u64)&val, }; err = __vcpu_ioctl(vcpu, KVM_HAS_DEVICE_ATTR, &attr); @@ -428,15 +428,15 @@ static bool is_steal_time_supported(struct kvm_vcpu *vcpu) return val & BIT(KVM_FEATURE_STEAL_TIME); } -static void steal_time_init(struct kvm_vcpu *vcpu, uint32_t i) +static void steal_time_init(struct kvm_vcpu *vcpu, u32 i) { int err; - uint64_t st_gpa; + u64 st_gpa; struct kvm_vm *vm = vcpu->vm; struct kvm_device_attr attr = { .group = KVM_LOONGARCH_VCPU_PVTIME_CTRL, .attr = KVM_LOONGARCH_VCPU_PVTIME_GPA, - .addr = (uint64_t)&st_gpa, + .addr = (u64)&st_gpa, }; /* ST_GPA_BASE is identity mapped */ @@ -451,7 +451,7 @@ static void steal_time_init(struct kvm_vcpu *vcpu, uint32_t i) TEST_ASSERT(err == 0, "Fail to set PV stealtime GPA"); } -static void steal_time_dump(struct kvm_vm *vm, uint32_t vcpu_idx) +static void steal_time_dump(struct kvm_vm *vm, u32 vcpu_idx) { struct kvm_steal_time *st = addr_gva2hva(vm, (ulong)st_gva[vcpu_idx]); @@ -461,6 +461,11 @@ static void steal_time_dump(struct kvm_vm *vm, uint32_t vcpu_idx) ksft_print_msg(" version: %d\n", st->version); ksft_print_msg(" preempted: %d\n", st->preempted); } + +static void check_steal_time_uapi(void) +{ + +} #endif static void *do_steal_time(void *arg) diff --git a/tools/testing/selftests/kvm/system_counter_offset_test.c b/tools/testing/selftests/kvm/system_counter_offset_test.c index 513d421a9bff..dc5e30b7b77f 100644 --- a/tools/testing/selftests/kvm/system_counter_offset_test.c +++ b/tools/testing/selftests/kvm/system_counter_offset_test.c @@ -17,7 +17,7 @@ #ifdef __x86_64__ struct test_case { - uint64_t tsc_offset; + u64 tsc_offset; }; static struct test_case test_cases[] = { @@ -39,12 +39,12 @@ static void setup_system_counter(struct kvm_vcpu *vcpu, struct test_case *test) &test->tsc_offset); } -static uint64_t guest_read_system_counter(struct test_case *test) +static u64 guest_read_system_counter(struct test_case *test) { return rdtsc(); } -static uint64_t host_read_guest_system_counter(struct test_case *test) +static u64 host_read_guest_system_counter(struct test_case *test) { return rdtsc() + test->tsc_offset; } @@ -69,9 +69,9 @@ static void guest_main(void) } } -static void handle_sync(struct ucall *uc, uint64_t start, uint64_t end) +static void handle_sync(struct ucall *uc, u64 start, u64 end) { - uint64_t obs = uc->args[2]; + u64 obs = uc->args[2]; TEST_ASSERT(start <= obs && obs <= end, "unexpected system counter value: %"PRIu64" expected range: [%"PRIu64", %"PRIu64"]", @@ -88,7 +88,7 @@ static void handle_abort(struct ucall *uc) static void enter_guest(struct kvm_vcpu *vcpu) { - uint64_t start, end; + u64 start, end; struct ucall uc; int i; diff --git a/tools/testing/selftests/kvm/x86/amx_test.c b/tools/testing/selftests/kvm/x86/amx_test.c index 37b166260ee3..4e63da2b1889 100644 --- a/tools/testing/selftests/kvm/x86/amx_test.c +++ b/tools/testing/selftests/kvm/x86/amx_test.c @@ -80,10 +80,10 @@ static inline void __tilerelease(void) asm volatile(".byte 0xc4, 0xe2, 0x78, 0x49, 0xc0" ::); } -static inline void __xsavec(struct xstate *xstate, uint64_t rfbm) +static inline void __xsavec(struct xstate *xstate, u64 rfbm) { - uint32_t rfbm_lo = rfbm; - uint32_t rfbm_hi = rfbm >> 32; + u32 rfbm_lo = rfbm; + u32 rfbm_hi = rfbm >> 32; asm volatile("xsavec (%%rdi)" : : "D" (xstate), "a" (rfbm_lo), "d" (rfbm_hi) @@ -236,7 +236,7 @@ int main(int argc, char *argv[]) struct kvm_x86_state *state; struct kvm_x86_state *tile_state = NULL; int xsave_restore_size; - vm_vaddr_t amx_cfg, tiledata, xstate; + gva_t amx_cfg, tiledata, xstate; struct ucall uc; int ret; @@ -263,15 +263,15 @@ int main(int argc, char *argv[]) vcpu_regs_get(vcpu, ®s1); /* amx cfg for guest_code */ - amx_cfg = vm_vaddr_alloc_page(vm); + amx_cfg = vm_alloc_page(vm); memset(addr_gva2hva(vm, amx_cfg), 0x0, getpagesize()); /* amx tiledata for guest_code */ - tiledata = vm_vaddr_alloc_pages(vm, 2); + tiledata = vm_alloc_pages(vm, 2); memset(addr_gva2hva(vm, tiledata), rand() | 1, 2 * getpagesize()); /* XSAVE state for guest_code */ - xstate = vm_vaddr_alloc_pages(vm, DIV_ROUND_UP(XSAVE_SIZE, PAGE_SIZE)); + xstate = vm_alloc_pages(vm, DIV_ROUND_UP(XSAVE_SIZE, PAGE_SIZE)); memset(addr_gva2hva(vm, xstate), 0, PAGE_SIZE * DIV_ROUND_UP(XSAVE_SIZE, PAGE_SIZE)); vcpu_args_set(vcpu, 3, amx_cfg, tiledata, xstate); diff --git a/tools/testing/selftests/kvm/x86/aperfmperf_test.c b/tools/testing/selftests/kvm/x86/aperfmperf_test.c index 8b15a13df939..c91660103137 100644 --- a/tools/testing/selftests/kvm/x86/aperfmperf_test.c +++ b/tools/testing/selftests/kvm/x86/aperfmperf_test.c @@ -35,9 +35,9 @@ static int open_dev_msr(int cpu) return open_path_or_exit(path, O_RDONLY); } -static uint64_t read_dev_msr(int msr_fd, uint32_t msr) +static u64 read_dev_msr(int msr_fd, u32 msr) { - uint64_t data; + u64 data; ssize_t rc; rc = pread(msr_fd, &data, sizeof(data), msr); @@ -107,8 +107,8 @@ static void guest_code(void *nested_test_data) static void guest_no_aperfmperf(void) { - uint64_t msr_val; - uint8_t vector; + u64 msr_val; + u8 vector; vector = rdmsr_safe(MSR_IA32_APERF, &msr_val); GUEST_ASSERT(vector == GP_VECTOR); @@ -122,8 +122,8 @@ static void guest_no_aperfmperf(void) int main(int argc, char *argv[]) { const bool has_nested = kvm_cpu_has(X86_FEATURE_SVM) || kvm_cpu_has(X86_FEATURE_VMX); - uint64_t host_aperf_before, host_mperf_before; - vm_vaddr_t nested_test_data_gva; + u64 host_aperf_before, host_mperf_before; + gva_t nested_test_data_gva; struct kvm_vcpu *vcpu; struct kvm_vm *vm; int msr_fd, cpu, i; @@ -166,8 +166,8 @@ int main(int argc, char *argv[]) host_mperf_before = read_dev_msr(msr_fd, MSR_IA32_MPERF); for (i = 0; i <= NUM_ITERATIONS * (1 + has_nested); i++) { - uint64_t host_aperf_after, host_mperf_after; - uint64_t guest_aperf, guest_mperf; + u64 host_aperf_after, host_mperf_after; + u64 guest_aperf, guest_mperf; struct ucall uc; vcpu_run(vcpu); diff --git a/tools/testing/selftests/kvm/x86/apic_bus_clock_test.c b/tools/testing/selftests/kvm/x86/apic_bus_clock_test.c index f8916bb34405..404f0028e110 100644 --- a/tools/testing/selftests/kvm/x86/apic_bus_clock_test.c +++ b/tools/testing/selftests/kvm/x86/apic_bus_clock_test.c @@ -19,8 +19,8 @@ * timer frequency. */ static const struct { - const uint32_t tdcr; - const uint32_t divide_count; + const u32 tdcr; + const u32 divide_count; } tdcrs[] = { {0x0, 2}, {0x1, 4}, @@ -42,12 +42,12 @@ static void apic_enable(void) xapic_enable(); } -static uint32_t apic_read_reg(unsigned int reg) +static u32 apic_read_reg(unsigned int reg) { return is_x2apic ? x2apic_read_reg(reg) : xapic_read_reg(reg); } -static void apic_write_reg(unsigned int reg, uint32_t val) +static void apic_write_reg(unsigned int reg, u32 val) { if (is_x2apic) x2apic_write_reg(reg, val); @@ -55,12 +55,12 @@ static void apic_write_reg(unsigned int reg, uint32_t val) xapic_write_reg(reg, val); } -static void apic_guest_code(uint64_t apic_hz, uint64_t delay_ms) +static void apic_guest_code(u64 apic_hz, u64 delay_ms) { - uint64_t tsc_hz = guest_tsc_khz * 1000; - const uint32_t tmict = ~0u; - uint64_t tsc0, tsc1, freq; - uint32_t tmcct; + u64 tsc_hz = guest_tsc_khz * 1000; + const u32 tmict = ~0u; + u64 tsc0, tsc1, freq; + u32 tmcct; int i; apic_enable(); @@ -121,7 +121,7 @@ static void test_apic_bus_clock(struct kvm_vcpu *vcpu) } } -static void run_apic_bus_clock_test(uint64_t apic_hz, uint64_t delay_ms, +static void run_apic_bus_clock_test(u64 apic_hz, u64 delay_ms, bool x2apic) { struct kvm_vcpu *vcpu; @@ -168,8 +168,8 @@ int main(int argc, char *argv[]) * Arbitrarilty default to 25MHz for the APIC bus frequency, which is * different enough from the default 1GHz to be interesting. */ - uint64_t apic_hz = 25 * 1000 * 1000; - uint64_t delay_ms = 100; + u64 apic_hz = 25 * 1000 * 1000; + u64 delay_ms = 100; int opt; TEST_REQUIRE(kvm_has_cap(KVM_CAP_X86_APIC_BUS_CYCLES_NS)); diff --git a/tools/testing/selftests/kvm/x86/cpuid_test.c b/tools/testing/selftests/kvm/x86/cpuid_test.c index f9ed14996977..ef0ddd240887 100644 --- a/tools/testing/selftests/kvm/x86/cpuid_test.c +++ b/tools/testing/selftests/kvm/x86/cpuid_test.c @@ -140,10 +140,10 @@ static void run_vcpu(struct kvm_vcpu *vcpu, int stage) } } -struct kvm_cpuid2 *vcpu_alloc_cpuid(struct kvm_vm *vm, vm_vaddr_t *p_gva, struct kvm_cpuid2 *cpuid) +struct kvm_cpuid2 *vcpu_alloc_cpuid(struct kvm_vm *vm, gva_t *p_gva, struct kvm_cpuid2 *cpuid) { int size = sizeof(*cpuid) + cpuid->nent * sizeof(cpuid->entries[0]); - vm_vaddr_t gva = vm_vaddr_alloc(vm, size, KVM_UTIL_MIN_VADDR); + gva_t gva = vm_alloc(vm, size, KVM_UTIL_MIN_VADDR); struct kvm_cpuid2 *guest_cpuids = addr_gva2hva(vm, gva); memcpy(guest_cpuids, cpuid, size); @@ -217,7 +217,7 @@ static void test_get_cpuid2(struct kvm_vcpu *vcpu) int main(void) { struct kvm_vcpu *vcpu; - vm_vaddr_t cpuid_gva; + gva_t cpuid_gva; struct kvm_vm *vm; int stage; diff --git a/tools/testing/selftests/kvm/x86/debug_regs.c b/tools/testing/selftests/kvm/x86/debug_regs.c index 2d814c1d1dc4..0dfaf03cd0a0 100644 --- a/tools/testing/selftests/kvm/x86/debug_regs.c +++ b/tools/testing/selftests/kvm/x86/debug_regs.c @@ -16,7 +16,7 @@ #define IRQ_VECTOR 0xAA /* For testing data access debug BP */ -uint32_t guest_value; +u32 guest_value; extern unsigned char sw_bp, hw_bp, write_data, ss_start, bd_start; @@ -86,7 +86,7 @@ int main(void) struct kvm_run *run; struct kvm_vm *vm; struct ucall uc; - uint64_t cmd; + u64 cmd; int i; /* Instruction lengths starting at ss_start */ int ss_size[6] = { diff --git a/tools/testing/selftests/kvm/x86/dirty_log_page_splitting_test.c b/tools/testing/selftests/kvm/x86/dirty_log_page_splitting_test.c index b0d2b04a7ff2..388ba4101f97 100644 --- a/tools/testing/selftests/kvm/x86/dirty_log_page_splitting_test.c +++ b/tools/testing/selftests/kvm/x86/dirty_log_page_splitting_test.c @@ -23,7 +23,7 @@ #define SLOTS 2 #define ITERATIONS 2 -static uint64_t guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE; +static u64 guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE; static enum vm_mem_backing_src_type backing_src = VM_MEM_SRC_ANONYMOUS_HUGETLB; @@ -33,10 +33,10 @@ static int iteration; static int vcpu_last_completed_iteration[KVM_MAX_VCPUS]; struct kvm_page_stats { - uint64_t pages_4k; - uint64_t pages_2m; - uint64_t pages_1g; - uint64_t hugepages; + u64 pages_4k; + u64 pages_2m; + u64 pages_1g; + u64 hugepages; }; static void get_page_stats(struct kvm_vm *vm, struct kvm_page_stats *stats, const char *stage) @@ -89,9 +89,9 @@ static void run_test(enum vm_guest_mode mode, void *unused) { struct kvm_vm *vm; unsigned long **bitmaps; - uint64_t guest_num_pages; - uint64_t host_num_pages; - uint64_t pages_per_slot; + u64 guest_num_pages; + u64 host_num_pages; + u64 pages_per_slot; int i; struct kvm_page_stats stats_populated; struct kvm_page_stats stats_dirty_logging_enabled; diff --git a/tools/testing/selftests/kvm/x86/evmcs_smm_controls_test.c b/tools/testing/selftests/kvm/x86/evmcs_smm_controls_test.c index af7c90103396..5b3aef109cfc 100644 --- a/tools/testing/selftests/kvm/x86/evmcs_smm_controls_test.c +++ b/tools/testing/selftests/kvm/x86/evmcs_smm_controls_test.c @@ -29,13 +29,13 @@ * SMI handler: runs in real-address mode. * Reports SMRAM_STAGE via port IO, then does RSM. */ -static uint8_t smi_handler[] = { +static u8 smi_handler[] = { 0xb0, SMRAM_STAGE, /* mov $SMRAM_STAGE, %al */ 0xe4, SYNC_PORT, /* in $SYNC_PORT, %al */ 0x0f, 0xaa, /* rsm */ }; -static inline void sync_with_host(uint64_t phase) +static inline void sync_with_host(u64 phase) { asm volatile("in $" XSTR(SYNC_PORT) ", %%al \n" : "+a" (phase)); @@ -73,7 +73,7 @@ static void guest_code(struct vmx_pages *vmx_pages, int main(int argc, char *argv[]) { - vm_vaddr_t vmx_pages_gva = 0, hv_pages_gva = 0; + gva_t vmx_pages_gva = 0, hv_pages_gva = 0; struct hyperv_test_pages *hv; struct hv_enlightened_vmcs *evmcs; struct kvm_vcpu *vcpu; diff --git a/tools/testing/selftests/kvm/x86/fastops_test.c b/tools/testing/selftests/kvm/x86/fastops_test.c index 8926cfe0e209..c0d30ccd8767 100644 --- a/tools/testing/selftests/kvm/x86/fastops_test.c +++ b/tools/testing/selftests/kvm/x86/fastops_test.c @@ -15,7 +15,7 @@ "pop %[flags]\n\t" #define flags_constraint(flags_val) [flags]"=r"(flags_val) -#define bt_constraint(__bt_val) [bt_val]"rm"((uint32_t)__bt_val) +#define bt_constraint(__bt_val) [bt_val]"rm"((u32)__bt_val) #define guest_execute_fastop_1(FEP, insn, __val, __flags) \ ({ \ @@ -28,17 +28,17 @@ #define guest_test_fastop_1(insn, type_t, __val) \ ({ \ type_t val = __val, ex_val = __val, input = __val; \ - uint64_t flags, ex_flags; \ + u64 flags, ex_flags; \ \ guest_execute_fastop_1("", insn, ex_val, ex_flags); \ guest_execute_fastop_1(KVM_FEP, insn, val, flags); \ \ __GUEST_ASSERT(val == ex_val, \ "Wanted 0x%lx for '%s 0x%lx', got 0x%lx", \ - (uint64_t)ex_val, insn, (uint64_t)input, (uint64_t)val); \ + (u64)ex_val, insn, (u64)input, (u64)val); \ __GUEST_ASSERT(flags == ex_flags, \ "Wanted flags 0x%lx for '%s 0x%lx', got 0x%lx", \ - ex_flags, insn, (uint64_t)input, flags); \ + ex_flags, insn, (u64)input, flags); \ }) #define guest_execute_fastop_2(FEP, insn, __input, __output, __flags) \ @@ -52,18 +52,18 @@ #define guest_test_fastop_2(insn, type_t, __val1, __val2) \ ({ \ type_t input = __val1, input2 = __val2, output = __val2, ex_output = __val2; \ - uint64_t flags, ex_flags; \ + u64 flags, ex_flags; \ \ guest_execute_fastop_2("", insn, input, ex_output, ex_flags); \ guest_execute_fastop_2(KVM_FEP, insn, input, output, flags); \ \ __GUEST_ASSERT(output == ex_output, \ "Wanted 0x%lx for '%s 0x%lx 0x%lx', got 0x%lx", \ - (uint64_t)ex_output, insn, (uint64_t)input, \ - (uint64_t)input2, (uint64_t)output); \ + (u64)ex_output, insn, (u64)input, \ + (u64)input2, (u64)output); \ __GUEST_ASSERT(flags == ex_flags, \ "Wanted flags 0x%lx for '%s 0x%lx, 0x%lx', got 0x%lx", \ - ex_flags, insn, (uint64_t)input, (uint64_t)input2, flags); \ + ex_flags, insn, (u64)input, (u64)input2, flags); \ }) #define guest_execute_fastop_cl(FEP, insn, __shift, __output, __flags) \ @@ -77,25 +77,25 @@ #define guest_test_fastop_cl(insn, type_t, __val1, __val2) \ ({ \ type_t output = __val2, ex_output = __val2, input = __val2; \ - uint8_t shift = __val1; \ - uint64_t flags, ex_flags; \ + u8 shift = __val1; \ + u64 flags, ex_flags; \ \ guest_execute_fastop_cl("", insn, shift, ex_output, ex_flags); \ guest_execute_fastop_cl(KVM_FEP, insn, shift, output, flags); \ \ __GUEST_ASSERT(output == ex_output, \ "Wanted 0x%lx for '%s 0x%x, 0x%lx', got 0x%lx", \ - (uint64_t)ex_output, insn, shift, (uint64_t)input, \ - (uint64_t)output); \ + (u64)ex_output, insn, shift, (u64)input, \ + (u64)output); \ __GUEST_ASSERT(flags == ex_flags, \ "Wanted flags 0x%lx for '%s 0x%x, 0x%lx', got 0x%lx", \ - ex_flags, insn, shift, (uint64_t)input, flags); \ + ex_flags, insn, shift, (u64)input, flags); \ }) #define guest_execute_fastop_div(__KVM_ASM_SAFE, insn, __a, __d, __rm, __flags) \ ({ \ - uint64_t ign_error_code; \ - uint8_t vector; \ + u64 ign_error_code; \ + u8 vector; \ \ __asm__ __volatile__(fastop(__KVM_ASM_SAFE(insn " %[denom]")) \ : "+a"(__a), "+d"(__d), flags_constraint(__flags), \ @@ -109,8 +109,8 @@ ({ \ type_t _a = __val1, _d = __val1, rm = __val2; \ type_t a = _a, d = _d, ex_a = _a, ex_d = _d; \ - uint64_t flags, ex_flags; \ - uint8_t v, ex_v; \ + u64 flags, ex_flags; \ + u8 v, ex_v; \ \ ex_v = guest_execute_fastop_div(KVM_ASM_SAFE, insn, ex_a, ex_d, rm, ex_flags); \ v = guest_execute_fastop_div(KVM_ASM_SAFE_FEP, insn, a, d, rm, flags); \ @@ -118,17 +118,17 @@ GUEST_ASSERT_EQ(v, ex_v); \ __GUEST_ASSERT(v == ex_v, \ "Wanted vector 0x%x for '%s 0x%lx:0x%lx/0x%lx', got 0x%x", \ - ex_v, insn, (uint64_t)_a, (uint64_t)_d, (uint64_t)rm, v); \ + ex_v, insn, (u64)_a, (u64)_d, (u64)rm, v); \ __GUEST_ASSERT(a == ex_a && d == ex_d, \ "Wanted 0x%lx:0x%lx for '%s 0x%lx:0x%lx/0x%lx', got 0x%lx:0x%lx",\ - (uint64_t)ex_a, (uint64_t)ex_d, insn, (uint64_t)_a, \ - (uint64_t)_d, (uint64_t)rm, (uint64_t)a, (uint64_t)d); \ + (u64)ex_a, (u64)ex_d, insn, (u64)_a, \ + (u64)_d, (u64)rm, (u64)a, (u64)d); \ __GUEST_ASSERT(v || ex_v || (flags == ex_flags), \ "Wanted flags 0x%lx for '%s 0x%lx:0x%lx/0x%lx', got 0x%lx", \ - ex_flags, insn, (uint64_t)_a, (uint64_t)_d, (uint64_t)rm, flags);\ + ex_flags, insn, (u64)_a, (u64)_d, (u64)rm, flags);\ }) -static const uint64_t vals[] = { +static const u64 vals[] = { 0, 1, 2, @@ -185,10 +185,10 @@ if (sizeof(type_t) != 1) { \ static void guest_code(void) { - guest_test_fastops(uint8_t, "b"); - guest_test_fastops(uint16_t, "w"); - guest_test_fastops(uint32_t, "l"); - guest_test_fastops(uint64_t, "q"); + guest_test_fastops(u8, "b"); + guest_test_fastops(u16, "w"); + guest_test_fastops(u32, "l"); + guest_test_fastops(u64, "q"); GUEST_DONE(); } diff --git a/tools/testing/selftests/kvm/x86/feature_msrs_test.c b/tools/testing/selftests/kvm/x86/feature_msrs_test.c index a72f13ae2edb..158550701771 100644 --- a/tools/testing/selftests/kvm/x86/feature_msrs_test.c +++ b/tools/testing/selftests/kvm/x86/feature_msrs_test.c @@ -12,7 +12,7 @@ #include "kvm_util.h" #include "processor.h" -static bool is_kvm_controlled_msr(uint32_t msr) +static bool is_kvm_controlled_msr(u32 msr) { return msr == MSR_IA32_VMX_CR0_FIXED1 || msr == MSR_IA32_VMX_CR4_FIXED1; } @@ -21,7 +21,7 @@ static bool is_kvm_controlled_msr(uint32_t msr) * For VMX MSRs with a "true" variant, KVM requires userspace to set the "true" * MSR, and doesn't allow setting the hidden version. */ -static bool is_hidden_vmx_msr(uint32_t msr) +static bool is_hidden_vmx_msr(u32 msr) { switch (msr) { case MSR_IA32_VMX_PINBASED_CTLS: @@ -34,15 +34,15 @@ static bool is_hidden_vmx_msr(uint32_t msr) } } -static bool is_quirked_msr(uint32_t msr) +static bool is_quirked_msr(u32 msr) { return msr != MSR_AMD64_DE_CFG; } -static void test_feature_msr(uint32_t msr) +static void test_feature_msr(u32 msr) { - const uint64_t supported_mask = kvm_get_feature_msr(msr); - uint64_t reset_value = is_quirked_msr(msr) ? supported_mask : 0; + const u64 supported_mask = kvm_get_feature_msr(msr); + u64 reset_value = is_quirked_msr(msr) ? supported_mask : 0; struct kvm_vcpu *vcpu; struct kvm_vm *vm; diff --git a/tools/testing/selftests/kvm/x86/fix_hypercall_test.c b/tools/testing/selftests/kvm/x86/fix_hypercall_test.c index 00b6e85735dd..753a0e730ea8 100644 --- a/tools/testing/selftests/kvm/x86/fix_hypercall_test.c +++ b/tools/testing/selftests/kvm/x86/fix_hypercall_test.c @@ -26,18 +26,18 @@ static void guest_ud_handler(struct ex_regs *regs) regs->rip += HYPERCALL_INSN_SIZE; } -static const uint8_t vmx_vmcall[HYPERCALL_INSN_SIZE] = { 0x0f, 0x01, 0xc1 }; -static const uint8_t svm_vmmcall[HYPERCALL_INSN_SIZE] = { 0x0f, 0x01, 0xd9 }; +static const u8 vmx_vmcall[HYPERCALL_INSN_SIZE] = { 0x0f, 0x01, 0xc1 }; +static const u8 svm_vmmcall[HYPERCALL_INSN_SIZE] = { 0x0f, 0x01, 0xd9 }; -extern uint8_t hypercall_insn[HYPERCALL_INSN_SIZE]; -static uint64_t do_sched_yield(uint8_t apic_id) +extern u8 hypercall_insn[HYPERCALL_INSN_SIZE]; +static u64 do_sched_yield(u8 apic_id) { - uint64_t ret; + u64 ret; asm volatile("hypercall_insn:\n\t" ".byte 0xcc,0xcc,0xcc\n\t" : "=a"(ret) - : "a"((uint64_t)KVM_HC_SCHED_YIELD), "b"((uint64_t)apic_id) + : "a"((u64)KVM_HC_SCHED_YIELD), "b"((u64)apic_id) : "memory"); return ret; @@ -45,9 +45,9 @@ static uint64_t do_sched_yield(uint8_t apic_id) static void guest_main(void) { - const uint8_t *native_hypercall_insn; - const uint8_t *other_hypercall_insn; - uint64_t ret; + const u8 *native_hypercall_insn; + const u8 *other_hypercall_insn; + u64 ret; if (host_cpu_is_intel) { native_hypercall_insn = vmx_vmcall; @@ -72,7 +72,7 @@ static void guest_main(void) * the "right" hypercall. */ if (quirk_disabled) { - GUEST_ASSERT(ret == (uint64_t)-EFAULT); + GUEST_ASSERT(ret == (u64)-EFAULT); GUEST_ASSERT(!memcmp(other_hypercall_insn, hypercall_insn, HYPERCALL_INSN_SIZE)); } else { diff --git a/tools/testing/selftests/kvm/x86/flds_emulation.h b/tools/testing/selftests/kvm/x86/flds_emulation.h index 37b1a9f52864..fd6b6c67199a 100644 --- a/tools/testing/selftests/kvm/x86/flds_emulation.h +++ b/tools/testing/selftests/kvm/x86/flds_emulation.h @@ -12,7 +12,7 @@ * KVM to emulate the instruction (e.g. by providing an MMIO address) to * exercise emulation failures. */ -static inline void flds(uint64_t address) +static inline void flds(u64 address) { __asm__ __volatile__(FLDS_MEM_EAX :: "a"(address)); } @@ -21,8 +21,8 @@ static inline void handle_flds_emulation_failure_exit(struct kvm_vcpu *vcpu) { struct kvm_run *run = vcpu->run; struct kvm_regs regs; - uint8_t *insn_bytes; - uint64_t flags; + u8 *insn_bytes; + u64 flags; TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_INTERNAL_ERROR); diff --git a/tools/testing/selftests/kvm/x86/hwcr_msr_test.c b/tools/testing/selftests/kvm/x86/hwcr_msr_test.c index 10b1b0ba374e..8e20a03b3329 100644 --- a/tools/testing/selftests/kvm/x86/hwcr_msr_test.c +++ b/tools/testing/selftests/kvm/x86/hwcr_msr_test.c @@ -10,11 +10,11 @@ void test_hwcr_bit(struct kvm_vcpu *vcpu, unsigned int bit) { - const uint64_t ignored = BIT_ULL(3) | BIT_ULL(6) | BIT_ULL(8); - const uint64_t valid = BIT_ULL(18) | BIT_ULL(24); - const uint64_t legal = ignored | valid; - uint64_t val = BIT_ULL(bit); - uint64_t actual; + const u64 ignored = BIT_ULL(3) | BIT_ULL(6) | BIT_ULL(8); + const u64 valid = BIT_ULL(18) | BIT_ULL(24); + const u64 legal = ignored | valid; + u64 val = BIT_ULL(bit); + u64 actual; int r; r = _vcpu_set_msr(vcpu, MSR_K7_HWCR, val); diff --git a/tools/testing/selftests/kvm/x86/hyperv_clock.c b/tools/testing/selftests/kvm/x86/hyperv_clock.c index e058bc676cd6..c083cea546dc 100644 --- a/tools/testing/selftests/kvm/x86/hyperv_clock.c +++ b/tools/testing/selftests/kvm/x86/hyperv_clock.c @@ -98,7 +98,7 @@ static inline void check_tsc_msr_tsc_page(struct ms_hyperv_tsc_page *tsc_page) GUEST_ASSERT(r2 >= t1 && r2 - t2 < 100000); } -static void guest_main(struct ms_hyperv_tsc_page *tsc_page, vm_paddr_t tsc_page_gpa) +static void guest_main(struct ms_hyperv_tsc_page *tsc_page, gpa_t tsc_page_gpa) { u64 tsc_scale, tsc_offset; @@ -208,7 +208,7 @@ int main(void) struct kvm_vcpu *vcpu; struct kvm_vm *vm; struct ucall uc; - vm_vaddr_t tsc_page_gva; + gva_t tsc_page_gva; int stage; TEST_REQUIRE(kvm_has_cap(KVM_CAP_HYPERV_TIME)); @@ -218,7 +218,7 @@ int main(void) vcpu_set_hv_cpuid(vcpu); - tsc_page_gva = vm_vaddr_alloc_page(vm); + tsc_page_gva = vm_alloc_page(vm); memset(addr_gva2hva(vm, tsc_page_gva), 0x0, getpagesize()); TEST_ASSERT((addr_gva2gpa(vm, tsc_page_gva) & (getpagesize() - 1)) == 0, "TSC page has to be page aligned"); diff --git a/tools/testing/selftests/kvm/x86/hyperv_evmcs.c b/tools/testing/selftests/kvm/x86/hyperv_evmcs.c index 74cf19661309..c7fa114aee20 100644 --- a/tools/testing/selftests/kvm/x86/hyperv_evmcs.c +++ b/tools/testing/selftests/kvm/x86/hyperv_evmcs.c @@ -30,7 +30,7 @@ static void guest_nmi_handler(struct ex_regs *regs) { } -static inline void rdmsr_from_l2(uint32_t msr) +static inline void rdmsr_from_l2(u32 msr) { /* Currently, L1 doesn't preserve GPRs during vmexits. */ __asm__ __volatile__ ("rdmsr" : : "c"(msr) : @@ -76,7 +76,7 @@ void l2_guest_code(void) } void guest_code(struct vmx_pages *vmx_pages, struct hyperv_test_pages *hv_pages, - vm_vaddr_t hv_hcall_page_gpa) + gpa_t hv_hcall_page_gpa) { #define L2_GUEST_STACK_SIZE 64 unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE]; @@ -231,8 +231,8 @@ static struct kvm_vcpu *save_restore_vm(struct kvm_vm *vm, int main(int argc, char *argv[]) { - vm_vaddr_t vmx_pages_gva = 0, hv_pages_gva = 0; - vm_vaddr_t hcall_page; + gva_t vmx_pages_gva = 0, hv_pages_gva = 0; + gva_t hcall_page; struct kvm_vcpu *vcpu; struct kvm_vm *vm; @@ -246,7 +246,7 @@ int main(int argc, char *argv[]) vm = vm_create_with_one_vcpu(&vcpu, guest_code); - hcall_page = vm_vaddr_alloc_pages(vm, 1); + hcall_page = vm_alloc_pages(vm, 1); memset(addr_gva2hva(vm, hcall_page), 0x0, getpagesize()); vcpu_set_hv_cpuid(vcpu); diff --git a/tools/testing/selftests/kvm/x86/hyperv_extended_hypercalls.c b/tools/testing/selftests/kvm/x86/hyperv_extended_hypercalls.c index 949e08e98f31..ae047db7b1be 100644 --- a/tools/testing/selftests/kvm/x86/hyperv_extended_hypercalls.c +++ b/tools/testing/selftests/kvm/x86/hyperv_extended_hypercalls.c @@ -15,19 +15,19 @@ /* Any value is fine */ #define EXT_CAPABILITIES 0xbull -static void guest_code(vm_paddr_t in_pg_gpa, vm_paddr_t out_pg_gpa, - vm_vaddr_t out_pg_gva) +static void guest_code(gpa_t in_pg_gpa, gpa_t out_pg_gpa, + gva_t out_pg_gva) { - uint64_t *output_gva; + u64 *output_gva; wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID); wrmsr(HV_X64_MSR_HYPERCALL, in_pg_gpa); - output_gva = (uint64_t *)out_pg_gva; + output_gva = (u64 *)out_pg_gva; hyperv_hypercall(HV_EXT_CALL_QUERY_CAPABILITIES, in_pg_gpa, out_pg_gpa); - /* TLFS states output will be a uint64_t value */ + /* TLFS states output will be a u64 value */ GUEST_ASSERT_EQ(*output_gva, EXT_CAPABILITIES); GUEST_DONE(); @@ -35,12 +35,12 @@ static void guest_code(vm_paddr_t in_pg_gpa, vm_paddr_t out_pg_gpa, int main(void) { - vm_vaddr_t hcall_out_page; - vm_vaddr_t hcall_in_page; + gva_t hcall_out_page; + gva_t hcall_in_page; struct kvm_vcpu *vcpu; struct kvm_run *run; struct kvm_vm *vm; - uint64_t *outval; + u64 *outval; struct ucall uc; TEST_REQUIRE(kvm_has_cap(KVM_CAP_HYPERV_CPUID)); @@ -57,11 +57,11 @@ int main(void) vcpu_set_hv_cpuid(vcpu); /* Hypercall input */ - hcall_in_page = vm_vaddr_alloc_pages(vm, 1); + hcall_in_page = vm_alloc_pages(vm, 1); memset(addr_gva2hva(vm, hcall_in_page), 0x0, vm->page_size); /* Hypercall output */ - hcall_out_page = vm_vaddr_alloc_pages(vm, 1); + hcall_out_page = vm_alloc_pages(vm, 1); memset(addr_gva2hva(vm, hcall_out_page), 0x0, vm->page_size); vcpu_args_set(vcpu, 3, addr_gva2gpa(vm, hcall_in_page), diff --git a/tools/testing/selftests/kvm/x86/hyperv_features.c b/tools/testing/selftests/kvm/x86/hyperv_features.c index 130b9ce7e5dd..7347f1fe5157 100644 --- a/tools/testing/selftests/kvm/x86/hyperv_features.c +++ b/tools/testing/selftests/kvm/x86/hyperv_features.c @@ -22,27 +22,27 @@ KVM_X86_CPU_FEATURE(HYPERV_CPUID_ENLIGHTMENT_INFO, 0, EBX, 0) struct msr_data { - uint32_t idx; + u32 idx; bool fault_expected; bool write; u64 write_val; }; struct hcall_data { - uint64_t control; - uint64_t expect; + u64 control; + u64 expect; bool ud_expected; }; -static bool is_write_only_msr(uint32_t msr) +static bool is_write_only_msr(u32 msr) { return msr == HV_X64_MSR_EOI; } static void guest_msr(struct msr_data *msr) { - uint8_t vector = 0; - uint64_t msr_val = 0; + u8 vector = 0; + u64 msr_val = 0; GUEST_ASSERT(msr->idx); @@ -82,10 +82,10 @@ static void guest_msr(struct msr_data *msr) GUEST_DONE(); } -static void guest_hcall(vm_vaddr_t pgs_gpa, struct hcall_data *hcall) +static void guest_hcall(gpa_t pgs_gpa, struct hcall_data *hcall) { u64 res, input, output; - uint8_t vector; + u8 vector; GUEST_ASSERT_NE(hcall->control, 0); @@ -134,14 +134,14 @@ static void guest_test_msrs_access(void) struct kvm_vm *vm; struct ucall uc; int stage = 0; - vm_vaddr_t msr_gva; + gva_t msr_gva; struct msr_data *msr; bool has_invtsc = kvm_cpu_has(X86_FEATURE_INVTSC); while (true) { vm = vm_create_with_one_vcpu(&vcpu, guest_msr); - msr_gva = vm_vaddr_alloc_page(vm); + msr_gva = vm_alloc_page(vm); memset(addr_gva2hva(vm, msr_gva), 0x0, getpagesize()); msr = addr_gva2hva(vm, msr_gva); @@ -523,17 +523,17 @@ static void guest_test_hcalls_access(void) struct kvm_vm *vm; struct ucall uc; int stage = 0; - vm_vaddr_t hcall_page, hcall_params; + gva_t hcall_page, hcall_params; struct hcall_data *hcall; while (true) { vm = vm_create_with_one_vcpu(&vcpu, guest_hcall); /* Hypercall input/output */ - hcall_page = vm_vaddr_alloc_pages(vm, 2); + hcall_page = vm_alloc_pages(vm, 2); memset(addr_gva2hva(vm, hcall_page), 0x0, 2 * getpagesize()); - hcall_params = vm_vaddr_alloc_page(vm); + hcall_params = vm_alloc_page(vm); memset(addr_gva2hva(vm, hcall_params), 0x0, getpagesize()); hcall = addr_gva2hva(vm, hcall_params); diff --git a/tools/testing/selftests/kvm/x86/hyperv_ipi.c b/tools/testing/selftests/kvm/x86/hyperv_ipi.c index ca61836c4e32..771535f9aad3 100644 --- a/tools/testing/selftests/kvm/x86/hyperv_ipi.c +++ b/tools/testing/selftests/kvm/x86/hyperv_ipi.c @@ -18,7 +18,7 @@ #define IPI_VECTOR 0xfe -static volatile uint64_t ipis_rcvd[RECEIVER_VCPU_ID_2 + 1]; +static volatile u64 ipis_rcvd[RECEIVER_VCPU_ID_2 + 1]; struct hv_vpset { u64 format; @@ -45,13 +45,13 @@ struct hv_send_ipi_ex { struct hv_vpset vp_set; }; -static inline void hv_init(vm_vaddr_t pgs_gpa) +static inline void hv_init(gpa_t pgs_gpa) { wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID); wrmsr(HV_X64_MSR_HYPERCALL, pgs_gpa); } -static void receiver_code(void *hcall_page, vm_vaddr_t pgs_gpa) +static void receiver_code(void *hcall_page, gpa_t pgs_gpa) { u32 vcpu_id; @@ -85,7 +85,7 @@ static inline void nop_loop(void) asm volatile("nop"); } -static void sender_guest_code(void *hcall_page, vm_vaddr_t pgs_gpa) +static void sender_guest_code(void *hcall_page, gpa_t pgs_gpa) { struct hv_send_ipi *ipi = (struct hv_send_ipi *)hcall_page; struct hv_send_ipi_ex *ipi_ex = (struct hv_send_ipi_ex *)hcall_page; @@ -243,7 +243,7 @@ int main(int argc, char *argv[]) { struct kvm_vm *vm; struct kvm_vcpu *vcpu[3]; - vm_vaddr_t hcall_page; + gva_t hcall_page; pthread_t threads[2]; int stage = 1, r; struct ucall uc; @@ -253,7 +253,7 @@ int main(int argc, char *argv[]) vm = vm_create_with_one_vcpu(&vcpu[0], sender_guest_code); /* Hypercall input/output */ - hcall_page = vm_vaddr_alloc_pages(vm, 2); + hcall_page = vm_alloc_pages(vm, 2); memset(addr_gva2hva(vm, hcall_page), 0x0, 2 * getpagesize()); diff --git a/tools/testing/selftests/kvm/x86/hyperv_svm_test.c b/tools/testing/selftests/kvm/x86/hyperv_svm_test.c index 0ddb63229bcb..7a62f6a9d606 100644 --- a/tools/testing/selftests/kvm/x86/hyperv_svm_test.c +++ b/tools/testing/selftests/kvm/x86/hyperv_svm_test.c @@ -21,7 +21,7 @@ #define L2_GUEST_STACK_SIZE 256 /* Exit to L1 from L2 with RDMSR instruction */ -static inline void rdmsr_from_l2(uint32_t msr) +static inline void rdmsr_from_l2(u32 msr) { /* Currently, L1 doesn't preserve GPRs during vmexits. */ __asm__ __volatile__ ("rdmsr" : : "c"(msr) : @@ -67,7 +67,7 @@ void l2_guest_code(void) static void __attribute__((__flatten__)) guest_code(struct svm_test_data *svm, struct hyperv_test_pages *hv_pages, - vm_vaddr_t pgs_gpa) + gpa_t pgs_gpa) { unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE]; struct vmcb *vmcb = svm->vmcb; @@ -149,8 +149,8 @@ static void __attribute__((__flatten__)) guest_code(struct svm_test_data *svm, int main(int argc, char *argv[]) { - vm_vaddr_t nested_gva = 0, hv_pages_gva = 0; - vm_vaddr_t hcall_page; + gva_t nested_gva = 0, hv_pages_gva = 0; + gva_t hcall_page; struct kvm_vcpu *vcpu; struct kvm_vm *vm; struct ucall uc; @@ -165,7 +165,7 @@ int main(int argc, char *argv[]) vcpu_alloc_svm(vm, &nested_gva); vcpu_alloc_hyperv_test_pages(vm, &hv_pages_gva); - hcall_page = vm_vaddr_alloc_pages(vm, 1); + hcall_page = vm_alloc_pages(vm, 1); memset(addr_gva2hva(vm, hcall_page), 0x0, getpagesize()); vcpu_args_set(vcpu, 3, nested_gva, hv_pages_gva, addr_gva2gpa(vm, hcall_page)); diff --git a/tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c b/tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c index c542cc4762b1..15ee8b7bfc11 100644 --- a/tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c +++ b/tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c @@ -61,14 +61,14 @@ struct hv_tlb_flush_ex { * - GVAs of the test pages' PTEs */ struct test_data { - vm_vaddr_t hcall_gva; - vm_paddr_t hcall_gpa; - vm_vaddr_t test_pages; - vm_vaddr_t test_pages_pte[NTEST_PAGES]; + gva_t hcall_gva; + gpa_t hcall_gpa; + gva_t test_pages; + gva_t test_pages_pte[NTEST_PAGES]; }; /* 'Worker' vCPU code checking the contents of the test page */ -static void worker_guest_code(vm_vaddr_t test_data) +static void worker_guest_code(gva_t test_data) { struct test_data *data = (struct test_data *)test_data; u32 vcpu_id = rdmsr(HV_X64_MSR_VP_INDEX); @@ -133,12 +133,12 @@ static void set_expected_val(void *addr, u64 val, int vcpu_id) * Update PTEs swapping two test pages. * TODO: use swap()/xchg() when these are provided. */ -static void swap_two_test_pages(vm_paddr_t pte_gva1, vm_paddr_t pte_gva2) +static void swap_two_test_pages(gpa_t pte_gva1, gpa_t pte_gva2) { - uint64_t tmp = *(uint64_t *)pte_gva1; + u64 tmp = *(u64 *)pte_gva1; - *(uint64_t *)pte_gva1 = *(uint64_t *)pte_gva2; - *(uint64_t *)pte_gva2 = tmp; + *(u64 *)pte_gva1 = *(u64 *)pte_gva2; + *(u64 *)pte_gva2 = tmp; } /* @@ -196,12 +196,12 @@ static inline void post_test(struct test_data *data, u64 exp1, u64 exp2) #define TESTVAL2 0x0202020202020202 /* Main vCPU doing the test */ -static void sender_guest_code(vm_vaddr_t test_data) +static void sender_guest_code(gva_t test_data) { struct test_data *data = (struct test_data *)test_data; struct hv_tlb_flush *flush = (struct hv_tlb_flush *)data->hcall_gva; struct hv_tlb_flush_ex *flush_ex = (struct hv_tlb_flush_ex *)data->hcall_gva; - vm_paddr_t hcall_gpa = data->hcall_gpa; + gpa_t hcall_gpa = data->hcall_gpa; int i, stage = 1; wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID); @@ -581,9 +581,9 @@ int main(int argc, char *argv[]) struct kvm_vm *vm; struct kvm_vcpu *vcpu[3]; pthread_t threads[2]; - vm_vaddr_t test_data_page, gva; - vm_paddr_t gpa; - uint64_t *pte; + gva_t test_data_page, gva; + gpa_t gpa; + u64 *pte; struct test_data *data; struct ucall uc; int stage = 1, r, i; @@ -593,11 +593,11 @@ int main(int argc, char *argv[]) vm = vm_create_with_one_vcpu(&vcpu[0], sender_guest_code); /* Test data page */ - test_data_page = vm_vaddr_alloc_page(vm); + test_data_page = vm_alloc_page(vm); data = (struct test_data *)addr_gva2hva(vm, test_data_page); /* Hypercall input/output */ - data->hcall_gva = vm_vaddr_alloc_pages(vm, 2); + data->hcall_gva = vm_alloc_pages(vm, 2); data->hcall_gpa = addr_gva2gpa(vm, data->hcall_gva); memset(addr_gva2hva(vm, data->hcall_gva), 0x0, 2 * PAGE_SIZE); @@ -606,7 +606,7 @@ int main(int argc, char *argv[]) * and the test will swap their mappings. The third page keeps the indication * about the current state of mappings. */ - data->test_pages = vm_vaddr_alloc_pages(vm, NTEST_PAGES + 1); + data->test_pages = vm_alloc_pages(vm, NTEST_PAGES + 1); for (i = 0; i < NTEST_PAGES; i++) memset(addr_gva2hva(vm, data->test_pages + PAGE_SIZE * i), (u8)(i + 1), PAGE_SIZE); @@ -617,7 +617,7 @@ int main(int argc, char *argv[]) * Get PTE pointers for test pages and map them inside the guest. * Use separate page for each PTE for simplicity. */ - gva = vm_vaddr_unused_gap(vm, NTEST_PAGES * PAGE_SIZE, KVM_UTIL_MIN_VADDR); + gva = vm_unused_gva_gap(vm, NTEST_PAGES * PAGE_SIZE, KVM_UTIL_MIN_VADDR); for (i = 0; i < NTEST_PAGES; i++) { pte = vm_get_pte(vm, data->test_pages + i * PAGE_SIZE); gpa = addr_hva2gpa(vm, pte); diff --git a/tools/testing/selftests/kvm/x86/kvm_buslock_test.c b/tools/testing/selftests/kvm/x86/kvm_buslock_test.c index d88500c118eb..52014a3210c8 100644 --- a/tools/testing/selftests/kvm/x86/kvm_buslock_test.c +++ b/tools/testing/selftests/kvm/x86/kvm_buslock_test.c @@ -73,7 +73,7 @@ static void guest_code(void *test_data) int main(int argc, char *argv[]) { const bool has_nested = kvm_cpu_has(X86_FEATURE_SVM) || kvm_cpu_has(X86_FEATURE_VMX); - vm_vaddr_t nested_test_data_gva; + gva_t nested_test_data_gva; struct kvm_vcpu *vcpu; struct kvm_run *run; struct kvm_vm *vm; diff --git a/tools/testing/selftests/kvm/x86/kvm_clock_test.c b/tools/testing/selftests/kvm/x86/kvm_clock_test.c index 5bc12222d87a..5ad4aeb8e373 100644 --- a/tools/testing/selftests/kvm/x86/kvm_clock_test.c +++ b/tools/testing/selftests/kvm/x86/kvm_clock_test.c @@ -17,8 +17,8 @@ #include "processor.h" struct test_case { - uint64_t kvmclock_base; - int64_t realtime_offset; + u64 kvmclock_base; + s64 realtime_offset; }; static struct test_case test_cases[] = { @@ -31,7 +31,7 @@ static struct test_case test_cases[] = { #define GUEST_SYNC_CLOCK(__stage, __val) \ GUEST_SYNC_ARGS(__stage, __val, 0, 0, 0) -static void guest_main(vm_paddr_t pvti_pa, struct pvclock_vcpu_time_info *pvti) +static void guest_main(gpa_t pvti_pa, struct pvclock_vcpu_time_info *pvti) { int i; @@ -52,7 +52,7 @@ static inline void assert_flags(struct kvm_clock_data *data) static void handle_sync(struct ucall *uc, struct kvm_clock_data *start, struct kvm_clock_data *end) { - uint64_t obs, exp_lo, exp_hi; + u64 obs, exp_lo, exp_hi; obs = uc->args[2]; exp_lo = start->clock; @@ -135,8 +135,8 @@ static void enter_guest(struct kvm_vcpu *vcpu) int main(void) { struct kvm_vcpu *vcpu; - vm_vaddr_t pvti_gva; - vm_paddr_t pvti_gpa; + gva_t pvti_gva; + gpa_t pvti_gpa; struct kvm_vm *vm; int flags; @@ -147,7 +147,7 @@ int main(void) vm = vm_create_with_one_vcpu(&vcpu, guest_main); - pvti_gva = vm_vaddr_alloc(vm, getpagesize(), 0x10000); + pvti_gva = vm_alloc(vm, getpagesize(), 0x10000); pvti_gpa = addr_gva2gpa(vm, pvti_gva); vcpu_args_set(vcpu, 2, pvti_gpa, pvti_gva); diff --git a/tools/testing/selftests/kvm/x86/kvm_pv_test.c b/tools/testing/selftests/kvm/x86/kvm_pv_test.c index 1b805cbdb47b..8ed5fa635021 100644 --- a/tools/testing/selftests/kvm/x86/kvm_pv_test.c +++ b/tools/testing/selftests/kvm/x86/kvm_pv_test.c @@ -13,7 +13,7 @@ #include "processor.h" struct msr_data { - uint32_t idx; + u32 idx; const char *name; }; @@ -40,8 +40,8 @@ static struct msr_data msrs_to_test[] = { static void test_msr(struct msr_data *msr) { - uint64_t ignored; - uint8_t vector; + u64 ignored; + u8 vector; PR_MSR(msr); @@ -53,7 +53,7 @@ static void test_msr(struct msr_data *msr) } struct hcall_data { - uint64_t nr; + u64 nr; const char *name; }; @@ -73,7 +73,7 @@ static struct hcall_data hcalls_to_test[] = { static void test_hcall(struct hcall_data *hc) { - uint64_t r; + u64 r; PR_HCALL(hc); r = kvm_hypercall(hc->nr, 0, 0, 0, 0); diff --git a/tools/testing/selftests/kvm/x86/monitor_mwait_test.c b/tools/testing/selftests/kvm/x86/monitor_mwait_test.c index e45c028d2a7e..9c156cf7db0e 100644 --- a/tools/testing/selftests/kvm/x86/monitor_mwait_test.c +++ b/tools/testing/selftests/kvm/x86/monitor_mwait_test.c @@ -67,7 +67,7 @@ static void guest_monitor_wait(void *arg) int main(int argc, char *argv[]) { - uint64_t disabled_quirks; + u64 disabled_quirks; struct kvm_vcpu *vcpu; struct kvm_vm *vm; struct ucall uc; diff --git a/tools/testing/selftests/kvm/x86/nested_close_kvm_test.c b/tools/testing/selftests/kvm/x86/nested_close_kvm_test.c index f001cb836bfa..761fec293408 100644 --- a/tools/testing/selftests/kvm/x86/nested_close_kvm_test.c +++ b/tools/testing/selftests/kvm/x86/nested_close_kvm_test.c @@ -67,7 +67,7 @@ static void l1_guest_code(void *data) int main(int argc, char *argv[]) { - vm_vaddr_t guest_gva; + gva_t guest_gva; struct kvm_vcpu *vcpu; struct kvm_vm *vm; diff --git a/tools/testing/selftests/kvm/x86/nested_dirty_log_test.c b/tools/testing/selftests/kvm/x86/nested_dirty_log_test.c index 619229bbd693..0e67cce83570 100644 --- a/tools/testing/selftests/kvm/x86/nested_dirty_log_test.c +++ b/tools/testing/selftests/kvm/x86/nested_dirty_log_test.c @@ -47,10 +47,10 @@ #define TEST_SYNC_WRITE_FAULT BIT(1) #define TEST_SYNC_NO_FAULT BIT(2) -static void l2_guest_code(vm_vaddr_t base) +static void l2_guest_code(gva_t base) { - vm_vaddr_t page0 = TEST_GUEST_ADDR(base, 0); - vm_vaddr_t page1 = TEST_GUEST_ADDR(base, 1); + gva_t page0 = TEST_GUEST_ADDR(base, 0); + gva_t page1 = TEST_GUEST_ADDR(base, 1); READ_ONCE(*(u64 *)page0); GUEST_SYNC(page0 | TEST_SYNC_READ_FAULT); @@ -143,7 +143,7 @@ static void l1_guest_code(void *data) static void test_handle_ucall_sync(struct kvm_vm *vm, u64 arg, unsigned long *bmap) { - vm_vaddr_t gva = arg & ~(PAGE_SIZE - 1); + gva_t gva = arg & ~(PAGE_SIZE - 1); int page_nr, i; /* @@ -198,7 +198,7 @@ static void test_handle_ucall_sync(struct kvm_vm *vm, u64 arg, static void test_dirty_log(bool nested_tdp) { - vm_vaddr_t nested_gva = 0; + gva_t nested_gva = 0; unsigned long *bmap; struct kvm_vcpu *vcpu; struct kvm_vm *vm; diff --git a/tools/testing/selftests/kvm/x86/nested_emulation_test.c b/tools/testing/selftests/kvm/x86/nested_emulation_test.c index abc824dba04f..fb7dcbe53ac7 100644 --- a/tools/testing/selftests/kvm/x86/nested_emulation_test.c +++ b/tools/testing/selftests/kvm/x86/nested_emulation_test.c @@ -13,8 +13,8 @@ enum { struct emulated_instruction { const char name[32]; - uint8_t opcode[15]; - uint32_t exit_reason[NR_VIRTUALIZATION_FLAVORS]; + u8 opcode[15]; + u32 exit_reason[NR_VIRTUALIZATION_FLAVORS]; }; static struct emulated_instruction instructions[] = { @@ -32,13 +32,13 @@ static struct emulated_instruction instructions[] = { }, }; -static uint8_t kvm_fep[] = { 0x0f, 0x0b, 0x6b, 0x76, 0x6d }; /* ud2 ; .ascii "kvm" */ -static uint8_t l2_guest_code[sizeof(kvm_fep) + 15]; -static uint8_t *l2_instruction = &l2_guest_code[sizeof(kvm_fep)]; +static u8 kvm_fep[] = { 0x0f, 0x0b, 0x6b, 0x76, 0x6d }; /* ud2 ; .ascii "kvm" */ +static u8 l2_guest_code[sizeof(kvm_fep) + 15]; +static u8 *l2_instruction = &l2_guest_code[sizeof(kvm_fep)]; -static uint32_t get_instruction_length(struct emulated_instruction *insn) +static u32 get_instruction_length(struct emulated_instruction *insn) { - uint32_t i; + u32 i; for (i = 0; i < ARRAY_SIZE(insn->opcode) && insn->opcode[i]; i++) ; @@ -81,8 +81,8 @@ static void guest_code(void *test_data) for (i = 0; i < ARRAY_SIZE(instructions); i++) { struct emulated_instruction *insn = &instructions[i]; - uint32_t insn_len = get_instruction_length(insn); - uint32_t exit_insn_len; + u32 insn_len = get_instruction_length(insn); + u32 exit_insn_len; u32 exit_reason; /* @@ -122,7 +122,7 @@ static void guest_code(void *test_data) int main(int argc, char *argv[]) { - vm_vaddr_t nested_test_data_gva; + gva_t nested_test_data_gva; struct kvm_vcpu *vcpu; struct kvm_vm *vm; diff --git a/tools/testing/selftests/kvm/x86/nested_exceptions_test.c b/tools/testing/selftests/kvm/x86/nested_exceptions_test.c index 3641a42934ac..186e980aa8ee 100644 --- a/tools/testing/selftests/kvm/x86/nested_exceptions_test.c +++ b/tools/testing/selftests/kvm/x86/nested_exceptions_test.c @@ -72,7 +72,7 @@ static void l2_ss_injected_tf_test(void) } static void svm_run_l2(struct svm_test_data *svm, void *l2_code, int vector, - uint32_t error_code) + u32 error_code) { struct vmcb *vmcb = svm->vmcb; struct vmcb_control_area *ctrl = &vmcb->control; @@ -111,7 +111,7 @@ static void l1_svm_code(struct svm_test_data *svm) GUEST_DONE(); } -static void vmx_run_l2(void *l2_code, int vector, uint32_t error_code) +static void vmx_run_l2(void *l2_code, int vector, u32 error_code) { GUEST_ASSERT(!vmwrite(GUEST_RIP, (u64)l2_code)); @@ -216,7 +216,7 @@ static void queue_ss_exception(struct kvm_vcpu *vcpu, bool inject) */ int main(int argc, char *argv[]) { - vm_vaddr_t nested_test_data_gva; + gva_t nested_test_data_gva; struct kvm_vcpu_events events; struct kvm_vcpu *vcpu; struct kvm_vm *vm; diff --git a/tools/testing/selftests/kvm/x86/nested_invalid_cr3_test.c b/tools/testing/selftests/kvm/x86/nested_invalid_cr3_test.c index a6b6da9cf7fe..11fd2467d823 100644 --- a/tools/testing/selftests/kvm/x86/nested_invalid_cr3_test.c +++ b/tools/testing/selftests/kvm/x86/nested_invalid_cr3_test.c @@ -78,7 +78,7 @@ int main(int argc, char *argv[]) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; - vm_vaddr_t guest_gva = 0; + gva_t guest_gva = 0; TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_VMX) || kvm_cpu_has(X86_FEATURE_SVM)); diff --git a/tools/testing/selftests/kvm/x86/nested_set_state_test.c b/tools/testing/selftests/kvm/x86/nested_set_state_test.c index 0f2102b43629..831380732671 100644 --- a/tools/testing/selftests/kvm/x86/nested_set_state_test.c +++ b/tools/testing/selftests/kvm/x86/nested_set_state_test.c @@ -250,14 +250,14 @@ void test_vmx_nested_state(struct kvm_vcpu *vcpu) static void vcpu_efer_enable_svm(struct kvm_vcpu *vcpu) { - uint64_t old_efer = vcpu_get_msr(vcpu, MSR_EFER); + u64 old_efer = vcpu_get_msr(vcpu, MSR_EFER); vcpu_set_msr(vcpu, MSR_EFER, old_efer | EFER_SVME); } static void vcpu_efer_disable_svm(struct kvm_vcpu *vcpu) { - uint64_t old_efer = vcpu_get_msr(vcpu, MSR_EFER); + u64 old_efer = vcpu_get_msr(vcpu, MSR_EFER); vcpu_set_msr(vcpu, MSR_EFER, old_efer & ~EFER_SVME); } diff --git a/tools/testing/selftests/kvm/x86/nested_tsc_adjust_test.c b/tools/testing/selftests/kvm/x86/nested_tsc_adjust_test.c index 2839f650e5c9..f0e4adac4751 100644 --- a/tools/testing/selftests/kvm/x86/nested_tsc_adjust_test.c +++ b/tools/testing/selftests/kvm/x86/nested_tsc_adjust_test.c @@ -53,9 +53,9 @@ enum { /* The virtual machine object. */ static struct kvm_vm *vm; -static void check_ia32_tsc_adjust(int64_t max) +static void check_ia32_tsc_adjust(s64 max) { - int64_t adjust; + s64 adjust; adjust = rdmsr(MSR_IA32_TSC_ADJUST); GUEST_SYNC(adjust); @@ -64,7 +64,7 @@ static void check_ia32_tsc_adjust(int64_t max) static void l2_guest_code(void) { - uint64_t l1_tsc = rdtsc() - TSC_OFFSET_VALUE; + u64 l1_tsc = rdtsc() - TSC_OFFSET_VALUE; wrmsr(MSR_IA32_TSC, l1_tsc - TSC_ADJUST_VALUE); check_ia32_tsc_adjust(-2 * TSC_ADJUST_VALUE); @@ -88,7 +88,7 @@ static void l1_guest_code(void *data) */ if (this_cpu_has(X86_FEATURE_VMX)) { struct vmx_pages *vmx_pages = data; - uint32_t control; + u32 control; GUEST_ASSERT(prepare_for_vmx_operation(vmx_pages)); GUEST_ASSERT(load_vmcs(vmx_pages)); @@ -117,7 +117,7 @@ static void l1_guest_code(void *data) GUEST_DONE(); } -static void report(int64_t val) +static void report(s64 val) { pr_info("IA32_TSC_ADJUST is %ld (%lld * TSC_ADJUST_VALUE + %lld).\n", val, val / TSC_ADJUST_VALUE, val % TSC_ADJUST_VALUE); @@ -125,7 +125,7 @@ static void report(int64_t val) int main(int argc, char *argv[]) { - vm_vaddr_t nested_gva; + gva_t nested_gva; struct kvm_vcpu *vcpu; TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_VMX) || diff --git a/tools/testing/selftests/kvm/x86/nested_tsc_scaling_test.c b/tools/testing/selftests/kvm/x86/nested_tsc_scaling_test.c index 4260c9e4f489..190e93af20a1 100644 --- a/tools/testing/selftests/kvm/x86/nested_tsc_scaling_test.c +++ b/tools/testing/selftests/kvm/x86/nested_tsc_scaling_test.c @@ -19,7 +19,7 @@ /* L2 is scaled up (from L1's perspective) by this factor */ #define L2_SCALE_FACTOR 4ULL -#define TSC_OFFSET_L2 ((uint64_t) -33125236320908) +#define TSC_OFFSET_L2 ((u64)-33125236320908) #define TSC_MULTIPLIER_L2 (L2_SCALE_FACTOR << 48) #define L2_GUEST_STACK_SIZE 64 @@ -35,9 +35,9 @@ enum { USLEEP, UCHECK_L1, UCHECK_L2 }; * measurements, a difference of 1% between the actual and the expected value * is tolerated. */ -static void compare_tsc_freq(uint64_t actual, uint64_t expected) +static void compare_tsc_freq(u64 actual, u64 expected) { - uint64_t tolerance, thresh_low, thresh_high; + u64 tolerance, thresh_low, thresh_high; tolerance = expected / 100; thresh_low = expected - tolerance; @@ -55,7 +55,7 @@ static void compare_tsc_freq(uint64_t actual, uint64_t expected) static void check_tsc_freq(int level) { - uint64_t tsc_start, tsc_end, tsc_freq; + u64 tsc_start, tsc_end, tsc_freq; /* * Reading the TSC twice with about a second's difference should give @@ -106,7 +106,7 @@ static void l1_svm_code(struct svm_test_data *svm) static void l1_vmx_code(struct vmx_pages *vmx_pages) { unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE]; - uint32_t control; + u32 control; /* check that L1's frequency looks alright before launching L2 */ check_tsc_freq(UCHECK_L1); @@ -152,14 +152,14 @@ int main(int argc, char *argv[]) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; - vm_vaddr_t guest_gva = 0; + gva_t guest_gva = 0; - uint64_t tsc_start, tsc_end; - uint64_t tsc_khz; - uint64_t l1_scale_factor; - uint64_t l0_tsc_freq = 0; - uint64_t l1_tsc_freq = 0; - uint64_t l2_tsc_freq = 0; + u64 tsc_start, tsc_end; + u64 tsc_khz; + u64 l1_scale_factor; + u64 l0_tsc_freq = 0; + u64 l1_tsc_freq = 0; + u64 l2_tsc_freq = 0; TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_VMX) || kvm_cpu_has(X86_FEATURE_SVM)); diff --git a/tools/testing/selftests/kvm/x86/nested_vmsave_vmload_test.c b/tools/testing/selftests/kvm/x86/nested_vmsave_vmload_test.c index 71717118d692..85d3f4cc76f3 100644 --- a/tools/testing/selftests/kvm/x86/nested_vmsave_vmload_test.c +++ b/tools/testing/selftests/kvm/x86/nested_vmsave_vmload_test.c @@ -128,7 +128,7 @@ static void l1_guest_code(struct svm_test_data *svm) int main(int argc, char *argv[]) { - vm_vaddr_t nested_gva = 0; + gva_t nested_gva = 0; struct vmcb *test_vmcb[2]; struct kvm_vcpu *vcpu; struct kvm_vm *vm; diff --git a/tools/testing/selftests/kvm/x86/nx_huge_pages_test.c b/tools/testing/selftests/kvm/x86/nx_huge_pages_test.c index c0d84827f736..70950067b989 100644 --- a/tools/testing/selftests/kvm/x86/nx_huge_pages_test.c +++ b/tools/testing/selftests/kvm/x86/nx_huge_pages_test.c @@ -32,7 +32,7 @@ #define RETURN_OPCODE 0xC3 /* Call the specified memory address. */ -static void guest_do_CALL(uint64_t target) +static void guest_do_CALL(u64 target) { ((void (*)(void)) target)(); } @@ -46,14 +46,14 @@ static void guest_do_CALL(uint64_t target) */ void guest_code(void) { - uint64_t hpage_1 = HPAGE_GVA; - uint64_t hpage_2 = hpage_1 + (PAGE_SIZE * 512); - uint64_t hpage_3 = hpage_2 + (PAGE_SIZE * 512); + u64 hpage_1 = HPAGE_GVA; + u64 hpage_2 = hpage_1 + (PAGE_SIZE * 512); + u64 hpage_3 = hpage_2 + (PAGE_SIZE * 512); - READ_ONCE(*(uint64_t *)hpage_1); + READ_ONCE(*(u64 *)hpage_1); GUEST_SYNC(1); - READ_ONCE(*(uint64_t *)hpage_2); + READ_ONCE(*(u64 *)hpage_2); GUEST_SYNC(2); guest_do_CALL(hpage_1); @@ -62,10 +62,10 @@ void guest_code(void) guest_do_CALL(hpage_3); GUEST_SYNC(4); - READ_ONCE(*(uint64_t *)hpage_1); + READ_ONCE(*(u64 *)hpage_1); GUEST_SYNC(5); - READ_ONCE(*(uint64_t *)hpage_3); + READ_ONCE(*(u64 *)hpage_3); GUEST_SYNC(6); } @@ -107,7 +107,7 @@ void run_test(int reclaim_period_ms, bool disable_nx_huge_pages, { struct kvm_vcpu *vcpu; struct kvm_vm *vm; - uint64_t nr_bytes; + u64 nr_bytes; void *hva; int r; diff --git a/tools/testing/selftests/kvm/x86/platform_info_test.c b/tools/testing/selftests/kvm/x86/platform_info_test.c index 9cbf283ebc55..80bb07e6531c 100644 --- a/tools/testing/selftests/kvm/x86/platform_info_test.c +++ b/tools/testing/selftests/kvm/x86/platform_info_test.c @@ -23,8 +23,8 @@ static void guest_code(void) { - uint64_t msr_platform_info; - uint8_t vector; + u64 msr_platform_info; + u8 vector; GUEST_SYNC(true); msr_platform_info = rdmsr(MSR_PLATFORM_INFO); @@ -42,7 +42,7 @@ int main(int argc, char *argv[]) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; - uint64_t msr_platform_info; + u64 msr_platform_info; struct ucall uc; TEST_REQUIRE(kvm_has_cap(KVM_CAP_MSR_PLATFORM_INFO)); diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/testing/selftests/kvm/x86/pmu_counters_test.c index 3eaa216b96c0..dc6afac3aa91 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -30,9 +30,9 @@ #define NUM_INSNS_RETIRED (NUM_LOOPS * NUM_INSNS_PER_LOOP + NUM_EXTRA_INSNS) /* Track which architectural events are supported by hardware. */ -static uint32_t hardware_pmu_arch_events; +static u32 hardware_pmu_arch_events; -static uint8_t kvm_pmu_version; +static u8 kvm_pmu_version; static bool kvm_has_perf_caps; #define X86_PMU_FEATURE_NULL \ @@ -57,7 +57,7 @@ struct kvm_intel_pmu_event { * kvm_x86_pmu_feature use syntax that's only valid in function scope, and the * compiler often thinks the feature definitions aren't compile-time constants. */ -static struct kvm_intel_pmu_event intel_event_to_feature(uint8_t idx) +static struct kvm_intel_pmu_event intel_event_to_feature(u8 idx) { const struct kvm_intel_pmu_event __intel_event_to_feature[] = { [INTEL_ARCH_CPU_CYCLES_INDEX] = { X86_PMU_FEATURE_CPU_CYCLES, X86_PMU_FEATURE_CPU_CYCLES_FIXED }, @@ -89,8 +89,8 @@ static struct kvm_intel_pmu_event intel_event_to_feature(uint8_t idx) static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct kvm_vcpu **vcpu, void *guest_code, - uint8_t pmu_version, - uint64_t perf_capabilities) + u8 pmu_version, + u64 perf_capabilities) { struct kvm_vm *vm; @@ -132,7 +132,7 @@ static void run_vcpu(struct kvm_vcpu *vcpu) } while (uc.cmd != UCALL_DONE); } -static uint8_t guest_get_pmu_version(void) +static u8 guest_get_pmu_version(void) { /* * Return the effective PMU version, i.e. the minimum between what KVM @@ -141,7 +141,7 @@ static uint8_t guest_get_pmu_version(void) * supported by KVM to verify KVM doesn't freak out and do something * bizarre with an architecturally valid, but unsupported, version. */ - return min_t(uint8_t, kvm_pmu_version, this_cpu_property(X86_PROPERTY_PMU_VERSION)); + return min_t(u8, kvm_pmu_version, this_cpu_property(X86_PROPERTY_PMU_VERSION)); } /* @@ -153,9 +153,9 @@ static uint8_t guest_get_pmu_version(void) * Sanity check that in all cases, the event doesn't count when it's disabled, * and that KVM correctly emulates the write of an arbitrary value. */ -static void guest_assert_event_count(uint8_t idx, uint32_t pmc, uint32_t pmc_msr) +static void guest_assert_event_count(u8 idx, u32 pmc, u32 pmc_msr) { - uint64_t count; + u64 count; count = _rdpmc(pmc); if (!(hardware_pmu_arch_events & BIT(idx))) @@ -236,7 +236,7 @@ do { \ FEP "xor %%eax, %%eax\n\t" \ FEP "xor %%edx, %%edx\n\t" \ "wrmsr\n\t" \ - :: "a"((uint32_t)_value), "d"(_value >> 32), \ + :: "a"((u32)_value), "d"(_value >> 32), \ "c"(_msr), "D"(_msr), [m]"m"(kvm_pmu_version) \ ); \ } while (0) @@ -255,8 +255,8 @@ do { \ guest_assert_event_count(_idx, _pmc, _pmc_msr); \ } while (0) -static void __guest_test_arch_event(uint8_t idx, uint32_t pmc, uint32_t pmc_msr, - uint32_t ctrl_msr, uint64_t ctrl_msr_value) +static void __guest_test_arch_event(u8 idx, u32 pmc, u32 pmc_msr, + u32 ctrl_msr, u64 ctrl_msr_value) { GUEST_TEST_EVENT(idx, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, ""); @@ -264,14 +264,14 @@ static void __guest_test_arch_event(uint8_t idx, uint32_t pmc, uint32_t pmc_msr, GUEST_TEST_EVENT(idx, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, KVM_FEP); } -static void guest_test_arch_event(uint8_t idx) +static void guest_test_arch_event(u8 idx) { - uint32_t nr_gp_counters = this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); - uint32_t pmu_version = guest_get_pmu_version(); + u32 nr_gp_counters = this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); + u32 pmu_version = guest_get_pmu_version(); /* PERF_GLOBAL_CTRL exists only for Architectural PMU Version 2+. */ bool guest_has_perf_global_ctrl = pmu_version >= 2; struct kvm_x86_pmu_feature gp_event, fixed_event; - uint32_t base_pmc_msr; + u32 base_pmc_msr; unsigned int i; /* The host side shouldn't invoke this without a guest PMU. */ @@ -289,7 +289,7 @@ static void guest_test_arch_event(uint8_t idx) GUEST_ASSERT(nr_gp_counters); for (i = 0; i < nr_gp_counters; i++) { - uint64_t eventsel = ARCH_PERFMON_EVENTSEL_OS | + u64 eventsel = ARCH_PERFMON_EVENTSEL_OS | ARCH_PERFMON_EVENTSEL_ENABLE | intel_pmu_arch_events[idx]; @@ -320,7 +320,7 @@ static void guest_test_arch_event(uint8_t idx) static void guest_test_arch_events(void) { - uint8_t i; + u8 i; for (i = 0; i < NR_INTEL_ARCH_EVENTS; i++) guest_test_arch_event(i); @@ -328,8 +328,8 @@ static void guest_test_arch_events(void) GUEST_DONE(); } -static void test_arch_events(uint8_t pmu_version, uint64_t perf_capabilities, - uint8_t length, uint32_t unavailable_mask) +static void test_arch_events(u8 pmu_version, u64 perf_capabilities, + u8 length, u32 unavailable_mask) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; @@ -373,11 +373,11 @@ __GUEST_ASSERT(expect_gp ? vector == GP_VECTOR : !vector, \ "Expected " #insn "(0x%x) to yield 0x%lx, got 0x%lx", \ msr, expected, val); -static void guest_test_rdpmc(uint32_t rdpmc_idx, bool expect_success, - uint64_t expected_val) +static void guest_test_rdpmc(u32 rdpmc_idx, bool expect_success, + u64 expected_val) { - uint8_t vector; - uint64_t val; + u8 vector; + u64 val; vector = rdpmc_safe(rdpmc_idx, &val); GUEST_ASSERT_PMC_MSR_ACCESS(RDPMC, rdpmc_idx, !expect_success, vector); @@ -393,19 +393,19 @@ static void guest_test_rdpmc(uint32_t rdpmc_idx, bool expect_success, GUEST_ASSERT_PMC_VALUE(RDPMC, rdpmc_idx, val, expected_val); } -static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_counters, - uint8_t nr_counters, uint32_t or_mask) +static void guest_rd_wr_counters(u32 base_msr, u8 nr_possible_counters, + u8 nr_counters, u32 or_mask) { const bool pmu_has_fast_mode = !guest_get_pmu_version(); - uint8_t i; + u8 i; for (i = 0; i < nr_possible_counters; i++) { /* * TODO: Test a value that validates full-width writes and the * width of the counters. */ - const uint64_t test_val = 0xffff; - const uint32_t msr = base_msr + i; + const u64 test_val = 0xffff; + const u32 msr = base_msr + i; /* * Fixed counters are supported if the counter is less than the @@ -418,12 +418,12 @@ static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_counters * KVM drops writes to MSR_P6_PERFCTR[0|1] if the counters are * unsupported, i.e. doesn't #GP and reads back '0'. */ - const uint64_t expected_val = expect_success ? test_val : 0; + const u64 expected_val = expect_success ? test_val : 0; const bool expect_gp = !expect_success && msr != MSR_P6_PERFCTR0 && msr != MSR_P6_PERFCTR1; - uint32_t rdpmc_idx; - uint8_t vector; - uint64_t val; + u32 rdpmc_idx; + u8 vector; + u64 val; vector = wrmsr_safe(msr, test_val); GUEST_ASSERT_PMC_MSR_ACCESS(WRMSR, msr, expect_gp, vector); @@ -461,9 +461,9 @@ static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_counters static void guest_test_gp_counters(void) { - uint8_t pmu_version = guest_get_pmu_version(); - uint8_t nr_gp_counters = 0; - uint32_t base_msr; + u8 pmu_version = guest_get_pmu_version(); + u8 nr_gp_counters = 0; + u32 base_msr; if (pmu_version) nr_gp_counters = this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); @@ -477,7 +477,7 @@ static void guest_test_gp_counters(void) * counters, of which there are none. */ if (pmu_version > 1) { - uint64_t global_ctrl = rdmsr(MSR_CORE_PERF_GLOBAL_CTRL); + u64 global_ctrl = rdmsr(MSR_CORE_PERF_GLOBAL_CTRL); if (nr_gp_counters) GUEST_ASSERT_EQ(global_ctrl, GENMASK_ULL(nr_gp_counters - 1, 0)); @@ -495,8 +495,8 @@ static void guest_test_gp_counters(void) GUEST_DONE(); } -static void test_gp_counters(uint8_t pmu_version, uint64_t perf_capabilities, - uint8_t nr_gp_counters) +static void test_gp_counters(u8 pmu_version, u64 perf_capabilities, + u8 nr_gp_counters) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; @@ -514,9 +514,9 @@ static void test_gp_counters(uint8_t pmu_version, uint64_t perf_capabilities, static void guest_test_fixed_counters(void) { - uint64_t supported_bitmask = 0; - uint8_t nr_fixed_counters = 0; - uint8_t i; + u64 supported_bitmask = 0; + u8 nr_fixed_counters = 0; + u8 i; /* Fixed counters require Architectural vPMU Version 2+. */ if (guest_get_pmu_version() >= 2) @@ -533,8 +533,8 @@ static void guest_test_fixed_counters(void) nr_fixed_counters, supported_bitmask); for (i = 0; i < MAX_NR_FIXED_COUNTERS; i++) { - uint8_t vector; - uint64_t val; + u8 vector; + u64 val; if (i >= nr_fixed_counters && !(supported_bitmask & BIT_ULL(i))) { vector = wrmsr_safe(MSR_CORE_PERF_FIXED_CTR_CTRL, @@ -561,9 +561,8 @@ static void guest_test_fixed_counters(void) GUEST_DONE(); } -static void test_fixed_counters(uint8_t pmu_version, uint64_t perf_capabilities, - uint8_t nr_fixed_counters, - uint32_t supported_bitmask) +static void test_fixed_counters(u8 pmu_version, u64 perf_capabilities, + u8 nr_fixed_counters, u32 supported_bitmask) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; @@ -583,14 +582,14 @@ static void test_fixed_counters(uint8_t pmu_version, uint64_t perf_capabilities, static void test_intel_counters(void) { - uint8_t nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); - uint8_t nr_gp_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); - uint8_t pmu_version = kvm_cpu_property(X86_PROPERTY_PMU_VERSION); + u8 nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); + u8 nr_gp_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); + u8 pmu_version = kvm_cpu_property(X86_PROPERTY_PMU_VERSION); unsigned int i; - uint8_t v, j; - uint32_t k; + u8 v, j; + u32 k; - const uint64_t perf_caps[] = { + const u64 perf_caps[] = { 0, PMU_CAP_FW_WRITES, }; @@ -602,7 +601,7 @@ static void test_intel_counters(void) * as alternating bit sequencues, e.g. to detect if KVM is checking the * wrong bit(s). */ - const uint32_t unavailable_masks[] = { + const u32 unavailable_masks[] = { 0x0, 0xffffffffu, 0xaaaaaaaau, @@ -620,7 +619,7 @@ static void test_intel_counters(void) * Intel, i.e. is the last version that is guaranteed to be backwards * compatible with KVM's existing behavior. */ - uint8_t max_pmu_version = max_t(typeof(pmu_version), pmu_version, 5); + u8 max_pmu_version = max_t(typeof(pmu_version), pmu_version, 5); /* * Detect the existence of events that aren't supported by selftests. diff --git a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c b/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c index 93b61c077991..c1232344fda8 100644 --- a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c @@ -53,11 +53,11 @@ static const struct __kvm_pmu_event_filter base_event_filter = { }; struct { - uint64_t loads; - uint64_t stores; - uint64_t loads_stores; - uint64_t branches_retired; - uint64_t instructions_retired; + u64 loads; + u64 stores; + u64 loads_stores; + u64 branches_retired; + u64 instructions_retired; } pmc_results; /* @@ -75,9 +75,9 @@ static void guest_gp_handler(struct ex_regs *regs) * * Return on success. GUEST_SYNC(0) on error. */ -static void check_msr(uint32_t msr, uint64_t bits_to_flip) +static void check_msr(u32 msr, u64 bits_to_flip) { - uint64_t v = rdmsr(msr) ^ bits_to_flip; + u64 v = rdmsr(msr) ^ bits_to_flip; wrmsr(msr, v); if (rdmsr(msr) != v) @@ -89,10 +89,10 @@ static void check_msr(uint32_t msr, uint64_t bits_to_flip) GUEST_SYNC(-EIO); } -static void run_and_measure_loop(uint32_t msr_base) +static void run_and_measure_loop(u32 msr_base) { - const uint64_t branches_retired = rdmsr(msr_base + 0); - const uint64_t insn_retired = rdmsr(msr_base + 1); + const u64 branches_retired = rdmsr(msr_base + 0); + const u64 insn_retired = rdmsr(msr_base + 1); __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); @@ -147,7 +147,7 @@ static void amd_guest_code(void) * Run the VM to the next GUEST_SYNC(value), and return the value passed * to the sync. Any other exit from the guest is fatal. */ -static uint64_t run_vcpu_to_sync(struct kvm_vcpu *vcpu) +static u64 run_vcpu_to_sync(struct kvm_vcpu *vcpu) { struct ucall uc; @@ -161,7 +161,7 @@ static uint64_t run_vcpu_to_sync(struct kvm_vcpu *vcpu) static void run_vcpu_and_sync_pmc_results(struct kvm_vcpu *vcpu) { - uint64_t r; + u64 r; memset(&pmc_results, 0, sizeof(pmc_results)); sync_global_to_guest(vcpu->vm, pmc_results); @@ -182,7 +182,7 @@ static void run_vcpu_and_sync_pmc_results(struct kvm_vcpu *vcpu) */ static bool sanity_check_pmu(struct kvm_vcpu *vcpu) { - uint64_t r; + u64 r; vm_install_exception_handler(vcpu->vm, GP_VECTOR, guest_gp_handler); r = run_vcpu_to_sync(vcpu); @@ -195,7 +195,7 @@ static bool sanity_check_pmu(struct kvm_vcpu *vcpu) * Remove the first occurrence of 'event' (if any) from the filter's * event list. */ -static void remove_event(struct __kvm_pmu_event_filter *f, uint64_t event) +static void remove_event(struct __kvm_pmu_event_filter *f, u64 event) { bool found = false; int i; @@ -212,8 +212,8 @@ static void remove_event(struct __kvm_pmu_event_filter *f, uint64_t event) #define ASSERT_PMC_COUNTING_INSTRUCTIONS() \ do { \ - uint64_t br = pmc_results.branches_retired; \ - uint64_t ir = pmc_results.instructions_retired; \ + u64 br = pmc_results.branches_retired; \ + u64 ir = pmc_results.instructions_retired; \ bool br_matched = this_pmu_has_errata(BRANCHES_RETIRED_OVERCOUNT) ? \ br >= NUM_BRANCHES : br == NUM_BRANCHES; \ \ @@ -228,8 +228,8 @@ do { \ #define ASSERT_PMC_NOT_COUNTING_INSTRUCTIONS() \ do { \ - uint64_t br = pmc_results.branches_retired; \ - uint64_t ir = pmc_results.instructions_retired; \ + u64 br = pmc_results.branches_retired; \ + u64 ir = pmc_results.instructions_retired; \ \ TEST_ASSERT(!br, "%s: Branch instructions retired = %lu (expected 0)", \ __func__, br); \ @@ -378,7 +378,7 @@ static bool use_amd_pmu(void) static bool supports_event_mem_inst_retired(void) { - uint32_t eax, ebx, ecx, edx; + u32 eax, ebx, ecx, edx; cpuid(1, &eax, &ebx, &ecx, &edx); if (x86_family(eax) == 0x6) { @@ -415,15 +415,15 @@ static bool supports_event_mem_inst_retired(void) #define EXCLUDE_MASKED_ENTRY(event_select, mask, match) \ KVM_PMU_ENCODE_MASKED_ENTRY(event_select, mask, match, true) -static void masked_events_guest_test(uint32_t msr_base) +static void masked_events_guest_test(u32 msr_base) { /* * The actual value of the counters don't determine the outcome of * the test. Only that they are zero or non-zero. */ - const uint64_t loads = rdmsr(msr_base + 0); - const uint64_t stores = rdmsr(msr_base + 1); - const uint64_t loads_stores = rdmsr(msr_base + 2); + const u64 loads = rdmsr(msr_base + 0); + const u64 stores = rdmsr(msr_base + 1); + const u64 loads_stores = rdmsr(msr_base + 2); int val; @@ -476,7 +476,7 @@ static void amd_masked_events_guest_code(void) } static void run_masked_events_test(struct kvm_vcpu *vcpu, - const uint64_t masked_events[], + const u64 masked_events[], const int nmasked_events) { struct __kvm_pmu_event_filter f = { @@ -485,7 +485,7 @@ static void run_masked_events_test(struct kvm_vcpu *vcpu, .flags = KVM_PMU_EVENT_FLAG_MASKED_EVENTS, }; - memcpy(f.events, masked_events, sizeof(uint64_t) * nmasked_events); + memcpy(f.events, masked_events, sizeof(u64) * nmasked_events); test_with_filter(vcpu, &f); } @@ -494,12 +494,12 @@ static void run_masked_events_test(struct kvm_vcpu *vcpu, #define ALLOW_LOADS_STORES BIT(2) struct masked_events_test { - uint64_t intel_events[MAX_TEST_EVENTS]; - uint64_t intel_event_end; - uint64_t amd_events[MAX_TEST_EVENTS]; - uint64_t amd_event_end; + u64 intel_events[MAX_TEST_EVENTS]; + u64 intel_event_end; + u64 amd_events[MAX_TEST_EVENTS]; + u64 amd_event_end; const char *msg; - uint32_t flags; + u32 flags; }; /* @@ -582,9 +582,9 @@ const struct masked_events_test test_cases[] = { }; static int append_test_events(const struct masked_events_test *test, - uint64_t *events, int nevents) + u64 *events, int nevents) { - const uint64_t *evts; + const u64 *evts; int i; evts = use_intel_pmu() ? test->intel_events : test->amd_events; @@ -603,7 +603,7 @@ static bool bool_eq(bool a, bool b) return a == b; } -static void run_masked_events_tests(struct kvm_vcpu *vcpu, uint64_t *events, +static void run_masked_events_tests(struct kvm_vcpu *vcpu, u64 *events, int nevents) { int ntests = ARRAY_SIZE(test_cases); @@ -630,7 +630,7 @@ static void run_masked_events_tests(struct kvm_vcpu *vcpu, uint64_t *events, } } -static void add_dummy_events(uint64_t *events, int nevents) +static void add_dummy_events(u64 *events, int nevents) { int i; @@ -650,7 +650,7 @@ static void add_dummy_events(uint64_t *events, int nevents) static void test_masked_events(struct kvm_vcpu *vcpu) { int nevents = KVM_PMU_EVENT_FILTER_MAX_EVENTS - MAX_TEST_EVENTS; - uint64_t events[KVM_PMU_EVENT_FILTER_MAX_EVENTS]; + u64 events[KVM_PMU_EVENT_FILTER_MAX_EVENTS]; /* Run the test cases against a sparse PMU event filter. */ run_masked_events_tests(vcpu, events, 0); @@ -668,8 +668,8 @@ static int set_pmu_event_filter(struct kvm_vcpu *vcpu, return __vm_ioctl(vcpu->vm, KVM_SET_PMU_EVENT_FILTER, f); } -static int set_pmu_single_event_filter(struct kvm_vcpu *vcpu, uint64_t event, - uint32_t flags, uint32_t action) +static int set_pmu_single_event_filter(struct kvm_vcpu *vcpu, u64 event, + u32 flags, u32 action) { struct __kvm_pmu_event_filter f = { .nevents = 1, @@ -685,9 +685,9 @@ static int set_pmu_single_event_filter(struct kvm_vcpu *vcpu, uint64_t event, static void test_filter_ioctl(struct kvm_vcpu *vcpu) { - uint8_t nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); + u8 nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); struct __kvm_pmu_event_filter f; - uint64_t e = ~0ul; + u64 e = ~0ul; int r; /* @@ -729,7 +729,7 @@ static void test_filter_ioctl(struct kvm_vcpu *vcpu) TEST_ASSERT(!r, "Masking non-existent fixed counters should be allowed"); } -static void intel_run_fixed_counter_guest_code(uint8_t idx) +static void intel_run_fixed_counter_guest_code(u8 idx) { for (;;) { wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); @@ -745,8 +745,8 @@ static void intel_run_fixed_counter_guest_code(uint8_t idx) } } -static uint64_t test_with_fixed_counter_filter(struct kvm_vcpu *vcpu, - uint32_t action, uint32_t bitmap) +static u64 test_with_fixed_counter_filter(struct kvm_vcpu *vcpu, + u32 action, u32 bitmap) { struct __kvm_pmu_event_filter f = { .action = action, @@ -757,9 +757,9 @@ static uint64_t test_with_fixed_counter_filter(struct kvm_vcpu *vcpu, return run_vcpu_to_sync(vcpu); } -static uint64_t test_set_gp_and_fixed_event_filter(struct kvm_vcpu *vcpu, - uint32_t action, - uint32_t bitmap) +static u64 test_set_gp_and_fixed_event_filter(struct kvm_vcpu *vcpu, + u32 action, + u32 bitmap) { struct __kvm_pmu_event_filter f = base_event_filter; @@ -770,12 +770,12 @@ static uint64_t test_set_gp_and_fixed_event_filter(struct kvm_vcpu *vcpu, return run_vcpu_to_sync(vcpu); } -static void __test_fixed_counter_bitmap(struct kvm_vcpu *vcpu, uint8_t idx, - uint8_t nr_fixed_counters) +static void __test_fixed_counter_bitmap(struct kvm_vcpu *vcpu, u8 idx, + u8 nr_fixed_counters) { unsigned int i; - uint32_t bitmap; - uint64_t count; + u32 bitmap; + u64 count; TEST_ASSERT(nr_fixed_counters < sizeof(bitmap) * 8, "Invalid nr_fixed_counters"); @@ -815,10 +815,10 @@ static void __test_fixed_counter_bitmap(struct kvm_vcpu *vcpu, uint8_t idx, static void test_fixed_counter_bitmap(void) { - uint8_t nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); + u8 nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); struct kvm_vm *vm; struct kvm_vcpu *vcpu; - uint8_t idx; + u8 idx; /* * Check that pmu_event_filter works as expected when it's applied to diff --git a/tools/testing/selftests/kvm/x86/private_mem_conversions_test.c b/tools/testing/selftests/kvm/x86/private_mem_conversions_test.c index 1969f4ab9b28..1d2f5d4fd45d 100644 --- a/tools/testing/selftests/kvm/x86/private_mem_conversions_test.c +++ b/tools/testing/selftests/kvm/x86/private_mem_conversions_test.c @@ -23,13 +23,13 @@ #include #define BASE_DATA_SLOT 10 -#define BASE_DATA_GPA ((uint64_t)(1ull << 32)) -#define PER_CPU_DATA_SIZE ((uint64_t)(SZ_2M + PAGE_SIZE)) +#define BASE_DATA_GPA ((u64)(1ull << 32)) +#define PER_CPU_DATA_SIZE ((u64)(SZ_2M + PAGE_SIZE)) /* Horrific macro so that the line info is captured accurately :-( */ #define memcmp_g(gpa, pattern, size) \ do { \ - uint8_t *mem = (uint8_t *)gpa; \ + u8 *mem = (u8 *)gpa; \ size_t i; \ \ for (i = 0; i < size; i++) \ @@ -38,7 +38,7 @@ do { \ pattern, i, gpa + i, mem[i]); \ } while (0) -static void memcmp_h(uint8_t *mem, uint64_t gpa, uint8_t pattern, size_t size) +static void memcmp_h(u8 *mem, gpa_t gpa, u8 pattern, size_t size) { size_t i; @@ -70,13 +70,13 @@ enum ucall_syncs { SYNC_PRIVATE, }; -static void guest_sync_shared(uint64_t gpa, uint64_t size, - uint8_t current_pattern, uint8_t new_pattern) +static void guest_sync_shared(gpa_t gpa, u64 size, + u8 current_pattern, u8 new_pattern) { GUEST_SYNC5(SYNC_SHARED, gpa, size, current_pattern, new_pattern); } -static void guest_sync_private(uint64_t gpa, uint64_t size, uint8_t pattern) +static void guest_sync_private(gpa_t gpa, u64 size, u8 pattern) { GUEST_SYNC4(SYNC_PRIVATE, gpa, size, pattern); } @@ -86,10 +86,10 @@ static void guest_sync_private(uint64_t gpa, uint64_t size, uint8_t pattern) #define MAP_GPA_SHARED BIT(1) #define MAP_GPA_DO_FALLOCATE BIT(2) -static void guest_map_mem(uint64_t gpa, uint64_t size, bool map_shared, +static void guest_map_mem(gpa_t gpa, u64 size, bool map_shared, bool do_fallocate) { - uint64_t flags = MAP_GPA_SET_ATTRIBUTES; + u64 flags = MAP_GPA_SET_ATTRIBUTES; if (map_shared) flags |= MAP_GPA_SHARED; @@ -98,19 +98,19 @@ static void guest_map_mem(uint64_t gpa, uint64_t size, bool map_shared, kvm_hypercall_map_gpa_range(gpa, size, flags); } -static void guest_map_shared(uint64_t gpa, uint64_t size, bool do_fallocate) +static void guest_map_shared(gpa_t gpa, u64 size, bool do_fallocate) { guest_map_mem(gpa, size, true, do_fallocate); } -static void guest_map_private(uint64_t gpa, uint64_t size, bool do_fallocate) +static void guest_map_private(gpa_t gpa, u64 size, bool do_fallocate) { guest_map_mem(gpa, size, false, do_fallocate); } struct { - uint64_t offset; - uint64_t size; + u64 offset; + u64 size; } static const test_ranges[] = { GUEST_STAGE(0, PAGE_SIZE), GUEST_STAGE(0, SZ_2M), @@ -119,11 +119,11 @@ struct { GUEST_STAGE(SZ_2M, PAGE_SIZE), }; -static void guest_test_explicit_conversion(uint64_t base_gpa, bool do_fallocate) +static void guest_test_explicit_conversion(u64 base_gpa, bool do_fallocate) { - const uint8_t def_p = 0xaa; - const uint8_t init_p = 0xcc; - uint64_t j; + const u8 def_p = 0xaa; + const u8 init_p = 0xcc; + u64 j; int i; /* Memory should be shared by default. */ @@ -134,12 +134,12 @@ static void guest_test_explicit_conversion(uint64_t base_gpa, bool do_fallocate) memcmp_g(base_gpa, init_p, PER_CPU_DATA_SIZE); for (i = 0; i < ARRAY_SIZE(test_ranges); i++) { - uint64_t gpa = base_gpa + test_ranges[i].offset; - uint64_t size = test_ranges[i].size; - uint8_t p1 = 0x11; - uint8_t p2 = 0x22; - uint8_t p3 = 0x33; - uint8_t p4 = 0x44; + gpa_t gpa = base_gpa + test_ranges[i].offset; + u64 size = test_ranges[i].size; + u8 p1 = 0x11; + u8 p2 = 0x22; + u8 p3 = 0x33; + u8 p4 = 0x44; /* * Set the test region to pattern one to differentiate it from @@ -214,10 +214,10 @@ static void guest_test_explicit_conversion(uint64_t base_gpa, bool do_fallocate) } } -static void guest_punch_hole(uint64_t gpa, uint64_t size) +static void guest_punch_hole(gpa_t gpa, u64 size) { /* "Mapping" memory shared via fallocate() is done via PUNCH_HOLE. */ - uint64_t flags = MAP_GPA_SHARED | MAP_GPA_DO_FALLOCATE; + u64 flags = MAP_GPA_SHARED | MAP_GPA_DO_FALLOCATE; kvm_hypercall_map_gpa_range(gpa, size, flags); } @@ -227,9 +227,9 @@ static void guest_punch_hole(uint64_t gpa, uint64_t size) * proper conversion. Freeing (PUNCH_HOLE) should zap SPTEs, and reallocating * (subsequent fault) should zero memory. */ -static void guest_test_punch_hole(uint64_t base_gpa, bool precise) +static void guest_test_punch_hole(u64 base_gpa, bool precise) { - const uint8_t init_p = 0xcc; + const u8 init_p = 0xcc; int i; /* @@ -239,8 +239,8 @@ static void guest_test_punch_hole(uint64_t base_gpa, bool precise) guest_map_private(base_gpa, PER_CPU_DATA_SIZE, false); for (i = 0; i < ARRAY_SIZE(test_ranges); i++) { - uint64_t gpa = base_gpa + test_ranges[i].offset; - uint64_t size = test_ranges[i].size; + gpa_t gpa = base_gpa + test_ranges[i].offset; + u64 size = test_ranges[i].size; /* * Free all memory before each iteration, even for the !precise @@ -268,7 +268,7 @@ static void guest_test_punch_hole(uint64_t base_gpa, bool precise) } } -static void guest_code(uint64_t base_gpa) +static void guest_code(u64 base_gpa) { /* * Run the conversion test twice, with and without doing fallocate() on @@ -289,8 +289,8 @@ static void guest_code(uint64_t base_gpa) static void handle_exit_hypercall(struct kvm_vcpu *vcpu) { struct kvm_run *run = vcpu->run; - uint64_t gpa = run->hypercall.args[0]; - uint64_t size = run->hypercall.args[1] * PAGE_SIZE; + gpa_t gpa = run->hypercall.args[0]; + u64 size = run->hypercall.args[1] * PAGE_SIZE; bool set_attributes = run->hypercall.args[2] & MAP_GPA_SET_ATTRIBUTES; bool map_shared = run->hypercall.args[2] & MAP_GPA_SHARED; bool do_fallocate = run->hypercall.args[2] & MAP_GPA_DO_FALLOCATE; @@ -337,7 +337,7 @@ static void *__test_mem_conversions(void *__vcpu) case UCALL_ABORT: REPORT_GUEST_ASSERT(uc); case UCALL_SYNC: { - uint64_t gpa = uc.args[1]; + gpa_t gpa = uc.args[1]; size_t size = uc.args[2]; size_t i; @@ -347,7 +347,7 @@ static void *__test_mem_conversions(void *__vcpu) for (i = 0; i < size; i += vm->page_size) { size_t nr_bytes = min_t(size_t, vm->page_size, size - i); - uint8_t *hva = addr_gpa2hva(vm, gpa + i); + u8 *hva = addr_gpa2hva(vm, gpa + i); /* In all cases, the host should observe the shared data. */ memcmp_h(hva, gpa + i, uc.args[3], nr_bytes); @@ -366,8 +366,8 @@ static void *__test_mem_conversions(void *__vcpu) } } -static void test_mem_conversions(enum vm_mem_backing_src_type src_type, uint32_t nr_vcpus, - uint32_t nr_memslots) +static void test_mem_conversions(enum vm_mem_backing_src_type src_type, u32 nr_vcpus, + u32 nr_memslots) { /* * Allocate enough memory so that each vCPU's chunk of memory can be @@ -402,7 +402,7 @@ static void test_mem_conversions(enum vm_mem_backing_src_type src_type, uint32_t KVM_MEM_GUEST_MEMFD, memfd, slot_size * i); for (i = 0; i < nr_vcpus; i++) { - uint64_t gpa = BASE_DATA_GPA + i * per_cpu_size; + gpa_t gpa = BASE_DATA_GPA + i * per_cpu_size; vcpu_args_set(vcpus[i], 1, gpa); @@ -450,8 +450,8 @@ static void usage(const char *cmd) int main(int argc, char *argv[]) { enum vm_mem_backing_src_type src_type = DEFAULT_VM_MEM_SRC; - uint32_t nr_memslots = 1; - uint32_t nr_vcpus = 1; + u32 nr_memslots = 1; + u32 nr_vcpus = 1; int opt; TEST_REQUIRE(kvm_check_cap(KVM_CAP_VM_TYPES) & BIT(KVM_X86_SW_PROTECTED_VM)); diff --git a/tools/testing/selftests/kvm/x86/private_mem_kvm_exits_test.c b/tools/testing/selftests/kvm/x86/private_mem_kvm_exits_test.c index 13e72fcec8dd..10db9fe6d906 100644 --- a/tools/testing/selftests/kvm/x86/private_mem_kvm_exits_test.c +++ b/tools/testing/selftests/kvm/x86/private_mem_kvm_exits_test.c @@ -17,17 +17,17 @@ #define EXITS_TEST_SIZE (EXITS_TEST_NPAGES * PAGE_SIZE) #define EXITS_TEST_SLOT 10 -static uint64_t guest_repeatedly_read(void) +static u64 guest_repeatedly_read(void) { - volatile uint64_t value; + volatile u64 value; while (true) - value = *((uint64_t *) EXITS_TEST_GVA); + value = *((u64 *)EXITS_TEST_GVA); return value; } -static uint32_t run_vcpu_get_exit_reason(struct kvm_vcpu *vcpu) +static u32 run_vcpu_get_exit_reason(struct kvm_vcpu *vcpu) { int r; @@ -50,7 +50,7 @@ static void test_private_access_memslot_deleted(void) struct kvm_vcpu *vcpu; pthread_t vm_thread; void *thread_return; - uint32_t exit_reason; + u32 exit_reason; vm = vm_create_shape_with_one_vcpu(protected_vm_shape, &vcpu, guest_repeatedly_read); @@ -72,7 +72,7 @@ static void test_private_access_memslot_deleted(void) vm_mem_region_delete(vm, EXITS_TEST_SLOT); pthread_join(vm_thread, &thread_return); - exit_reason = (uint32_t)(uint64_t)thread_return; + exit_reason = (u32)(u64)thread_return; TEST_ASSERT_EQ(exit_reason, KVM_EXIT_MEMORY_FAULT); TEST_ASSERT_EQ(vcpu->run->memory_fault.flags, KVM_MEMORY_EXIT_FLAG_PRIVATE); @@ -86,7 +86,7 @@ static void test_private_access_memslot_not_private(void) { struct kvm_vm *vm; struct kvm_vcpu *vcpu; - uint32_t exit_reason; + u32 exit_reason; vm = vm_create_shape_with_one_vcpu(protected_vm_shape, &vcpu, guest_repeatedly_read); diff --git a/tools/testing/selftests/kvm/x86/set_boot_cpu_id.c b/tools/testing/selftests/kvm/x86/set_boot_cpu_id.c index 49913784bc82..8e3898646c69 100644 --- a/tools/testing/selftests/kvm/x86/set_boot_cpu_id.c +++ b/tools/testing/selftests/kvm/x86/set_boot_cpu_id.c @@ -86,11 +86,11 @@ static void run_vcpu(struct kvm_vcpu *vcpu) } } -static struct kvm_vm *create_vm(uint32_t nr_vcpus, uint32_t bsp_vcpu_id, +static struct kvm_vm *create_vm(u32 nr_vcpus, u32 bsp_vcpu_id, struct kvm_vcpu *vcpus[]) { struct kvm_vm *vm; - uint32_t i; + u32 i; vm = vm_create(nr_vcpus); @@ -104,7 +104,7 @@ static struct kvm_vm *create_vm(uint32_t nr_vcpus, uint32_t bsp_vcpu_id, return vm; } -static void run_vm_bsp(uint32_t bsp_vcpu_id) +static void run_vm_bsp(u32 bsp_vcpu_id) { struct kvm_vcpu *vcpus[2]; struct kvm_vm *vm; diff --git a/tools/testing/selftests/kvm/x86/set_sregs_test.c b/tools/testing/selftests/kvm/x86/set_sregs_test.c index f4095a3d1278..8e654cc9ab16 100644 --- a/tools/testing/selftests/kvm/x86/set_sregs_test.c +++ b/tools/testing/selftests/kvm/x86/set_sregs_test.c @@ -46,9 +46,9 @@ do { \ X86_CR4_MCE | X86_CR4_PGE | X86_CR4_PCE | \ X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT) -static uint64_t calc_supported_cr4_feature_bits(void) +static u64 calc_supported_cr4_feature_bits(void) { - uint64_t cr4 = KVM_ALWAYS_ALLOWED_CR4; + u64 cr4 = KVM_ALWAYS_ALLOWED_CR4; if (kvm_cpu_has(X86_FEATURE_UMIP)) cr4 |= X86_CR4_UMIP; @@ -74,7 +74,7 @@ static uint64_t calc_supported_cr4_feature_bits(void) return cr4; } -static void test_cr_bits(struct kvm_vcpu *vcpu, uint64_t cr4) +static void test_cr_bits(struct kvm_vcpu *vcpu, u64 cr4) { struct kvm_sregs sregs; int rc, i; diff --git a/tools/testing/selftests/kvm/x86/sev_init2_tests.c b/tools/testing/selftests/kvm/x86/sev_init2_tests.c index b238615196ad..8eeba2327c7c 100644 --- a/tools/testing/selftests/kvm/x86/sev_init2_tests.c +++ b/tools/testing/selftests/kvm/x86/sev_init2_tests.c @@ -34,7 +34,7 @@ static int __sev_ioctl(int vm_fd, int cmd_id, void *data) { struct kvm_sev_cmd cmd = { .id = cmd_id, - .data = (uint64_t)data, + .data = (u64)data, .sev_fd = open_sev_dev_path_or_exit(), }; int ret; @@ -94,7 +94,7 @@ void test_vm_types(void) "VM type is KVM_X86_SW_PROTECTED_VM"); } -void test_flags(uint32_t vm_type) +void test_flags(u32 vm_type) { int i; @@ -104,7 +104,7 @@ void test_flags(uint32_t vm_type) "invalid flag"); } -void test_features(uint32_t vm_type, uint64_t supported_features) +void test_features(u32 vm_type, u64 supported_features) { int i; diff --git a/tools/testing/selftests/kvm/x86/sev_smoke_test.c b/tools/testing/selftests/kvm/x86/sev_smoke_test.c index 8bd37a476f15..1a49ee391586 100644 --- a/tools/testing/selftests/kvm/x86/sev_smoke_test.c +++ b/tools/testing/selftests/kvm/x86/sev_smoke_test.c @@ -13,9 +13,9 @@ #include "linux/psp-sev.h" #include "sev.h" -static void guest_sev_test_msr(uint32_t msr) +static void guest_sev_test_msr(u32 msr) { - uint64_t val = rdmsr(msr); + u64 val = rdmsr(msr); wrmsr(msr, val); GUEST_ASSERT(val == rdmsr(msr)); @@ -23,7 +23,7 @@ static void guest_sev_test_msr(uint32_t msr) #define guest_sev_test_reg(reg) \ do { \ - uint64_t val = get_##reg(); \ + u64 val = get_##reg(); \ \ set_##reg(val); \ GUEST_ASSERT(val == get_##reg()); \ @@ -42,7 +42,7 @@ static void guest_sev_test_regs(void) static void guest_snp_code(void) { - uint64_t sev_msr = rdmsr(MSR_AMD64_SEV); + u64 sev_msr = rdmsr(MSR_AMD64_SEV); GUEST_ASSERT(sev_msr & MSR_AMD64_SEV_ENABLED); GUEST_ASSERT(sev_msr & MSR_AMD64_SEV_ES_ENABLED); @@ -104,19 +104,19 @@ static void compare_xsave(u8 *from_host, u8 *from_guest) abort(); } -static void test_sync_vmsa(uint32_t type, uint64_t policy) +static void test_sync_vmsa(u32 type, u64 policy) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; - vm_vaddr_t gva; + gva_t gva; void *hva; double x87val = M_PI; struct kvm_xsave __attribute__((aligned(64))) xsave = { 0 }; vm = vm_sev_create_with_one_vcpu(type, guest_code_xsave, &vcpu); - gva = vm_vaddr_alloc_shared(vm, PAGE_SIZE, KVM_UTIL_MIN_VADDR, - MEM_REGION_TEST_DATA); + gva = vm_alloc_shared(vm, PAGE_SIZE, KVM_UTIL_MIN_VADDR, + MEM_REGION_TEST_DATA); hva = addr_gva2hva(vm, gva); vcpu_args_set(vcpu, 1, gva); @@ -150,7 +150,7 @@ static void test_sync_vmsa(uint32_t type, uint64_t policy) kvm_vm_free(vm); } -static void test_sev(void *guest_code, uint32_t type, uint64_t policy) +static void test_sev(void *guest_code, u32 type, u64 policy) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; @@ -201,7 +201,7 @@ static void guest_shutdown_code(void) __asm__ __volatile__("ud2"); } -static void test_sev_shutdown(uint32_t type, uint64_t policy) +static void test_sev_shutdown(u32 type, u64 policy) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; @@ -218,7 +218,7 @@ static void test_sev_shutdown(uint32_t type, uint64_t policy) kvm_vm_free(vm); } -static void test_sev_smoke(void *guest, uint32_t type, uint64_t policy) +static void test_sev_smoke(void *guest, u32 type, u64 policy) { const u64 xf_mask = XFEATURE_MASK_X87_AVX; diff --git a/tools/testing/selftests/kvm/x86/smaller_maxphyaddr_emulation_test.c b/tools/testing/selftests/kvm/x86/smaller_maxphyaddr_emulation_test.c index 0e8aec568010..3dca85e95478 100644 --- a/tools/testing/selftests/kvm/x86/smaller_maxphyaddr_emulation_test.c +++ b/tools/testing/selftests/kvm/x86/smaller_maxphyaddr_emulation_test.c @@ -20,8 +20,8 @@ static void guest_code(bool tdp_enabled) { - uint64_t error_code; - uint64_t vector; + u64 error_code; + u64 vector; vector = kvm_asm_safe_ec(FLDS_MEM_EAX, error_code, "a"(MEM_REGION_GVA)); @@ -47,8 +47,8 @@ int main(int argc, char *argv[]) struct kvm_vcpu *vcpu; struct kvm_vm *vm; struct ucall uc; - uint64_t *hva; - uint64_t gpa; + u64 *hva; + gpa_t gpa; int rc; TEST_REQUIRE(kvm_has_cap(KVM_CAP_SMALLER_MAXPHYADDR)); diff --git a/tools/testing/selftests/kvm/x86/smm_test.c b/tools/testing/selftests/kvm/x86/smm_test.c index ade8412bf94a..740051167dbd 100644 --- a/tools/testing/selftests/kvm/x86/smm_test.c +++ b/tools/testing/selftests/kvm/x86/smm_test.c @@ -34,13 +34,13 @@ * independent subset of asm here. * SMI handler always report back fixed stage SMRAM_STAGE. */ -uint8_t smi_handler[] = { +u8 smi_handler[] = { 0xb0, SMRAM_STAGE, /* mov $SMRAM_STAGE, %al */ 0xe4, SYNC_PORT, /* in $SYNC_PORT, %al */ 0x0f, 0xaa, /* rsm */ }; -static inline void sync_with_host(uint64_t phase) +static inline void sync_with_host(u64 phase) { asm volatile("in $" XSTR(SYNC_PORT)", %%al \n" : "+a" (phase)); @@ -65,7 +65,7 @@ static void guest_code(void *arg) { #define L2_GUEST_STACK_SIZE 64 unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE]; - uint64_t apicbase = rdmsr(MSR_IA32_APICBASE); + u64 apicbase = rdmsr(MSR_IA32_APICBASE); struct svm_test_data *svm = arg; struct vmx_pages *vmx_pages = arg; @@ -113,7 +113,7 @@ static void guest_code(void *arg) int main(int argc, char *argv[]) { - vm_vaddr_t nested_gva = 0; + gva_t nested_gva = 0; struct kvm_vcpu *vcpu; struct kvm_regs regs; diff --git a/tools/testing/selftests/kvm/x86/state_test.c b/tools/testing/selftests/kvm/x86/state_test.c index 992a52504a4a..409c6cc9f921 100644 --- a/tools/testing/selftests/kvm/x86/state_test.c +++ b/tools/testing/selftests/kvm/x86/state_test.c @@ -144,8 +144,8 @@ static void __attribute__((__flatten__)) guest_code(void *arg) GUEST_SYNC(1); if (this_cpu_has(X86_FEATURE_XSAVE)) { - uint64_t supported_xcr0 = this_cpu_supported_xcr0(); - uint8_t buffer[PAGE_SIZE]; + u64 supported_xcr0 = this_cpu_supported_xcr0(); + u8 buffer[PAGE_SIZE]; memset(buffer, 0xcc, sizeof(buffer)); @@ -172,8 +172,8 @@ static void __attribute__((__flatten__)) guest_code(void *arg) } if (this_cpu_has(X86_FEATURE_MPX)) { - uint64_t bounds[2] = { 10, 0xffffffffull }; - uint64_t output[2] = { }; + u64 bounds[2] = { 10, 0xffffffffull }; + u64 output[2] = { }; GUEST_ASSERT(supported_xcr0 & XFEATURE_MASK_BNDREGS); GUEST_ASSERT(supported_xcr0 & XFEATURE_MASK_BNDCSR); @@ -257,8 +257,8 @@ void check_nested_state(int stage, struct kvm_x86_state *state) int main(int argc, char *argv[]) { - uint64_t *xstate_bv, saved_xstate_bv; - vm_vaddr_t nested_gva = 0; + u64 *xstate_bv, saved_xstate_bv; + gva_t nested_gva = 0; struct kvm_cpuid2 empty_cpuid = {}; struct kvm_regs regs1, regs2; struct kvm_vcpu *vcpu, *vcpuN; @@ -331,7 +331,7 @@ int main(int argc, char *argv[]) * supported features, even if something goes awry in saving * the original snapshot. */ - xstate_bv = (void *)&((uint8_t *)state->xsave->region)[512]; + xstate_bv = (void *)&((u8 *)state->xsave->region)[512]; saved_xstate_bv = *xstate_bv; vcpuN = __vm_vcpu_add(vm, vcpu->id + 1); diff --git a/tools/testing/selftests/kvm/x86/svm_int_ctl_test.c b/tools/testing/selftests/kvm/x86/svm_int_ctl_test.c index 917b6066cfc1..d3cc5e4f7883 100644 --- a/tools/testing/selftests/kvm/x86/svm_int_ctl_test.c +++ b/tools/testing/selftests/kvm/x86/svm_int_ctl_test.c @@ -82,7 +82,7 @@ static void l1_guest_code(struct svm_test_data *svm) int main(int argc, char *argv[]) { struct kvm_vcpu *vcpu; - vm_vaddr_t svm_gva; + gva_t svm_gva; struct kvm_vm *vm; struct ucall uc; diff --git a/tools/testing/selftests/kvm/x86/svm_lbr_nested_state.c b/tools/testing/selftests/kvm/x86/svm_lbr_nested_state.c index ff99438824d3..7fbfaa054c95 100644 --- a/tools/testing/selftests/kvm/x86/svm_lbr_nested_state.c +++ b/tools/testing/selftests/kvm/x86/svm_lbr_nested_state.c @@ -97,9 +97,9 @@ void test_lbrv_nested_state(bool nested_lbrv) { struct kvm_x86_state *state = NULL; struct kvm_vcpu *vcpu; - vm_vaddr_t svm_gva; struct kvm_vm *vm; struct ucall uc; + gva_t svm_gva; pr_info("Testing with nested LBRV %s\n", nested_lbrv ? "enabled" : "disabled"); diff --git a/tools/testing/selftests/kvm/x86/svm_nested_clear_efer_svme.c b/tools/testing/selftests/kvm/x86/svm_nested_clear_efer_svme.c index a521a9eed061..6a89eaffc657 100644 --- a/tools/testing/selftests/kvm/x86/svm_nested_clear_efer_svme.c +++ b/tools/testing/selftests/kvm/x86/svm_nested_clear_efer_svme.c @@ -38,7 +38,7 @@ int main(int argc, char *argv[]) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; - vm_vaddr_t nested_gva = 0; + gva_t nested_gva = 0; TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_SVM)); diff --git a/tools/testing/selftests/kvm/x86/svm_nested_shutdown_test.c b/tools/testing/selftests/kvm/x86/svm_nested_shutdown_test.c index 00135cbba35e..c6ea3d609a62 100644 --- a/tools/testing/selftests/kvm/x86/svm_nested_shutdown_test.c +++ b/tools/testing/selftests/kvm/x86/svm_nested_shutdown_test.c @@ -42,7 +42,7 @@ static void l1_guest_code(struct svm_test_data *svm, struct idt_entry *idt) int main(int argc, char *argv[]) { struct kvm_vcpu *vcpu; - vm_vaddr_t svm_gva; + gva_t svm_gva; struct kvm_vm *vm; TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_SVM)); diff --git a/tools/testing/selftests/kvm/x86/svm_nested_soft_inject_test.c b/tools/testing/selftests/kvm/x86/svm_nested_soft_inject_test.c index 4bd1655f9e6d..f72f11d4c4f8 100644 --- a/tools/testing/selftests/kvm/x86/svm_nested_soft_inject_test.c +++ b/tools/testing/selftests/kvm/x86/svm_nested_soft_inject_test.c @@ -76,7 +76,7 @@ static void l2_guest_code_nmi(void) ud2(); } -static void l1_guest_code(struct svm_test_data *svm, uint64_t is_nmi, uint64_t idt_alt) +static void l1_guest_code(struct svm_test_data *svm, u64 is_nmi, u64 idt_alt) { #define L2_GUEST_STACK_SIZE 64 unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE]; @@ -144,8 +144,8 @@ static void run_test(bool is_nmi) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; - vm_vaddr_t svm_gva; - vm_vaddr_t idt_alt_vm; + gva_t svm_gva; + gva_t idt_alt_vm; struct kvm_guest_debug debug; pr_info("Running %s test\n", is_nmi ? "NMI" : "soft int"); @@ -161,14 +161,14 @@ static void run_test(bool is_nmi) if (!is_nmi) { void *idt, *idt_alt; - idt_alt_vm = vm_vaddr_alloc_page(vm); + idt_alt_vm = vm_alloc_page(vm); idt_alt = addr_gva2hva(vm, idt_alt_vm); idt = addr_gva2hva(vm, vm->arch.idt); memcpy(idt_alt, idt, getpagesize()); } else { idt_alt_vm = 0; } - vcpu_args_set(vcpu, 3, svm_gva, (uint64_t)is_nmi, (uint64_t)idt_alt_vm); + vcpu_args_set(vcpu, 3, svm_gva, (u64)is_nmi, (u64)idt_alt_vm); memset(&debug, 0, sizeof(debug)); vcpu_guest_debug_set(vcpu, &debug); diff --git a/tools/testing/selftests/kvm/x86/svm_nested_vmcb12_gpa.c b/tools/testing/selftests/kvm/x86/svm_nested_vmcb12_gpa.c index 569869bed20b..a4935ce2fb99 100644 --- a/tools/testing/selftests/kvm/x86/svm_nested_vmcb12_gpa.c +++ b/tools/testing/selftests/kvm/x86/svm_nested_vmcb12_gpa.c @@ -28,28 +28,28 @@ static void l2_code(void) vmcall(); } -static void l1_vmrun(struct svm_test_data *svm, u64 gpa) +static void l1_vmrun(struct svm_test_data *svm, gpa_t gpa) { generic_svm_setup(svm, l2_code, &l2_guest_stack[L2_GUEST_STACK_SIZE]); asm volatile ("vmrun %[gpa]" : : [gpa] "a" (gpa) : "memory"); } -static void l1_vmload(struct svm_test_data *svm, u64 gpa) +static void l1_vmload(struct svm_test_data *svm, gpa_t gpa) { generic_svm_setup(svm, l2_code, &l2_guest_stack[L2_GUEST_STACK_SIZE]); asm volatile ("vmload %[gpa]" : : [gpa] "a" (gpa) : "memory"); } -static void l1_vmsave(struct svm_test_data *svm, u64 gpa) +static void l1_vmsave(struct svm_test_data *svm, gpa_t gpa) { generic_svm_setup(svm, l2_code, &l2_guest_stack[L2_GUEST_STACK_SIZE]); asm volatile ("vmsave %[gpa]" : : [gpa] "a" (gpa) : "memory"); } -static void l1_vmexit(struct svm_test_data *svm, u64 gpa) +static void l1_vmexit(struct svm_test_data *svm, gpa_t gpa) { generic_svm_setup(svm, l2_code, &l2_guest_stack[L2_GUEST_STACK_SIZE]); @@ -74,7 +74,7 @@ static u64 unmappable_gpa(struct kvm_vcpu *vcpu) static void test_invalid_vmcb12(struct kvm_vcpu *vcpu) { - vm_vaddr_t nested_gva = 0; + gva_t nested_gva = 0; struct ucall uc; @@ -90,7 +90,7 @@ static void test_invalid_vmcb12(struct kvm_vcpu *vcpu) static void test_unmappable_vmcb12(struct kvm_vcpu *vcpu) { - vm_vaddr_t nested_gva = 0; + gva_t nested_gva = 0; vcpu_alloc_svm(vcpu->vm, &nested_gva); vcpu_args_set(vcpu, 2, nested_gva, unmappable_gpa(vcpu)); @@ -103,7 +103,7 @@ static void test_unmappable_vmcb12(struct kvm_vcpu *vcpu) static void test_unmappable_vmcb12_vmexit(struct kvm_vcpu *vcpu) { struct kvm_x86_state *state; - vm_vaddr_t nested_gva = 0; + gva_t nested_gva = 0; struct ucall uc; /* diff --git a/tools/testing/selftests/kvm/x86/svm_vmcall_test.c b/tools/testing/selftests/kvm/x86/svm_vmcall_test.c index 8a62cca28cfb..b1887242f3b8 100644 --- a/tools/testing/selftests/kvm/x86/svm_vmcall_test.c +++ b/tools/testing/selftests/kvm/x86/svm_vmcall_test.c @@ -36,7 +36,7 @@ static void l1_guest_code(struct svm_test_data *svm) int main(int argc, char *argv[]) { struct kvm_vcpu *vcpu; - vm_vaddr_t svm_gva; + gva_t svm_gva; struct kvm_vm *vm; TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_SVM)); diff --git a/tools/testing/selftests/kvm/x86/sync_regs_test.c b/tools/testing/selftests/kvm/x86/sync_regs_test.c index 8fa3948b0170..e0c52321f87c 100644 --- a/tools/testing/selftests/kvm/x86/sync_regs_test.c +++ b/tools/testing/selftests/kvm/x86/sync_regs_test.c @@ -20,7 +20,7 @@ #include "kvm_util.h" #include "processor.h" -#define UCALL_PIO_PORT ((uint16_t)0x1000) +#define UCALL_PIO_PORT ((u16)0x1000) struct ucall uc_none = { .cmd = UCALL_NONE, diff --git a/tools/testing/selftests/kvm/x86/triple_fault_event_test.c b/tools/testing/selftests/kvm/x86/triple_fault_event_test.c index 56306a19144a..f1c488e0d497 100644 --- a/tools/testing/selftests/kvm/x86/triple_fault_event_test.c +++ b/tools/testing/selftests/kvm/x86/triple_fault_event_test.c @@ -72,13 +72,13 @@ int main(void) if (has_vmx) { - vm_vaddr_t vmx_pages_gva; + gva_t vmx_pages_gva; vm = vm_create_with_one_vcpu(&vcpu, l1_guest_code_vmx); vcpu_alloc_vmx(vm, &vmx_pages_gva); vcpu_args_set(vcpu, 1, vmx_pages_gva); } else { - vm_vaddr_t svm_gva; + gva_t svm_gva; vm = vm_create_with_one_vcpu(&vcpu, l1_guest_code_svm); vcpu_alloc_svm(vm, &svm_gva); diff --git a/tools/testing/selftests/kvm/x86/tsc_msrs_test.c b/tools/testing/selftests/kvm/x86/tsc_msrs_test.c index 12b0964f4f13..91583969a14f 100644 --- a/tools/testing/selftests/kvm/x86/tsc_msrs_test.c +++ b/tools/testing/selftests/kvm/x86/tsc_msrs_test.c @@ -95,7 +95,7 @@ int main(void) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; - uint64_t val; + u64 val; ksft_print_header(); ksft_set_plan(5); diff --git a/tools/testing/selftests/kvm/x86/tsc_scaling_sync.c b/tools/testing/selftests/kvm/x86/tsc_scaling_sync.c index 59c7304f805e..59da8d4da607 100644 --- a/tools/testing/selftests/kvm/x86/tsc_scaling_sync.c +++ b/tools/testing/selftests/kvm/x86/tsc_scaling_sync.c @@ -21,10 +21,10 @@ pthread_spinlock_t create_lock; #define TEST_TSC_KHZ 2345678UL #define TEST_TSC_OFFSET 200000000 -uint64_t tsc_sync; +u64 tsc_sync; static void guest_code(void) { - uint64_t start_tsc, local_tsc, tmp; + u64 start_tsc, local_tsc, tmp; start_tsc = rdtsc(); do { diff --git a/tools/testing/selftests/kvm/x86/ucna_injection_test.c b/tools/testing/selftests/kvm/x86/ucna_injection_test.c index 1e5e564523b3..df1ec8209c76 100644 --- a/tools/testing/selftests/kvm/x86/ucna_injection_test.c +++ b/tools/testing/selftests/kvm/x86/ucna_injection_test.c @@ -45,7 +45,7 @@ #define MCI_CTL2_RESERVED_BIT BIT_ULL(29) -static uint64_t supported_mcg_caps; +static u64 supported_mcg_caps; /* * Record states about the injected UCNA. @@ -53,30 +53,30 @@ static uint64_t supported_mcg_caps; * handler. Variables without the 'i_' prefixes are recorded in guest main * execution thread. */ -static volatile uint64_t i_ucna_rcvd; -static volatile uint64_t i_ucna_addr; -static volatile uint64_t ucna_addr; -static volatile uint64_t ucna_addr2; +static volatile u64 i_ucna_rcvd; +static volatile u64 i_ucna_addr; +static volatile u64 ucna_addr; +static volatile u64 ucna_addr2; struct thread_params { struct kvm_vcpu *vcpu; - uint64_t *p_i_ucna_rcvd; - uint64_t *p_i_ucna_addr; - uint64_t *p_ucna_addr; - uint64_t *p_ucna_addr2; + u64 *p_i_ucna_rcvd; + u64 *p_i_ucna_addr; + u64 *p_ucna_addr; + u64 *p_ucna_addr2; }; static void verify_apic_base_addr(void) { - uint64_t msr = rdmsr(MSR_IA32_APICBASE); - uint64_t base = GET_APIC_BASE(msr); + u64 msr = rdmsr(MSR_IA32_APICBASE); + u64 base = GET_APIC_BASE(msr); GUEST_ASSERT(base == APIC_DEFAULT_GPA); } static void ucna_injection_guest_code(void) { - uint64_t ctl2; + u64 ctl2; verify_apic_base_addr(); xapic_enable(); @@ -106,7 +106,7 @@ static void ucna_injection_guest_code(void) static void cmci_disabled_guest_code(void) { - uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); + u64 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN); GUEST_DONE(); @@ -114,7 +114,7 @@ static void cmci_disabled_guest_code(void) static void cmci_enabled_guest_code(void) { - uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); + u64 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_RESERVED_BIT); GUEST_DONE(); @@ -145,14 +145,15 @@ static void run_vcpu_expect_gp(struct kvm_vcpu *vcpu) printf("vCPU received GP in guest.\n"); } -static void inject_ucna(struct kvm_vcpu *vcpu, uint64_t addr) { +static void inject_ucna(struct kvm_vcpu *vcpu, u64 addr) +{ /* * A UCNA error is indicated with VAL=1, UC=1, PCC=0, S=0 and AR=0 in * the IA32_MCi_STATUS register. * MSCOD=1 (BIT[16] - MscodDataRdErr). * MCACOD=0x0090 (Memory controller error format, channel 0) */ - uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | + u64 status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | 0x10090; struct kvm_x86_mce mce = {}; mce.status = status; @@ -216,10 +217,10 @@ static void test_ucna_injection(struct kvm_vcpu *vcpu, struct thread_params *par { struct kvm_vm *vm = vcpu->vm; params->vcpu = vcpu; - params->p_i_ucna_rcvd = (uint64_t *)addr_gva2hva(vm, (uint64_t)&i_ucna_rcvd); - params->p_i_ucna_addr = (uint64_t *)addr_gva2hva(vm, (uint64_t)&i_ucna_addr); - params->p_ucna_addr = (uint64_t *)addr_gva2hva(vm, (uint64_t)&ucna_addr); - params->p_ucna_addr2 = (uint64_t *)addr_gva2hva(vm, (uint64_t)&ucna_addr2); + params->p_i_ucna_rcvd = (u64 *)addr_gva2hva(vm, (u64)&i_ucna_rcvd); + params->p_i_ucna_addr = (u64 *)addr_gva2hva(vm, (u64)&i_ucna_addr); + params->p_ucna_addr = (u64 *)addr_gva2hva(vm, (u64)&ucna_addr); + params->p_ucna_addr2 = (u64 *)addr_gva2hva(vm, (u64)&ucna_addr2); run_ucna_injection(params); @@ -242,7 +243,7 @@ static void test_ucna_injection(struct kvm_vcpu *vcpu, struct thread_params *par static void setup_mce_cap(struct kvm_vcpu *vcpu, bool enable_cmci_p) { - uint64_t mcg_caps = MCG_CTL_P | MCG_SER_P | MCG_LMCE_P | KVM_MAX_MCE_BANKS; + u64 mcg_caps = MCG_CTL_P | MCG_SER_P | MCG_LMCE_P | KVM_MAX_MCE_BANKS; if (enable_cmci_p) mcg_caps |= MCG_CMCI_P; @@ -250,7 +251,7 @@ static void setup_mce_cap(struct kvm_vcpu *vcpu, bool enable_cmci_p) vcpu_ioctl(vcpu, KVM_X86_SETUP_MCE, &mcg_caps); } -static struct kvm_vcpu *create_vcpu_with_mce_cap(struct kvm_vm *vm, uint32_t vcpuid, +static struct kvm_vcpu *create_vcpu_with_mce_cap(struct kvm_vm *vm, u32 vcpuid, bool enable_cmci_p, void *guest_code) { struct kvm_vcpu *vcpu = vm_vcpu_add(vm, vcpuid, guest_code); diff --git a/tools/testing/selftests/kvm/x86/userspace_io_test.c b/tools/testing/selftests/kvm/x86/userspace_io_test.c index be7d72f3c029..9c5a87576c2e 100644 --- a/tools/testing/selftests/kvm/x86/userspace_io_test.c +++ b/tools/testing/selftests/kvm/x86/userspace_io_test.c @@ -10,7 +10,7 @@ #include "kvm_util.h" #include "processor.h" -static void guest_ins_port80(uint8_t *buffer, unsigned int count) +static void guest_ins_port80(u8 *buffer, unsigned int count) { unsigned long end; @@ -26,7 +26,7 @@ static void guest_ins_port80(uint8_t *buffer, unsigned int count) static void guest_code(void) { - uint8_t buffer[8192]; + u8 buffer[8192]; int i; /* diff --git a/tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c b/tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c index 8463a9956410..2808ce727e5f 100644 --- a/tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c +++ b/tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c @@ -23,21 +23,21 @@ struct kvm_msr_filter filter_allow = { .nmsrs = 1, /* Test an MSR the kernel knows about. */ .base = MSR_IA32_XSS, - .bitmap = (uint8_t*)&deny_bits, + .bitmap = (u8 *)&deny_bits, }, { .flags = KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE, .nmsrs = 1, /* Test an MSR the kernel doesn't know about. */ .base = MSR_IA32_FLUSH_CMD, - .bitmap = (uint8_t*)&deny_bits, + .bitmap = (u8 *)&deny_bits, }, { .flags = KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE, .nmsrs = 1, /* Test a fabricated MSR that no one knows about. */ .base = MSR_NON_EXISTENT, - .bitmap = (uint8_t*)&deny_bits, + .bitmap = (u8 *)&deny_bits, }, }, }; @@ -49,7 +49,7 @@ struct kvm_msr_filter filter_fs = { .flags = KVM_MSR_FILTER_READ, .nmsrs = 1, .base = MSR_FS_BASE, - .bitmap = (uint8_t*)&deny_bits, + .bitmap = (u8 *)&deny_bits, }, }, }; @@ -61,12 +61,12 @@ struct kvm_msr_filter filter_gs = { .flags = KVM_MSR_FILTER_READ, .nmsrs = 1, .base = MSR_GS_BASE, - .bitmap = (uint8_t*)&deny_bits, + .bitmap = (u8 *)&deny_bits, }, }, }; -static uint64_t msr_non_existent_data; +static u64 msr_non_existent_data; static int guest_exception_count; static u32 msr_reads, msr_writes; @@ -77,7 +77,7 @@ static u8 bitmap_c0000000[KVM_MSR_FILTER_MAX_BITMAP_SIZE]; static u8 bitmap_c0000000_read[KVM_MSR_FILTER_MAX_BITMAP_SIZE]; static u8 bitmap_deadbeef[1] = { 0x1 }; -static void deny_msr(uint8_t *bitmap, u32 msr) +static void deny_msr(u8 *bitmap, u32 msr) { u32 idx = msr & (KVM_MSR_FILTER_MAX_BITMAP_SIZE - 1); @@ -142,26 +142,26 @@ struct kvm_msr_filter no_filter_deny = { * Note: Force test_rdmsr() to not be inlined to prevent the labels, * rdmsr_start and rdmsr_end, from being defined multiple times. */ -static noinline uint64_t test_rdmsr(uint32_t msr) +static noinline u64 test_rdmsr(u32 msr) { - uint32_t a, d; + u32 a, d; guest_exception_count = 0; __asm__ __volatile__("rdmsr_start: rdmsr; rdmsr_end:" : "=a"(a), "=d"(d) : "c"(msr) : "memory"); - return a | ((uint64_t) d << 32); + return a | ((u64)d << 32); } /* * Note: Force test_wrmsr() to not be inlined to prevent the labels, * wrmsr_start and wrmsr_end, from being defined multiple times. */ -static noinline void test_wrmsr(uint32_t msr, uint64_t value) +static noinline void test_wrmsr(u32 msr, u64 value) { - uint32_t a = value; - uint32_t d = value >> 32; + u32 a = value; + u32 d = value >> 32; guest_exception_count = 0; @@ -176,26 +176,26 @@ extern char wrmsr_start, wrmsr_end; * Note: Force test_em_rdmsr() to not be inlined to prevent the labels, * rdmsr_start and rdmsr_end, from being defined multiple times. */ -static noinline uint64_t test_em_rdmsr(uint32_t msr) +static noinline u64 test_em_rdmsr(u32 msr) { - uint32_t a, d; + u32 a, d; guest_exception_count = 0; __asm__ __volatile__(KVM_FEP "em_rdmsr_start: rdmsr; em_rdmsr_end:" : "=a"(a), "=d"(d) : "c"(msr) : "memory"); - return a | ((uint64_t) d << 32); + return a | ((u64)d << 32); } /* * Note: Force test_em_wrmsr() to not be inlined to prevent the labels, * wrmsr_start and wrmsr_end, from being defined multiple times. */ -static noinline void test_em_wrmsr(uint32_t msr, uint64_t value) +static noinline void test_em_wrmsr(u32 msr, u64 value) { - uint32_t a = value; - uint32_t d = value >> 32; + u32 a = value; + u32 d = value >> 32; guest_exception_count = 0; @@ -208,7 +208,7 @@ extern char em_wrmsr_start, em_wrmsr_end; static void guest_code_filter_allow(void) { - uint64_t data; + u64 data; /* * Test userspace intercepting rdmsr / wrmsr for MSR_IA32_XSS. @@ -328,7 +328,7 @@ static void guest_code_filter_deny(void) static void guest_code_permission_bitmap(void) { - uint64_t data; + u64 data; data = test_rdmsr(MSR_FS_BASE); GUEST_ASSERT(data == MSR_FS_BASE); @@ -391,7 +391,7 @@ static void check_for_guest_assert(struct kvm_vcpu *vcpu) } } -static void process_rdmsr(struct kvm_vcpu *vcpu, uint32_t msr_index) +static void process_rdmsr(struct kvm_vcpu *vcpu, u32 msr_index) { struct kvm_run *run = vcpu->run; @@ -423,7 +423,7 @@ static void process_rdmsr(struct kvm_vcpu *vcpu, uint32_t msr_index) } } -static void process_wrmsr(struct kvm_vcpu *vcpu, uint32_t msr_index) +static void process_wrmsr(struct kvm_vcpu *vcpu, u32 msr_index) { struct kvm_run *run = vcpu->run; @@ -464,7 +464,7 @@ static void process_ucall_done(struct kvm_vcpu *vcpu) uc.cmd, UCALL_DONE); } -static uint64_t process_ucall(struct kvm_vcpu *vcpu) +static u64 process_ucall(struct kvm_vcpu *vcpu) { struct ucall uc = {}; @@ -489,20 +489,20 @@ static uint64_t process_ucall(struct kvm_vcpu *vcpu) } static void run_guest_then_process_rdmsr(struct kvm_vcpu *vcpu, - uint32_t msr_index) + u32 msr_index) { vcpu_run(vcpu); process_rdmsr(vcpu, msr_index); } static void run_guest_then_process_wrmsr(struct kvm_vcpu *vcpu, - uint32_t msr_index) + u32 msr_index) { vcpu_run(vcpu); process_wrmsr(vcpu, msr_index); } -static uint64_t run_guest_then_process_ucall(struct kvm_vcpu *vcpu) +static u64 run_guest_then_process_ucall(struct kvm_vcpu *vcpu) { vcpu_run(vcpu); return process_ucall(vcpu); @@ -519,7 +519,7 @@ KVM_ONE_VCPU_TEST_SUITE(user_msr); KVM_ONE_VCPU_TEST(user_msr, msr_filter_allow, guest_code_filter_allow) { struct kvm_vm *vm = vcpu->vm; - uint64_t cmd; + u64 cmd; int rc; rc = kvm_check_cap(KVM_CAP_X86_USER_SPACE_MSR); @@ -732,7 +732,7 @@ static void run_msr_filter_flag_test(struct kvm_vm *vm) .flags = KVM_MSR_FILTER_READ, .nmsrs = 1, .base = 0, - .bitmap = (uint8_t *)&deny_bits, + .bitmap = (u8 *)&deny_bits, }, }, }; diff --git a/tools/testing/selftests/kvm/x86/vmx_apic_access_test.c b/tools/testing/selftests/kvm/x86/vmx_apic_access_test.c index a81a24761aac..1720113eae79 100644 --- a/tools/testing/selftests/kvm/x86/vmx_apic_access_test.c +++ b/tools/testing/selftests/kvm/x86/vmx_apic_access_test.c @@ -38,7 +38,7 @@ static void l1_guest_code(struct vmx_pages *vmx_pages, unsigned long high_gpa) { #define L2_GUEST_STACK_SIZE 64 unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE]; - uint32_t control; + u32 control; GUEST_ASSERT(prepare_for_vmx_operation(vmx_pages)); GUEST_ASSERT(load_vmcs(vmx_pages)); @@ -72,7 +72,7 @@ static void l1_guest_code(struct vmx_pages *vmx_pages, unsigned long high_gpa) int main(int argc, char *argv[]) { unsigned long apic_access_addr = ~0ul; - vm_vaddr_t vmx_pages_gva; + gva_t vmx_pages_gva; unsigned long high_gpa; struct vmx_pages *vmx; bool done = false; diff --git a/tools/testing/selftests/kvm/x86/vmx_apicv_updates_test.c b/tools/testing/selftests/kvm/x86/vmx_apicv_updates_test.c index 337c53fddeff..80a4fd1e5bbb 100644 --- a/tools/testing/selftests/kvm/x86/vmx_apicv_updates_test.c +++ b/tools/testing/selftests/kvm/x86/vmx_apicv_updates_test.c @@ -33,7 +33,7 @@ static void l1_guest_code(struct vmx_pages *vmx_pages) { #define L2_GUEST_STACK_SIZE 64 unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE]; - uint32_t control; + u32 control; GUEST_ASSERT(prepare_for_vmx_operation(vmx_pages)); GUEST_ASSERT(load_vmcs(vmx_pages)); @@ -110,7 +110,7 @@ static void l1_guest_code(struct vmx_pages *vmx_pages) int main(int argc, char *argv[]) { - vm_vaddr_t vmx_pages_gva; + gva_t vmx_pages_gva; struct vmx_pages *vmx; struct kvm_vcpu *vcpu; struct kvm_vm *vm; diff --git a/tools/testing/selftests/kvm/x86/vmx_invalid_nested_guest_state.c b/tools/testing/selftests/kvm/x86/vmx_invalid_nested_guest_state.c index a100ee5f0009..a2eaceed9ad5 100644 --- a/tools/testing/selftests/kvm/x86/vmx_invalid_nested_guest_state.c +++ b/tools/testing/selftests/kvm/x86/vmx_invalid_nested_guest_state.c @@ -52,7 +52,7 @@ static void l1_guest_code(struct vmx_pages *vmx_pages) int main(int argc, char *argv[]) { - vm_vaddr_t vmx_pages_gva; + gva_t vmx_pages_gva; struct kvm_sregs sregs; struct kvm_vcpu *vcpu; struct kvm_run *run; diff --git a/tools/testing/selftests/kvm/x86/vmx_msrs_test.c b/tools/testing/selftests/kvm/x86/vmx_msrs_test.c index 90720b6205f4..c1e8632a1bb6 100644 --- a/tools/testing/selftests/kvm/x86/vmx_msrs_test.c +++ b/tools/testing/selftests/kvm/x86/vmx_msrs_test.c @@ -12,11 +12,10 @@ #include "kvm_util.h" #include "vmx.h" -static void vmx_fixed1_msr_test(struct kvm_vcpu *vcpu, uint32_t msr_index, - uint64_t mask) +static void vmx_fixed1_msr_test(struct kvm_vcpu *vcpu, u32 msr_index, u64 mask) { - uint64_t val = vcpu_get_msr(vcpu, msr_index); - uint64_t bit; + u64 val = vcpu_get_msr(vcpu, msr_index); + u64 bit; mask &= val; @@ -26,11 +25,10 @@ static void vmx_fixed1_msr_test(struct kvm_vcpu *vcpu, uint32_t msr_index, } } -static void vmx_fixed0_msr_test(struct kvm_vcpu *vcpu, uint32_t msr_index, - uint64_t mask) +static void vmx_fixed0_msr_test(struct kvm_vcpu *vcpu, u32 msr_index, u64 mask) { - uint64_t val = vcpu_get_msr(vcpu, msr_index); - uint64_t bit; + u64 val = vcpu_get_msr(vcpu, msr_index); + u64 bit; mask = ~mask | val; @@ -40,7 +38,7 @@ static void vmx_fixed0_msr_test(struct kvm_vcpu *vcpu, uint32_t msr_index, } } -static void vmx_fixed0and1_msr_test(struct kvm_vcpu *vcpu, uint32_t msr_index) +static void vmx_fixed0and1_msr_test(struct kvm_vcpu *vcpu, u32 msr_index) { vmx_fixed0_msr_test(vcpu, msr_index, GENMASK_ULL(31, 0)); vmx_fixed1_msr_test(vcpu, msr_index, GENMASK_ULL(63, 32)); @@ -68,10 +66,10 @@ static void vmx_save_restore_msrs_test(struct kvm_vcpu *vcpu) } static void __ia32_feature_control_msr_test(struct kvm_vcpu *vcpu, - uint64_t msr_bit, + u64 msr_bit, struct kvm_x86_cpu_feature feature) { - uint64_t val; + u64 val; vcpu_clear_cpuid_feature(vcpu, feature); @@ -90,7 +88,7 @@ static void __ia32_feature_control_msr_test(struct kvm_vcpu *vcpu, static void ia32_feature_control_msr_test(struct kvm_vcpu *vcpu) { - uint64_t supported_bits = FEAT_CTL_LOCKED | + u64 supported_bits = FEAT_CTL_LOCKED | FEAT_CTL_VMX_ENABLED_INSIDE_SMX | FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX | FEAT_CTL_SGX_LC_ENABLED | diff --git a/tools/testing/selftests/kvm/x86/vmx_nested_la57_state_test.c b/tools/testing/selftests/kvm/x86/vmx_nested_la57_state_test.c index 915c42001dba..f13dee317383 100644 --- a/tools/testing/selftests/kvm/x86/vmx_nested_la57_state_test.c +++ b/tools/testing/selftests/kvm/x86/vmx_nested_la57_state_test.c @@ -30,7 +30,7 @@ static void l1_guest_code(struct vmx_pages *vmx_pages) #define L2_GUEST_STACK_SIZE 64 unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE]; u64 guest_cr4; - vm_paddr_t pml5_pa, pml4_pa; + gpa_t pml5_pa, pml4_pa; u64 *pml5; u64 exit_reason; @@ -73,7 +73,7 @@ void guest_code(struct vmx_pages *vmx_pages) int main(int argc, char *argv[]) { - vm_vaddr_t vmx_pages_gva = 0; + gva_t vmx_pages_gva = 0; struct kvm_vm *vm; struct kvm_vcpu *vcpu; struct kvm_x86_state *state; diff --git a/tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c b/tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c index 7ff6f62e20a3..d004108dbdc6 100644 --- a/tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c +++ b/tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c @@ -52,16 +52,16 @@ static const union perf_capabilities format_caps = { .pebs_format = -1, }; -static void guest_test_perf_capabilities_gp(uint64_t val) +static void guest_test_perf_capabilities_gp(u64 val) { - uint8_t vector = wrmsr_safe(MSR_IA32_PERF_CAPABILITIES, val); + u8 vector = wrmsr_safe(MSR_IA32_PERF_CAPABILITIES, val); __GUEST_ASSERT(vector == GP_VECTOR, "Expected #GP for value '0x%lx', got %s", val, ex_str(vector)); } -static void guest_code(uint64_t current_val) +static void guest_code(u64 current_val) { int i; @@ -129,7 +129,7 @@ KVM_ONE_VCPU_TEST(vmx_pmu_caps, basic_perf_capabilities, guest_code) KVM_ONE_VCPU_TEST(vmx_pmu_caps, fungible_perf_capabilities, guest_code) { - const uint64_t fungible_caps = host_cap.capabilities & ~immutable_caps.capabilities; + const u64 fungible_caps = host_cap.capabilities & ~immutable_caps.capabilities; int bit; for_each_set_bit(bit, &fungible_caps, 64) { @@ -148,7 +148,7 @@ KVM_ONE_VCPU_TEST(vmx_pmu_caps, fungible_perf_capabilities, guest_code) */ KVM_ONE_VCPU_TEST(vmx_pmu_caps, immutable_perf_capabilities, guest_code) { - const uint64_t reserved_caps = (~host_cap.capabilities | + const u64 reserved_caps = (~host_cap.capabilities | immutable_caps.capabilities) & ~format_caps.capabilities; union perf_capabilities val = host_cap; @@ -210,7 +210,7 @@ KVM_ONE_VCPU_TEST(vmx_pmu_caps, lbr_perf_capabilities, guest_code) KVM_ONE_VCPU_TEST(vmx_pmu_caps, perf_capabilities_unsupported, guest_code) { - uint64_t val; + u64 val; int i, r; vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, host_cap.capabilities); diff --git a/tools/testing/selftests/kvm/x86/vmx_preemption_timer_test.c b/tools/testing/selftests/kvm/x86/vmx_preemption_timer_test.c index 00dd2ac07a61..1b7b6ba23de7 100644 --- a/tools/testing/selftests/kvm/x86/vmx_preemption_timer_test.c +++ b/tools/testing/selftests/kvm/x86/vmx_preemption_timer_test.c @@ -152,7 +152,7 @@ void guest_code(struct vmx_pages *vmx_pages) int main(int argc, char *argv[]) { - vm_vaddr_t vmx_pages_gva = 0; + gva_t vmx_pages_gva = 0; struct kvm_regs regs1, regs2; struct kvm_vm *vm; diff --git a/tools/testing/selftests/kvm/x86/xapic_ipi_test.c b/tools/testing/selftests/kvm/x86/xapic_ipi_test.c index ae4a4b6c05ca..39ce9a9369f5 100644 --- a/tools/testing/selftests/kvm/x86/xapic_ipi_test.c +++ b/tools/testing/selftests/kvm/x86/xapic_ipi_test.c @@ -48,20 +48,20 @@ * Incremented in the IPI handler. Provides evidence to the sender that the IPI * arrived at the destination */ -static volatile uint64_t ipis_rcvd; +static volatile u64 ipis_rcvd; /* Data struct shared between host main thread and vCPUs */ struct test_data_page { - uint32_t halter_apic_id; - volatile uint64_t hlt_count; - volatile uint64_t wake_count; - uint64_t ipis_sent; - uint64_t migrations_attempted; - uint64_t migrations_completed; - uint32_t icr; - uint32_t icr2; - uint32_t halter_tpr; - uint32_t halter_ppr; + u32 halter_apic_id; + volatile u64 hlt_count; + volatile u64 wake_count; + u64 ipis_sent; + u64 migrations_attempted; + u64 migrations_completed; + u32 icr; + u32 icr2; + u32 halter_tpr; + u32 halter_ppr; /* * Record local version register as a cross-check that APIC access @@ -69,19 +69,19 @@ struct test_data_page { * arch/x86/kvm/lapic.c). If test is failing, check that values match * to determine whether APIC access exits are working. */ - uint32_t halter_lvr; + u32 halter_lvr; }; struct thread_params { struct test_data_page *data; struct kvm_vcpu *vcpu; - uint64_t *pipis_rcvd; /* host address of ipis_rcvd global */ + u64 *pipis_rcvd; /* host address of ipis_rcvd global */ }; void verify_apic_base_addr(void) { - uint64_t msr = rdmsr(MSR_IA32_APICBASE); - uint64_t base = GET_APIC_BASE(msr); + u64 msr = rdmsr(MSR_IA32_APICBASE); + u64 base = GET_APIC_BASE(msr); GUEST_ASSERT(base == APIC_DEFAULT_GPA); } @@ -125,12 +125,12 @@ static void guest_ipi_handler(struct ex_regs *regs) static void sender_guest_code(struct test_data_page *data) { - uint64_t last_wake_count; - uint64_t last_hlt_count; - uint64_t last_ipis_rcvd_count; - uint32_t icr_val; - uint32_t icr2_val; - uint64_t tsc_start; + u64 last_wake_count; + u64 last_hlt_count; + u64 last_ipis_rcvd_count; + u32 icr_val; + u32 icr2_val; + u64 tsc_start; verify_apic_base_addr(); xapic_enable(); @@ -248,7 +248,7 @@ static void cancel_join_vcpu_thread(pthread_t thread, struct kvm_vcpu *vcpu) } void do_migrations(struct test_data_page *data, int run_secs, int delay_usecs, - uint64_t *pipis_rcvd) + u64 *pipis_rcvd) { long pages_not_moved; unsigned long nodemask = 0; @@ -259,9 +259,9 @@ void do_migrations(struct test_data_page *data, int run_secs, int delay_usecs, int i; int from, to; unsigned long bit; - uint64_t hlt_count; - uint64_t wake_count; - uint64_t ipis_sent; + u64 hlt_count; + u64 wake_count; + u64 ipis_sent; fprintf(stderr, "Calling migrate_pages every %d microseconds\n", delay_usecs); @@ -393,12 +393,12 @@ int main(int argc, char *argv[]) int run_secs = 0; int delay_usecs = 0; struct test_data_page *data; - vm_vaddr_t test_data_page_vaddr; + gva_t test_data_page_gva; bool migrate = false; pthread_t threads[2]; struct thread_params params[2]; struct kvm_vm *vm; - uint64_t *pipis_rcvd; + u64 *pipis_rcvd; get_cmdline_args(argc, argv, &run_secs, &migrate, &delay_usecs); if (run_secs <= 0) @@ -414,16 +414,16 @@ int main(int argc, char *argv[]) params[1].vcpu = vm_vcpu_add(vm, 1, sender_guest_code); - test_data_page_vaddr = vm_vaddr_alloc_page(vm); - data = addr_gva2hva(vm, test_data_page_vaddr); + test_data_page_gva = vm_alloc_page(vm); + data = addr_gva2hva(vm, test_data_page_gva); memset(data, 0, sizeof(*data)); params[0].data = data; params[1].data = data; - vcpu_args_set(params[0].vcpu, 1, test_data_page_vaddr); - vcpu_args_set(params[1].vcpu, 1, test_data_page_vaddr); + vcpu_args_set(params[0].vcpu, 1, test_data_page_gva); + vcpu_args_set(params[1].vcpu, 1, test_data_page_gva); - pipis_rcvd = (uint64_t *)addr_gva2hva(vm, (uint64_t)&ipis_rcvd); + pipis_rcvd = (u64 *)addr_gva2hva(vm, (u64)&ipis_rcvd); params[0].pipis_rcvd = pipis_rcvd; params[1].pipis_rcvd = pipis_rcvd; diff --git a/tools/testing/selftests/kvm/x86/xapic_state_test.c b/tools/testing/selftests/kvm/x86/xapic_state_test.c index 0c5e12f5f14e..637bb90c1d93 100644 --- a/tools/testing/selftests/kvm/x86/xapic_state_test.c +++ b/tools/testing/selftests/kvm/x86/xapic_state_test.c @@ -23,7 +23,7 @@ static void xapic_guest_code(void) xapic_enable(); while (1) { - uint64_t val = (u64)xapic_read_reg(APIC_IRR) | + u64 val = (u64)xapic_read_reg(APIC_IRR) | (u64)xapic_read_reg(APIC_IRR + 0x10) << 32; xapic_write_reg(APIC_ICR2, val >> 32); @@ -43,7 +43,7 @@ static void x2apic_guest_code(void) x2apic_enable(); do { - uint64_t val = x2apic_read_reg(APIC_IRR) | + u64 val = x2apic_read_reg(APIC_IRR) | x2apic_read_reg(APIC_IRR + 0x10) << 32; if (val & X2APIC_RSVD_BITS_MASK) { @@ -56,12 +56,12 @@ static void x2apic_guest_code(void) } while (1); } -static void ____test_icr(struct xapic_vcpu *x, uint64_t val) +static void ____test_icr(struct xapic_vcpu *x, u64 val) { struct kvm_vcpu *vcpu = x->vcpu; struct kvm_lapic_state xapic; struct ucall uc; - uint64_t icr; + u64 icr; /* * Tell the guest what ICR value to write. Use the IRR to pass info, @@ -93,7 +93,7 @@ static void ____test_icr(struct xapic_vcpu *x, uint64_t val) TEST_ASSERT_EQ(icr, val & ~APIC_ICR_BUSY); } -static void __test_icr(struct xapic_vcpu *x, uint64_t val) +static void __test_icr(struct xapic_vcpu *x, u64 val) { /* * The BUSY bit is reserved on both AMD and Intel, but only AMD treats @@ -109,7 +109,7 @@ static void __test_icr(struct xapic_vcpu *x, uint64_t val) static void test_icr(struct xapic_vcpu *x) { struct kvm_vcpu *vcpu = x->vcpu; - uint64_t icr, i, j; + u64 icr, i, j; icr = APIC_DEST_SELF | APIC_INT_ASSERT | APIC_DM_FIXED; for (i = 0; i <= 0xff; i++) @@ -142,9 +142,9 @@ static void test_icr(struct xapic_vcpu *x) __test_icr(x, -1ull & ~APIC_DM_FIXED_MASK); } -static void __test_apic_id(struct kvm_vcpu *vcpu, uint64_t apic_base) +static void __test_apic_id(struct kvm_vcpu *vcpu, u64 apic_base) { - uint32_t apic_id, expected; + u32 apic_id, expected; struct kvm_lapic_state xapic; vcpu_set_msr(vcpu, MSR_IA32_APICBASE, apic_base); @@ -170,9 +170,9 @@ static void __test_apic_id(struct kvm_vcpu *vcpu, uint64_t apic_base) */ static void test_apic_id(void) { - const uint32_t NR_VCPUS = 3; + const u32 NR_VCPUS = 3; struct kvm_vcpu *vcpus[NR_VCPUS]; - uint64_t apic_base; + u64 apic_base; struct kvm_vm *vm; int i; diff --git a/tools/testing/selftests/kvm/x86/xapic_tpr_test.c b/tools/testing/selftests/kvm/x86/xapic_tpr_test.c index 3862134d9d40..ab25db2235d5 100644 --- a/tools/testing/selftests/kvm/x86/xapic_tpr_test.c +++ b/tools/testing/selftests/kvm/x86/xapic_tpr_test.c @@ -58,7 +58,7 @@ static void tpr_guest_irq_queue(void) if (is_x2apic) { x2apic_write_reg(APIC_SELF_IPI, IRQ_VECTOR); } else { - uint32_t icr, icr2; + u32 icr, icr2; icr = APIC_DEST_SELF | APIC_DEST_PHYSICAL | APIC_DM_FIXED | IRQ_VECTOR; @@ -69,9 +69,9 @@ static void tpr_guest_irq_queue(void) } } -static uint8_t tpr_guest_tpr_get(void) +static u8 tpr_guest_tpr_get(void) { - uint32_t taskpri; + u32 taskpri; if (is_x2apic) taskpri = x2apic_read_reg(APIC_TASKPRI); @@ -81,9 +81,9 @@ static uint8_t tpr_guest_tpr_get(void) return GET_APIC_PRI(taskpri); } -static uint8_t tpr_guest_ppr_get(void) +static u8 tpr_guest_ppr_get(void) { - uint32_t procpri; + u32 procpri; if (is_x2apic) procpri = x2apic_read_reg(APIC_PROCPRI); @@ -93,9 +93,9 @@ static uint8_t tpr_guest_ppr_get(void) return GET_APIC_PRI(procpri); } -static uint8_t tpr_guest_cr8_get(void) +static u8 tpr_guest_cr8_get(void) { - uint64_t cr8; + u64 cr8; asm volatile ("mov %%cr8, %[cr8]\n\t" : [cr8] "=r"(cr8)); @@ -104,7 +104,7 @@ static uint8_t tpr_guest_cr8_get(void) static void tpr_guest_check_tpr_ppr_cr8_equal(void) { - uint8_t tpr; + u8 tpr; tpr = tpr_guest_tpr_get(); @@ -157,19 +157,19 @@ static void tpr_guest_code(void) GUEST_DONE(); } -static uint8_t lapic_tpr_get(struct kvm_lapic_state *xapic) +static u8 lapic_tpr_get(struct kvm_lapic_state *xapic) { return GET_APIC_PRI(*((u32 *)&xapic->regs[APIC_TASKPRI])); } -static void lapic_tpr_set(struct kvm_lapic_state *xapic, uint8_t val) +static void lapic_tpr_set(struct kvm_lapic_state *xapic, u8 val) { u32 *taskpri = (u32 *)&xapic->regs[APIC_TASKPRI]; *taskpri = SET_APIC_PRI(*taskpri, val); } -static uint8_t sregs_tpr(struct kvm_sregs *sregs) +static u8 sregs_tpr(struct kvm_sregs *sregs) { return sregs->cr8 & GENMASK(3, 0); } @@ -197,7 +197,7 @@ static void test_tpr_check_tpr_cr8_equal(struct kvm_vcpu *vcpu) static void test_tpr_set_tpr_for_irq(struct kvm_vcpu *vcpu, bool mask) { struct kvm_lapic_state xapic; - uint8_t tpr; + u8 tpr; static_assert(IRQ_VECTOR >= 16, "invalid IRQ vector number"); tpr = IRQ_VECTOR / 16; diff --git a/tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c b/tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c index d038c1571729..40dc9e6b3fad 100644 --- a/tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c +++ b/tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c @@ -21,7 +21,7 @@ */ #define ASSERT_XFEATURE_DEPENDENCIES(supported_xcr0, xfeatures, dependencies) \ do { \ - uint64_t __supported = (supported_xcr0) & ((xfeatures) | (dependencies)); \ + u64 __supported = (supported_xcr0) & ((xfeatures) | (dependencies)); \ \ __GUEST_ASSERT((__supported & (xfeatures)) != (xfeatures) || \ __supported == ((xfeatures) | (dependencies)), \ @@ -39,7 +39,7 @@ do { \ */ #define ASSERT_ALL_OR_NONE_XFEATURE(supported_xcr0, xfeatures) \ do { \ - uint64_t __supported = (supported_xcr0) & (xfeatures); \ + u64 __supported = (supported_xcr0) & (xfeatures); \ \ __GUEST_ASSERT(!__supported || __supported == (xfeatures), \ "supported = 0x%lx, xfeatures = 0x%llx", \ @@ -48,8 +48,8 @@ do { \ static void guest_code(void) { - uint64_t initial_xcr0; - uint64_t supported_xcr0; + u64 initial_xcr0; + u64 supported_xcr0; int i, vector; set_cr4(get_cr4() | X86_CR4_OSXSAVE); diff --git a/tools/testing/selftests/kvm/x86/xen_shinfo_test.c b/tools/testing/selftests/kvm/x86/xen_shinfo_test.c index 23909b501ac2..5076f6a75455 100644 --- a/tools/testing/selftests/kvm/x86/xen_shinfo_test.c +++ b/tools/testing/selftests/kvm/x86/xen_shinfo_test.c @@ -116,15 +116,15 @@ struct pvclock_wall_clock { } __attribute__((__packed__)); struct vcpu_runstate_info { - uint32_t state; - uint64_t state_entry_time; - uint64_t time[5]; /* Extra field for overrun check */ + u32 state; + u64 state_entry_time; + u64 time[5]; /* Extra field for overrun check */ }; struct compat_vcpu_runstate_info { - uint32_t state; - uint64_t state_entry_time; - uint64_t time[5]; + u32 state; + u64 state_entry_time; + u64 time[5]; } __attribute__((__packed__)); struct arch_vcpu_info { @@ -133,8 +133,8 @@ struct arch_vcpu_info { }; struct vcpu_info { - uint8_t evtchn_upcall_pending; - uint8_t evtchn_upcall_mask; + u8 evtchn_upcall_pending; + u8 evtchn_upcall_mask; unsigned long evtchn_pending_sel; struct arch_vcpu_info arch; struct pvclock_vcpu_time_info time; @@ -145,7 +145,7 @@ struct shared_info { unsigned long evtchn_pending[64]; unsigned long evtchn_mask[64]; struct pvclock_wall_clock wc; - uint32_t wc_sec_hi; + u32 wc_sec_hi; /* arch_shared_info here */ }; @@ -658,7 +658,7 @@ int main(int argc, char *argv[]) printf("Testing RUNSTATE_ADJUST\n"); rst.type = KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_ADJUST; memset(&rst.u, 0, sizeof(rst.u)); - rst.u.runstate.state = (uint64_t)-1; + rst.u.runstate.state = (u64)-1; rst.u.runstate.time_blocked = 0x5a - rs->time[RUNSTATE_blocked]; rst.u.runstate.time_offline = @@ -1113,7 +1113,7 @@ int main(int argc, char *argv[]) /* Don't change the address, just trigger a write */ struct kvm_xen_vcpu_attr adj = { .type = KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_ADJUST, - .u.runstate.state = (uint64_t)-1 + .u.runstate.state = (u64)-1 }; vcpu_ioctl(vcpu, KVM_XEN_VCPU_SET_ATTR, &adj); diff --git a/tools/testing/selftests/kvm/x86/xss_msr_test.c b/tools/testing/selftests/kvm/x86/xss_msr_test.c index f331a4e9bae3..12c63df6bbce 100644 --- a/tools/testing/selftests/kvm/x86/xss_msr_test.c +++ b/tools/testing/selftests/kvm/x86/xss_msr_test.c @@ -17,7 +17,7 @@ int main(int argc, char *argv[]) bool xss_in_msr_list; struct kvm_vm *vm; struct kvm_vcpu *vcpu; - uint64_t xss_val; + u64 xss_val; int i, r; /* Create VM */ diff --git a/tools/testing/selftests/mm/config b/tools/testing/selftests/mm/config index 1dbe2b4558ab..06f78bd232e2 100644 --- a/tools/testing/selftests/mm/config +++ b/tools/testing/selftests/mm/config @@ -13,3 +13,4 @@ CONFIG_PROFILING=y CONFIG_UPROBES=y CONFIG_MEMORY_FAILURE=y CONFIG_HWPOISON_INJECT=m +CONFIG_PROC_MEM_ALWAYS_FORCE=y diff --git a/tools/testing/selftests/sched_ext/Makefile b/tools/testing/selftests/sched_ext/Makefile index 789037be44c7..5d2dffca0e91 100644 --- a/tools/testing/selftests/sched_ext/Makefile +++ b/tools/testing/selftests/sched_ext/Makefile @@ -175,6 +175,7 @@ auto-test-targets := \ maximal \ maybe_null \ minimal \ + non_scx_kfunc_deny \ numa \ allowed_cpus \ peek_dsq \ diff --git a/tools/testing/selftests/sched_ext/non_scx_kfunc_deny.bpf.c b/tools/testing/selftests/sched_ext/non_scx_kfunc_deny.bpf.c new file mode 100644 index 000000000000..9f16d39255e7 --- /dev/null +++ b/tools/testing/selftests/sched_ext/non_scx_kfunc_deny.bpf.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Verify that context-sensitive SCX kfuncs (even "unlocked" ones) are + * restricted to only SCX struct_ops programs. Non-SCX struct_ops programs, + * such as TCP congestion control programs, should be rejected by the BPF + * verifier when attempting to call these kfuncs. + * + * Copyright (C) 2026 Ching-Chun (Jim) Huang + * Copyright (C) 2026 Cheng-Yang Chou + */ + +#include +#include +#include + +/* SCX kfunc from scx_kfunc_ids_any set */ +void scx_bpf_kick_cpu(s32 cpu, u64 flags) __ksym; + +SEC("struct_ops/ssthresh") +__u32 BPF_PROG(tcp_ca_ssthresh, struct sock *sk) +{ + /* + * This call should be rejected by the verifier because this is a + * TCP congestion control program (non-SCX struct_ops). + */ + scx_bpf_kick_cpu(0, 0); + return 2; +} + +SEC("struct_ops/cong_avoid") +void BPF_PROG(tcp_ca_cong_avoid, struct sock *sk, __u32 ack, __u32 acked) {} + +SEC("struct_ops/undo_cwnd") +__u32 BPF_PROG(tcp_ca_undo_cwnd, struct sock *sk) { return 2; } + +SEC(".struct_ops") +struct tcp_congestion_ops tcp_non_scx_ca = { + .ssthresh = (void *)tcp_ca_ssthresh, + .cong_avoid = (void *)tcp_ca_cong_avoid, + .undo_cwnd = (void *)tcp_ca_undo_cwnd, + .name = "tcp_kfunc_deny", +}; + +char _license[] SEC("license") = "GPL"; diff --git a/tools/testing/selftests/sched_ext/non_scx_kfunc_deny.c b/tools/testing/selftests/sched_ext/non_scx_kfunc_deny.c new file mode 100644 index 000000000000..1c031575fb87 --- /dev/null +++ b/tools/testing/selftests/sched_ext/non_scx_kfunc_deny.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Verify that context-sensitive SCX kfuncs (even "unlocked" ones) are + * restricted to only SCX struct_ops programs. Non-SCX struct_ops programs, + * such as TCP congestion control programs, should be rejected by the BPF + * verifier when attempting to call these kfuncs. + * + * Copyright (C) 2026 Ching-Chun (Jim) Huang + * Copyright (C) 2026 Cheng-Yang Chou + */ + +#include +#include +#include +#include +#include +#include "non_scx_kfunc_deny.bpf.skel.h" +#include "scx_test.h" + +static enum scx_test_status run(void *ctx) +{ + struct non_scx_kfunc_deny *skel; + int err; + + skel = non_scx_kfunc_deny__open(); + if (!skel) { + SCX_ERR("Failed to open skel"); + return SCX_TEST_FAIL; + } + + err = non_scx_kfunc_deny__load(skel); + non_scx_kfunc_deny__destroy(skel); + + if (err == 0) { + SCX_ERR("non-SCX BPF program loaded when it should have been rejected"); + return SCX_TEST_FAIL; + } + + return SCX_TEST_PASS; +} + +struct scx_test non_scx_kfunc_deny = { + .name = "non_scx_kfunc_deny", + .description = "Verify that non-SCX struct_ops programs cannot call SCX kfuncs", + .run = run, +}; +REGISTER_SCX_TEST(&non_scx_kfunc_deny) diff --git a/tools/testing/selftests/tc-testing/tc-tests/qdiscs/taprio.json b/tools/testing/selftests/tc-testing/tc-tests/qdiscs/taprio.json index 557fb074acf0..cd19d05925e4 100644 --- a/tools/testing/selftests/tc-testing/tc-tests/qdiscs/taprio.json +++ b/tools/testing/selftests/tc-testing/tc-tests/qdiscs/taprio.json @@ -302,5 +302,31 @@ "$TC qdisc del dev $ETH root", "echo \"1\" > /sys/bus/netdevsim/del_device" ] + }, + { + "id": "c7e1", + "name": "Class dump after graft and delete of explicit child qdisc", + "category": [ + "qdisc", + "taprio" + ], + "plugins": { + "requires": "nsPlugin" + }, + "setup": [ + "echo \"1 1 8\" > /sys/bus/netdevsim/new_device", + "$TC qdisc replace dev $ETH handle 8001: parent root taprio num_tc 8 map 0 1 2 3 4 5 6 7 queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 base-time 0 sched-entry S ff 20000000 clockid CLOCK_TAI", + "$TC qdisc add dev $ETH parent 8001:1 handle 8002: pfifo", + "$TC qdisc del dev $ETH parent 8001:1 handle 8002:" + ], + "cmdUnderTest": "$TC class show dev $ETH", + "expExitCode": "0", + "verifyCmd": "$TC class show dev $ETH", + "matchPattern": "class taprio 8001:[0-9]+ root", + "matchCount": "8", + "teardown": [ + "$TC qdisc del dev $ETH root", + "echo \"1\" > /sys/bus/netdevsim/del_device" + ] } ] diff --git a/tools/testing/vma/include/dup.h b/tools/testing/vma/include/dup.h index b4864aad2db0..9e0dfd3a85b0 100644 --- a/tools/testing/vma/include/dup.h +++ b/tools/testing/vma/include/dup.h @@ -1330,7 +1330,7 @@ static inline int __compat_vma_mmap(struct vm_area_desc *desc, /* Update the VMA from the descriptor. */ compat_set_vma_from_desc(vma, desc); /* Complete any specified mmap actions. */ - return mmap_action_complete(vma, &desc->action); + return mmap_action_complete(vma, &desc->action, /*is_compat=*/true); } static inline int compat_vma_mmap(struct file *file, struct vm_area_struct *vma) diff --git a/tools/testing/vma/include/stubs.h b/tools/testing/vma/include/stubs.h index a30b8bc84955..64164e25658f 100644 --- a/tools/testing/vma/include/stubs.h +++ b/tools/testing/vma/include/stubs.h @@ -87,7 +87,8 @@ static inline int mmap_action_prepare(struct vm_area_desc *desc) } static inline int mmap_action_complete(struct vm_area_struct *vma, - struct mmap_action *action) + struct mmap_action *action, + bool is_compat) { return 0; }