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soc/tegra: Updates for v6.17-rc1

Browse Source 
The bulk of this is the addition of Tegra264 support for various low-
 level components. This also adds fabric descriptors for the new Tegra254
 and Tegra264 chips.
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Merge tag 'tegra-for-6.17-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers

soc/tegra: Updates for v6.17-rc1

The bulk of this is the addition of Tegra264 support for various low-
level components. This also adds fabric descriptors for the new Tegra254
and Tegra264 chips.

* tag 'tegra-for-6.17-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: cbb: Add support for CBB fabrics in Tegra254
  soc/tegra: cbb: Add support for CBB fabrics in Tegra264
  soc/tegra: cbb: Support HW lookup to get timed out target address
  soc/tegra: cbb: Improve handling for per SoC fabric data
  soc/tegra: cbb: Make error interrupt enable and status per SoC
  soc/tegra: cbb: Change master/slave to initiator/target
  soc/tegra: cbb: Clear ERR_FORCE register with ERR_STATUS
  soc/tegra: Add Tegra264 APBMISC compatible string
  soc/tegra: pmc: Add Tegra264 support
  soc/tegra: Enable support for Tegra264

Link: https://lore.kernel.org/r/20250711220943.2389322-1-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-07-21 18:18:07 +02:00
commit 985da98f29
5 changed files with 733 additions and 191 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/soc/tegra/Kconfig
View File

@ -138,6 +138,14 @@ config ARCH_TEGRA_241_SOC
help
Enable support for the NVIDIA Tegra241 SoC.
config ARCH_TEGRA_264_SOC
bool "NVIDIA Tegra264 SoC"
depends on !CPU_BIG_ENDIAN
select MAILBOX
select SOC_TEGRA_PMC
help
Enable support for the NVIDIA Tegra264 SoC.
endif
endif

34
drivers/soc/tegra/cbb/tegra194-cbb.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved
* Copyright (c) 2021-2025, NVIDIA CORPORATION. All rights reserved
*
* The driver handles Error's from Control Backbone(CBB) generated due to
* illegal accesses. When an error is reported from a NOC within CBB,
@ -138,7 +138,7 @@ struct tegra194_cbb_userbits {
struct tegra194_cbb_noc_data {
const char *name;
bool erd_mask_inband_err;
const char * const *master_id;
const char * const *initiator_id;
unsigned int max_aperture;
const struct tegra194_cbb_aperture *noc_aperture;
const char * const *routeid_initflow;
@ -216,7 +216,7 @@ static const char * const tegra194_axi2apb_error[] = {
"CH2RFIFOF - Ch2 Request FIFO Full interrupt"
};
static const char * const tegra194_master_id[] = {
static const char * const tegra194_initiator_id[] = {
[0x0] = "CCPLEX",
[0x1] = "CCPLEX_DPMU",
[0x2] = "BPMP",
@ -238,7 +238,7 @@ static const struct tegra_cbb_error tegra194_cbb_errors[] = {
{
.code = "SLV",
.source = "Target",
.desc = "Target error detected by CBB slave"
.desc = "Target error detected by CBB target"
}, {
.code = "DEC",
.source = "Initiator NIU",
@ -1774,8 +1774,8 @@ static void print_errlog5(struct seq_file *file, struct tegra194_cbb *cbb)
tegra_cbb_print_err(file, "\t AXI ID\t\t: %#x\n", userbits.axi_id);
}
tegra_cbb_print_err(file, "\t Master ID\t\t: %s\n",
cbb->noc->master_id[userbits.mstr_id]);
tegra_cbb_print_err(file, "\t Initiator ID\t\t: %s\n",
cbb->noc->initiator_id[userbits.mstr_id]);
tegra_cbb_print_err(file, "\t Security Group(GRPSEC): %#x\n", userbits.grpsec);
tegra_cbb_print_cache(file, userbits.axcache);
tegra_cbb_print_prot(file, userbits.axprot);
@ -1837,14 +1837,14 @@ print_errlog1_2(struct seq_file *file, struct tegra194_cbb *cbb,
/*
* Print transcation type, error code and description from ErrLog0 for all
* errors. For NOC slave errors, all relevant error info is printed using
* errors. For NOC target errors, all relevant error info is printed using
* ErrLog0 only. But additional information is printed for errors from
* APB slaves because for them:
* - All errors are logged as SLV(slave) errors due to APB having only single
* APB targets because for them:
* - All errors are logged as SLV(target) errors due to APB having only single
* bit pslverr to report all errors.
* - Exact cause is printed by reading DMAAPB_X_RAW_INTERRUPT_STATUS register.
* - The driver prints information showing AXI2APB bridge and exact error
* only if there is error in any AXI2APB slave.
* only if there is error in any AXI2APB target.
* - There is still no way to disambiguate a DEC error from SLV error type.
*/
static bool print_errlog0(struct seq_file *file, struct tegra194_cbb *cbb)
@ -1884,8 +1884,8 @@ static bool print_errlog0(struct seq_file *file, struct tegra194_cbb *cbb)
/* For all SLV errors, read DMAAPB_X_RAW_INTERRUPT_STATUS
* register to get error status for all AXI2APB bridges.
* Print bridge details if a bit is set in a bridge's
* status register due to error in a APB slave connected
* to that bridge. For other NOC slaves, none of the status
* status register due to error in a APB target connected
* to that bridge. For other NOC targets, none of the status
* register will be set.
*/
@ -2118,7 +2118,7 @@ static const struct tegra_cbb_ops tegra194_cbb_ops = {
static struct tegra194_cbb_noc_data tegra194_cbb_central_noc_data = {
.name = "cbb-noc",
.erd_mask_inband_err = true,
.master_id = tegra194_master_id,
.initiator_id = tegra194_initiator_id,
.noc_aperture = tegra194_cbbcentralnoc_apert_lookup,
.max_aperture = ARRAY_SIZE(tegra194_cbbcentralnoc_apert_lookup),
.routeid_initflow = tegra194_cbbcentralnoc_routeid_initflow,
@ -2130,7 +2130,7 @@ static struct tegra194_cbb_noc_data tegra194_cbb_central_noc_data = {
static struct tegra194_cbb_noc_data tegra194_aon_noc_data = {
.name = "aon-noc",
.erd_mask_inband_err = false,
.master_id = tegra194_master_id,
.initiator_id = tegra194_initiator_id,
.noc_aperture = tegra194_aonnoc_aperture_lookup,
.max_aperture = ARRAY_SIZE(tegra194_aonnoc_aperture_lookup),
.routeid_initflow = tegra194_aonnoc_routeid_initflow,
@ -2142,7 +2142,7 @@ static struct tegra194_cbb_noc_data tegra194_aon_noc_data = {
static struct tegra194_cbb_noc_data tegra194_bpmp_noc_data = {
.name = "bpmp-noc",
.erd_mask_inband_err = false,
.master_id = tegra194_master_id,
.initiator_id = tegra194_initiator_id,
.noc_aperture = tegra194_bpmpnoc_apert_lookup,
.max_aperture = ARRAY_SIZE(tegra194_bpmpnoc_apert_lookup),
.routeid_initflow = tegra194_bpmpnoc_routeid_initflow,
@ -2154,7 +2154,7 @@ static struct tegra194_cbb_noc_data tegra194_bpmp_noc_data = {
static struct tegra194_cbb_noc_data tegra194_rce_noc_data = {
.name = "rce-noc",
.erd_mask_inband_err = false,
.master_id = tegra194_master_id,
.initiator_id = tegra194_initiator_id,
.noc_aperture = tegra194_scenoc_apert_lookup,
.max_aperture = ARRAY_SIZE(tegra194_scenoc_apert_lookup),
.routeid_initflow = tegra194_scenoc_routeid_initflow,
@ -2166,7 +2166,7 @@ static struct tegra194_cbb_noc_data tegra194_rce_noc_data = {
static struct tegra194_cbb_noc_data tegra194_sce_noc_data = {
.name = "sce-noc",
.erd_mask_inband_err = false,
.master_id = tegra194_master_id,
.initiator_id = tegra194_initiator_id,
.noc_aperture = tegra194_scenoc_apert_lookup,
.max_aperture = ARRAY_SIZE(tegra194_scenoc_apert_lookup),
.routeid_initflow = tegra194_scenoc_routeid_initflow,

760
drivers/soc/tegra/cbb/tegra234-cbb.c
View File

File diff suppressed because it is too large Load Diff

1
drivers/soc/tegra/fuse/tegra-apbmisc.c
View File

@ -128,6 +128,7 @@ static const struct of_device_id apbmisc_match[] __initconst = {
{ .compatible = "nvidia,tegra186-misc", },
{ .compatible = "nvidia,tegra194-misc", },
{ .compatible = "nvidia,tegra234-misc", },
{ .compatible = "nvidia,tegra264-misc", },
{},
};

121
drivers/soc/tegra/pmc.c
View File

@ -4247,7 +4247,128 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = {
.has_single_mmio_aperture = false,
};
static const struct tegra_pmc_regs tegra264_pmc_regs = {
.scratch0 = 0x684,
.rst_status = 0x4,
.rst_source_shift = 0x2,
.rst_source_mask = 0x1fc,
.rst_level_shift = 0x0,
.rst_level_mask = 0x3,
};
static const char * const tegra264_reset_sources[] = {
"SYS_RESET_N", /* 0x0 */
"CSDC_RTC_XTAL",
"VREFRO_POWER_BAD",
"SCPM_SOC_XTAL",
"SCPM_RTC_XTAL",
"FMON_32K",
"FMON_OSC",
"POD_RTC",
"POD_IO", /* 0x8 */
"POD_PLUS_IO_SPLL",
"POD_PLUS_SOC",
"VMON_PLUS_UV",
"VMON_PLUS_OV",
"FUSECRC_FAULT",
"OSC_FAULT",
"BPMP_BOOT_FAULT",
"SCPM_BPMP_CORE_CLK", /* 0x10 */
"SCPM_PSC_SE_CLK",
"VMON_SOC_MIN",
"VMON_SOC_MAX",
"VMON_MSS_MIN",
"VMON_MSS_MAX",
"POD_PLUS_IO_VMON",
"NVJTAG_SEL_MONITOR",
"NV_THERM_FAULT", /* 0x18 */
"FSI_THERM_FAULT",
"PSC_SW",
"SCPM_OESP_SE_CLK",
"SCPM_SB_SE_CLK",
"POD_CPU",
"POD_GPU",
"DCLS_GPU",
"POD_MSS", /* 0x20 */
"FMON_FSI",
"POD_FSI",
"VMON_FSI_MIN",
"VMON_FSI_MAX",
"VMON_CPU0_MIN",
"VMON_CPU0_MAX",
"BPMP_FMON",
"AO_WDT_POR", /* 0x28 */
"BPMP_WDT_POR",
"AO_TKE_WDT_POR",
"RCE0_WDT_POR",
"RCE1_WDT_POR",
"DCE_WDT_POR",
"FSI_R5_WDT_POR",
"FSI_R52_0_WDT_POR",
"FSI_R52_1_WDT_POR", /* 0x30 */
"FSI_R52_2_WDT_POR",
"FSI_R52_3_WDT_POR",
"TOP_0_WDT_POR",
"TOP_1_WDT_POR",
"TOP_2_WDT_POR",
"APE_C0_WDT_POR",
"APE_C1_WDT_POR",
"GPU_TKE_WDT_POR", /* 0x38 */
"PSC_WDT_POR",
"OESP_WDT_POR",
"SB_WDT_POR",
"SW_MAIN",
"L0L1_RST_OUT_N",
"FSI_HSM",
"CSITE_SW",
"AO_WDT_DBG", /* 0x40 */
"BPMP_WDT_DBG",
"AO_TKE_WDT_DBG",
"RCE0_WDT_DBG",
"RCE1_WDT_DBG",
"DCE_WDT_DBG",
"FSI_R5_WDT_DBG",
"FSI_R52_0_WDT_DBG",
"FSI_R52_1_WDT_DBG", /* 0x48 */
"FSI_R52_2_WDT_DBG",
"FSI_R52_3_WDT_DBG",
"TOP_0_WDT_DBG",
"TOP_1_WDT_DBG",
"TOP_2_WDT_DBG",
"APE_C0_WDT_DBG",
"APE_C1_WDT_DBG",
"PSC_WDT_DBG", /* 0x50 */
"OESP_WDT_DBG",
"SB_WDT_DBG",
"TSC_0_WDT_DBG",
"TSC_1_WDT_DBG",
"L2_RST_OUT_N",
"SC7"
};
static const struct tegra_wake_event tegra264_wake_events[] = {
};
static const struct tegra_pmc_soc tegra264_pmc_soc = {
.has_impl_33v_pwr = true,
.regs = &tegra264_pmc_regs,
.init = tegra186_pmc_init,
.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
.set_wake_filters = tegra186_pmc_set_wake_filters,
.irq_set_wake = tegra186_pmc_irq_set_wake,
.irq_set_type = tegra186_pmc_irq_set_type,
.reset_sources = tegra264_reset_sources,
.num_reset_sources = ARRAY_SIZE(tegra264_reset_sources),
.reset_levels = tegra186_reset_levels,
.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
.wake_events = tegra264_wake_events,
.num_wake_events = ARRAY_SIZE(tegra264_wake_events),
.max_wake_events = 128,
.max_wake_vectors = 4,
};
static const struct of_device_id tegra_pmc_match[] = {
{ .compatible = "nvidia,tegra264-pmc", .data = &tegra264_pmc_soc },
{ .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
{ .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
{ .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },