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mlx5-updates-2023-08-16
1) aRFS ethtool stats
Improve aRFS observability by adding new set of counters. Each Rx
ring will have this set of counters listed below.
These counters are exposed through ethtool -S.
1.1) arfs_add: number of times a new rule has been created.
1.2) arfs_request_in: number of times a rule was requested to move from
its current Rx ring to a new Rx ring (incremented on the destination
Rx ring).
1.3) arfs_request_out: number of times a rule was requested to move out
from its current Rx ring (incremented on source/current Rx ring).
1.4) arfs_expired: number of times a rule has been expired by the
kernel and removed from HW.
1.5) arfs_err: number of times a rule creation or modification has
failed.
2) Supporting inline WQE when possible in SW steering
3) Misc cleanups and fixups to net-next branch
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Merge tag 'mlx5-updates-2023-08-16' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux
Saeed Mahameed says:
====================
mlx5-updates-2023-08-16
1) aRFS ethtool stats
Improve aRFS observability by adding new set of counters. Each Rx
ring will have this set of counters listed below.
These counters are exposed through ethtool -S.
1.1) arfs_add: number of times a new rule has been created.
1.2) arfs_request_in: number of times a rule was requested to move from
its current Rx ring to a new Rx ring (incremented on the destination
Rx ring).
1.3) arfs_request_out: number of times a rule was requested to move out
from its current Rx ring (incremented on source/current Rx ring).
1.4) arfs_expired: number of times a rule has been expired by the
kernel and removed from HW.
1.5) arfs_err: number of times a rule creation or modification has
failed.
2) Supporting inline WQE when possible in SW steering
3) Misc cleanups and fixups to net-next branch
* tag 'mlx5-updates-2023-08-16' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux:
net/mlx5: Devcom, only use devcom after NULL check in mlx5_devcom_send_event()
net/mlx5: DR, Supporting inline WQE when possible
net/mlx5: Rename devlink port ops struct for PFs/VFs
net/mlx5: Remove VPORT_UPLINK handling from devlink_port.c
net/mlx5: Call mlx5_esw_offloads_rep_load/unload() for uplink port directly
net/mlx5: Update dead links in Kconfig documentation
net/mlx5: Remove health syndrome enum duplication
net/mlx5: DR, Remove unneeded local variable
net/mlx5: DR, Fix code indentation
net/mlx5: IRQ, consolidate irq and affinity mask allocation
net/mlx5e: Fix spelling mistake "Faided" -> "Failed"
net/mlx5e: aRFS, Introduce ethtool stats
net/mlx5e: aRFS, Warn if aRFS table does not exist for aRFS rule
net/mlx5e: aRFS, Prevent repeated kernel rule migrations requests
====================
Link: https://lore.kernel.org/r/20230821175739.81188-1-saeed@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
commit
9817363372
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|
@ -346,6 +346,24 @@ the software port.
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- The number of receive packets with CQE compression on ring i [#accel]_.
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- Acceleration
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* - `rx[i]_arfs_add`
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- The number of aRFS flow rules added to the device for direct RQ steering
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on ring i [#accel]_.
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- Acceleration
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* - `rx[i]_arfs_request_in`
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- Number of flow rules that have been requested to move into ring i for
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direct RQ steering [#accel]_.
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- Acceleration
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* - `rx[i]_arfs_request_out`
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- Number of flow rules that have been requested to move out of ring i [#accel]_.
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- Acceleration
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* - `rx[i]_arfs_expired`
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- Number of flow rules that have been expired and removed [#accel]_.
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- Acceleration
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* - `rx[i]_arfs_err`
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- Number of flow rules that failed to be added to the flow table.
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- Error
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@ -445,11 +463,6 @@ the software port.
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context.
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- Error
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* - `rx[i]_xsk_arfs_err`
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- aRFS (accelerated Receive Flow Steering) does not occur in the XSK RQ
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context, so this counter should never increment.
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- Error
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* - `rx[i]_xdp_tx_xmit`
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- The number of packets forwarded back to the port due to XDP program
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`XDP_TX` action (bouncing). these packets are not counted by other
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|
|
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|
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@ -36,7 +36,7 @@ Enabling the driver and kconfig options
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**CONFIG_MLX5_CORE_EN_DCB=(y/n)**:
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| Enables `Data Center Bridging (DCB) Support <https://community.mellanox.com/s/article/howto-auto-config-pfc-and-ets-on-connectx-4-via-lldp-dcbx>`_.
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| Enables `Data Center Bridging (DCB) Support <https://enterprise-support.nvidia.com/s/article/howto-auto-config-pfc-and-ets-on-connectx-4-via-lldp-dcbx>`_.
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**CONFIG_MLX5_CORE_IPOIB=(y/n)**
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@ -59,12 +59,12 @@ Enabling the driver and kconfig options
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**CONFIG_MLX5_EN_ARFS=(y/n)**
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| Enables Hardware-accelerated receive flow steering (arfs) support, and ntuple filtering.
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| https://community.mellanox.com/s/article/howto-configure-arfs-on-connectx-4
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| https://enterprise-support.nvidia.com/s/article/howto-configure-arfs-on-connectx-4
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**CONFIG_MLX5_EN_IPSEC=(y/n)**
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| Enables `IPSec XFRM cryptography-offload acceleration <https://support.mellanox.com/s/article/ConnectX-6DX-Bluefield-2-IPsec-HW-Full-Offload-Configuration-Guide>`_.
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| Enables :ref:`IPSec XFRM cryptography-offload acceleration <xfrm_device>`.
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**CONFIG_MLX5_EN_MACSEC=(y/n)**
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@ -87,8 +87,8 @@ Enabling the driver and kconfig options
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| Ethernet SRIOV E-Switch support in ConnectX NIC. E-Switch provides internal SRIOV packet steering
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| and switching for the enabled VFs and PF in two available modes:
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| 1) `Legacy SRIOV mode (L2 mac vlan steering based) <https://community.mellanox.com/s/article/howto-configure-sr-iov-for-connectx-4-connectx-5-with-kvm--ethernet-x>`_.
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| 2) `Switchdev mode (eswitch offloads) <https://www.mellanox.com/related-docs/prod_software/ASAP2_Hardware_Offloading_for_vSwitches_User_Manual_v4.4.pdf>`_.
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| 1) `Legacy SRIOV mode (L2 mac vlan steering based) <https://enterprise-support.nvidia.com/s/article/HowTo-Configure-SR-IOV-for-ConnectX-4-ConnectX-5-ConnectX-6-with-KVM-Ethernet>`_.
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| 2) :ref:`Switchdev mode (eswitch offloads) <switchdev>`.
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**CONFIG_MLX5_FPGA=(y/n)**
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@ -101,13 +101,13 @@ Enabling the driver and kconfig options
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**CONFIG_MLX5_INFINIBAND=(y/n/m)** (module mlx5_ib.ko)
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| Provides low-level InfiniBand/RDMA and `RoCE <https://community.mellanox.com/s/article/recommended-network-configuration-examples-for-roce-deployment>`_ support.
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| Provides low-level InfiniBand/RDMA and `RoCE <https://enterprise-support.nvidia.com/s/article/recommended-network-configuration-examples-for-roce-deployment>`_ support.
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**CONFIG_MLX5_MPFS=(y/n)**
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| Ethernet Multi-Physical Function Switch (MPFS) support in ConnectX NIC.
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| MPFs is required for when `Multi-Host <http://www.mellanox.com/page/multihost>`_ configuration is enabled to allow passing
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| MPFs is required for when `Multi-Host <https://www.nvidia.com/en-us/networking/multi-host/>`_ configuration is enabled to allow passing
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| user configured unicast MAC addresses to the requesting PF.
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@ -1,4 +1,5 @@
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.. SPDX-License-Identifier: GPL-2.0
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.. _xfrm_device:
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===============================================
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XFRM device - offloading the IPsec computations
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@ -432,8 +432,10 @@ static void arfs_may_expire_flow(struct mlx5e_priv *priv)
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}
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spin_unlock_bh(&arfs->arfs_lock);
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hlist_for_each_entry_safe(arfs_rule, htmp, &del_list, hlist) {
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if (arfs_rule->rule)
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if (arfs_rule->rule) {
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mlx5_del_flow_rules(arfs_rule->rule);
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priv->channel_stats[arfs_rule->rxq]->rq.arfs_expired++;
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}
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hlist_del(&arfs_rule->hlist);
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kfree(arfs_rule);
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}
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@ -509,6 +511,7 @@ static struct mlx5_flow_handle *arfs_add_rule(struct mlx5e_priv *priv,
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spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
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if (!spec) {
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priv->channel_stats[arfs_rule->rxq]->rq.arfs_err++;
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err = -ENOMEM;
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goto out;
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}
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@ -519,6 +522,8 @@ static struct mlx5_flow_handle *arfs_add_rule(struct mlx5e_priv *priv,
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ntohs(tuple->etype));
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arfs_table = arfs_get_table(arfs, tuple->ip_proto, tuple->etype);
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if (!arfs_table) {
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WARN_ONCE(1, "arfs table does not exist for etype %u and ip_proto %u\n",
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tuple->etype, tuple->ip_proto);
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err = -EINVAL;
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goto out;
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}
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@ -600,9 +605,11 @@ static void arfs_modify_rule_rq(struct mlx5e_priv *priv,
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dst.type = MLX5_FLOW_DESTINATION_TYPE_TIR;
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dst.tir_num = mlx5e_rx_res_get_tirn_direct(priv->rx_res, rxq);
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err = mlx5_modify_rule_destination(rule, &dst, NULL);
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if (err)
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if (err) {
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priv->channel_stats[rxq]->rq.arfs_err++;
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netdev_warn(priv->netdev,
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"Failed to modify aRFS rule destination to rq=%d\n", rxq);
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}
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}
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static void arfs_handle_work(struct work_struct *work)
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@ -632,6 +639,7 @@ static void arfs_handle_work(struct work_struct *work)
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if (IS_ERR(rule))
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goto out;
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arfs_rule->rule = rule;
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priv->channel_stats[arfs_rule->rxq]->rq.arfs_add++;
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} else {
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arfs_modify_rule_rq(priv, arfs_rule->rule,
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arfs_rule->rxq);
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@ -650,8 +658,10 @@ static struct arfs_rule *arfs_alloc_rule(struct mlx5e_priv *priv,
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struct arfs_tuple *tuple;
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rule = kzalloc(sizeof(*rule), GFP_ATOMIC);
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if (!rule)
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if (!rule) {
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priv->channel_stats[rxq]->rq.arfs_err++;
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return NULL;
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}
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rule->priv = priv;
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rule->rxq = rxq;
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@ -740,10 +750,13 @@ int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
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spin_lock_bh(&arfs->arfs_lock);
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arfs_rule = arfs_find_rule(arfs_t, &fk);
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if (arfs_rule) {
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if (arfs_rule->rxq == rxq_index) {
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if (arfs_rule->rxq == rxq_index || work_busy(&arfs_rule->arfs_work)) {
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spin_unlock_bh(&arfs->arfs_lock);
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return arfs_rule->filter_id;
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}
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priv->channel_stats[rxq_index]->rq.arfs_request_in++;
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priv->channel_stats[arfs_rule->rxq]->rq.arfs_request_out++;
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arfs_rule->rxq = rxq_index;
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} else {
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arfs_rule = arfs_alloc_rule(priv, arfs_t, &fk, rxq_index, flow_id);
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@ -180,7 +180,13 @@ static const struct counter_desc sw_stats_desc[] = {
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_congst_umr) },
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#ifdef CONFIG_MLX5_EN_ARFS
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_add) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_request_in) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_request_out) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_expired) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_err) },
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#endif
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_recover) },
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#ifdef CONFIG_PAGE_POOL_STATS
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_alloc_fast) },
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@ -231,7 +237,6 @@ static const struct counter_desc sw_stats_desc[] = {
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_cqe_compress_blks) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_cqe_compress_pkts) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_congst_umr) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_arfs_err) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_xmit) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_mpwqe) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_inlnw) },
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|
|
@ -321,7 +326,6 @@ static void mlx5e_stats_grp_sw_update_stats_xskrq(struct mlx5e_sw_stats *s,
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s->rx_xsk_cqe_compress_blks += xskrq_stats->cqe_compress_blks;
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s->rx_xsk_cqe_compress_pkts += xskrq_stats->cqe_compress_pkts;
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s->rx_xsk_congst_umr += xskrq_stats->congst_umr;
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s->rx_xsk_arfs_err += xskrq_stats->arfs_err;
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}
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static void mlx5e_stats_grp_sw_update_stats_rq_stats(struct mlx5e_sw_stats *s,
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|
|
@ -354,7 +358,13 @@ static void mlx5e_stats_grp_sw_update_stats_rq_stats(struct mlx5e_sw_stats *s,
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s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
|
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s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
|
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s->rx_congst_umr += rq_stats->congst_umr;
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#ifdef CONFIG_MLX5_EN_ARFS
|
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s->rx_arfs_add += rq_stats->arfs_add;
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s->rx_arfs_request_in += rq_stats->arfs_request_in;
|
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s->rx_arfs_request_out += rq_stats->arfs_request_out;
|
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s->rx_arfs_expired += rq_stats->arfs_expired;
|
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s->rx_arfs_err += rq_stats->arfs_err;
|
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#endif
|
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s->rx_recover += rq_stats->recover;
|
||||
#ifdef CONFIG_PAGE_POOL_STATS
|
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s->rx_pp_alloc_fast += rq_stats->pp_alloc_fast;
|
||||
|
|
@ -1990,7 +2000,13 @@ static const struct counter_desc rq_stats_desc[] = {
|
|||
{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
|
||||
{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
|
||||
{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, congst_umr) },
|
||||
#ifdef CONFIG_MLX5_EN_ARFS
|
||||
{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_add) },
|
||||
{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_request_in) },
|
||||
{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_request_out) },
|
||||
{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_expired) },
|
||||
{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_err) },
|
||||
#endif
|
||||
{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, recover) },
|
||||
#ifdef CONFIG_PAGE_POOL_STATS
|
||||
{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_alloc_fast) },
|
||||
|
|
@ -2092,7 +2108,6 @@ static const struct counter_desc xskrq_stats_desc[] = {
|
|||
{ MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
|
||||
{ MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
|
||||
{ MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, congst_umr) },
|
||||
{ MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, arfs_err) },
|
||||
};
|
||||
|
||||
static const struct counter_desc xsksq_stats_desc[] = {
|
||||
|
|
@ -2168,7 +2183,6 @@ static const struct counter_desc ptp_rq_stats_desc[] = {
|
|||
{ MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
|
||||
{ MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
|
||||
{ MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, congst_umr) },
|
||||
{ MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, arfs_err) },
|
||||
{ MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, recover) },
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -194,7 +194,13 @@ struct mlx5e_sw_stats {
|
|||
u64 rx_cqe_compress_blks;
|
||||
u64 rx_cqe_compress_pkts;
|
||||
u64 rx_congst_umr;
|
||||
#ifdef CONFIG_MLX5_EN_ARFS
|
||||
u64 rx_arfs_add;
|
||||
u64 rx_arfs_request_in;
|
||||
u64 rx_arfs_request_out;
|
||||
u64 rx_arfs_expired;
|
||||
u64 rx_arfs_err;
|
||||
#endif
|
||||
u64 rx_recover;
|
||||
u64 ch_events;
|
||||
u64 ch_poll;
|
||||
|
|
@ -256,7 +262,6 @@ struct mlx5e_sw_stats {
|
|||
u64 rx_xsk_cqe_compress_blks;
|
||||
u64 rx_xsk_cqe_compress_pkts;
|
||||
u64 rx_xsk_congst_umr;
|
||||
u64 rx_xsk_arfs_err;
|
||||
u64 tx_xsk_xmit;
|
||||
u64 tx_xsk_mpwqe;
|
||||
u64 tx_xsk_inlnw;
|
||||
|
|
@ -358,7 +363,13 @@ struct mlx5e_rq_stats {
|
|||
u64 cqe_compress_blks;
|
||||
u64 cqe_compress_pkts;
|
||||
u64 congst_umr;
|
||||
#ifdef CONFIG_MLX5_EN_ARFS
|
||||
u64 arfs_add;
|
||||
u64 arfs_request_in;
|
||||
u64 arfs_request_out;
|
||||
u64 arfs_expired;
|
||||
u64 arfs_err;
|
||||
#endif
|
||||
u64 recover;
|
||||
#ifdef CONFIG_PAGE_POOL_STATS
|
||||
u64 pp_alloc_fast;
|
||||
|
|
|
|||
|
|
@ -16,8 +16,7 @@ mlx5_esw_get_port_parent_id(struct mlx5_core_dev *dev, struct netdev_phys_item_i
|
|||
|
||||
static bool mlx5_esw_devlink_port_supported(struct mlx5_eswitch *esw, u16 vport_num)
|
||||
{
|
||||
return vport_num == MLX5_VPORT_UPLINK ||
|
||||
(mlx5_core_is_ecpf(esw->dev) && vport_num == MLX5_VPORT_PF) ||
|
||||
return (mlx5_core_is_ecpf(esw->dev) && vport_num == MLX5_VPORT_PF) ||
|
||||
mlx5_eswitch_is_vf_vport(esw, vport_num) ||
|
||||
mlx5_core_is_ec_vf_vport(esw->dev, vport_num);
|
||||
}
|
||||
|
|
@ -25,7 +24,6 @@ static bool mlx5_esw_devlink_port_supported(struct mlx5_eswitch *esw, u16 vport_
|
|||
static struct devlink_port *mlx5_esw_dl_port_alloc(struct mlx5_eswitch *esw, u16 vport_num)
|
||||
{
|
||||
struct mlx5_core_dev *dev = esw->dev;
|
||||
struct devlink_port_attrs attrs = {};
|
||||
struct netdev_phys_item_id ppid = {};
|
||||
struct devlink_port *dl_port;
|
||||
u32 controller_num = 0;
|
||||
|
|
@ -42,13 +40,7 @@ static struct devlink_port *mlx5_esw_dl_port_alloc(struct mlx5_eswitch *esw, u16
|
|||
if (external)
|
||||
controller_num = dev->priv.eswitch->offloads.host_number + 1;
|
||||
|
||||
if (vport_num == MLX5_VPORT_UPLINK) {
|
||||
attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL;
|
||||
attrs.phys.port_number = pfnum;
|
||||
memcpy(attrs.switch_id.id, ppid.id, ppid.id_len);
|
||||
attrs.switch_id.id_len = ppid.id_len;
|
||||
devlink_port_attrs_set(dl_port, &attrs);
|
||||
} else if (vport_num == MLX5_VPORT_PF) {
|
||||
if (vport_num == MLX5_VPORT_PF) {
|
||||
memcpy(dl_port->attrs.switch_id.id, ppid.id, ppid.id_len);
|
||||
dl_port->attrs.switch_id.id_len = ppid.id_len;
|
||||
devlink_port_attrs_pci_pf_set(dl_port, controller_num, pfnum, external);
|
||||
|
|
@ -71,7 +63,7 @@ static void mlx5_esw_dl_port_free(struct devlink_port *dl_port)
|
|||
kfree(dl_port);
|
||||
}
|
||||
|
||||
static const struct devlink_port_ops mlx5_esw_dl_port_ops = {
|
||||
static const struct devlink_port_ops mlx5_esw_pf_vf_dl_port_ops = {
|
||||
.port_fn_hw_addr_get = mlx5_devlink_port_fn_hw_addr_get,
|
||||
.port_fn_hw_addr_set = mlx5_devlink_port_fn_hw_addr_set,
|
||||
.port_fn_roce_get = mlx5_devlink_port_fn_roce_get,
|
||||
|
|
@ -103,7 +95,7 @@ int mlx5_esw_offloads_devlink_port_register(struct mlx5_eswitch *esw, u16 vport_
|
|||
devlink = priv_to_devlink(dev);
|
||||
dl_port_index = mlx5_esw_vport_to_devlink_port_index(dev, vport_num);
|
||||
err = devl_port_register_with_ops(devlink, dl_port, dl_port_index,
|
||||
&mlx5_esw_dl_port_ops);
|
||||
&mlx5_esw_pf_vf_dl_port_ops);
|
||||
if (err)
|
||||
goto reg_err;
|
||||
|
||||
|
|
|
|||
|
|
@ -316,7 +316,7 @@ void mlx5_esw_ipsec_restore_dest_uplink(struct mlx5_core_dev *mdev)
|
|||
err = mlx5_esw_ipsec_modify_flow_dests(esw, flow);
|
||||
if (err)
|
||||
mlx5_core_warn_once(mdev,
|
||||
"Faided to modify flow dests for IPsec");
|
||||
"Failed to modify flow dests for IPsec");
|
||||
}
|
||||
rhashtable_walk_stop(&iter);
|
||||
rhashtable_walk_exit(&iter);
|
||||
|
|
|
|||
|
|
@ -2542,11 +2542,9 @@ int mlx5_esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
|
|||
if (esw->mode != MLX5_ESWITCH_OFFLOADS)
|
||||
return 0;
|
||||
|
||||
if (vport_num != MLX5_VPORT_UPLINK) {
|
||||
err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = mlx5_esw_offloads_rep_load(esw, vport_num);
|
||||
if (err)
|
||||
|
|
@ -2554,8 +2552,7 @@ int mlx5_esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
|
|||
return err;
|
||||
|
||||
load_err:
|
||||
if (vport_num != MLX5_VPORT_UPLINK)
|
||||
mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
|
||||
mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
|
||||
return err;
|
||||
}
|
||||
|
||||
|
|
@ -2566,8 +2563,7 @@ void mlx5_esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
|
|||
|
||||
mlx5_esw_offloads_rep_unload(esw, vport_num);
|
||||
|
||||
if (vport_num != MLX5_VPORT_UPLINK)
|
||||
mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
|
||||
mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
|
||||
}
|
||||
|
||||
static int esw_set_slave_root_fdb(struct mlx5_core_dev *master,
|
||||
|
|
@ -3471,7 +3467,7 @@ int esw_offloads_enable(struct mlx5_eswitch *esw)
|
|||
vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
|
||||
|
||||
/* Uplink vport rep must load first. */
|
||||
err = mlx5_esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
|
||||
err = mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK);
|
||||
if (err)
|
||||
goto err_uplink;
|
||||
|
||||
|
|
@ -3482,7 +3478,7 @@ int esw_offloads_enable(struct mlx5_eswitch *esw)
|
|||
return 0;
|
||||
|
||||
err_vports:
|
||||
mlx5_esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
|
||||
mlx5_esw_offloads_rep_unload(esw, MLX5_VPORT_UPLINK);
|
||||
err_uplink:
|
||||
esw_offloads_steering_cleanup(esw);
|
||||
err_steering_init:
|
||||
|
|
@ -3520,7 +3516,7 @@ static int esw_offloads_stop(struct mlx5_eswitch *esw,
|
|||
void esw_offloads_disable(struct mlx5_eswitch *esw)
|
||||
{
|
||||
mlx5_eswitch_disable_pf_vf_vports(esw);
|
||||
mlx5_esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
|
||||
mlx5_esw_offloads_rep_unload(esw, MLX5_VPORT_UPLINK);
|
||||
esw_set_passing_vport_metadata(esw, false);
|
||||
esw_offloads_steering_cleanup(esw);
|
||||
mapping_destroy(esw->offloads.reg_c0_obj_pool);
|
||||
|
|
|
|||
|
|
@ -49,20 +49,6 @@ enum {
|
|||
MAX_MISSES = 3,
|
||||
};
|
||||
|
||||
enum {
|
||||
MLX5_HEALTH_SYNDR_FW_ERR = 0x1,
|
||||
MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7,
|
||||
MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8,
|
||||
MLX5_HEALTH_SYNDR_CRC_ERR = 0x9,
|
||||
MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa,
|
||||
MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb,
|
||||
MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc,
|
||||
MLX5_HEALTH_SYNDR_EQ_ERR = 0xd,
|
||||
MLX5_HEALTH_SYNDR_EQ_INV = 0xe,
|
||||
MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf,
|
||||
MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10
|
||||
};
|
||||
|
||||
enum {
|
||||
MLX5_DROP_HEALTH_WORK,
|
||||
};
|
||||
|
|
@ -357,27 +343,27 @@ static int mlx5_health_try_recover(struct mlx5_core_dev *dev)
|
|||
static const char *hsynd_str(u8 synd)
|
||||
{
|
||||
switch (synd) {
|
||||
case MLX5_HEALTH_SYNDR_FW_ERR:
|
||||
case MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR:
|
||||
return "firmware internal error";
|
||||
case MLX5_HEALTH_SYNDR_IRISC_ERR:
|
||||
case MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC:
|
||||
return "irisc not responding";
|
||||
case MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR:
|
||||
case MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR:
|
||||
return "unrecoverable hardware error";
|
||||
case MLX5_HEALTH_SYNDR_CRC_ERR:
|
||||
case MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR:
|
||||
return "firmware CRC error";
|
||||
case MLX5_HEALTH_SYNDR_FETCH_PCI_ERR:
|
||||
case MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR:
|
||||
return "ICM fetch PCI error";
|
||||
case MLX5_HEALTH_SYNDR_HW_FTL_ERR:
|
||||
case MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR:
|
||||
return "HW fatal error\n";
|
||||
case MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR:
|
||||
case MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN:
|
||||
return "async EQ buffer overrun";
|
||||
case MLX5_HEALTH_SYNDR_EQ_ERR:
|
||||
case MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR:
|
||||
return "EQ error";
|
||||
case MLX5_HEALTH_SYNDR_EQ_INV:
|
||||
case MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV:
|
||||
return "Invalid EQ referenced";
|
||||
case MLX5_HEALTH_SYNDR_FFSER_ERR:
|
||||
case MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR:
|
||||
return "FFSER error";
|
||||
case MLX5_HEALTH_SYNDR_HIGH_TEMP:
|
||||
case MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR:
|
||||
return "High temperature";
|
||||
default:
|
||||
return "unrecognized error";
|
||||
|
|
|
|||
|
|
@ -256,14 +256,15 @@ int mlx5_devcom_send_event(struct mlx5_devcom_comp_dev *devcom,
|
|||
int event, int rollback_event,
|
||||
void *event_data)
|
||||
{
|
||||
struct mlx5_devcom_comp *comp = devcom->comp;
|
||||
struct mlx5_devcom_comp_dev *pos;
|
||||
struct mlx5_devcom_comp *comp;
|
||||
int err = 0;
|
||||
void *data;
|
||||
|
||||
if (IS_ERR_OR_NULL(devcom))
|
||||
return -ENODEV;
|
||||
|
||||
comp = devcom->comp;
|
||||
down_write(&comp->sem);
|
||||
list_for_each_entry(pos, &comp->comp_dev_list_head, list) {
|
||||
data = rcu_dereference_protected(pos->data, lockdep_is_held(&comp->sem));
|
||||
|
|
|
|||
|
|
@ -259,8 +259,11 @@ struct mlx5_irq *mlx5_irq_alloc(struct mlx5_irq_pool *pool, int i,
|
|||
int err;
|
||||
|
||||
irq = kzalloc(sizeof(*irq), GFP_KERNEL);
|
||||
if (!irq)
|
||||
if (!irq || !zalloc_cpumask_var(&irq->mask, GFP_KERNEL)) {
|
||||
kfree(irq);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
if (!i || !pci_msix_can_alloc_dyn(dev->pdev)) {
|
||||
/* The vector at index 0 is always statically allocated. If
|
||||
* dynamic irq is not supported all vectors are statically
|
||||
|
|
@ -297,11 +300,7 @@ struct mlx5_irq *mlx5_irq_alloc(struct mlx5_irq_pool *pool, int i,
|
|||
mlx5_core_err(dev, "Failed to request irq. err = %d\n", err);
|
||||
goto err_req_irq;
|
||||
}
|
||||
if (!zalloc_cpumask_var(&irq->mask, GFP_KERNEL)) {
|
||||
mlx5_core_warn(dev, "zalloc_cpumask_var failed\n");
|
||||
err = -ENOMEM;
|
||||
goto err_cpumask;
|
||||
}
|
||||
|
||||
if (af_desc) {
|
||||
cpumask_copy(irq->mask, &af_desc->mask);
|
||||
irq_set_affinity_and_hint(irq->map.virq, irq->mask);
|
||||
|
|
@ -319,8 +318,6 @@ struct mlx5_irq *mlx5_irq_alloc(struct mlx5_irq_pool *pool, int i,
|
|||
err_xa:
|
||||
if (af_desc)
|
||||
irq_update_affinity_hint(irq->map.virq, NULL);
|
||||
free_cpumask_var(irq->mask);
|
||||
err_cpumask:
|
||||
free_irq(irq->map.virq, &irq->nh);
|
||||
err_req_irq:
|
||||
#ifdef CONFIG_RFS_ACCEL
|
||||
|
|
@ -333,6 +330,7 @@ struct mlx5_irq *mlx5_irq_alloc(struct mlx5_irq_pool *pool, int i,
|
|||
if (i && pci_msix_can_alloc_dyn(dev->pdev))
|
||||
pci_msix_free_irq(dev->pdev, irq->map);
|
||||
err_alloc_irq:
|
||||
free_cpumask_var(irq->mask);
|
||||
kfree(irq);
|
||||
return ERR_PTR(err);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1422,7 +1422,6 @@ dr_action_create_reformat_action(struct mlx5dr_domain *dmn,
|
|||
case DR_ACTION_TYP_TNL_L3_TO_L2:
|
||||
{
|
||||
u8 *hw_actions;
|
||||
int ret;
|
||||
|
||||
hw_actions = kzalloc(DR_ACTION_CACHE_LINE_SIZE, GFP_KERNEL);
|
||||
if (!hw_actions)
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@ struct dr_qp_init_attr {
|
|||
u32 cqn;
|
||||
u32 pdn;
|
||||
u32 max_send_wr;
|
||||
u32 max_send_sge;
|
||||
struct mlx5_uars_page *uar;
|
||||
u8 isolate_vl_tc:1;
|
||||
};
|
||||
|
|
@ -246,6 +247,37 @@ static int dr_poll_cq(struct mlx5dr_cq *dr_cq, int ne)
|
|||
return err == CQ_POLL_ERR ? err : npolled;
|
||||
}
|
||||
|
||||
static int dr_qp_get_args_update_send_wqe_size(struct dr_qp_init_attr *attr)
|
||||
{
|
||||
return roundup_pow_of_two(sizeof(struct mlx5_wqe_ctrl_seg) +
|
||||
sizeof(struct mlx5_wqe_flow_update_ctrl_seg) +
|
||||
sizeof(struct mlx5_wqe_header_modify_argument_update_seg));
|
||||
}
|
||||
|
||||
/* We calculate for specific RC QP with the required functionality */
|
||||
static int dr_qp_calc_rc_send_wqe(struct dr_qp_init_attr *attr)
|
||||
{
|
||||
int update_arg_size;
|
||||
int inl_size = 0;
|
||||
int tot_size;
|
||||
int size;
|
||||
|
||||
update_arg_size = dr_qp_get_args_update_send_wqe_size(attr);
|
||||
|
||||
size = sizeof(struct mlx5_wqe_ctrl_seg) +
|
||||
sizeof(struct mlx5_wqe_raddr_seg);
|
||||
inl_size = size + ALIGN(sizeof(struct mlx5_wqe_inline_seg) +
|
||||
DR_STE_SIZE, 16);
|
||||
|
||||
size += attr->max_send_sge * sizeof(struct mlx5_wqe_data_seg);
|
||||
|
||||
size = max(size, update_arg_size);
|
||||
|
||||
tot_size = max(size, inl_size);
|
||||
|
||||
return ALIGN(tot_size, MLX5_SEND_WQE_BB);
|
||||
}
|
||||
|
||||
static struct mlx5dr_qp *dr_create_rc_qp(struct mlx5_core_dev *mdev,
|
||||
struct dr_qp_init_attr *attr)
|
||||
{
|
||||
|
|
@ -253,6 +285,7 @@ static struct mlx5dr_qp *dr_create_rc_qp(struct mlx5_core_dev *mdev,
|
|||
u32 temp_qpc[MLX5_ST_SZ_DW(qpc)] = {};
|
||||
struct mlx5_wq_param wqp;
|
||||
struct mlx5dr_qp *dr_qp;
|
||||
int wqe_size;
|
||||
int inlen;
|
||||
void *qpc;
|
||||
void *in;
|
||||
|
|
@ -332,6 +365,15 @@ static struct mlx5dr_qp *dr_create_rc_qp(struct mlx5_core_dev *mdev,
|
|||
if (err)
|
||||
goto err_in;
|
||||
dr_qp->uar = attr->uar;
|
||||
wqe_size = dr_qp_calc_rc_send_wqe(attr);
|
||||
dr_qp->max_inline_data = min(wqe_size -
|
||||
(sizeof(struct mlx5_wqe_ctrl_seg) +
|
||||
sizeof(struct mlx5_wqe_raddr_seg) +
|
||||
sizeof(struct mlx5_wqe_inline_seg)),
|
||||
(2 * MLX5_SEND_WQE_BB -
|
||||
(sizeof(struct mlx5_wqe_ctrl_seg) +
|
||||
sizeof(struct mlx5_wqe_raddr_seg) +
|
||||
sizeof(struct mlx5_wqe_inline_seg))));
|
||||
|
||||
return dr_qp;
|
||||
|
||||
|
|
@ -395,8 +437,48 @@ dr_rdma_handle_flow_access_arg_segments(struct mlx5_wqe_ctrl_seg *wq_ctrl,
|
|||
MLX5_SEND_WQE_DS;
|
||||
}
|
||||
|
||||
static int dr_set_data_inl_seg(struct mlx5dr_qp *dr_qp,
|
||||
struct dr_data_seg *data_seg, void *wqe)
|
||||
{
|
||||
int inline_header_size = sizeof(struct mlx5_wqe_ctrl_seg) +
|
||||
sizeof(struct mlx5_wqe_raddr_seg) +
|
||||
sizeof(struct mlx5_wqe_inline_seg);
|
||||
struct mlx5_wqe_inline_seg *seg;
|
||||
int left_space;
|
||||
int inl = 0;
|
||||
void *addr;
|
||||
int len;
|
||||
int idx;
|
||||
|
||||
seg = wqe;
|
||||
wqe += sizeof(*seg);
|
||||
addr = (void *)(unsigned long)(data_seg->addr);
|
||||
len = data_seg->length;
|
||||
inl += len;
|
||||
left_space = MLX5_SEND_WQE_BB - inline_header_size;
|
||||
|
||||
if (likely(len > left_space)) {
|
||||
memcpy(wqe, addr, left_space);
|
||||
len -= left_space;
|
||||
addr += left_space;
|
||||
idx = (dr_qp->sq.pc + 1) & (dr_qp->sq.wqe_cnt - 1);
|
||||
wqe = mlx5_wq_cyc_get_wqe(&dr_qp->wq.sq, idx);
|
||||
}
|
||||
|
||||
memcpy(wqe, addr, len);
|
||||
|
||||
if (likely(inl)) {
|
||||
seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
|
||||
return DIV_ROUND_UP(inl + sizeof(seg->byte_count),
|
||||
MLX5_SEND_WQE_DS);
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
dr_rdma_handle_icm_write_segments(struct mlx5_wqe_ctrl_seg *wq_ctrl,
|
||||
dr_rdma_handle_icm_write_segments(struct mlx5dr_qp *dr_qp,
|
||||
struct mlx5_wqe_ctrl_seg *wq_ctrl,
|
||||
u64 remote_addr,
|
||||
u32 rkey,
|
||||
struct dr_data_seg *data_seg,
|
||||
|
|
@ -412,15 +494,17 @@ dr_rdma_handle_icm_write_segments(struct mlx5_wqe_ctrl_seg *wq_ctrl,
|
|||
wq_raddr->reserved = 0;
|
||||
|
||||
wq_dseg = (void *)(wq_raddr + 1);
|
||||
/* WQE ctrl segment + WQE remote addr segment */
|
||||
*size = (sizeof(*wq_ctrl) + sizeof(*wq_raddr)) / MLX5_SEND_WQE_DS;
|
||||
|
||||
wq_dseg->byte_count = cpu_to_be32(data_seg->length);
|
||||
wq_dseg->lkey = cpu_to_be32(data_seg->lkey);
|
||||
wq_dseg->addr = cpu_to_be64(data_seg->addr);
|
||||
|
||||
*size = (sizeof(*wq_ctrl) + /* WQE ctrl segment */
|
||||
sizeof(*wq_dseg) + /* WQE data segment */
|
||||
sizeof(*wq_raddr)) / /* WQE remote addr segment */
|
||||
MLX5_SEND_WQE_DS;
|
||||
if (data_seg->send_flags & IB_SEND_INLINE) {
|
||||
*size += dr_set_data_inl_seg(dr_qp, data_seg, wq_dseg);
|
||||
} else {
|
||||
wq_dseg->byte_count = cpu_to_be32(data_seg->length);
|
||||
wq_dseg->lkey = cpu_to_be32(data_seg->lkey);
|
||||
wq_dseg->addr = cpu_to_be64(data_seg->addr);
|
||||
*size += sizeof(*wq_dseg) / MLX5_SEND_WQE_DS; /* WQE data segment */
|
||||
}
|
||||
}
|
||||
|
||||
static void dr_set_ctrl_seg(struct mlx5_wqe_ctrl_seg *wq_ctrl,
|
||||
|
|
@ -451,7 +535,7 @@ static void dr_rdma_segments(struct mlx5dr_qp *dr_qp, u64 remote_addr,
|
|||
switch (opcode) {
|
||||
case MLX5_OPCODE_RDMA_READ:
|
||||
case MLX5_OPCODE_RDMA_WRITE:
|
||||
dr_rdma_handle_icm_write_segments(wq_ctrl, remote_addr,
|
||||
dr_rdma_handle_icm_write_segments(dr_qp, wq_ctrl, remote_addr,
|
||||
rkey, data_seg, &size);
|
||||
break;
|
||||
case MLX5_OPCODE_FLOW_TBL_ACCESS:
|
||||
|
|
@ -572,7 +656,7 @@ static void dr_fill_write_args_segs(struct mlx5dr_send_ring *send_ring,
|
|||
if (send_ring->pending_wqe % send_ring->signal_th == 0)
|
||||
send_info->write.send_flags |= IB_SEND_SIGNALED;
|
||||
else
|
||||
send_info->write.send_flags = 0;
|
||||
send_info->write.send_flags &= ~IB_SEND_SIGNALED;
|
||||
}
|
||||
|
||||
static void dr_fill_write_icm_segs(struct mlx5dr_domain *dmn,
|
||||
|
|
@ -596,9 +680,13 @@ static void dr_fill_write_icm_segs(struct mlx5dr_domain *dmn,
|
|||
}
|
||||
|
||||
send_ring->pending_wqe++;
|
||||
if (!send_info->write.lkey)
|
||||
send_info->write.send_flags |= IB_SEND_INLINE;
|
||||
|
||||
if (send_ring->pending_wqe % send_ring->signal_th == 0)
|
||||
send_info->write.send_flags |= IB_SEND_SIGNALED;
|
||||
else
|
||||
send_info->write.send_flags &= ~IB_SEND_SIGNALED;
|
||||
|
||||
send_ring->pending_wqe++;
|
||||
send_info->read.length = send_info->write.length;
|
||||
|
|
@ -608,9 +696,9 @@ static void dr_fill_write_icm_segs(struct mlx5dr_domain *dmn,
|
|||
send_info->read.lkey = send_ring->sync_mr->mkey;
|
||||
|
||||
if (send_ring->pending_wqe % send_ring->signal_th == 0)
|
||||
send_info->read.send_flags = IB_SEND_SIGNALED;
|
||||
send_info->read.send_flags |= IB_SEND_SIGNALED;
|
||||
else
|
||||
send_info->read.send_flags = 0;
|
||||
send_info->read.send_flags &= ~IB_SEND_SIGNALED;
|
||||
}
|
||||
|
||||
static void dr_fill_data_segs(struct mlx5dr_domain *dmn,
|
||||
|
|
@ -1257,6 +1345,7 @@ int mlx5dr_send_ring_alloc(struct mlx5dr_domain *dmn)
|
|||
dmn->send_ring->cq->qp = dmn->send_ring->qp;
|
||||
|
||||
dmn->info.max_send_wr = QUEUE_SIZE;
|
||||
init_attr.max_send_sge = 1;
|
||||
dmn->info.max_inline_size = min(dmn->send_ring->qp->max_inline_data,
|
||||
DR_STE_SIZE);
|
||||
|
||||
|
|
|
|||
|
|
@ -336,7 +336,7 @@ static int mlx5_cmd_dr_create_fte(struct mlx5_flow_root_namespace *ns,
|
|||
if (fte->action.pkt_reformat->owner == MLX5_FLOW_RESOURCE_OWNER_FW) {
|
||||
err = -EINVAL;
|
||||
mlx5dr_err(domain, "FW-owned reformat can't be used in SW rule\n");
|
||||
goto free_actions;
|
||||
goto free_actions;
|
||||
}
|
||||
|
||||
is_decap = fte->action.pkt_reformat->reformat_type ==
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user