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drm/amd/display: Cache edp config in dc link

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Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wenjing Liu 2017-08-15 19:10:14 -04:00 committed by Alex Deucher
parent 5e9a81b2c4
commit 9799624ac2
2 changed files with 3 additions and 1 deletions
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2
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
View File

@ -2258,6 +2258,8 @@ static void retrieve_link_cap(struct dc_link *link)
DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
link->dpcd_caps.panel_mode_edp =
edp_config_cap.bits.ALT_SCRAMBLER_RESET;
link->dpcd_caps.dpcd_display_control_capable =
edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
link->test_pattern_enabled = false;
link->compliance_test_state.raw = 0;

2
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -760,6 +760,7 @@ struct dpcd_caps {
bool allow_invalid_MSA_timing_param;
bool panel_mode_edp;
bool dpcd_display_control_capable;
};
struct dc_link_status {
@ -834,7 +835,6 @@ struct dc_link {
struct dpcd_caps dpcd_caps;
unsigned short chip_caps;
unsigned int dpcd_sink_count;
enum edp_revision edp_revision;
bool psr_enabled;