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ARM: dts: uniphier: Add ahci controller nodes for PXs2

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Add ahci core controller and glue layer nodes including reset-controller
and sata-phy.

This supports for PXs2 and the boards without PXs2 vodka board that
doesn't implement any SATA connectors.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042249.4708-8-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Kunihiko Hayashi 2022-09-13 13:22:47 +09:00 committed by Arnd Bergmann
parent d5566de59b
commit 97837505f0
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GPG Key ID: 9A6C79EFE60018D9
2 changed files with 44 additions and 0 deletions
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4
arch/arm/boot/dts/uniphier-pxs2-gentil.dts
View File

@ -99,3 +99,7 @@ &usb0 {
&usb1 {
status = "okay";
};
&ahci {
status = "okay";
};

40
arch/arm/boot/dts/uniphier-pxs2.dtsi
View File

@ -599,6 +599,46 @@ mdio: mdio {
};
};
ahci: sata@65600000 {
compatible = "socionext,uniphier-pxs2-ahci",
"generic-ahci";
status = "disabled";
reg = <0x65600000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_clk 28>;
resets = <&sys_rst 28>, <&ahci_rst 0>;
ports-implemented = <1>;
phys = <&ahci_phy>;
};
sata-controller@65700000 {
compatible = "socionext,uniphier-pxs2-ahci-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65700000 0x100>;
ahci_rst: reset-controller@0 {
compatible = "socionext,uniphier-pxs2-ahci-reset";
reg = <0x0 0x4>;
clock-names = "link";
clocks = <&sys_clk 28>;
reset-names = "link";
resets = <&sys_rst 28>;
#reset-cells = <1>;
};
ahci_phy: sata-phy@10 {
compatible = "socionext,uniphier-pxs2-ahci-phy";
reg = <0x10 0x10>;
clock-names = "link";
clocks = <&sys_clk 28>;
reset-names = "link", "phy";
resets = <&sys_rst 28>, <&sys_rst 30>;
#phy-cells = <0>;
};
};
usb0: usb@65a00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";