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i.MX arm64 device tree changes for 6.19:

Browse Source 
- New board support: Protonic PRT8ML, Toradex SMARC iMX95, Skov Rev.C
   HDMI, i.MX 95 Verdin Evaluation KitPHYTEC phyBOARD-Segin-i.MX91 board,
   Skov i.MX8MP variant
 - A series from Alexander Stein to clean up and improve imx95-tqma9596sa
   board support
 - Add MicIn routing support for mba8mx boards
 - A couple of patch sets from Frank Li to clean up dt-schema warnings
   and add more device support for imx8dxl and imx8qxp boards
 - A series from Ioana Ciornei to add FPGA based GPIO controller and SFP+
   cages for layerscape boards
 - A change from Jan Petrous to add GMAC Ethernet for S32G2 EVB, RDB2 and
   S32G3 RDB3 boards
 - A series from Markus Niebel to improve imx95-tqma9596sa board support
 - A couple of changes from Martin Kepplinger-Novaković to enable cpuidle
   cooling device support for imx8mp
 - A series from Max Krummenacher to clean up todo and add thermal
   support for imx8-apalis board
 - A series from Primoz Fiser to add USB vbus regulators, jtag and
   pwm-fan overlay for imx93-phyboard
 - A couple of series from Richard Zhu to add supports-clkreq property
   and vpcie3v3aux regulator for PCIe M.2 device
 - A series from Stefano Radaelli to add WiFi, BT, PMIC, WM8904 audio,
   and ADS7846 touchscreen support for imx93-var-som
 - A series from Tim Harvey to make some cleanups for imx8mm-venice
   boards
 - A change from Xu Yang to add DDR Perf Monitor support for i.MX94
 - Other small and random changes
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 =QJty
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Merge tag 'imx-dt64-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

i.MX arm64 device tree changes for 6.19:

- New board support: Protonic PRT8ML, Toradex SMARC iMX95, Skov Rev.C
  HDMI, i.MX 95 Verdin Evaluation KitPHYTEC phyBOARD-Segin-i.MX91 board,
  Skov i.MX8MP variant
- A series from Alexander Stein to clean up and improve imx95-tqma9596sa
  board support
- Add MicIn routing support for mba8mx boards
- A couple of patch sets from Frank Li to clean up dt-schema warnings
  and add more device support for imx8dxl and imx8qxp boards
- A series from Ioana Ciornei to add FPGA based GPIO controller and SFP+
  cages for layerscape boards
- A change from Jan Petrous to add GMAC Ethernet for S32G2 EVB, RDB2 and
  S32G3 RDB3 boards
- A series from Markus Niebel to improve imx95-tqma9596sa board support
- A couple of changes from Martin Kepplinger-Novaković to enable cpuidle
  cooling device support for imx8mp
- A series from Max Krummenacher to clean up todo and add thermal
  support for imx8-apalis board
- A series from Primoz Fiser to add USB vbus regulators, jtag and
  pwm-fan overlay for imx93-phyboard
- A couple of series from Richard Zhu to add supports-clkreq property
  and vpcie3v3aux regulator for PCIe M.2 device
- A series from Stefano Radaelli to add WiFi, BT, PMIC, WM8904 audio,
  and ADS7846 touchscreen support for imx93-var-som
- A series from Tim Harvey to make some cleanups for imx8mm-venice
  boards
- A change from Xu Yang to add DDR Perf Monitor support for i.MX94
- Other small and random changes

* tag 'imx-dt64-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (122 commits)
  arm64: dts: freescale: add Toradex SMARC iMX95
  arm64: dts: freescale: tqma9352: Add vcc-supply for spi-nor
  arm64: dts: mb-smarc-2: Add MicIn routing
  arm64: dts: mba8xx: Add MicIn routing
  arm64: dts: mba8mx: Add MicIn routing
  arm64: dts: imx8mp: make 'dsp' node depend on 'aips5'
  arm64: dts: imx8mp: convert 'aips5' to 'aipstz5'
  arm64: dts: imx8mp-skov: add Rev.C HDMI support
  arm64: dts: imx8mp: Add missing LED enumerators for DH electronics i.MX8M Plus DHCOM on PDK2
  arm64: dts: freescale: Add GMAC Ethernet for S32G2 EVB and RDB2 and S32G3 RDB3
  arm64: dts: imx8qm-apalis: add pwm used by the backlight
  arm64: dts: imx95-tqma9596sa-mb-smarc-2: add aliases for SPI
  arm64: dts: imx95-tqma9596sa-mb-smarc-2: remove superfluous line
  arm64: dts: imx95-tqma9596sa-mb-smarc-2: mark LPUART1 as reserved
  arm64: dts: imx95-tqma9596sa-mb-smarc-2: Add MicIn routing
  arm64: dts: imx95-tqma9596sa: add EEPROM pagesize
  arm64: dts: imx95-tqma9596sa: whitespace fixes
  arm64: dts: imx95-tqma9596sa: add gpio bus recovery for i2c
  arm64: dts: imx95-tqma9596sa: remove superfluous pinmux for usdhci
  arm64: dts: imx95-tqma9596sa: remove superfluous pinmux for i2c
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-11-21 17:10:41 +01:00
commit 976e33268c
91 changed files with 5687 additions and 567 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
arch/arm64/boot/dts/freescale/Makefile
View File

@ -136,12 +136,18 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb
imx8mm-phyboard-polis-peb-av-10-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-av-10.dtbo
imx8mm-phyboard-polis-peb-av-10-etml1010g3dra-dtbs += imx8mm-phyboard-polis-rdk.dtb \
imx8mm-phyboard-polis-peb-av-10-etml1010g3dra.dtbo
imx8mm-phyboard-polis-peb-av-10-ph128800t006-dtbs += imx8mm-phyboard-polis-rdk.dtb \
imx8mm-phyboard-polis-peb-av-10-ph128800t006.dtbo
imx8mm-phyboard-polis-peb-eval-01-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-eval-01.dtbo
imx8mm-phycore-no-eth-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-no-eth.dtbo
imx8mm-phycore-no-spiflash-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-no-spiflash.dtbo
imx8mm-phycore-rpmsg-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-rpmsg.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-av-10.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-av-10-etml1010g3dra.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-av-10-ph128800t006.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-eval-01.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-no-eth.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-no-spiflash.dtb
@ -226,14 +232,32 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-smarc-universal-board.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
imx8mp-phyboard-pollux-etml1010g3dra-dtbs += imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-phyboard-pollux-etml1010g3dra.dtbo
imx8mp-phyboard-pollux-peb-av-10-dtbs += imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-phyboard-pollux-peb-av-10.dtbo
imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra-dtbs += imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtbo
imx8mp-phyboard-pollux-peb-av-10-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtbo
imx8mp-phyboard-pollux-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-phyboard-pollux-ph128800t006.dtbo
imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-etml1010g3dra.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-ph128800t006.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-prt8ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-basic.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-bd500.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-tian-g07017.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-jutouch-jt101tm023.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-toradex-smarc-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314.dtb
@ -344,6 +368,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb
@ -356,11 +381,15 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
imx93-phyboard-nash-jtag-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-jtag.dtbo
imx93-phyboard-nash-peb-wlbt-07-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-peb-wlbt-07.dtbo
imx93-phyboard-nash-pwm-fan-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-pwm-fan.dtbo
imx93-phyboard-segin-peb-eval-01-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-eval-01.dtbo
imx93-phyboard-segin-peb-wlbt-05-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-wlbt-05.dtbo
imx93-phycore-rpmsg-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-segin.dtb imx93-phycore-rpmsg.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-jtag.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-peb-wlbt-07.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-pwm-fan.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-eval-01.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-wlbt-05.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-rpmsg.dtb
@ -373,6 +402,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb
imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo
@ -382,6 +412,8 @@ imx95-19x19-evk-pcie1-ep-dtbs += imx95-19x19-evk.dtb imx-pcie1-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-pcie0-ep.dtb imx95-19x19-evk-pcie1-ep.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-libra-rdk-fpsc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-verdin-evk.dtb
imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo
imx8mm-kontron-bl-lte-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-bl-lte.dtbo

3
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View File

@ -493,10 +493,11 @@ QORIQ_CLK_PLL_DIV(4)>,
};
usb0: usb@2f00000 {
compatible = "snps,dwc3";
compatible = "fsl,ls1012a-dwc3", "fsl,ls1028a-dwc3";
reg = <0x0 0x2f00000 0x0 0x10000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
dma-coherent;
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;

8
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -613,9 +613,11 @@ gpio3: gpio@2320000 {
};
usb0: usb@3100000 {
compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
compatible = "fsl,ls1028a-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu 1>;
dma-coherent;
snps,dis_rxdet_inp3_quirk;
snps,quirk-frame-length-adjustment = <0x20>;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
@ -623,9 +625,11 @@ usb0: usb@3100000 {
};
usb1: usb@3110000 {
compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
compatible = "fsl,ls1028a-dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu 2>;
dma-coherent;
snps,dis_rxdet_inp3_quirk;
snps,quirk-frame-length-adjustment = <0x20>;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;

9
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -833,10 +833,11 @@ aux_bus: bus {
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
usb0: usb@2f00000 {
compatible = "snps,dwc3";
compatible = "fsl,ls1043a-dwc3", "fsl,ls1028a-dwc3";
reg = <0x0 0x2f00000 0x0 0x10000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
dma-coherent;
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
usb3-lpm-capable;
@ -845,10 +846,11 @@ usb0: usb@2f00000 {
};
usb1: usb@3000000 {
compatible = "snps,dwc3";
compatible = "fsl,ls1043a-dwc3", "fsl,ls1028a-dwc3";
reg = <0x0 0x3000000 0x0 0x10000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
dma-coherent;
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
usb3-lpm-capable;
@ -857,10 +859,11 @@ usb1: usb@3000000 {
};
usb2: usb@3100000 {
compatible = "snps,dwc3";
compatible = "fsl,ls1043a-dwc3", "fsl,ls1028a-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
dma-coherent;
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
usb3-lpm-capable;

52
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
View File

@ -42,6 +42,21 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
sfp1: sfp-1 {
compatible = "sff,sfp";
i2c-bus = <&sfp1_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&stat_pres2 6 GPIO_ACTIVE_LOW>;
};
sfp2: sfp-2 {
compatible = "sff,sfp";
i2c-bus = <&sfp2_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&stat_pres2 7 GPIO_ACTIVE_LOW>;
};
};
&dspi {
@ -139,6 +154,31 @@ temp-sensor@4c {
reg = <0x4c>;
};
};
i2c@7 {
reg = <0x7>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux@76 {
compatible = "nxp,pca9547";
reg = <0x76>;
#address-cells = <1>;
#size-cells = <0>;
sfp1_i2c: i2c@6 {
reg = <0x6>;
#address-cells = <1>;
#size-cells = <0>;
};
sfp2_i2c: i2c@7 {
reg = <0x7>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
};
};
@ -166,8 +206,20 @@ nand@1,0 {
fpga: board-control@2,0 {
compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2 0x0 0x0000100>;
ranges = <0 2 0 0x100>;
stat_pres2: gpio@c {
compatible = "fsl,ls1046aqds-fpga-gpio-stat-pres2";
reg = <0xc 1>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"SLOT1", "SLOT2", "SLOT3", "SLOT4", "SLOT5", "SLOT6",
"SFP1_MOD_DEF", "SFP2_MOD_DEF";
};
};
};

9
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -749,10 +749,11 @@ aux_bus: bus {
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
usb0: usb@2f00000 {
compatible = "snps,dwc3";
compatible = "fsl,ls1046a-dwc3", "fsl,ls1028a-dwc3";
reg = <0x0 0x2f00000 0x0 0x10000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
dma-coherent;
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
@ -760,10 +761,11 @@ usb0: usb@2f00000 {
};
usb1: usb@3000000 {
compatible = "snps,dwc3";
compatible = "fsl,ls1046a-dwc3", "fsl,ls1028a-dwc3";
reg = <0x0 0x3000000 0x0 0x10000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
dma-coherent;
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
@ -771,10 +773,11 @@ usb1: usb@3000000 {
};
usb2: usb@3100000 {
compatible = "snps,dwc3";
compatible = "fsl,ls1046a-dwc3", "fsl,ls1028a-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
dma-coherent;
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;

4
arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts
View File

@ -253,6 +253,10 @@ usbhub: usb-hub@2d {
reg = <0x2d>;
};
uc: board-controller@7e {
compatible = "traverse,ten64-controller";
reg = <0x7e>;
};
};
&i2c2 {

8
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View File

@ -489,10 +489,12 @@ esdhc: mmc@2140000 {
};
usb0: usb@3100000 {
compatible = "snps,dwc3";
compatible = "fsl,ls1088a-dwc3", "fsl,ls1028a-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
iommus = <&smmu 1>;
dma-coherent;
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
@ -500,10 +502,12 @@ usb0: usb@3100000 {
};
usb1: usb@3110000 {
compatible = "snps,dwc3";
compatible = "fsl,ls1088a-dwc3", "fsl,ls1028a-dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
iommus = <&smmu 2>;
dma-coherent;
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;

2
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
View File

@ -6,7 +6,7 @@
/dts-v1/;
#include "fsl-lx2160a.dtsi"
#include "fsl-lx2160a-rev2.dtsi"
/ {
model = "NXP Layerscape LX2160AQDS";

80
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
View File

@ -6,7 +6,7 @@
/dts-v1/;
#include "fsl-lx2160a.dtsi"
#include "fsl-lx2160a-rev2.dtsi"
/ {
model = "NXP Layerscape LX2160ARDB";
@ -31,6 +31,28 @@ sb_3v3: regulator-sb3v3 {
regulator-boot-on;
regulator-always-on;
};
sfp2: sfp-2 {
compatible = "sff,sfp";
i2c-bus = <&sfp2_i2c>;
maximum-power-milliwatt = <2000>;
/* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */
/* tx-disable-gpios = <&sfp2_csr 0 GPIO_ACTIVE_HIGH>; */
los-gpios = <&sfp2_csr 4 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&sfp2_csr 5 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&sfp2_csr 7 GPIO_ACTIVE_LOW>;
};
sfp3: sfp-3 {
compatible = "sff,sfp";
i2c-bus = <&sfp3_i2c>;
maximum-power-milliwatt = <2000>;
/* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */
/* tx-disable-gpios = <&sfp3_csr 0 GPIO_ACTIVE_HIGH>; */
los-gpios = <&sfp3_csr 4 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&sfp3_csr 5 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&sfp3_csr 7 GPIO_ACTIVE_LOW>;
};
};
&crypto {
@ -170,6 +192,37 @@ mt35xu512aba1: flash@1 {
&i2c0 {
status = "okay";
cpld@66 {
compatible = "fsl,lx2160ardb-fpga";
reg = <0x66>;
#address-cells = <1>;
#size-cells = <0>;
sfp2_csr: gpio@19 {
compatible = "fsl,lx2160ardb-fpga-gpio-sfp";
reg = <0x19>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"SFP2_TX_EN", "",
"", "",
"SFP2_RX_LOS", "SFP2_TX_FAULT",
"", "SFP2_MOD_ABS";
};
sfp3_csr: gpio@1a {
compatible = "fsl,lx2160ardb-fpga-gpio-sfp";
reg = <0x1a>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"SFP3_TX_EN", "",
"", "",
"SFP3_RX_LOS", "SFP3_TX_FAULT",
"", "SFP3_MOD_ABS";
};
};
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
@ -205,6 +258,31 @@ temperature-sensor@4d {
vcc-supply = <&sb_3v3>;
};
};
i2c@7 {
reg = <0x7>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux@75 {
compatible = "nxp,pca9547";
reg = <0x75>;
#address-cells = <1>;
#size-cells = <0>;
sfp2_i2c: i2c@4 {
reg = <0x4>;
#address-cells = <1>;
#size-cells = <0>;
};
sfp3_i2c: i2c@5 {
reg = <0x5>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
};
};

8
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@ -1094,24 +1094,28 @@ ftm_alarm0: rtc@2800000 {
};
usb0: usb@3100000 {
compatible = "snps,dwc3";
compatible = "fsl,lx2160a-dwc3", "fsl,ls1028a-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
usb3-lpm-capable;
iommus = <&smmu 1>;
dma-coherent;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
usb1: usb@3110000 {
compatible = "snps,dwc3";
compatible = "fsl,lx2160a-dwc3", "fsl,ls1028a-dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
usb3-lpm-capable;
iommus = <&smmu 2>;
dma-coherent;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";

2
arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
View File

@ -6,7 +6,7 @@
/dts-v1/;
#include "fsl-lx2160a.dtsi"
#include "fsl-lx2160a-rev2.dtsi"
/ {
model = "NXP Layerscape LX2162AQDS";

5
arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi
View File

@ -109,7 +109,10 @@ &pciea {
status = "okay";
};
/* TODO: Apalis BKL1_PWM */
/* Apalis BKL1_PWM */
&pwm_lvds1 {
status = "okay";
};
/* Apalis DAP1 */
&sai1 {

5
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi
View File

@ -196,7 +196,10 @@ &pciea {
status = "okay";
};
/* TODO: Apalis BKL1_PWM */
/* Apalis BKL1_PWM */
&pwm_lvds1 {
status = "okay";
};
/* Apalis DAP1 */
&sai1 {

5
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi
View File

@ -245,7 +245,10 @@ &pciea {
status = "okay";
};
/* TODO: Apalis BKL1_PWM */
/* Apalis BKL1_PWM */
&pwm_lvds1 {
status = "okay";
};
/* Apalis DAP1 */
&sai1 {

51
arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
View File

@ -18,7 +18,7 @@ backlight: backlight {
brightness-levels = <0 45 63 88 119 158 203 255>;
default-brightness-level = <4>;
enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */
/* TODO: hook-up to Apalis BKL1_PWM */
pwms = <&pwm_lvds1 0 6666667 PWM_POLARITY_INVERTED>;
status = "disabled";
};
@ -31,12 +31,6 @@ gpio_fan: gpio-fan {
3000 1>;
};
/* TODO: LVDS Panel */
/* TODO: Shared PCIe/SATA Reference Clock */
/* TODO: PCIe Wi-Fi Reference Clock */
/*
* Power management bus used to control LDO1OUT of the
* second PMIC PF8100. This is used for controlling voltage levels of
@ -83,8 +77,8 @@ reg_module_wifi: regulator-module-wifi {
gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
regulator-name = "wifi_pwrdn_fake_regulator";
regulator-settling-time-us = <100>;
regulator-name = "Wi-Fi_POWER_DOWN"; /* Wi-Fi module PDn */
startup-delay-us = <100>;
};
reg_pcie_switch: regulator-pcie-switch {
@ -232,6 +226,34 @@ sound-spdif {
spdif-out;
};
thermal-zones {
pmic-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
cooling-maps {
cooling_maps_map0: map0 {
trip = <&pmic_alert0>;
};
};
trips {
pmic_alert0: trip0 {
hysteresis = <2000>;
temperature = <110000>;
type = "passive";
};
pmic_crit0: trip1 {
hysteresis = <2000>;
temperature = <125000>;
type = "critical";
};
};
};
};
touchscreen: touchscreen {
compatible = "toradex,vf50-touchscreen";
interrupt-parent = <&lsio_gpio3>;
@ -262,15 +284,15 @@ &asrc0 {
&adc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0>;
vref-supply = <&reg_vref_1v8>;
};
&adc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
vref-supply = <&reg_vref_1v8>;
};
/* TODO: Asynchronous Sample Rate Converter (ASRC) */
&cpu_alert0 {
temperature = <95000>;
};
@ -799,7 +821,10 @@ &phyx2_lpcg {
<&hsio_refa_clk>, <&hsio_per_clk>;
};
/* TODO: Apalis BKL1_PWM */
&pwm_lvds1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm_bkl>;
};
/* Apalis DAP1 */
&sai1 {
@ -841,8 +866,6 @@ &spdif0 {
status = "okay";
};
/* TODO: Thermal Zones */
/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
/* Apalis USBH4 */

6
arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
View File

@ -296,7 +296,8 @@ edma0: dma-controller@591f0000 {
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 20 unused */
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, /* 21 */
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 22 unused */
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; /* 23 unused */
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, /* 23 unused */
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
<&pd IMX_SC_R_DMA_0_CH1>,
<&pd IMX_SC_R_DMA_0_CH2>,
@ -558,7 +559,8 @@ edma1: dma-controller@599f0000 {
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 7 unused */
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* sai5 */
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
<&pd IMX_SC_R_DMA_1_CH1>,
<&pd IMX_SC_R_DMA_1_CH2>,

20
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
View File

@ -77,7 +77,11 @@ usdhc1: mmc@5b010000 {
<&sdhc0_lpcg IMX_LPCG_CLK_5>,
<&sdhc0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <400000000>;
power-domains = <&pd IMX_SC_R_SDHC_0>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
status = "disabled";
};
@ -88,6 +92,8 @@ usdhc2: mmc@5b020000 {
<&sdhc1_lpcg IMX_LPCG_CLK_5>,
<&sdhc1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
power-domains = <&pd IMX_SC_R_SDHC_1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
@ -101,7 +107,11 @@ usdhc3: mmc@5b030000 {
<&sdhc2_lpcg IMX_LPCG_CLK_5>,
<&sdhc2_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
power-domains = <&pd IMX_SC_R_SDHC_2>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
status = "disabled";
};
@ -114,8 +124,9 @@ fec1: ethernet@5b040000 {
clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
<&enet0_lpcg IMX_LPCG_CLK_2>,
<&enet0_lpcg IMX_LPCG_CLK_3>,
<&enet0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
<&enet0_lpcg IMX_LPCG_CLK_0>,
<&enet0_lpcg IMX_LPCG_CLK_1>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
assigned-clock-rates = <250000000>, <125000000>;
@ -134,8 +145,9 @@ fec2: ethernet@5b050000 {
clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
<&enet1_lpcg IMX_LPCG_CLK_2>,
<&enet1_lpcg IMX_LPCG_CLK_3>,
<&enet1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
<&enet1_lpcg IMX_LPCG_CLK_0>,
<&enet0_lpcg IMX_LPCG_CLK_1>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
assigned-clock-rates = <250000000>, <125000000>;

6
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
View File

@ -182,7 +182,8 @@ edma2: dma-controller@5a1f0000 {
<GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
<&pd IMX_SC_R_DMA_2_CH1>,
<&pd IMX_SC_R_DMA_2_CH2>,
@ -466,7 +467,8 @@ edma3: dma-controller@5a9f0000 {
<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
<&pd IMX_SC_R_DMA_3_CH1>,
<&pd IMX_SC_R_DMA_3_CH2>,

14
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
View File

@ -598,6 +598,10 @@ &lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&lsio_mu5 {
@ -649,6 +653,7 @@ &pcie0 {
pinctrl-names = "default";
reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcieb>;
vpcie3v3aux-supply = <&reg_pcieb>;
status = "okay";
};
@ -775,8 +780,10 @@ &usbotg2 {
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1>;
pinctrl-2 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-sd;
no-sdio;
@ -785,12 +792,15 @@ &usdhc1 {
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
max-frequency = <100000000>;
status = "okay";
};

9
arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
View File

@ -101,7 +101,8 @@ &edma0 {
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* gpt0 */
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* gpt1 */
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* gpt2 */
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; /* gpt3 */
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, /* gpt3 */
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
<&pd IMX_SC_R_DMA_0_CH1>,
<&pd IMX_SC_R_DMA_0_CH2>,
@ -145,7 +146,8 @@ &edma2 {
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
};
&edma3 {
@ -156,7 +158,8 @@ &edma3 {
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
};
&flexcan1 {

1
arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
View File

@ -7,6 +7,7 @@
/delete-node/ &fec2;
/delete-node/ &usbotg3;
/delete-node/ &usb3_phy;
/delete-node/ &usb3_lpcg;
/ {
conn_enet0_root_clk: clock-conn-enet0-root {

1
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
View File

@ -542,6 +542,7 @@ &pcie0 {
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
vpcie-supply = <&reg_pcie0>;
supports-clkreq;
status = "okay";
};

44
arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10-etml1010g3dra.dtso Normal file
View File

@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include "imx8mm-phyboard-polis-peb-av-10.dtsi"
&backlight {
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
pwms = <&pwm4 0 50000 0>;
status = "okay";
};
&bridge_out {
ti,lvds-vod-swing-clock-microvolt = <200000 600000>;
ti,lvds-vod-swing-data-microvolt = <200000 600000>;
};
&lcdif {
status = "okay";
};
&mipi_dsi {
status = "okay";
};
&panel {
compatible = "edt,etml1010g3dra";
status = "okay";
};
&pwm4 {
status = "okay";
};
&sn65dsi83 {
status = "okay";
};

44
arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10-ph128800t006.dtso Normal file
View File

@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include "imx8mm-phyboard-polis-peb-av-10.dtsi"
&backlight {
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
pwms = <&pwm4 0 50000 0>;
status = "okay";
};
&bridge_out {
ti,lvds-vod-swing-clock-microvolt = <200000 600000>;
ti,lvds-vod-swing-data-microvolt = <200000 600000>;
};
&lcdif {
status = "okay";
};
&mipi_dsi {
status = "okay";
};
&panel {
compatible = "powertip,ph128800t006-zhc01";
status = "okay";
};
&pwm4 {
status = "okay";
};
&sn65dsi83 {
status = "okay";
};

189
arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtsi Normal file
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@ -0,0 +1,189 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
#include <dt-bindings/clock/imx8mm-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include "imx8mm-pinfunc.h"
&{/} {
backlight: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
power-supply = <&reg_vdd_3v3_s>;
status = "disabled";
};
panel: panel {
backlight = <&backlight>;
power-supply = <&reg_vcc_3v3>;
status = "disabled";
port {
panel_in: endpoint {
remote-endpoint = <&bridge_out>;
};
};
};
reg_sound_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8_Audio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_sound_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3_Analog";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
sound-peb-av-10 {
compatible = "simple-audio-card";
simple-audio-card,name = "snd-peb-av-10";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,mclk-fs = <32>;
simple-audio-card,widgets =
"Line", "Line In",
"Speaker", "Speaker",
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Speaker", "SPOP",
"Speaker", "SPOM",
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1L", "Line In",
"LINE1R", "Line In",
"MIC3R", "Microphone Jack",
"Microphone Jack", "Mic Bias";
simple-audio-card,cpu {
sound-dai = <&sai5>;
};
dailink_master: simple-audio-card,codec {
sound-dai = <&codec>;
clocks = <&clk IMX8MM_CLK_SAI5>;
};
};
};
&bridge_out {
remote-endpoint = <&panel_in>;
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
codec: codec@18 {
compatible = "ti,tlv320aic3007";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tlv320>;
#sound-dai-cells = <0>;
reg = <0x18>;
reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
ai3x-gpio-func = <0xd 0x0>;
ai3x-micbias-vg = <2>;
AVDD-supply = <&reg_sound_3v3>;
IOVDD-supply = <&reg_sound_3v3>;
DRVDD-supply = <&reg_sound_3v3>;
DVDD-supply = <&reg_sound_1v8>;
};
eeprom@57 {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x57>;
vcc-supply = <&reg_vdd_3v3_s>;
};
eeprom@5f {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x5f>;
size = <32>;
vcc-supply = <&reg_vdd_3v3_s>;
};
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
};
&sai5 {
assigned-clocks = <&clk IMX8MM_CLK_SAI5>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;
assigned-clock-rates = <11289600>;
clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
<&clk IMX8MM_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k",
"pll11k";
fsl,sai-mclk-direction-output;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
#sound-dai-cells = <0>;
status = "okay";
};
&iomuxc {
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e2
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e2
>;
};
pinctrl_lcd: lcd0grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x12
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x12
>;
};
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6
>;
};
pinctrl_tlv320: tlv320grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x116
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16
>;
};
};

234
arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso
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@ -1,239 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/imx8mm-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include "imx8mm-pinfunc.h"
&{/} {
backlight: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
default-brightness-level = <6>;
pwms = <&pwm4 0 50000 0>;
power-supply = <&reg_vdd_3v3_s>;
enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
brightness-levels = <0 4 8 16 32 64 128 255>;
};
panel {
compatible = "edt,etml1010g3dra";
backlight = <&backlight>;
power-supply = <&reg_vcc_3v3>;
port {
panel_in: endpoint {
remote-endpoint = <&bridge_out>;
};
};
};
reg_sound_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8_Audio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_sound_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3_Analog";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
sound-peb-av-10 {
compatible = "simple-audio-card";
simple-audio-card,name = "snd-peb-av-10";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,mclk-fs = <32>;
simple-audio-card,widgets =
"Line", "Line In",
"Speaker", "Speaker",
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Speaker", "SPOP",
"Speaker", "SPOM",
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1L", "Line In",
"LINE1R", "Line In",
"MIC3R", "Microphone Jack",
"Microphone Jack", "Mic Bias";
simple-audio-card,cpu {
sound-dai = <&sai5>;
};
dailink_master: simple-audio-card,codec {
sound-dai = <&codec>;
clocks = <&clk IMX8MM_CLK_SAI5>;
};
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
codec: codec@18 {
compatible = "ti,tlv320aic3007";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tlv320>;
#sound-dai-cells = <0>;
reg = <0x18>;
reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
ai3x-gpio-func = <0xd 0x0>;
ai3x-micbias-vg = <2>;
AVDD-supply = <&reg_sound_3v3>;
IOVDD-supply = <&reg_sound_3v3>;
DRVDD-supply = <&reg_sound_3v3>;
DVDD-supply = <&reg_sound_1v8>;
};
eeprom@57 {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x57>;
vcc-supply = <&reg_vdd_3v3_s>;
};
eeprom@5f {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x5f>;
size = <32>;
vcc-supply = <&reg_vdd_3v3_s>;
};
};
&lcdif {
status = "okay";
};
&mipi_dsi {
samsung,esc-clock-frequency = <10000000>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&bridge_in>;
};
};
};
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&sai5 {
assigned-clocks = <&clk IMX8MM_CLK_SAI5>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;
assigned-clock-rates = <11289600>;
clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
<&clk IMX8MM_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k",
"pll11k";
fsl,sai-mclk-direction-output;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
#sound-dai-cells = <0>;
status = "okay";
};
&sn65dsi83 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_in: endpoint {
remote-endpoint = <&dsi_out>;
data-lanes = <1 2 3 4>;
};
};
port@2 {
reg = <2>;
bridge_out: endpoint {
remote-endpoint = <&panel_in>;
ti,lvds-vod-swing-clock-microvolt = <200000 600000>;
ti,lvds-vod-swing-data-microvolt = <200000 600000>;
};
};
};
};
&iomuxc {
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e2
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e2
>;
};
pinctrl_lcd: lcd0grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x12
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x12
>;
};
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6
>;
};
pinctrl_tlv320: tlv320grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x16
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16
>;
};
};
#include "imx8mm-phyboard-polis-peb-av-10.dtsi"

3
arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso
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@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
* Author: Janine Hagemann <j.hagemann@phytec.de>
*/
/dts-v1/;

11
arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
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@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2022 PHYTEC Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
/dts-v1/;
@ -285,6 +284,8 @@ &usbotg1 {
over-current-active-low;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
pinctrl-0 = <&pinctrl_usbotg1>;
pinctrl-names = "default";
srp-disable;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
@ -458,6 +459,12 @@ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x00
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182

28
arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi
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@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2022 PHYTEC Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
#include "imx8mm.dtsi"
@ -288,6 +287,23 @@ sn65dsi83: bridge@2d {
reg = <0x2d>;
vcc-supply = <&reg_vdd_1v8>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_in: endpoint {
remote-endpoint = <&mipi_dsi_out>;
data-lanes = <1 2 3 4>;
};
};
port@2 {
reg = <2>;
bridge_out: endpoint {};
};
};
};
/* EEPROM */
@ -305,6 +321,14 @@ rv3028: rtc@52 {
};
};
&mipi_dsi {
samsung,esc-clock-frequency = <10000000>;
};
&mipi_dsi_out {
remote-endpoint = <&bridge_in>;
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;

2
arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts
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@ -452,7 +452,7 @@ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x00
>;
};

3
arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
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@ -115,6 +115,7 @@ mdio {
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
@ -445,7 +446,7 @@ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x0
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f

11
arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
View File

@ -351,17 +351,6 @@ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190

1
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
View File

@ -253,6 +253,7 @@ mdio {
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

1
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
View File

@ -248,6 +248,7 @@ mdio {
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

33
arch/arm64/boot/dts/freescale/imx8mp-aipstz.h Normal file
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@ -0,0 +1,33 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright 2025 NXP
*/
#ifndef __IMX8MP_AIPSTZ_H
#define __IMX8MP_AIPSTZ_H
/* consumer type - master or peripheral */
#define IMX8MP_AIPSTZ_MASTER 0x0
#define IMX8MP_AIPSTZ_PERIPH 0x1
/* master configuration options */
#define IMX8MP_AIPSTZ_MPL (1 << 0)
#define IMX8MP_AIPSTZ_MTW (1 << 1)
#define IMX8MP_AIPSTZ_MTR (1 << 2)
#define IMX8MP_AIPSTZ_MBW (1 << 3)
/* peripheral configuration options */
#define IMX8MP_AIPSTZ_TP (1 << 0)
#define IMX8MP_AIPSTZ_WP (1 << 1)
#define IMX8MP_AIPSTZ_SP (1 << 2)
#define IMX8MP_AIPSTZ_BW (1 << 3)
/* master ID definitions */
#define IMX8MP_AIPSTZ_EDMA 0 /* AUDIOMIX EDMA */
#define IMX8MP_AIPSTZ_CA53 1 /* Cortex-A53 cluster */
#define IMX8MP_AIPSTZ_SDMA2 3 /* AUDIOMIX SDMA2 */
#define IMX8MP_AIPSTZ_SDMA3 3 /* AUDIOMIX SDMA3 */
#define IMX8MP_AIPSTZ_HIFI4 5 /* HIFI4 DSP */
#define IMX8MP_AIPSTZ_CM7 6 /* Cortex-M7 */
#endif /* __IMX8MP_AIPSTZ_H */

4
arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
View File

@ -96,9 +96,9 @@ mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 { /* RTL8211E */
ethphy0: ethernet-phy@1 { /* RTL8211E */
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reg = <1>;
reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
reset-assert-us = <20>;
reset-deassert-us = <200000>;

47
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts
View File

@ -22,6 +22,18 @@ chosen {
stdout-path = &uart2;
};
hdmi-connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
};
reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
@ -222,6 +234,28 @@ flash: flash@0 {
};
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
status = "okay";
ports {
port@1 {
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
&hdmi_tx_phy {
status = "okay";
};
&i2c4 {
expander0: gpio@20 {
compatible = "nxp,pca9535";
@ -276,6 +310,10 @@ ethmac2: mac-address@c {
};
};
&lcdif3 {
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
@ -430,6 +468,15 @@ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2

4
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts
View File

@ -88,6 +88,7 @@ led-0 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
function-enumerator = <0>;
gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* GPIO E */
pinctrl-0 = <&pinctrl_dhcom_e>;
pinctrl-names = "default";
@ -97,6 +98,7 @@ led-1 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */
pinctrl-0 = <&pinctrl_dhcom_f>;
pinctrl-names = "default";
@ -106,6 +108,7 @@ led-2 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; /* GPIO H */
pinctrl-0 = <&pinctrl_dhcom_h>;
pinctrl-names = "default";
@ -115,6 +118,7 @@ led-3 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
function-enumerator = <3>;
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
pinctrl-0 = <&pinctrl_dhcom_i>;
pinctrl-names = "default";

6
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@ -442,6 +442,10 @@ &flexcan2 {
status = "disabled";/* can2 pin conflict with pdm */
};
&hdmi_pai {
status = "okay";
};
&hdmi_pvi {
status = "okay";
};
@ -710,6 +714,8 @@ &pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie0>;
vpcie3v3aux-supply = <&reg_pcie0>;
supports-clkreq;
status = "okay";
};

44
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso Normal file
View File

@ -0,0 +1,44 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx8mp-clock.h>
/dts-v1/;
/plugin/;
&backlight_lvds1 {
brightness-levels = <0 8 16 32 64 128 255>;
default-brightness-level = <8>;
enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
num-interpolated-steps = <2>;
pwms = <&pwm3 0 50000 0>;
status = "okay";
};
&lcdif2 {
status = "okay";
};
&lvds_bridge {
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
/*
* The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
* 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout
* engine can reach accurate pixel clock of exactly 72.4 MHz.
*/
assigned-clock-rates = <0>, <506800000>;
status = "okay";
};
&panel_lvds1 {
compatible = "edt,etml1010g3dra";
status = "okay";
};
&pwm3 {
status = "okay";
};

45
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso Normal file
View File

@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx8mp-clock.h>
#include "imx8mp-phyboard-pollux-peb-av-10.dtsi"
&backlight_lvds0 {
brightness-levels = <0 8 16 32 64 128 255>;
default-brightness-level = <8>;
enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
num-interpolated-steps = <2>;
pwms = <&pwm4 0 50000 0>;
status = "okay";
};
&lcdif2 {
status = "okay";
};
&lvds_bridge {
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
/*
* The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
* 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout
* engine can reach accurate pixel clock of exactly 72.4 MHz.
*/
assigned-clock-rates = <0>, <506800000>;
status = "okay";
};
&panel_lvds0 {
compatible = "edt,etml1010g3dra";
status = "okay";
};
&pwm4 {
status = "okay";
};

45
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso Normal file
View File

@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx8mp-clock.h>
#include "imx8mp-phyboard-pollux-peb-av-10.dtsi"
&backlight_lvds0 {
brightness-levels = <0 8 16 32 64 128 255>;
default-brightness-level = <8>;
enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
num-interpolated-steps = <2>;
pwms = <&pwm4 0 66667 0>;
status = "okay";
};
&lcdif2 {
status = "okay";
};
&lvds_bridge {
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
/*
* The LVDS panel uses 66.5 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
* 66.5 * 7 = 465.5 MHz so the LDB serializer and LCDIFv3 scanout
* engine can reach accurate pixel clock of exactly 66.5 MHz.
*/
assigned-clock-rates = <0>, <465500000>;
status = "okay";
};
&panel_lvds0 {
compatible = "powertip,ph128800t006-zhc01";
status = "okay";
};
&pwm4 {
status = "okay";
};

198
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10.dtsi Normal file
View File

@ -0,0 +1,198 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include "imx8mp-pinfunc.h"
&{/} {
backlight_lvds0: backlight0 {
compatible = "pwm-backlight";
pinctrl-0 = <&pinctrl_lvds0>;
pinctrl-names = "default";
power-supply = <&reg_vcc_12v>;
status = "disabled";
};
panel_lvds0: panel-lvds0 {
backlight = <&backlight_lvds0>;
power-supply = <&reg_vcc_3v3_sw>;
status = "disabled";
port {
panel0_in: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
};
reg_vcc_12v: regulator-12v {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <12000000>;
regulator-min-microvolt = <12000000>;
regulator-name = "VCC_12V";
};
reg_vcc_1v8_audio: regulator-1v8 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "VCC_1V8_Audio";
};
reg_vcc_3v3_analog: regulator-3v3 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VCC_3V3_Analog";
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "snd-peb-av-10";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,mclk-fs = <32>;
simple-audio-card,widgets =
"Line", "Line In",
"Speaker", "Speaker",
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Speaker", "SPOP",
"Speaker", "SPOM",
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1L", "Line In",
"LINE1R", "Line In",
"MIC3R", "Microphone Jack",
"Microphone Jack", "Mic Bias";
simple-audio-card,cpu {
sound-dai = <&sai2>;
};
dailink_master: simple-audio-card,codec {
sound-dai = <&codec>;
clocks = <&clk IMX8MP_CLK_SAI2>;
};
};
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
codec: codec@18 {
compatible = "ti,tlv320aic3007";
reg = <0x18>;
pinctrl-0 = <&pinctrl_tlv320>;
pinctrl-names = "default";
#sound-dai-cells = <0>;
reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
ai3x-gpio-func = <0xd 0x0>;
ai3x-micbias-vg = <2>;
AVDD-supply = <&reg_vcc_3v3_analog>;
DRVDD-supply = <&reg_vcc_3v3_analog>;
DVDD-supply = <&reg_vcc_1v8_audio>;
IOVDD-supply = <&reg_vcc_3v3_sw>;
};
eeprom@57 {
compatible = "atmel,24c32";
reg = <0x57>;
pagesize = <32>;
vcc-supply = <&reg_vcc_3v3_sw>;
};
};
&ldb_lvds_ch0 {
remote-endpoint = <&panel0_in>;
};
&pwm4 {
pinctrl-0 = <&pinctrl_pwm4>;
pinctrl-names = "default";
};
&sai2 {
pinctrl-0 = <&pinctrl_sai2>;
pinctrl-names = "default";
assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
<&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_AUDIO_PLL1_OUT>,
<&clk IMX8MP_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k",
"pll11k";
#sound-dai-cells = <0>;
fsl,sai-mclk-direction-output;
fsl,sai-synchronous-rx;
status = "okay";
};
&iomuxc {
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1e2
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1e2
>;
};
pinctrl_lvds0: lvds0grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x12
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x12
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6
MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC 0xd6
MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
>;
};
pinctrl_tlv320: tlv320grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x16
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x16
>;
};
};

9
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10.dtso Normal file
View File

@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
/dts-v1/;
/plugin/;
#include "imx8mp-phyboard-pollux-peb-av-10.dtsi"

45
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-ph128800t006.dtso Normal file
View File

@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx8mp-clock.h>
/dts-v1/;
/plugin/;
&backlight_lvds1 {
brightness-levels = <0 8 16 32 64 128 255>;
default-brightness-level = <8>;
enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
num-interpolated-steps = <2>;
pwms = <&pwm3 0 66667 0>;
status = "okay";
};
&lcdif2 {
status = "okay";
};
&lvds_bridge {
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
/*
* The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
* 66.5 * 7 = 465.5 MHz so the LDB serializer and LCDIFv3 scanout
* engine can reach accurate pixel clock of exactly 66.5 MHz.
*/
assigned-clock-rates = <0>, <465500000>;
status = "okay";
};
&panel_lvds1 {
compatible = "powertip,ph128800t006-zhc01";
status = "okay";
};
&pwm3 {
status = "okay";
};

52
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
View File

@ -1,14 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2020 PHYTEC Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
/dts-v1/;
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/leds/leds-pca9532.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/thermal/thermal.h>
#include "imx8mp-phycore-som.dtsi"
@ -21,16 +19,12 @@ chosen {
stdout-path = &uart1;
};
backlight_lvds: backlight {
backlight_lvds1: backlight1 {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds1>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <11>;
enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
num-interpolated-steps = <2>;
pinctrl-names = "default";
power-supply = <&reg_lvds1_reg_en>;
pwms = <&pwm3 0 50000 0>;
status = "disabled";
};
fan0: fan {
@ -43,10 +37,11 @@ fan0: fan {
#cooling-cells = <2>;
};
panel1_lvds: panel-lvds {
compatible = "edt,etml1010g3dra";
backlight = <&backlight_lvds>;
panel_lvds1: panel-lvds1 {
/* compatible panel in overlay */
backlight = <&backlight_lvds1>;
power-supply = <&reg_vcc_3v3_sw>;
status = "disabled";
port {
panel1_in: endpoint {
@ -232,32 +227,8 @@ led-3 {
};
};
&lcdif2 {
status = "okay";
};
&lvds_bridge {
status = "okay";
ports {
port@2 {
ldb_lvds_ch1: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
};
&media_blk_ctrl {
/*
* The LVDS panel on this device uses 72.4 MHz pixel clock,
* set IMX8MP_VIDEO_PLL1 to 72.4 * 7 = 506.8 MHz so the LDB
* serializer and LCDIFv3 scanout engine can reach accurate
* pixel clock of exactly 72.4 MHz.
*/
assigned-clock-rates = <500000000>, <200000000>,
<0>, <0>, <500000000>,
<506800000>;
&ldb_lvds_ch1 {
remote-endpoint = <&panel1_in>;
};
&snvs_pwrkey {
@ -282,9 +253,8 @@ &pcie {
};
&pwm3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
pinctrl-names = "default";
};
&rv3028 {

3
arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
View File

@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2020 PHYTEC Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
#include <dt-bindings/net/ti-dp83867.h>

504
arch/arm64/boot/dts/freescale/imx8mp-prt8ml.dts Normal file
View File

@ -0,0 +1,504 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2020 Protonic Holland
* Copyright 2019 NXP
*/
/dts-v1/;
#include "imx8mp.dtsi"
/ {
model = "Protonic PRT8ML";
compatible = "prt,prt8ml", "fsl,imx8mp";
chosen {
stdout-path = &uart4;
};
pcie_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie_refclk_oe: pcie0-refclk-oe {
compatible = "gpio-gate-clock";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_refclk>;
clocks = <&pcie_refclk>;
#clock-cells = <0>;
enable-gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;
};
};
&A53_0 {
cpu-supply = <&fan53555>;
};
&A53_1 {
cpu-supply = <&fan53555>;
};
&A53_2 {
cpu-supply = <&fan53555>;
};
&A53_3 {
cpu-supply = <&fan53555>;
};
&a53_opp_table {
opp-1200000000 {
opp-microvolt = <900000>;
};
opp-1600000000 {
opp-microvolt = <980000>;
};
/* Power supply insuffient for 1.8 GHz */
/delete-node/ opp-1800000000;
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
/* Disable DMA to meet performance requirements */
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
switch@0 {
compatible = "nxp,sja1105q";
reg = <0>;
reset-gpios = <&gpio_exp_1 4 GPIO_ACTIVE_LOW>;
spi-cpha;
spi-max-frequency = <4000000>;
spi-rx-delay-us = <1>;
spi-tx-delay-us = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@3 {
reg = <3>;
label = "rj45";
phy-handle = <&rj45_phy>;
phy-mode = "rgmii-id";
};
port@4 {
reg = <4>;
ethernet = <&fec>;
label = "cpu";
phy-mode = "rgmii-id";
rx-internal-delay-ps = <2000>;
tx-internal-delay-ps = <2000>;
/* Unreliable at 1000Mbps, limit RGMII to 100Mbps */
fixed-link {
full-duplex;
speed = <100>;
};
};
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii"; /* switch inserts delay */
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
status = "okay";
fixed-link {
full-duplex;
speed = <100>;
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
rj45_phy: ethernet-phy@2 {
reg = <2>;
reset-gpios = <&gpio_exp_1 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
};
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
ak5558: codec@10 {
compatible = "asahi-kasei,ak5558";
reg = <0x10>;
reset-gpios = <&gpio_exp_1 2 GPIO_ACTIVE_LOW>;
};
gpio_exp_1: gpio@25 {
compatible = "nxp,pca9571";
reg = <0x25>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
tps65987ddh_0: usb-pd@20 {
compatible = "ti,tps6598x";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tps65987ddh_0>;
interrupts-extended = <&gpio1 12 IRQ_TYPE_LEVEL_LOW>;
};
gpio_exp_2: gpio@25 {
compatible = "nxp,pca9571";
reg = <0x25>;
gpio-controller;
#gpio-cells = <2>;
c0-hreset-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_LOW>;
line-name = "c0-hreset";
output-low;
};
c1-hreset-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_LOW>;
line-name = "c1-hreset";
output-low;
};
};
fan53555: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fan53555>;
regulator-name = "fan53555";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <980000>;
regulator-always-on;
regulator-boot-on;
fcs,suspend-voltage-selector = <1>;
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
ak4458: codec@11 {
compatible = "asahi-kasei,ak4458";
reg = <0x11>;
#sound-dai-cells = <0>;
reset-gpios = <&gpio_exp_2 5 GPIO_ACTIVE_LOW>;
};
tps65987ddh_1: usb-pd@20 {
compatible = "ti,tps6598x";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tps65987ddh_1>;
interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>;
};
};
&lcdif1 {
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <100000000>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
no-1-8-v;
sd-uhs-sdr12;
sd-uhs-sdr25;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x154
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x154
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x154
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x154
>;
};
pinctrl_fan53555: fan53555grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x114
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154
MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x400000c3
MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x400000c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400000c3
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400000c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400000c3
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400000c3
>;
};
pinctrl_pcie_refclk: pcierefclkgrp {
fsl,pins = <
MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0xc6
>;
};
pinctrl_tps65987ddh_0: tps65987ddh-0grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x1d0
>;
};
pinctrl_tps65987ddh_1: tps65987ddh-1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1d0
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x040
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x040
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0d4
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
>;
};
};

8
arch/arm64/boot/dts/freescale/imx8mp-skov-revc-hdmi.dts Normal file
View File

@ -0,0 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include "imx8mp-skov-revb-hdmi.dts"
/ {
model = "SKOV IMX8MP CPU revC - HDMI";
compatible = "skov,imx8mp-skov-revc-hdmi", "fsl,imx8mp";
};

79
arch/arm64/boot/dts/freescale/imx8mp-skov-revc-jutouch-jt101tm023.dts Normal file
View File

@ -0,0 +1,79 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include "imx8mp-skov-reva.dtsi"
/ {
model = "SKOV IMX8MP CPU revC - JuTouch JT101TM023";
compatible = "skov,imx8mp-skov-revc-jutouch-jt101tm023", "fsl,imx8mp";
panel {
compatible = "jutouch,jt101tm023";
backlight = <&backlight>;
power-supply = <&reg_tft_vcom>;
port {
in_lvds0: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
};
};
&backlight {
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
status = "okay";
touchscreen@2a {
compatible = "eeti,exc81w32", "eeti,exc80h84";
reg = <0x2a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touchscreen>;
interrupts-extended = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
touchscreen-size-x = <1280>;
touchscreen-size-y = <800>;
vdd-supply = <&reg_vdd_3v3>;
};
};
&lcdif2 {
status = "okay";
};
&lvds_bridge {
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>,
<&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */
assigned-clock-rates = <0>, <506800000>;
status = "okay";
ports {
port@1 {
ldb_lvds_ch0: endpoint {
remote-endpoint = <&in_lvds0>;
};
};
};
};
&pwm4 {
status = "okay";
};
&pwm1 {
status = "okay";
};
&reg_tft_vcom {
regulator-min-microvolt = <3160000>;
regulator-max-microvolt = <3160000>;
voltage-table = <3160000 73>;
status = "okay";
};

7
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
View File

@ -238,6 +238,13 @@ sound {
audio-asrc = <&easrc>;
audio-cpu = <&sai3>;
audio-codec = <&tlv320aic3x04>;
audio-routing =
"IN3_L", "Mic Jack",
"Mic Jack", "Mic Bias",
"IN1_L", "Line In Jack",
"IN1_R", "Line In Jack",
"Line Out Jack", "LOL",
"Line Out Jack", "LOR";
};
thermal-zones {

54
arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi
View File

@ -101,6 +101,7 @@ ethphy0: ethernet-phy@0 {
reg = <0x0>;
interrupt-parent = <&gpio3>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
@ -395,13 +396,6 @@ &i2c3 {
status = "okay";
};
/* off-board header */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* console */
&uart2 {
pinctrl-names = "default";
@ -409,25 +403,6 @@ &uart2 {
status = "okay";
};
/* off-board header */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
/* off-board */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <4>;
non-removable;
status = "okay";
bus-width = <4>;
non-removable;
status = "okay";
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
@ -464,7 +439,7 @@ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x0
>;
};
@ -523,13 +498,6 @@ MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
@ -537,24 +505,6 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190

11
arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
View File

@ -365,17 +365,6 @@ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190

1
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
View File

@ -228,6 +228,7 @@ mdio {
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

81
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -13,6 +13,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include "imx8mp-aipstz.h"
#include "imx8mp-pinfunc.h"
/ {
@ -80,6 +81,12 @@ A53_0: cpu@0 {
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
cpu0_therm: thermal-idle {
#cooling-cells = <2>;
duration-us = <10000>;
exit-latency-us = <700>;
};
};
A53_1: cpu@1 {
@ -98,6 +105,12 @@ A53_1: cpu@1 {
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
cpu1_therm: thermal-idle {
#cooling-cells = <2>;
duration-us = <10000>;
exit-latency-us = <700>;
};
};
A53_2: cpu@2 {
@ -116,6 +129,12 @@ A53_2: cpu@2 {
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
cpu2_therm: thermal-idle {
#cooling-cells = <2>;
duration-us = <10000>;
exit-latency-us = <700>;
};
};
A53_3: cpu@3 {
@ -134,6 +153,12 @@ A53_3: cpu@3 {
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
cpu3_therm: thermal-idle {
#cooling-cells = <2>;
duration-us = <10000>;
exit-latency-us = <700>;
};
};
A53_L2: l2-cache0 {
@ -323,7 +348,11 @@ map0 {
<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&gpu3d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&gpu2d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_therm 0 50>,
<&cpu1_therm 0 50>,
<&cpu2_therm 0 50>,
<&cpu3_therm 0 50>;
};
};
};
@ -356,7 +385,11 @@ map0 {
<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&gpu3d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&gpu2d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_therm 0 50>,
<&cpu1_therm 0 50>,
<&cpu2_therm 0 50>,
<&cpu3_therm 0 50>;
};
};
};
@ -1396,12 +1429,14 @@ eqos: ethernet@30bf0000 {
};
};
aips5: bus@30c00000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30c00000 0x400000>;
aips5: bus@30df0000 {
compatible = "fsl,imx8mp-aipstz";
reg = <0x30df0000 0x10000>;
power-domains = <&pgc_audio>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
#access-controller-cells = <3>;
ranges = <0x30c00000 0x30c00000 0x400000>;
spba-bus@30c00000 {
compatible = "fsl,spba-bus", "simple-bus";
@ -1770,6 +1805,7 @@ mipi_csi_0: csi@32e40000 {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
<&clk IMX8MP_CLK_24M>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
fsl,num-channels = <3>;
status = "disabled";
ports {
@ -1805,6 +1841,7 @@ mipi_csi_1: csi@32e50000 {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
<&clk IMX8MP_CLK_24M>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
fsl,num-channels = <3>;
status = "disabled";
ports {
@ -2073,7 +2110,7 @@ irqsteer_hdmi: interrupt-controller@32fc2000 {
hdmi_pvi: display-bridge@32fc4000 {
compatible = "fsl,imx8mp-hdmi-pvi";
reg = <0x32fc4000 0x1000>;
reg = <0x32fc4000 0x800>;
interrupt-parent = <&irqsteer_hdmi>;
interrupts = <12>;
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
@ -2099,6 +2136,23 @@ pvi_to_hdmi_tx: endpoint {
};
};
hdmi_pai: audio-bridge@32fc4800 {
compatible = "fsl,imx8mp-hdmi-pai";
reg = <0x32fc4800 0x800>;
interrupt-parent = <&irqsteer_hdmi>;
interrupts = <14>;
clocks = <&clk IMX8MP_CLK_HDMI_APB>;
clock-names = "apb";
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PAI>;
status = "disabled";
port {
pai_to_hdmi_tx: endpoint {
remote-endpoint = <&hdmi_tx_from_pai>;
};
};
};
lcdif3: display-controller@32fc6000 {
compatible = "fsl,imx8mp-lcdif";
reg = <0x32fc6000 0x1000>;
@ -2150,6 +2204,14 @@ port@1 {
reg = <1>;
/* Point endpoint to the HDMI connector */
};
port@2 {
reg = <2>;
hdmi_tx_from_pai: endpoint {
remote-endpoint = <&pai_to_hdmi_tx>;
};
};
};
};
@ -2445,6 +2507,11 @@ dsp: dsp@3b6e8000 {
firmware-name = "imx/dsp/hifi4.bin";
resets = <&audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL>;
reset-names = "runstall";
access-controllers = <&aips5
IMX8MP_AIPSTZ_HIFI4
IMX8MP_AIPSTZ_MASTER
(IMX8MP_AIPSTZ_MPL | IMX8MP_AIPSTZ_MTW | IMX8MP_AIPSTZ_MTR)
>;
status = "disabled";
};
};

3
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
View File

@ -375,6 +375,7 @@ &pcie0 {
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&clk IMX8MQ_CLK_PCIE1_AUX>;
vph-supply = <&vgen5_reg>;
supports-clkreq;
status = "okay";
};
@ -397,7 +398,9 @@ &pcie1 {
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_AUX>;
vpcie-supply = <&reg_pcie1>;
vpcie3v3aux-supply = <&reg_pcie1>;
vph-supply = <&vgen5_reg>;
supports-clkreq;
status = "okay";
};

10
arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi
View File

@ -11,4 +11,12 @@ / {
model = "Toradex Apalis iMX8QM V1.1";
};
/* TODO: Cooling Maps */
&cooling_maps_map0 {
cooling-device =
<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};

2
arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi
View File

@ -314,8 +314,6 @@ &pinctrl_pcie_sata_refclk {
<IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x00000021>;
};
/* TODO: On-module Wi-Fi */
/* Apalis MMC1 */
&usdhc2 {
/*

156
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
View File

@ -249,6 +249,13 @@ reg_2v8: regulator-2v8 {
regulator-max-microvolt = <2800000>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_usdhc2_vmmc: usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
@ -323,6 +330,15 @@ reg_pciea: regulator-pcie {
enable-active-high;
};
reg_usb_otg1_vbus: regulator-usbotg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&lsio_gpio4 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
@ -566,6 +582,8 @@ light-sensor@44 {
pressure-sensor@60 {
compatible = "fsl,mpl3115";
reg = <0x60>;
vdd-supply = <&reg_3v3>;
vddio-supply = <&reg_3v3>;
};
max7322: gpio@68 {
@ -686,6 +704,16 @@ &lpuart0 {
status = "okay";
};
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
@ -775,6 +803,8 @@ &pciea {
pinctrl-names = "default";
reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pciea>;
vpcie3v3aux-supply = <&reg_pciea>;
supports-clkreq;
status = "okay";
};
@ -800,8 +830,12 @@ &pwm_lvds1 {
};
&usdhc1 {
pinctrl-names = "default";
assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1>;
pinctrl-2 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-sd;
no-sdio;
@ -810,8 +844,10 @@ &usdhc1 {
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
@ -819,10 +855,25 @@ &usdhc2 {
status = "okay";
};
&usbphy1 {
status = "okay";
};
&usb3_phy {
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
srp-disable;
hnp-disable;
adp-disable;
disable-over-current;
status = "okay";
};
&usbotg3 {
status = "okay";
};
@ -896,6 +947,38 @@ &vpu_dsp {
status = "okay";
};
&thermal_zones {
pmic-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
trips {
pmic_alert0: trip0 {
temperature = <110000>;
hysteresis = <2000>;
type = "passive";
};
pmic_crit0: trip1 {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&pmic_alert0>;
cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
@ -1011,38 +1094,38 @@ IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21
pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp {
fsl,pins = <
IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020
IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020
IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020
IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020
>;
};
pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp {
fsl,pins = <
IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020
IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020
IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020
IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020
IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020
IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
>;
};
@ -1092,6 +1175,15 @@ IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020
>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020
IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020
IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020
IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020
>;
};
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <
IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020
@ -1201,6 +1293,12 @@ IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
@ -1228,4 +1326,12 @@ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
>;
};
};

6
arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi
View File

@ -327,7 +327,8 @@ &edma0 {
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, /* sai5 */
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
<&pd IMX_SC_R_DMA_2_CH1>,
<&pd IMX_SC_R_DMA_2_CH2>,
@ -365,7 +366,8 @@ &edma1 {
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* no used */
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai6 */
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai7 */
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* sai7 */
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
<&pd IMX_SC_R_DMA_3_CH1>,
<&pd IMX_SC_R_DMA_3_CH2>,

3
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
View File

@ -99,7 +99,8 @@ &edma2 {
<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
<&pd IMX_SC_R_DMA_0_CH1>,
<&pd IMX_SC_R_DMA_0_CH2>,

2
arch/arm64/boot/dts/freescale/imx8qm.dtsi
View File

@ -369,7 +369,7 @@ watchdog {
};
};
thermal-zones {
thermal_zones: thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;

176
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@ -150,6 +150,13 @@ reg_2v8: regulator-2v8 {
regulator-max-microvolt = <2800000>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_pcieb: regulator-pcie {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
@ -212,6 +219,15 @@ reg_can_stby: regulator-can-stby {
vin-supply = <&reg_can_en>;
};
reg_fec2_supply: regulator-fec2_nvcc {
compatible = "regulator-fixed";
regulator-name = "fec2_nvcc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg1_vbus: regulator-usbotg1-vbus {
compatible = "regulator-fixed";
regulator-max-microvolt = <5000000>;
@ -397,6 +413,8 @@ &fec1 {
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
nvmem-cells = <&fec_mac0>;
nvmem-cell-names = "mac-address";
fsl,magic-packet;
status = "okay";
@ -408,9 +426,26 @@ ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
phy-supply = <&reg_fec2_supply>;
fsl,magic-packet;
nvmem-cells = <&fec_mac1>;
nvmem-cell-names = "mac-address";
status = "disabled";
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
@ -453,6 +488,8 @@ i2c@2 {
pressure-sensor@60 {
compatible = "fsl,mpl3115";
reg = <0x60>;
vdd-supply = <&reg_3v3>;
vddio-supply = <&reg_3v3>;
};
};
@ -586,6 +623,20 @@ &flexcan2 {
status = "okay";
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <133000000>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
};
};
&jpegdec {
status = "okay";
};
@ -600,6 +651,16 @@ &lpuart0 {
status = "okay";
};
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
@ -631,6 +692,8 @@ &pcie0 {
pinctrl-names = "default";
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcieb>;
vpcie3v3aux-supply = <&reg_pcieb>;
supports-clkreq;
status = "okay";
};
@ -729,9 +792,11 @@ map0 {
&usdhc1 {
assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1>;
pinctrl-2 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-sd;
no-sdio;
@ -742,8 +807,10 @@ &usdhc1 {
&usdhc2 {
assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
@ -807,8 +874,8 @@ &iomuxc {
pinctrl_cm40_i2c: cm40i2cgrp {
fsl,pins = <
IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c
IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c
IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c
IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c
>;
};
@ -821,16 +888,16 @@ IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c
pinctrl_esai0: esai0grp {
fsl,pins = <
IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040
IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040
IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040
IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040
IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040
IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040
IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040
IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040
IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040
IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040
IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040
IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040
IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040
IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040
IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040
IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040
IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040
IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040
IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040
IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040
>;
};
@ -853,6 +920,23 @@ IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <
IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060
IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060
IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060
IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060
IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060
IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060
IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060
>;
};
pinctrl_flexcan1: flexcan0grp {
fsl,pins = <
IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21
@ -874,6 +958,27 @@ IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
>;
};
pinctrl_ioexp_rst: ioexprstgrp {
fsl,pins = <
IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021
@ -900,17 +1005,26 @@ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020
IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020
IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020
IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
>;
};
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <
IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020
IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020
IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020
IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020
>;
};
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <
IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
>;
};
@ -932,13 +1046,13 @@ IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021
pinctrl_typec: typecgrp {
fsl,pins = <
IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021
IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021
>;
};
pinctrl_typec_mux: typecmuxgrp {
fsl,pins = <
IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60
IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60
>;
};
@ -953,11 +1067,11 @@ IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS 0x06000040
pinctrl_sai1: sai1grp {
fsl,pins = <
IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040
IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040
IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040
IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060
IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040
IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040
IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040
IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040
IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060
IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040
>;
};
@ -977,6 +1091,14 @@ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021
IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021
IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041

9
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View File

@ -234,11 +234,20 @@ ocotp: ocotp {
compatible = "fsl,imx8qxp-scu-ocotp";
#address-cells = <1>;
#size-cells = <1>;
fec_mac0: mac@2c4 {
reg = <0x2c4 6>;
};
fec_mac1: mac@2c6 {
reg = <0x2c6 6>;
};
};
scu_key: keys {
compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
linux,keycodes = <KEY_POWER>;
wakeup-source;
status = "disabled";
};

345
arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts Normal file
View File

@ -0,0 +1,345 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
* Author: Christoph Stoidner <c.stoidner@phytec.de>
*
* Product homepage:
* phyBOARD-Segin carrier board is reused for the i.MX91 design.
* https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/
*/
/dts-v1/;
#include "imx91-phycore-som.dtsi"
/{
model = "PHYTEC phyBOARD-Segin-i.MX91";
compatible = "phytec,imx91-phyboard-segin", "phytec,imx91-phycore-som",
"fsl,imx91";
aliases {
ethernet1 = &eqos;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &i2c_rtc;
rtc1 = &bbnsm_rtc;
serial0 = &lpuart1;
};
chosen {
stdout-path = &lpuart1;
};
flexcan1_tc: can-phy0 {
/* TI SN65HVD234D CAN-CC 1MBit/s */
compatible = "ti,tcan1043";
#phy-cells = <0>;
max-bitrate = <1000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1_tc>;
enable-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
};
reg_sound_1v8: regulator-sound-1v8 {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "VCC1V8_AUDIO";
};
reg_sound_3v3: regulator-sound-3v3 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VCC3V3_ANALOG";
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "USB_OTG1_VBUS";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
compatible = "regulator-fixed";
regulator-name = "USB_OTG2_VBUS";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VCC_SD";
};
sound: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,widgets =
"Line", "Line In",
"Line", "Line Out",
"Speaker", "Speaker";
simple-audio-card,routing =
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"Speaker", "SPOP",
"Speaker", "SPOM",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
dailink_master: simple-audio-card,codec {
sound-dai = <&audio_codec>;
clocks = <&clk IMX93_CLK_SAI1>;
};
};
};
/* Ethernet */
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rmii";
phy-handle = <&ethphy2>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <100000000>, <50000000>;
status = "okay";
};
&mdio {
ethphy2: ethernet-phy@2 {
compatible = "ethernet-phy-id0022.1561";
reg = <2>;
clocks = <&clk IMX91_CLK_ENET2_REGULAR>;
clock-names = "rmii-ref";
micrel,led-mode = <1>;
};
};
/* CAN */
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
phys = <&flexcan1_tc>;
status = "okay";
};
/* I2C2 */
&lpi2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_lpi2c2>;
pinctrl-1 = <&pinctrl_lpi2c2_gpio>;
scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
/* Codec */
audio_codec: audio-codec@18 {
compatible = "ti,tlv320aic3007";
reg = <0x18>;
#sound-dai-cells = <0>;
AVDD-supply = <&reg_sound_3v3>;
IOVDD-supply = <&reg_sound_3v3>;
DRVDD-supply = <&reg_sound_3v3>;
DVDD-supply = <&reg_sound_1v8>;
};
/* RTC */
i2c_rtc: rtc@68 {
compatible = "microcrystal,rv4162";
reg = <0x68>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupt-parent = <&gpio4>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
};
};
/* Console */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* Audio */
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clk IMX93_CLK_SAI1>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <19200000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
/* USB */
&usbphynop1 {
vbus-supply = <&reg_usb_otg1_vbus>;
};
&usbphynop2 {
vbus-supply = <&reg_usb_otg2_vbus>;
};
&usbotg1 {
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
status = "okay";
};
/* SD-Card */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
bus-width = <4>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
disable-wp;
no-mmc;
no-sdio;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x4000050e
MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x50e
MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x50e
MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e
MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x57e
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
MX91_PAD_PDM_CLK__CAN1_TX 0x139e
>;
};
pinctrl_flexcan1_tc: flexcan1tcgrp {
fsl,pins = <
MX91_PAD_ENET2_TD3__GPIO4_IO16 0x31e
>;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
};
pinctrl_lpi2c2_gpio: lpi2c2gpiogrp {
fsl,pins = <
MX91_PAD_I2C2_SCL__GPIO1_IO2 0x31e
MX91_PAD_I2C2_SDA__GPIO1_IO3 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX91_PAD_ENET2_RD2__GPIO4_IO26 0x31e
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX91_PAD_UART2_RXD__SAI1_MCLK 0x1202
MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x1202
MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x1202
MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x1402
MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x1402
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
MX91_PAD_UART1_TXD__LPUART1_TX 0x30e
>;
};
pinctrl_usdhc2_cd: usdhc2cdgrp {
fsl,pins = <
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
>;
};
pinctrl_usdhc2_default: usdhc2grp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1386
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x159e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
};

304
arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi Normal file
View File

@ -0,0 +1,304 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
* Author: Christoph Stoidner <c.stoidner@phytec.de>
*
* Product homepage:
* https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
*/
#include <dt-bindings/leds/common.h>
#include "imx91.dtsi"
/ {
model = "PHYTEC phyCORE-i.MX91";
compatible = "phytec,imx91-phycore-som", "fsl,imx91";
aliases {
ethernet0 = &fec;
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
linux,cma {
compatible = "shared-dma-pool";
reusable;
alloc-ranges = <0 0x80000000 0 0x40000000>;
size = <0 0x10000000>;
linux,cma-default;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
reg_vdda_1v8: regulator-vdda-1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDA_1V8";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
vin-supply = <&buck5>;
};
};
/* ADC */
&adc1 {
vref-supply = <&reg_vdda_1v8>;
};
/* Ethernet */
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET2_REGULAR>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <100000000>, <50000000>;
status = "okay";
mdio: mdio {
clock-frequency = <5000000>;
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
reset-assert-us = <30>;
};
};
};
/* I2C3 */
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
regulators {
buck1: BUCK1 {
regulator-name = "VDD_SOC";
regulator-max-microvolt = <950000>;
regulator-min-microvolt = <610000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "VDDQ_0V6";
regulator-max-microvolt = <600000>;
regulator-min-microvolt = <600000>;
regulator-boot-on;
regulator-always-on;
};
buck4: BUCK4 {
regulator-name = "VDD_3V3_BUCK";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "VDD_1V8";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "VDD_1V1";
regulator-max-microvolt = <1100000>;
regulator-min-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "PMIC_SNVS_1V8";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "VDD_0V8";
regulator-max-microvolt = <800000>;
regulator-min-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "NVCC_SD2";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
/* EEPROM */
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&buck4>;
};
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
no-1-8-v;
status = "okay";
};
/* Watchdog */
&wdog3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_fec: fecgrp {
fsl,pins = <
MX91_PAD_ENET2_MDC__ENET2_MDC 0x50e
MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x502
/* the three pins below are connected to PHYs straps,
* that is what the pull-up/down setting is for.
*/
MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x37e
MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x37e
MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e
MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x50e
MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x50e
MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x50e
MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x4000050e
MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e
>;
};
pinctrl_leds: ledsgrp {
fsl,pins = <
MX91_PAD_I2C1_SDA__GPIO1_IO1 0x11e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
fsl,pins = <
MX91_PAD_GPIO_IO28__GPIO2_IO28 0x31e
MX91_PAD_GPIO_IO29__GPIO2_IO29 0x31e
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX91_PAD_ENET2_RD3__GPIO4_IO27 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x179e
MX91_PAD_SD1_CMD__USDHC1_CMD 0x1386
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1386
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1386
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1386
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1386
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1386
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1386
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x17be
MX91_PAD_SD1_CMD__USDHC1_CMD 0x139e
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x139e
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13be
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x139e
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x139e
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x139e
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x139e
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x139e
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x17be
MX91_PAD_SD1_CMD__USDHC1_CMD 0x139e
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x139e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13be
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13be
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13be
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13be
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13be
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13be
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13be
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
>;
};
};

2
arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
View File

@ -706,7 +706,7 @@ flexcan2: can@425b0000 {
};
flexspi1: spi@425e0000 {
compatible = "nxp,imx8mm-fspi";
compatible = "nxp,imx93-fspi", "nxp,imx8mm-fspi";
reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
#address-cells = <1>;

31
arch/arm64/boot/dts/freescale/imx93-phyboard-nash-jtag.dtso Normal file
View File

@ -0,0 +1,31 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
* Author: Primoz Fiser <primoz.fiser@norik.com>
*/
#include "imx93-pinfunc.h"
/dts-v1/;
/plugin/;
/*
* NOTE: Bind pinctrl_jtag to gpio2 so that the pinctrl settings are applied.
* JTAG itself has no dedicated driver, so without attaching it to an active
* device node (like gpio2), the pinmux configuration would not take effect.
*/
&gpio2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_jtag>;
};
&iomuxc {
pinctrl_jtag: jtaggrp {
fsl,pins = <
MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x31e
MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x31e
MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x31e
MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x31e
>;
};
};

75
arch/arm64/boot/dts/freescale/imx93-phyboard-nash-pwm-fan.dtso Normal file
View File

@ -0,0 +1,75 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
* Author: Primoz Fiser <primoz.fiser@norik.com>
*/
#include <dt-bindings/pwm/pwm.h>
#include "imx93-pinfunc.h"
/dts-v1/;
/plugin/;
&{/} {
fan0: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fan>;
cooling-levels = <1 90 150 200 255>;
pwms = <&tpm6 1 40000 PWM_POLARITY_INVERTED>;
};
thermal-zones {
cpu-thermal {
trips {
cpu_low: cpu-low {
hysteresis = <3000>;
temperature = <50000>;
type = "active";
};
cpu_med: cpu-med {
hysteresis = <3000>;
temperature = <58000>;
type = "active";
};
cpu_high: cpu-high {
hysteresis = <3000>;
temperature = <65000>;
type = "active";
};
};
cooling-maps {
map1 {
cooling-device = <&fan0 1 1>;
trip = <&cpu_low>;
};
map2 {
cooling-device = <&fan0 2 2>;
trip = <&cpu_med>;
};
map3 {
cooling-device = <&fan0 4 4>;
trip = <&cpu_high>;
};
};
};
};
};
&tpm6 {
status = "okay";
};
&iomuxc {
pinctrl_fan: fangrp {
fsl,pins = <
MX93_PAD_GPIO_IO23__TPM6_CH1 0x31e
>;
};
};

24
arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
View File

@ -71,6 +71,22 @@ iio-hwmon {
io-channels = <&curr_sens 0>;
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "USB1_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb2_vbus: regulator-usb2-vbus {
compatible = "regulator-fixed";
regulator-name = "USB2_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
@ -187,6 +203,14 @@ &lpuart7 {
};
/* USB */
&usbphynop1 {
vbus-supply = <&reg_usb1_vbus>;
};
&usbphynop2 {
vbus-supply = <&reg_usb2_vbus>;
};
&usbotg1 {
disable-over-current;
dr_mode = "otg";

24
arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
View File

@ -59,6 +59,22 @@ reg_sound_3v3: regulator-sound-3v3 {
regulator-name = "VCC3V3_ANALOG";
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "USB_OTG1_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
compatible = "regulator-fixed";
regulator-name = "USB_OTG2_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
enable-active-high;
@ -177,6 +193,14 @@ &sai1 {
};
/* USB */
&usbphynop1 {
vbus-supply = <&reg_usb_otg1_vbus>;
};
&usbphynop2 {
vbus-supply = <&reg_usb_otg2_vbus>;
};
&usbotg1 {
disable-over-current;
dr_mode = "otg";

1
arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
View File

@ -67,6 +67,7 @@ flash0: flash@0 {
spi-max-frequency = <62000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
vcc-supply = <&buck5>;
partitions {
compatible = "fixed-partitions";

332
arch/arm64/boot/dts/freescale/imx93-var-som.dtsi
View File

@ -12,7 +12,35 @@ /{
model = "Variscite VAR-SOM-MX93 module";
compatible = "variscite,var-som-mx93", "fsl,imx93";
mmc_pwrseq: mmc-pwrseq {
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"IN1L", "Microphone Jack",
"IN1R", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
simple-audio-card,mclk-fs = <256>;
codec_dai: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
};
usdhc3_pwrseq: mmc-pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
@ -70,6 +98,175 @@ led@1 {
};
};
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep", "gpio";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
pinctrl-2 = <&pinctrl_lpi2c3_gpio>;
scl-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
status = "okay";
pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <2237500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4{
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5{
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
wm8904: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
#sound-dai-cells = <0>;
clocks = <&clk IMX93_CLK_SAI1_GATE>;
clock-names = "mclk";
AVDD-supply = <&buck5>;
CPVDD-supply = <&buck5>;
DBVDD-supply = <&buck4>;
DCVDD-supply = <&buck5>;
MICVDD-supply = <&buck5>;
wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
"soft", "music";
/*
* Config registers per name, respectively:
* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
*/
wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
/* GPIO1 = DMIC_CLK, don't touch others */
wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
};
};
&lpspi8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi8>;
cs-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
status = "okay";
/* Resistive touch controller */
ads7846: touchscreen@0 {
compatible = "ti,ads7846";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_restouch>;
interrupt-parent = <&gpio4>;
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <1000000>;
pendown-gpio = <&gpio4 29 0>;
vcc-supply = <&buck5>;
ti,x-min = /bits/ 16 <125>;
ti,x-max = /bits/ 16 <4008>;
ti,y-min = /bits/ 16 <282>;
ti,y-max = /bits/ 16 <3864>;
ti,x-plate-ohms = /bits/ 16 <180>;
ti,pressure-max = /bits/ 16 <255>;
ti,debounce-max = /bits/ 16 <10>;
ti,debounce-tol = /bits/ 16 <3>;
ti,debounce-rep = /bits/ 16 <1>;
ti,settle-delay-usec = /bits/ 16 <150>;
ti,keep-vref-on;
wakeup-source;
};
};
/* BT module */
&lpuart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart5>, <&pinctrl_bluetooth>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&sai1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_sai1>;
pinctrl-1 = <&pinctrl_sai1_sleep>;
assigned-clocks = <&clk IMX93_CLK_SAI1>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
@ -81,7 +278,27 @@ &usdhc1 {
status = "okay";
};
/* WiFi */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>;
pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>;
bus-width = <4>;
mmc-pwrseq = <&usdhc3_pwrseq>;
non-removable;
wakeup-source;
status = "okay";
};
&iomuxc {
pinctrl_bluetooth: bluetoothgrp {
fsl,pins = <
MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
@ -108,6 +325,68 @@ MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp {
fsl,pins = <
MX93_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e
MX93_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e
>;
};
pinctrl_lpspi8: lpspi8grp {
fsl,pins = <
MX93_PAD_GPIO_IO12__GPIO2_IO12 0x31e
MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x31e
MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x31e
MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x31e
>;
};
pinctrl_lpuart5: lpuart5grp {
fsl,pins = <
MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
>;
};
pinctrl_restouch: restouchgrp {
fsl,pins = <
MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x31e
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e
MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e
MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e
MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e
MX93_PAD_UART2_RXD__SAI1_MCLK 0x31e
>;
};
pinctrl_sai1_sleep: sai1-sleepgrp {
fsl,pins = <
MX93_PAD_SAI1_TXC__GPIO1_IO12 0x31e
MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x31e
MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x31e
MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x31e
MX93_PAD_UART2_RXD__GPIO1_IO06 0x31e
MX93_PAD_I2C2_SDA__GPIO1_IO03 0x31e
MX93_PAD_I2C2_SCL__GPIO1_IO02 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
@ -123,4 +402,55 @@ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 /* SDIO_B_CLK */
MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 /* SDIO_B_CMD */
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 /* SDIO_B_D0 */
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 /* SDIO_B_D1 */
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 /* SDIO_B_D2 */
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 /* SDIO_B_D3 */
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e /* SDIO_B_CLK */
MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e /* SDIO_B_CMD */
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e /* SDIO_B_D0 */
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e /* SDIO_B_D1 */
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e /* SDIO_B_D2 */
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e /* SDIO_B_D3 */
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe /* SDIO_B_CLK */
MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe /* SDIO_B_CMD */
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe /* SDIO_B_D0 */
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe /* SDIO_B_D1 */
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe /* SDIO_B_D2 */
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe /* SDIO_B_D3 */
>;
};
pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
fsl,pins = <
MX93_PAD_SD3_CLK__GPIO3_IO20 0x400
MX93_PAD_SD3_CMD__GPIO3_IO21 0x400
MX93_PAD_SD3_DATA0__GPIO3_IO22 0x400
MX93_PAD_SD3_DATA1__GPIO3_IO23 0x400
MX93_PAD_SD3_DATA2__GPIO3_IO24 0x400
MX93_PAD_SD3_DATA3__GPIO3_IO25 0x400
>;
};
pinctrl_usdhc3_wlan: usdhc3-wlangrp {
fsl,pins = <
MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e /* WIFI_REG_ON */
MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x51e /* WIFI_PWR_EN */
>;
};
};

6
arch/arm64/boot/dts/freescale/imx94.dtsi
View File

@ -1190,5 +1190,11 @@ wdog3: watchdog@49220000 {
status = "disabled";
};
};
ddr-pmu@4e090dc0 {
compatible = "fsl,imx94-ddr-pmu", "fsl,imx93-ddr-pmu";
reg = <0x0 0x4e090dc0 0x0 0x200>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
};
};
};

3
arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
View File

@ -61,6 +61,7 @@ chosen {
fan0: pwm-fan {
compatible = "pwm-fan";
fan-supply = <&reg_vcc_12v>;
#cooling-cells = <2>;
cooling-levels = <64 128 192 255>;
pwms = <&tpm6 0 4000000 PWM_POLARITY_INVERTED>;
@ -556,6 +557,8 @@ &pcie0 {
pinctrl-names = "default";
reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_m2_pwr>;
vpcie3v3aux-supply = <&reg_m2_pwr>;
supports-clkreq;
status = "okay";
};

3
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
View File

@ -542,6 +542,8 @@ &pcie0 {
pinctrl-names = "default";
reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie0>;
vpcie3v3aux-supply = <&reg_pcie0>;
supports-clkreq;
status = "okay";
};
@ -557,6 +559,7 @@ &pcie1 {
pinctrl-names = "default";
reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_slot_pwr>;
vpcie3v3aux-supply = <&reg_slot_pwr>;
status = "okay";
};

695
arch/arm64/boot/dts/freescale/imx95-19x19-verdin-evk.dts Normal file
View File

@ -0,0 +1,695 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 NXP
* Copyright 2025 Marek Vasut <marek.vasut@mailbox.org>
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx95.dtsi"
#define FALLING_EDGE 1
#define RISING_EDGE 2
#define BRD_SM_CTRL_SD3_WAKE 0x8000 /* PCAL6408A-0 */
#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /* PCAL6408A-4 */
#define BRD_SM_CTRL_BT_WAKE 0x8002 /* PCAL6408A-5 */
#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /* PCAL6408A-6 */
#define BRD_SM_CTRL_BUTTON 0x8004 /* PCAL6408A-7 */
/ {
model = "i.MX 95 Verdin Evaluation Kit (EVK)";
compatible = "toradex,verdin-imx95-19x19-evk", "fsl,imx95";
aliases {
ethernet0 = &enetc_port0;
ethernet1 = &enetc_port1;
ethernet2 = &enetc_port2;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c4 = &lpi2c5;
i2c5 = &lpi2c6;
i2c6 = &lpi2c7;
i2c7 = &lpi2c8;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart1;
};
chosen {
stdout-path = &lpuart1;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux_cma: linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x80000000 0 0x7f000000>;
size = <0 0x3c000000>;
linux,cma-default;
reusable;
};
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "+V1.8_SW";
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_SW";
};
reg_m2_pwr: regulator-m2-pwr {
compatible = "regulator-fixed";
regulator-name = "M.2-power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 4 GPIO_ACTIVE_LOW>;
};
reg_pcie0: regulator-pcie {
compatible = "regulator-fixed";
regulator-name = "PCIE_WLAN_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_m2_pwr>;
gpio = <&i2c7_pcal6524 18 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VDD_SD2_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <12000>;
};
usdhc3_pwrseq: usdhc3-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&i2c7_pcal6524 11 GPIO_ACTIVE_HIGH>;
};
sound-wm8904 {
compatible = "fsl,imx-audio-wm8904";
model = "wm8904-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8904>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"AMIC", "MICBIAS",
"IN2L", "AMIC";
};
};
&enetc_port0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enetc0>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
status = "okay";
};
&flexspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi1>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi1_reset>;
reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <200000000>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
};
};
&lpi2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c4>;
status = "okay";
wm8904: codec@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8904";
reg = <0x1a>;
clocks = <&scmi_clk IMX95_CLK_SAI3>;
clock-names = "mclk";
AVDD-supply = <&reg_1p8v>;
CPVDD-supply = <&reg_1p8v>;
DBVDD-supply = <&reg_1p8v>;
DCVDD-supply = <&reg_1p8v>;
MICVDD-supply = <&reg_1p8v>;
};
};
&lpi2c5 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c5>;
status = "okay";
};
&lpi2c6 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c6>;
status = "okay";
};
&lpi2c7 {
clock-frequency = <1000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c7>;
status = "okay";
i2c7_pcal6524: i2c7-gpio@23 {
compatible = "nxp,pcal6524";
reg = <0x23>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c7_pcal6524>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio5>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
};
/* Current measurement at SoM 5V power output */
hwmon@41 {
compatible = "ti,ina219";
reg = <0x41>;
shunt-resistor = <10000>;
};
/* Current measurement at Board power input */
hwmon@45 {
compatible = "ti,ina219";
reg = <0x45>;
shunt-resistor = <10000>;
};
eeprom@50 {
compatible = "st,24c02";
reg = <0x50>;
};
ptn5110: tcpc@52 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
interrupt-parent = <&gpio5>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
typec_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec_con_hs: endpoint {
remote-endpoint = <&usb3_data_hs>;
};
};
port@1 {
reg = <1>;
typec_con_ss: endpoint {
remote-endpoint = <&usb3_data_ss>;
};
};
};
};
};
};
&lpuart1 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&mu7 {
status = "okay";
};
&netcmix_blk_ctrl {
status = "okay";
};
&netc_blk_ctrl {
status = "okay";
};
&netc_emdio {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emdio>;
status = "okay";
ethphy0: ethernet-phy@1 {
reg = <1>;
realtek,clkout-disable;
};
};
&pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
reset-gpio = <&i2c7_pcal6524 17 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie0>;
status = "okay";
};
&pcie1 {
pinctrl-0 = <&pinctrl_pcie1>;
pinctrl-names = "default";
reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
status = "okay";
};
&sai1 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI1>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>,
<3612672000>, <393216000>,
<361267200>, <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&sai3 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI3>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>,
<3612672000>, <393216000>,
<361267200>, <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&usb3 {
status = "okay";
};
&usb3_dwc3 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
role-switch-default-mode = "peripheral";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
status = "okay";
port {
usb3_data_hs: endpoint {
remote-endpoint = <&typec_con_hs>;
};
};
};
&usb3_phy {
fsl,phy-tx-preemp-amp-tune-microamp = <600>;
orientation-switch;
status = "okay";
port {
usb3_data_ss: endpoint {
remote-endpoint = <&typec_con_ss>;
};
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-3 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
mmc-pwrseq = <&usdhc3_pwrseq>;
vmmc-supply = <&reg_pcie0>;
bus-width = <4>;
keep-power-in-suspend;
non-removable;
status = "okay";
};
&scmi_misc {
nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE FALLING_EDGE
BRD_SM_CTRL_PCIE1_WAKE FALLING_EDGE
BRD_SM_CTRL_BT_WAKE FALLING_EDGE
BRD_SM_CTRL_PCIE2_WAKE FALLING_EDGE
BRD_SM_CTRL_BUTTON FALLING_EDGE>;
};
&wdog3 {
fsl,ext-reset-output;
status = "okay";
};
&scmi_iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins =
<IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x3fe>;
};
pinctrl_emdio: emdiogrp {
fsl,pins =
<IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e>,
<IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e>;
};
pinctrl_enetc0: enetc0grp {
fsl,pins =
<IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e>,
<IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e>,
<IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e>,
<IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e>,
<IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>,
<IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>,
<IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>,
<IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>,
<IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>,
<IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>,
<IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>,
<IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>;
};
pinctrl_flexspi1: flexspi1grp {
fsl,pins =
<IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe>,
<IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe>,
<IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe>,
<IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe>,
<IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe>,
<IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe>,
<IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe>,
<IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x3fe>,
<IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x3fe>,
<IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x3fe>,
<IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x3fe>;
};
pinctrl_flexspi1_reset: flexspi1-reset-grp {
fsl,pins =
<IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x3fe>;
};
pinctrl_hp: hpgrp {
fsl,pins =
<IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e>;
};
pinctrl_i2c4_pcal6408: i2c4pcal6498grp {
fsl,pins =
<IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x31e>;
};
pinctrl_i2c7_pcal6524: i2c7pcal6524grp {
fsl,pins =
<IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e>;
};
pinctrl_lpi2c4: lpi2c4grp {
fsl,pins =
<IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e>,
<IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e>;
};
pinctrl_lpi2c5: lpi2c5grp {
fsl,pins =
<IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e>,
<IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e>;
};
pinctrl_lpi2c6: lpi2c6grp {
fsl,pins =
<IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x40000b9e>,
<IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x40000b9e>;
};
pinctrl_lpi2c7: lpi2c7grp {
fsl,pins =
<IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e>,
<IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e>;
};
pinctrl_pcal6416: pcal6416grp {
fsl,pins =
<IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins =
<IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins =
<IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e>;
};
pinctrl_pdm: pdmgrp {
fsl,pins =
<IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e>,
<IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins =
<IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e>;
};
pinctrl_sai1: sai1grp {
fsl,pins =
<IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x31e>,
<IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e>,
<IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e>,
<IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x31e>;
};
pinctrl_sai2: sai2grp {
fsl,pins =
<IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e>,
<IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e>,
<IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e>,
<IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e>,
<IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e>,
<IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e>,
<IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e>,
<IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e>,
<IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e>,
<IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e>,
<IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e>;
};
pinctrl_sai3: sai3grp {
fsl,pins =
<IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e>,
<IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e>,
<IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e>,
<IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e>,
<IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e>;
};
pinctrl_tpm6: tpm6grp {
fsl,pins =
<IMX95_PAD_GPIO_IO19__TPM6_CH2 0x51e>;
};
pinctrl_typec: typecgrp {
fsl,pins =
<IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e>;
};
pinctrl_uart1: uart1grp {
fsl,pins =
<IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>,
<IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins =
<IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>,
<IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>,
<IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>,
<IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>,
<IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>,
<IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>,
<IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>,
<IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>,
<IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>,
<IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>,
<IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins =
<IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>,
<IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>,
<IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>,
<IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>,
<IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>,
<IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>,
<IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>,
<IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>,
<IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>,
<IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>,
<IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins =
<IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>,
<IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>,
<IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>,
<IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>,
<IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>,
<IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>,
<IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>,
<IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>,
<IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>,
<IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>,
<IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins =
<IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins =
<IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>,
<IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>,
<IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>,
<IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>,
<IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>,
<IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>,
<IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins =
<IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>,
<IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>,
<IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>,
<IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>,
<IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>,
<IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>,
<IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins =
<IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>,
<IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>,
<IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>,
<IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>,
<IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>,
<IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>,
<IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins =
<IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e>,
<IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e>,
<IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e>,
<IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e>,
<IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e>,
<IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e>;
};
};

277
arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts Normal file
View File

@ -0,0 +1,277 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2025 Toradex
*
* https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95
* https://www.toradex.com/products/carrier-board/smarc-development-board-kit
*/
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
#include "imx95-toradex-smarc.dtsi"
/ {
model = "Toradex SMARC iMX95 on Toradex SMARC Development Board";
compatible = "toradex,smarc-imx95-dev",
"toradex,smarc-imx95",
"fsl,imx95";
reg_carrier_1p8v: regulator-carrier-1p8v {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "On-carrier 1V8";
};
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "tdx-smarc-wm8904";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"Microphone Jack", "MICBIAS",
"IN1L", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
codec_dai: simple-audio-card,codec {
clocks = <&scmi_clk IMX95_CLK_SAI3>;
sound-dai = <&wm8904_1a>;
};
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
};
};
/* SMARC GBE0 */
&enetc_port0 {
status = "okay";
};
/* SMARC GBE1 */
&enetc_port1 {
status = "okay";
};
/* SMARC CAN0 */
&flexcan1 {
status = "okay";
};
/* SMARC CAN1 */
&flexcan2 {
status = "okay";
};
&gpio2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio12>, <&pinctrl_gpio13>;
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio10>, <&pinctrl_gpio11>;
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio2>,
<&pinctrl_gpio3>,
<&pinctrl_gpio4>,
<&pinctrl_gpio6>,
<&pinctrl_gpio8>,
<&pinctrl_gpio9>;
};
/* SMARC I2C_CAM0 */
&i2c_cam0 {
status = "okay";
};
/* SMARC I2C_CAM1 */
&i2c_cam1 {
status = "okay";
};
/* SMARC I2C_GP */
&lpi2c2 {
status = "okay";
wm8904_1a: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>, <&pinctrl_sai3_mclk>;
#sound-dai-cells = <0>;
clocks = <&scmi_clk IMX95_CLK_SAI3>;
clock-names = "mclk";
AVDD-supply = <&reg_carrier_1p8v>;
CPVDD-supply = <&reg_carrier_1p8v>;
DBVDD-supply = <&reg_carrier_1p8v>;
DCVDD-supply = <&reg_carrier_1p8v>;
MICVDD-supply = <&reg_carrier_1p8v>;
};
temperature-sensor@4f {
compatible = "ti,tmp1075";
reg = <0x4f>;
};
eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
};
};
/* SMARC I2C_PM */
&lpi2c3 {
clock-frequency = <100000>;
status = "okay";
fan_controller: fan@18 {
compatible = "ti,amc6821";
reg = <0x18>;
#pwm-cells = <2>;
fan {
cooling-levels = <255>;
pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>;
};
};
/* Current measurement into module VCC */
hwmon@40 {
compatible = "ti,ina226";
reg = <0x40>;
shunt-resistor = <5000>;
};
};
/* SMARC I2C_LCD */
&lpi2c5 {
status = "okay";
i2c-mux@70 {
compatible = "nxp,pca9543";
reg = <0x70>;
i2c-mux-idle-disconnect;
#address-cells = <1>;
#size-cells = <0>;
/* I2C on DSI Connector Pins 4/6 */
i2c_dsi_0: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
/* I2C on DSI Connector Pins 52/54 */
i2c_dsi_1: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
/* SMARC SPI0 */
&lpspi6 {
status = "okay";
};
/* SMARC SER1, used as the Linux Console */
&lpuart1 {
status = "okay";
};
/* SMARC SER0, RS485 */
&lpuart2 {
linux,rs485-enabled-at-boot-time;
rs485-rts-active-low;
rs485-rx-during-tx;
status = "okay";
};
/* SMARC SER3, RS232 */
&lpuart3 {
status = "okay";
};
/* SMARC MDIO, shared between all ethernet ports */
&netc_emdio {
status = "okay";
ethphy3: ethernet-phy@4 {
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio7>;
interrupt-parent = <&gpio5>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
};
};
/* SMARC PCIE_A / M2 Key B */
&pcie0 {
status = "okay";
};
/* SMARC PCIE_B / M2 Key E */
&pcie1 {
status = "okay";
};
/* SMARC I2S0 */
&sai3 {
status = "okay";
};
/* SMARC LCD0_BKLT_PWM */
&tpm3 {
status = "okay";
};
/* SMARC LCD1_BKLT_PWM */
&tpm4 {
status = "okay";
};
/* SMARC GPIO5 as PWM */
&tpm5 {
status = "okay";
};
/* SMARC USB0 */
&usb2 {
status = "okay";
};
/* SMARC USB1..4 */
&usb3 {
status = "okay";
};
&usb3_dwc3 {
status = "okay";
};
&usb3_phy {
status = "okay";
};
/* SMARC SDIO */
&usdhc2 {
status = "okay";
};

1155
arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi Normal file
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File diff suppressed because it is too large Load Diff

75
arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
View File

@ -39,6 +39,8 @@ aliases {
serial5 = &lpuart6;
serial6 = &lpuart7;
serial7 = &lpuart8;
spi0 = &flexspi1;
spi1 = &lpspi3;
};
chosen {
@ -144,6 +146,13 @@ sound {
model = "tqm-tlv320aic32";
audio-codec = <&tlv320aic3x04>;
audio-cpu = <&sai3>;
audio-routing =
"IN3_L", "Mic Jack",
"Mic Jack", "Mic Bias",
"IN1_L", "Line In Jack",
"IN1_R", "Line In Jack",
"Line Out Jack", "LOL",
"Line Out Jack", "LOR";
};
};
@ -172,15 +181,11 @@ pcie2-clk-en-hog {
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_3v3>;
status = "okay";
};
&flexcan3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan3>;
xceiver-supply = <&reg_3v3>;
status = "okay";
};
@ -204,15 +209,12 @@ eeprom2: eeprom@57 {
};
&lpspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi3>;
cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>, <&gpio2 7 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* SER0 */
&lpuart1 {
status = "disabled";
status = "reserved";
};
/* SER3 */
@ -232,27 +234,11 @@ &lpuart8 {
/* X44 mPCIe */
&pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
clocks = <&scmi_clk IMX95_CLK_HSIO>,
<&pcieclk 1>,
<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
reset-gpio = <&expander2 9 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* X22 PCIe x1 socket */
&pcie1 {
pinctrl-0 = <&pinctrl_pcie1>;
pinctrl-names = "default";
clocks = <&scmi_clk IMX95_CLK_HSIO>,
<&pcieclk 0>,
<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
reset-gpio = <&expander2 10 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -261,39 +247,9 @@ &reg_sdvmmc {
};
&sai3 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI3>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>,
<3612672000>, <393216000>,
<361267200>, <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&sai5 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI5>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>,
<3612672000>, <393216000>,
<361267200>, <12288000>;
};
/* X4 */
&usb2 {
srp-disable;
@ -305,20 +261,9 @@ &usb2 {
status = "okay";
};
/* X16 */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
pinctrl-3 = <&pinctrl_usdhc2>;
vmmc-supply = <&reg_sdvmmc>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
no-1-8-v;
no-mmc;
no-sdio;
disable-wp;
bus-width = <4>;
status = "okay";
};

153
arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi
View File

@ -106,16 +106,25 @@ &netc_timer {
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
};
&flexcan3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan3>;
};
&flexspi1 {
pinctrl-names = "default", "sleep";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi1>;
pinctrl-1 = <&pinctrl_flexspi1>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-max-frequency = <66000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
vcc-supply = <&reg_1v8>;
@ -156,9 +165,8 @@ &gpio2 {
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-1 = <&pinctrl_lpi2c1>;
status = "okay";
tmp1075: temperature-sensor@4a {
@ -195,6 +203,7 @@ m24c64: eeprom@54 {
eeprom@58 {
compatible = "atmel,24c64d-wl";
reg = <0x58>;
pagesize = <32>;
vcc-supply = <&reg_1v8>;
};
@ -202,6 +211,7 @@ eeprom@58 {
eeprom@5c {
compatible = "atmel,24c64d-wl";
reg = <0x5c>;
pagesize = <32>;
vcc-supply = <&reg_1v8>;
};
@ -255,9 +265,11 @@ expander1: gpio@75 {
/* I2C_CAM0 */
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
dp_bridge: dp-bridge@f {
@ -292,21 +304,31 @@ dp_dsi_in: endpoint {
/* I2C_CAM1 */
&lpi2c4 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_lpi2c4>;
pinctrl-1 = <&pinctrl_lpi2c4>;
pinctrl-1 = <&pinctrl_lpi2c4_gpio>;
sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* I2C_LCD */
&lpi2c6 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_lpi2c6>;
pinctrl-1 = <&pinctrl_lpi2c6>;
pinctrl-1 = <&pinctrl_lpi2c6_gpio>;
sda-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&lpspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi3>;
cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>, <&gpio2 7 GPIO_ACTIVE_LOW>;
};
/* SER0 */
&lpuart1 {
pinctrl-names = "default";
@ -375,6 +397,63 @@ ethphy3: ethernet-phy@3 {
};
};
&pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
clocks = <&scmi_clk IMX95_CLK_HSIO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
<&pcieclk 1>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
reset-gpios = <&expander2 9 GPIO_ACTIVE_LOW>;
};
&pcie1 {
pinctrl-0 = <&pinctrl_pcie1>;
pinctrl-names = "default";
clocks = <&scmi_clk IMX95_CLK_HSIO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
<&pcieclk 0>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
reset-gpios = <&expander2 10 GPIO_ACTIVE_LOW>;
};
&sai3 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI3>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>,
<3612672000>, <393216000>,
<361267200>, <12288000>;
fsl,sai-mclk-direction-output;
};
&sai5 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI5>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>,
<3612672000>, <393216000>,
<361267200>, <12288000>;
};
&scmi_bbm {
linux,code = <KEY_POWER>;
};
@ -425,11 +504,10 @@ &usb3_phy {
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-3 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
no-sdio;
@ -437,6 +515,18 @@ &usdhc1 {
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
vmmc-supply = <&reg_sdvmmc>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
no-1-8-v;
disable-wp;
bus-width = <4>;
};
&wdog3 {
status = "okay";
};
@ -497,12 +587,12 @@ pinctrl_flexcan3: flexcan3grp {
};
pinctrl_flexspi1: flexspi1grp {
fsl,pins = <IMX95_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x11e>,
<IMX95_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x11e>,
<IMX95_PAD_SD3_DATA0__FLEXSPI1_A_DATA_BIT0 0x11e>,
<IMX95_PAD_SD3_DATA1__FLEXSPI1_A_DATA_BIT1 0x11e>,
<IMX95_PAD_SD3_DATA2__FLEXSPI1_A_DATA_BIT2 0x11e>,
<IMX95_PAD_SD3_DATA3__FLEXSPI1_A_DATA_BIT3 0x11e>;
fsl,pins = <IMX95_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x19e>,
<IMX95_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x19e>,
<IMX95_PAD_SD3_DATA0__FLEXSPI1_A_DATA_BIT0 0x19e>,
<IMX95_PAD_SD3_DATA1__FLEXSPI1_A_DATA_BIT1 0x19e>,
<IMX95_PAD_SD3_DATA2__FLEXSPI1_A_DATA_BIT2 0x19e>,
<IMX95_PAD_SD3_DATA3__FLEXSPI1_A_DATA_BIT3 0x19e>;
};
pinctrl_gpio1: gpio1grp {
@ -527,14 +617,29 @@ pinctrl_lpi2c3: lpi2c3grp {
<IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x4000191e>;
};
pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp {
fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x4000191e>,
<IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x4000191e>;
};
pinctrl_lpi2c4: lpi2c4grp {
fsl,pins = <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x4000191e>,
<IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x4000191e>;
fsl,pins = <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x4000191e>,
<IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x4000191e>;
};
pinctrl_lpi2c4_gpio: lpi2c4-gpiogrp {
fsl,pins = <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x4000191e>,
<IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x4000191e>;
};
pinctrl_lpi2c6: lpi2c6grp {
fsl,pins = <IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x4000191e>,
<IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x4000191e>;
fsl,pins = <IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x4000191e>,
<IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x4000191e>;
};
pinctrl_lpi2c6_gpio: lpi2c6-gpiogrp {
fsl,pins = <IMX95_PAD_GPIO_IO02__GPIO2_IO_BIT2 0x4000191e>,
<IMX95_PAD_GPIO_IO03__GPIO2_IO_BIT3 0x4000191e>;
};
pinctrl_lpspi3: lpspi3grp {
@ -617,7 +722,7 @@ pinctrl_tpm4: tpm4grp {
fsl,pins = <IMX95_PAD_GPIO_IO05__TPM4_CH0 0x51e>;
};
pinctrl_tpm5: tpm4grp {
pinctrl_tpm5: tpm5grp {
fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x51e>;
};

2
arch/arm64/boot/dts/freescale/imx95.dtsi
View File

@ -945,7 +945,7 @@ flexcan3: can@42600000 {
};
flexspi1: spi@425e0000 {
compatible = "nxp,imx8mm-fspi";
compatible = "nxp,imx95-fspi", "nxp,imx8mm-fspi";
reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>;
reg-names = "fspi_base", "fspi_mmap";
#address-cells = <1>;

7
arch/arm64/boot/dts/freescale/mba8mx.dtsi
View File

@ -141,6 +141,13 @@ sound: sound {
model = "tqm-tlv320aic32";
ssi-controller = <&sai3>;
audio-codec = <&tlv320aic3x04>;
audio-routing =
"IN3_L", "Mic Jack",
"Mic Jack", "Mic Bias",
"IN1_L", "Line In Jack",
"IN1_R", "Line In Jack",
"Line Out Jack", "LOL",
"Line Out Jack", "LOR";
};
};

7
arch/arm64/boot/dts/freescale/mba8xx.dtsi
View File

@ -128,6 +128,13 @@ sound {
model = "tqm-tlv320aic32";
audio-codec = <&tlv320aic3x04>;
ssi-controller = <&sai1>;
audio-routing =
"IN3_L", "Mic Jack",
"Mic Jack", "Mic Bias",
"IN1_L", "Line In Jack",
"IN1_R", "Line In Jack",
"Line Out Jack", "LOL",
"Line Out Jack", "LOR";
};
};

58
arch/arm64/boot/dts/freescale/s32g2.dtsi
View File

@ -3,7 +3,7 @@
* NXP S32G2 SoC family
*
* Copyright (c) 2021 SUSE LLC
* Copyright 2017-2021, 2024 NXP
* Copyright 2017-2021, 2024-2025 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -727,6 +727,62 @@ usdhc0: mmc@402f0000 {
status = "disabled";
};
gmac0: ethernet@4033c000 {
compatible = "nxp,s32g2-dwmac";
reg = <0x4033c000 0x2000>, /* gmac IP */
<0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
status = "disabled";
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <5>;
queue0 {
};
queue1 {
};
queue2 {
};
queue3 {
};
queue4 {
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
queue0 {
};
queue1 {
};
queue2 {
};
queue3 {
};
queue4 {
};
};
gmac0mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
gic: interrupt-controller@50800000 {
compatible = "arm,gic-v3";
reg = <0x50800000 0x10000>,

18
arch/arm64/boot/dts/freescale/s32g274a-evb.dts
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 SUSE LLC
* Copyright 2019-2021, 2024 NXP
* Copyright 2019-2021, 2024-2025 NXP
*/
/dts-v1/;
@ -14,6 +14,7 @@ / {
compatible = "nxp,s32g274a-evb", "nxp,s32g2";
aliases {
ethernet0 = &gmac0;
serial0 = &uart0;
};
@ -43,3 +44,18 @@ &usdhc0 {
no-1-8-v;
status = "okay";
};
&gmac0 {
clocks = <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>;
clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
phy-mode = "rgmii-id";
phy-handle = <&rgmiiaphy4>;
status = "okay";
};
&gmac0mdio {
/* KSZ 9031 on RGMII */
rgmiiaphy4: ethernet-phy@4 {
reg = <4>;
};
};

16
arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
View File

@ -14,6 +14,7 @@ / {
compatible = "nxp,s32g274a-rdb2", "nxp,s32g2";
aliases {
ethernet0 = &gmac0;
serial0 = &uart0;
serial1 = &uart1;
};
@ -77,3 +78,18 @@ &usdhc0 {
no-1-8-v;
status = "okay";
};
&gmac0 {
clocks = <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>;
clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
phy-mode = "rgmii-id";
phy-handle = <&rgmiiaphy1>;
status = "okay";
};
&gmac0mdio {
/* KSZ 9031 on RGMII */
rgmiiaphy1: ethernet-phy@1 {
reg = <1>;
};
};

58
arch/arm64/boot/dts/freescale/s32g3.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2021-2024 NXP
* Copyright 2021-2025 NXP
*
* Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
* Ciprian Costea <ciprianmarian.costea@nxp.com>
@ -804,6 +804,62 @@ usdhc0: mmc@402f0000 {
status = "disabled";
};
gmac0: ethernet@4033c000 {
compatible = "nxp,s32g2-dwmac";
reg = <0x4033c000 0x2000>, /* gmac IP */
<0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
status = "disabled";
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <5>;
queue0 {
};
queue1 {
};
queue2 {
};
queue3 {
};
queue4 {
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
queue0 {
};
queue1 {
};
queue2 {
};
queue3 {
};
queue4 {
};
};
gmac0mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
swt8: watchdog@40500000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <40500000 0x1000>;

18
arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2021-2024 NXP
* Copyright 2021-2025 NXP
*
* NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)
*/
@ -15,6 +15,7 @@ / {
compatible = "nxp,s32g399a-rdb3", "nxp,s32g3";
aliases {
ethernet0 = &gmac0;
mmc0 = &usdhc0;
serial0 = &uart0;
serial1 = &uart1;
@ -93,3 +94,18 @@ &usdhc0 {
disable-wp;
status = "okay";
};
&gmac0 {
clocks = <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>;
clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
phy-mode = "rgmii-id";
phy-handle = <&rgmiiaphy1>;
status = "okay";
};
&gmac0mdio {
/* KSZ 9031 on RGMII */
rgmiiaphy1: ethernet-phy@1 {
reg = <1>;
};
};

7
arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi
View File

@ -98,6 +98,13 @@ sound {
model = "tqm-tlv320aic32";
ssi-controller = <&sai1>;
audio-codec = <&tlv320aic3x04>;
audio-routing =
"IN3_L", "Mic Jack",
"Mic Jack", "Mic Bias",
"IN1_L", "Line In Jack",
"IN1_R", "Line In Jack",
"Line Out Jack", "LOL",
"Line Out Jack", "LOR";
};
};