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drm/i915: pass dev_priv explicitly to TRANS_VRR_CTL

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Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_VRR_CTL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/d86be64197d547085e857b09dacd21f4ee6b1517.1715183162.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2024-05-08 18:47:47 +03:00
parent 6a3691ca47
commit 975a0f68f0
2 changed files with 9 additions and 6 deletions
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13
drivers/gpu/drm/i915/display/intel_vrr.c
View File

@ -213,13 +213,15 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
0, PIPE_VBLANK_WITH_DELAY);
if (!crtc_state->vrr.flipline) {
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0);
intel_de_write(dev_priv,
TRANS_VRR_CTL(dev_priv, cpu_transcoder), 0);
return;
}
intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
trans_vrr_ctl(crtc_state));
intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
}
@ -263,7 +265,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
VRR_VSYNC_START(crtc_state->vrr.vsync_start));
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
}
@ -276,7 +278,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
if (!old_crtc_state->vrr.enable)
return;
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
trans_vrr_ctl(old_crtc_state));
intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(cpu_transcoder),
VRR_STATUS_VRR_EN_LIVE, 1000);
@ -292,7 +294,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 trans_vrr_ctl, trans_vrr_vsync;
trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
trans_vrr_ctl = intel_de_read(dev_priv,
TRANS_VRR_CTL(dev_priv, cpu_transcoder));
crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;

2
drivers/gpu/drm/i915/i915_reg.h
View File

@ -1233,7 +1233,7 @@
#define _TRANS_VRR_CTL_B 0x61420
#define _TRANS_VRR_CTL_C 0x62420
#define _TRANS_VRR_CTL_D 0x63420
#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
#define VRR_CTL_VRR_ENABLE REG_BIT(31)
#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)