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drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks
We use intel_display for function hooks of shared_dpll_mgr and any function that gets called when we use for_each_shared_dpll. This also contains some opportunistic display->platform.xx changes all to reductate the use of drm_i915_private. --v2 -rebase --v3 -Don't use inline to_i915 [Jani] Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250212074542.3569452-5-suraj.kandpal@intel.com
This commit is contained in:
Suraj Kandpal
parent
bd867a00f7
commit
972259d93c
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@ -358,10 +358,10 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
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}
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}
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static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
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static int icl_calc_tbt_pll_link(struct intel_display *display,
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enum port port)
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{
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u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
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u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
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switch (val) {
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case DDI_CLK_SEL_NONE:
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@ -1367,7 +1367,7 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
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static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_display *display = to_intel_display(encoder);
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enum tc_port tc_port = intel_encoder_to_tc(encoder);
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const struct intel_ddi_buf_trans *trans;
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int n_entries, ln;
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@ -1376,17 +1376,17 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
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return;
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trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
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if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
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if (drm_WARN_ON_ONCE(display->drm, !trans))
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return;
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for (ln = 0; ln < 2; ln++) {
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int level;
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intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
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intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
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level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
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intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
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intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln),
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DKL_TX_PRESHOOT_COEFF_MASK |
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DKL_TX_DE_EMPAHSIS_COEFF_MASK |
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DKL_TX_VSWING_CONTROL_MASK,
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@ -1396,7 +1396,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
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level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
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intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
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intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln),
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DKL_TX_PRESHOOT_COEFF_MASK |
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DKL_TX_DE_EMPAHSIS_COEFF_MASK |
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DKL_TX_VSWING_CONTROL_MASK,
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@ -1404,10 +1404,10 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
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DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
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DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
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intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
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intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
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DKL_TX_DP20BITMODE, 0);
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if (IS_ALDERLAKE_P(dev_priv)) {
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if (display->platform.alderlake_p) {
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u32 val;
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
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@ -1423,7 +1423,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
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val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
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}
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intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
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intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
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DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
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DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
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val);
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@ -1551,14 +1551,14 @@ static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t
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}
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static struct intel_shared_dpll *
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_icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
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_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
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u32 clk_sel_mask, u32 clk_sel_shift)
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{
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enum intel_dpll_id id;
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id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
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id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
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return intel_get_shared_dpll_by_id(i915, id);
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return intel_get_shared_dpll_by_id(display, id);
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}
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static void adls_ddi_enable_clock(struct intel_encoder *encoder,
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@ -1597,10 +1597,10 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
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static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_display *display = to_intel_display(encoder);
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enum phy phy = intel_encoder_to_phy(encoder);
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return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
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return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy),
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ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
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ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
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}
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@ -1641,10 +1641,10 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
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static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_display *display = to_intel_display(encoder);
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enum phy phy = intel_encoder_to_phy(encoder);
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return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
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return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
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RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
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RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
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}
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@ -1694,12 +1694,12 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
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static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_display *display = to_intel_display(encoder);
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enum phy phy = intel_encoder_to_phy(encoder);
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enum intel_dpll_id id;
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u32 val;
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val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
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val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));
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val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
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val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
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id = val;
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@ -1712,7 +1712,7 @@ static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
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if (phy >= PHY_C)
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id += DPLL_ID_DG1_DPLL2;
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return intel_get_shared_dpll_by_id(i915, id);
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return intel_get_shared_dpll_by_id(display, id);
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}
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static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
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@ -1751,10 +1751,10 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
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struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_display *display = to_intel_display(encoder);
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enum phy phy = intel_encoder_to_phy(encoder);
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return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
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return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
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ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
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ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
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}
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@ -1859,13 +1859,13 @@ static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
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static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_display *display = to_intel_display(encoder);
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enum tc_port tc_port = intel_encoder_to_tc(encoder);
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enum port port = encoder->port;
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enum intel_dpll_id id;
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u32 tmp;
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tmp = intel_de_read(i915, DDI_CLK_SEL(port));
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tmp = intel_de_read(display, DDI_CLK_SEL(port));
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switch (tmp & DDI_CLK_SEL_MASK) {
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case DDI_CLK_SEL_TBT_162:
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@ -1884,12 +1884,12 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode
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return NULL;
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}
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return intel_get_shared_dpll_by_id(i915, id);
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return intel_get_shared_dpll_by_id(display, id);
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}
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static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_display *display = to_intel_display(encoder->base.dev);
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enum intel_dpll_id id;
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switch (encoder->port) {
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@ -1907,7 +1907,7 @@ static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
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return NULL;
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}
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return intel_get_shared_dpll_by_id(i915, id);
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return intel_get_shared_dpll_by_id(display, id);
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}
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static void skl_ddi_enable_clock(struct intel_encoder *encoder,
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@ -1958,12 +1958,12 @@ static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
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static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_display *display = to_intel_display(encoder);
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enum port port = encoder->port;
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enum intel_dpll_id id;
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u32 tmp;
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tmp = intel_de_read(i915, DPLL_CTRL2);
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tmp = intel_de_read(display, DPLL_CTRL2);
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/*
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* FIXME Not sure if the override affects both
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@ -1975,7 +1975,7 @@ static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
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id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
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DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
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return intel_get_shared_dpll_by_id(i915, id);
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return intel_get_shared_dpll_by_id(display, id);
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}
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void hsw_ddi_enable_clock(struct intel_encoder *encoder,
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@ -2009,12 +2009,12 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
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static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_display *display = to_intel_display(encoder);
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enum port port = encoder->port;
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enum intel_dpll_id id;
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u32 tmp;
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tmp = intel_de_read(i915, PORT_CLK_SEL(port));
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tmp = intel_de_read(display, PORT_CLK_SEL(port));
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switch (tmp & PORT_CLK_SEL_MASK) {
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case PORT_CLK_SEL_WRPLL1:
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@ -2042,7 +2042,7 @@ static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
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return NULL;
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}
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return intel_get_shared_dpll_by_id(i915, id);
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return intel_get_shared_dpll_by_id(display, id);
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}
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void intel_ddi_enable_clock(struct intel_encoder *encoder,
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@ -2122,13 +2122,13 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
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}
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static void
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tgl_dkl_phy_check_and_rewrite(struct drm_i915_private *dev_priv,
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tgl_dkl_phy_check_and_rewrite(struct intel_display *display,
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enum tc_port tc_port, u32 ln0, u32 ln1)
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{
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if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
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intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
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if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
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intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
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if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)))
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intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
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if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)))
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intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
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}
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static void
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@ -2136,24 +2136,23 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
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const struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
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enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
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u32 ln0, ln1, pin_assignment;
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u8 width;
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if (DISPLAY_VER(dev_priv) >= 14)
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if (DISPLAY_VER(display) >= 14)
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return;
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if (!intel_encoder_is_tc(&dig_port->base) ||
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intel_tc_port_in_tbt_alt_mode(dig_port))
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return;
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if (DISPLAY_VER(dev_priv) >= 12) {
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ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0));
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ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1));
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if (DISPLAY_VER(display) >= 12) {
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ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0));
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ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1));
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} else {
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ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
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ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
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ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port));
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ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port));
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}
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ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
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@ -2165,7 +2164,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
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switch (pin_assignment) {
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case 0x0:
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drm_WARN_ON(&dev_priv->drm,
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drm_WARN_ON(display->drm,
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!intel_tc_port_in_legacy_mode(dig_port));
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if (width == 1) {
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ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
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@ -2210,16 +2209,16 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
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MISSING_CASE(pin_assignment);
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}
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if (DISPLAY_VER(dev_priv) >= 12) {
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intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
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intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
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if (DISPLAY_VER(display) >= 12) {
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intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
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intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
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/* WA_14018221282 */
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if (IS_DISPLAY_VER(display, 12, 13))
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tgl_dkl_phy_check_and_rewrite(dev_priv, tc_port, ln0, ln1);
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tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1);
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} else {
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intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
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intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
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intel_de_write(display, MG_DP_MODE(0, tc_port), ln0);
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intel_de_write(display, MG_DP_MODE(1, tc_port), ln1);
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}
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}
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@ -3727,12 +3726,13 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
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static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_display *display = to_intel_display(encoder);
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enum tc_port tc_port = intel_encoder_to_tc(encoder);
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int ln;
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for (ln = 0; ln < 2; ln++)
|
||||
intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);
|
||||
intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln),
|
||||
DKL_PCS_DW5_CORE_SOFTRESET, 0);
|
||||
}
|
||||
|
||||
static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
|
||||
|
|
@ -4253,21 +4253,21 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
|
|||
struct intel_crtc_state *crtc_state,
|
||||
struct intel_shared_dpll *pll)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
struct intel_display *display = to_intel_display(encoder);
|
||||
enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
|
||||
struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
|
||||
bool pll_active;
|
||||
|
||||
if (drm_WARN_ON(&i915->drm, !pll))
|
||||
if (drm_WARN_ON(display->drm, !pll))
|
||||
return;
|
||||
|
||||
port_dpll->pll = pll;
|
||||
pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
|
||||
drm_WARN_ON(&i915->drm, !pll_active);
|
||||
pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
|
||||
drm_WARN_ON(display->drm, !pll_active);
|
||||
|
||||
icl_set_active_port_dpll(crtc_state, port_dpll_id);
|
||||
|
||||
crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
|
||||
crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
|
||||
&crtc_state->dpll_hw_state);
|
||||
}
|
||||
|
||||
|
|
@ -4356,12 +4356,12 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
|
|||
struct intel_crtc_state *crtc_state,
|
||||
struct intel_shared_dpll *pll)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
struct intel_display *display = to_intel_display(encoder);
|
||||
enum icl_port_dpll_id port_dpll_id;
|
||||
struct icl_port_dpll *port_dpll;
|
||||
bool pll_active;
|
||||
|
||||
if (drm_WARN_ON(&i915->drm, !pll))
|
||||
if (drm_WARN_ON(display->drm, !pll))
|
||||
return;
|
||||
|
||||
if (icl_ddi_tc_pll_is_tbt(pll))
|
||||
|
|
@ -4372,15 +4372,15 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
|
|||
port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
|
||||
|
||||
port_dpll->pll = pll;
|
||||
pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
|
||||
drm_WARN_ON(&i915->drm, !pll_active);
|
||||
pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
|
||||
drm_WARN_ON(display->drm, !pll_active);
|
||||
|
||||
icl_set_active_port_dpll(crtc_state, port_dpll_id);
|
||||
|
||||
if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
|
||||
crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
|
||||
crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
|
||||
else
|
||||
crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
|
||||
crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
|
||||
&crtc_state->dpll_hw_state);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -507,7 +507,6 @@ static void
|
|||
icl_tc_phy_aux_power_well_enable(struct intel_display *display,
|
||||
struct i915_power_well *power_well)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(display->drm);
|
||||
enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
|
||||
struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
|
||||
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
|
||||
|
|
@ -539,7 +538,7 @@ icl_tc_phy_aux_power_well_enable(struct intel_display *display,
|
|||
|
||||
tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx);
|
||||
|
||||
if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) &
|
||||
if (wait_for(intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)) &
|
||||
DKL_CMN_UC_DW27_UC_HEALTH, 1))
|
||||
drm_warn(display->drm,
|
||||
"Timeout waiting TC uC health\n");
|
||||
|
|
|
|||
|
|
@ -20,20 +20,20 @@ void intel_dkl_phy_init(struct drm_i915_private *i915)
|
|||
}
|
||||
|
||||
static void
|
||||
dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
|
||||
dkl_phy_set_hip_idx(struct intel_display *display, struct intel_dkl_phy_reg reg)
|
||||
{
|
||||
enum tc_port tc_port = DKL_REG_TC_PORT(reg);
|
||||
|
||||
drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS);
|
||||
drm_WARN_ON(display->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS);
|
||||
|
||||
intel_de_write(i915,
|
||||
intel_de_write(display,
|
||||
HIP_INDEX_REG(tc_port),
|
||||
HIP_INDEX_VAL(tc_port, reg.bank_idx));
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_dkl_phy_read - read a Dekel PHY register
|
||||
* @i915: i915 device instance
|
||||
* @display: intel_display device instance
|
||||
* @reg: Dekel PHY register
|
||||
*
|
||||
* Read the @reg Dekel PHY register.
|
||||
|
|
@ -41,42 +41,42 @@ dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
|
|||
* Returns the read value.
|
||||
*/
|
||||
u32
|
||||
intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
|
||||
intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
spin_lock(&i915->display.dkl.phy_lock);
|
||||
spin_lock(&display->dkl.phy_lock);
|
||||
|
||||
dkl_phy_set_hip_idx(i915, reg);
|
||||
val = intel_de_read(i915, DKL_REG_MMIO(reg));
|
||||
dkl_phy_set_hip_idx(display, reg);
|
||||
val = intel_de_read(display, DKL_REG_MMIO(reg));
|
||||
|
||||
spin_unlock(&i915->display.dkl.phy_lock);
|
||||
spin_unlock(&display->dkl.phy_lock);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_dkl_phy_write - write a Dekel PHY register
|
||||
* @i915: i915 device instance
|
||||
* @display: intel_display device instance
|
||||
* @reg: Dekel PHY register
|
||||
* @val: value to write
|
||||
*
|
||||
* Write @val to the @reg Dekel PHY register.
|
||||
*/
|
||||
void
|
||||
intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val)
|
||||
intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val)
|
||||
{
|
||||
spin_lock(&i915->display.dkl.phy_lock);
|
||||
spin_lock(&display->dkl.phy_lock);
|
||||
|
||||
dkl_phy_set_hip_idx(i915, reg);
|
||||
intel_de_write(i915, DKL_REG_MMIO(reg), val);
|
||||
dkl_phy_set_hip_idx(display, reg);
|
||||
intel_de_write(display, DKL_REG_MMIO(reg), val);
|
||||
|
||||
spin_unlock(&i915->display.dkl.phy_lock);
|
||||
spin_unlock(&display->dkl.phy_lock);
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_dkl_phy_rmw - read-modify-write a Dekel PHY register
|
||||
* @i915: i915 device instance
|
||||
* @display: display device instance
|
||||
* @reg: Dekel PHY register
|
||||
* @clear: mask to clear
|
||||
* @set: mask to set
|
||||
|
|
@ -85,30 +85,30 @@ intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg,
|
|||
* this value back to the register if the value differs from the read one.
|
||||
*/
|
||||
void
|
||||
intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
|
||||
intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
|
||||
{
|
||||
spin_lock(&i915->display.dkl.phy_lock);
|
||||
spin_lock(&display->dkl.phy_lock);
|
||||
|
||||
dkl_phy_set_hip_idx(i915, reg);
|
||||
intel_de_rmw(i915, DKL_REG_MMIO(reg), clear, set);
|
||||
dkl_phy_set_hip_idx(display, reg);
|
||||
intel_de_rmw(display, DKL_REG_MMIO(reg), clear, set);
|
||||
|
||||
spin_unlock(&i915->display.dkl.phy_lock);
|
||||
spin_unlock(&display->dkl.phy_lock);
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_dkl_phy_posting_read - do a posting read from a Dekel PHY register
|
||||
* @i915: i915 device instance
|
||||
* @display: display device instance
|
||||
* @reg: Dekel PHY register
|
||||
*
|
||||
* Read the @reg Dekel PHY register without returning the read value.
|
||||
*/
|
||||
void
|
||||
intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
|
||||
intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
|
||||
{
|
||||
spin_lock(&i915->display.dkl.phy_lock);
|
||||
spin_lock(&display->dkl.phy_lock);
|
||||
|
||||
dkl_phy_set_hip_idx(i915, reg);
|
||||
intel_de_posting_read(i915, DKL_REG_MMIO(reg));
|
||||
dkl_phy_set_hip_idx(display, reg);
|
||||
intel_de_posting_read(display, DKL_REG_MMIO(reg));
|
||||
|
||||
spin_unlock(&i915->display.dkl.phy_lock);
|
||||
spin_unlock(&display->dkl.phy_lock);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,15 +11,16 @@
|
|||
#include "intel_dkl_phy_regs.h"
|
||||
|
||||
struct drm_i915_private;
|
||||
struct intel_display;
|
||||
|
||||
void intel_dkl_phy_init(struct drm_i915_private *i915);
|
||||
u32
|
||||
intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg);
|
||||
intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
|
||||
void
|
||||
intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val);
|
||||
intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val);
|
||||
void
|
||||
intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set);
|
||||
intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set);
|
||||
void
|
||||
intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg);
|
||||
intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
|
||||
|
||||
#endif /* __INTEL_DKL_PHY_H__ */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -390,7 +390,7 @@ struct intel_shared_dpll {
|
|||
|
||||
/* shared dpll functions */
|
||||
struct intel_shared_dpll *
|
||||
intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
|
||||
intel_get_shared_dpll_by_id(struct intel_display *display,
|
||||
enum intel_dpll_id id);
|
||||
void assert_shared_dpll(struct drm_i915_private *i915,
|
||||
struct intel_shared_dpll *pll,
|
||||
|
|
@ -413,10 +413,10 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
|
|||
void intel_update_active_dpll(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
struct intel_encoder *encoder);
|
||||
int intel_dpll_get_freq(struct drm_i915_private *i915,
|
||||
int intel_dpll_get_freq(struct intel_display *display,
|
||||
const struct intel_shared_dpll *pll,
|
||||
const struct intel_dpll_hw_state *dpll_hw_state);
|
||||
bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
|
||||
bool intel_dpll_get_hw_state(struct intel_display *display,
|
||||
struct intel_shared_dpll *pll,
|
||||
struct intel_dpll_hw_state *dpll_hw_state);
|
||||
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
|
||||
|
|
@ -424,8 +424,8 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
|
|||
void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
|
||||
void intel_shared_dpll_init(struct drm_i915_private *i915);
|
||||
void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
|
||||
void intel_dpll_readout_hw_state(struct drm_i915_private *i915);
|
||||
void intel_dpll_sanitize_state(struct drm_i915_private *i915);
|
||||
void intel_dpll_readout_hw_state(struct intel_display *display);
|
||||
void intel_dpll_sanitize_state(struct intel_display *display);
|
||||
|
||||
void intel_dpll_dump_hw_state(struct intel_display *display,
|
||||
struct drm_printer *p,
|
||||
|
|
|
|||
|
|
@ -795,7 +795,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
|
|||
pipe_name(pipe));
|
||||
}
|
||||
|
||||
intel_dpll_readout_hw_state(i915);
|
||||
intel_dpll_readout_hw_state(display);
|
||||
|
||||
drm_connector_list_iter_begin(&i915->drm, &conn_iter);
|
||||
for_each_intel_connector_iter(connector, &conn_iter) {
|
||||
|
|
@ -1014,7 +1014,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
|
|||
|
||||
intel_sanitize_all_crtcs(i915, ctx);
|
||||
|
||||
intel_dpll_sanitize_state(i915);
|
||||
intel_dpll_sanitize_state(display);
|
||||
|
||||
intel_wm_get_hw_state(i915);
|
||||
|
||||
|
|
|
|||
|
|
@ -249,6 +249,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
|
|||
static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
||||
struct intel_display *display = to_intel_display(crtc);
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
enum pipe pipe = crtc->pipe;
|
||||
i915_reg_t reg;
|
||||
|
|
@ -263,7 +264,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
|
|||
|
||||
if (HAS_PCH_CPT(dev_priv)) {
|
||||
reg = TRANS_CHICKEN2(pipe);
|
||||
val = intel_de_read(dev_priv, reg);
|
||||
val = intel_de_read(display, reg);
|
||||
/*
|
||||
* Workaround: Set the timing override bit
|
||||
* before enabling the pch transcoder.
|
||||
|
|
@ -272,12 +273,12 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
|
|||
/* Configure frame start delay to match the CPU */
|
||||
val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
|
||||
val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
|
||||
intel_de_write(dev_priv, reg, val);
|
||||
intel_de_write(display, reg, val);
|
||||
}
|
||||
|
||||
reg = PCH_TRANSCONF(pipe);
|
||||
val = intel_de_read(dev_priv, reg);
|
||||
pipeconf_val = intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe));
|
||||
val = intel_de_read(display, reg);
|
||||
pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe));
|
||||
|
||||
if (HAS_PCH_IBX(dev_priv)) {
|
||||
/* Configure frame start delay to match the CPU */
|
||||
|
|
@ -307,9 +308,9 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
|
|||
val |= TRANS_INTERLACE_PROGRESSIVE;
|
||||
}
|
||||
|
||||
intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
|
||||
if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
|
||||
drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
|
||||
intel_de_write(display, reg, val | TRANS_ENABLE);
|
||||
if (intel_de_wait_for_set(display, reg, TRANS_STATE_ENABLE, 100))
|
||||
drm_err(display->drm, "failed to enable transcoder %c\n",
|
||||
pipe_name(pipe));
|
||||
}
|
||||
|
||||
|
|
@ -383,15 +384,15 @@ void ilk_pch_enable(struct intel_atomic_state *state,
|
|||
if (HAS_PCH_CPT(dev_priv)) {
|
||||
u32 sel;
|
||||
|
||||
temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
|
||||
temp = intel_de_read(display, PCH_DPLL_SEL);
|
||||
temp |= TRANS_DPLL_ENABLE(pipe);
|
||||
sel = TRANS_DPLLB_SEL(pipe);
|
||||
if (crtc_state->shared_dpll ==
|
||||
intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
|
||||
intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
|
||||
temp |= sel;
|
||||
else
|
||||
temp &= ~sel;
|
||||
intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
|
||||
intel_de_write(display, PCH_DPLL_SEL, temp);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -420,11 +421,12 @@ void ilk_pch_enable(struct intel_atomic_state *state,
|
|||
intel_crtc_has_dp_encoder(crtc_state)) {
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
u32 bpc = (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) >> 5;
|
||||
u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))
|
||||
& TRANSCONF_BPC_MASK) >> 5;
|
||||
i915_reg_t reg = TRANS_DP_CTL(pipe);
|
||||
enum port port;
|
||||
|
||||
temp = intel_de_read(dev_priv, reg);
|
||||
temp = intel_de_read(display, reg);
|
||||
temp &= ~(TRANS_DP_PORT_SEL_MASK |
|
||||
TRANS_DP_VSYNC_ACTIVE_HIGH |
|
||||
TRANS_DP_HSYNC_ACTIVE_HIGH |
|
||||
|
|
@ -438,10 +440,10 @@ void ilk_pch_enable(struct intel_atomic_state *state,
|
|||
temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
|
||||
|
||||
port = intel_get_crtc_new_encoder(state, crtc_state)->port;
|
||||
drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D);
|
||||
drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D);
|
||||
temp |= TRANS_DP_PORT_SEL(port);
|
||||
|
||||
intel_de_write(dev_priv, reg, temp);
|
||||
intel_de_write(display, reg, temp);
|
||||
}
|
||||
|
||||
ilk_enable_pch_transcoder(crtc_state);
|
||||
|
|
@ -496,6 +498,7 @@ static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
|
|||
void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
||||
struct intel_display *display = to_intel_display(crtc);
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
struct intel_shared_dpll *pll;
|
||||
enum pipe pipe = crtc->pipe;
|
||||
|
|
@ -503,12 +506,12 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
|
|||
bool pll_active;
|
||||
u32 tmp;
|
||||
|
||||
if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
|
||||
if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
|
||||
return;
|
||||
|
||||
crtc_state->has_pch_encoder = true;
|
||||
|
||||
tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
|
||||
tmp = intel_de_read(display, FDI_RX_CTL(pipe));
|
||||
crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
|
||||
FDI_DP_PORT_WIDTH_SHIFT) + 1;
|
||||
|
||||
|
|
@ -522,19 +525,19 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
|
|||
*/
|
||||
pll_id = (enum intel_dpll_id) pipe;
|
||||
} else {
|
||||
tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
|
||||
tmp = intel_de_read(display, PCH_DPLL_SEL);
|
||||
if (tmp & TRANS_DPLLB_SEL(pipe))
|
||||
pll_id = DPLL_ID_PCH_PLL_B;
|
||||
else
|
||||
pll_id = DPLL_ID_PCH_PLL_A;
|
||||
}
|
||||
|
||||
crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
|
||||
crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id);
|
||||
pll = crtc_state->shared_dpll;
|
||||
|
||||
pll_active = intel_dpll_get_hw_state(dev_priv, pll,
|
||||
pll_active = intel_dpll_get_hw_state(display, pll,
|
||||
&crtc_state->dpll_hw_state);
|
||||
drm_WARN_ON(&dev_priv->drm, !pll_active);
|
||||
drm_WARN_ON(display->drm, !pll_active);
|
||||
|
||||
tmp = crtc_state->dpll_hw_state.i9xx.dpll;
|
||||
crtc_state->pixel_multiplier =
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user