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drm/i915/wm: Add WM0 prefill helpers

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Add skl_wm0_prefill_lines() (based on the actual state) and
skl_wm0_prefill_lines_worst() (worst case estimate) which
tell us how many extra lines are needed in prefill for WM0.

The returned numbers are in .16 binary fixed point.

TODO: skl_wm0_prefill_lines_worst() is a bit rough still

v2: Drop all pre-icl FIXMEs since this only gets used for VRR guardband

Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20251014191808.12326-8-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä 2025-10-14 22:18:06 +03:00
parent b95e31cdfc
commit 9704c1cbed
4 changed files with 95 additions and 1 deletions
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32
drivers/gpu/drm/i915/display/skl_scaler.c
View File

@ -1026,7 +1026,37 @@ static unsigned int _skl_scaler_max_scale(const struct intel_crtc_state *crtc_st
crtc_state->hw.pipe_mode.crtc_clock));
}
static unsigned int skl_scaler_max_scale(const struct intel_crtc_state *crtc_state)
unsigned int skl_scaler_max_total_scale(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
unsigned int max_scale;
if (crtc->num_scalers < 1)
return 0x10000;
/* FIXME find out the max downscale factors properly */
max_scale = 9 << 16;
if (crtc->num_scalers > 1)
max_scale *= 9;
return _skl_scaler_max_scale(crtc_state, max_scale);
}
unsigned int skl_scaler_max_hscale(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
unsigned int max_scale;
if (crtc->num_scalers < 1)
return 0x10000;
/* FIXME find out the max downscale factors properly */
max_scale = 3 << 16;
return _skl_scaler_max_scale(crtc_state, max_scale);
}
unsigned int skl_scaler_max_scale(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
unsigned int max_scale;

4
drivers/gpu/drm/i915/display/skl_scaler.h
View File

@ -46,6 +46,10 @@ void adl_scaler_ecc_mask(const struct intel_crtc_state *crtc_state);
void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state);
unsigned int skl_scaler_max_total_scale(const struct intel_crtc_state *crtc_state);
unsigned int skl_scaler_max_scale(const struct intel_crtc_state *crtc_state);
unsigned int skl_scaler_max_hscale(const struct intel_crtc_state *crtc_state);
unsigned int skl_scaler_1st_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state);
unsigned int skl_scaler_2nd_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state);
unsigned int skl_scaler_1st_prefill_lines_worst(const struct intel_crtc_state *crtc_state);

57
drivers/gpu/drm/i915/display/skl_watermark.c
View File

@ -30,6 +30,7 @@
#include "intel_plane.h"
#include "intel_vblank.h"
#include "intel_wm.h"
#include "skl_scaler.h"
#include "skl_universal_plane_regs.h"
#include "skl_watermark.h"
#include "skl_watermark_regs.h"
@ -2245,6 +2246,57 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
intel_crtc_vblank_length(crtc_state);
}
unsigned int skl_wm0_prefill_lines_worst(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->primary);
const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
int ret, pixel_rate, width, level = 0;
const struct drm_format_info *info;
struct skl_wm_level wm = {};
struct skl_wm_params wp;
unsigned int latency;
u64 modifier;
u32 format;
/* only expected to be used for VRR guardband calculation */
drm_WARN_ON(display->drm, !HAS_VRR(display));
/* FIXME rather ugly to pick this by hand but maybe no better way? */
format = DRM_FORMAT_XBGR16161616F;
if (HAS_4TILE(display))
modifier = I915_FORMAT_MOD_4_TILED;
else
modifier = I915_FORMAT_MOD_Y_TILED;
info = drm_get_format_info(display->drm, format, modifier);
pixel_rate = DIV_ROUND_UP_ULL(mul_u32_u32(skl_scaler_max_total_scale(crtc_state),
pipe_mode->crtc_clock),
0x10000);
/* FIXME limit to max plane width? */
width = DIV_ROUND_UP_ULL(mul_u32_u32(skl_scaler_max_hscale(crtc_state),
pipe_mode->crtc_hdisplay),
0x10000);
/* FIXME is 90/270 rotation worse than 0/180? */
ret = skl_compute_wm_params(crtc_state, width, info,
modifier, DRM_MODE_ROTATE_0,
pixel_rate, &wp, 0, 1);
drm_WARN_ON(display->drm, ret);
latency = skl_wm_latency(display, level, &wp);
skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);
/* FIXME is this sane? */
if (wm.min_ddb_alloc == U16_MAX)
wm.lines = skl_wm_max_lines(display);
return wm.lines << 16;
}
static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@ -2261,6 +2313,11 @@ static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
return wm0_lines;
}
unsigned int skl_wm0_prefill_lines(const struct intel_crtc_state *crtc_state)
{
return skl_max_wm0_lines(crtc_state) << 16;
}
/*
* TODO: In case we use PKG_C_LATENCY to allow C-states when the delayed vblank
* size is too small for the package C exit latency we need to notify PSR about

3
drivers/gpu/drm/i915/display/skl_watermark.h
View File

@ -79,5 +79,8 @@ void intel_program_dpkgc_latency(struct intel_atomic_state *state);
bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state);
unsigned int skl_wm0_prefill_lines_worst(const struct intel_crtc_state *crtc_state);
unsigned int skl_wm0_prefill_lines(const struct intel_crtc_state *crtc_state);
#endif /* __SKL_WATERMARK_H__ */