From 96c5f4130014eca8f55d842ebe5b075e81ad9ee9 Mon Sep 17 00:00:00 2001 From: Zhang Yunlong Date: Thu, 25 Jan 2018 21:07:10 +0800 Subject: [PATCH] camera: rockchip: camsys_drv: v0.0x25.0 support px30 Change-Id: I60dc9c0d7f47a29d3f0fd88a85cea0aeb4b28b38 Signed-off-by: Zhang Yunlong --- drivers/media/video/rk_camsys/Makefile | 9 +- drivers/media/video/rk_camsys/camsys_drv.c | 11 +- .../media/video/rk_camsys/camsys_internal.h | 4 +- drivers/media/video/rk_camsys/camsys_marvin.c | 12 +- .../video/rk_camsys/camsys_mipicsi_phy.c | 5 +- .../media/video/rk_camsys/camsys_soc_priv.c | 6 + .../media/video/rk_camsys/camsys_soc_rk3326.c | 221 ++++++++++++++++++ .../media/video/rk_camsys/camsys_soc_rk3326.h | 77 ++++++ .../media/video/rk_camsys/camsys_soc_rk3368.c | 7 +- .../media/video/rk_camsys/camsys_soc_rk3368.h | 2 +- 10 files changed, 335 insertions(+), 19 deletions(-) create mode 100644 drivers/media/video/rk_camsys/camsys_soc_rk3326.c create mode 100644 drivers/media/video/rk_camsys/camsys_soc_rk3326.h diff --git a/drivers/media/video/rk_camsys/Makefile b/drivers/media/video/rk_camsys/Makefile index 14a5cc46a765..f865c07f12b6 100755 --- a/drivers/media/video/rk_camsys/Makefile +++ b/drivers/media/video/rk_camsys/Makefile @@ -2,7 +2,12 @@ # Makefile for rockchip camsys driver # obj-$(CONFIG_CAMSYS_DRV) += camsys_drv.o -obj-$(CONFIG_CAMSYS_MRV) += camsys_marvin.o camsys_mipicsi_phy.o camsys_soc_priv.o camsys_soc_rk3288.o camsys_soc_rk3368.o camsys_soc_rk3366.o camsys_soc_rk3399.o +obj-$(CONFIG_CAMSYS_MRV) += camsys_marvin.o camsys_mipicsi_phy.o camsys_soc_priv.o +obj-$(CONFIG_CAMSYS_MRV) += camsys_soc_rk3288.o +obj-$(CONFIG_CAMSYS_MRV) += camsys_soc_rk3368.o +obj-$(CONFIG_CAMSYS_MRV) += camsys_soc_rk3366.o +obj-$(CONFIG_CAMSYS_MRV) += camsys_soc_rk3399.o +obj-$(CONFIG_CAMSYS_MRV) += camsys_soc_rk3326.o obj-$(CONFIG_CAMSYS_CIF) += camsys_cif.o -obj-y += ext_flashled_drv/ +obj-y += ext_flashled_drv/ diff --git a/drivers/media/video/rk_camsys/camsys_drv.c b/drivers/media/video/rk_camsys/camsys_drv.c index 393b83ad925c..8bcbe5754f6d 100644 --- a/drivers/media/video/rk_camsys/camsys_drv.c +++ b/drivers/media/video/rk_camsys/camsys_drv.c @@ -465,10 +465,7 @@ static int camsys_sysctl(camsys_sysctrl_t *devctl, camsys_dev_t *camsys_dev) /* spin_lock(&camsys_dev->lock); */ mutex_lock(&camsys_dev->extdevs.mut); - if (devctl->ops == 0xaa) { - dump_stack(); - return 0; - } + /* Internal */ if (camsys_dev->dev_id & devctl->dev_mask) { switch (devctl->ops) { @@ -1431,7 +1428,8 @@ static int camsys_platform_probe(struct platform_device *pdev) CHIP_TYPE = 3366; else if (strstr(compatible, "rk3399")) CHIP_TYPE = 3399; - + else if (strstr(compatible, "px30") || strstr(compatible, "rk3326")) + CHIP_TYPE = 3326; camsys_soc_init(CHIP_TYPE); err = of_address_to_resource(dev->of_node, 0, ®ister_res); @@ -1497,6 +1495,7 @@ static int camsys_platform_probe(struct platform_device *pdev) dev_name(&pdev->dev), CAMSYS_REGISTER_MEM_NAME); err = -ENXIO; + kfree(meminfo); goto request_mem_fail; } camsys_dev->rk_isp_base = meminfo->vir_base; @@ -1605,7 +1604,7 @@ static int camsys_platform_probe(struct platform_device *pdev) meminfo_fail = NULL; } - kfree(camsys_dev); + devm_kfree(&pdev->dev, camsys_dev); camsys_dev = NULL; } fail_end: diff --git a/drivers/media/video/rk_camsys/camsys_internal.h b/drivers/media/video/rk_camsys/camsys_internal.h index 01de68791ece..eb638dac9557 100644 --- a/drivers/media/video/rk_camsys/camsys_internal.h +++ b/drivers/media/video/rk_camsys/camsys_internal.h @@ -189,9 +189,11 @@ 1) replace current->pid with irqsta->pid. *v0.0x24.0: 1) function is the same as commit in v0.0x22.3 but now is better way. +*v0.0x25.0: + 1) support px30. */ -#define CAMSYS_DRIVER_VERSION KERNEL_VERSION(0, 0x24, 0) +#define CAMSYS_DRIVER_VERSION KERNEL_VERSION(0, 0x25, 0) #define CAMSYS_PLATFORM_DRV_NAME "RockChip-CamSys" #define CAMSYS_PLATFORM_MARVIN_NAME "Platform_MarvinDev" diff --git a/drivers/media/video/rk_camsys/camsys_marvin.c b/drivers/media/video/rk_camsys/camsys_marvin.c index 01d655fd16a5..e7ec58e1e93a 100644 --- a/drivers/media/video/rk_camsys/camsys_marvin.c +++ b/drivers/media/video/rk_camsys/camsys_marvin.c @@ -633,7 +633,8 @@ static int camsys_mrv_clkin_cb(void *ptr, unsigned int on) clk_prepare_enable(clk->isp); clk_prepare_enable(clk->isp_jpe); clk_prepare_enable(clk->pclkin_isp); - if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366) { + if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366 || + CHIP_TYPE == 3326) { clk_prepare_enable(clk->cif_clk_out); clk_prepare_enable(clk->pclk_dphyrx); } else { @@ -652,7 +653,8 @@ static int camsys_mrv_clkin_cb(void *ptr, unsigned int on) clk_disable_unprepare(clk->isp); clk_disable_unprepare(clk->isp_jpe); clk_disable_unprepare(clk->pclkin_isp); - if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366) { + if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366 || + CHIP_TYPE == 3326) { clk_disable_unprepare(clk->cif_clk_out); clk_disable_unprepare(clk->pclk_dphyrx); } else { @@ -960,7 +962,8 @@ int camsys_mrv_probe_cb(struct platform_device *pdev, camsys_dev_t *camsys_dev) err = -EINVAL; goto clk_failed; } - if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366) { + if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366 || + CHIP_TYPE == 3326) { /* mrv_clk->pd_isp = devm_clk_get(&pdev->dev, "pd_isp"); */ mrv_clk->aclk_isp = devm_clk_get(&pdev->dev, "aclk_isp"); mrv_clk->hclk_isp = devm_clk_get(&pdev->dev, "hclk_isp"); @@ -1208,7 +1211,8 @@ int camsys_mrv_probe_cb(struct platform_device *pdev, camsys_dev_t *camsys_dev) if (!IS_ERR_OR_NULL(mrv_clk->cif_clk_out)) clk_put(mrv_clk->cif_clk_out); - if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366) { + if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366 || + CHIP_TYPE == 3326) { if (!IS_ERR_OR_NULL(mrv_clk->pclk_dphyrx)) clk_put(mrv_clk->pclk_dphyrx); diff --git a/drivers/media/video/rk_camsys/camsys_mipicsi_phy.c b/drivers/media/video/rk_camsys/camsys_mipicsi_phy.c index 946f49c2e4bd..cdef8c847539 100644 --- a/drivers/media/video/rk_camsys/camsys_mipicsi_phy.c +++ b/drivers/media/video/rk_camsys/camsys_mipicsi_phy.c @@ -93,7 +93,8 @@ static int camsys_mipiphy_remove_cb(struct platform_device *pdev) } } } - if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366 || CHIP_TYPE == 3399) { + if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366 || + CHIP_TYPE == 3399 || CHIP_TYPE == 3326) { if (camsys_dev->csiphy_reg != NULL) { kfree(camsys_dev->csiphy_reg); camsys_dev->csiphy_reg = NULL; @@ -207,7 +208,7 @@ struct platform_device *pdev, camsys_dev_t *camsys_dev) } if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366 || - CHIP_TYPE == 3399 || CHIP_TYPE == 3288) { + CHIP_TYPE == 3399 || CHIP_TYPE == 3288 || CHIP_TYPE == 3326) { if (CHIP_TYPE == 3399) { camsys_dev->dsiphy_reg = diff --git a/drivers/media/video/rk_camsys/camsys_soc_priv.c b/drivers/media/video/rk_camsys/camsys_soc_priv.c index 07608ced545a..238128dd4eb0 100644 --- a/drivers/media/video/rk_camsys/camsys_soc_priv.c +++ b/drivers/media/video/rk_camsys/camsys_soc_priv.c @@ -11,6 +11,8 @@ extern int camsys_rk3366_cfg( camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para); extern int camsys_rk3399_cfg( camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para); +extern int camsys_rk3326_cfg( + camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para); #else extern int camsys_rk3288_cfg( camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para); @@ -45,6 +47,10 @@ int camsys_soc_init(unsigned int chip_type) strlcpy(camsys_soc_p->name, "camsys_rk3399", 31); camsys_soc_p->soc_cfg = camsys_rk3399_cfg; camsys_trace(2, "rk3399 exit!"); + } else if (chip_type == 3326) { + strlcpy(camsys_soc_p->name, "camsys_rk3326", 31); + camsys_soc_p->soc_cfg = camsys_rk3326_cfg; + camsys_trace(2, "rk3326 exit!"); } #else if (chip_type == 3288) { diff --git a/drivers/media/video/rk_camsys/camsys_soc_rk3326.c b/drivers/media/video/rk_camsys/camsys_soc_rk3326.c new file mode 100644 index 000000000000..c65e855ce468 --- /dev/null +++ b/drivers/media/video/rk_camsys/camsys_soc_rk3326.c @@ -0,0 +1,221 @@ +/* + ************************************************************************* + * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + ************************************************************************* + */ + +#ifdef CONFIG_ARM64 +#include "camsys_soc_priv.h" +#include "camsys_soc_rk3326.h" + +struct mipiphy_hsfreqrange_s { + unsigned int range_l; + unsigned int range_h; + unsigned char cfg_bit; +}; + +static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = { + {80, 110, 0x00}, + {110, 150, 0x01}, + {150, 200, 0x02}, + {200, 250, 0x03}, + {250, 300, 0x04}, + {300, 400, 0x05}, + {400, 500, 0x06}, + {500, 600, 0x07}, + {600, 700, 0x08}, + {700, 800, 0x09}, + {800, 1000, 0xa}, + {1000, 1100, 0xb}, + {1100, 1250, 0xc}, + {1250, 1350, 0xd}, + {1350, 1500, 0xe} +}; + +static int camsys_rk3326_mipihpy_cfg(camsys_mipiphy_soc_para_t *para) +{ + unsigned char hsfreqrange = 0xff, i; + struct mipiphy_hsfreqrange_s *hsfreqrange_p; + unsigned long csiphy_virt; + //unsigned long base; + + if (para->camsys_dev->csiphy_reg) { + csiphy_virt = + (unsigned long)para->camsys_dev->csiphy_reg->vir_base; + } else { + csiphy_virt = 0x00; + } + if (para->phy->bit_rate == 0 || + para->phy->data_en_bit == 0) { + if (para->phy->phy_index == 0) { + write_grf_reg(GRF_PD_VI_CON_OFFSET, + DPHY_CSIPHY_CLKLANE_EN_OFFSET_MASK | + (0 << DPHY_CSIPHY_CLKLANE_EN_OFFSET_BITS)); + write_grf_reg(GRF_PD_VI_CON_OFFSET, + DPHY_CSIPHY_DATALANE_EN_OFFSET_MASK | + (0 << DPHY_CSIPHY_DATALANE_EN_OFFSET_BITS)); + camsys_trace(1, "mipi phy 0 standby!"); + } + + return 0; + } + + hsfreqrange_p = mipiphy_hsfreqrange; + for (i = 0; + i < (sizeof(mipiphy_hsfreqrange) / + sizeof(struct mipiphy_hsfreqrange_s)); + i++) { + if ((para->phy->bit_rate > hsfreqrange_p->range_l) && + (para->phy->bit_rate <= hsfreqrange_p->range_h)) { + hsfreqrange = hsfreqrange_p->cfg_bit; + break; + } + hsfreqrange_p++; + } + + if (hsfreqrange == 0xff) { + camsys_err("mipi phy config bitrate %d Mbps isn't supported!", + para->phy->bit_rate); + hsfreqrange = 0x00; + } + + if (para->phy->phy_index == 0) { + /* phy start */ + write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe4); + + /* set data lane num and enable clock lane */ + write_csiphy_reg(MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET, + ((para->phy->data_en_bit << MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) | + (0x1 << MIPI_CSI_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT) | 0x1)); + /* Reset dphy analog part */ + write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe0); + usleep_range(500, 1000); + /* Reset dphy digital part */ + write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1e); + write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1f); + /* not into receive mode/wait stopstate */ + write_grf_reg(GRF_PD_VI_CON_OFFSET, + DPHY_CSIPHY_FORCERXMODE_OFFSET_MASK | + (0x0 << DPHY_CSIPHY_FORCERXMODE_OFFSET_BITS)); + + write_csiphy_reg((MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + 0x100), + hsfreqrange | + (read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + + 0x100) & (~0xf))); + + if (para->phy->data_en_bit > 0x00) { + write_csiphy_reg((MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + + 0x180), hsfreqrange | + (read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + + 0x180) & (~0xf))); + } + if (para->phy->data_en_bit > 0x02) { + write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + + 0x200, hsfreqrange | + (read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + + 0x200) & (~0xf))); + } + if (para->phy->data_en_bit > 0x04) { + write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + + 0x280, hsfreqrange | + (read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + + 0x280) & (~0xf))); + write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + + 0x300, hsfreqrange | + (read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + + 0x300) & (~0xf))); + } + + write_grf_reg(GRF_PD_VI_CON_OFFSET, + DPHY_CSIPHY_CLKLANE_EN_OFFSET_MASK | + (1 << DPHY_CSIPHY_CLKLANE_EN_OFFSET_BITS)); + write_grf_reg(GRF_PD_VI_CON_OFFSET, + DPHY_CSIPHY_DATALANE_EN_OFFSET_MASK | + (0x0f << DPHY_CSIPHY_DATALANE_EN_OFFSET_BITS)); + + } else { + camsys_err("mipi phy index %d is invalidate!", + para->phy->phy_index); + goto fail; + } + + camsys_trace(1, "mipi phy(%d) turn on(lane: 0x%x bit_rate: %dMbps)", + para->phy->phy_index, + para->phy->data_en_bit, para->phy->bit_rate); + + return 0; + +fail: + return -1; +} + +#define VI_IRCL 0x0014 +int camsys_rk3326_cfg +( + camsys_dev_t *camsys_dev, + camsys_soc_cfg_t cfg_cmd, + void *cfg_para +) +{ + unsigned int *para_int; + + switch (cfg_cmd) { + case Clk_DriverStrength_Cfg: { + para_int = (unsigned int *)cfg_para; + __raw_writel((((*para_int) & 0x03) << 6) | (0x03 << 22), + (void *)(camsys_dev->rk_grf_base + 0x104));//m0 cifclk_out + break; + } + + case Cif_IoDomain_Cfg: { + para_int = (unsigned int *)cfg_para; + if (*para_int < 28000000) { + /* 1.8v IO */ + __raw_writel((1 << GRF_IO_VSEL_VCCIO3_BITS) | GRF_IO_VSEL_VCCIO3_MASK, + (void *)(camsys_dev->rk_grf_base + GRF_IO_VSEL_OFFSET)); + } else { + /* 3.3v IO */ + __raw_writel((0 << GRF_IO_VSEL_VCCIO3_BITS) | GRF_IO_VSEL_VCCIO3_MASK, + (void *)(camsys_dev->rk_grf_base + GRF_IO_VSEL_OFFSET)); + } + break; + } + + case Mipi_Phy_Cfg: { + camsys_rk3326_mipihpy_cfg + ((camsys_mipiphy_soc_para_t *)cfg_para); + break; + } + + case Isp_SoftRst: {/* ddl@rock-chips.com: v0.d.0 */ + unsigned long reset; + + reset = (unsigned long)cfg_para; + + if (reset == 1) + __raw_writel(0x80, (void *)(camsys_dev->rk_isp_base + + VI_IRCL)); + else + __raw_writel(0x00, (void *)(camsys_dev->rk_isp_base + + VI_IRCL)); + camsys_trace(2, "Isp self soft rst: %ld", reset); + break; + } + + default: + { + camsys_warn("cfg_cmd: 0x%x isn't support", cfg_cmd); + break; + } + + } + + return 0; +} +#endif /* CONFIG_ARM64 */ diff --git a/drivers/media/video/rk_camsys/camsys_soc_rk3326.h b/drivers/media/video/rk_camsys/camsys_soc_rk3326.h new file mode 100644 index 000000000000..0ea76ce253ed --- /dev/null +++ b/drivers/media/video/rk_camsys/camsys_soc_rk3326.h @@ -0,0 +1,77 @@ +/* + ************************************************************************* + * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + ************************************************************************* + */ + +#ifndef __RKCAMSYS_SOC_RK3326_H__ +#define __RKCAMSYS_SOC_RK3326_H__ + +#include "camsys_internal.h" + +/* MARVIN REGISTER */ +#define MRV_MIPI_BASE 0x1C00 +#define MRV_MIPI_CTRL 0x00 + +#define GRF_IO_VSEL_OFFSET (0x0180) +#define GRF_IO_VSEL_VCCIO3_MASK (0x1 << 20) +#define GRF_IO_VSEL_VCCIO3_BITS (4) +#define GRF_PD_VI_CON_OFFSET (0x0430) +/* bit 13-14 */ +#define ISP_CIF_IF_DATAWIDTH_MASK (0x3 << 29) +#define ISP_CIF_IF_DATAWIDTH_8B (0x0 << 13) +#define ISP_CIF_IF_DATAWIDTH_10B (0x1 << 13) +#define ISP_CIF_IF_DATAWIDTH_12B (0x2 << 13) + +/* bit 9 */ +#define DPHY_CSIPHY_CLK_INV_SEL_MASK (0x1 << 25) +#define DPHY_CSIPHY_CLK_INV_SEL (0x1 << 9) +/* bit 8 */ +#define DPHY_CSIPHY_CLKLANE_EN_OFFSET_MASK (0x1 << 24)//???? +#define DPHY_CSIPHY_CLKLANE_EN_OFFSET_BITS (8) +/* bit 4-7 */ +#define DPHY_CSIPHY_DATALANE_EN_OFFSET_MASK (0xF << 20)//????? +#define DPHY_CSIPHY_DATALANE_EN_OFFSET_BITS (4) +/* bit 0-3 */ +#define DPHY_CSIPHY_FORCERXMODE_OFFSET_MASK (0xF << 16) +#define DPHY_CSIPHY_FORCERXMODE_OFFSET_BITS (0) + +/* LOW POWER MODE SET */ +/* base */ +#define MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET (0x00) +#define MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT (2) +#define MIPI_CSI_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT (6) +#define MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET (0x04) +#define MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET (0x80) +#define MIPI_CSI_DPHY_CTRL_SIG_INV_OFFSET (0x84) + +/* Configure the count time of the THS-SETTLE by protocol. */ +#define MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET (0x00) +/* MSB enable for pin_rxdatahs_ + * 1: enable + * 0: disable + */ +#define MIPI_CSI_DPHY_LANEX_MSB_EN_OFFSET (0x38) + +#define write_grf_reg(addr, val) \ + __raw_writel(val, (void *)(addr + para->camsys_dev->rk_grf_base)) +#define read_grf_reg(addr) \ + __raw_readl((void *)(addr + para->camsys_dev->rk_grf_base)) +#define mask_grf_reg(addr, msk, val) \ + write_grf_reg(addr, (val) | ((~(msk)) & read_grf_reg(addr))) + +#define write_cru_reg(addr, val) \ + __raw_writel(val, (void *)(addr + para->camsys_dev->rk_cru_base)) +/* csi phy */ +#define write_csiphy_reg(addr, val) \ + __raw_writel(val, (void *)(addr + csiphy_virt)) +#define read_csiphy_reg(addr) \ + __raw_readl((void *)(addr + csiphy_virt)) + +#endif diff --git a/drivers/media/video/rk_camsys/camsys_soc_rk3368.c b/drivers/media/video/rk_camsys/camsys_soc_rk3368.c index 32a7dafd11d7..1058b3a13a0d 100644 --- a/drivers/media/video/rk_camsys/camsys_soc_rk3368.c +++ b/drivers/media/video/rk_camsys/camsys_soc_rk3368.c @@ -128,8 +128,9 @@ static int camsys_rk3368_mipihpy_cfg(camsys_mipiphy_soc_para_t *para) write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe4); /* set data lane num and enable clock lane */ - write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET, - ((para->phy->data_en_bit << 2) | (0x1 << 6) | 0x1)); + write_csiphy_reg(MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET, + ((para->phy->data_en_bit << MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET_BIT) | + (0x1 << 6) | 0x1)); /* Reset dphy analog part */ write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe0); usleep_range(500, 1000); @@ -139,7 +140,7 @@ static int camsys_rk3368_mipihpy_cfg(camsys_mipiphy_soc_para_t *para) write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_CSI_DPHY_RX_FORCERXMODE_MASK | - MIPI_CSI_DPHY_RX_FORCERXMODE_BIT); + (0x0 << MIPI_CSI_DPHY_RX_FORCERXMODE_BIT)); write_csiphy_reg((MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + 0x100), hsfreqrange | diff --git a/drivers/media/video/rk_camsys/camsys_soc_rk3368.h b/drivers/media/video/rk_camsys/camsys_soc_rk3368.h index b9862ed6574d..121c30eaae08 100644 --- a/drivers/media/video/rk_camsys/camsys_soc_rk3368.h +++ b/drivers/media/video/rk_camsys/camsys_soc_rk3368.h @@ -90,7 +90,7 @@ #define MIPI_CSI_DPHY_LANEX_MSB_EN_OFFSET (0x38) #define MIPI_CSI_DPHY_RX_FORCERXMODE_MASK (0x0f << 24) -#define MIPI_CSI_DPHY_RX_FORCERXMODE_BIT (0 << 8) +#define MIPI_CSI_DPHY_RX_FORCERXMODE_BIT (8) #define CSIHOST_N_LANES_OFFSET 0x04 #define CSIHOST_N_LANES_OFFSET_BIT (0)