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soc: mediatek: mt8167-mmsys: add routes for all display paths
mt8167 display output pipeline can be configured in many different ways. Add support for additional routes according to the SoC data sheet and Android sources. There's a few inconsistencies between those two, but assume the Android sources are correct since they are required to drive HDMI output via DPI1. Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
Luca Leonardo Scorcia
AngeloGioacchino Del Regno
parent
6c53881542
commit
96c2b43b1f
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@ -5,35 +5,200 @@
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#define MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x030
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#define MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN 0x038
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#define MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x03c
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#define MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x058
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#define MT8167_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN 0x05c
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#define MT8167_DISP_REG_CONFIG_DISP_UFOE_SEL_IN 0x060
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#define MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0x064
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#define MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0x068
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#define MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN 0x06c
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#define MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN 0x070
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#define MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN 0x074
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#define MT8167_OVL0_MOUT_EN_COLOR0 0x1
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#define MT8167_OVL0_MOUT_EN_WDMA0 0x2
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#define MT8167_OVL0_MOUT_EN_MASK 0x3
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#define MT8167_DITHER_MOUT_EN_RDMA0 0x1
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#define MT8167_DITHER_MOUT_EN_UFOE 0x2
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#define MT8167_DITHER_MOUT_EN_WDMA0 0x4
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#define MT8167_DITHER_MOUT_EN_MASK 0x7
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#define MT8167_RDMA0_SOUT_DSI0 0x2
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#define MT8167_RDMA0_SOUT_MASK 0x3
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#define MT8167_UFOE_MOUT_EN_DSI0 0x1
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#define MT8167_UFOE_MOUT_EN_DPI0 0x2
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/*
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* For some reason Android sources and the data sheet don't agree here,
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* the data sheet has UFOE_MOUT_EN_WDMA0 as 0x4 and does not mention DPI1.
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*/
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#define MT8167_UFOE_MOUT_EN_DPI1 0x4
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#define MT8167_UFOE_MOUT_EN_WDMA0 0x8
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#define MT8167_UFOE_MOUT_EN_MASK 0xF
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#define MT8167_COLOR0_SEL_IN_RDMA0 0x0
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#define MT8167_COLOR0_SEL_IN_OVL0 0x1
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#define MT8167_COLOR0_SEL_IN_MASK 0x1
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#define MT8167_WDMA0_SEL_IN_OVL0 0x0
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#define MT8167_WDMA0_SEL_IN_DITHER 0x1
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#define MT8167_WDMA0_SEL_IN_UFOE 0x2
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#define MT8167_WDMA0_SEL_IN_MASK 0x3
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#define MT8167_UFOE_SEL_IN_RDMA0 0x0
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#define MT8167_UFOE_SEL_IN_DITHER 0x1
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#define MT8167_UFOE_SEL_IN_MASK 0x1
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#define MT8167_DSI0_SEL_IN_UFOE 0x0
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#define MT8167_DSI0_SEL_IN_RDMA0 0x1
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#define MT8167_DSI0_SEL_IN_RDMA1 0x2
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#define MT8167_DSI0_SEL_IN_MASK 0x3
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#define MT8167_DPI0_SEL_IN_UFOE 0x0
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#define MT8167_DPI0_SEL_IN_RDMA0 0x1
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#define MT8167_DPI0_SEL_IN_RDMA1 0x2
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#define MT8167_DPI0_SEL_IN_MASK 0x3
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#define MT8167_DPI1_SEL_IN_UFOE 0x0
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#define MT8167_DPI1_SEL_IN_RDMA0 0x1
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#define MT8167_DPI1_SEL_IN_RDMA1 0x2
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#define MT8167_DPI1_SEL_IN_MASK 0x3
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#define MT8167_RDMA0_SOUT_UFOE 0x0
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#define MT8167_RDMA0_SOUT_COLOR0 0x1
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#define MT8167_RDMA0_SOUT_DSI0 0x2
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#define MT8167_RDMA0_SOUT_DPI0 0x3
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/* DPI1 is only defined in Android sources, not in the data sheet */
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#define MT8167_RDMA0_SOUT_DPI1 0x4
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#define MT8167_RDMA0_SOUT_MASK 0x7
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#define MT8167_RDMA1_SOUT_DSI0 0x0
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#define MT8167_RDMA1_SOUT_DPI0 0x1
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/* DPI1 is only defined in Android sources, not in the data sheet */
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#define MT8167_RDMA1_SOUT_DPI1 0x2
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#define MT8167_RDMA1_SOUT_MASK 0x3
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static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
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/* OVL0<->COLOR0 */
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MMSYS_ROUTE(OVL, 0, COLOR, 0,
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MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
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OVL0_MOUT_EN_COLOR0),
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MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8167_OVL0_MOUT_EN_MASK,
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MT8167_OVL0_MOUT_EN_COLOR0),
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MMSYS_ROUTE(OVL, 0, COLOR, 0,
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MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8167_COLOR0_SEL_IN_MASK,
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MT8167_COLOR0_SEL_IN_OVL0),
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/* OVL0<->WDMA0 */
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MMSYS_ROUTE(OVL, 0, WDMA, 0,
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MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8167_OVL0_MOUT_EN_MASK,
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MT8167_OVL0_MOUT_EN_WDMA0),
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MMSYS_ROUTE(OVL, 0, WDMA, 0,
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MT8167_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN, MT8167_COLOR0_SEL_IN_MASK,
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MT8167_WDMA0_SEL_IN_OVL0),
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/* DITHER0 outputs */
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MMSYS_ROUTE(DITHER, 0, RDMA, 0,
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MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_MASK,
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MT8167_DITHER_MOUT_EN_RDMA0),
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MMSYS_ROUTE(OVL, 0, COLOR, 0,
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MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
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COLOR0_SEL_IN_OVL0),
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MMSYS_ROUTE(RDMA, 0, DSI, 0,
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MMSYS_ROUTE(DITHER, 0, UFOE, 0,
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MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_MASK,
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MT8167_DITHER_MOUT_EN_UFOE),
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MMSYS_ROUTE(DITHER, 0, WDMA, 0,
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MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_MASK,
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MT8167_DITHER_MOUT_EN_WDMA0),
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/* UFOE<->DSI0 */
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MMSYS_ROUTE(UFOE, 0, DSI, 0,
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MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK,
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MT8167_UFOE_MOUT_EN_DSI0),
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MMSYS_ROUTE(UFOE, 0, DSI, 0,
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MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_MASK,
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MT8167_DSI0_SEL_IN_RDMA0),
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MT8167_DSI0_SEL_IN_UFOE),
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/* UFOE<->DPI0 */
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MMSYS_ROUTE(UFOE, 0, DPI, 0,
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MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK,
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MT8167_UFOE_MOUT_EN_DPI0),
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MMSYS_ROUTE(UFOE, 0, DPI, 0,
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MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, MT8167_DPI0_SEL_IN_MASK,
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MT8167_DPI0_SEL_IN_UFOE),
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/* UFOE<->DPI1 */
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MMSYS_ROUTE(UFOE, 0, DPI, 1,
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MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK,
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MT8167_UFOE_MOUT_EN_DPI1),
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MMSYS_ROUTE(UFOE, 0, DPI, 1,
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MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN, MT8167_DPI1_SEL_IN_MASK,
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MT8167_DPI1_SEL_IN_UFOE),
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/* UFOE<->WDMA0 */
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MMSYS_ROUTE(UFOE, 0, WDMA, 0,
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MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK,
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MT8167_UFOE_MOUT_EN_WDMA0),
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MMSYS_ROUTE(UFOE, 0, WDMA, 0,
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MT8167_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN, MT8167_WDMA0_SEL_IN_MASK,
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MT8167_WDMA0_SEL_IN_UFOE),
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/* RDMA0<->UFOE */
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MMSYS_ROUTE(RDMA, 0, UFOE, 0,
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MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK,
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MT8167_RDMA0_SOUT_UFOE),
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MMSYS_ROUTE(RDMA, 0, UFOE, 0,
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MT8167_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, MT8167_UFOE_SEL_IN_MASK,
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MT8167_UFOE_SEL_IN_RDMA0),
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/* RDMA0->COLOR0 */
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MMSYS_ROUTE(RDMA, 0, COLOR, 0,
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MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK,
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MT8167_RDMA0_SOUT_COLOR0),
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MMSYS_ROUTE(RDMA, 0, COLOR, 0,
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MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8167_COLOR0_SEL_IN_MASK,
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MT8167_COLOR0_SEL_IN_RDMA0),
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/* RDMA0<->DSI0 */
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MMSYS_ROUTE(RDMA, 0, DSI, 0,
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MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK,
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MT8167_RDMA0_SOUT_DSI0),
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MMSYS_ROUTE(RDMA, 0, DSI, 0,
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MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_MASK,
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MT8167_DSI0_SEL_IN_RDMA0),
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/* RDMA0<->DPI0 */
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MMSYS_ROUTE(RDMA, 0, DPI, 0,
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MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK,
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MT8167_RDMA0_SOUT_DPI0),
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MMSYS_ROUTE(RDMA, 0, DPI, 0,
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MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, MT8167_DPI0_SEL_IN_MASK,
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MT8167_DPI0_SEL_IN_RDMA0),
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/* RDMA0<->DPI1 */
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MMSYS_ROUTE(RDMA, 0, DPI, 1,
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MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK,
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MT8167_RDMA0_SOUT_DPI1),
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MMSYS_ROUTE(RDMA, 0, DPI, 1,
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MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN, MT8167_DPI1_SEL_IN_MASK,
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MT8167_DPI1_SEL_IN_RDMA0),
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/* RDMA1<->DSI0 */
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MMSYS_ROUTE(RDMA, 1, DSI, 0,
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MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN, MT8167_RDMA1_SOUT_MASK,
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MT8167_RDMA1_SOUT_DSI0),
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MMSYS_ROUTE(RDMA, 1, DSI, 0,
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MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_MASK,
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MT8167_DSI0_SEL_IN_RDMA1),
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/* RDMA1<->DPI0 */
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MMSYS_ROUTE(RDMA, 1, DPI, 0,
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MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN, MT8167_RDMA1_SOUT_MASK,
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MT8167_RDMA1_SOUT_DPI0),
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MMSYS_ROUTE(RDMA, 1, DPI, 0,
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MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, MT8167_DPI0_SEL_IN_MASK,
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MT8167_DPI0_SEL_IN_RDMA1),
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/* RDMA1<->DPI1 */
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MMSYS_ROUTE(RDMA, 1, DPI, 1,
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MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN, MT8167_RDMA1_SOUT_MASK,
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MT8167_RDMA1_SOUT_DPI1),
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MMSYS_ROUTE(RDMA, 1, DPI, 1,
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MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN, MT8167_DPI1_SEL_IN_MASK,
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MT8167_DPI1_SEL_IN_RDMA1),
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};
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#endif /* __SOC_MEDIATEK_MT8167_MMSYS_H */
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