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arm64: dts: imx95: Add i3c1 and i3c2

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Add i3c1 and i3c2 support.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Frank Li 2025-02-21 16:15:59 -05:00 committed by Shawn Guo
parent c25548f22d
commit 969497ebef
1 changed files with 26 additions and 0 deletions
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26
arch/arm64/boot/dts/freescale/imx95.dtsi
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@ -673,6 +673,19 @@ tpm6: pwm@42510000 {
status = "disabled";
};
i3c2: i3c@42520000 {
compatible = "silvaco,i3c-master-v1";
reg = <0x42520000 0x10000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>;
#size-cells = <0>;
clocks = <&scmi_clk IMX95_CLK_BUSAON>,
<&scmi_clk IMX95_CLK_I3C2>,
<&scmi_clk IMX95_CLK_I3C2SLOW>;
clock-names = "pclk", "fast_clk", "slow_clk";
status = "disabled";
};
lpi2c3: i2c@42530000 {
compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x42530000 0x10000>;
@ -1245,6 +1258,19 @@ tpm2: pwm@44320000 {
status = "disabled";
};
i3c1: i3c@44330000 {
compatible = "silvaco,i3c-master-v1";
reg = <0x44330000 0x10000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>;
#size-cells = <0>;
clocks = <&scmi_clk IMX95_CLK_BUSAON>,
<&scmi_clk IMX95_CLK_I3C1>,
<&scmi_clk IMX95_CLK_I3C1SLOW>;
clock-names = "pclk", "fast_clk", "slow_clk";
status = "disabled";
};
lpi2c1: i2c@44340000 {
compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x44340000 0x10000>;