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net: dsa: b53: ensure BCM5325 PHYs are enabled

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According to the datasheet, BCM5325 uses B53_PD_MODE_CTRL_25 register to
disable clocking to individual PHYs.
Only ports 1-4 can be enabled or disabled and the datasheet is explicit
about not toggling BIT(0) since it disables the PLL power and the switch.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://patch.msgid.link/20250614080000.1884236-15-noltari@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Álvaro Fernández Rojas 2025-06-14 10:00:00 +02:00 committed by Jakub Kicinski
parent c00df10187
commit 966a83df36
2 changed files with 17 additions and 1 deletions
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13
drivers/net/dsa/b53/b53_common.c
View File

@ -660,6 +660,19 @@ int b53_setup_port(struct dsa_switch *ds, int port)
if (dsa_is_user_port(ds, port))
b53_set_eap_mode(dev, port, EAP_MODE_SIMPLIFIED);
if (is5325(dev) &&
in_range(port, 1, 4)) {
u8 reg;
b53_read8(dev, B53_CTRL_PAGE, B53_PD_MODE_CTRL_25, &reg);
reg &= ~PD_MODE_POWER_DOWN_PORT(0);
if (dsa_is_unused_port(ds, port))
reg |= PD_MODE_POWER_DOWN_PORT(port);
else
reg &= ~PD_MODE_POWER_DOWN_PORT(port);
b53_write8(dev, B53_CTRL_PAGE, B53_PD_MODE_CTRL_25, reg);
}
return 0;
}
EXPORT_SYMBOL(b53_setup_port);

5
drivers/net/dsa/b53/b53_regs.h
View File

@ -103,8 +103,11 @@
#define PORT_OVERRIDE_SPEED_2000M BIT(6) /* BCM5301X only, requires setting 1000M */
#define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */
/* Power-down mode control */
/* Power-down mode control (8 bit) */
#define B53_PD_MODE_CTRL_25 0x0f
#define PD_MODE_PORT_MASK 0x1f
/* Bit 0 also powers down the switch. */
#define PD_MODE_POWER_DOWN_PORT(i) BIT(i)
/* IP Multicast control (8 bit) */
#define B53_IP_MULTICAST_CTRL 0x21