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drm/rockchip: hdmi: Limit rk3229/rk3328 max output resolution
Limit RK3229/RK3328 max output resolution to 4K 50/60 YCbCr420 mode. Change-Id: Icb934f6f057503ccb619f4ca6167b0958def336a Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
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@ -2019,6 +2019,13 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
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hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
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}
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if ((hdmi->dev_type == RK3328_HDMI ||
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hdmi->dev_type == RK3228_HDMI) &&
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drm_match_cea_mode(mode) > 94 &&
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mode->crtc_clock > 340000 &&
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!(mode->flags & DRM_MODE_FLAG_420_MASK))
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mode->flags |= DRM_MODE_FLAG_420;
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if (mode->flags & DRM_MODE_FLAG_420_MASK) {
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hdmi->hdmi_data.enc_in_bus_format =
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MEDIA_BUS_FMT_UYYVYY8_0_5X24;
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@ -493,6 +493,18 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
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struct drm_connector_state *conn_state)
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{
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struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
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struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
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if (hdmi->phy) {
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if (drm_match_cea_mode(&crtc_state->mode) > 94 &&
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crtc_state->mode.crtc_clock > 340000 &&
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!(crtc_state->mode.flags & DRM_MODE_FLAG_420_MASK)) {
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crtc_state->mode.flags |= DRM_MODE_FLAG_420;
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phy_set_bus_width(hdmi->phy, 4);
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} else {
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phy_set_bus_width(hdmi->phy, 8);
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}
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}
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if (crtc_state->mode.flags & DRM_MODE_FLAG_420_MASK) {
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s->output_mode = ROCKCHIP_OUT_MODE_YUV420;
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