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media: qcom: iris: split firmware_data from raw platform data

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Having firmware-related fields in platform data results in the tying
platform data to the HFI firmware data rather than the actual hardware.
For example, SM8450 uses Gen2 firmware, so currently its platform data
should be placed next to the other gen2 platforms, although it has the
VPU2.0 core, similar to the one found on SM8250 and SC7280 and so the
hardware-specific platform data is also close to those devices.

Split firmware data to a separate struct, separating hardware-related
data from the firmware interfaces.

Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
This commit is contained in:
Dmitry Baryshkov 2026-03-29 02:33:09 +02:00 committed by Bryan O'Donoghue
parent 10175bca76
commit 95faed0b9f
11 changed files with 211 additions and 376 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

82
drivers/media/platform/qcom/iris/iris_buffer.c
View File

@ -301,31 +301,31 @@ static void iris_fill_internal_buf_info(struct iris_inst *inst,
void iris_get_internal_buffers(struct iris_inst *inst, u32 plane)
{
const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data;
const u32 *internal_buf_type;
u32 internal_buffer_count, i;
if (inst->domain == DECODER) {
if (V4L2_TYPE_IS_OUTPUT(plane)) {
internal_buf_type = platform_data->dec_ip_int_buf_tbl;
internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size;
internal_buf_type = firmware_data->dec_ip_int_buf_tbl;
internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size;
for (i = 0; i < internal_buffer_count; i++)
iris_fill_internal_buf_info(inst, internal_buf_type[i]);
} else {
internal_buf_type = platform_data->dec_op_int_buf_tbl;
internal_buffer_count = platform_data->dec_op_int_buf_tbl_size;
internal_buf_type = firmware_data->dec_op_int_buf_tbl;
internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size;
for (i = 0; i < internal_buffer_count; i++)
iris_fill_internal_buf_info(inst, internal_buf_type[i]);
}
} else {
if (V4L2_TYPE_IS_OUTPUT(plane)) {
internal_buf_type = platform_data->enc_ip_int_buf_tbl;
internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size;
internal_buf_type = firmware_data->enc_ip_int_buf_tbl;
internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size;
for (i = 0; i < internal_buffer_count; i++)
iris_fill_internal_buf_info(inst, internal_buf_type[i]);
} else {
internal_buf_type = platform_data->enc_op_int_buf_tbl;
internal_buffer_count = platform_data->enc_op_int_buf_tbl_size;
internal_buf_type = firmware_data->enc_op_int_buf_tbl;
internal_buffer_count = firmware_data->enc_op_int_buf_tbl_size;
for (i = 0; i < internal_buffer_count; i++)
iris_fill_internal_buf_info(inst, internal_buf_type[i]);
}
@ -366,7 +366,7 @@ static int iris_create_internal_buffer(struct iris_inst *inst,
int iris_create_internal_buffers(struct iris_inst *inst, u32 plane)
{
const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data;
u32 internal_buffer_count, i, j;
struct iris_buffers *buffers;
const u32 *internal_buf_type;
@ -374,19 +374,19 @@ int iris_create_internal_buffers(struct iris_inst *inst, u32 plane)
if (inst->domain == DECODER) {
if (V4L2_TYPE_IS_OUTPUT(plane)) {
internal_buf_type = platform_data->dec_ip_int_buf_tbl;
internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size;
internal_buf_type = firmware_data->dec_ip_int_buf_tbl;
internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size;
} else {
internal_buf_type = platform_data->dec_op_int_buf_tbl;
internal_buffer_count = platform_data->dec_op_int_buf_tbl_size;
internal_buf_type = firmware_data->dec_op_int_buf_tbl;
internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size;
}
} else {
if (V4L2_TYPE_IS_OUTPUT(plane)) {
internal_buf_type = platform_data->enc_ip_int_buf_tbl;
internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size;
internal_buf_type = firmware_data->enc_ip_int_buf_tbl;
internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size;
} else {
internal_buf_type = platform_data->enc_op_int_buf_tbl;
internal_buffer_count = platform_data->enc_op_int_buf_tbl_size;
internal_buf_type = firmware_data->enc_op_int_buf_tbl;
internal_buffer_count = firmware_data->enc_op_int_buf_tbl_size;
}
}
@ -442,7 +442,7 @@ int iris_queue_internal_deferred_buffers(struct iris_inst *inst, enum iris_buffe
int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane)
{
const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data;
struct iris_buffer *buffer, *next;
struct iris_buffers *buffers;
const u32 *internal_buf_type;
@ -451,19 +451,19 @@ int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane)
if (inst->domain == DECODER) {
if (V4L2_TYPE_IS_OUTPUT(plane)) {
internal_buf_type = platform_data->dec_ip_int_buf_tbl;
internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size;
internal_buf_type = firmware_data->dec_ip_int_buf_tbl;
internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size;
} else {
internal_buf_type = platform_data->dec_op_int_buf_tbl;
internal_buffer_count = platform_data->dec_op_int_buf_tbl_size;
internal_buf_type = firmware_data->dec_op_int_buf_tbl;
internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size;
}
} else {
if (V4L2_TYPE_IS_OUTPUT(plane)) {
internal_buf_type = platform_data->enc_ip_int_buf_tbl;
internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size;
internal_buf_type = firmware_data->enc_ip_int_buf_tbl;
internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size;
} else {
internal_buf_type = platform_data->enc_op_int_buf_tbl;
internal_buffer_count = platform_data->enc_op_int_buf_tbl_size;
internal_buf_type = firmware_data->enc_op_int_buf_tbl;
internal_buffer_count = firmware_data->enc_op_int_buf_tbl_size;
}
}
@ -501,7 +501,7 @@ int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffer *buf
static int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane, bool force)
{
const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data;
struct iris_buffer *buf, *next;
struct iris_buffers *buffers;
const u32 *internal_buf_type;
@ -510,19 +510,19 @@ static int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane, bool
if (inst->domain == DECODER) {
if (V4L2_TYPE_IS_OUTPUT(plane)) {
internal_buf_type = platform_data->dec_ip_int_buf_tbl;
len = platform_data->dec_ip_int_buf_tbl_size;
internal_buf_type = firmware_data->dec_ip_int_buf_tbl;
len = firmware_data->dec_ip_int_buf_tbl_size;
} else {
internal_buf_type = platform_data->dec_op_int_buf_tbl;
len = platform_data->dec_op_int_buf_tbl_size;
internal_buf_type = firmware_data->dec_op_int_buf_tbl;
len = firmware_data->dec_op_int_buf_tbl_size;
}
} else {
if (V4L2_TYPE_IS_OUTPUT(plane)) {
internal_buf_type = platform_data->enc_ip_int_buf_tbl;
len = platform_data->enc_ip_int_buf_tbl_size;
internal_buf_type = firmware_data->enc_ip_int_buf_tbl;
len = firmware_data->enc_ip_int_buf_tbl_size;
} else {
internal_buf_type = platform_data->enc_op_int_buf_tbl;
len = platform_data->enc_op_int_buf_tbl_size;
internal_buf_type = firmware_data->enc_op_int_buf_tbl;
len = firmware_data->enc_op_int_buf_tbl_size;
}
}
@ -593,17 +593,17 @@ static int iris_release_internal_buffers(struct iris_inst *inst,
static int iris_release_input_internal_buffers(struct iris_inst *inst)
{
const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data;
const u32 *internal_buf_type;
u32 internal_buffer_count, i;
int ret;
if (inst->domain == DECODER) {
internal_buf_type = platform_data->dec_ip_int_buf_tbl;
internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size;
internal_buf_type = firmware_data->dec_ip_int_buf_tbl;
internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size;
} else {
internal_buf_type = platform_data->enc_ip_int_buf_tbl;
internal_buffer_count = platform_data->enc_ip_int_buf_tbl_size;
internal_buf_type = firmware_data->enc_ip_int_buf_tbl;
internal_buffer_count = firmware_data->enc_ip_int_buf_tbl_size;
}
for (i = 0; i < internal_buffer_count; i++) {

2
drivers/media/platform/qcom/iris/iris_core.h
View File

@ -54,6 +54,7 @@ struct qcom_ubwc_cfg_data;
* @resets: table of iris reset clocks
* @controller_resets: table of controller reset clocks
* @iris_platform_data: a structure for platform data
* @iris_firmware_data: a pointer to the firmware (or HFI) specific data
* @ubwc_cfg: UBWC configuration for the platform
* @state: current state of core
* @iface_q_table_daddr: device address for interface queue table memory
@ -97,6 +98,7 @@ struct iris_core {
struct reset_control_bulk_data *resets;
struct reset_control_bulk_data *controller_resets;
const struct iris_platform_data *iris_platform_data;
const struct iris_firmware_data *iris_firmware_data;
const struct qcom_ubwc_cfg_data *ubwc_cfg;
enum iris_core_state state;
dma_addr_t iface_q_table_daddr;

8
drivers/media/platform/qcom/iris/iris_ctrls.c
View File

@ -332,8 +332,8 @@ void iris_session_init_caps(struct iris_core *core)
const struct platform_inst_fw_cap *caps;
u32 i, num_cap, cap_id;
caps = core->iris_platform_data->inst_fw_caps_dec;
num_cap = core->iris_platform_data->inst_fw_caps_dec_size;
caps = core->iris_firmware_data->inst_fw_caps_dec;
num_cap = core->iris_firmware_data->inst_fw_caps_dec_size;
for (i = 0; i < num_cap; i++) {
cap_id = caps[i].cap_id;
@ -360,8 +360,8 @@ void iris_session_init_caps(struct iris_core *core)
}
}
caps = core->iris_platform_data->inst_fw_caps_enc;
num_cap = core->iris_platform_data->inst_fw_caps_enc_size;
caps = core->iris_firmware_data->inst_fw_caps_enc;
num_cap = core->iris_firmware_data->inst_fw_caps_enc_size;
for (i = 0; i < num_cap; i++) {
cap_id = caps[i].cap_id;

8
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
View File

@ -1033,8 +1033,8 @@ static int iris_hfi_gen1_session_set_config_params(struct iris_inst *inst, u32 p
};
if (inst->domain == DECODER) {
config_params = core->iris_platform_data->dec_input_config_params_default;
config_params_size = core->iris_platform_data->dec_input_config_params_default_size;
config_params = core->iris_firmware_data->dec_input_config_params_default;
config_params_size = core->iris_firmware_data->dec_input_config_params_default_size;
if (V4L2_TYPE_IS_OUTPUT(plane)) {
handler = vdec_prop_type_handle_inp_arr;
handler_size = ARRAY_SIZE(vdec_prop_type_handle_inp_arr);
@ -1043,8 +1043,8 @@ static int iris_hfi_gen1_session_set_config_params(struct iris_inst *inst, u32 p
handler_size = ARRAY_SIZE(vdec_prop_type_handle_out_arr);
}
} else {
config_params = core->iris_platform_data->enc_input_config_params;
config_params_size = core->iris_platform_data->enc_input_config_params_size;
config_params = core->iris_firmware_data->enc_input_config_params;
config_params_size = core->iris_firmware_data->enc_input_config_params_size;
handler = venc_prop_type_handle_inp_arr;
handler_size = ARRAY_SIZE(venc_prop_type_handle_inp_arr);
}

66
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
View File

@ -601,7 +601,7 @@ static int iris_hfi_gen2_set_super_block(struct iris_inst *inst, u32 plane)
static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst, u32 plane)
{
const struct iris_platform_data *pdata = inst->core->iris_platform_data;
const struct iris_firmware_data *fdata = inst->core->iris_firmware_data;
u32 config_params_size = 0, i, j;
const u32 *config_params = NULL;
int ret;
@ -630,31 +630,31 @@ static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst, u32 p
if (inst->domain == DECODER) {
if (V4L2_TYPE_IS_OUTPUT(plane)) {
if (inst->codec == V4L2_PIX_FMT_H264) {
config_params = pdata->dec_input_config_params_default;
config_params_size = pdata->dec_input_config_params_default_size;
config_params = fdata->dec_input_config_params_default;
config_params_size = fdata->dec_input_config_params_default_size;
} else if (inst->codec == V4L2_PIX_FMT_HEVC) {
config_params = pdata->dec_input_config_params_hevc;
config_params_size = pdata->dec_input_config_params_hevc_size;
config_params = fdata->dec_input_config_params_hevc;
config_params_size = fdata->dec_input_config_params_hevc_size;
} else if (inst->codec == V4L2_PIX_FMT_VP9) {
config_params = pdata->dec_input_config_params_vp9;
config_params_size = pdata->dec_input_config_params_vp9_size;
config_params = fdata->dec_input_config_params_vp9;
config_params_size = fdata->dec_input_config_params_vp9_size;
} else if (inst->codec == V4L2_PIX_FMT_AV1) {
config_params = pdata->dec_input_config_params_av1;
config_params_size = pdata->dec_input_config_params_av1_size;
config_params = fdata->dec_input_config_params_av1;
config_params_size = fdata->dec_input_config_params_av1_size;
} else {
return -EINVAL;
}
} else {
config_params = pdata->dec_output_config_params;
config_params_size = pdata->dec_output_config_params_size;
config_params = fdata->dec_output_config_params;
config_params_size = fdata->dec_output_config_params_size;
}
} else {
if (V4L2_TYPE_IS_OUTPUT(plane)) {
config_params = pdata->enc_input_config_params;
config_params_size = pdata->enc_input_config_params_size;
config_params = fdata->enc_input_config_params;
config_params_size = fdata->enc_input_config_params_size;
} else {
config_params = pdata->enc_output_config_params;
config_params_size = pdata->enc_output_config_params_size;
config_params = fdata->enc_output_config_params;
config_params_size = fdata->enc_output_config_params_size;
}
}
@ -849,24 +849,24 @@ static int iris_hfi_gen2_subscribe_change_param(struct iris_inst *inst, u32 plan
switch (inst->codec) {
case V4L2_PIX_FMT_H264:
change_param = core->iris_platform_data->dec_input_config_params_default;
change_param = core->iris_firmware_data->dec_input_config_params_default;
change_param_size =
core->iris_platform_data->dec_input_config_params_default_size;
core->iris_firmware_data->dec_input_config_params_default_size;
break;
case V4L2_PIX_FMT_HEVC:
change_param = core->iris_platform_data->dec_input_config_params_hevc;
change_param = core->iris_firmware_data->dec_input_config_params_hevc;
change_param_size =
core->iris_platform_data->dec_input_config_params_hevc_size;
core->iris_firmware_data->dec_input_config_params_hevc_size;
break;
case V4L2_PIX_FMT_VP9:
change_param = core->iris_platform_data->dec_input_config_params_vp9;
change_param = core->iris_firmware_data->dec_input_config_params_vp9;
change_param_size =
core->iris_platform_data->dec_input_config_params_vp9_size;
core->iris_firmware_data->dec_input_config_params_vp9_size;
break;
case V4L2_PIX_FMT_AV1:
change_param = core->iris_platform_data->dec_input_config_params_av1;
change_param = core->iris_firmware_data->dec_input_config_params_av1;
change_param_size =
core->iris_platform_data->dec_input_config_params_av1_size;
core->iris_firmware_data->dec_input_config_params_av1_size;
break;
}
@ -996,29 +996,29 @@ static int iris_hfi_gen2_subscribe_property(struct iris_inst *inst, u32 plane)
return 0;
if (V4L2_TYPE_IS_OUTPUT(plane)) {
subscribe_prop_size = core->iris_platform_data->dec_input_prop_size;
subcribe_prop = core->iris_platform_data->dec_input_prop;
subscribe_prop_size = core->iris_firmware_data->dec_input_prop_size;
subcribe_prop = core->iris_firmware_data->dec_input_prop;
} else {
switch (inst->codec) {
case V4L2_PIX_FMT_H264:
subcribe_prop = core->iris_platform_data->dec_output_prop_avc;
subcribe_prop = core->iris_firmware_data->dec_output_prop_avc;
subscribe_prop_size =
core->iris_platform_data->dec_output_prop_avc_size;
core->iris_firmware_data->dec_output_prop_avc_size;
break;
case V4L2_PIX_FMT_HEVC:
subcribe_prop = core->iris_platform_data->dec_output_prop_hevc;
subcribe_prop = core->iris_firmware_data->dec_output_prop_hevc;
subscribe_prop_size =
core->iris_platform_data->dec_output_prop_hevc_size;
core->iris_firmware_data->dec_output_prop_hevc_size;
break;
case V4L2_PIX_FMT_VP9:
subcribe_prop = core->iris_platform_data->dec_output_prop_vp9;
subcribe_prop = core->iris_firmware_data->dec_output_prop_vp9;
subscribe_prop_size =
core->iris_platform_data->dec_output_prop_vp9_size;
core->iris_firmware_data->dec_output_prop_vp9_size;
break;
case V4L2_PIX_FMT_AV1:
subcribe_prop = core->iris_platform_data->dec_output_prop_av1;
subcribe_prop = core->iris_firmware_data->dec_output_prop_av1;
subscribe_prop_size =
core->iris_platform_data->dec_output_prop_av1_size;
core->iris_firmware_data->dec_output_prop_av1_size;
break;
}
}

91
drivers/media/platform/qcom/iris/iris_platform_common.h
View File

@ -201,9 +201,61 @@ enum platform_pm_domain_type {
IRIS_APV_HW_POWER_DOMAIN,
};
struct iris_platform_data {
struct iris_firmware_data {
void (*init_hfi_ops)(struct iris_core *core);
u32 core_arch;
const struct platform_inst_fw_cap *inst_fw_caps_dec;
u32 inst_fw_caps_dec_size;
const struct platform_inst_fw_cap *inst_fw_caps_enc;
u32 inst_fw_caps_enc_size;
const u32 *dec_input_config_params_default;
unsigned int dec_input_config_params_default_size;
const u32 *dec_input_config_params_hevc;
unsigned int dec_input_config_params_hevc_size;
const u32 *dec_input_config_params_vp9;
unsigned int dec_input_config_params_vp9_size;
const u32 *dec_input_config_params_av1;
unsigned int dec_input_config_params_av1_size;
const u32 *dec_output_config_params;
unsigned int dec_output_config_params_size;
const u32 *enc_input_config_params;
unsigned int enc_input_config_params_size;
const u32 *enc_output_config_params;
unsigned int enc_output_config_params_size;
const u32 *dec_input_prop;
unsigned int dec_input_prop_size;
const u32 *dec_output_prop_avc;
unsigned int dec_output_prop_avc_size;
const u32 *dec_output_prop_hevc;
unsigned int dec_output_prop_hevc_size;
const u32 *dec_output_prop_vp9;
unsigned int dec_output_prop_vp9_size;
const u32 *dec_output_prop_av1;
unsigned int dec_output_prop_av1_size;
const u32 *dec_ip_int_buf_tbl;
unsigned int dec_ip_int_buf_tbl_size;
const u32 *dec_op_int_buf_tbl;
unsigned int dec_op_int_buf_tbl_size;
const u32 *enc_ip_int_buf_tbl;
unsigned int enc_ip_int_buf_tbl_size;
const u32 *enc_op_int_buf_tbl;
unsigned int enc_op_int_buf_tbl_size;
};
struct iris_platform_data {
/*
* XXX: remove firmware_data pointer and consider moving
* get_vpu_buffer_size pointer once we have platforms supporting both
* firmware kinds.
*/
const struct iris_firmware_data *firmware_data;
u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type);
const struct vpu_ops *vpu_ops;
const struct icc_info *icc_tbl;
unsigned int icc_tbl_size;
@ -225,13 +277,8 @@ struct iris_platform_data {
struct iris_fmt *inst_iris_fmts;
u32 inst_iris_fmts_size;
struct platform_inst_caps *inst_caps;
const struct platform_inst_fw_cap *inst_fw_caps_dec;
u32 inst_fw_caps_dec_size;
const struct platform_inst_fw_cap *inst_fw_caps_enc;
u32 inst_fw_caps_enc_size;
const struct tz_cp_config *tz_cp_config_data;
u32 tz_cp_config_data_size;
u32 core_arch;
u32 num_vpp_pipe;
bool no_aon;
u32 max_session_count;
@ -239,38 +286,6 @@ struct iris_platform_data {
u32 max_core_mbpf;
/* max number of macroblocks per second supported */
u32 max_core_mbps;
const u32 *dec_input_config_params_default;
unsigned int dec_input_config_params_default_size;
const u32 *dec_input_config_params_hevc;
unsigned int dec_input_config_params_hevc_size;
const u32 *dec_input_config_params_vp9;
unsigned int dec_input_config_params_vp9_size;
const u32 *dec_input_config_params_av1;
unsigned int dec_input_config_params_av1_size;
const u32 *dec_output_config_params;
unsigned int dec_output_config_params_size;
const u32 *enc_input_config_params;
unsigned int enc_input_config_params_size;
const u32 *enc_output_config_params;
unsigned int enc_output_config_params_size;
const u32 *dec_input_prop;
unsigned int dec_input_prop_size;
const u32 *dec_output_prop_avc;
unsigned int dec_output_prop_avc_size;
const u32 *dec_output_prop_hevc;
unsigned int dec_output_prop_hevc_size;
const u32 *dec_output_prop_vp9;
unsigned int dec_output_prop_vp9_size;
const u32 *dec_output_prop_av1;
unsigned int dec_output_prop_av1_size;
const u32 *dec_ip_int_buf_tbl;
unsigned int dec_ip_int_buf_tbl_size;
const u32 *dec_op_int_buf_tbl;
unsigned int dec_op_int_buf_tbl_size;
const u32 *enc_ip_int_buf_tbl;
unsigned int enc_ip_int_buf_tbl_size;
const u32 *enc_op_int_buf_tbl;
unsigned int enc_op_int_buf_tbl_size;
};
#endif

67
drivers/media/platform/qcom/iris/iris_platform_gen1.c
View File

@ -332,8 +332,33 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] = {
BUF_SCRATCH_2,
};
const struct iris_platform_data sm8250_data = {
const struct iris_firmware_data iris_hfi_gen1_data = {
.init_hfi_ops = &iris_hfi_gen1_sys_ops_init,
.inst_fw_caps_dec = inst_fw_cap_sm8250_dec,
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec),
.inst_fw_caps_enc = inst_fw_cap_sm8250_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc),
.dec_input_config_params_default =
sm8250_vdec_input_config_param_default,
.dec_input_config_params_default_size =
ARRAY_SIZE(sm8250_vdec_input_config_param_default),
.enc_input_config_params = sm8250_venc_input_config_param,
.enc_input_config_params_size =
ARRAY_SIZE(sm8250_venc_input_config_param),
.dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl,
.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl),
.dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl,
.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl),
.enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
};
const struct iris_platform_data sm8250_data = {
.firmware_data = &iris_hfi_gen1_data,
.get_vpu_buffer_size = iris_vpu_buf_size,
.vpu_ops = &iris_vpu2_ops,
.icc_tbl = sm8250_icc_table,
@ -355,35 +380,16 @@ const struct iris_platform_data sm8250_data = {
.inst_iris_fmts = platform_fmts_sm8250_dec,
.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec),
.inst_caps = &platform_inst_cap_sm8250,
.inst_fw_caps_dec = inst_fw_cap_sm8250_dec,
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec),
.inst_fw_caps_enc = inst_fw_cap_sm8250_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc),
.tz_cp_config_data = tz_cp_config_sm8250,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250),
.num_vpp_pipe = 4,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
.dec_input_config_params_default =
sm8250_vdec_input_config_param_default,
.dec_input_config_params_default_size =
ARRAY_SIZE(sm8250_vdec_input_config_param_default),
.enc_input_config_params = sm8250_venc_input_config_param,
.enc_input_config_params_size =
ARRAY_SIZE(sm8250_venc_input_config_param),
.dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl,
.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl),
.dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl,
.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl),
.enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
};
const struct iris_platform_data sc7280_data = {
.init_hfi_ops = &iris_hfi_gen1_sys_ops_init,
.firmware_data = &iris_hfi_gen1_data,
.get_vpu_buffer_size = iris_vpu_buf_size,
.vpu_ops = &iris_vpu2_ops,
.icc_tbl = sm8250_icc_table,
@ -403,10 +409,6 @@ const struct iris_platform_data sc7280_data = {
.inst_iris_fmts = platform_fmts_sm8250_dec,
.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec),
.inst_caps = &platform_inst_cap_sm8250,
.inst_fw_caps_dec = inst_fw_cap_sm8250_dec,
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec),
.inst_fw_caps_enc = inst_fw_cap_sm8250_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc),
.tz_cp_config_data = tz_cp_config_sm8250,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250),
.num_vpp_pipe = 1,
@ -415,19 +417,4 @@ const struct iris_platform_data sc7280_data = {
.max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256,
/* max spec for SC7280 is 4096x2176@60fps */
.max_core_mbps = 4096 * 2176 / 256 * 60,
.dec_input_config_params_default =
sm8250_vdec_input_config_param_default,
.dec_input_config_params_default_size =
ARRAY_SIZE(sm8250_vdec_input_config_param_default),
.enc_input_config_params = sm8250_venc_input_config_param,
.enc_input_config_params_size =
ARRAY_SIZE(sm8250_venc_input_config_param),
.dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl,
.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl),
.dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl,
.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl),
.enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
};

248
drivers/media/platform/qcom/iris/iris_platform_gen2.c
View File

@ -906,40 +906,16 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = {
BUF_SCRATCH_2,
};
const struct iris_platform_data sm8550_data = {
const struct iris_firmware_data iris_hfi_gen2_data = {
.init_hfi_ops = iris_hfi_gen2_sys_ops_init,
.get_vpu_buffer_size = iris_vpu_buf_size,
.vpu_ops = &iris_vpu3_ops,
.icc_tbl = sm8550_icc_table,
.icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
.clk_rst_tbl = sm8550_clk_reset_table,
.clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
.bw_tbl_dec = sm8550_bw_table_dec,
.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
.pmdomain_tbl = sm8550_pmdomain_table,
.pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
.opp_pd_tbl = sm8550_opp_pd_table,
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
.opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu30_p4.mbn",
.inst_iris_fmts = platform_fmts_sm8550_dec,
.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
.inst_caps = &platform_inst_cap_sm8550,
.core_arch = VIDEO_ARCH_LX,
.inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
.tz_cp_config_data = tz_cp_config_sm8550,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
.core_arch = VIDEO_ARCH_LX,
.num_vpp_pipe = 4,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K * 2,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
.dec_input_config_params_default =
sm8550_vdec_input_config_params_default,
.dec_input_config_params_default_size =
@ -996,6 +972,37 @@ const struct iris_platform_data sm8550_data = {
.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
};
const struct iris_platform_data sm8550_data = {
.firmware_data = &iris_hfi_gen2_data,
.get_vpu_buffer_size = iris_vpu_buf_size,
.vpu_ops = &iris_vpu3_ops,
.icc_tbl = sm8550_icc_table,
.icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
.clk_rst_tbl = sm8550_clk_reset_table,
.clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
.bw_tbl_dec = sm8550_bw_table_dec,
.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
.pmdomain_tbl = sm8550_pmdomain_table,
.pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
.opp_pd_tbl = sm8550_opp_pd_table,
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
.opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu30_p4.mbn",
.inst_iris_fmts = platform_fmts_sm8550_dec,
.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
.inst_caps = &platform_inst_cap_sm8550,
.tz_cp_config_data = tz_cp_config_sm8550,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
.num_vpp_pipe = 4,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K * 2,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
};
/*
* Shares most of SM8550 data except:
* - vpu_ops to iris_vpu33_ops
@ -1004,7 +1011,7 @@ const struct iris_platform_data sm8550_data = {
* - fwname to "qcom/vpu/vpu33_p4.mbn"
*/
const struct iris_platform_data sm8650_data = {
.init_hfi_ops = iris_hfi_gen2_sys_ops_init,
.firmware_data = &iris_hfi_gen2_data,
.get_vpu_buffer_size = iris_vpu33_buf_size,
.vpu_ops = &iris_vpu33_ops,
.icc_tbl = sm8550_icc_table,
@ -1028,75 +1035,16 @@ const struct iris_platform_data sm8650_data = {
.inst_iris_fmts = platform_fmts_sm8550_dec,
.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
.inst_caps = &platform_inst_cap_sm8550,
.inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
.tz_cp_config_data = tz_cp_config_sm8550,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
.core_arch = VIDEO_ARCH_LX,
.num_vpp_pipe = 4,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K * 2,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
.dec_input_config_params_default =
sm8550_vdec_input_config_params_default,
.dec_input_config_params_default_size =
ARRAY_SIZE(sm8550_vdec_input_config_params_default),
.dec_input_config_params_hevc =
sm8550_vdec_input_config_param_hevc,
.dec_input_config_params_hevc_size =
ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
.dec_input_config_params_vp9 =
sm8550_vdec_input_config_param_vp9,
.dec_input_config_params_vp9_size =
ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
.dec_input_config_params_av1 =
sm8550_vdec_input_config_param_av1,
.dec_input_config_params_av1_size =
ARRAY_SIZE(sm8550_vdec_input_config_param_av1),
.dec_output_config_params =
sm8550_vdec_output_config_params,
.dec_output_config_params_size =
ARRAY_SIZE(sm8550_vdec_output_config_params),
.enc_input_config_params =
sm8550_venc_input_config_params,
.enc_input_config_params_size =
ARRAY_SIZE(sm8550_venc_input_config_params),
.enc_output_config_params =
sm8550_venc_output_config_params,
.enc_output_config_params_size =
ARRAY_SIZE(sm8550_venc_output_config_params),
.dec_input_prop = sm8550_vdec_subscribe_input_properties,
.dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
.dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
.dec_output_prop_avc_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
.dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
.dec_output_prop_hevc_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
.dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
.dec_output_prop_vp9_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
.dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1,
.dec_output_prop_av1_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1),
.dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
.dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
.enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl,
.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl),
.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
};
const struct iris_platform_data sm8750_data = {
.init_hfi_ops = iris_hfi_gen2_sys_ops_init,
.firmware_data = &iris_hfi_gen2_data,
.get_vpu_buffer_size = iris_vpu33_buf_size,
.vpu_ops = &iris_vpu35_ops,
.icc_tbl = sm8550_icc_table,
@ -1118,71 +1066,12 @@ const struct iris_platform_data sm8750_data = {
.inst_iris_fmts = platform_fmts_sm8550_dec,
.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
.inst_caps = &platform_inst_cap_sm8550,
.inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
.tz_cp_config_data = tz_cp_config_sm8550,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
.core_arch = VIDEO_ARCH_LX,
.num_vpp_pipe = 4,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K * 2,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
.dec_input_config_params_default =
sm8550_vdec_input_config_params_default,
.dec_input_config_params_default_size =
ARRAY_SIZE(sm8550_vdec_input_config_params_default),
.dec_input_config_params_hevc =
sm8550_vdec_input_config_param_hevc,
.dec_input_config_params_hevc_size =
ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
.dec_input_config_params_vp9 =
sm8550_vdec_input_config_param_vp9,
.dec_input_config_params_vp9_size =
ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
.dec_input_config_params_av1 =
sm8550_vdec_input_config_param_av1,
.dec_input_config_params_av1_size =
ARRAY_SIZE(sm8550_vdec_input_config_param_av1),
.dec_output_config_params =
sm8550_vdec_output_config_params,
.dec_output_config_params_size =
ARRAY_SIZE(sm8550_vdec_output_config_params),
.enc_input_config_params =
sm8550_venc_input_config_params,
.enc_input_config_params_size =
ARRAY_SIZE(sm8550_venc_input_config_params),
.enc_output_config_params =
sm8550_venc_output_config_params,
.enc_output_config_params_size =
ARRAY_SIZE(sm8550_venc_output_config_params),
.dec_input_prop = sm8550_vdec_subscribe_input_properties,
.dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
.dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
.dec_output_prop_avc_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
.dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
.dec_output_prop_hevc_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
.dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
.dec_output_prop_vp9_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
.dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1,
.dec_output_prop_av1_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1),
.dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
.dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
.enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl,
.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl),
.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
};
/*
@ -1190,7 +1079,7 @@ const struct iris_platform_data sm8750_data = {
* - inst_caps to platform_inst_cap_qcs8300
*/
const struct iris_platform_data qcs8300_data = {
.init_hfi_ops = iris_hfi_gen2_sys_ops_init,
.firmware_data = &iris_hfi_gen2_data,
.get_vpu_buffer_size = iris_vpu_buf_size,
.vpu_ops = &iris_vpu3_ops,
.icc_tbl = sm8550_icc_table,
@ -1212,69 +1101,10 @@ const struct iris_platform_data qcs8300_data = {
.inst_iris_fmts = platform_fmts_sm8550_dec,
.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
.inst_caps = &platform_inst_cap_qcs8300,
.inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
.tz_cp_config_data = tz_cp_config_sm8550,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
.core_arch = VIDEO_ARCH_LX,
.num_vpp_pipe = 2,
.max_session_count = 16,
.max_core_mbpf = ((4096 * 2176) / 256) * 4,
.max_core_mbps = (((3840 * 2176) / 256) * 120),
.dec_input_config_params_default =
sm8550_vdec_input_config_params_default,
.dec_input_config_params_default_size =
ARRAY_SIZE(sm8550_vdec_input_config_params_default),
.dec_input_config_params_hevc =
sm8550_vdec_input_config_param_hevc,
.dec_input_config_params_hevc_size =
ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
.dec_input_config_params_vp9 =
sm8550_vdec_input_config_param_vp9,
.dec_input_config_params_vp9_size =
ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
.dec_input_config_params_av1 =
sm8550_vdec_input_config_param_av1,
.dec_input_config_params_av1_size =
ARRAY_SIZE(sm8550_vdec_input_config_param_av1),
.dec_output_config_params =
sm8550_vdec_output_config_params,
.dec_output_config_params_size =
ARRAY_SIZE(sm8550_vdec_output_config_params),
.enc_input_config_params =
sm8550_venc_input_config_params,
.enc_input_config_params_size =
ARRAY_SIZE(sm8550_venc_input_config_params),
.enc_output_config_params =
sm8550_venc_output_config_params,
.enc_output_config_params_size =
ARRAY_SIZE(sm8550_venc_output_config_params),
.dec_input_prop = sm8550_vdec_subscribe_input_properties,
.dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
.dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
.dec_output_prop_avc_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
.dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
.dec_output_prop_hevc_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
.dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
.dec_output_prop_vp9_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
.dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1,
.dec_output_prop_av1_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1),
.dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
.dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
.enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl,
.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl),
.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
};

3
drivers/media/platform/qcom/iris/iris_probe.c
View File

@ -251,6 +251,7 @@ static int iris_probe(struct platform_device *pdev)
return core->irq;
core->iris_platform_data = of_device_get_match_data(core->dev);
core->iris_firmware_data = core->iris_platform_data->firmware_data;
core->ubwc_cfg = qcom_ubwc_config_get_data();
if (IS_ERR(core->ubwc_cfg))
@ -264,7 +265,7 @@ static int iris_probe(struct platform_device *pdev)
disable_irq_nosync(core->irq);
iris_init_ops(core);
core->iris_platform_data->init_hfi_ops(core);
core->iris_firmware_data->init_hfi_ops(core);
ret = iris_init_resources(core);
if (ret)

10
drivers/media/platform/qcom/iris/iris_vidc.c
View File

@ -243,7 +243,7 @@ static void iris_session_close(struct iris_inst *inst)
static void iris_check_num_queued_internal_buffers(struct iris_inst *inst, u32 plane)
{
const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data;
struct iris_buffer *buf, *next;
struct iris_buffers *buffers;
const u32 *internal_buf_type;
@ -251,11 +251,11 @@ static void iris_check_num_queued_internal_buffers(struct iris_inst *inst, u32 p
u32 count = 0;
if (V4L2_TYPE_IS_OUTPUT(plane)) {
internal_buf_type = platform_data->dec_ip_int_buf_tbl;
internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size;
internal_buf_type = firmware_data->dec_ip_int_buf_tbl;
internal_buffer_count = firmware_data->dec_ip_int_buf_tbl_size;
} else {
internal_buf_type = platform_data->dec_op_int_buf_tbl;
internal_buffer_count = platform_data->dec_op_int_buf_tbl_size;
internal_buf_type = firmware_data->dec_op_int_buf_tbl;
internal_buffer_count = firmware_data->dec_op_int_buf_tbl_size;
}
for (i = 0; i < internal_buffer_count; i++) {

2
drivers/media/platform/qcom/iris/iris_vpu_common.c
View File

@ -63,7 +63,7 @@ static void iris_vpu_setup_ucregion_memory_map(struct iris_core *core)
writel(QTBL_ENABLE, core->reg_base + QTBL_INFO);
if (core->sfr_daddr) {
value = (u32)core->sfr_daddr + core->iris_platform_data->core_arch;
value = (u32)core->sfr_daddr + core->iris_firmware_data->core_arch;
writel(value, core->reg_base + SFR_ADDR);
}