mirror of
https://github.com/torvalds/linux.git
synced 2026-10-13 13:51:03 +02:00
arm64: dts: imx8mp-frdm: add sd, ethernet, wifi, usb and hdmi support
Add support for the following new features: - SD Card - Ethernet (FEC + EQOS) - Wifi - USB - HDMI Signed-off-by: Fabian Pfitzner <f.pfitzner@pengutronix.de> Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Fabian Pfitzner
Frank Li
parent
e77f8e6bba
commit
95d7d7d2ad
|
|
@ -42,6 +42,67 @@ memory@40000000 {
|
|||
reg = <0x0 0x40000000 0 0xc0000000>,
|
||||
<0x1 0x00000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
native-hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
label = "HDMI OUT";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_in: endpoint {
|
||||
remote-endpoint = <&hdmi_tx_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-sd {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usb_vbus: regulator-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "USB_VBUS";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&pcal6416_1 5 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usdhc1_vmmc: regulator-wifi-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "WLAN_EN";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&pcal6416_1 10 GPIO_ACTIVE_HIGH>;
|
||||
/*
|
||||
* IW612 wifi chip needs more delay than other wifi chips to complete
|
||||
* the host interface initialization after power up, otherwise the
|
||||
* internal state of IW612 may be unstable, resulting in the failure of
|
||||
* the SDIO3.0 switch voltage.
|
||||
*/
|
||||
enable-active-high;
|
||||
startup-delay-us = <20000>;
|
||||
};
|
||||
|
||||
reg_usdhc1_vqmmc: regulator-wifi-vqmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "regulator-wifi-vqmmc";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
sdio_pwrseq: usdhc1-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
|
|
@ -60,6 +121,146 @@ &A53_3 {
|
|||
cpu-supply = <®_arm>;
|
||||
};
|
||||
|
||||
&eqos {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_eqos>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
snps,force_thresh_dma_mode;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_eqos_phy>;
|
||||
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <80000>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_tx_setup: tx-queues-config {
|
||||
snps,tx-queues-to-use = <5>;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
};
|
||||
|
||||
queue4 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0xf0>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_rx_setup: rx-queues-config {
|
||||
snps,rx-queues-to-use = <5>;
|
||||
snps,rx-sched-sp;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
snps,map-to-dma-channel = <0>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
snps,map-to-dma-channel = <1>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
snps,map-to-dma-channel = <2>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
snps,map-to-dma-channel = <3>;
|
||||
};
|
||||
|
||||
queue4 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0xf0>;
|
||||
snps,map-to-dma-channel = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy1>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec_phy>;
|
||||
eee-broken-1000t;
|
||||
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <80000>;
|
||||
realtek,aldps-enable;
|
||||
realtek,clkout-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_pvi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_tx {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hdmi>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
hdmi_tx_out: endpoint {
|
||||
remote-endpoint = <&hdmi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_tx_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -218,6 +419,10 @@ &i2c3 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&lcdif3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -237,6 +442,58 @@ &uart3 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy1 {
|
||||
vbus-supply = <®_usb_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3_1 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
vmmc-supply = <®_usdhc1_vmmc>;
|
||||
vqmmc-supply = <®_usdhc1_vqmmc>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-mmc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
|
|
@ -250,6 +507,74 @@ &usdhc3 {
|
|||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
pinctrl_eqos: eqosgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
|
||||
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
|
||||
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
|
||||
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
|
||||
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
|
||||
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
|
||||
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
|
||||
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
|
||||
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
|
||||
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
|
||||
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
|
||||
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
|
||||
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
|
||||
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_eqos_phy: eqosphygrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
|
||||
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
|
||||
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
|
||||
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
|
||||
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
|
||||
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
|
||||
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
|
||||
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
|
||||
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
|
||||
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
|
||||
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
|
||||
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
|
||||
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
|
||||
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec_phy: fecphygrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hdmi: hdmigrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
/* Pin might be required by multiple drivers
|
||||
* (e. g. HDMI Audio and HDMI TX)
|
||||
*/
|
||||
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
|
||||
|
|
@ -293,6 +618,12 @@ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
|
||||
|
|
@ -310,6 +641,81 @@ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
|
||||
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
|
||||
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
|
||||
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
|
||||
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
|
||||
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
|
||||
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
|
||||
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
|
||||
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user