From 959393e81cf1fe7f2a75d639b90cd7c816103f25 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Jul 2026 15:12:22 +0200 Subject: [PATCH] dt-bindings: firmware: xilinx: Add missing example for ZynqMP Document clock-controller under zynqmp-firmware in the binding example so ZynqMP DTs validate against xlnx,versal-clk.yaml (Versal example already did). Acked-by: Conor Dooley Link: https://patch.msgid.link/12dba601a8b631e565dd98e52a89b0ec18fcdce2.1783516336.git.michal.simek@amd.com Signed-off-by: Michal Simek --- .../bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml index d50438b0fca8..680082c29f01 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml @@ -132,6 +132,14 @@ examples: zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; + clock-controller { + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, + <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", + "aux_ref_clk", "gt_crx_ref_clk"; + #clock-cells = <1>; + }; soc-nvmem { compatible = "xlnx,zynqmp-nvmem-fw"; nvmem-layout {