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can: kvaser_pciefd: Use FIELD_{GET,PREP} and GENMASK where appropriate
Replace opencoded masking and shifting, with GENMASK, FIELD_GET and FIELD_PREP macros. Suggested-by: Vincent MAILHOL <mailhol.vincent@wanadoo.fr> Signed-off-by: Jimmy Assarsson <extja@kvaser.com> Reviewed-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr> Link: https://lore.kernel.org/all/20230529134248.752036-12-extja@kvaser.com Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Jimmy Assarsson
Marc Kleine-Budde
parent
69335013c4
commit
954fb21268
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@ -5,6 +5,7 @@
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* - PEAK linux canfd driver
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*/
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#include <linux/bitfield.h>
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#include <linux/can/dev.h>
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#include <linux/device.h>
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#include <linux/ethtool.h>
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@ -26,7 +27,7 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
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#define KVASER_PCIEFD_BEC_POLL_FREQ (jiffies + msecs_to_jiffies(200))
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#define KVASER_PCIEFD_MAX_ERR_REP 256U
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#define KVASER_PCIEFD_CAN_TX_MAX_COUNT 17U
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#define KVASER_PCIEFD_MAX_CAN_CHANNELS 4U
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#define KVASER_PCIEFD_MAX_CAN_CHANNELS 4UL
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#define KVASER_PCIEFD_DMA_COUNT 2U
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#define KVASER_PCIEFD_DMA_SIZE (4U * 1024U)
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@ -79,15 +80,16 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
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/* PCI interrupt fields */
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#define KVASER_PCIEFD_IRQ_SRB BIT(4)
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#define KVASER_PCIEFD_IRQ_ALL_MSK 0x1f
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#define KVASER_PCIEFD_IRQ_ALL_MASK GENMASK(4, 0)
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/* Enable 64-bit DMA address translation */
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#define KVASER_PCIEFD_64BIT_DMA_BIT BIT(0)
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/* System build information fields */
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#define KVASER_PCIEFD_SYSID_NRCHAN_SHIFT 24
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#define KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT 16
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#define KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT 1
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#define KVASER_PCIEFD_SYSID_VERSION_NR_CHAN_MASK GENMASK(31, 24)
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#define KVASER_PCIEFD_SYSID_VERSION_MAJOR_MASK GENMASK(23, 16)
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#define KVASER_PCIEFD_SYSID_VERSION_MINOR_MASK GENMASK(7, 0)
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#define KVASER_PCIEFD_SYSID_BUILD_SEQ_MASK GENMASK(15, 1)
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/* Reset DMA buffer 0, 1 and FIFO offset */
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#define KVASER_PCIEFD_SRB_CMD_RDB1 BIT(5)
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@ -110,17 +112,18 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
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#define KVASER_PCIEFD_SRB_STAT_DI BIT(15)
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/* SRB current packet level */
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#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK 0xff
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#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK GENMASK(7, 0)
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/* DMA Enable */
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#define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0)
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/* KCAN CTRL packet types */
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#define KVASER_PCIEFD_KCAN_CTRL_EFLUSH (4 << 29)
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#define KVASER_PCIEFD_KCAN_CTRL_EFRAME (5 << 29)
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#define KVASER_PCIEFD_KCAN_CTRL_TYPE_MASK GENMASK(31, 29)
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#define KVASER_PCIEFD_KCAN_CTRL_TYPE_EFLUSH 0x4
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#define KVASER_PCIEFD_KCAN_CTRL_TYPE_EFRAME 0x5
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/* Command sequence number */
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#define KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT 16
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#define KVASER_PCIEFD_KCAN_CMD_SEQ_MASK GENMASK(23, 16)
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/* Abort, flush and reset */
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#define KVASER_PCIEFD_KCAN_CMD_AT BIT(1)
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/* Request status packet */
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@ -148,10 +151,12 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
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#define KVASER_PCIEFD_KCAN_IRQ_TAR BIT(0)
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/* Tx FIFO size */
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#define KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT 16
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#define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_MAX_MASK GENMASK(23, 16)
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/* Tx FIFO current packet level */
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#define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK GENMASK(7, 0)
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/* Current status packet sequence number */
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#define KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT 24
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#define KVASER_PCIEFD_KCAN_STAT_SEQNO_MASK GENMASK(31, 24)
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/* Controller got CAN FD capability */
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#define KVASER_PCIEFD_KCAN_STAT_FD BIT(19)
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/* Controller got one-shot capability */
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@ -187,12 +192,14 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
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#define KVASER_PCIEFD_KCAN_MODE_RM BIT(8)
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/* BTRN and BTRD fields */
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#define KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT 26
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#define KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT 17
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#define KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT 13
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#define KVASER_PCIEFD_KCAN_BTRN_TSEG2_MASK GENMASK(30, 26)
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#define KVASER_PCIEFD_KCAN_BTRN_TSEG1_MASK GENMASK(25, 17)
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#define KVASER_PCIEFD_KCAN_BTRN_SJW_MASK GENMASK(16, 13)
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#define KVASER_PCIEFD_KCAN_BTRN_BRP_MASK GENMASK(12, 0)
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/* PWM Control fields */
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#define KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT 16
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#define KVASER_PCIEFD_KCAN_PWM_TOP_MASK GENMASK(23, 16)
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#define KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK GENMASK(7, 0)
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/* KCAN packet type IDs */
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#define KVASER_PCIEFD_PACK_TYPE_DATA 0
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@ -206,13 +213,14 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
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#define KVASER_PCIEFD_PACK_TYPE_BUS_LOAD 9
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/* Common KCAN packet definitions, second word */
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#define KVASER_PCIEFD_PACKET_TYPE_SHIFT 28
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#define KVASER_PCIEFD_PACKET_CHID_SHIFT 25
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#define KVASER_PCIEFD_PACKET_SEQ_MSK 0xff
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#define KVASER_PCIEFD_PACKET_TYPE_MASK GENMASK(31, 28)
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#define KVASER_PCIEFD_PACKET_CHID_MASK GENMASK(27, 25)
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#define KVASER_PCIEFD_PACKET_SEQ_MASK GENMASK(7, 0)
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/* KCAN Transmit/Receive data packet, first word */
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#define KVASER_PCIEFD_RPACKET_IDE BIT(30)
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#define KVASER_PCIEFD_RPACKET_RTR BIT(29)
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#define KVASER_PCIEFD_RPACKET_ID_MASK GENMASK(28, 0)
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/* KCAN Transmit data packet, second word */
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#define KVASER_PCIEFD_TPACKET_AREQ BIT(31)
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#define KVASER_PCIEFD_TPACKET_SMS BIT(16)
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@ -220,7 +228,7 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
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#define KVASER_PCIEFD_RPACKET_FDF BIT(15)
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#define KVASER_PCIEFD_RPACKET_BRS BIT(14)
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#define KVASER_PCIEFD_RPACKET_ESI BIT(13)
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#define KVASER_PCIEFD_RPACKET_DLC_SHIFT 8
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#define KVASER_PCIEFD_RPACKET_DLC_MASK GENMASK(11, 8)
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/* KCAN Transmit acknowledge packet, first word */
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#define KVASER_PCIEFD_APACKET_NACK BIT(11)
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@ -233,7 +241,8 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
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#define KVASER_PCIEFD_SPACK_IRM BIT(21)
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#define KVASER_PCIEFD_SPACK_IDET BIT(20)
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#define KVASER_PCIEFD_SPACK_BOFF BIT(16)
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#define KVASER_PCIEFD_SPACK_RXERR_SHIFT 8
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#define KVASER_PCIEFD_SPACK_RXERR_MASK GENMASK(15, 8)
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#define KVASER_PCIEFD_SPACK_TXERR_MASK GENMASK(7, 0)
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/* KCAN Status packet, second word */
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#define KVASER_PCIEFD_SPACK_EPLR BIT(24)
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#define KVASER_PCIEFD_SPACK_EWLR BIT(23)
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@ -318,7 +327,7 @@ static void kvaser_pciefd_request_status(struct kvaser_pciefd_can *can)
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u32 cmd;
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cmd = KVASER_PCIEFD_KCAN_CMD_SRQ;
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cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
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cmd |= FIELD_PREP(KVASER_PCIEFD_KCAN_CMD_SEQ_MASK, ++can->cmd_seq);
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iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
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}
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@ -418,7 +427,7 @@ static void kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can *can)
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/* If controller is already idle, run abort, flush and reset */
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cmd = KVASER_PCIEFD_KCAN_CMD_AT;
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cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
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cmd |= FIELD_PREP(KVASER_PCIEFD_KCAN_CMD_SEQ_MASK, ++can->cmd_seq);
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iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
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} else if (!(status & KVASER_PCIEFD_KCAN_STAT_RMR)) {
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u32 mode;
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@ -489,10 +498,10 @@ static void kvaser_pciefd_pwm_stop(struct kvaser_pciefd_can *can)
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spin_lock_irqsave(&can->lock, irq);
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pwm_ctrl = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
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top = (pwm_ctrl >> KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT) & 0xff;
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top = FIELD_GET(KVASER_PCIEFD_KCAN_PWM_TOP_MASK, pwm_ctrl);
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/* Set duty cycle to zero */
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pwm_ctrl |= top;
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pwm_ctrl |= FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK, top);
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iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
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spin_unlock_irqrestore(&can->lock, irq);
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}
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@ -509,14 +518,14 @@ static void kvaser_pciefd_pwm_start(struct kvaser_pciefd_can *can)
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/* Set frequency to 500 KHz*/
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top = can->kv_pcie->bus_freq / (2 * 500000) - 1;
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pwm_ctrl = top & 0xff;
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pwm_ctrl |= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT;
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pwm_ctrl = FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK, top);
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pwm_ctrl |= FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TOP_MASK, top);
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iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
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/* Set duty cycle to 95 */
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trigger = (100 * top - 95 * (top + 1) + 50) / 100;
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pwm_ctrl = trigger & 0xff;
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pwm_ctrl |= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT;
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pwm_ctrl = FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK, trigger);
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pwm_ctrl |= FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TOP_MASK, top);
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iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
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spin_unlock_irqrestore(&can->lock, irq);
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}
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@ -581,8 +590,8 @@ static int kvaser_pciefd_prepare_tx_packet(struct kvaser_pciefd_tx_packet *p,
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if (cf->can_id & CAN_EFF_FLAG)
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p->header[0] |= KVASER_PCIEFD_RPACKET_IDE;
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p->header[0] |= cf->can_id & CAN_EFF_MASK;
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p->header[1] |= can_fd_len2dlc(cf->len) << KVASER_PCIEFD_RPACKET_DLC_SHIFT;
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p->header[0] |= FIELD_PREP(KVASER_PCIEFD_RPACKET_ID_MASK, cf->can_id);
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p->header[1] |= FIELD_PREP(KVASER_PCIEFD_RPACKET_DLC_MASK, can_fd_len2dlc(cf->len));
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p->header[1] |= KVASER_PCIEFD_TPACKET_AREQ;
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if (can_is_canfd_skb(skb)) {
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@ -593,7 +602,7 @@ static int kvaser_pciefd_prepare_tx_packet(struct kvaser_pciefd_tx_packet *p,
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p->header[1] |= KVASER_PCIEFD_RPACKET_ESI;
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}
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p->header[1] |= seq & KVASER_PCIEFD_PACKET_SEQ_MSK;
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p->header[1] |= FIELD_PREP(KVASER_PCIEFD_PACKET_SEQ_MASK, seq);
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packet_size = cf->len;
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memcpy(p->data, cf->data, packet_size);
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@ -645,7 +654,8 @@ static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb,
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KVASER_PCIEFD_KCAN_FIFO_LAST_REG);
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}
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count = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NPACKETS_REG);
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count = FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK,
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ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NPACKETS_REG));
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/* No room for a new message, stop the queue until at least one
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* successful transmit
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*/
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@ -670,12 +680,10 @@ static int kvaser_pciefd_set_bittiming(struct kvaser_pciefd_can *can, bool data)
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else
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bt = &can->can.bittiming;
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btrn = ((bt->phase_seg2 - 1) & 0x1f) <<
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KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT |
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(((bt->prop_seg + bt->phase_seg1) - 1) & 0x1ff) <<
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KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT |
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((bt->sjw - 1) & 0xf) << KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT |
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((bt->brp - 1) & 0x1fff);
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btrn = FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_TSEG2_MASK, bt->phase_seg2 - 1) |
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FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_TSEG1_MASK, bt->prop_seg + bt->phase_seg1 - 1) |
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FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_SJW_MASK, bt->sjw - 1) |
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FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_BRP_MASK, bt->brp - 1);
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spin_lock_irqsave(&can->lock, irq_flags);
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mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
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@ -771,7 +779,7 @@ static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie)
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for (i = 0; i < pcie->nr_channels; i++) {
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struct net_device *netdev;
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struct kvaser_pciefd_can *can;
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u32 status, tx_npackets;
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u32 status, tx_nr_packets_max;
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netdev = alloc_candev(sizeof(struct kvaser_pciefd_can),
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KVASER_PCIEFD_CAN_TX_MAX_COUNT);
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@ -798,10 +806,10 @@ static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie)
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/* Disable Bus load reporting */
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iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_BUS_LOAD_REG);
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tx_npackets = ioread32(can->reg_base +
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KVASER_PCIEFD_KCAN_TX_NPACKETS_REG);
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if (((tx_npackets >> KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT) &
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0xff) < KVASER_PCIEFD_CAN_TX_MAX_COUNT) {
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tx_nr_packets_max =
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FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_MAX_MASK,
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ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NPACKETS_REG));
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if (tx_nr_packets_max < KVASER_PCIEFD_CAN_TX_MAX_COUNT) {
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dev_err(&pcie->pci->dev,
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"Max Tx count is smaller than expected\n");
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@ -924,8 +932,9 @@ static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie)
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pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
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/* Empty Rx FIFO */
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srb_packet_count = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG) &
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KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK;
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srb_packet_count =
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FIELD_GET(KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK,
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ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG));
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while (srb_packet_count) {
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/* Drop current packet in FIFO */
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ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_FIFO_LAST_REG);
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@ -947,17 +956,17 @@ static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie)
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static int kvaser_pciefd_setup_board(struct kvaser_pciefd *pcie)
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{
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u32 sysid, srb_status, build;
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u32 version, srb_status, build;
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sysid = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_VERSION_REG);
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version = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_VERSION_REG);
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pcie->nr_channels = min(KVASER_PCIEFD_MAX_CAN_CHANNELS,
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((sysid >> KVASER_PCIEFD_SYSID_NRCHAN_SHIFT) & 0xff));
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FIELD_GET(KVASER_PCIEFD_SYSID_VERSION_NR_CHAN_MASK, version));
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build = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_BUILD_REG);
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dev_dbg(&pcie->pci->dev, "Version %u.%u.%u\n",
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(sysid >> KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT) & 0xff,
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sysid & 0xff,
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(build >> KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT) & 0x7fff);
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dev_dbg(&pcie->pci->dev, "Version %lu.%lu.%lu\n",
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FIELD_GET(KVASER_PCIEFD_SYSID_VERSION_MAJOR_MASK, version),
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FIELD_GET(KVASER_PCIEFD_SYSID_VERSION_MINOR_MASK, version),
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FIELD_GET(KVASER_PCIEFD_SYSID_BUILD_SEQ_MASK, build));
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srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG);
|
||||
if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DMA)) {
|
||||
|
|
@ -986,7 +995,7 @@ static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie,
|
|||
struct canfd_frame *cf;
|
||||
struct can_priv *priv;
|
||||
struct net_device_stats *stats;
|
||||
u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
|
||||
u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
|
||||
|
||||
if (ch_id >= pcie->nr_channels)
|
||||
return -EIO;
|
||||
|
|
@ -1014,11 +1023,11 @@ static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie,
|
|||
}
|
||||
}
|
||||
|
||||
cf->can_id = p->header[0] & CAN_EFF_MASK;
|
||||
cf->can_id = FIELD_GET(KVASER_PCIEFD_RPACKET_ID_MASK, p->header[0]);
|
||||
if (p->header[0] & KVASER_PCIEFD_RPACKET_IDE)
|
||||
cf->can_id |= CAN_EFF_FLAG;
|
||||
|
||||
cf->len = can_fd_dlc2len(p->header[1] >> KVASER_PCIEFD_RPACKET_DLC_SHIFT);
|
||||
cf->len = can_fd_dlc2len(FIELD_GET(KVASER_PCIEFD_RPACKET_DLC_MASK, p->header[1]));
|
||||
|
||||
if (p->header[0] & KVASER_PCIEFD_RPACKET_RTR) {
|
||||
cf->can_id |= CAN_RTR_FLAG;
|
||||
|
|
@ -1095,8 +1104,8 @@ static int kvaser_pciefd_rx_error_frame(struct kvaser_pciefd_can *can,
|
|||
|
||||
old_state = can->can.state;
|
||||
|
||||
bec.txerr = p->header[0] & 0xff;
|
||||
bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff;
|
||||
bec.txerr = FIELD_GET(KVASER_PCIEFD_SPACK_TXERR_MASK, p->header[0]);
|
||||
bec.rxerr = FIELD_GET(KVASER_PCIEFD_SPACK_RXERR_MASK, p->header[0]);
|
||||
|
||||
kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state,
|
||||
&rx_state);
|
||||
|
|
@ -1145,7 +1154,7 @@ static int kvaser_pciefd_handle_error_packet(struct kvaser_pciefd *pcie,
|
|||
struct kvaser_pciefd_rx_packet *p)
|
||||
{
|
||||
struct kvaser_pciefd_can *can;
|
||||
u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
|
||||
u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
|
||||
|
||||
if (ch_id >= pcie->nr_channels)
|
||||
return -EIO;
|
||||
|
|
@ -1169,8 +1178,8 @@ static int kvaser_pciefd_handle_status_resp(struct kvaser_pciefd_can *can,
|
|||
|
||||
old_state = can->can.state;
|
||||
|
||||
bec.txerr = p->header[0] & 0xff;
|
||||
bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff;
|
||||
bec.txerr = FIELD_GET(KVASER_PCIEFD_SPACK_TXERR_MASK, p->header[0]);
|
||||
bec.rxerr = FIELD_GET(KVASER_PCIEFD_SPACK_RXERR_MASK, p->header[0]);
|
||||
|
||||
kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state,
|
||||
&rx_state);
|
||||
|
|
@ -1220,7 +1229,7 @@ static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie,
|
|||
struct kvaser_pciefd_can *can;
|
||||
u8 cmdseq;
|
||||
u32 status;
|
||||
u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
|
||||
u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
|
||||
|
||||
if (ch_id >= pcie->nr_channels)
|
||||
return -EIO;
|
||||
|
|
@ -1228,34 +1237,35 @@ static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie,
|
|||
can = pcie->can[ch_id];
|
||||
|
||||
status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
|
||||
cmdseq = (status >> KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT) & 0xff;
|
||||
cmdseq = FIELD_GET(KVASER_PCIEFD_KCAN_STAT_SEQNO_MASK, status);
|
||||
|
||||
/* Reset done, start abort and flush */
|
||||
if (p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
|
||||
p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&
|
||||
p->header[1] & KVASER_PCIEFD_SPACK_AUTO &&
|
||||
cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) &&
|
||||
cmdseq == FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[1]) &&
|
||||
status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
|
||||
u32 cmd;
|
||||
|
||||
iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
|
||||
can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
|
||||
cmd = KVASER_PCIEFD_KCAN_CMD_AT;
|
||||
cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
|
||||
cmd |= FIELD_PREP(KVASER_PCIEFD_KCAN_CMD_SEQ_MASK, ++can->cmd_seq);
|
||||
iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
|
||||
} else if (p->header[0] & KVASER_PCIEFD_SPACK_IDET &&
|
||||
p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
|
||||
cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) &&
|
||||
cmdseq == FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[1]) &&
|
||||
status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
|
||||
/* Reset detected, send end of flush if no packet are in FIFO */
|
||||
u8 count = ioread32(can->reg_base +
|
||||
KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
|
||||
u8 count = FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK,
|
||||
ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NPACKETS_REG));
|
||||
|
||||
if (!count)
|
||||
iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH,
|
||||
iowrite32(FIELD_PREP(KVASER_PCIEFD_KCAN_CTRL_TYPE_MASK,
|
||||
KVASER_PCIEFD_KCAN_CTRL_TYPE_EFLUSH),
|
||||
can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
|
||||
} else if (!(p->header[1] & KVASER_PCIEFD_SPACK_AUTO) &&
|
||||
cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK)) {
|
||||
cmdseq == FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[1])) {
|
||||
/* Response to status request received */
|
||||
kvaser_pciefd_handle_status_resp(can, p);
|
||||
if (can->can.state != CAN_STATE_BUS_OFF &&
|
||||
|
|
@ -1306,7 +1316,7 @@ static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie,
|
|||
{
|
||||
struct kvaser_pciefd_can *can;
|
||||
bool one_shot_fail = false;
|
||||
u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
|
||||
u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
|
||||
|
||||
if (ch_id >= pcie->nr_channels)
|
||||
return -EIO;
|
||||
|
|
@ -1324,7 +1334,7 @@ static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie,
|
|||
if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) {
|
||||
netdev_dbg(can->can.dev, "Packet was flushed\n");
|
||||
} else {
|
||||
int echo_idx = p->header[0] & KVASER_PCIEFD_PACKET_SEQ_MSK;
|
||||
int echo_idx = FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[0]);
|
||||
int dlc;
|
||||
u8 count;
|
||||
struct sk_buff *skb;
|
||||
|
|
@ -1333,8 +1343,8 @@ static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie,
|
|||
if (skb)
|
||||
kvaser_pciefd_set_skb_timestamp(pcie, skb, p->timestamp);
|
||||
dlc = can_get_echo_skb(can->can.dev, echo_idx, NULL);
|
||||
count = ioread32(can->reg_base +
|
||||
KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
|
||||
count = FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK,
|
||||
ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NPACKETS_REG));
|
||||
|
||||
if (count < KVASER_PCIEFD_CAN_TX_MAX_COUNT &&
|
||||
netif_queue_stopped(can->can.dev))
|
||||
|
|
@ -1355,7 +1365,7 @@ static int kvaser_pciefd_handle_eflush_packet(struct kvaser_pciefd *pcie,
|
|||
struct kvaser_pciefd_rx_packet *p)
|
||||
{
|
||||
struct kvaser_pciefd_can *can;
|
||||
u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
|
||||
u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
|
||||
|
||||
if (ch_id >= pcie->nr_channels)
|
||||
return -EIO;
|
||||
|
|
@ -1394,15 +1404,15 @@ static int kvaser_pciefd_read_packet(struct kvaser_pciefd *pcie, int *start_pos,
|
|||
pos += 2;
|
||||
p->timestamp = le64_to_cpu(timestamp);
|
||||
|
||||
type = (p->header[1] >> KVASER_PCIEFD_PACKET_TYPE_SHIFT) & 0xf;
|
||||
type = FIELD_GET(KVASER_PCIEFD_PACKET_TYPE_MASK, p->header[1]);
|
||||
switch (type) {
|
||||
case KVASER_PCIEFD_PACK_TYPE_DATA:
|
||||
ret = kvaser_pciefd_handle_data_packet(pcie, p, &buffer[pos]);
|
||||
if (!(p->header[0] & KVASER_PCIEFD_RPACKET_RTR)) {
|
||||
u8 data_len;
|
||||
|
||||
data_len = can_fd_dlc2len(p->header[1] >>
|
||||
KVASER_PCIEFD_RPACKET_DLC_SHIFT);
|
||||
data_len = can_fd_dlc2len(FIELD_GET(KVASER_PCIEFD_RPACKET_DLC_MASK,
|
||||
p->header[1]));
|
||||
pos += DIV_ROUND_UP(data_len, 4);
|
||||
}
|
||||
break;
|
||||
|
|
@ -1520,7 +1530,7 @@ static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev)
|
|||
|
||||
board_irq = ioread32(pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
|
||||
|
||||
if (!(board_irq & KVASER_PCIEFD_IRQ_ALL_MSK))
|
||||
if (!(board_irq & KVASER_PCIEFD_IRQ_ALL_MASK))
|
||||
return IRQ_NONE;
|
||||
|
||||
if (board_irq & KVASER_PCIEFD_IRQ_SRB)
|
||||
|
|
@ -1612,7 +1622,7 @@ static int kvaser_pciefd_probe(struct pci_dev *pdev,
|
|||
pcie->reg_base + KVASER_PCIEFD_SRB_IEN_REG);
|
||||
|
||||
/* Enable PCI interrupts */
|
||||
iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK,
|
||||
iowrite32(KVASER_PCIEFD_IRQ_ALL_MASK,
|
||||
pcie->reg_base + KVASER_PCIEFD_IEN_REG);
|
||||
|
||||
/* Ready the DMA buffers */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user