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drm/i915/rps: refactor display rps support

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Make the gt rps code and display irq code interact via
intel_display_rps.[ch], instead of direct access. Add no-op static
inline stubs for xe instead of having a separate build unit doing
nothing. All of this clarifies the interfaces between i915 core and
display.

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/ef2a46dc8f30b72282494f54e98cb5fed7523b58.1746536745.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2025-05-06 16:06:49 +03:00
parent 7a3bf08ae9
commit 9536d60202
7 changed files with 56 additions and 39 deletions
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5
drivers/gpu/drm/i915/display/intel_display_irq.c
View File

@ -5,7 +5,6 @@
#include <drm/drm_vblank.h>
#include "gt/intel_rps.h"
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
@ -15,6 +14,7 @@
#include "intel_de.h"
#include "intel_display_irq.h"
#include "intel_display_rpm.h"
#include "intel_display_rps.h"
#include "intel_display_trace.h"
#include "intel_display_types.h"
#include "intel_dmc_wl.h"
@ -876,7 +876,6 @@ static void ilk_gtt_fault_irq_handler(struct intel_display *display)
void ilk_display_irq_handler(struct intel_display *display, u32 de_iir)
{
struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm);
enum pipe pipe;
u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
@ -923,7 +922,7 @@ void ilk_display_irq_handler(struct intel_display *display, u32 de_iir)
}
if (DISPLAY_VER(display) == 5 && de_iir & DE_PCU_EVENT)
gen5_rps_irq_handler(&to_gt(dev_priv)->rps);
ilk_display_rps_irq_handler(display);
}
void ivb_display_irq_handler(struct intel_display *display, u32 de_iir)

27
drivers/gpu/drm/i915/display/intel_display_rps.c
View File

@ -8,6 +8,8 @@
#include "gt/intel_rps.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_display_irq.h"
#include "intel_display_rps.h"
#include "intel_display_types.h"
@ -81,3 +83,28 @@ void intel_display_rps_mark_interactive(struct intel_display *display,
intel_rps_mark_interactive(&to_gt(i915)->rps, interactive);
state->rps_interactive = interactive;
}
void ilk_display_rps_enable(struct intel_display *display)
{
struct drm_i915_private *i915 = to_i915(display->drm);
spin_lock(&i915->irq_lock);
ilk_enable_display_irq(display, DE_PCU_EVENT);
spin_unlock(&i915->irq_lock);
}
void ilk_display_rps_disable(struct intel_display *display)
{
struct drm_i915_private *i915 = to_i915(display->drm);
spin_lock(&i915->irq_lock);
ilk_disable_display_irq(display, DE_PCU_EVENT);
spin_unlock(&i915->irq_lock);
}
void ilk_display_rps_irq_handler(struct intel_display *display)
{
struct drm_i915_private *i915 = to_i915(display->drm);
gen5_rps_irq_handler(&to_gt(i915)->rps);
}

24
drivers/gpu/drm/i915/display/intel_display_rps.h
View File

@ -13,10 +13,34 @@ struct drm_crtc;
struct intel_atomic_state;
struct intel_display;
#ifdef I915
void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc,
struct dma_fence *fence);
void intel_display_rps_mark_interactive(struct intel_display *display,
struct intel_atomic_state *state,
bool interactive);
void ilk_display_rps_enable(struct intel_display *display);
void ilk_display_rps_disable(struct intel_display *display);
void ilk_display_rps_irq_handler(struct intel_display *display);
#else
static inline void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc,
struct dma_fence *fence)
{
}
static inline void intel_display_rps_mark_interactive(struct intel_display *display,
struct intel_atomic_state *state,
bool interactive)
{
}
static inline void ilk_display_rps_enable(struct intel_display *display)
{
}
static inline void ilk_display_rps_disable(struct intel_display *display)
{
}
static inline void ilk_display_rps_irq_handler(struct intel_display *display)
{
}
#endif
#endif /* __INTEL_DISPLAY_RPS_H__ */

10
drivers/gpu/drm/i915/gt/intel_rps.c
View File

@ -8,7 +8,7 @@
#include <drm/intel/i915_drm.h>
#include "display/intel_display.h"
#include "display/intel_display_irq.h"
#include "display/intel_display_rps.h"
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
@ -608,9 +608,7 @@ static bool gen5_rps_enable(struct intel_rps *rps)
rps->ips.last_count2 = intel_uncore_read(uncore, GFXEC);
rps->ips.last_time2 = ktime_get_raw_ns();
spin_lock(&i915->irq_lock);
ilk_enable_display_irq(display, DE_PCU_EVENT);
spin_unlock(&i915->irq_lock);
ilk_display_rps_enable(display);
spin_unlock_irq(&mchdev_lock);
@ -628,9 +626,7 @@ static void gen5_rps_disable(struct intel_rps *rps)
spin_lock_irq(&mchdev_lock);
spin_lock(&i915->irq_lock);
ilk_disable_display_irq(display, DE_PCU_EVENT);
spin_unlock(&i915->irq_lock);
ilk_display_rps_disable(display);
rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);

1
drivers/gpu/drm/xe/Makefile
View File

@ -182,7 +182,6 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
display/xe_display.o \
display/xe_display_misc.o \
display/xe_display_rpm.o \
display/xe_display_rps.o \
display/xe_display_wa.o \
display/xe_dsb_buffer.o \
display/xe_fb_pin.o \

11
drivers/gpu/drm/xe/compat-i915-headers/gt/intel_rps.h
View File

@ -1,11 +0,0 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2023 Intel Corporation
*/
#ifndef __INTEL_RPS_H__
#define __INTEL_RPS_H__
#define gen5_rps_irq_handler(x) ({})
#endif /* __INTEL_RPS_H__ */

17
drivers/gpu/drm/xe/display/xe_display_rps.c
View File

@ -1,17 +0,0 @@
// SPDX-License-Identifier: MIT
/*
* Copyright © 2023 Intel Corporation
*/
#include "intel_display_rps.h"
void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc,
struct dma_fence *fence)
{
}
void intel_display_rps_mark_interactive(struct intel_display *display,
struct intel_atomic_state *state,
bool interactive)
{
}