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drm/amd/display: Add ASIC cap to limit DCC surface width

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[Why]
Certain configurations of DCN401 require ODM4:1 to support DCC for 10K
surfaces. DCC should be conservatively disabled in those cases.

The issue is that current logic limits 10K surface DCC for all
configurations of DCN401.

[How]
Add DC ASIC cap to indicate max surface width that can support DCC.
Disable DCC if this ASIC cap is non-zero and surface width exceeds it.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
George Shen 2024-06-17 16:32:15 -04:00 committed by Alex Deucher
parent 02b438afc6
commit 95134e5852
3 changed files with 11 additions and 0 deletions
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2
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -293,6 +293,8 @@ struct dc_caps {
bool cursor_not_scaled;
bool dcmode_power_limits_present;
bool sequential_ono;
/* Conservative limit for DCC cases which require ODM4:1 to support*/
uint32_t dcc_plane_width_limit;
};
struct dc_bug_wa {

6
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
View File

@ -829,6 +829,7 @@ bool hubbub401_get_dcc_compression_cap(struct hubbub *hubbub,
struct dc_surface_dcc_cap *output)
{
struct dc *dc = hubbub->ctx->dc;
const unsigned int max_dcc_plane_width = dc->caps.dcc_plane_width_limit;
/* DCN4_Programming_Guide_DCHUB.docx, Section 5.11.2.2 */
enum dcc_control dcc_control;
unsigned int plane0_bpe, plane1_bpe;
@ -843,6 +844,11 @@ bool hubbub401_get_dcc_compression_cap(struct hubbub *hubbub,
if (dc->debug.disable_dcc == DCC_DISABLE)
return false;
/* Conservatively disable DCC for cases where ODM4:1 may be required. */
if (max_dcc_plane_width != 0 &&
(input->surface_size.width > max_dcc_plane_width || input->plane1_size.width > max_dcc_plane_width))
return false;
switch (input->format) {
default:
is_dual_plane = false;

3
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
View File

@ -1822,6 +1822,9 @@ static bool dcn401_resource_construct(
dc->caps.extended_aux_timeout_support = true;
dc->caps.dmcub_support = true;
if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev))
dc->caps.dcc_plane_width_limit = 7680;
/* Color pipeline capabilities */
dc->caps.color.dpp.dcn_arch = 1;
dc->caps.color.dpp.input_lut_shared = 0;