dt-bindings: media: Correct camss supply description

Usually, the supply is around 1.2 V, not 1.8 V, and also correct wording.

Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
This commit is contained in:
David Heidelberg 2025-12-22 15:16:05 +01:00 committed by Hans Verkuil
parent 555e882051
commit 94d14ac1f2
8 changed files with 16 additions and 16 deletions

View File

@ -126,11 +126,11 @@ properties:
vdda-phy-supply:
description:
Phandle to a regulator supply to PHY core block.
0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
Phandle to 1.8V regulator supply to PHY refclk pll block.
1.2V supply to CSIPHY IP blocks.
ports:
$ref: /schemas/graph.yaml#/properties/ports

View File

@ -125,11 +125,11 @@ properties:
vdda-phy-supply:
description:
Phandle to a regulator supply to PHY core block.
0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
Phandle to 1.8V regulator supply to PHY refclk pll block.
1.2V supply to CSIPHY IP blocks.
ports:
$ref: /schemas/graph.yaml#/properties/ports

View File

@ -264,11 +264,11 @@ properties:
vdda-phy-supply:
description:
Phandle to a regulator supply to PHY core block.
0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
Phandle to 1.8V regulator supply to PHY refclk pll block.
1.2V supply to CSIPHY IP blocks.
required:
- clock-names

View File

@ -91,11 +91,11 @@ properties:
vdda-phy-supply:
description:
Phandle to a regulator supply to PHY core block.
0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
Phandle to 1.8V regulator supply to PHY refclk pll block.
1.2V supply to CSIPHY IP blocks.
ports:
$ref: /schemas/graph.yaml#/properties/ports

View File

@ -207,11 +207,11 @@ properties:
vdda-phy-supply:
description:
Phandle to a regulator supply to PHY core block.
0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
Phandle to 1.8V regulator supply to PHY refclk pll block.
1.2V supply to CSIPHY IP blocks.
required:
- clock-names

View File

@ -296,11 +296,11 @@ properties:
vdda-phy-supply:
description:
Phandle to a regulator supply to PHY core block.
0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
Phandle to 1.8V regulator supply to PHY refclk pll block.
1.2V supply to CSIPHY IP blocks.
required:
- clock-names

View File

@ -134,11 +134,11 @@ properties:
vdda-phy-supply:
description:
Phandle to a regulator supply to PHY core block.
0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
Phandle to 1.2V regulator supply to PHY refclk pll block.
1.2V supply to CSIPHY IP blocks.
ports:
$ref: /schemas/graph.yaml#/properties/ports

View File

@ -120,11 +120,11 @@ properties:
vdd-csiphy-0p8-supply:
description:
Phandle to a 0.8V regulator supply to a PHY.
0.8V supply to a PHY.
vdd-csiphy-1p2-supply:
description:
Phandle to 1.2V regulator supply to a PHY.
1.2V supply to a PHY.
ports:
$ref: /schemas/graph.yaml#/properties/ports