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drm/i915/dmc: Enable PIPEDMC_ERROR interrupt on display version 30+

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Enable PIPEDMC_ERROR alongside the existing PIPEDMC_GTT_FAULT and
PIPEDMC_ATS_FAULT interrupt bits for display version 30+.

On PTL, DC state transitions do not trigger the spurious PIPEDMC_ERROR
interrupts that were previously a concern. Enable the interrupt so pipe
DMC errors are reported by intel_pipedmc_irq_handler().

v2:
- Remove IGT reference from commit message (Suraj).

Bspec: 70296
Suggested-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260708090712.3800170-1-dibin.moolakadan.subrahmanian@intel.com
This commit is contained in:
Dibin Moolakadan Subrahmanian 2026-07-08 14:37:12 +05:30 committed by Suraj Kandpal
parent f7768b46b9
commit 94896bc5fb
1 changed files with 6 additions and 4 deletions
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10
drivers/gpu/drm/i915/display/intel_dmc.c
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@ -505,14 +505,16 @@ static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
static u32 pipedmc_interrupt_mask(struct intel_display *display)
{
/*
* TODO: Check if PIPEDMC_ERROR bit enabling causes errors
* on PTL, enable it if validation passes
*/
if (DISPLAY_VER(display) >= 35)
return PIPEDMC_FLIPQ_PROG_DONE |
PIPEDMC_ERROR;
if (DISPLAY_VER(display) >= 30)
return PIPEDMC_FLIPQ_PROG_DONE |
PIPEDMC_GTT_FAULT |
PIPEDMC_ATS_FAULT |
PIPEDMC_ERROR;
/*
* FIXME PIPEDMC_ERROR not enabled for now due to LNL pipe B
* triggering it during the first DC state transition. Figure