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ath11k: PCI changes to support WCN6750
In order to add the support for WCN6750 in ATH11K , it is required to move certain PCI definitions to the header file. As a result, add ATH11K_PCI_* prefix to these definitions. Also, change the scope of certain PCI APIs that are required to enable WCN6750 from static to global. Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1 Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com> Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com> Link: https://lore.kernel.org/r/20220328055714.6449-2-quic_mpubbise@quicinc.com
This commit is contained in:
Manikanta Pubbisetty
Kalle Valo
parent
9149a94ada
commit
948171b5f6
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: BSD-3-Clause-Clear
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/*
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* Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/module.h>
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@ -17,25 +18,10 @@
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#define ATH11K_PCI_BAR_NUM 0
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#define ATH11K_PCI_DMA_MASK 32
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#define ATH11K_PCI_IRQ_CE0_OFFSET 3
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#define ATH11K_PCI_IRQ_DP_OFFSET 14
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#define WINDOW_ENABLE_BIT 0x40000000
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#define WINDOW_REG_ADDRESS 0x310c
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#define WINDOW_VALUE_MASK GENMASK(24, 19)
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#define WINDOW_START 0x80000
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#define WINDOW_RANGE_MASK GENMASK(18, 0)
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#define TCSR_SOC_HW_VERSION 0x0224
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#define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
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#define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
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/* BAR0 + 4k is always accessible, and no
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* need to force wakeup.
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* 4K - 32 = 0xFE0
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*/
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#define ACCESS_ALWAYS_OFF 0xFE0
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#define QCA6390_DEVICE_ID 0x1101
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#define QCN9074_DEVICE_ID 0x1104
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#define WCN6855_DEVICE_ID 0x1103
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@ -147,27 +133,30 @@ static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offse
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{
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struct ath11k_base *ab = ab_pci->ab;
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u32 window = FIELD_GET(WINDOW_VALUE_MASK, offset);
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u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
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lockdep_assert_held(&ab_pci->window_lock);
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if (window != ab_pci->register_window) {
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iowrite32(WINDOW_ENABLE_BIT | window,
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ab->mem + WINDOW_REG_ADDRESS);
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ioread32(ab->mem + WINDOW_REG_ADDRESS);
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iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
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ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
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ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
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ab_pci->register_window = window;
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}
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}
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static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci)
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{
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u32 umac_window = FIELD_GET(WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET);
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u32 ce_window = FIELD_GET(WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE);
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u32 umac_window;
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u32 ce_window;
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u32 window;
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umac_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET);
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ce_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE);
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window = (umac_window << 12) | (ce_window << 6);
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iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS);
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iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
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ab_pci->ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
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}
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static inline u32 ath11k_pci_get_window_start(struct ath11k_base *ab,
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@ -176,13 +165,13 @@ static inline u32 ath11k_pci_get_window_start(struct ath11k_base *ab,
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u32 window_start;
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/* If offset lies within DP register range, use 3rd window */
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if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK)
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window_start = 3 * WINDOW_START;
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if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
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window_start = 3 * ATH11K_PCI_WINDOW_START;
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/* If offset lies within CE register range, use 2nd window */
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else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK)
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window_start = 2 * WINDOW_START;
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else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < ATH11K_PCI_WINDOW_RANGE_MASK)
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window_start = 2 * ATH11K_PCI_WINDOW_START;
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else
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window_start = WINDOW_START;
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window_start = ATH11K_PCI_WINDOW_START;
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return window_start;
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}
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@ -198,32 +187,32 @@ void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value)
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*/
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if (ab->hw_params.wakeup_mhi &&
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test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
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offset >= ACCESS_ALWAYS_OFF)
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offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
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ret = mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
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if (offset < WINDOW_START) {
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if (offset < ATH11K_PCI_WINDOW_START) {
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iowrite32(value, ab->mem + offset);
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} else {
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if (ab->bus_params.static_window_map)
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window_start = ath11k_pci_get_window_start(ab, offset);
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else
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window_start = WINDOW_START;
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window_start = ATH11K_PCI_WINDOW_START;
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if (window_start == WINDOW_START) {
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if (window_start == ATH11K_PCI_WINDOW_START) {
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spin_lock_bh(&ab_pci->window_lock);
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ath11k_pci_select_window(ab_pci, offset);
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iowrite32(value, ab->mem + window_start +
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(offset & WINDOW_RANGE_MASK));
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(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
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spin_unlock_bh(&ab_pci->window_lock);
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} else {
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iowrite32(value, ab->mem + window_start +
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(offset & WINDOW_RANGE_MASK));
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(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
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}
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}
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if (ab->hw_params.wakeup_mhi &&
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test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
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offset >= ACCESS_ALWAYS_OFF &&
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offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF &&
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!ret)
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mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
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}
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@ -239,32 +228,32 @@ u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset)
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*/
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if (ab->hw_params.wakeup_mhi &&
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test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
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offset >= ACCESS_ALWAYS_OFF)
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offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF)
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ret = mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
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if (offset < WINDOW_START) {
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if (offset < ATH11K_PCI_WINDOW_START) {
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val = ioread32(ab->mem + offset);
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} else {
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if (ab->bus_params.static_window_map)
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window_start = ath11k_pci_get_window_start(ab, offset);
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else
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window_start = WINDOW_START;
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window_start = ATH11K_PCI_WINDOW_START;
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if (window_start == WINDOW_START) {
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if (window_start == ATH11K_PCI_WINDOW_START) {
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spin_lock_bh(&ab_pci->window_lock);
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ath11k_pci_select_window(ab_pci, offset);
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val = ioread32(ab->mem + window_start +
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(offset & WINDOW_RANGE_MASK));
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(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
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spin_unlock_bh(&ab_pci->window_lock);
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} else {
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val = ioread32(ab->mem + window_start +
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(offset & WINDOW_RANGE_MASK));
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(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
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}
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}
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if (ab->hw_params.wakeup_mhi &&
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test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
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offset >= ACCESS_ALWAYS_OFF &&
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offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF &&
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!ret)
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mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
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@ -474,8 +463,8 @@ int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector)
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return pci_irq_vector(pci_dev, vector);
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}
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static void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
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u32 *msi_addr_hi)
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void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
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u32 *msi_addr_hi)
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{
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struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
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struct pci_dev *pci_dev = to_pci_dev(ab->dev);
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@ -519,8 +508,7 @@ int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ab_pci, char *user_nam
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return -EINVAL;
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}
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static void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id,
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u32 *msi_idx)
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void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx)
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{
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u32 i, msi_data_idx;
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@ -536,9 +524,9 @@ static void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id,
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*msi_idx = msi_data_idx;
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}
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static int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
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int *num_vectors, u32 *user_base_data,
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u32 *base_vector)
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int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
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int *num_vectors, u32 *user_base_data,
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u32 *base_vector)
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{
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struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
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@ -561,7 +549,7 @@ static void ath11k_pci_free_ext_irq(struct ath11k_base *ab)
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}
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}
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static void ath11k_pci_free_irq(struct ath11k_base *ab)
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void ath11k_pci_free_irq(struct ath11k_base *ab)
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{
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int i, irq_idx;
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@ -710,7 +698,7 @@ static void ath11k_pci_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp)
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enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
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}
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static void ath11k_pci_ext_irq_enable(struct ath11k_base *ab)
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void ath11k_pci_ext_irq_enable(struct ath11k_base *ab)
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{
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int i;
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@ -741,7 +729,7 @@ static void ath11k_pci_sync_ext_irqs(struct ath11k_base *ab)
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}
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}
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static void ath11k_pci_ext_irq_disable(struct ath11k_base *ab)
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void ath11k_pci_ext_irq_disable(struct ath11k_base *ab)
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{
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__ath11k_pci_ext_irq_disable(ab);
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ath11k_pci_sync_ext_irqs(ab);
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@ -854,8 +842,8 @@ static int ath11k_pci_ext_irq_config(struct ath11k_base *ab)
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return 0;
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}
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static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
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const struct cpumask *m)
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int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
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const struct cpumask *m)
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{
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if (test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
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return 0;
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@ -863,7 +851,7 @@ static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
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return irq_set_affinity_hint(ab_pci->pdev->irq, m);
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}
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static int ath11k_pci_config_irq(struct ath11k_base *ab)
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int ath11k_pci_config_irq(struct ath11k_base *ab)
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{
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struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
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struct ath11k_ce_pipe *ce_pipe;
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@ -939,7 +927,7 @@ static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab)
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&cfg->shadow_reg_v2_len);
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}
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static void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab)
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void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab)
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{
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int i;
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@ -1151,7 +1139,7 @@ static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci)
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set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags);
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}
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static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
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void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
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{
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if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
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pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
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@ -1234,20 +1222,20 @@ static void ath11k_pci_kill_tasklets(struct ath11k_base *ab)
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}
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}
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static void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab)
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void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab)
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{
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ath11k_pci_ce_irqs_disable(ab);
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ath11k_pci_sync_ce_irqs(ab);
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ath11k_pci_kill_tasklets(ab);
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}
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static void ath11k_pci_stop(struct ath11k_base *ab)
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void ath11k_pci_stop(struct ath11k_base *ab)
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{
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ath11k_pci_ce_irq_disable_sync(ab);
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ath11k_ce_cleanup_pipes(ab);
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}
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static int ath11k_pci_start(struct ath11k_base *ab)
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int ath11k_pci_start(struct ath11k_base *ab)
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{
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struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
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@ -1277,8 +1265,8 @@ static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab)
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ath11k_pci_ce_irq_disable_sync(ab);
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}
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static int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
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u8 *ul_pipe, u8 *dl_pipe)
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int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
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u8 *ul_pipe, u8 *dl_pipe)
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{
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const struct service_to_pipe *entry;
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bool ul_set = false, dl_set = false;
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: BSD-3-Clause-Clear */
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/*
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* Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _ATH11K_PCI_H
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#define _ATH11K_PCI_H
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@ -52,6 +53,21 @@
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#define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c
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#define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4
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#define ATH11K_PCI_IRQ_CE0_OFFSET 3
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#define ATH11K_PCI_IRQ_DP_OFFSET 14
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#define ATH11K_PCI_WINDOW_ENABLE_BIT 0x40000000
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#define ATH11K_PCI_WINDOW_REG_ADDRESS 0x310c
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#define ATH11K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)
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#define ATH11K_PCI_WINDOW_START 0x80000
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#define ATH11K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)
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/* BAR0 + 4k is always accessible, and no
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* need to force wakeup.
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* 4K - 32 = 0xFE0
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*/
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#define ATH11K_PCI_ACCESS_ALWAYS_OFF 0xFE0
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struct ath11k_msi_user {
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char *name;
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int num_vectors;
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@ -103,5 +119,24 @@ int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ar_pci, char *user_nam
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int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector);
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void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value);
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u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset);
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void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
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u32 *msi_addr_hi);
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void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx);
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void ath11k_pci_free_irq(struct ath11k_base *ab);
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int ath11k_pci_config_irq(struct ath11k_base *ab);
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void ath11k_pci_ext_irq_enable(struct ath11k_base *ab);
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void ath11k_pci_ext_irq_disable(struct ath11k_base *ab);
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void ath11k_pci_stop(struct ath11k_base *ab);
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int ath11k_pci_start(struct ath11k_base *ab);
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int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
|
||||
u8 *ul_pipe, u8 *dl_pipe);
|
||||
void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab);
|
||||
void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab);
|
||||
int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
|
||||
int *num_vectors, u32 *user_base_data,
|
||||
u32 *base_vector);
|
||||
void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci);
|
||||
int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
|
||||
const struct cpumask *m);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user