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drm/i915/display: move pre-HSW clock gating init to display
Move the remaining pre-HSW display clock gating programming into display. This also drops display register includes from intel_clock_gating.c. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20260428095104.818360-8-luciano.coelho@intel.com Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
Luca Coelho
parent
5c9a79d564
commit
943722d70f
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@ -6,6 +6,7 @@
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#include <drm/intel/intel_gmd_misc_regs.h>
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#include "intel_de.h"
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#include "i9xx_plane_regs.h"
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#include "intel_display.h"
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#include "intel_display_clock_gating.h"
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#include "intel_display_core.h"
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@ -176,3 +177,94 @@ void intel_display_hsw_init_clock_gating(struct intel_display *display)
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HSW_UNMASK_VBL_TO_REGS_IN_SRD);
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}
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}
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void intel_display_disable_trickle_feed(struct intel_display *display)
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{
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enum pipe pipe;
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for_each_pipe(display, pipe) {
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intel_de_rmw(display, DSPCNTR(display, pipe), 0,
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DISP_TRICKLE_FEED_DISABLE);
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intel_de_rmw(display, DSPSURF(display, pipe), 0, 0);
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intel_de_posting_read(display, DSPSURF(display, pipe));
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}
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}
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void intel_display_ilk_init_clock_gating(struct intel_display *display)
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{
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u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
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/*
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* Required for FBC
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* WaFbcDisableDpfcClockGating:ilk
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*/
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dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
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ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
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ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
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intel_de_write(display, ILK_DISPLAY_CHICKEN2,
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intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
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ILK_DPARB_GATE | ILK_VSDPFD_FULL);
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dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
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intel_de_write(display, DISP_ARB_CTL,
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intel_de_read(display, DISP_ARB_CTL) |
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DISP_FBC_WM_DIS);
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if (display->platform.ironlake && display->platform.mobile) {
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/* WaFbcAsynchFlipDisableFbcQueue:ilk */
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intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
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intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
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}
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intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
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intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
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intel_display_disable_trickle_feed(display);
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}
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void intel_display_gen6_init_clock_gating(struct intel_display *display)
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{
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u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
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intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
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intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
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intel_de_write(display, ILK_DISPLAY_CHICKEN1,
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intel_de_read(display, ILK_DISPLAY_CHICKEN1) |
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ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
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intel_de_write(display, ILK_DISPLAY_CHICKEN2,
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intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
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ILK_DPARB_GATE | ILK_VSDPFD_FULL);
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intel_de_write(display, ILK_DSPCLK_GATE_D,
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intel_de_read(display, ILK_DSPCLK_GATE_D) |
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ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
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ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
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intel_display_disable_trickle_feed(display);
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}
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void intel_display_ivb_init_clock_gating(struct intel_display *display)
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{
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intel_de_write(display, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
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intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
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}
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void intel_display_g4x_init_clock_gating(struct intel_display *display)
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{
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u32 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
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OVRUNIT_CLOCK_GATE_DISABLE |
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OVCUNIT_CLOCK_GATE_DISABLE;
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if (display->platform.gm45)
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dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
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intel_de_write(display, DSPCLK_GATE_D, dspclk_gate);
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intel_display_disable_trickle_feed(display);
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}
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void intel_display_i965gm_init_clock_gating(struct intel_display *display)
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{
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intel_de_write(display, DSPCLK_GATE_D, 0);
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}
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@ -17,5 +17,11 @@ void intel_display_bdw_clock_gating_disable_fbcq(struct intel_display *display);
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void intel_display_bdw_clock_gating_vblank_in_srd(struct intel_display *display);
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void intel_display_bdw_clock_gating_kvm_notif(struct intel_display *display);
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void intel_display_hsw_init_clock_gating(struct intel_display *display);
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void intel_display_disable_trickle_feed(struct intel_display *display);
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void intel_display_ilk_init_clock_gating(struct intel_display *display);
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void intel_display_gen6_init_clock_gating(struct intel_display *display);
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void intel_display_ivb_init_clock_gating(struct intel_display *display);
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void intel_display_g4x_init_clock_gating(struct intel_display *display);
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void intel_display_i965gm_init_clock_gating(struct intel_display *display);
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#endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
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@ -217,6 +217,34 @@
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# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
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# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
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# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
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#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
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#define ILK_FBCQ_DIS REG_BIT(22)
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#define ILK_PABSTRETCH_DIS REG_BIT(21)
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#define ILK_SABSTRETCH_DIS REG_BIT(20)
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#define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
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#define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
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#define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
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#define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
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#define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
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#define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
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#define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
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#define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
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#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
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#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
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#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
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/* Required on all Ironlake and Sandybridge according to the B-Spec. */
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#define ILK_ELPIN_409_SELECT REG_BIT(25)
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#define ILK_DPARB_GATE REG_BIT(22)
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#define ILK_VSDPFD_FULL REG_BIT(21)
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#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
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#define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28)
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#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9)
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#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8)
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#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7)
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#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5)
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/*
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* This bit must be set on the 830 to prevent hangs when turning off the
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* overlay scaler.
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@ -494,21 +494,6 @@
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#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
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#define GEN7_FF_DS_SCHED_HW (0x0 << 4)
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#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
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#define ILK_FBCQ_DIS REG_BIT(22)
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#define ILK_PABSTRETCH_DIS REG_BIT(21)
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#define ILK_SABSTRETCH_DIS REG_BIT(20)
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#define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
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#define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
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#define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
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#define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
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#define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
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#define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
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#define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
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#define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
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#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
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#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
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#define DPLL_TEST _MMIO(0x606c)
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#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
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#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
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@ -700,19 +685,6 @@
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#define DG1_MSTR_IRQ REG_BIT(31)
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#define DG1_MSTR_TILE(t) REG_BIT(t)
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#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
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/* Required on all Ironlake and Sandybridge according to the B-Spec. */
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#define ILK_ELPIN_409_SELECT REG_BIT(25)
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#define ILK_DPARB_GATE REG_BIT(22)
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#define ILK_VSDPFD_FULL REG_BIT(21)
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#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
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#define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28)
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#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9)
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#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8)
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#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7)
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#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5)
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#define IVB_CHICKEN3 _MMIO(0x4200c)
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#define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5)
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#define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2)
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@ -30,11 +30,8 @@
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#include <drm/intel/intel_gmd_misc_regs.h>
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#include <drm/intel/mchbar_regs.h>
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#include "display/i9xx_plane_regs.h"
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#include "display/intel_display.h"
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#include "display/intel_display_clock_gating.h"
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#include "display/intel_display_core.h"
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#include "display/intel_display_regs.h"
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#include "gt/intel_engine_regs.h"
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#include "gt/intel_gt.h"
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#include "gt/intel_gt_mcr.h"
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@ -68,74 +65,15 @@ static void glk_init_clock_gating(struct drm_i915_private *i915)
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intel_display_glk_init_clock_gating(i915->display);
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}
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static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
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{
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struct intel_display *display = dev_priv->display;
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enum pipe pipe;
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for_each_pipe(display, pipe) {
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intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),
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0, DISP_TRICKLE_FEED_DISABLE);
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intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe),
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0, 0);
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intel_uncore_posting_read(&dev_priv->uncore,
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DSPSURF(display, pipe));
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}
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}
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static void ilk_init_clock_gating(struct drm_i915_private *i915)
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{
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u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
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/*
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* Required for FBC
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* WaFbcDisableDpfcClockGating:ilk
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*/
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dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
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ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
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ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
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intel_uncore_write(&i915->uncore, PCH_3DCGDIS0,
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MARIUNIT_CLOCK_GATE_DISABLE |
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SVSMUNIT_CLOCK_GATE_DISABLE);
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intel_uncore_write(&i915->uncore, PCH_3DCGDIS1,
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VFMUNIT_CLOCK_GATE_DISABLE);
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/*
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* According to the spec the following bits should be set in
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* order to enable memory self-refresh
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* The bit 22/21 of 0x42004
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* The bit 5 of 0x42020
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* The bit 15 of 0x45000
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*/
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intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
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(intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
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ILK_DPARB_GATE | ILK_VSDPFD_FULL));
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dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
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intel_uncore_write(&i915->uncore, DISP_ARB_CTL,
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(intel_uncore_read(&i915->uncore, DISP_ARB_CTL) |
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DISP_FBC_WM_DIS));
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/*
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* Based on the document from hardware guys the following bits
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* should be set unconditionally in order to enable FBC.
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* The bit 22 of 0x42000
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* The bit 22 of 0x42004
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* The bit 7,8,9 of 0x42020.
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*/
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if (IS_IRONLAKE_M(i915)) {
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/* WaFbcAsynchFlipDisableFbcQueue:ilk */
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intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
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intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
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}
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intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
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intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
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g4x_disable_trickle_feed(i915);
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intel_display_ilk_init_clock_gating(i915->display);
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intel_pch_init_clock_gating(i915->display);
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}
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@ -152,11 +90,7 @@ static void gen6_check_mch_setup(struct drm_i915_private *i915)
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static void gen6_init_clock_gating(struct drm_i915_private *i915)
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{
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u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
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intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
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intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
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intel_display_gen6_init_clock_gating(i915->display);
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intel_uncore_write(&i915->uncore, GEN6_UCGCTL1,
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intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) |
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@ -191,19 +125,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *i915)
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*
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* WaFbcAsynchFlipDisableFbcQueue:snb
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*/
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intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1,
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intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) |
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ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
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intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
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intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
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ILK_DPARB_GATE | ILK_VSDPFD_FULL);
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intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D,
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intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) |
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ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
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ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
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g4x_disable_trickle_feed(i915);
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intel_pch_init_clock_gating(i915->display);
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gen6_check_mch_setup(i915);
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@ -335,10 +256,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
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{
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struct intel_display *display = i915->display;
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intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
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/* WaFbcAsynchFlipDisableFbcQueue:ivb */
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intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
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intel_display_ivb_init_clock_gating(display);
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/* WaDisableBackToBackFlipFix:ivb */
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intel_uncore_write(&i915->uncore, IVB_CHICKEN3,
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@ -367,7 +285,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
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intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
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0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
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g4x_disable_trickle_feed(i915);
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intel_display_disable_trickle_feed(display);
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||||
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||||
intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
|
||||
GEN6_MBC_SNPCR_MED);
|
||||
|
|
@ -440,21 +358,12 @@ static void chv_init_clock_gating(struct drm_i915_private *i915)
|
|||
|
||||
static void g4x_init_clock_gating(struct drm_i915_private *i915)
|
||||
{
|
||||
u32 dspclk_gate;
|
||||
|
||||
intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0);
|
||||
intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
|
||||
GS_UNIT_CLOCK_GATE_DISABLE |
|
||||
CL_UNIT_CLOCK_GATE_DISABLE);
|
||||
intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0);
|
||||
dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
|
||||
OVRUNIT_CLOCK_GATE_DISABLE |
|
||||
OVCUNIT_CLOCK_GATE_DISABLE;
|
||||
if (IS_GM45(i915))
|
||||
dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
|
||||
intel_uncore_write(&i915->uncore, DSPCLK_GATE_D, dspclk_gate);
|
||||
|
||||
g4x_disable_trickle_feed(i915);
|
||||
intel_display_g4x_init_clock_gating(i915->display);
|
||||
}
|
||||
|
||||
static void i965gm_init_clock_gating(struct drm_i915_private *i915)
|
||||
|
|
@ -463,7 +372,7 @@ static void i965gm_init_clock_gating(struct drm_i915_private *i915)
|
|||
|
||||
intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
|
||||
intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
|
||||
intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
|
||||
intel_display_i965gm_init_clock_gating(i915->display);
|
||||
intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
|
||||
intel_uncore_write16(uncore, DEUC, 0);
|
||||
intel_uncore_write(uncore,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user