mirror of
https://github.com/torvalds/linux.git
synced 2026-05-22 22:22:08 +02:00
Qualcomm clock updates for v6.8
New drivers to support global, display, gpu, tcsr, and rpmh clocks for the SM8650 platform is introduced. Global and RPMh clock support for the new X1E80100 platform is added. Support for the Stromer APCS PLL found in IPQ5018 is added. A new type of branch clock, with support for controlling separate memory control bits is introduced, and used in the newly introduced clock driver for the ECPRI on QDU1000 and QRU1000. A number of missing clock related to CSI2 on MSM8939 are added. Support for the camera clock controller on SC8280XP is added. PLL configuration is corrected in GPU and Video clock controllers for SM8150, runtim PM support and a few missing resets are added to the video clock controller. For SM8550 configuration of a variety of GDSCs in GCC is corrected. Shared RCGs was not marked appropriately when the driver was upstreamed, so this is corrected as well. For GPU and Display clock controllers PLL configuration settings are reviewed and corrected. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmWQ6LwVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3Fnr8P/0hDbF5/DHs/XAlrK0bcL6zeNFs6 Zxbp9NnWDvN9jQzjaDbm0WlR7yXhzn0QaL5nsyDxBHYZYwRIeBbFqnYQvjlRYgEr UJJXOY5MKpCXbIo0quSvuA7yXbBeVggJkl01Jsgw8Z0c6ggp0EwmHSbHh62QfQIL htxNeiF1JBr3bDGHuG/FNQMy9YuEt1wHT0XK7Q+Cim7oRiDPao6tYlUuEVg6vSJH oBRb3lTVFlbxsrucVbv6i+UckPY766FCrgLeX7xJ2j8cDWLiWYTimkcAgTWTatei ofQyoEoLvTgm3ADe69RxSgzJPociYiyyLRIx2WiNcRKGOHMVE4IxigUN5EDQD2V+ QOyNkXYcO8rwAjb4CANGi++ZzEvsM7NPHVbdv5+U2pTuw9p2t42PZLaAoq+TX0LD NMRJjW8sVK02+L6EdP8ALeqFsx3z/aJTqsQqJbBYqUSrpQVclnwGDIxm1JGAlhd8 Zph4uOCfPHGyVsPmO4RwY/Y1sP7IpMPoyuwt1rpo3hIB3zr97uGs/lUEhxvcRDm5 7xnxzCazGsWuhKMvkjOX87t4W5dj49iG8cUxGpzcW3OeWYWkd6wX26yQ6JWUizNy K8J8I+DCWih6DXhLfqqdlFSO5KrTmk1TFVRLxfVNTc1VsS2mY9fRtHefhpvcAjKs j/4U2W+Ez6U2Y74/ =qjtu -----END PGP SIGNATURE----- Merge tag 'qcom-clk-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: - New drivers to support global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650 - Global and RPMh clock support for the Qualcomm X1E80100 SoC - Support for the Stromer APCS PLL found in Qualcomm IPQ5018 - Add a new type of branch clock, with support for controlling separate memory control bits, to the Qualcomm clk driver - Use new branch type in Qualcomm ECPRI clk driver for QDU1000 and QRU1000 - Add a number of missing clocks related to CSI2 on Qualcomm MSM8939 - Add support for the camera clock controller on Qualcomm SC8280XP - Correct PLL configuration in GPU and video clock controllers for Qualcomm SM8150 - Add runtime PM support and a few missing resets to Qualcomm SM8150 video clock controller - Fix configuration of various GCC GDSCs on Qualcomm SM8550 - Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver - Fix up GPU and display clock controllers PLL configuration settings on Qualcomm SM8550 * tag 'qcom-clk-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (41 commits) clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config clk: qcom: dispcc-sm8550: Use the correct PLL configuration function clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: gpucc-sm8550: Update GPU PLL settings clk: qcom: gcc-sm8550: Mark RCGs shared where applicable clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag clk: qcom: camcc-sc8280xp: Prevent error pointer dereference clk: qcom: videocc-sm8150: Add runtime PM support clk: qcom: videocc-sm8150: Add missing PLL config property clk: qcom: videocc-sm8150: Update the videocc resets dt-bindings: clock: Update the videocc resets for sm8150 clk: qcom: rpmh: Add support for X1E80100 rpmh clocks clk: qcom: Add Global Clock controller (GCC) driver for X1E80100 dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for X1E80100 dt-bindings: clock: qcom: Add X1E80100 GCC clocks clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000 clk: qcom: branch: Add mem ops support for branch2 clocks ...
This commit is contained in:
Stephen Boyd
commit
93beaa981a
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|
@ -16,6 +16,7 @@ description:
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,ipq5018-a53pll
|
||||
- qcom,ipq5332-a53pll
|
||||
- qcom,ipq6018-a53pll
|
||||
- qcom,ipq8074-a53pll
|
||||
|
|
|
|||
|
|
@ -15,6 +15,9 @@ description: |
|
|||
|
||||
See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8250-camcc
|
||||
|
|
@ -33,15 +36,6 @@ properties:
|
|||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: MMCX power domain
|
||||
|
|
@ -56,14 +50,10 @@ properties:
|
|||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
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||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -0,0 +1,57 @@
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|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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||||
%YAML 1.2
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||||
---
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||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq6018.yaml#
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||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
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||||
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||||
title: Qualcomm Global Clock & Reset Controller on IPQ6018
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||||
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||||
maintainers:
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||||
- Stephen Boyd <sboyd@kernel.org>
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||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
- Robert Marko <robimarko@gmail.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
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domains on IPQ6018.
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||||
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||||
See also::
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include/dt-bindings/clock/qcom,gcc-ipq6018.h
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include/dt-bindings/reset/qcom,gcc-ipq6018.h
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||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
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||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-ipq6018
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||||
|
||||
clocks:
|
||||
items:
|
||||
- description: board XO clock
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- description: sleep clock
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||||
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||||
clock-names:
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||||
items:
|
||||
- const: xo
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||||
- const: sleep_clk
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||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
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||||
- clock-names
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||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
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||||
- |
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||||
clock-controller@1800000 {
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compatible = "qcom,gcc-ipq6018";
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reg = <0x01800000 0x80000>;
|
||||
clocks = <&xo>, <&sleep_clk>;
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clock-names = "xo", "sleep_clk";
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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};
|
||||
...
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|
@ -15,8 +15,6 @@ description: |
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|||
domains.
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See also::
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include/dt-bindings/clock/qcom,gcc-ipq6018.h
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include/dt-bindings/reset/qcom,gcc-ipq6018.h
|
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include/dt-bindings/clock/qcom,gcc-msm8953.h
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||||
include/dt-bindings/clock/qcom,gcc-mdm9607.h
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||||
|
||||
|
|
@ -26,7 +24,6 @@ allOf:
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-ipq6018
|
||||
- qcom,gcc-mdm9607
|
||||
|
||||
required:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,68 @@
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|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,qdu1000-ecpricc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm ECPRI Clock & Reset Controller for QDU1000 and QRU1000
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
- Imran Shaik <quic_imrashai@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm ECPRI Specification V2.0 Common Public Radio Interface clock control
|
||||
module which supports the clocks, resets on QDU1000 and QRU1000
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,qdu1000-ecpricc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 source from GCC
|
||||
- description: GPLL1 source from GCC
|
||||
- description: GPLL2 source from GCC
|
||||
- description: GPLL3 source from GCC
|
||||
- description: GPLL4 source from GCC
|
||||
- description: GPLL5 source from GCC
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,qdu1000-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@280000 {
|
||||
compatible = "qcom,qdu1000-ecpricc";
|
||||
reg = <0x00280000 0x31c00>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>,
|
||||
<&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>,
|
||||
<&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>,
|
||||
<&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>,
|
||||
<&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -35,6 +35,8 @@ properties:
|
|||
- qcom,sm8350-rpmh-clk
|
||||
- qcom,sm8450-rpmh-clk
|
||||
- qcom,sm8550-rpmh-clk
|
||||
- qcom,sm8650-rpmh-clk
|
||||
- qcom,x1e80100-rpmh-clk
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -15,6 +15,9 @@ description: |
|
|||
|
||||
See also:: include/dt-bindings/clock/qcom,camcc-sc7180.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7180-camcc
|
||||
|
|
@ -31,28 +34,15 @@ properties:
|
|||
- const: iface
|
||||
- const: xo
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -15,6 +15,9 @@ description: |
|
|||
|
||||
See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7280-camcc
|
||||
|
|
@ -31,28 +34,15 @@ properties:
|
|||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -15,6 +15,9 @@ description: |
|
|||
|
||||
See also:: include/dt-bindings/clock/qcom,camcc-sm845.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-camcc
|
||||
|
|
@ -27,28 +30,15 @@ properties:
|
|||
items:
|
||||
- const: bi_tcxo
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -16,10 +16,15 @@ description: |
|
|||
See also::
|
||||
include/dt-bindings/clock/qcom,sm8450-camcc.h
|
||||
include/dt-bindings/clock/qcom,sm8550-camcc.h
|
||||
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc8280xp-camcc
|
||||
- qcom,sm8450-camcc
|
||||
- qcom,sm8550-camcc
|
||||
|
||||
|
|
@ -40,29 +45,16 @@ properties:
|
|||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- power-domains
|
||||
- required-opps
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -17,12 +17,14 @@ description: |
|
|||
include/dt-bindings/clock/qcom,sm8450-gpucc.h
|
||||
include/dt-bindings/clock/qcom,sm8550-gpucc.h
|
||||
include/dt-bindings/reset/qcom,sm8450-gpucc.h
|
||||
include/dt-bindings/reset/qcom,sm8650-gpucc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm8450-gpucc
|
||||
- qcom,sm8550-gpucc
|
||||
- qcom,sm8650-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -13,12 +13,16 @@ description: |
|
|||
Qualcomm TCSR clock control module provides the clocks, resets and
|
||||
power domains on SM8550
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h
|
||||
See also:
|
||||
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
|
||||
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm8550-tcsr
|
||||
- enum:
|
||||
- qcom,sm8550-tcsr
|
||||
- qcom,sm8650-tcsr
|
||||
- const: syscon
|
||||
|
||||
clocks:
|
||||
|
|
|
|||
106
Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml
Normal file
106
Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml
Normal file
|
|
@ -0,0 +1,106 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller for SM8650
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SM8650.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm8650-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board Always On XO source
|
||||
- description: Display's AHB clock
|
||||
- description: sleep clock
|
||||
- description: Byte clock from DSI PHY0
|
||||
- description: Pixel clock from DSI PHY0
|
||||
- description: Byte clock from DSI PHY1
|
||||
- description: Pixel clock from DSI PHY1
|
||||
- description: Link clock from DP PHY0
|
||||
- description: VCO DIV clock from DP PHY0
|
||||
- description: Link clock from DP PHY1
|
||||
- description: VCO DIV clock from DP PHY1
|
||||
- description: Link clock from DP PHY2
|
||||
- description: VCO DIV clock from DP PHY2
|
||||
- description: Link clock from DP PHY3
|
||||
- description: VCO DIV clock from DP PHY3
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the MMCX power domain.
|
||||
maxItems: 1
|
||||
|
||||
required-opps:
|
||||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,sm8650-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sm8650-dispcc";
|
||||
reg = <0x0af00000 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&gcc GCC_DISP_AHB_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi1_phy 0>,
|
||||
<&dsi1_phy 1>,
|
||||
<&dp0_phy 0>,
|
||||
<&dp0_phy 1>,
|
||||
<&dp1_phy 0>,
|
||||
<&dp1_phy 1>,
|
||||
<&dp2_phy 0>,
|
||||
<&dp2_phy 1>,
|
||||
<&dp3_phy 0>,
|
||||
<&dp3_phy 1>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
...
|
||||
65
Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml
Normal file
65
Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8650-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on SM8650
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SM8650
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm8650-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8650-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board Always On XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE 0 Pipe clock source
|
||||
- description: PCIE 1 Pipe clock source
|
||||
- description: PCIE 1 Phy Auxiliary clock source
|
||||
- description: UFS Phy Rx symbol 0 clock source
|
||||
- description: UFS Phy Rx symbol 1 clock source
|
||||
- description: UFS Phy Tx symbol 0 clock source
|
||||
- description: USB3 Phy wrapper pipe clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,sm8650-gcc";
|
||||
reg = <0x00100000 0x001f4200>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>,
|
||||
<&pcie0_phy>,
|
||||
<&pcie1_phy>,
|
||||
<&pcie_1_phy_aux_clk>,
|
||||
<&ufs_mem_phy 0>,
|
||||
<&ufs_mem_phy 1>,
|
||||
<&ufs_mem_phy 2>,
|
||||
<&usb_1_qmpphy>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on X1E80100
|
||||
|
||||
maintainers:
|
||||
- Rajendra Nayak <quic_rjendra@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on X1E80100
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,x1e80100-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,x1e80100-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIe 3 pipe clock
|
||||
- description: PCIe 4 pipe clock
|
||||
- description: PCIe 5 pipe clock
|
||||
- description: PCIe 6a pipe clock
|
||||
- description: PCIe 6b pipe clock
|
||||
- description: USB QMP Phy 0 clock source
|
||||
- description: USB QMP Phy 1 clock source
|
||||
- description: USB QMP Phy 2 clock source
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the CX power domain.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,x1e80100-gcc";
|
||||
reg = <0x00100000 0x200000>;
|
||||
clocks = <&bi_tcxo_div2>,
|
||||
<&sleep_clk>,
|
||||
<&pcie3_phy>,
|
||||
<&pcie4_phy>,
|
||||
<&pcie5_phy>,
|
||||
<&pcie6a_phy>,
|
||||
<&pcie6b_phy>,
|
||||
<&usb_1_ss0_qmpphy 0>,
|
||||
<&usb_1_ss1_qmpphy 1>,
|
||||
<&usb_1_ss2_qmpphy 2>;
|
||||
power-domains = <&rpmhpd RPMHPD_CX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -20,6 +20,16 @@ menuconfig COMMON_CLK_QCOM
|
|||
|
||||
if COMMON_CLK_QCOM
|
||||
|
||||
config CLK_X1E80100_GCC
|
||||
tristate "X1E80100 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on Qualcomm Technologies, Inc
|
||||
X1E80100 devices.
|
||||
Say Y if you want to use peripheral devices such as UART, SPI, I2C,
|
||||
USB, UFS, SD/eMMC, PCIe, etc.
|
||||
|
||||
config QCOM_A53PLL
|
||||
tristate "MSM8916 A53 PLL"
|
||||
help
|
||||
|
|
@ -427,6 +437,15 @@ config SC_CAMCC_7280
|
|||
Say Y if you want to support camera devices and functionality such as
|
||||
capturing pictures.
|
||||
|
||||
config SC_CAMCC_8280XP
|
||||
tristate "SC8280XP Camera Clock Controller"
|
||||
select SC_GCC_8280XP
|
||||
help
|
||||
Support for the camera clock controller on Qualcomm Technologies, Inc
|
||||
SC8280XP devices.
|
||||
Say Y if you want to support camera devices and functionality such as
|
||||
capturing pictures.
|
||||
|
||||
config SC_DISPCC_7180
|
||||
tristate "SC7180 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
|
|
@ -668,6 +687,15 @@ config QDU_GCC_1000
|
|||
QRU1000 devices. Say Y if you want to use peripheral
|
||||
devices such as UART, SPI, I2C, USB, SD, PCIe, etc.
|
||||
|
||||
config QDU_ECPRICC_1000
|
||||
tristate "QDU1000/QRU1000 ECPRI Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QDU_GCC_1000
|
||||
help
|
||||
Support for the ECPRI clock controller on QDU1000 and
|
||||
QRU1000 devices. Say Y if you want to support the ECPRI
|
||||
clock controller functionality such as Ethernet.
|
||||
|
||||
config SDM_GCC_845
|
||||
tristate "SDM845/SDM670 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
|
|
@ -842,6 +870,16 @@ config SM_DISPCC_8550
|
|||
Say Y if you want to support display devices and functionality such as
|
||||
splash screen.
|
||||
|
||||
config SM_DISPCC_8650
|
||||
tristate "SM8650 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_8650
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
SM8650 devices.
|
||||
Say Y if you want to support display devices and functionality such as
|
||||
splash screen.
|
||||
|
||||
config SM_GCC_4450
|
||||
tristate "SM4450 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
|
|
@ -938,6 +976,15 @@ config SM_GCC_8550
|
|||
Say Y if you want to use peripheral devices such as UART,
|
||||
SPI, I2C, USB, SD/UFS, PCIe etc.
|
||||
|
||||
config SM_GCC_8650
|
||||
tristate "SM8650 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on SM8650 devices.
|
||||
Say Y if you want to use peripheral devices such as UART,
|
||||
SPI, I2C, USB, SD/UFS, PCIe etc.
|
||||
|
||||
config SM_GPUCC_6115
|
||||
tristate "SM6115 Graphics Clock Controller"
|
||||
select SM_GCC_6115
|
||||
|
|
@ -1019,6 +1066,14 @@ config SM_GPUCC_8550
|
|||
Say Y if you want to support graphics controller devices and
|
||||
functionality such as 3D graphics.
|
||||
|
||||
config SM_GPUCC_8650
|
||||
tristate "SM8650 Graphics Clock Controller"
|
||||
select SM_GCC_8650
|
||||
help
|
||||
Support for the graphics clock controller on SM8650 devices.
|
||||
Say Y if you want to support graphics controller devices and
|
||||
functionality such as 3D graphics.
|
||||
|
||||
config SM_TCSRCC_8550
|
||||
tristate "SM8550 TCSR Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
|
|
@ -1027,6 +1082,14 @@ config SM_TCSRCC_8550
|
|||
Support for the TCSR clock controller on SM8550 devices.
|
||||
Say Y if you want to use peripheral devices such as SD/UFS.
|
||||
|
||||
config SM_TCSRCC_8650
|
||||
tristate "SM8650 TCSR Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the TCSR clock controller on SM8650 devices.
|
||||
Say Y if you want to use peripheral devices such as SD/UFS.
|
||||
|
||||
config SM_VIDEOCC_8150
|
||||
tristate "SM8150 Video Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
|
|||
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
|
||||
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
|
||||
obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
|
||||
obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o
|
||||
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
|
||||
obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
|
||||
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
|
||||
|
|
@ -65,9 +66,11 @@ obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o
|
|||
obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
|
||||
obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o
|
||||
obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
|
||||
obj-$(CONFIG_QDU_ECPRICC_1000) += ecpricc-qdu1000.o
|
||||
obj-$(CONFIG_QDU_GCC_1000) += gcc-qdu1000.o
|
||||
obj-$(CONFIG_SC_CAMCC_7180) += camcc-sc7180.o
|
||||
obj-$(CONFIG_SC_CAMCC_7280) += camcc-sc7280.o
|
||||
obj-$(CONFIG_SC_CAMCC_8280XP) += camcc-sc8280xp.o
|
||||
obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
|
||||
obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o
|
||||
obj-$(CONFIG_SC_DISPCC_8280XP) += dispcc-sc8280xp.o
|
||||
|
|
@ -110,6 +113,7 @@ obj-$(CONFIG_SM_DISPCC_6375) += dispcc-sm6375.o
|
|||
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
|
||||
obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o
|
||||
obj-$(CONFIG_SM_DISPCC_8550) += dispcc-sm8550.o
|
||||
obj-$(CONFIG_SM_DISPCC_8650) += dispcc-sm8650.o
|
||||
obj-$(CONFIG_SM_GCC_4450) += gcc-sm4450.o
|
||||
obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o
|
||||
obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
|
||||
|
|
@ -121,6 +125,7 @@ obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
|
|||
obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
|
||||
obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
|
||||
obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o
|
||||
obj-$(CONFIG_SM_GCC_8650) += gcc-sm8650.o
|
||||
obj-$(CONFIG_SM_GPUCC_6115) += gpucc-sm6115.o
|
||||
obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o
|
||||
obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
|
||||
|
|
@ -130,7 +135,9 @@ obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
|
|||
obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
|
||||
obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o
|
||||
obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o
|
||||
obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o
|
||||
obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
|
||||
obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_8350) += videocc-sm8350.o
|
||||
|
|
|
|||
|
|
@ -73,6 +73,20 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config ipq5018_pll_config = {
|
||||
.l = 0x32,
|
||||
.config_ctl_val = 0x4001075b,
|
||||
.config_ctl_hi_val = 0x304,
|
||||
.main_output_mask = BIT(0),
|
||||
.aux_output_mask = BIT(1),
|
||||
.early_output_mask = BIT(3),
|
||||
.alpha_en_mask = BIT(24),
|
||||
.status_val = 0x3,
|
||||
.status_mask = GENMASK(10, 8),
|
||||
.lock_det = BIT(2),
|
||||
.test_ctl_hi_val = 0x00400003,
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config ipq5332_pll_config = {
|
||||
.l = 0x2d,
|
||||
.config_ctl_val = 0x4001075b,
|
||||
|
|
@ -129,6 +143,12 @@ struct apss_pll_data {
|
|||
const struct alpha_pll_config *pll_config;
|
||||
};
|
||||
|
||||
static const struct apss_pll_data ipq5018_pll_data = {
|
||||
.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
|
||||
.pll = &ipq_pll_stromer_plus,
|
||||
.pll_config = &ipq5018_pll_config,
|
||||
};
|
||||
|
||||
static struct apss_pll_data ipq5332_pll_data = {
|
||||
.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
|
||||
.pll = &ipq_pll_stromer_plus,
|
||||
|
|
@ -195,6 +215,7 @@ static int apss_ipq_pll_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
static const struct of_device_id apss_ipq_pll_match_table[] = {
|
||||
{ .compatible = "qcom,ipq5018-a53pll", .data = &ipq5018_pll_data },
|
||||
{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
|
||||
{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
|
||||
{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
|
||||
|
|
|
|||
3045
drivers/clk/qcom/camcc-sc8280xp.c
Normal file
3045
drivers/clk/qcom/camcc-sc8280xp.c
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -1,6 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
|
|
@ -134,6 +135,43 @@ static void clk_branch2_disable(struct clk_hw *hw)
|
|||
clk_branch_toggle(hw, false, clk_branch2_check_halt);
|
||||
}
|
||||
|
||||
static int clk_branch2_mem_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);
|
||||
struct clk_branch branch = mem_br->branch;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg,
|
||||
mem_br->mem_enable_ack_mask, mem_br->mem_enable_ack_mask);
|
||||
|
||||
ret = regmap_read_poll_timeout(branch.clkr.regmap, mem_br->mem_ack_reg,
|
||||
val, val & mem_br->mem_enable_ack_mask, 0, 200);
|
||||
if (ret) {
|
||||
WARN(1, "%s mem enable failed\n", clk_hw_get_name(&branch.clkr.hw));
|
||||
return ret;
|
||||
}
|
||||
|
||||
return clk_branch2_enable(hw);
|
||||
}
|
||||
|
||||
static void clk_branch2_mem_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);
|
||||
|
||||
regmap_update_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg,
|
||||
mem_br->mem_enable_ack_mask, 0);
|
||||
|
||||
return clk_branch2_disable(hw);
|
||||
}
|
||||
|
||||
const struct clk_ops clk_branch2_mem_ops = {
|
||||
.enable = clk_branch2_mem_enable,
|
||||
.disable = clk_branch2_mem_disable,
|
||||
.is_enabled = clk_is_enabled_regmap,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_branch2_mem_ops);
|
||||
|
||||
const struct clk_ops clk_branch2_ops = {
|
||||
.enable = clk_branch2_enable,
|
||||
.disable = clk_branch2_disable,
|
||||
|
|
|
|||
|
|
@ -38,6 +38,23 @@ struct clk_branch {
|
|||
struct clk_regmap clkr;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct clk_mem_branch - gating clock which are associated with memories
|
||||
*
|
||||
* @mem_enable_reg: branch clock memory gating register
|
||||
* @mem_ack_reg: branch clock memory ack register
|
||||
* @mem_enable_ack_mask: branch clock memory enable and ack field in @mem_ack_reg
|
||||
* @branch: branch clock gating handle
|
||||
*
|
||||
* Clock which can gate its memories.
|
||||
*/
|
||||
struct clk_mem_branch {
|
||||
u32 mem_enable_reg;
|
||||
u32 mem_ack_reg;
|
||||
u32 mem_enable_ack_mask;
|
||||
struct clk_branch branch;
|
||||
};
|
||||
|
||||
/* Branch clock common bits for HLOS-owned clocks */
|
||||
#define CBCR_CLK_OFF BIT(31)
|
||||
#define CBCR_NOC_FSM_STATUS GENMASK(30, 28)
|
||||
|
|
@ -85,8 +102,12 @@ extern const struct clk_ops clk_branch_ops;
|
|||
extern const struct clk_ops clk_branch2_ops;
|
||||
extern const struct clk_ops clk_branch_simple_ops;
|
||||
extern const struct clk_ops clk_branch2_aon_ops;
|
||||
extern const struct clk_ops clk_branch2_mem_ops;
|
||||
|
||||
#define to_clk_branch(_hw) \
|
||||
container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
|
||||
|
||||
#define to_clk_mem_branch(_hw) \
|
||||
container_of(to_clk_branch(_hw), struct clk_mem_branch, branch)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -372,6 +372,9 @@ DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1);
|
|||
DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1);
|
||||
DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1);
|
||||
|
||||
DEFINE_CLK_RPMH_VRM(clk3, _a2, "clka3", 2);
|
||||
DEFINE_CLK_RPMH_VRM(clk4, _a2, "clka4", 2);
|
||||
DEFINE_CLK_RPMH_VRM(clk5, _a2, "clka5", 2);
|
||||
DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2);
|
||||
DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2);
|
||||
DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2);
|
||||
|
|
@ -630,6 +633,37 @@ static const struct clk_rpmh_desc clk_rpmh_sm8550 = {
|
|||
.num_clks = ARRAY_SIZE(sm8550_rpmh_clocks),
|
||||
};
|
||||
|
||||
static struct clk_hw *sm8650_rpmh_clocks[] = {
|
||||
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
|
||||
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
|
||||
[RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw,
|
||||
[RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw,
|
||||
[RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw,
|
||||
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw,
|
||||
[RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw,
|
||||
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw,
|
||||
[RPMH_RF_CLK1] = &clk_rpmh_clk1_a1.hw,
|
||||
[RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_ao.hw,
|
||||
[RPMH_RF_CLK2] = &clk_rpmh_clk2_a1.hw,
|
||||
[RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_ao.hw,
|
||||
/*
|
||||
* The clka3 RPMh resource is missing in cmd-db
|
||||
* for current platforms, while the clka3 exists
|
||||
* on the PMK8550, the clock is unconnected and
|
||||
* unused.
|
||||
*/
|
||||
[RPMH_RF_CLK4] = &clk_rpmh_clk4_a2.hw,
|
||||
[RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a2_ao.hw,
|
||||
[RPMH_RF_CLK5] = &clk_rpmh_clk5_a2.hw,
|
||||
[RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a2_ao.hw,
|
||||
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
|
||||
};
|
||||
|
||||
static const struct clk_rpmh_desc clk_rpmh_sm8650 = {
|
||||
.clks = sm8650_rpmh_clocks,
|
||||
.num_clks = ARRAY_SIZE(sm8650_rpmh_clocks),
|
||||
};
|
||||
|
||||
static struct clk_hw *sc7280_rpmh_clocks[] = {
|
||||
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
|
||||
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
|
||||
|
|
@ -737,6 +771,28 @@ static const struct clk_rpmh_desc clk_rpmh_sm4450 = {
|
|||
.num_clks = ARRAY_SIZE(sm4450_rpmh_clocks),
|
||||
};
|
||||
|
||||
static struct clk_hw *x1e80100_rpmh_clocks[] = {
|
||||
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
|
||||
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
|
||||
[RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw,
|
||||
[RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw,
|
||||
[RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw,
|
||||
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw,
|
||||
[RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw,
|
||||
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw,
|
||||
[RPMH_RF_CLK3] = &clk_rpmh_clk3_a2.hw,
|
||||
[RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a2_ao.hw,
|
||||
[RPMH_RF_CLK4] = &clk_rpmh_clk4_a2.hw,
|
||||
[RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a2_ao.hw,
|
||||
[RPMH_RF_CLK5] = &clk_rpmh_clk5_a2.hw,
|
||||
[RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a2_ao.hw,
|
||||
};
|
||||
|
||||
static const struct clk_rpmh_desc clk_rpmh_x1e80100 = {
|
||||
.clks = x1e80100_rpmh_clocks,
|
||||
.num_clks = ARRAY_SIZE(x1e80100_rpmh_clocks),
|
||||
};
|
||||
|
||||
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
|
||||
void *data)
|
||||
{
|
||||
|
|
@ -837,7 +893,9 @@ static const struct of_device_id clk_rpmh_match_table[] = {
|
|||
{ .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},
|
||||
{ .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450},
|
||||
{ .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550},
|
||||
{ .compatible = "qcom,sm8650-rpmh-clk", .data = &clk_rpmh_sm8650},
|
||||
{ .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},
|
||||
{ .compatible = "qcom,x1e80100-rpmh-clk", .data = &clk_rpmh_x1e80100},
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
|
||||
|
|
|
|||
|
|
@ -81,6 +81,10 @@ static const struct alpha_pll_config disp_cc_pll0_config = {
|
|||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x82aa299c,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000003,
|
||||
.test_ctl_hi1_val = 0x00009000,
|
||||
.test_ctl_hi2_val = 0x00000034,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000005,
|
||||
};
|
||||
|
|
@ -108,6 +112,10 @@ static const struct alpha_pll_config disp_cc_pll1_config = {
|
|||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x82aa299c,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000003,
|
||||
.test_ctl_hi1_val = 0x00009000,
|
||||
.test_ctl_hi2_val = 0x00000034,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000005,
|
||||
};
|
||||
|
|
@ -1766,8 +1774,8 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev)
|
|||
goto err_put_rpm;
|
||||
}
|
||||
|
||||
clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
||||
clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
|
||||
clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
||||
clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
|
||||
|
||||
/* Enable clock gating for MDP clocks */
|
||||
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
|
||||
|
|
|
|||
1818
drivers/clk/qcom/dispcc-sm8650.c
Normal file
1818
drivers/clk/qcom/dispcc-sm8650.c
Normal file
File diff suppressed because it is too large
Load Diff
2456
drivers/clk/qcom/ecpricc-qdu1000.c
Normal file
2456
drivers/clk/qcom/ecpricc-qdu1000.c
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -696,7 +696,7 @@ static struct clk_rcg2 apss_ahb_clk_src = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
|
||||
static const struct freq_tbl ftbl_gcc_camss_csi0_1_2_clk[] = {
|
||||
F(100000000, P_GPLL0, 8, 0, 0),
|
||||
F(200000000, P_GPLL0, 4, 0, 0),
|
||||
{ }
|
||||
|
|
@ -706,7 +706,7 @@ static struct clk_rcg2 csi0_clk_src = {
|
|||
.cmd_rcgr = 0x4e020,
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_xo_gpll0_map,
|
||||
.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
|
||||
.freq_tbl = ftbl_gcc_camss_csi0_1_2_clk,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "csi0_clk_src",
|
||||
.parent_data = gcc_xo_gpll0_parent_data,
|
||||
|
|
@ -719,7 +719,7 @@ static struct clk_rcg2 csi1_clk_src = {
|
|||
.cmd_rcgr = 0x4f020,
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_xo_gpll0_map,
|
||||
.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
|
||||
.freq_tbl = ftbl_gcc_camss_csi0_1_2_clk,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "csi1_clk_src",
|
||||
.parent_data = gcc_xo_gpll0_parent_data,
|
||||
|
|
@ -728,6 +728,19 @@ static struct clk_rcg2 csi1_clk_src = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 csi2_clk_src = {
|
||||
.cmd_rcgr = 0x3c020,
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_xo_gpll0_map,
|
||||
.freq_tbl = ftbl_gcc_camss_csi0_1_2_clk,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "csi2_clk_src",
|
||||
.parent_data = gcc_xo_gpll0_parent_data,
|
||||
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
|
||||
F(19200000, P_XO, 1, 0, 0),
|
||||
F(50000000, P_GPLL0, 16, 0, 0),
|
||||
|
|
@ -2385,6 +2398,91 @@ static struct clk_branch gcc_camss_csi1rdi_clk = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_camss_csi2_ahb_clk = {
|
||||
.halt_reg = 0x3c040,
|
||||
.clkr = {
|
||||
.enable_reg = 0x3c040,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_camss_csi2_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&camss_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_camss_csi2_clk = {
|
||||
.halt_reg = 0x3c03c,
|
||||
.clkr = {
|
||||
.enable_reg = 0x3c03c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_camss_csi2_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&csi2_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_camss_csi2phy_clk = {
|
||||
.halt_reg = 0x3c048,
|
||||
.clkr = {
|
||||
.enable_reg = 0x3c048,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_camss_csi2phy_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&csi2_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_camss_csi2pix_clk = {
|
||||
.halt_reg = 0x3c058,
|
||||
.clkr = {
|
||||
.enable_reg = 0x3c058,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_camss_csi2pix_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&csi2_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_camss_csi2rdi_clk = {
|
||||
.halt_reg = 0x3c050,
|
||||
.clkr = {
|
||||
.enable_reg = 0x3c050,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_camss_csi2rdi_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&csi2_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_camss_csi_vfe0_clk = {
|
||||
.halt_reg = 0x58050,
|
||||
.clkr = {
|
||||
|
|
@ -3682,6 +3780,7 @@ static struct clk_regmap *gcc_msm8939_clocks[] = {
|
|||
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
|
||||
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
|
||||
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
|
||||
[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
|
||||
[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
|
||||
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
|
||||
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
|
||||
|
|
@ -3751,6 +3850,11 @@ static struct clk_regmap *gcc_msm8939_clocks[] = {
|
|||
[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
|
||||
[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
|
||||
[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
|
||||
[GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
|
||||
[GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
|
||||
[GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
|
||||
[GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
|
||||
[GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
|
||||
[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
|
||||
[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
|
||||
[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
|
||||
|
|
|
|||
|
|
@ -401,7 +401,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
|
|||
.parent_data = gcc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -416,7 +416,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
|
|||
.parent_data = gcc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -431,7 +431,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
|
|||
.parent_data = gcc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -451,7 +451,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
|
|||
.parent_data = gcc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -471,7 +471,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -486,7 +486,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
|
|||
.parent_data = gcc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -501,7 +501,7 @@ static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -521,7 +521,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -536,7 +536,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -551,7 +551,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -566,7 +566,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -596,7 +596,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -611,7 +611,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -626,7 +626,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -641,7 +641,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -656,7 +656,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -671,7 +671,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -700,7 +700,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
|
||||
|
|
@ -717,7 +717,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
|
||||
|
|
@ -750,7 +750,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
|
||||
|
|
@ -767,7 +767,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
|
||||
|
|
@ -784,7 +784,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
|
||||
|
|
@ -801,7 +801,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
|
||||
|
|
@ -818,7 +818,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
|
||||
|
|
@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
|
||||
|
|
@ -852,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
|
||||
|
|
@ -869,7 +869,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
|
||||
|
|
@ -886,7 +886,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
|
||||
|
|
@ -903,7 +903,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
|
||||
|
|
@ -920,7 +920,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
|
||||
|
|
@ -937,7 +937,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
|
||||
|
|
@ -975,7 +975,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_8,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
|
||||
|
|
@ -992,7 +992,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
|
||||
|
|
@ -1025,7 +1025,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
|
|||
.parent_data = gcc_parent_data_9,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1048,7 +1048,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1071,7 +1071,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1093,7 +1093,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
|
|||
.parent_data = gcc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1114,7 +1114,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
|
|||
.parent_data = gcc_parent_data_4,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1136,7 +1136,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1159,7 +1159,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1174,7 +1174,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1189,7 +1189,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
|
|||
.parent_data = gcc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -2998,38 +2998,46 @@ static struct clk_branch gcc_video_axi1_clk = {
|
|||
|
||||
static struct gdsc pcie_0_gdsc = {
|
||||
.gdscr = 0x6b004,
|
||||
.collapse_ctrl = 0x52020,
|
||||
.collapse_mask = BIT(0),
|
||||
.pd = {
|
||||
.name = "pcie_0_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc pcie_0_phy_gdsc = {
|
||||
.gdscr = 0x6c000,
|
||||
.collapse_ctrl = 0x52020,
|
||||
.collapse_mask = BIT(3),
|
||||
.pd = {
|
||||
.name = "pcie_0_phy_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc pcie_1_gdsc = {
|
||||
.gdscr = 0x8d004,
|
||||
.collapse_ctrl = 0x52020,
|
||||
.collapse_mask = BIT(1),
|
||||
.pd = {
|
||||
.name = "pcie_1_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc pcie_1_phy_gdsc = {
|
||||
.gdscr = 0x8e000,
|
||||
.collapse_ctrl = 0x52020,
|
||||
.collapse_mask = BIT(4),
|
||||
.pd = {
|
||||
.name = "pcie_1_phy_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc ufs_phy_gdsc = {
|
||||
|
|
@ -3038,7 +3046,7 @@ static struct gdsc ufs_phy_gdsc = {
|
|||
.name = "ufs_phy_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc ufs_mem_phy_gdsc = {
|
||||
|
|
@ -3047,7 +3055,7 @@ static struct gdsc ufs_mem_phy_gdsc = {
|
|||
.name = "ufs_mem_phy_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc usb30_prim_gdsc = {
|
||||
|
|
@ -3056,7 +3064,7 @@ static struct gdsc usb30_prim_gdsc = {
|
|||
.name = "usb30_prim_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc usb3_phy_gdsc = {
|
||||
|
|
@ -3065,7 +3073,7 @@ static struct gdsc usb3_phy_gdsc = {
|
|||
.name = "usb3_phy_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct clk_regmap *gcc_sm8550_clocks[] = {
|
||||
|
|
|
|||
3849
drivers/clk/qcom/gcc-sm8650.c
Normal file
3849
drivers/clk/qcom/gcc-sm8650.c
Normal file
File diff suppressed because it is too large
Load Diff
6807
drivers/clk/qcom/gcc-x1e80100.c
Normal file
6807
drivers/clk/qcom/gcc-x1e80100.c
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -37,8 +37,8 @@ static struct alpha_pll_config gpu_cc_pll1_config = {
|
|||
.config_ctl_hi_val = 0x00002267,
|
||||
.config_ctl_hi1_val = 0x00000024,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000002,
|
||||
.test_ctl_hi1_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000000,
|
||||
.test_ctl_hi1_val = 0x00000020,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000805,
|
||||
.user_ctl_hi1_val = 0x000000d0,
|
||||
|
|
|
|||
|
|
@ -35,12 +35,12 @@ enum {
|
|||
};
|
||||
|
||||
static const struct pll_vco lucid_ole_vco[] = {
|
||||
{ 249600000, 2300000000, 0 },
|
||||
{ 249600000, 2000000000, 0 },
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config gpu_cc_pll0_config = {
|
||||
.l = 0x0d,
|
||||
.alpha = 0x0,
|
||||
.l = 0x1e,
|
||||
.alpha = 0xbaaa,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x82aa299c,
|
||||
|
|
|
|||
663
drivers/clk/qcom/gpucc-sm8650.c
Normal file
663
drivers/clk/qcom/gpucc-sm8650.c
Normal file
|
|
@ -0,0 +1,663 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,sm8650-gpucc.h>
|
||||
#include <dt-bindings/reset/qcom,sm8650-gpucc.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "clk-regmap-mux.h"
|
||||
#include "clk-regmap-phy-mux.h"
|
||||
#include "gdsc.h"
|
||||
#include "reset.h"
|
||||
|
||||
enum {
|
||||
DT_BI_TCXO,
|
||||
DT_GPLL0_OUT_MAIN,
|
||||
DT_GPLL0_OUT_MAIN_DIV,
|
||||
};
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_GPLL0_OUT_MAIN,
|
||||
P_GPLL0_OUT_MAIN_DIV,
|
||||
P_GPU_CC_PLL0_OUT_MAIN,
|
||||
P_GPU_CC_PLL1_OUT_MAIN,
|
||||
};
|
||||
|
||||
static struct pll_vco lucid_ole_vco[] = {
|
||||
{ 249600000, 2100000000, 0 },
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config gpu_cc_pll0_config = {
|
||||
.l = 0x20,
|
||||
.alpha = 0x4aaa,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x82aa299c,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000003,
|
||||
.test_ctl_hi1_val = 0x00009000,
|
||||
.test_ctl_hi2_val = 0x00000034,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000005,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll0 = {
|
||||
.offset = 0x0,
|
||||
.vco_table = lucid_ole_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_ole_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_evo_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config gpu_cc_pll1_config = {
|
||||
.l = 0x1b,
|
||||
.alpha = 0x1555,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x82aa299c,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000003,
|
||||
.test_ctl_hi1_val = 0x00009000,
|
||||
.test_ctl_hi2_val = 0x00000034,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000005,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll1 = {
|
||||
.offset = 0x1000,
|
||||
.vco_table = lucid_ole_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_ole_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_pll1",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_evo_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .index = DT_GPLL0_OUT_MAIN },
|
||||
{ .index = DT_GPLL0_OUT_MAIN_DIV },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
|
||||
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &gpu_cc_pll0.clkr.hw },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .index = DT_GPLL0_OUT_MAIN },
|
||||
{ .index = DT_GPLL0_OUT_MAIN_DIV },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_2[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .index = DT_GPLL0_OUT_MAIN },
|
||||
{ .index = DT_GPLL0_OUT_MAIN_DIV },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
|
||||
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_ff_clk_src = {
|
||||
.cmd_rcgr = 0x9474,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_ff_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(260000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
|
||||
F(625000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
|
||||
.cmd_rcgr = 0x9318,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gmu_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
|
||||
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_hub_clk_src = {
|
||||
.cmd_rcgr = 0x93ec,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hub_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div gpu_cc_hub_div_clk_src = {
|
||||
.reg = 0x942c,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_hub_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_ahb_clk = {
|
||||
.halt_reg = 0x911c,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x911c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_crc_ahb_clk = {
|
||||
.halt_reg = 0x9120,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9120,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_crc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_accu_shift_clk = {
|
||||
.halt_reg = 0x9160,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9160,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "gpu_cc_cx_accu_shift_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_ff_clk = {
|
||||
.halt_reg = 0x914c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x914c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_ff_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_ff_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_gmu_clk = {
|
||||
.halt_reg = 0x913c,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x913c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_gmu_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_gmu_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cxo_aon_clk = {
|
||||
.halt_reg = 0x9004,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cxo_aon_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cxo_clk = {
|
||||
.halt_reg = 0x9144,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9144,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cxo_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_demet_clk = {
|
||||
.halt_reg = 0x900c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x900c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_demet_clk",
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_freq_measure_clk = {
|
||||
.halt_reg = 0x9008,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_freq_measure_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
|
||||
.halt_reg = 0x90a8,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90a8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gfx3d_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = {
|
||||
.halt_reg = 0x90c8,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90c8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gfx3d_rdvm_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gmu_clk = {
|
||||
.halt_reg = 0x90bc,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90bc,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gmu_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_gmu_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_vsense_clk = {
|
||||
.halt_reg = 0x90b0,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90b0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_vsense_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_accu_shift_clk = {
|
||||
.halt_reg = 0x90d0,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90d0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "gpu_cc_gx_accu_shift_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_ff_clk = {
|
||||
.halt_reg = 0x90c0,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90c0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "gpu_cc_gx_ff_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_ff_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
|
||||
.halt_reg = 0x7000,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x7000,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hub_aon_clk = {
|
||||
.halt_reg = 0x93e8,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x93e8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hub_aon_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hub_cx_int_clk = {
|
||||
.halt_reg = 0x9148,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9148,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hub_cx_int_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
|
||||
.halt_reg = 0x9150,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9150,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_memnoc_gfx_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_sleep_clk = {
|
||||
.halt_reg = 0x9134,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9134,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_sleep_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_dpm_clk = {
|
||||
.halt_reg = 0x9164,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9164,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "gpu_cc_dpm_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc gpu_cx_gdsc = {
|
||||
.gdscr = 0x9108,
|
||||
.gds_hw_ctrl = 0x9168,
|
||||
.clk_dis_wait_val = 8,
|
||||
.pd = {
|
||||
.name = "gpu_cx_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = VOTABLE | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc gpu_gx_gdsc = {
|
||||
.gdscr = 0x905c,
|
||||
.clamp_io_ctrl = 0x9504,
|
||||
.resets = (unsigned int []){ GPUCC_GPU_CC_GX_BCR,
|
||||
GPUCC_GPU_CC_ACD_BCR,
|
||||
GPUCC_GPU_CC_GX_ACD_IROOT_BCR },
|
||||
.reset_count = 3,
|
||||
.pd = {
|
||||
.name = "gpu_gx_gdsc",
|
||||
.power_on = gdsc_gx_do_nothing_enable,
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
|
||||
};
|
||||
|
||||
static struct clk_regmap *gpu_cc_sm8650_clocks[] = {
|
||||
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
|
||||
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
|
||||
[GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr,
|
||||
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
|
||||
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
|
||||
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
|
||||
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
|
||||
[GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
|
||||
[GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr,
|
||||
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
|
||||
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
|
||||
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
|
||||
[GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr,
|
||||
[GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr,
|
||||
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
|
||||
[GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr,
|
||||
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
|
||||
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
|
||||
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
|
||||
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
|
||||
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
|
||||
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
|
||||
[GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr,
|
||||
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
|
||||
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
|
||||
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
|
||||
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map gpu_cc_sm8650_resets[] = {
|
||||
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
|
||||
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
|
||||
[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
|
||||
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
|
||||
[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
|
||||
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
|
||||
[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
|
||||
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
|
||||
[GPUCC_GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c },
|
||||
};
|
||||
|
||||
static struct gdsc *gpu_cc_sm8650_gdscs[] = {
|
||||
[GPU_CX_GDSC] = &gpu_cx_gdsc,
|
||||
[GPU_GX_GDSC] = &gpu_gx_gdsc,
|
||||
};
|
||||
|
||||
static const struct regmap_config gpu_cc_sm8650_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0xa000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc gpu_cc_sm8650_desc = {
|
||||
.config = &gpu_cc_sm8650_regmap_config,
|
||||
.clks = gpu_cc_sm8650_clocks,
|
||||
.num_clks = ARRAY_SIZE(gpu_cc_sm8650_clocks),
|
||||
.resets = gpu_cc_sm8650_resets,
|
||||
.num_resets = ARRAY_SIZE(gpu_cc_sm8650_resets),
|
||||
.gdscs = gpu_cc_sm8650_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8650_gdscs),
|
||||
};
|
||||
|
||||
static const struct of_device_id gpu_cc_sm8650_match_table[] = {
|
||||
{ .compatible = "qcom,sm8650-gpucc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, gpu_cc_sm8650_match_table);
|
||||
|
||||
static int gpu_cc_sm8650_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &gpu_cc_sm8650_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
|
||||
clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &gpu_cc_sm8650_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver gpu_cc_sm8650_driver = {
|
||||
.probe = gpu_cc_sm8650_probe,
|
||||
.driver = {
|
||||
.name = "sm8650-gpucc",
|
||||
.of_match_table = gpu_cc_sm8650_match_table,
|
||||
},
|
||||
};
|
||||
module_platform_driver(gpu_cc_sm8650_driver);
|
||||
|
||||
MODULE_DESCRIPTION("QTI GPU_CC SM8650 Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
182
drivers/clk/qcom/tcsrcc-sm8650.c
Normal file
182
drivers/clk/qcom/tcsrcc-sm8650.c
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,sm8650-tcsr.h>
|
||||
|
||||
#include "clk-branch.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "common.h"
|
||||
#include "reset.h"
|
||||
|
||||
enum {
|
||||
DT_BI_TCXO_PAD,
|
||||
};
|
||||
|
||||
static struct clk_branch tcsr_pcie_0_clkref_en = {
|
||||
.halt_reg = 0x31100,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x31100,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "tcsr_pcie_0_clkref_en",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_BI_TCXO_PAD,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch tcsr_pcie_1_clkref_en = {
|
||||
.halt_reg = 0x31114,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x31114,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "tcsr_pcie_1_clkref_en",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_BI_TCXO_PAD,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch tcsr_ufs_clkref_en = {
|
||||
.halt_reg = 0x31110,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x31110,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "tcsr_ufs_clkref_en",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_BI_TCXO_PAD,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch tcsr_ufs_pad_clkref_en = {
|
||||
.halt_reg = 0x31104,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x31104,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "tcsr_ufs_pad_clkref_en",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_BI_TCXO_PAD,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch tcsr_usb2_clkref_en = {
|
||||
.halt_reg = 0x31118,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x31118,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "tcsr_usb2_clkref_en",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_BI_TCXO_PAD,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch tcsr_usb3_clkref_en = {
|
||||
.halt_reg = 0x31108,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x31108,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "tcsr_usb3_clkref_en",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_BI_TCXO_PAD,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap *tcsr_cc_sm8650_clocks[] = {
|
||||
[TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr,
|
||||
[TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr,
|
||||
[TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr,
|
||||
[TCSR_UFS_PAD_CLKREF_EN] = &tcsr_ufs_pad_clkref_en.clkr,
|
||||
[TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr,
|
||||
[TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr,
|
||||
};
|
||||
|
||||
static const struct regmap_config tcsr_cc_sm8650_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x3b000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc tcsr_cc_sm8650_desc = {
|
||||
.config = &tcsr_cc_sm8650_regmap_config,
|
||||
.clks = tcsr_cc_sm8650_clocks,
|
||||
.num_clks = ARRAY_SIZE(tcsr_cc_sm8650_clocks),
|
||||
};
|
||||
|
||||
static const struct of_device_id tcsr_cc_sm8650_match_table[] = {
|
||||
{ .compatible = "qcom,sm8650-tcsr" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, tcsr_cc_sm8650_match_table);
|
||||
|
||||
static int tcsr_cc_sm8650_probe(struct platform_device *pdev)
|
||||
{
|
||||
return qcom_cc_probe(pdev, &tcsr_cc_sm8650_desc);
|
||||
}
|
||||
|
||||
static struct platform_driver tcsr_cc_sm8650_driver = {
|
||||
.probe = tcsr_cc_sm8650_probe,
|
||||
.driver = {
|
||||
.name = "tcsr_cc-sm8650",
|
||||
.of_match_table = tcsr_cc_sm8650_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init tcsr_cc_sm8650_init(void)
|
||||
{
|
||||
return platform_driver_register(&tcsr_cc_sm8650_driver);
|
||||
}
|
||||
subsys_initcall(tcsr_cc_sm8650_init);
|
||||
|
||||
static void __exit tcsr_cc_sm8650_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&tcsr_cc_sm8650_driver);
|
||||
}
|
||||
module_exit(tcsr_cc_sm8650_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI TCSRCC SM8650 Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -6,6 +6,7 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,videocc-sm8150.h>
|
||||
|
|
@ -33,6 +34,7 @@ static struct alpha_pll_config video_pll0_config = {
|
|||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00002267,
|
||||
.config_ctl_hi1_val = 0x00000024,
|
||||
.test_ctl_hi1_val = 0x00000020,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000805,
|
||||
.user_ctl_hi1_val = 0x000000D0,
|
||||
|
|
@ -214,6 +216,10 @@ static const struct regmap_config video_cc_sm8150_regmap_config = {
|
|||
|
||||
static const struct qcom_reset_map video_cc_sm8150_resets[] = {
|
||||
[VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },
|
||||
[VIDEO_CC_INTERFACE_BCR] = { 0x8f0 },
|
||||
[VIDEO_CC_MVS0_BCR] = { 0x870 },
|
||||
[VIDEO_CC_MVS1_BCR] = { 0x8b0 },
|
||||
[VIDEO_CC_MVSC_BCR] = { 0x810 },
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc video_cc_sm8150_desc = {
|
||||
|
|
@ -235,17 +241,32 @@ MODULE_DEVICE_TABLE(of, video_cc_sm8150_match_table);
|
|||
static int video_cc_sm8150_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
ret = devm_pm_runtime_enable(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pm_runtime_resume_and_get(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &video_cc_sm8150_desc);
|
||||
if (IS_ERR(regmap))
|
||||
if (IS_ERR(regmap)) {
|
||||
pm_runtime_put_sync(&pdev->dev);
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
|
||||
clk_trion_pll_configure(&video_pll0, regmap, &video_pll0_config);
|
||||
|
||||
/* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
|
||||
regmap_update_bits(regmap, 0x984, 0x1, 0x1);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap);
|
||||
ret = qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap);
|
||||
|
||||
pm_runtime_put_sync(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver video_cc_sm8150_driver = {
|
||||
|
|
|
|||
|
|
@ -193,6 +193,12 @@
|
|||
#define GCC_VENUS0_CORE1_VCODEC0_CLK 184
|
||||
#define GCC_OXILI_TIMER_CLK 185
|
||||
#define SYSTEM_MM_NOC_BFDCD_CLK_SRC 186
|
||||
#define CSI2_CLK_SRC 187
|
||||
#define GCC_CAMSS_CSI2_AHB_CLK 188
|
||||
#define GCC_CAMSS_CSI2_CLK 189
|
||||
#define GCC_CAMSS_CSI2PHY_CLK 190
|
||||
#define GCC_CAMSS_CSI2PIX_CLK 191
|
||||
#define GCC_CAMSS_CSI2RDI_CLK 192
|
||||
|
||||
/* Indexes for GDSCs */
|
||||
#define BIMC_GDSC 0
|
||||
|
|
|
|||
147
include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
Normal file
147
include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
Normal file
|
|
@ -0,0 +1,147 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_ECPRI_CC_QDU1000_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_ECPRI_CC_QDU1000_H
|
||||
|
||||
/* ECPRI_CC clocks */
|
||||
#define ECPRI_CC_PLL0 0
|
||||
#define ECPRI_CC_PLL1 1
|
||||
#define ECPRI_CC_ECPRI_CG_CLK 2
|
||||
#define ECPRI_CC_ECPRI_CLK_SRC 3
|
||||
#define ECPRI_CC_ECPRI_DMA_CLK 4
|
||||
#define ECPRI_CC_ECPRI_DMA_CLK_SRC 5
|
||||
#define ECPRI_CC_ECPRI_DMA_NOC_CLK 6
|
||||
#define ECPRI_CC_ECPRI_FAST_CLK 7
|
||||
#define ECPRI_CC_ECPRI_FAST_CLK_SRC 8
|
||||
#define ECPRI_CC_ECPRI_FAST_DIV2_CLK 9
|
||||
#define ECPRI_CC_ECPRI_FAST_DIV2_CLK_SRC 10
|
||||
#define ECPRI_CC_ECPRI_FAST_DIV2_NOC_CLK 11
|
||||
#define ECPRI_CC_ECPRI_FR_CLK 12
|
||||
#define ECPRI_CC_ECPRI_ORAN_CLK_SRC 13
|
||||
#define ECPRI_CC_ECPRI_ORAN_DIV2_CLK 14
|
||||
#define ECPRI_CC_ETH_100G_C2C0_HM_FF_CLK_SRC 15
|
||||
#define ECPRI_CC_ETH_100G_C2C0_UDP_FIFO_CLK 16
|
||||
#define ECPRI_CC_ETH_100G_C2C1_UDP_FIFO_CLK 17
|
||||
#define ECPRI_CC_ETH_100G_C2C_0_HM_FF_0_CLK 18
|
||||
#define ECPRI_CC_ETH_100G_C2C_0_HM_FF_1_CLK 19
|
||||
#define ECPRI_CC_ETH_100G_C2C_HM_FF_0_DIV_CLK_SRC 20
|
||||
#define ECPRI_CC_ETH_100G_C2C_HM_FF_1_DIV_CLK_SRC 21
|
||||
#define ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK 22
|
||||
#define ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK_SRC 23
|
||||
#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_CLK 24
|
||||
#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_DIV_CLK_SRC 25
|
||||
#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_CLK 26
|
||||
#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_DIV_CLK_SRC 27
|
||||
#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_CLK_SRC 28
|
||||
#define ECPRI_CC_ETH_100G_DBG_C2C_UDP_FIFO_CLK 29
|
||||
#define ECPRI_CC_ETH_100G_FH0_HM_FF_CLK_SRC 30
|
||||
#define ECPRI_CC_ETH_100G_FH0_MACSEC_CLK_SRC 31
|
||||
#define ECPRI_CC_ETH_100G_FH1_HM_FF_CLK_SRC 32
|
||||
#define ECPRI_CC_ETH_100G_FH1_MACSEC_CLK_SRC 33
|
||||
#define ECPRI_CC_ETH_100G_FH2_HM_FF_CLK_SRC 34
|
||||
#define ECPRI_CC_ETH_100G_FH2_MACSEC_CLK_SRC 35
|
||||
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_0_CLK 36
|
||||
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_0_DIV_CLK_SRC 37
|
||||
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_1_CLK 38
|
||||
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_1_DIV_CLK_SRC 39
|
||||
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_2_CLK 40
|
||||
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_2_DIV_CLK_SRC 41
|
||||
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_3_CLK 42
|
||||
#define ECPRI_CC_ETH_100G_FH_0_HM_FF_3_DIV_CLK_SRC 43
|
||||
#define ECPRI_CC_ETH_100G_FH_0_UDP_FIFO_CLK 44
|
||||
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_0_CLK 45
|
||||
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_0_DIV_CLK_SRC 46
|
||||
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_1_CLK 47
|
||||
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_1_DIV_CLK_SRC 48
|
||||
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_2_CLK 49
|
||||
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_2_DIV_CLK_SRC 50
|
||||
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_3_CLK 51
|
||||
#define ECPRI_CC_ETH_100G_FH_1_HM_FF_3_DIV_CLK_SRC 52
|
||||
#define ECPRI_CC_ETH_100G_FH_1_UDP_FIFO_CLK 53
|
||||
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_0_CLK 54
|
||||
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_0_DIV_CLK_SRC 55
|
||||
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_1_CLK 56
|
||||
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_1_DIV_CLK_SRC 57
|
||||
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_2_CLK 58
|
||||
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_2_DIV_CLK_SRC 59
|
||||
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_3_CLK 60
|
||||
#define ECPRI_CC_ETH_100G_FH_2_HM_FF_3_DIV_CLK_SRC 61
|
||||
#define ECPRI_CC_ETH_100G_FH_2_UDP_FIFO_CLK 62
|
||||
#define ECPRI_CC_ETH_100G_FH_MACSEC_0_CLK 63
|
||||
#define ECPRI_CC_ETH_100G_FH_MACSEC_1_CLK 64
|
||||
#define ECPRI_CC_ETH_100G_FH_MACSEC_2_CLK 65
|
||||
#define ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK 66
|
||||
#define ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK_SRC 67
|
||||
#define ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK 68
|
||||
#define ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK_SRC 69
|
||||
#define ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK 70
|
||||
#define ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK_SRC 71
|
||||
#define ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK 72
|
||||
#define ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK_SRC 73
|
||||
#define ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK 74
|
||||
#define ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK_SRC 75
|
||||
#define ECPRI_CC_ETH_DBG_NFAPI_AXI_CLK 76
|
||||
#define ECPRI_CC_ETH_DBG_NOC_AXI_CLK 77
|
||||
#define ECPRI_CC_ETH_PHY_0_OCK_SRAM_CLK 78
|
||||
#define ECPRI_CC_ETH_PHY_1_OCK_SRAM_CLK 79
|
||||
#define ECPRI_CC_ETH_PHY_2_OCK_SRAM_CLK 80
|
||||
#define ECPRI_CC_ETH_PHY_3_OCK_SRAM_CLK 81
|
||||
#define ECPRI_CC_ETH_PHY_4_OCK_SRAM_CLK 82
|
||||
#define ECPRI_CC_MSS_EMAC_CLK 83
|
||||
#define ECPRI_CC_MSS_EMAC_CLK_SRC 84
|
||||
#define ECPRI_CC_MSS_ORAN_CLK 85
|
||||
#define ECPRI_CC_PHY0_LANE0_RX_CLK 86
|
||||
#define ECPRI_CC_PHY0_LANE0_TX_CLK 87
|
||||
#define ECPRI_CC_PHY0_LANE1_RX_CLK 88
|
||||
#define ECPRI_CC_PHY0_LANE1_TX_CLK 89
|
||||
#define ECPRI_CC_PHY0_LANE2_RX_CLK 90
|
||||
#define ECPRI_CC_PHY0_LANE2_TX_CLK 91
|
||||
#define ECPRI_CC_PHY0_LANE3_RX_CLK 92
|
||||
#define ECPRI_CC_PHY0_LANE3_TX_CLK 93
|
||||
#define ECPRI_CC_PHY1_LANE0_RX_CLK 94
|
||||
#define ECPRI_CC_PHY1_LANE0_TX_CLK 95
|
||||
#define ECPRI_CC_PHY1_LANE1_RX_CLK 96
|
||||
#define ECPRI_CC_PHY1_LANE1_TX_CLK 97
|
||||
#define ECPRI_CC_PHY1_LANE2_RX_CLK 98
|
||||
#define ECPRI_CC_PHY1_LANE2_TX_CLK 99
|
||||
#define ECPRI_CC_PHY1_LANE3_RX_CLK 100
|
||||
#define ECPRI_CC_PHY1_LANE3_TX_CLK 101
|
||||
#define ECPRI_CC_PHY2_LANE0_RX_CLK 102
|
||||
#define ECPRI_CC_PHY2_LANE0_TX_CLK 103
|
||||
#define ECPRI_CC_PHY2_LANE1_RX_CLK 104
|
||||
#define ECPRI_CC_PHY2_LANE1_TX_CLK 105
|
||||
#define ECPRI_CC_PHY2_LANE2_RX_CLK 106
|
||||
#define ECPRI_CC_PHY2_LANE2_TX_CLK 107
|
||||
#define ECPRI_CC_PHY2_LANE3_RX_CLK 108
|
||||
#define ECPRI_CC_PHY2_LANE3_TX_CLK 109
|
||||
#define ECPRI_CC_PHY3_LANE0_RX_CLK 110
|
||||
#define ECPRI_CC_PHY3_LANE0_TX_CLK 111
|
||||
#define ECPRI_CC_PHY3_LANE1_RX_CLK 112
|
||||
#define ECPRI_CC_PHY3_LANE1_TX_CLK 113
|
||||
#define ECPRI_CC_PHY3_LANE2_RX_CLK 114
|
||||
#define ECPRI_CC_PHY3_LANE2_TX_CLK 115
|
||||
#define ECPRI_CC_PHY3_LANE3_RX_CLK 116
|
||||
#define ECPRI_CC_PHY3_LANE3_TX_CLK 117
|
||||
#define ECPRI_CC_PHY4_LANE0_RX_CLK 118
|
||||
#define ECPRI_CC_PHY4_LANE0_TX_CLK 119
|
||||
#define ECPRI_CC_PHY4_LANE1_RX_CLK 120
|
||||
#define ECPRI_CC_PHY4_LANE1_TX_CLK 121
|
||||
#define ECPRI_CC_PHY4_LANE2_RX_CLK 122
|
||||
#define ECPRI_CC_PHY4_LANE2_TX_CLK 123
|
||||
#define ECPRI_CC_PHY4_LANE3_RX_CLK 124
|
||||
#define ECPRI_CC_PHY4_LANE3_TX_CLK 125
|
||||
|
||||
/* ECPRI_CC resets */
|
||||
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ECPRI_SS_BCR 0
|
||||
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_C2C_BCR 1
|
||||
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH0_BCR 2
|
||||
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH1_BCR 3
|
||||
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH2_BCR 4
|
||||
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_WRAPPER_TOP_BCR 5
|
||||
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_MODEM_BCR 6
|
||||
#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_NOC_BCR 7
|
||||
|
||||
#endif
|
||||
179
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
Normal file
179
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
Normal file
|
|
@ -0,0 +1,179 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2023, Linaro Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLK_QCOM_CAMCC_SC8280XP_H__
|
||||
#define __DT_BINDINGS_CLK_QCOM_CAMCC_SC8280XP_H__
|
||||
|
||||
/* CAMCC clocks */
|
||||
#define CAMCC_PLL0 0
|
||||
#define CAMCC_PLL0_OUT_EVEN 1
|
||||
#define CAMCC_PLL0_OUT_ODD 2
|
||||
#define CAMCC_PLL1 3
|
||||
#define CAMCC_PLL1_OUT_EVEN 4
|
||||
#define CAMCC_PLL2 5
|
||||
#define CAMCC_PLL3 6
|
||||
#define CAMCC_PLL3_OUT_EVEN 7
|
||||
#define CAMCC_PLL4 8
|
||||
#define CAMCC_PLL4_OUT_EVEN 9
|
||||
#define CAMCC_PLL5 10
|
||||
#define CAMCC_PLL5_OUT_EVEN 11
|
||||
#define CAMCC_PLL6 12
|
||||
#define CAMCC_PLL6_OUT_EVEN 13
|
||||
#define CAMCC_PLL7 14
|
||||
#define CAMCC_PLL7_OUT_EVEN 15
|
||||
#define CAMCC_PLL7_OUT_ODD 16
|
||||
#define CAMCC_BPS_AHB_CLK 17
|
||||
#define CAMCC_BPS_AREG_CLK 18
|
||||
#define CAMCC_BPS_AXI_CLK 19
|
||||
#define CAMCC_BPS_CLK 20
|
||||
#define CAMCC_BPS_CLK_SRC 21
|
||||
#define CAMCC_CAMNOC_AXI_CLK 22
|
||||
#define CAMCC_CAMNOC_AXI_CLK_SRC 23
|
||||
#define CAMCC_CAMNOC_DCD_XO_CLK 24
|
||||
#define CAMCC_CCI_0_CLK 25
|
||||
#define CAMCC_CCI_0_CLK_SRC 26
|
||||
#define CAMCC_CCI_1_CLK 27
|
||||
#define CAMCC_CCI_1_CLK_SRC 28
|
||||
#define CAMCC_CCI_2_CLK 29
|
||||
#define CAMCC_CCI_2_CLK_SRC 30
|
||||
#define CAMCC_CCI_3_CLK 31
|
||||
#define CAMCC_CCI_3_CLK_SRC 32
|
||||
#define CAMCC_CORE_AHB_CLK 33
|
||||
#define CAMCC_CPAS_AHB_CLK 34
|
||||
#define CAMCC_CPHY_RX_CLK_SRC 35
|
||||
#define CAMCC_CSI0PHYTIMER_CLK 36
|
||||
#define CAMCC_CSI0PHYTIMER_CLK_SRC 37
|
||||
#define CAMCC_CSI1PHYTIMER_CLK 38
|
||||
#define CAMCC_CSI1PHYTIMER_CLK_SRC 39
|
||||
#define CAMCC_CSI2PHYTIMER_CLK 40
|
||||
#define CAMCC_CSI2PHYTIMER_CLK_SRC 41
|
||||
#define CAMCC_CSI3PHYTIMER_CLK 42
|
||||
#define CAMCC_CSI3PHYTIMER_CLK_SRC 43
|
||||
#define CAMCC_CSIPHY0_CLK 44
|
||||
#define CAMCC_CSIPHY1_CLK 45
|
||||
#define CAMCC_CSIPHY2_CLK 46
|
||||
#define CAMCC_CSIPHY3_CLK 47
|
||||
#define CAMCC_FAST_AHB_CLK_SRC 48
|
||||
#define CAMCC_GDSC_CLK 49
|
||||
#define CAMCC_ICP_AHB_CLK 50
|
||||
#define CAMCC_ICP_CLK 51
|
||||
#define CAMCC_ICP_CLK_SRC 52
|
||||
#define CAMCC_IFE_0_AXI_CLK 53
|
||||
#define CAMCC_IFE_0_CLK 54
|
||||
#define CAMCC_IFE_0_CLK_SRC 55
|
||||
#define CAMCC_IFE_0_CPHY_RX_CLK 56
|
||||
#define CAMCC_IFE_0_CSID_CLK 57
|
||||
#define CAMCC_IFE_0_CSID_CLK_SRC 58
|
||||
#define CAMCC_IFE_0_DSP_CLK 59
|
||||
#define CAMCC_IFE_1_AXI_CLK 60
|
||||
#define CAMCC_IFE_1_CLK 61
|
||||
#define CAMCC_IFE_1_CLK_SRC 62
|
||||
#define CAMCC_IFE_1_CPHY_RX_CLK 63
|
||||
#define CAMCC_IFE_1_CSID_CLK 64
|
||||
#define CAMCC_IFE_1_CSID_CLK_SRC 65
|
||||
#define CAMCC_IFE_1_DSP_CLK 66
|
||||
#define CAMCC_IFE_2_AXI_CLK 67
|
||||
#define CAMCC_IFE_2_CLK 68
|
||||
#define CAMCC_IFE_2_CLK_SRC 69
|
||||
#define CAMCC_IFE_2_CPHY_RX_CLK 70
|
||||
#define CAMCC_IFE_2_CSID_CLK 71
|
||||
#define CAMCC_IFE_2_CSID_CLK_SRC 72
|
||||
#define CAMCC_IFE_2_DSP_CLK 73
|
||||
#define CAMCC_IFE_3_AXI_CLK 74
|
||||
#define CAMCC_IFE_3_CLK 75
|
||||
#define CAMCC_IFE_3_CLK_SRC 76
|
||||
#define CAMCC_IFE_3_CPHY_RX_CLK 77
|
||||
#define CAMCC_IFE_3_CSID_CLK 78
|
||||
#define CAMCC_IFE_3_CSID_CLK_SRC 79
|
||||
#define CAMCC_IFE_3_DSP_CLK 80
|
||||
#define CAMCC_IFE_LITE_0_CLK 81
|
||||
#define CAMCC_IFE_LITE_0_CLK_SRC 82
|
||||
#define CAMCC_IFE_LITE_0_CPHY_RX_CLK 83
|
||||
#define CAMCC_IFE_LITE_0_CSID_CLK 84
|
||||
#define CAMCC_IFE_LITE_0_CSID_CLK_SRC 85
|
||||
#define CAMCC_IFE_LITE_1_CLK 86
|
||||
#define CAMCC_IFE_LITE_1_CLK_SRC 87
|
||||
#define CAMCC_IFE_LITE_1_CPHY_RX_CLK 88
|
||||
#define CAMCC_IFE_LITE_1_CSID_CLK 89
|
||||
#define CAMCC_IFE_LITE_1_CSID_CLK_SRC 90
|
||||
#define CAMCC_IFE_LITE_2_CLK 91
|
||||
#define CAMCC_IFE_LITE_2_CLK_SRC 92
|
||||
#define CAMCC_IFE_LITE_2_CPHY_RX_CLK 93
|
||||
#define CAMCC_IFE_LITE_2_CSID_CLK 94
|
||||
#define CAMCC_IFE_LITE_2_CSID_CLK_SRC 95
|
||||
#define CAMCC_IFE_LITE_3_CLK 96
|
||||
#define CAMCC_IFE_LITE_3_CLK_SRC 97
|
||||
#define CAMCC_IFE_LITE_3_CPHY_RX_CLK 98
|
||||
#define CAMCC_IFE_LITE_3_CSID_CLK 99
|
||||
#define CAMCC_IFE_LITE_3_CSID_CLK_SRC 100
|
||||
#define CAMCC_IPE_0_AHB_CLK 101
|
||||
#define CAMCC_IPE_0_AREG_CLK 102
|
||||
#define CAMCC_IPE_0_AXI_CLK 103
|
||||
#define CAMCC_IPE_0_CLK 104
|
||||
#define CAMCC_IPE_0_CLK_SRC 105
|
||||
#define CAMCC_IPE_1_AHB_CLK 106
|
||||
#define CAMCC_IPE_1_AREG_CLK 107
|
||||
#define CAMCC_IPE_1_AXI_CLK 108
|
||||
#define CAMCC_IPE_1_CLK 109
|
||||
#define CAMCC_JPEG_CLK 110
|
||||
#define CAMCC_JPEG_CLK_SRC 111
|
||||
#define CAMCC_LRME_CLK 112
|
||||
#define CAMCC_LRME_CLK_SRC 113
|
||||
#define CAMCC_MCLK0_CLK 114
|
||||
#define CAMCC_MCLK0_CLK_SRC 115
|
||||
#define CAMCC_MCLK1_CLK 116
|
||||
#define CAMCC_MCLK1_CLK_SRC 117
|
||||
#define CAMCC_MCLK2_CLK 118
|
||||
#define CAMCC_MCLK2_CLK_SRC 119
|
||||
#define CAMCC_MCLK3_CLK 120
|
||||
#define CAMCC_MCLK3_CLK_SRC 121
|
||||
#define CAMCC_MCLK4_CLK 122
|
||||
#define CAMCC_MCLK4_CLK_SRC 123
|
||||
#define CAMCC_MCLK5_CLK 124
|
||||
#define CAMCC_MCLK5_CLK_SRC 125
|
||||
#define CAMCC_MCLK6_CLK 126
|
||||
#define CAMCC_MCLK6_CLK_SRC 127
|
||||
#define CAMCC_MCLK7_CLK 128
|
||||
#define CAMCC_MCLK7_CLK_SRC 129
|
||||
#define CAMCC_SLEEP_CLK 130
|
||||
#define CAMCC_SLEEP_CLK_SRC 131
|
||||
#define CAMCC_SLOW_AHB_CLK_SRC 132
|
||||
#define CAMCC_XO_CLK_SRC 133
|
||||
|
||||
/* CAMCC resets */
|
||||
#define CAMCC_BPS_BCR 0
|
||||
#define CAMCC_CAMNOC_BCR 1
|
||||
#define CAMCC_CCI_BCR 2
|
||||
#define CAMCC_CPAS_BCR 3
|
||||
#define CAMCC_CSI0PHY_BCR 4
|
||||
#define CAMCC_CSI1PHY_BCR 5
|
||||
#define CAMCC_CSI2PHY_BCR 6
|
||||
#define CAMCC_CSI3PHY_BCR 7
|
||||
#define CAMCC_ICP_BCR 8
|
||||
#define CAMCC_IFE_0_BCR 9
|
||||
#define CAMCC_IFE_1_BCR 10
|
||||
#define CAMCC_IFE_2_BCR 11
|
||||
#define CAMCC_IFE_3_BCR 12
|
||||
#define CAMCC_IFE_LITE_0_BCR 13
|
||||
#define CAMCC_IFE_LITE_1_BCR 14
|
||||
#define CAMCC_IFE_LITE_2_BCR 15
|
||||
#define CAMCC_IFE_LITE_3_BCR 16
|
||||
#define CAMCC_IPE_0_BCR 17
|
||||
#define CAMCC_IPE_1_BCR 18
|
||||
#define CAMCC_JPEG_BCR 19
|
||||
#define CAMCC_LRME_BCR 20
|
||||
|
||||
/* CAMCC GDSCRs */
|
||||
#define BPS_GDSC 0
|
||||
#define IFE_0_GDSC 1
|
||||
#define IFE_1_GDSC 2
|
||||
#define IFE_2_GDSC 3
|
||||
#define IFE_3_GDSC 4
|
||||
#define IPE_0_GDSC 5
|
||||
#define IPE_1_GDSC 6
|
||||
#define TITAN_TOP_GDSC 7
|
||||
|
||||
#endif /* __DT_BINDINGS_CLK_QCOM_CAMCC_SC8280XP_H__ */
|
||||
102
include/dt-bindings/clock/qcom,sm8650-dispcc.h
Normal file
102
include/dt-bindings/clock/qcom,sm8650-dispcc.h
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
|
||||
* Copyright (c) 2023, Linaro Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
|
||||
|
||||
/* DISP_CC clocks */
|
||||
#define DISP_CC_MDSS_ACCU_CLK 0
|
||||
#define DISP_CC_MDSS_AHB1_CLK 1
|
||||
#define DISP_CC_MDSS_AHB_CLK 2
|
||||
#define DISP_CC_MDSS_AHB_CLK_SRC 3
|
||||
#define DISP_CC_MDSS_BYTE0_CLK 4
|
||||
#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
|
||||
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
|
||||
#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
|
||||
#define DISP_CC_MDSS_BYTE1_CLK 8
|
||||
#define DISP_CC_MDSS_BYTE1_CLK_SRC 9
|
||||
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10
|
||||
#define DISP_CC_MDSS_BYTE1_INTF_CLK 11
|
||||
#define DISP_CC_MDSS_DPTX0_AUX_CLK 12
|
||||
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13
|
||||
#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 14
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_CLK 15
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22
|
||||
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 23
|
||||
#define DISP_CC_MDSS_DPTX1_AUX_CLK 24
|
||||
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 25
|
||||
#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 26
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_CLK 27
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 28
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 29
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 30
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 31
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 32
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 33
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 34
|
||||
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 35
|
||||
#define DISP_CC_MDSS_DPTX2_AUX_CLK 36
|
||||
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 37
|
||||
#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 38
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_CLK 39
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46
|
||||
#define DISP_CC_MDSS_DPTX3_AUX_CLK 47
|
||||
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48
|
||||
#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 49
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_CLK 50
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 51
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 52
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 53
|
||||
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 54
|
||||
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 55
|
||||
#define DISP_CC_MDSS_ESC0_CLK 56
|
||||
#define DISP_CC_MDSS_ESC0_CLK_SRC 57
|
||||
#define DISP_CC_MDSS_ESC1_CLK 58
|
||||
#define DISP_CC_MDSS_ESC1_CLK_SRC 59
|
||||
#define DISP_CC_MDSS_MDP1_CLK 60
|
||||
#define DISP_CC_MDSS_MDP_CLK 61
|
||||
#define DISP_CC_MDSS_MDP_CLK_SRC 62
|
||||
#define DISP_CC_MDSS_MDP_LUT1_CLK 63
|
||||
#define DISP_CC_MDSS_MDP_LUT_CLK 64
|
||||
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 65
|
||||
#define DISP_CC_MDSS_PCLK0_CLK 66
|
||||
#define DISP_CC_MDSS_PCLK0_CLK_SRC 67
|
||||
#define DISP_CC_MDSS_PCLK1_CLK 68
|
||||
#define DISP_CC_MDSS_PCLK1_CLK_SRC 69
|
||||
#define DISP_CC_MDSS_RSCC_AHB_CLK 70
|
||||
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 71
|
||||
#define DISP_CC_MDSS_VSYNC1_CLK 72
|
||||
#define DISP_CC_MDSS_VSYNC_CLK 73
|
||||
#define DISP_CC_MDSS_VSYNC_CLK_SRC 74
|
||||
#define DISP_CC_PLL0 75
|
||||
#define DISP_CC_PLL1 76
|
||||
#define DISP_CC_SLEEP_CLK 77
|
||||
#define DISP_CC_SLEEP_CLK_SRC 78
|
||||
#define DISP_CC_XO_CLK 79
|
||||
#define DISP_CC_XO_CLK_SRC 80
|
||||
|
||||
/* DISP_CC resets */
|
||||
#define DISP_CC_MDSS_CORE_BCR 0
|
||||
#define DISP_CC_MDSS_CORE_INT2_BCR 1
|
||||
#define DISP_CC_MDSS_RSCC_BCR 2
|
||||
|
||||
/* DISP_CC GDSCR */
|
||||
#define MDSS_GDSC 0
|
||||
#define MDSS_INT2_GDSC 1
|
||||
|
||||
#endif
|
||||
254
include/dt-bindings/clock/qcom,sm8650-gcc.h
Normal file
254
include/dt-bindings/clock/qcom,sm8650-gcc.h
Normal file
|
|
@ -0,0 +1,254 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8650_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GCC_SM8650_H
|
||||
|
||||
/* GCC clocks */
|
||||
#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0
|
||||
#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
|
||||
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2
|
||||
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
|
||||
#define GCC_BOOT_ROM_AHB_CLK 4
|
||||
#define GCC_CAMERA_AHB_CLK 5
|
||||
#define GCC_CAMERA_HF_AXI_CLK 6
|
||||
#define GCC_CAMERA_SF_AXI_CLK 7
|
||||
#define GCC_CAMERA_XO_CLK 8
|
||||
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9
|
||||
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10
|
||||
#define GCC_CNOC_PCIE_SF_AXI_CLK 11
|
||||
#define GCC_DDRSS_GPU_AXI_CLK 12
|
||||
#define GCC_DDRSS_PCIE_SF_QTB_CLK 13
|
||||
#define GCC_DISP_AHB_CLK 14
|
||||
#define GCC_DISP_HF_AXI_CLK 15
|
||||
#define GCC_DISP_XO_CLK 16
|
||||
#define GCC_GP1_CLK 17
|
||||
#define GCC_GP1_CLK_SRC 18
|
||||
#define GCC_GP2_CLK 19
|
||||
#define GCC_GP2_CLK_SRC 20
|
||||
#define GCC_GP3_CLK 21
|
||||
#define GCC_GP3_CLK_SRC 22
|
||||
#define GCC_GPLL0 23
|
||||
#define GCC_GPLL0_OUT_EVEN 24
|
||||
#define GCC_GPLL1 25
|
||||
#define GCC_GPLL3 26
|
||||
#define GCC_GPLL4 27
|
||||
#define GCC_GPLL6 28
|
||||
#define GCC_GPLL7 29
|
||||
#define GCC_GPLL9 30
|
||||
#define GCC_GPU_CFG_AHB_CLK 31
|
||||
#define GCC_GPU_GPLL0_CLK_SRC 32
|
||||
#define GCC_GPU_GPLL0_DIV_CLK_SRC 33
|
||||
#define GCC_GPU_MEMNOC_GFX_CLK 34
|
||||
#define GCC_GPU_SNOC_DVM_GFX_CLK 35
|
||||
#define GCC_PCIE_0_AUX_CLK 36
|
||||
#define GCC_PCIE_0_AUX_CLK_SRC 37
|
||||
#define GCC_PCIE_0_CFG_AHB_CLK 38
|
||||
#define GCC_PCIE_0_MSTR_AXI_CLK 39
|
||||
#define GCC_PCIE_0_PHY_RCHNG_CLK 40
|
||||
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 41
|
||||
#define GCC_PCIE_0_PIPE_CLK 42
|
||||
#define GCC_PCIE_0_PIPE_CLK_SRC 43
|
||||
#define GCC_PCIE_0_SLV_AXI_CLK 44
|
||||
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45
|
||||
#define GCC_PCIE_1_AUX_CLK 46
|
||||
#define GCC_PCIE_1_AUX_CLK_SRC 47
|
||||
#define GCC_PCIE_1_CFG_AHB_CLK 48
|
||||
#define GCC_PCIE_1_MSTR_AXI_CLK 49
|
||||
#define GCC_PCIE_1_PHY_AUX_CLK 50
|
||||
#define GCC_PCIE_1_PHY_AUX_CLK_SRC 51
|
||||
#define GCC_PCIE_1_PHY_RCHNG_CLK 52
|
||||
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 53
|
||||
#define GCC_PCIE_1_PIPE_CLK 54
|
||||
#define GCC_PCIE_1_PIPE_CLK_SRC 55
|
||||
#define GCC_PCIE_1_SLV_AXI_CLK 56
|
||||
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 57
|
||||
#define GCC_PDM2_CLK 58
|
||||
#define GCC_PDM2_CLK_SRC 59
|
||||
#define GCC_PDM_AHB_CLK 60
|
||||
#define GCC_PDM_XO4_CLK 61
|
||||
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 62
|
||||
#define GCC_QMIP_CAMERA_RT_AHB_CLK 63
|
||||
#define GCC_QMIP_DISP_AHB_CLK 64
|
||||
#define GCC_QMIP_GPU_AHB_CLK 65
|
||||
#define GCC_QMIP_PCIE_AHB_CLK 66
|
||||
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 67
|
||||
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 68
|
||||
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 69
|
||||
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 70
|
||||
#define GCC_QUPV3_I2C_CORE_CLK 71
|
||||
#define GCC_QUPV3_I2C_S0_CLK 72
|
||||
#define GCC_QUPV3_I2C_S0_CLK_SRC 73
|
||||
#define GCC_QUPV3_I2C_S1_CLK 74
|
||||
#define GCC_QUPV3_I2C_S1_CLK_SRC 75
|
||||
#define GCC_QUPV3_I2C_S2_CLK 76
|
||||
#define GCC_QUPV3_I2C_S2_CLK_SRC 77
|
||||
#define GCC_QUPV3_I2C_S3_CLK 78
|
||||
#define GCC_QUPV3_I2C_S3_CLK_SRC 79
|
||||
#define GCC_QUPV3_I2C_S4_CLK 80
|
||||
#define GCC_QUPV3_I2C_S4_CLK_SRC 81
|
||||
#define GCC_QUPV3_I2C_S5_CLK 82
|
||||
#define GCC_QUPV3_I2C_S5_CLK_SRC 83
|
||||
#define GCC_QUPV3_I2C_S6_CLK 84
|
||||
#define GCC_QUPV3_I2C_S6_CLK_SRC 85
|
||||
#define GCC_QUPV3_I2C_S7_CLK 86
|
||||
#define GCC_QUPV3_I2C_S7_CLK_SRC 87
|
||||
#define GCC_QUPV3_I2C_S8_CLK 88
|
||||
#define GCC_QUPV3_I2C_S8_CLK_SRC 89
|
||||
#define GCC_QUPV3_I2C_S9_CLK 90
|
||||
#define GCC_QUPV3_I2C_S9_CLK_SRC 91
|
||||
#define GCC_QUPV3_I2C_S_AHB_CLK 92
|
||||
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 93
|
||||
#define GCC_QUPV3_WRAP1_CORE_CLK 94
|
||||
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 95
|
||||
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 96
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK 97
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 98
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK 99
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 100
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK 101
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 102
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK 103
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 104
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK 105
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 106
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK 107
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 108
|
||||
#define GCC_QUPV3_WRAP1_S6_CLK 109
|
||||
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 110
|
||||
#define GCC_QUPV3_WRAP1_S7_CLK 111
|
||||
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 112
|
||||
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 113
|
||||
#define GCC_QUPV3_WRAP2_CORE_CLK 114
|
||||
#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC 115
|
||||
#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK 116
|
||||
#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK 117
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK 118
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 119
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK 120
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 121
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK 122
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 123
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK 124
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 125
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK 126
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 127
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK 128
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 129
|
||||
#define GCC_QUPV3_WRAP2_S6_CLK 130
|
||||
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 131
|
||||
#define GCC_QUPV3_WRAP2_S7_CLK 132
|
||||
#define GCC_QUPV3_WRAP2_S7_CLK_SRC 133
|
||||
#define GCC_QUPV3_WRAP3_CORE_2X_CLK 134
|
||||
#define GCC_QUPV3_WRAP3_CORE_CLK 135
|
||||
#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 136
|
||||
#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 137
|
||||
#define GCC_QUPV3_WRAP3_S0_CLK 138
|
||||
#define GCC_QUPV3_WRAP3_S0_CLK_SRC 139
|
||||
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 140
|
||||
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 141
|
||||
#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK 142
|
||||
#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK 143
|
||||
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 144
|
||||
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 145
|
||||
#define GCC_QUPV3_WRAP_3_M_AHB_CLK 146
|
||||
#define GCC_QUPV3_WRAP_3_S_AHB_CLK 147
|
||||
#define GCC_SDCC2_AHB_CLK 148
|
||||
#define GCC_SDCC2_APPS_CLK 149
|
||||
#define GCC_SDCC2_APPS_CLK_SRC 150
|
||||
#define GCC_SDCC4_AHB_CLK 151
|
||||
#define GCC_SDCC4_APPS_CLK 152
|
||||
#define GCC_SDCC4_APPS_CLK_SRC 153
|
||||
#define GCC_UFS_PHY_AHB_CLK 154
|
||||
#define GCC_UFS_PHY_AXI_CLK 155
|
||||
#define GCC_UFS_PHY_AXI_CLK_SRC 156
|
||||
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 157
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK 158
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 159
|
||||
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 160
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK 161
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 162
|
||||
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 163
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 165
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 166
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 167
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 169
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 170
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 171
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 172
|
||||
#define GCC_USB30_PRIM_MASTER_CLK 173
|
||||
#define GCC_USB30_PRIM_MASTER_CLK_SRC 174
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177
|
||||
#define GCC_USB30_PRIM_SLEEP_CLK 178
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK 179
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 180
|
||||
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 181
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK 182
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 183
|
||||
#define GCC_VIDEO_AHB_CLK 184
|
||||
#define GCC_VIDEO_AXI0_CLK 185
|
||||
#define GCC_VIDEO_AXI1_CLK 186
|
||||
#define GCC_VIDEO_XO_CLK 187
|
||||
#define GCC_GPLL0_AO 188
|
||||
#define GCC_GPLL0_OUT_EVEN_AO 189
|
||||
#define GCC_GPLL1_AO 190
|
||||
#define GCC_GPLL3_AO 191
|
||||
#define GCC_GPLL4_AO 192
|
||||
#define GCC_GPLL6_AO 193
|
||||
|
||||
/* GCC resets */
|
||||
#define GCC_CAMERA_BCR 0
|
||||
#define GCC_DISPLAY_BCR 1
|
||||
#define GCC_GPU_BCR 2
|
||||
#define GCC_PCIE_0_BCR 3
|
||||
#define GCC_PCIE_0_LINK_DOWN_BCR 4
|
||||
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
|
||||
#define GCC_PCIE_0_PHY_BCR 6
|
||||
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
|
||||
#define GCC_PCIE_1_BCR 8
|
||||
#define GCC_PCIE_1_LINK_DOWN_BCR 9
|
||||
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10
|
||||
#define GCC_PCIE_1_PHY_BCR 11
|
||||
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12
|
||||
#define GCC_PCIE_PHY_BCR 13
|
||||
#define GCC_PCIE_PHY_CFG_AHB_BCR 14
|
||||
#define GCC_PCIE_PHY_COM_BCR 15
|
||||
#define GCC_PDM_BCR 16
|
||||
#define GCC_QUPV3_WRAPPER_1_BCR 17
|
||||
#define GCC_QUPV3_WRAPPER_2_BCR 18
|
||||
#define GCC_QUPV3_WRAPPER_3_BCR 19
|
||||
#define GCC_QUPV3_WRAPPER_I2C_BCR 20
|
||||
#define GCC_QUSB2PHY_PRIM_BCR 21
|
||||
#define GCC_QUSB2PHY_SEC_BCR 22
|
||||
#define GCC_SDCC2_BCR 23
|
||||
#define GCC_SDCC4_BCR 24
|
||||
#define GCC_UFS_PHY_BCR 25
|
||||
#define GCC_USB30_PRIM_BCR 26
|
||||
#define GCC_USB3_DP_PHY_PRIM_BCR 27
|
||||
#define GCC_USB3_DP_PHY_SEC_BCR 28
|
||||
#define GCC_USB3_PHY_PRIM_BCR 29
|
||||
#define GCC_USB3_PHY_SEC_BCR 30
|
||||
#define GCC_USB3PHY_PHY_PRIM_BCR 31
|
||||
#define GCC_USB3PHY_PHY_SEC_BCR 32
|
||||
#define GCC_VIDEO_AXI0_CLK_ARES 33
|
||||
#define GCC_VIDEO_AXI1_CLK_ARES 34
|
||||
#define GCC_VIDEO_BCR 35
|
||||
|
||||
/* GCC power domains */
|
||||
#define PCIE_0_GDSC 0
|
||||
#define PCIE_0_PHY_GDSC 1
|
||||
#define PCIE_1_GDSC 2
|
||||
#define PCIE_1_PHY_GDSC 3
|
||||
#define UFS_PHY_GDSC 4
|
||||
#define UFS_MEM_PHY_GDSC 5
|
||||
#define USB30_PRIM_GDSC 6
|
||||
#define USB3_PHY_GDSC 7
|
||||
|
||||
#endif
|
||||
43
include/dt-bindings/clock/qcom,sm8650-gpucc.h
Normal file
43
include/dt-bindings/clock/qcom,sm8650-gpucc.h
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8650_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8650_H
|
||||
|
||||
/* GPU_CC clocks */
|
||||
#define GPU_CC_AHB_CLK 0
|
||||
#define GPU_CC_CRC_AHB_CLK 1
|
||||
#define GPU_CC_CX_ACCU_SHIFT_CLK 2
|
||||
#define GPU_CC_CX_FF_CLK 3
|
||||
#define GPU_CC_CX_GMU_CLK 4
|
||||
#define GPU_CC_CXO_AON_CLK 5
|
||||
#define GPU_CC_CXO_CLK 6
|
||||
#define GPU_CC_DEMET_CLK 7
|
||||
#define GPU_CC_DPM_CLK 8
|
||||
#define GPU_CC_FF_CLK_SRC 9
|
||||
#define GPU_CC_FREQ_MEASURE_CLK 10
|
||||
#define GPU_CC_GMU_CLK_SRC 11
|
||||
#define GPU_CC_GX_ACCU_SHIFT_CLK 12
|
||||
#define GPU_CC_GX_FF_CLK 13
|
||||
#define GPU_CC_GX_GFX3D_CLK 14
|
||||
#define GPU_CC_GX_GFX3D_RDVM_CLK 15
|
||||
#define GPU_CC_GX_GMU_CLK 16
|
||||
#define GPU_CC_GX_VSENSE_CLK 17
|
||||
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18
|
||||
#define GPU_CC_HUB_AON_CLK 19
|
||||
#define GPU_CC_HUB_CLK_SRC 20
|
||||
#define GPU_CC_HUB_CX_INT_CLK 21
|
||||
#define GPU_CC_HUB_DIV_CLK_SRC 22
|
||||
#define GPU_CC_MEMNOC_GFX_CLK 23
|
||||
#define GPU_CC_PLL0 24
|
||||
#define GPU_CC_PLL1 25
|
||||
#define GPU_CC_SLEEP_CLK 26
|
||||
|
||||
/* GDSCs */
|
||||
#define GPU_GX_GDSC 0
|
||||
#define GPU_CX_GDSC 1
|
||||
|
||||
#endif
|
||||
18
include/dt-bindings/clock/qcom,sm8650-tcsr.h
Normal file
18
include/dt-bindings/clock/qcom,sm8650-tcsr.h
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8650_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8650_H
|
||||
|
||||
/* TCSR CC clocks */
|
||||
#define TCSR_PCIE_0_CLKREF_EN 0
|
||||
#define TCSR_PCIE_1_CLKREF_EN 1
|
||||
#define TCSR_UFS_CLKREF_EN 2
|
||||
#define TCSR_UFS_PAD_CLKREF_EN 3
|
||||
#define TCSR_USB2_CLKREF_EN 4
|
||||
#define TCSR_USB3_CLKREF_EN 5
|
||||
|
||||
#endif
|
||||
|
|
@ -16,6 +16,10 @@
|
|||
|
||||
/* VIDEO_CC Resets */
|
||||
#define VIDEO_CC_MVSC_CORE_CLK_BCR 0
|
||||
#define VIDEO_CC_INTERFACE_BCR 1
|
||||
#define VIDEO_CC_MVS0_BCR 2
|
||||
#define VIDEO_CC_MVS1_BCR 3
|
||||
#define VIDEO_CC_MVSC_BCR 4
|
||||
|
||||
/* VIDEO_CC GDSCRs */
|
||||
#define VENUS_GDSC 0
|
||||
|
|
|
|||
485
include/dt-bindings/clock/qcom,x1e80100-gcc.h
Normal file
485
include/dt-bindings/clock/qcom,x1e80100-gcc.h
Normal file
|
|
@ -0,0 +1,485 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_X1E80100_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GCC_X1E80100_H
|
||||
|
||||
/* GCC clocks */
|
||||
#define GCC_AGGRE_NOC_USB_NORTH_AXI_CLK 0
|
||||
#define GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK 1
|
||||
#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
|
||||
#define GCC_AGGRE_USB2_PRIM_AXI_CLK 3
|
||||
#define GCC_AGGRE_USB3_MP_AXI_CLK 4
|
||||
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5
|
||||
#define GCC_AGGRE_USB3_SEC_AXI_CLK 6
|
||||
#define GCC_AGGRE_USB3_TERT_AXI_CLK 7
|
||||
#define GCC_AGGRE_USB4_0_AXI_CLK 8
|
||||
#define GCC_AGGRE_USB4_1_AXI_CLK 9
|
||||
#define GCC_AGGRE_USB4_2_AXI_CLK 10
|
||||
#define GCC_AGGRE_USB_NOC_AXI_CLK 11
|
||||
#define GCC_AV1E_AHB_CLK 12
|
||||
#define GCC_AV1E_AXI_CLK 13
|
||||
#define GCC_AV1E_XO_CLK 14
|
||||
#define GCC_BOOT_ROM_AHB_CLK 15
|
||||
#define GCC_CAMERA_AHB_CLK 16
|
||||
#define GCC_CAMERA_HF_AXI_CLK 17
|
||||
#define GCC_CAMERA_SF_AXI_CLK 18
|
||||
#define GCC_CAMERA_XO_CLK 19
|
||||
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 20
|
||||
#define GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK 21
|
||||
#define GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK 22
|
||||
#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 23
|
||||
#define GCC_CFG_NOC_USB3_MP_AXI_CLK 24
|
||||
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 25
|
||||
#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 26
|
||||
#define GCC_CFG_NOC_USB3_TERT_AXI_CLK 27
|
||||
#define GCC_CFG_NOC_USB_ANOC_AHB_CLK 28
|
||||
#define GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK 29
|
||||
#define GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK 30
|
||||
#define GCC_CNOC_PCIE1_TUNNEL_CLK 31
|
||||
#define GCC_CNOC_PCIE2_TUNNEL_CLK 32
|
||||
#define GCC_CNOC_PCIE_NORTH_SF_AXI_CLK 33
|
||||
#define GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK 34
|
||||
#define GCC_CNOC_PCIE_TUNNEL_CLK 35
|
||||
#define GCC_DDRSS_GPU_AXI_CLK 36
|
||||
#define GCC_DISP_AHB_CLK 37
|
||||
#define GCC_DISP_HF_AXI_CLK 38
|
||||
#define GCC_DISP_XO_CLK 39
|
||||
#define GCC_GP1_CLK 40
|
||||
#define GCC_GP1_CLK_SRC 41
|
||||
#define GCC_GP2_CLK 42
|
||||
#define GCC_GP2_CLK_SRC 43
|
||||
#define GCC_GP3_CLK 44
|
||||
#define GCC_GP3_CLK_SRC 45
|
||||
#define GCC_GPLL0 46
|
||||
#define GCC_GPLL0_OUT_EVEN 47
|
||||
#define GCC_GPLL4 48
|
||||
#define GCC_GPLL7 49
|
||||
#define GCC_GPLL8 50
|
||||
#define GCC_GPLL9 51
|
||||
#define GCC_GPU_CFG_AHB_CLK 52
|
||||
#define GCC_GPU_GPLL0_CPH_CLK_SRC 53
|
||||
#define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC 54
|
||||
#define GCC_GPU_MEMNOC_GFX_CLK 55
|
||||
#define GCC_GPU_SNOC_DVM_GFX_CLK 56
|
||||
#define GCC_PCIE0_PHY_RCHNG_CLK 57
|
||||
#define GCC_PCIE1_PHY_RCHNG_CLK 58
|
||||
#define GCC_PCIE2_PHY_RCHNG_CLK 59
|
||||
#define GCC_PCIE_0_AUX_CLK 60
|
||||
#define GCC_PCIE_0_AUX_CLK_SRC 61
|
||||
#define GCC_PCIE_0_CFG_AHB_CLK 62
|
||||
#define GCC_PCIE_0_MSTR_AXI_CLK 63
|
||||
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 64
|
||||
#define GCC_PCIE_0_PIPE_CLK 65
|
||||
#define GCC_PCIE_0_SLV_AXI_CLK 66
|
||||
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 67
|
||||
#define GCC_PCIE_1_AUX_CLK 68
|
||||
#define GCC_PCIE_1_AUX_CLK_SRC 69
|
||||
#define GCC_PCIE_1_CFG_AHB_CLK 70
|
||||
#define GCC_PCIE_1_MSTR_AXI_CLK 71
|
||||
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 72
|
||||
#define GCC_PCIE_1_PIPE_CLK 73
|
||||
#define GCC_PCIE_1_SLV_AXI_CLK 74
|
||||
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 75
|
||||
#define GCC_PCIE_2_AUX_CLK 76
|
||||
#define GCC_PCIE_2_AUX_CLK_SRC 77
|
||||
#define GCC_PCIE_2_CFG_AHB_CLK 78
|
||||
#define GCC_PCIE_2_MSTR_AXI_CLK 79
|
||||
#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 80
|
||||
#define GCC_PCIE_2_PIPE_CLK 81
|
||||
#define GCC_PCIE_2_SLV_AXI_CLK 82
|
||||
#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 83
|
||||
#define GCC_PCIE_3_AUX_CLK 84
|
||||
#define GCC_PCIE_3_AUX_CLK_SRC 85
|
||||
#define GCC_PCIE_3_CFG_AHB_CLK 86
|
||||
#define GCC_PCIE_3_MSTR_AXI_CLK 87
|
||||
#define GCC_PCIE_3_PHY_AUX_CLK 88
|
||||
#define GCC_PCIE_3_PHY_RCHNG_CLK 89
|
||||
#define GCC_PCIE_3_PHY_RCHNG_CLK_SRC 90
|
||||
#define GCC_PCIE_3_PIPE_CLK 91
|
||||
#define GCC_PCIE_3_PIPE_DIV_CLK_SRC 92
|
||||
#define GCC_PCIE_3_PIPEDIV2_CLK 93
|
||||
#define GCC_PCIE_3_SLV_AXI_CLK 94
|
||||
#define GCC_PCIE_3_SLV_Q2A_AXI_CLK 95
|
||||
#define GCC_PCIE_4_AUX_CLK 96
|
||||
#define GCC_PCIE_4_AUX_CLK_SRC 97
|
||||
#define GCC_PCIE_4_CFG_AHB_CLK 98
|
||||
#define GCC_PCIE_4_MSTR_AXI_CLK 99
|
||||
#define GCC_PCIE_4_PHY_RCHNG_CLK 100
|
||||
#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 101
|
||||
#define GCC_PCIE_4_PIPE_CLK 102
|
||||
#define GCC_PCIE_4_PIPE_DIV_CLK_SRC 103
|
||||
#define GCC_PCIE_4_PIPEDIV2_CLK 104
|
||||
#define GCC_PCIE_4_SLV_AXI_CLK 105
|
||||
#define GCC_PCIE_4_SLV_Q2A_AXI_CLK 106
|
||||
#define GCC_PCIE_5_AUX_CLK 107
|
||||
#define GCC_PCIE_5_AUX_CLK_SRC 108
|
||||
#define GCC_PCIE_5_CFG_AHB_CLK 109
|
||||
#define GCC_PCIE_5_MSTR_AXI_CLK 110
|
||||
#define GCC_PCIE_5_PHY_RCHNG_CLK 111
|
||||
#define GCC_PCIE_5_PHY_RCHNG_CLK_SRC 112
|
||||
#define GCC_PCIE_5_PIPE_CLK 113
|
||||
#define GCC_PCIE_5_PIPE_DIV_CLK_SRC 114
|
||||
#define GCC_PCIE_5_PIPEDIV2_CLK 115
|
||||
#define GCC_PCIE_5_SLV_AXI_CLK 116
|
||||
#define GCC_PCIE_5_SLV_Q2A_AXI_CLK 117
|
||||
#define GCC_PCIE_6A_AUX_CLK 118
|
||||
#define GCC_PCIE_6A_AUX_CLK_SRC 119
|
||||
#define GCC_PCIE_6A_CFG_AHB_CLK 120
|
||||
#define GCC_PCIE_6A_MSTR_AXI_CLK 121
|
||||
#define GCC_PCIE_6A_PHY_AUX_CLK 122
|
||||
#define GCC_PCIE_6A_PHY_RCHNG_CLK 123
|
||||
#define GCC_PCIE_6A_PHY_RCHNG_CLK_SRC 124
|
||||
#define GCC_PCIE_6A_PIPE_CLK 125
|
||||
#define GCC_PCIE_6A_PIPE_DIV_CLK_SRC 126
|
||||
#define GCC_PCIE_6A_PIPEDIV2_CLK 127
|
||||
#define GCC_PCIE_6A_SLV_AXI_CLK 128
|
||||
#define GCC_PCIE_6A_SLV_Q2A_AXI_CLK 129
|
||||
#define GCC_PCIE_6B_AUX_CLK 130
|
||||
#define GCC_PCIE_6B_AUX_CLK_SRC 131
|
||||
#define GCC_PCIE_6B_CFG_AHB_CLK 132
|
||||
#define GCC_PCIE_6B_MSTR_AXI_CLK 133
|
||||
#define GCC_PCIE_6B_PHY_AUX_CLK 134
|
||||
#define GCC_PCIE_6B_PHY_RCHNG_CLK 135
|
||||
#define GCC_PCIE_6B_PHY_RCHNG_CLK_SRC 136
|
||||
#define GCC_PCIE_6B_PIPE_CLK 137
|
||||
#define GCC_PCIE_6B_PIPE_DIV_CLK_SRC 138
|
||||
#define GCC_PCIE_6B_PIPEDIV2_CLK 139
|
||||
#define GCC_PCIE_6B_SLV_AXI_CLK 140
|
||||
#define GCC_PCIE_6B_SLV_Q2A_AXI_CLK 141
|
||||
#define GCC_PCIE_RSCC_AHB_CLK 142
|
||||
#define GCC_PCIE_RSCC_XO_CLK 143
|
||||
#define GCC_PCIE_RSCC_XO_CLK_SRC 144
|
||||
#define GCC_PDM2_CLK 145
|
||||
#define GCC_PDM2_CLK_SRC 146
|
||||
#define GCC_PDM_AHB_CLK 147
|
||||
#define GCC_PDM_XO4_CLK 148
|
||||
#define GCC_QMIP_AV1E_AHB_CLK 149
|
||||
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 150
|
||||
#define GCC_QMIP_CAMERA_RT_AHB_CLK 151
|
||||
#define GCC_QMIP_DISP_AHB_CLK 152
|
||||
#define GCC_QMIP_GPU_AHB_CLK 153
|
||||
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 154
|
||||
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 155
|
||||
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 156
|
||||
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 157
|
||||
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 158
|
||||
#define GCC_QUPV3_WRAP0_CORE_CLK 159
|
||||
#define GCC_QUPV3_WRAP0_QSPI_S2_CLK 160
|
||||
#define GCC_QUPV3_WRAP0_QSPI_S3_CLK 161
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK 162
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 163
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK 164
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 165
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK 166
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 167
|
||||
#define GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC 168
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK 169
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 170
|
||||
#define GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC 171
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK 172
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 173
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK 174
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 175
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK 176
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 177
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK 178
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 179
|
||||
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 180
|
||||
#define GCC_QUPV3_WRAP1_CORE_CLK 181
|
||||
#define GCC_QUPV3_WRAP1_QSPI_S2_CLK 182
|
||||
#define GCC_QUPV3_WRAP1_QSPI_S3_CLK 183
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK 184
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 185
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK 186
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 187
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK 188
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 189
|
||||
#define GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC 190
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK 191
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 192
|
||||
#define GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC 193
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK 194
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 195
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK 196
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 197
|
||||
#define GCC_QUPV3_WRAP1_S6_CLK 198
|
||||
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 199
|
||||
#define GCC_QUPV3_WRAP1_S7_CLK 200
|
||||
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 201
|
||||
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 202
|
||||
#define GCC_QUPV3_WRAP2_CORE_CLK 203
|
||||
#define GCC_QUPV3_WRAP2_QSPI_S2_CLK 204
|
||||
#define GCC_QUPV3_WRAP2_QSPI_S3_CLK 205
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK 206
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 207
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK 208
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 209
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK 210
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 211
|
||||
#define GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC 212
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK 213
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 214
|
||||
#define GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC 215
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK 216
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 217
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK 218
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 219
|
||||
#define GCC_QUPV3_WRAP2_S6_CLK 220
|
||||
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 221
|
||||
#define GCC_QUPV3_WRAP2_S7_CLK 222
|
||||
#define GCC_QUPV3_WRAP2_S7_CLK_SRC 223
|
||||
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 224
|
||||
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 225
|
||||
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 226
|
||||
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 227
|
||||
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 228
|
||||
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 229
|
||||
#define GCC_SDCC2_AHB_CLK 230
|
||||
#define GCC_SDCC2_APPS_CLK 231
|
||||
#define GCC_SDCC2_APPS_CLK_SRC 232
|
||||
#define GCC_SDCC4_AHB_CLK 233
|
||||
#define GCC_SDCC4_APPS_CLK 234
|
||||
#define GCC_SDCC4_APPS_CLK_SRC 235
|
||||
#define GCC_SYS_NOC_USB_AXI_CLK 236
|
||||
#define GCC_UFS_PHY_AHB_CLK 237
|
||||
#define GCC_UFS_PHY_AXI_CLK 238
|
||||
#define GCC_UFS_PHY_AXI_CLK_SRC 239
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK 240
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 241
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK 242
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 243
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 244
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 245
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 246
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 247
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 248
|
||||
#define GCC_USB20_MASTER_CLK 249
|
||||
#define GCC_USB20_MASTER_CLK_SRC 250
|
||||
#define GCC_USB20_MOCK_UTMI_CLK 251
|
||||
#define GCC_USB20_MOCK_UTMI_CLK_SRC 252
|
||||
#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 253
|
||||
#define GCC_USB20_SLEEP_CLK 254
|
||||
#define GCC_USB30_MP_MASTER_CLK 255
|
||||
#define GCC_USB30_MP_MASTER_CLK_SRC 256
|
||||
#define GCC_USB30_MP_MOCK_UTMI_CLK 257
|
||||
#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 258
|
||||
#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 259
|
||||
#define GCC_USB30_MP_SLEEP_CLK 260
|
||||
#define GCC_USB30_PRIM_MASTER_CLK 261
|
||||
#define GCC_USB30_PRIM_MASTER_CLK_SRC 262
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 263
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 264
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 265
|
||||
#define GCC_USB30_PRIM_SLEEP_CLK 266
|
||||
#define GCC_USB30_SEC_MASTER_CLK 267
|
||||
#define GCC_USB30_SEC_MASTER_CLK_SRC 268
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_CLK 269
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 270
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 271
|
||||
#define GCC_USB30_SEC_SLEEP_CLK 272
|
||||
#define GCC_USB30_TERT_MASTER_CLK 273
|
||||
#define GCC_USB30_TERT_MASTER_CLK_SRC 274
|
||||
#define GCC_USB30_TERT_MOCK_UTMI_CLK 275
|
||||
#define GCC_USB30_TERT_MOCK_UTMI_CLK_SRC 276
|
||||
#define GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC 277
|
||||
#define GCC_USB30_TERT_SLEEP_CLK 278
|
||||
#define GCC_USB3_MP_PHY_AUX_CLK 279
|
||||
#define GCC_USB3_MP_PHY_AUX_CLK_SRC 280
|
||||
#define GCC_USB3_MP_PHY_COM_AUX_CLK 281
|
||||
#define GCC_USB3_MP_PHY_PIPE_0_CLK 282
|
||||
#define GCC_USB3_MP_PHY_PIPE_1_CLK 283
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK 284
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 285
|
||||
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 286
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK 287
|
||||
#define GCC_USB3_SEC_PHY_AUX_CLK 288
|
||||
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 289
|
||||
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 290
|
||||
#define GCC_USB3_SEC_PHY_PIPE_CLK 291
|
||||
#define GCC_USB3_TERT_PHY_AUX_CLK 292
|
||||
#define GCC_USB3_TERT_PHY_AUX_CLK_SRC 293
|
||||
#define GCC_USB3_TERT_PHY_COM_AUX_CLK 294
|
||||
#define GCC_USB3_TERT_PHY_PIPE_CLK 295
|
||||
#define GCC_USB4_0_CFG_AHB_CLK 296
|
||||
#define GCC_USB4_0_DP0_CLK 297
|
||||
#define GCC_USB4_0_DP1_CLK 298
|
||||
#define GCC_USB4_0_MASTER_CLK 299
|
||||
#define GCC_USB4_0_MASTER_CLK_SRC 300
|
||||
#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK 301
|
||||
#define GCC_USB4_0_PHY_PCIE_PIPE_CLK 302
|
||||
#define GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC 303
|
||||
#define GCC_USB4_0_PHY_RX0_CLK 304
|
||||
#define GCC_USB4_0_PHY_RX1_CLK 305
|
||||
#define GCC_USB4_0_PHY_USB_PIPE_CLK 306
|
||||
#define GCC_USB4_0_SB_IF_CLK 307
|
||||
#define GCC_USB4_0_SB_IF_CLK_SRC 308
|
||||
#define GCC_USB4_0_SYS_CLK 309
|
||||
#define GCC_USB4_0_TMU_CLK 310
|
||||
#define GCC_USB4_0_TMU_CLK_SRC 311
|
||||
#define GCC_USB4_1_CFG_AHB_CLK 312
|
||||
#define GCC_USB4_1_DP0_CLK 313
|
||||
#define GCC_USB4_1_DP1_CLK 314
|
||||
#define GCC_USB4_1_MASTER_CLK 315
|
||||
#define GCC_USB4_1_MASTER_CLK_SRC 316
|
||||
#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 317
|
||||
#define GCC_USB4_1_PHY_PCIE_PIPE_CLK 318
|
||||
#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 319
|
||||
#define GCC_USB4_1_PHY_RX0_CLK 320
|
||||
#define GCC_USB4_1_PHY_RX1_CLK 321
|
||||
#define GCC_USB4_1_PHY_USB_PIPE_CLK 322
|
||||
#define GCC_USB4_1_SB_IF_CLK 323
|
||||
#define GCC_USB4_1_SB_IF_CLK_SRC 324
|
||||
#define GCC_USB4_1_SYS_CLK 325
|
||||
#define GCC_USB4_1_TMU_CLK 326
|
||||
#define GCC_USB4_1_TMU_CLK_SRC 327
|
||||
#define GCC_USB4_2_CFG_AHB_CLK 328
|
||||
#define GCC_USB4_2_DP0_CLK 329
|
||||
#define GCC_USB4_2_DP1_CLK 330
|
||||
#define GCC_USB4_2_MASTER_CLK 331
|
||||
#define GCC_USB4_2_MASTER_CLK_SRC 332
|
||||
#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK 333
|
||||
#define GCC_USB4_2_PHY_PCIE_PIPE_CLK 334
|
||||
#define GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC 335
|
||||
#define GCC_USB4_2_PHY_RX0_CLK 336
|
||||
#define GCC_USB4_2_PHY_RX1_CLK 337
|
||||
#define GCC_USB4_2_PHY_USB_PIPE_CLK 338
|
||||
#define GCC_USB4_2_SB_IF_CLK 339
|
||||
#define GCC_USB4_2_SB_IF_CLK_SRC 340
|
||||
#define GCC_USB4_2_SYS_CLK 341
|
||||
#define GCC_USB4_2_TMU_CLK 342
|
||||
#define GCC_USB4_2_TMU_CLK_SRC 343
|
||||
#define GCC_VIDEO_AHB_CLK 344
|
||||
#define GCC_VIDEO_AXI0_CLK 345
|
||||
#define GCC_VIDEO_AXI1_CLK 346
|
||||
#define GCC_VIDEO_XO_CLK 347
|
||||
#define GCC_PCIE_3_PIPE_CLK_SRC 348
|
||||
#define GCC_PCIE_4_PIPE_CLK_SRC 349
|
||||
#define GCC_PCIE_5_PIPE_CLK_SRC 350
|
||||
#define GCC_PCIE_6A_PIPE_CLK_SRC 351
|
||||
#define GCC_PCIE_6B_PIPE_CLK_SRC 352
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 353
|
||||
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 354
|
||||
#define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 355
|
||||
|
||||
/* GCC power domains */
|
||||
#define GCC_PCIE_0_TUNNEL_GDSC 0
|
||||
#define GCC_PCIE_1_TUNNEL_GDSC 1
|
||||
#define GCC_PCIE_2_TUNNEL_GDSC 2
|
||||
#define GCC_PCIE_3_GDSC 3
|
||||
#define GCC_PCIE_3_PHY_GDSC 4
|
||||
#define GCC_PCIE_4_GDSC 5
|
||||
#define GCC_PCIE_4_PHY_GDSC 6
|
||||
#define GCC_PCIE_5_GDSC 7
|
||||
#define GCC_PCIE_5_PHY_GDSC 8
|
||||
#define GCC_PCIE_6_PHY_GDSC 9
|
||||
#define GCC_PCIE_6A_GDSC 10
|
||||
#define GCC_PCIE_6B_GDSC 11
|
||||
#define GCC_UFS_MEM_PHY_GDSC 12
|
||||
#define GCC_UFS_PHY_GDSC 13
|
||||
#define GCC_USB20_PRIM_GDSC 14
|
||||
#define GCC_USB30_MP_GDSC 15
|
||||
#define GCC_USB30_PRIM_GDSC 16
|
||||
#define GCC_USB30_SEC_GDSC 17
|
||||
#define GCC_USB30_TERT_GDSC 18
|
||||
#define GCC_USB3_MP_SS0_PHY_GDSC 19
|
||||
#define GCC_USB3_MP_SS1_PHY_GDSC 20
|
||||
#define GCC_USB4_0_GDSC 21
|
||||
#define GCC_USB4_1_GDSC 22
|
||||
#define GCC_USB4_2_GDSC 23
|
||||
#define GCC_USB_0_PHY_GDSC 24
|
||||
#define GCC_USB_1_PHY_GDSC 25
|
||||
#define GCC_USB_2_PHY_GDSC 26
|
||||
|
||||
/* GCC resets */
|
||||
#define GCC_AV1E_BCR 0
|
||||
#define GCC_CAMERA_BCR 1
|
||||
#define GCC_DISPLAY_BCR 2
|
||||
#define GCC_GPU_BCR 3
|
||||
#define GCC_PCIE_0_LINK_DOWN_BCR 4
|
||||
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
|
||||
#define GCC_PCIE_0_PHY_BCR 6
|
||||
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
|
||||
#define GCC_PCIE_0_TUNNEL_BCR 8
|
||||
#define GCC_PCIE_1_LINK_DOWN_BCR 9
|
||||
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10
|
||||
#define GCC_PCIE_1_PHY_BCR 11
|
||||
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12
|
||||
#define GCC_PCIE_1_TUNNEL_BCR 13
|
||||
#define GCC_PCIE_2_LINK_DOWN_BCR 14
|
||||
#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 15
|
||||
#define GCC_PCIE_2_PHY_BCR 16
|
||||
#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 17
|
||||
#define GCC_PCIE_2_TUNNEL_BCR 18
|
||||
#define GCC_PCIE_3_BCR 19
|
||||
#define GCC_PCIE_3_LINK_DOWN_BCR 20
|
||||
#define GCC_PCIE_3_NOCSR_COM_PHY_BCR 21
|
||||
#define GCC_PCIE_3_PHY_BCR 22
|
||||
#define GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR 23
|
||||
#define GCC_PCIE_4_BCR 24
|
||||
#define GCC_PCIE_4_LINK_DOWN_BCR 25
|
||||
#define GCC_PCIE_4_NOCSR_COM_PHY_BCR 26
|
||||
#define GCC_PCIE_4_PHY_BCR 27
|
||||
#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 28
|
||||
#define GCC_PCIE_5_BCR 29
|
||||
#define GCC_PCIE_5_LINK_DOWN_BCR 30
|
||||
#define GCC_PCIE_5_NOCSR_COM_PHY_BCR 31
|
||||
#define GCC_PCIE_5_PHY_BCR 32
|
||||
#define GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR 33
|
||||
#define GCC_PCIE_6A_BCR 34
|
||||
#define GCC_PCIE_6A_LINK_DOWN_BCR 35
|
||||
#define GCC_PCIE_6A_NOCSR_COM_PHY_BCR 36
|
||||
#define GCC_PCIE_6A_PHY_BCR 37
|
||||
#define GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR 38
|
||||
#define GCC_PCIE_6B_BCR 39
|
||||
#define GCC_PCIE_6B_LINK_DOWN_BCR 40
|
||||
#define GCC_PCIE_6B_NOCSR_COM_PHY_BCR 41
|
||||
#define GCC_PCIE_6B_PHY_BCR 42
|
||||
#define GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR 43
|
||||
#define GCC_PCIE_PHY_BCR 44
|
||||
#define GCC_PCIE_PHY_CFG_AHB_BCR 45
|
||||
#define GCC_PCIE_PHY_COM_BCR 46
|
||||
#define GCC_PCIE_RSCC_BCR 47
|
||||
#define GCC_PDM_BCR 48
|
||||
#define GCC_QUPV3_WRAPPER_0_BCR 49
|
||||
#define GCC_QUPV3_WRAPPER_1_BCR 50
|
||||
#define GCC_QUPV3_WRAPPER_2_BCR 51
|
||||
#define GCC_QUSB2PHY_HS0_MP_BCR 52
|
||||
#define GCC_QUSB2PHY_HS1_MP_BCR 53
|
||||
#define GCC_QUSB2PHY_PRIM_BCR 54
|
||||
#define GCC_QUSB2PHY_SEC_BCR 55
|
||||
#define GCC_QUSB2PHY_TERT_BCR 56
|
||||
#define GCC_QUSB2PHY_USB20_HS_BCR 57
|
||||
#define GCC_SDCC2_BCR 58
|
||||
#define GCC_SDCC4_BCR 59
|
||||
#define GCC_UFS_PHY_BCR 60
|
||||
#define GCC_USB20_PRIM_BCR 61
|
||||
#define GCC_USB30_MP_BCR 62
|
||||
#define GCC_USB30_PRIM_BCR 63
|
||||
#define GCC_USB30_SEC_BCR 64
|
||||
#define GCC_USB30_TERT_BCR 65
|
||||
#define GCC_USB3_MP_SS0_PHY_BCR 66
|
||||
#define GCC_USB3_MP_SS1_PHY_BCR 67
|
||||
#define GCC_USB3_PHY_PRIM_BCR 68
|
||||
#define GCC_USB3_PHY_SEC_BCR 69
|
||||
#define GCC_USB3_PHY_TERT_BCR 70
|
||||
#define GCC_USB3_UNIPHY_MP0_BCR 71
|
||||
#define GCC_USB3_UNIPHY_MP1_BCR 72
|
||||
#define GCC_USB3PHY_PHY_PRIM_BCR 73
|
||||
#define GCC_USB3PHY_PHY_SEC_BCR 74
|
||||
#define GCC_USB3PHY_PHY_TERT_BCR 75
|
||||
#define GCC_USB3UNIPHY_PHY_MP0_BCR 76
|
||||
#define GCC_USB3UNIPHY_PHY_MP1_BCR 77
|
||||
#define GCC_USB4_0_BCR 78
|
||||
#define GCC_USB4_0_DP0_PHY_PRIM_BCR 79
|
||||
#define GCC_USB4_1_DP0_PHY_SEC_BCR 80
|
||||
#define GCC_USB4_2_DP0_PHY_TERT_BCR 81
|
||||
#define GCC_USB4_1_BCR 82
|
||||
#define GCC_USB4_2_BCR 83
|
||||
#define GCC_USB_0_PHY_BCR 84
|
||||
#define GCC_USB_1_PHY_BCR 85
|
||||
#define GCC_USB_2_PHY_BCR 86
|
||||
#define GCC_VIDEO_BCR 87
|
||||
#endif
|
||||
20
include/dt-bindings/reset/qcom,sm8650-gpucc.h
Normal file
20
include/dt-bindings/reset/qcom,sm8650-gpucc.h
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8650_H
|
||||
#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8650_H
|
||||
|
||||
#define GPUCC_GPU_CC_ACD_BCR 0
|
||||
#define GPUCC_GPU_CC_CX_BCR 1
|
||||
#define GPUCC_GPU_CC_FAST_HUB_BCR 2
|
||||
#define GPUCC_GPU_CC_FF_BCR 3
|
||||
#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
|
||||
#define GPUCC_GPU_CC_GMU_BCR 5
|
||||
#define GPUCC_GPU_CC_GX_BCR 6
|
||||
#define GPUCC_GPU_CC_XO_BCR 7
|
||||
#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 8
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user