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i.MX clocks changes for 6.12

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- Use clk_hw pointer instead of fw_name for acm_aud_clk[0-1]_sel clocks
   on i.MX8Q as parents in ACM provider
 - Add i.MX95 NETCMIX support to the block control provider
 - Fix parents for ENETx_REF_SEL clocks on i.MX6UL
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Merge tag 'clk-imx-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx2

Pull i.MX clk driver updates from Abel Vesa:

 - Use clk_hw pointer instead of fw_name for acm_aud_clk[0-1]_sel clocks
   on i.MX8Q as parents in ACM provider
 - Add i.MX95 NETCMIX support to the block control provider
 - Fix parents for ENETx_REF_SEL clocks on i.MX6UL

* tag 'clk-imx-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
  clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL
  clk: imx95: enable the clock of NETCMIX block control
  dt-bindings: clock: add RMII clock selection
  dt-bindings: clock: add i.MX95 NETCMIX block control
  clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data
This commit is contained in:
Stephen Boyd 2024-09-05 11:18:55 -07:00
commit 9395f3d21d
5 changed files with 65 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
View File

@ -16,6 +16,7 @@ properties:
- nxp,imx95-lvds-csr
- nxp,imx95-display-csr
- nxp,imx95-camera-csr
- nxp,imx95-netcmix-blk-ctrl
- nxp,imx95-vpu-csr
- const: syscon

4
drivers/clk/imx/clk-imx6ul.c
View File

@ -542,8 +542,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clk_set_parent(hws[IMX6UL_CLK_ENFC_SEL]->clk, hws[IMX6UL_CLK_PLL2_PFD2]->clk);
clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk);
clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk);
clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET1_REF_125M]->clk);
clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF_125M]->clk);
imx_register_uart_clocks();
}

38
drivers/clk/imx/clk-imx8-acm.c
View File

@ -54,10 +54,12 @@ struct clk_imx8_acm_sel {
* struct imx8_acm_soc_data - soc specific data
* @sels: pointer to struct clk_imx8_acm_sel
* @num_sels: numbers of items
* @mclk_sels: pointer to imx8qm/qxp/dxl_mclk_sels
*/
struct imx8_acm_soc_data {
struct clk_imx8_acm_sel *sels;
unsigned int num_sels;
struct clk_parent_data *mclk_sels;
};
/**
@ -111,11 +113,14 @@ static const struct clk_parent_data imx8qm_mclk_out_sels[] = {
{ .fw_name = "sai6_rx_bclk" },
};
static const struct clk_parent_data imx8qm_mclk_sels[] = {
#define ACM_AUD_CLK0_SEL_INDEX 2
#define ACM_AUD_CLK1_SEL_INDEX 3
static struct clk_parent_data imx8qm_mclk_sels[] = {
{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
{ .fw_name = "acm_aud_clk0_sel" },
{ .fw_name = "acm_aud_clk1_sel" },
{ }, /* clk_hw pointer of "acm_aud_clk0_sel" */
{ }, /* clk_hw pointer of "acm_aud_clk1_sel" */
};
static const struct clk_parent_data imx8qm_asrc_mux_clk_sels[] = {
@ -176,11 +181,11 @@ static const struct clk_parent_data imx8qxp_mclk_out_sels[] = {
{ .fw_name = "sai4_rx_bclk" },
};
static const struct clk_parent_data imx8qxp_mclk_sels[] = {
static struct clk_parent_data imx8qxp_mclk_sels[] = {
{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
{ .fw_name = "acm_aud_clk0_sel" },
{ .fw_name = "acm_aud_clk1_sel" },
{ }, /* clk_hw pointer of "acm_aud_clk0_sel" */
{ }, /* clk_hw pointer of "acm_aud_clk1_sel" */
};
static struct clk_imx8_acm_sel imx8qxp_sels[] = {
@ -228,11 +233,11 @@ static const struct clk_parent_data imx8dxl_mclk_out_sels[] = {
{ .index = -1 },
};
static const struct clk_parent_data imx8dxl_mclk_sels[] = {
static struct clk_parent_data imx8dxl_mclk_sels[] = {
{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
{ .fw_name = "acm_aud_clk0_sel" },
{ .fw_name = "acm_aud_clk1_sel" },
{ }, /* clk_hw pointer of "acm_aud_clk0_sel" */
{ }, /* clk_hw pointer of "acm_aud_clk1_sel" */
};
static struct clk_imx8_acm_sel imx8dxl_sels[] = {
@ -375,6 +380,18 @@ static int imx8_acm_clk_probe(struct platform_device *pdev)
imx_check_clk_hws(hws, IMX_ADMA_ACM_CLK_END);
goto err_clk_register;
}
/*
* The IMX_ADMA_ACM_AUD_CLK0_SEL and IMX_ADMA_ACM_AUD_CLK1_SEL are
* registered first. After registration, update the clk_hw pointer
* to imx8qm/qxp/dxl_mclk_sels structures.
*/
if (sels[i].clkid == IMX_ADMA_ACM_AUD_CLK0_SEL)
priv->soc_data->mclk_sels[ACM_AUD_CLK0_SEL_INDEX].hw =
hws[IMX_ADMA_ACM_AUD_CLK0_SEL];
if (sels[i].clkid == IMX_ADMA_ACM_AUD_CLK1_SEL)
priv->soc_data->mclk_sels[ACM_AUD_CLK1_SEL_INDEX].hw =
hws[IMX_ADMA_ACM_AUD_CLK1_SEL];
}
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data);
@ -406,16 +423,19 @@ static void imx8_acm_clk_remove(struct platform_device *pdev)
static const struct imx8_acm_soc_data imx8qm_acm_data = {
.sels = imx8qm_sels,
.num_sels = ARRAY_SIZE(imx8qm_sels),
.mclk_sels = imx8qm_mclk_sels,
};
static const struct imx8_acm_soc_data imx8qxp_acm_data = {
.sels = imx8qxp_sels,
.num_sels = ARRAY_SIZE(imx8qxp_sels),
.mclk_sels = imx8qxp_mclk_sels,
};
static const struct imx8_acm_soc_data imx8dxl_acm_data = {
.sels = imx8dxl_sels,
.num_sels = ARRAY_SIZE(imx8dxl_sels),
.mclk_sels = imx8dxl_mclk_sels,
};
static const struct of_device_id imx8_acm_match[] = {

30
drivers/clk/imx/clk-imx95-blk-ctl.c
View File

@ -248,6 +248,35 @@ static const struct imx95_blk_ctl_dev_data dispmix_csr_dev_data = {
.clk_reg_offset = 0,
};
static const struct imx95_blk_ctl_clk_dev_data netxmix_clk_dev_data[] = {
[IMX95_CLK_NETCMIX_ENETC0_RMII] = {
.name = "enetc0_rmii_sel",
.parent_names = (const char *[]){"ext_enetref", "enetref"},
.num_parents = 2,
.reg = 4,
.bit_idx = 5,
.bit_width = 1,
.type = CLK_MUX,
.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
},
[IMX95_CLK_NETCMIX_ENETC1_RMII] = {
.name = "enetc1_rmii_sel",
.parent_names = (const char *[]){"ext_enetref", "enetref"},
.num_parents = 2,
.reg = 4,
.bit_idx = 10,
.bit_width = 1,
.type = CLK_MUX,
.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
},
};
static const struct imx95_blk_ctl_dev_data netcmix_dev_data = {
.num_clks = ARRAY_SIZE(netxmix_clk_dev_data),
.clk_dev_data = netxmix_clk_dev_data,
.clk_reg_offset = 0,
};
static int imx95_bc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@ -419,6 +448,7 @@ static const struct of_device_id imx95_bc_of_match[] = {
{ .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
{ .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data },
{ .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
{ .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
{ /* Sentinel */ },
};
MODULE_DEVICE_TABLE(of, imx95_bc_of_match);

3
include/dt-bindings/clock/nxp,imx95-clock.h
View File

@ -25,4 +25,7 @@
#define IMX95_CLK_DISPMIX_ENG0_SEL 0
#define IMX95_CLK_DISPMIX_ENG1_SEL 1
#define IMX95_CLK_NETCMIX_ENETC0_RMII 0
#define IMX95_CLK_NETCMIX_ENETC1_RMII 1
#endif /* __DT_BINDINGS_CLOCK_IMX95_H */