github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-28 09:04:39 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/i915/display: Fix PHY_C20_VDR_HDMI_RATE programming

Browse Source 
The PHY_C20_VDR_HDMI_RATE registers 7:2 bits are reserved and they are
not specified as a must-be-zero field. Accordingly this reserved field
shouldn't be zeroed; to ensure that use an RMW to update the
PHY_C20_HDMI_RATE field (which is bits 1:0 of the register).

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20251015125446.3931198-7-mika.kahola@intel.com
This commit is contained in:
Imre Deak 2025-10-15 15:54:45 +03:00 committed by Mika Kahola
parent 4fd6053274
commit 938a3b2252
2 changed files with 6 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/drm/i915/display/intel_cx0_phy.c
View File

@ -2714,9 +2714,10 @@ static void intel_c20_pll_program(struct intel_display *display,
MB_WRITE_COMMITTED);
if (!is_dp)
intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
intel_c20_get_hdmi_rate(port_clock),
MB_WRITE_COMMITTED);
intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
PHY_C20_HDMI_RATE_MASK,
intel_c20_get_hdmi_rate(port_clock),
MB_WRITE_COMMITTED);
/*
* 7. Write Vendor specific registers to toggle context setting to load

2
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
View File

@ -304,6 +304,8 @@
#define PHY_C20_DP_RATE(val) REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)
#define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
#define PHY_C20_VDR_HDMI_RATE 0xD01
#define PHY_C20_HDMI_RATE_MASK REG_GENMASK8(1, 0)
#define PHY_C20_HDMI_RATE(val) REG_FIELD_PREP8(PHY_C20_HDMI_RATE_MASK, val)
#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
#define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
#define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)